1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs 5 * 6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. 7 * Copyright (c) 2006 ATI Technologies Inc. 8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved. 9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com> 10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> 11 * 12 * Authors: 13 * Wu Fengguang <wfg@linux.intel.com> 14 * 15 * Maintained by: 16 * Wu Fengguang <wfg@linux.intel.com> 17 */ 18 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/pci.h> 22 #include <linux/slab.h> 23 #include <linux/module.h> 24 #include <linux/pm_runtime.h> 25 #include <sound/core.h> 26 #include <sound/jack.h> 27 #include <sound/asoundef.h> 28 #include <sound/tlv.h> 29 #include <sound/hdaudio.h> 30 #include <sound/hda_i915.h> 31 #include <sound/hda_chmap.h> 32 #include <sound/hda_codec.h> 33 #include "hda_local.h" 34 #include "hda_jack.h" 35 #include "hda_controller.h" 36 37 static bool static_hdmi_pcm; 38 module_param(static_hdmi_pcm, bool, 0644); 39 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); 40 41 static bool enable_acomp = true; 42 module_param(enable_acomp, bool, 0444); 43 MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)"); 44 45 static bool enable_silent_stream = 46 IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM); 47 module_param(enable_silent_stream, bool, 0644); 48 MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices"); 49 50 struct hdmi_spec_per_cvt { 51 hda_nid_t cvt_nid; 52 int assigned; 53 unsigned int channels_min; 54 unsigned int channels_max; 55 u32 rates; 56 u64 formats; 57 unsigned int maxbps; 58 }; 59 60 /* max. connections to a widget */ 61 #define HDA_MAX_CONNECTIONS 32 62 63 struct hdmi_spec_per_pin { 64 hda_nid_t pin_nid; 65 int dev_id; 66 /* pin idx, different device entries on the same pin use the same idx */ 67 int pin_nid_idx; 68 int num_mux_nids; 69 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; 70 int mux_idx; 71 hda_nid_t cvt_nid; 72 73 struct hda_codec *codec; 74 struct hdmi_eld sink_eld; 75 struct mutex lock; 76 struct delayed_work work; 77 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ 78 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ 79 int repoll_count; 80 bool setup; /* the stream has been set up by prepare callback */ 81 int channels; /* current number of channels */ 82 bool non_pcm; 83 bool chmap_set; /* channel-map override by ALSA API? */ 84 unsigned char chmap[8]; /* ALSA API channel-map */ 85 #ifdef CONFIG_SND_PROC_FS 86 struct snd_info_entry *proc_entry; 87 #endif 88 }; 89 90 /* operations used by generic code that can be overridden by patches */ 91 struct hdmi_ops { 92 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, 93 int dev_id, unsigned char *buf, int *eld_size); 94 95 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, 96 int dev_id, 97 int ca, int active_channels, int conn_type); 98 99 /* enable/disable HBR (HD passthrough) */ 100 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, 101 int dev_id, bool hbr); 102 103 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, 104 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 105 int format); 106 107 void (*pin_cvt_fixup)(struct hda_codec *codec, 108 struct hdmi_spec_per_pin *per_pin, 109 hda_nid_t cvt_nid); 110 }; 111 112 struct hdmi_pcm { 113 struct hda_pcm *pcm; 114 struct snd_jack *jack; 115 struct snd_kcontrol *eld_ctl; 116 }; 117 118 struct hdmi_spec { 119 struct hda_codec *codec; 120 int num_cvts; 121 struct snd_array cvts; /* struct hdmi_spec_per_cvt */ 122 hda_nid_t cvt_nids[4]; /* only for haswell fix */ 123 124 /* 125 * num_pins is the number of virtual pins 126 * for example, there are 3 pins, and each pin 127 * has 4 device entries, then the num_pins is 12 128 */ 129 int num_pins; 130 /* 131 * num_nids is the number of real pins 132 * In the above example, num_nids is 3 133 */ 134 int num_nids; 135 /* 136 * dev_num is the number of device entries 137 * on each pin. 138 * In the above example, dev_num is 4 139 */ 140 int dev_num; 141 struct snd_array pins; /* struct hdmi_spec_per_pin */ 142 struct hdmi_pcm pcm_rec[16]; 143 struct mutex pcm_lock; 144 struct mutex bind_lock; /* for audio component binding */ 145 /* pcm_bitmap means which pcms have been assigned to pins*/ 146 unsigned long pcm_bitmap; 147 int pcm_used; /* counter of pcm_rec[] */ 148 /* bitmap shows whether the pcm is opened in user space 149 * bit 0 means the first playback PCM (PCM3); 150 * bit 1 means the second playback PCM, and so on. 151 */ 152 unsigned long pcm_in_use; 153 154 struct hdmi_eld temp_eld; 155 struct hdmi_ops ops; 156 157 bool dyn_pin_out; 158 bool dyn_pcm_assign; 159 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */ 160 /* 161 * Non-generic VIA/NVIDIA specific 162 */ 163 struct hda_multi_out multiout; 164 struct hda_pcm_stream pcm_playback; 165 166 bool use_acomp_notifier; /* use eld_notify callback for hotplug */ 167 bool acomp_registered; /* audio component registered in this driver */ 168 bool force_connect; /* force connectivity */ 169 struct drm_audio_component_audio_ops drm_audio_ops; 170 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */ 171 172 struct hdac_chmap chmap; 173 hda_nid_t vendor_nid; 174 const int *port_map; 175 int port_num; 176 bool send_silent_stream; /* Flag to enable silent stream feature */ 177 }; 178 179 #ifdef CONFIG_SND_HDA_COMPONENT 180 static inline bool codec_has_acomp(struct hda_codec *codec) 181 { 182 struct hdmi_spec *spec = codec->spec; 183 return spec->use_acomp_notifier; 184 } 185 #else 186 #define codec_has_acomp(codec) false 187 #endif 188 189 struct hdmi_audio_infoframe { 190 u8 type; /* 0x84 */ 191 u8 ver; /* 0x01 */ 192 u8 len; /* 0x0a */ 193 194 u8 checksum; 195 196 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ 197 u8 SS01_SF24; 198 u8 CXT04; 199 u8 CA; 200 u8 LFEPBL01_LSV36_DM_INH7; 201 }; 202 203 struct dp_audio_infoframe { 204 u8 type; /* 0x84 */ 205 u8 len; /* 0x1b */ 206 u8 ver; /* 0x11 << 2 */ 207 208 u8 CC02_CT47; /* match with HDMI infoframe from this on */ 209 u8 SS01_SF24; 210 u8 CXT04; 211 u8 CA; 212 u8 LFEPBL01_LSV36_DM_INH7; 213 }; 214 215 union audio_infoframe { 216 struct hdmi_audio_infoframe hdmi; 217 struct dp_audio_infoframe dp; 218 u8 bytes[0]; 219 }; 220 221 /* 222 * HDMI routines 223 */ 224 225 #define get_pin(spec, idx) \ 226 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) 227 #define get_cvt(spec, idx) \ 228 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) 229 /* obtain hdmi_pcm object assigned to idx */ 230 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) 231 /* obtain hda_pcm object assigned to idx */ 232 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) 233 234 static int pin_id_to_pin_index(struct hda_codec *codec, 235 hda_nid_t pin_nid, int dev_id) 236 { 237 struct hdmi_spec *spec = codec->spec; 238 int pin_idx; 239 struct hdmi_spec_per_pin *per_pin; 240 241 /* 242 * (dev_id == -1) means it is NON-MST pin 243 * return the first virtual pin on this port 244 */ 245 if (dev_id == -1) 246 dev_id = 0; 247 248 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 249 per_pin = get_pin(spec, pin_idx); 250 if ((per_pin->pin_nid == pin_nid) && 251 (per_pin->dev_id == dev_id)) 252 return pin_idx; 253 } 254 255 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid); 256 return -EINVAL; 257 } 258 259 static int hinfo_to_pcm_index(struct hda_codec *codec, 260 struct hda_pcm_stream *hinfo) 261 { 262 struct hdmi_spec *spec = codec->spec; 263 int pcm_idx; 264 265 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) 266 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) 267 return pcm_idx; 268 269 codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo); 270 return -EINVAL; 271 } 272 273 static int hinfo_to_pin_index(struct hda_codec *codec, 274 struct hda_pcm_stream *hinfo) 275 { 276 struct hdmi_spec *spec = codec->spec; 277 struct hdmi_spec_per_pin *per_pin; 278 int pin_idx; 279 280 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 281 per_pin = get_pin(spec, pin_idx); 282 if (per_pin->pcm && 283 per_pin->pcm->pcm->stream == hinfo) 284 return pin_idx; 285 } 286 287 codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo, 288 hinfo_to_pcm_index(codec, hinfo)); 289 return -EINVAL; 290 } 291 292 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, 293 int pcm_idx) 294 { 295 int i; 296 struct hdmi_spec_per_pin *per_pin; 297 298 for (i = 0; i < spec->num_pins; i++) { 299 per_pin = get_pin(spec, i); 300 if (per_pin->pcm_idx == pcm_idx) 301 return per_pin; 302 } 303 return NULL; 304 } 305 306 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) 307 { 308 struct hdmi_spec *spec = codec->spec; 309 int cvt_idx; 310 311 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) 312 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) 313 return cvt_idx; 314 315 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid); 316 return -EINVAL; 317 } 318 319 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, 320 struct snd_ctl_elem_info *uinfo) 321 { 322 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 323 struct hdmi_spec *spec = codec->spec; 324 struct hdmi_spec_per_pin *per_pin; 325 struct hdmi_eld *eld; 326 int pcm_idx; 327 328 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 329 330 pcm_idx = kcontrol->private_value; 331 mutex_lock(&spec->pcm_lock); 332 per_pin = pcm_idx_to_pin(spec, pcm_idx); 333 if (!per_pin) { 334 /* no pin is bound to the pcm */ 335 uinfo->count = 0; 336 goto unlock; 337 } 338 eld = &per_pin->sink_eld; 339 uinfo->count = eld->eld_valid ? eld->eld_size : 0; 340 341 unlock: 342 mutex_unlock(&spec->pcm_lock); 343 return 0; 344 } 345 346 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, 347 struct snd_ctl_elem_value *ucontrol) 348 { 349 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 350 struct hdmi_spec *spec = codec->spec; 351 struct hdmi_spec_per_pin *per_pin; 352 struct hdmi_eld *eld; 353 int pcm_idx; 354 int err = 0; 355 356 pcm_idx = kcontrol->private_value; 357 mutex_lock(&spec->pcm_lock); 358 per_pin = pcm_idx_to_pin(spec, pcm_idx); 359 if (!per_pin) { 360 /* no pin is bound to the pcm */ 361 memset(ucontrol->value.bytes.data, 0, 362 ARRAY_SIZE(ucontrol->value.bytes.data)); 363 goto unlock; 364 } 365 366 eld = &per_pin->sink_eld; 367 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || 368 eld->eld_size > ELD_MAX_SIZE) { 369 snd_BUG(); 370 err = -EINVAL; 371 goto unlock; 372 } 373 374 memset(ucontrol->value.bytes.data, 0, 375 ARRAY_SIZE(ucontrol->value.bytes.data)); 376 if (eld->eld_valid) 377 memcpy(ucontrol->value.bytes.data, eld->eld_buffer, 378 eld->eld_size); 379 380 unlock: 381 mutex_unlock(&spec->pcm_lock); 382 return err; 383 } 384 385 static const struct snd_kcontrol_new eld_bytes_ctl = { 386 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE | 387 SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK, 388 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 389 .name = "ELD", 390 .info = hdmi_eld_ctl_info, 391 .get = hdmi_eld_ctl_get, 392 }; 393 394 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, 395 int device) 396 { 397 struct snd_kcontrol *kctl; 398 struct hdmi_spec *spec = codec->spec; 399 int err; 400 401 kctl = snd_ctl_new1(&eld_bytes_ctl, codec); 402 if (!kctl) 403 return -ENOMEM; 404 kctl->private_value = pcm_idx; 405 kctl->id.device = device; 406 407 /* no pin nid is associated with the kctl now 408 * tbd: associate pin nid to eld ctl later 409 */ 410 err = snd_hda_ctl_add(codec, 0, kctl); 411 if (err < 0) 412 return err; 413 414 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; 415 return 0; 416 } 417 418 #ifdef BE_PARANOID 419 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 420 int *packet_index, int *byte_index) 421 { 422 int val; 423 424 val = snd_hda_codec_read(codec, pin_nid, 0, 425 AC_VERB_GET_HDMI_DIP_INDEX, 0); 426 427 *packet_index = val >> 5; 428 *byte_index = val & 0x1f; 429 } 430 #endif 431 432 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 433 int packet_index, int byte_index) 434 { 435 int val; 436 437 val = (packet_index << 5) | (byte_index & 0x1f); 438 439 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); 440 } 441 442 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, 443 unsigned char val) 444 { 445 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); 446 } 447 448 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) 449 { 450 struct hdmi_spec *spec = codec->spec; 451 int pin_out; 452 453 /* Unmute */ 454 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 455 snd_hda_codec_write(codec, pin_nid, 0, 456 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); 457 458 if (spec->dyn_pin_out) 459 /* Disable pin out until stream is active */ 460 pin_out = 0; 461 else 462 /* Enable pin out: some machines with GM965 gets broken output 463 * when the pin is disabled or changed while using with HDMI 464 */ 465 pin_out = PIN_OUT; 466 467 snd_hda_codec_write(codec, pin_nid, 0, 468 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); 469 } 470 471 /* 472 * ELD proc files 473 */ 474 475 #ifdef CONFIG_SND_PROC_FS 476 static void print_eld_info(struct snd_info_entry *entry, 477 struct snd_info_buffer *buffer) 478 { 479 struct hdmi_spec_per_pin *per_pin = entry->private_data; 480 481 mutex_lock(&per_pin->lock); 482 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer); 483 mutex_unlock(&per_pin->lock); 484 } 485 486 static void write_eld_info(struct snd_info_entry *entry, 487 struct snd_info_buffer *buffer) 488 { 489 struct hdmi_spec_per_pin *per_pin = entry->private_data; 490 491 mutex_lock(&per_pin->lock); 492 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); 493 mutex_unlock(&per_pin->lock); 494 } 495 496 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) 497 { 498 char name[32]; 499 struct hda_codec *codec = per_pin->codec; 500 struct snd_info_entry *entry; 501 int err; 502 503 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); 504 err = snd_card_proc_new(codec->card, name, &entry); 505 if (err < 0) 506 return err; 507 508 snd_info_set_text_ops(entry, per_pin, print_eld_info); 509 entry->c.text.write = write_eld_info; 510 entry->mode |= 0200; 511 per_pin->proc_entry = entry; 512 513 return 0; 514 } 515 516 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 517 { 518 if (!per_pin->codec->bus->shutdown) { 519 snd_info_free_entry(per_pin->proc_entry); 520 per_pin->proc_entry = NULL; 521 } 522 } 523 #else 524 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, 525 int index) 526 { 527 return 0; 528 } 529 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 530 { 531 } 532 #endif 533 534 /* 535 * Audio InfoFrame routines 536 */ 537 538 /* 539 * Enable Audio InfoFrame Transmission 540 */ 541 static void hdmi_start_infoframe_trans(struct hda_codec *codec, 542 hda_nid_t pin_nid) 543 { 544 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 545 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 546 AC_DIPXMIT_BEST); 547 } 548 549 /* 550 * Disable Audio InfoFrame Transmission 551 */ 552 static void hdmi_stop_infoframe_trans(struct hda_codec *codec, 553 hda_nid_t pin_nid) 554 { 555 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 556 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 557 AC_DIPXMIT_DISABLE); 558 } 559 560 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) 561 { 562 #ifdef CONFIG_SND_DEBUG_VERBOSE 563 int i; 564 int size; 565 566 size = snd_hdmi_get_eld_size(codec, pin_nid); 567 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); 568 569 for (i = 0; i < 8; i++) { 570 size = snd_hda_codec_read(codec, pin_nid, 0, 571 AC_VERB_GET_HDMI_DIP_SIZE, i); 572 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); 573 } 574 #endif 575 } 576 577 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) 578 { 579 #ifdef BE_PARANOID 580 int i, j; 581 int size; 582 int pi, bi; 583 for (i = 0; i < 8; i++) { 584 size = snd_hda_codec_read(codec, pin_nid, 0, 585 AC_VERB_GET_HDMI_DIP_SIZE, i); 586 if (size == 0) 587 continue; 588 589 hdmi_set_dip_index(codec, pin_nid, i, 0x0); 590 for (j = 1; j < 1000; j++) { 591 hdmi_write_dip_byte(codec, pin_nid, 0x0); 592 hdmi_get_dip_index(codec, pin_nid, &pi, &bi); 593 if (pi != i) 594 codec_dbg(codec, "dip index %d: %d != %d\n", 595 bi, pi, i); 596 if (bi == 0) /* byte index wrapped around */ 597 break; 598 } 599 codec_dbg(codec, 600 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", 601 i, size, j); 602 } 603 #endif 604 } 605 606 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) 607 { 608 u8 *bytes = (u8 *)hdmi_ai; 609 u8 sum = 0; 610 int i; 611 612 hdmi_ai->checksum = 0; 613 614 for (i = 0; i < sizeof(*hdmi_ai); i++) 615 sum += bytes[i]; 616 617 hdmi_ai->checksum = -sum; 618 } 619 620 static void hdmi_fill_audio_infoframe(struct hda_codec *codec, 621 hda_nid_t pin_nid, 622 u8 *dip, int size) 623 { 624 int i; 625 626 hdmi_debug_dip_size(codec, pin_nid); 627 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ 628 629 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 630 for (i = 0; i < size; i++) 631 hdmi_write_dip_byte(codec, pin_nid, dip[i]); 632 } 633 634 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, 635 u8 *dip, int size) 636 { 637 u8 val; 638 int i; 639 640 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) 641 != AC_DIPXMIT_BEST) 642 return false; 643 644 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 645 for (i = 0; i < size; i++) { 646 val = snd_hda_codec_read(codec, pin_nid, 0, 647 AC_VERB_GET_HDMI_DIP_DATA, 0); 648 if (val != dip[i]) 649 return false; 650 } 651 652 return true; 653 } 654 655 static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 656 int dev_id, unsigned char *buf, int *eld_size) 657 { 658 snd_hda_set_dev_select(codec, nid, dev_id); 659 660 return snd_hdmi_get_eld(codec, nid, buf, eld_size); 661 } 662 663 static void hdmi_pin_setup_infoframe(struct hda_codec *codec, 664 hda_nid_t pin_nid, int dev_id, 665 int ca, int active_channels, 666 int conn_type) 667 { 668 union audio_infoframe ai; 669 670 memset(&ai, 0, sizeof(ai)); 671 if (conn_type == 0) { /* HDMI */ 672 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; 673 674 hdmi_ai->type = 0x84; 675 hdmi_ai->ver = 0x01; 676 hdmi_ai->len = 0x0a; 677 hdmi_ai->CC02_CT47 = active_channels - 1; 678 hdmi_ai->CA = ca; 679 hdmi_checksum_audio_infoframe(hdmi_ai); 680 } else if (conn_type == 1) { /* DisplayPort */ 681 struct dp_audio_infoframe *dp_ai = &ai.dp; 682 683 dp_ai->type = 0x84; 684 dp_ai->len = 0x1b; 685 dp_ai->ver = 0x11 << 2; 686 dp_ai->CC02_CT47 = active_channels - 1; 687 dp_ai->CA = ca; 688 } else { 689 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n", 690 pin_nid); 691 return; 692 } 693 694 snd_hda_set_dev_select(codec, pin_nid, dev_id); 695 696 /* 697 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or 698 * sizeof(*dp_ai) to avoid partial match/update problems when 699 * the user switches between HDMI/DP monitors. 700 */ 701 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, 702 sizeof(ai))) { 703 codec_dbg(codec, 704 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n", 705 pin_nid, 706 active_channels, ca); 707 hdmi_stop_infoframe_trans(codec, pin_nid); 708 hdmi_fill_audio_infoframe(codec, pin_nid, 709 ai.bytes, sizeof(ai)); 710 hdmi_start_infoframe_trans(codec, pin_nid); 711 } 712 } 713 714 static void hdmi_setup_audio_infoframe(struct hda_codec *codec, 715 struct hdmi_spec_per_pin *per_pin, 716 bool non_pcm) 717 { 718 struct hdmi_spec *spec = codec->spec; 719 struct hdac_chmap *chmap = &spec->chmap; 720 hda_nid_t pin_nid = per_pin->pin_nid; 721 int dev_id = per_pin->dev_id; 722 int channels = per_pin->channels; 723 int active_channels; 724 struct hdmi_eld *eld; 725 int ca; 726 727 if (!channels) 728 return; 729 730 snd_hda_set_dev_select(codec, pin_nid, dev_id); 731 732 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ 733 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 734 snd_hda_codec_write(codec, pin_nid, 0, 735 AC_VERB_SET_AMP_GAIN_MUTE, 736 AMP_OUT_UNMUTE); 737 738 eld = &per_pin->sink_eld; 739 740 ca = snd_hdac_channel_allocation(&codec->core, 741 eld->info.spk_alloc, channels, 742 per_pin->chmap_set, non_pcm, per_pin->chmap); 743 744 active_channels = snd_hdac_get_active_channels(ca); 745 746 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, 747 active_channels); 748 749 /* 750 * always configure channel mapping, it may have been changed by the 751 * user in the meantime 752 */ 753 snd_hdac_setup_channel_mapping(&spec->chmap, 754 pin_nid, non_pcm, ca, channels, 755 per_pin->chmap, per_pin->chmap_set); 756 757 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id, 758 ca, active_channels, eld->info.conn_type); 759 760 per_pin->non_pcm = non_pcm; 761 } 762 763 /* 764 * Unsolicited events 765 */ 766 767 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); 768 769 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, 770 int dev_id) 771 { 772 struct hdmi_spec *spec = codec->spec; 773 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); 774 775 if (pin_idx < 0) 776 return; 777 mutex_lock(&spec->pcm_lock); 778 hdmi_present_sense(get_pin(spec, pin_idx), 1); 779 mutex_unlock(&spec->pcm_lock); 780 } 781 782 static void jack_callback(struct hda_codec *codec, 783 struct hda_jack_callback *jack) 784 { 785 /* stop polling when notification is enabled */ 786 if (codec_has_acomp(codec)) 787 return; 788 789 check_presence_and_report(codec, jack->nid, jack->dev_id); 790 } 791 792 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res, 793 struct hda_jack_tbl *jack) 794 { 795 jack->jack_dirty = 1; 796 797 codec_dbg(codec, 798 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", 799 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA), 800 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); 801 802 check_presence_and_report(codec, jack->nid, jack->dev_id); 803 } 804 805 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) 806 { 807 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 808 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 809 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); 810 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); 811 812 codec_info(codec, 813 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", 814 codec->addr, 815 tag, 816 subtag, 817 cp_state, 818 cp_ready); 819 820 /* TODO */ 821 if (cp_state) { 822 ; 823 } 824 if (cp_ready) { 825 ; 826 } 827 } 828 829 830 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) 831 { 832 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 833 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 834 struct hda_jack_tbl *jack; 835 836 if (codec_has_acomp(codec)) 837 return; 838 839 if (codec->dp_mst) { 840 int dev_entry = 841 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 842 843 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry); 844 } else { 845 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0); 846 } 847 848 if (!jack) { 849 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); 850 return; 851 } 852 853 if (subtag == 0) 854 hdmi_intrinsic_event(codec, res, jack); 855 else 856 hdmi_non_intrinsic_event(codec, res); 857 } 858 859 static void haswell_verify_D0(struct hda_codec *codec, 860 hda_nid_t cvt_nid, hda_nid_t nid) 861 { 862 int pwr; 863 864 /* For Haswell, the converter 1/2 may keep in D3 state after bootup, 865 * thus pins could only choose converter 0 for use. Make sure the 866 * converters are in correct power state */ 867 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) 868 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); 869 870 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { 871 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, 872 AC_PWRST_D0); 873 msleep(40); 874 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); 875 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; 876 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr); 877 } 878 } 879 880 /* 881 * Callbacks 882 */ 883 884 /* HBR should be Non-PCM, 8 channels */ 885 #define is_hbr_format(format) \ 886 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) 887 888 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 889 int dev_id, bool hbr) 890 { 891 int pinctl, new_pinctl; 892 893 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { 894 snd_hda_set_dev_select(codec, pin_nid, dev_id); 895 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 896 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 897 898 if (pinctl < 0) 899 return hbr ? -EINVAL : 0; 900 901 new_pinctl = pinctl & ~AC_PINCTL_EPT; 902 if (hbr) 903 new_pinctl |= AC_PINCTL_EPT_HBR; 904 else 905 new_pinctl |= AC_PINCTL_EPT_NATIVE; 906 907 codec_dbg(codec, 908 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", 909 pin_nid, 910 pinctl == new_pinctl ? "" : "new-", 911 new_pinctl); 912 913 if (pinctl != new_pinctl) 914 snd_hda_codec_write(codec, pin_nid, 0, 915 AC_VERB_SET_PIN_WIDGET_CONTROL, 916 new_pinctl); 917 } else if (hbr) 918 return -EINVAL; 919 920 return 0; 921 } 922 923 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 924 hda_nid_t pin_nid, int dev_id, 925 u32 stream_tag, int format) 926 { 927 struct hdmi_spec *spec = codec->spec; 928 unsigned int param; 929 int err; 930 931 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id, 932 is_hbr_format(format)); 933 934 if (err) { 935 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); 936 return err; 937 } 938 939 if (spec->intel_hsw_fixup) { 940 941 /* 942 * on recent platforms IEC Coding Type is required for HBR 943 * support, read current Digital Converter settings and set 944 * ICT bitfield if needed. 945 */ 946 param = snd_hda_codec_read(codec, cvt_nid, 0, 947 AC_VERB_GET_DIGI_CONVERT_1, 0); 948 949 param = (param >> 16) & ~(AC_DIG3_ICT); 950 951 /* on recent platforms ICT mode is required for HBR support */ 952 if (is_hbr_format(format)) 953 param |= 0x1; 954 955 snd_hda_codec_write(codec, cvt_nid, 0, 956 AC_VERB_SET_DIGI_CONVERT_3, param); 957 } 958 959 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); 960 return 0; 961 } 962 963 /* Try to find an available converter 964 * If pin_idx is less then zero, just try to find an available converter. 965 * Otherwise, try to find an available converter and get the cvt mux index 966 * of the pin. 967 */ 968 static int hdmi_choose_cvt(struct hda_codec *codec, 969 int pin_idx, int *cvt_id) 970 { 971 struct hdmi_spec *spec = codec->spec; 972 struct hdmi_spec_per_pin *per_pin; 973 struct hdmi_spec_per_cvt *per_cvt = NULL; 974 int cvt_idx, mux_idx = 0; 975 976 /* pin_idx < 0 means no pin will be bound to the converter */ 977 if (pin_idx < 0) 978 per_pin = NULL; 979 else 980 per_pin = get_pin(spec, pin_idx); 981 982 /* Dynamically assign converter to stream */ 983 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 984 per_cvt = get_cvt(spec, cvt_idx); 985 986 /* Must not already be assigned */ 987 if (per_cvt->assigned) 988 continue; 989 if (per_pin == NULL) 990 break; 991 /* Must be in pin's mux's list of converters */ 992 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 993 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) 994 break; 995 /* Not in mux list */ 996 if (mux_idx == per_pin->num_mux_nids) 997 continue; 998 break; 999 } 1000 1001 /* No free converters */ 1002 if (cvt_idx == spec->num_cvts) 1003 return -EBUSY; 1004 1005 if (per_pin != NULL) 1006 per_pin->mux_idx = mux_idx; 1007 1008 if (cvt_id) 1009 *cvt_id = cvt_idx; 1010 1011 return 0; 1012 } 1013 1014 /* Assure the pin select the right convetor */ 1015 static void intel_verify_pin_cvt_connect(struct hda_codec *codec, 1016 struct hdmi_spec_per_pin *per_pin) 1017 { 1018 hda_nid_t pin_nid = per_pin->pin_nid; 1019 int mux_idx, curr; 1020 1021 mux_idx = per_pin->mux_idx; 1022 curr = snd_hda_codec_read(codec, pin_nid, 0, 1023 AC_VERB_GET_CONNECT_SEL, 0); 1024 if (curr != mux_idx) 1025 snd_hda_codec_write_cache(codec, pin_nid, 0, 1026 AC_VERB_SET_CONNECT_SEL, 1027 mux_idx); 1028 } 1029 1030 /* get the mux index for the converter of the pins 1031 * converter's mux index is the same for all pins on Intel platform 1032 */ 1033 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, 1034 hda_nid_t cvt_nid) 1035 { 1036 int i; 1037 1038 for (i = 0; i < spec->num_cvts; i++) 1039 if (spec->cvt_nids[i] == cvt_nid) 1040 return i; 1041 return -EINVAL; 1042 } 1043 1044 /* Intel HDMI workaround to fix audio routing issue: 1045 * For some Intel display codecs, pins share the same connection list. 1046 * So a conveter can be selected by multiple pins and playback on any of these 1047 * pins will generate sound on the external display, because audio flows from 1048 * the same converter to the display pipeline. Also muting one pin may make 1049 * other pins have no sound output. 1050 * So this function assures that an assigned converter for a pin is not selected 1051 * by any other pins. 1052 */ 1053 static void intel_not_share_assigned_cvt(struct hda_codec *codec, 1054 hda_nid_t pin_nid, 1055 int dev_id, int mux_idx) 1056 { 1057 struct hdmi_spec *spec = codec->spec; 1058 hda_nid_t nid; 1059 int cvt_idx, curr; 1060 struct hdmi_spec_per_cvt *per_cvt; 1061 struct hdmi_spec_per_pin *per_pin; 1062 int pin_idx; 1063 1064 /* configure the pins connections */ 1065 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 1066 int dev_id_saved; 1067 int dev_num; 1068 1069 per_pin = get_pin(spec, pin_idx); 1070 /* 1071 * pin not connected to monitor 1072 * no need to operate on it 1073 */ 1074 if (!per_pin->pcm) 1075 continue; 1076 1077 if ((per_pin->pin_nid == pin_nid) && 1078 (per_pin->dev_id == dev_id)) 1079 continue; 1080 1081 /* 1082 * if per_pin->dev_id >= dev_num, 1083 * snd_hda_get_dev_select() will fail, 1084 * and the following operation is unpredictable. 1085 * So skip this situation. 1086 */ 1087 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; 1088 if (per_pin->dev_id >= dev_num) 1089 continue; 1090 1091 nid = per_pin->pin_nid; 1092 1093 /* 1094 * Calling this function should not impact 1095 * on the device entry selection 1096 * So let's save the dev id for each pin, 1097 * and restore it when return 1098 */ 1099 dev_id_saved = snd_hda_get_dev_select(codec, nid); 1100 snd_hda_set_dev_select(codec, nid, per_pin->dev_id); 1101 curr = snd_hda_codec_read(codec, nid, 0, 1102 AC_VERB_GET_CONNECT_SEL, 0); 1103 if (curr != mux_idx) { 1104 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1105 continue; 1106 } 1107 1108 1109 /* choose an unassigned converter. The conveters in the 1110 * connection list are in the same order as in the codec. 1111 */ 1112 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1113 per_cvt = get_cvt(spec, cvt_idx); 1114 if (!per_cvt->assigned) { 1115 codec_dbg(codec, 1116 "choose cvt %d for pin nid %d\n", 1117 cvt_idx, nid); 1118 snd_hda_codec_write_cache(codec, nid, 0, 1119 AC_VERB_SET_CONNECT_SEL, 1120 cvt_idx); 1121 break; 1122 } 1123 } 1124 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1125 } 1126 } 1127 1128 /* A wrapper of intel_not_share_asigned_cvt() */ 1129 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, 1130 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) 1131 { 1132 int mux_idx; 1133 struct hdmi_spec *spec = codec->spec; 1134 1135 /* On Intel platform, the mapping of converter nid to 1136 * mux index of the pins are always the same. 1137 * The pin nid may be 0, this means all pins will not 1138 * share the converter. 1139 */ 1140 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); 1141 if (mux_idx >= 0) 1142 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); 1143 } 1144 1145 /* skeleton caller of pin_cvt_fixup ops */ 1146 static void pin_cvt_fixup(struct hda_codec *codec, 1147 struct hdmi_spec_per_pin *per_pin, 1148 hda_nid_t cvt_nid) 1149 { 1150 struct hdmi_spec *spec = codec->spec; 1151 1152 if (spec->ops.pin_cvt_fixup) 1153 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); 1154 } 1155 1156 /* called in hdmi_pcm_open when no pin is assigned to the PCM 1157 * in dyn_pcm_assign mode. 1158 */ 1159 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, 1160 struct hda_codec *codec, 1161 struct snd_pcm_substream *substream) 1162 { 1163 struct hdmi_spec *spec = codec->spec; 1164 struct snd_pcm_runtime *runtime = substream->runtime; 1165 int cvt_idx, pcm_idx; 1166 struct hdmi_spec_per_cvt *per_cvt = NULL; 1167 int err; 1168 1169 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1170 if (pcm_idx < 0) 1171 return -EINVAL; 1172 1173 err = hdmi_choose_cvt(codec, -1, &cvt_idx); 1174 if (err) 1175 return err; 1176 1177 per_cvt = get_cvt(spec, cvt_idx); 1178 per_cvt->assigned = 1; 1179 hinfo->nid = per_cvt->cvt_nid; 1180 1181 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); 1182 1183 set_bit(pcm_idx, &spec->pcm_in_use); 1184 /* todo: setup spdif ctls assign */ 1185 1186 /* Initially set the converter's capabilities */ 1187 hinfo->channels_min = per_cvt->channels_min; 1188 hinfo->channels_max = per_cvt->channels_max; 1189 hinfo->rates = per_cvt->rates; 1190 hinfo->formats = per_cvt->formats; 1191 hinfo->maxbps = per_cvt->maxbps; 1192 1193 /* Store the updated parameters */ 1194 runtime->hw.channels_min = hinfo->channels_min; 1195 runtime->hw.channels_max = hinfo->channels_max; 1196 runtime->hw.formats = hinfo->formats; 1197 runtime->hw.rates = hinfo->rates; 1198 1199 snd_pcm_hw_constraint_step(substream->runtime, 0, 1200 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1201 return 0; 1202 } 1203 1204 /* 1205 * HDA PCM callbacks 1206 */ 1207 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, 1208 struct hda_codec *codec, 1209 struct snd_pcm_substream *substream) 1210 { 1211 struct hdmi_spec *spec = codec->spec; 1212 struct snd_pcm_runtime *runtime = substream->runtime; 1213 int pin_idx, cvt_idx, pcm_idx; 1214 struct hdmi_spec_per_pin *per_pin; 1215 struct hdmi_eld *eld; 1216 struct hdmi_spec_per_cvt *per_cvt = NULL; 1217 int err; 1218 1219 /* Validate hinfo */ 1220 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1221 if (pcm_idx < 0) 1222 return -EINVAL; 1223 1224 mutex_lock(&spec->pcm_lock); 1225 pin_idx = hinfo_to_pin_index(codec, hinfo); 1226 if (!spec->dyn_pcm_assign) { 1227 if (snd_BUG_ON(pin_idx < 0)) { 1228 err = -EINVAL; 1229 goto unlock; 1230 } 1231 } else { 1232 /* no pin is assigned to the PCM 1233 * PA need pcm open successfully when probe 1234 */ 1235 if (pin_idx < 0) { 1236 err = hdmi_pcm_open_no_pin(hinfo, codec, substream); 1237 goto unlock; 1238 } 1239 } 1240 1241 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx); 1242 if (err < 0) 1243 goto unlock; 1244 1245 per_cvt = get_cvt(spec, cvt_idx); 1246 /* Claim converter */ 1247 per_cvt->assigned = 1; 1248 1249 set_bit(pcm_idx, &spec->pcm_in_use); 1250 per_pin = get_pin(spec, pin_idx); 1251 per_pin->cvt_nid = per_cvt->cvt_nid; 1252 hinfo->nid = per_cvt->cvt_nid; 1253 1254 /* flip stripe flag for the assigned stream if supported */ 1255 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE) 1256 azx_stream(get_azx_dev(substream))->stripe = 1; 1257 1258 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1259 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1260 AC_VERB_SET_CONNECT_SEL, 1261 per_pin->mux_idx); 1262 1263 /* configure unused pins to choose other converters */ 1264 pin_cvt_fixup(codec, per_pin, 0); 1265 1266 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); 1267 1268 /* Initially set the converter's capabilities */ 1269 hinfo->channels_min = per_cvt->channels_min; 1270 hinfo->channels_max = per_cvt->channels_max; 1271 hinfo->rates = per_cvt->rates; 1272 hinfo->formats = per_cvt->formats; 1273 hinfo->maxbps = per_cvt->maxbps; 1274 1275 eld = &per_pin->sink_eld; 1276 /* Restrict capabilities by ELD if this isn't disabled */ 1277 if (!static_hdmi_pcm && eld->eld_valid) { 1278 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); 1279 if (hinfo->channels_min > hinfo->channels_max || 1280 !hinfo->rates || !hinfo->formats) { 1281 per_cvt->assigned = 0; 1282 hinfo->nid = 0; 1283 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1284 err = -ENODEV; 1285 goto unlock; 1286 } 1287 } 1288 1289 /* Store the updated parameters */ 1290 runtime->hw.channels_min = hinfo->channels_min; 1291 runtime->hw.channels_max = hinfo->channels_max; 1292 runtime->hw.formats = hinfo->formats; 1293 runtime->hw.rates = hinfo->rates; 1294 1295 snd_pcm_hw_constraint_step(substream->runtime, 0, 1296 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1297 unlock: 1298 mutex_unlock(&spec->pcm_lock); 1299 return err; 1300 } 1301 1302 /* 1303 * HDA/HDMI auto parsing 1304 */ 1305 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) 1306 { 1307 struct hdmi_spec *spec = codec->spec; 1308 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1309 hda_nid_t pin_nid = per_pin->pin_nid; 1310 int dev_id = per_pin->dev_id; 1311 int conns; 1312 1313 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { 1314 codec_warn(codec, 1315 "HDMI: pin %d wcaps %#x does not support connection list\n", 1316 pin_nid, get_wcaps(codec, pin_nid)); 1317 return -EINVAL; 1318 } 1319 1320 snd_hda_set_dev_select(codec, pin_nid, dev_id); 1321 1322 if (spec->intel_hsw_fixup) { 1323 conns = spec->num_cvts; 1324 memcpy(per_pin->mux_nids, spec->cvt_nids, 1325 sizeof(hda_nid_t) * conns); 1326 } else { 1327 conns = snd_hda_get_raw_connections(codec, pin_nid, 1328 per_pin->mux_nids, 1329 HDA_MAX_CONNECTIONS); 1330 } 1331 1332 /* all the device entries on the same pin have the same conn list */ 1333 per_pin->num_mux_nids = conns; 1334 1335 return 0; 1336 } 1337 1338 static int hdmi_find_pcm_slot(struct hdmi_spec *spec, 1339 struct hdmi_spec_per_pin *per_pin) 1340 { 1341 int i; 1342 1343 /* 1344 * generic_hdmi_build_pcms() may allocate extra PCMs on some 1345 * platforms (with maximum of 'num_nids + dev_num - 1') 1346 * 1347 * The per_pin of pin_nid_idx=n and dev_id=m prefers to get pcm-n 1348 * if m==0. This guarantees that dynamic pcm assignments are compatible 1349 * with the legacy static per_pin-pcm assignment that existed in the 1350 * days before DP-MST. 1351 * 1352 * Intel DP-MST prefers this legacy behavior for compatibility, too. 1353 * 1354 * per_pin of m!=0 prefers to get pcm=(num_nids + (m - 1)). 1355 */ 1356 1357 if (per_pin->dev_id == 0 || spec->intel_hsw_fixup) { 1358 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap)) 1359 return per_pin->pin_nid_idx; 1360 } else { 1361 i = spec->num_nids + (per_pin->dev_id - 1); 1362 if (i < spec->pcm_used && !(test_bit(i, &spec->pcm_bitmap))) 1363 return i; 1364 } 1365 1366 /* have a second try; check the area over num_nids */ 1367 for (i = spec->num_nids; i < spec->pcm_used; i++) { 1368 if (!test_bit(i, &spec->pcm_bitmap)) 1369 return i; 1370 } 1371 1372 /* the last try; check the empty slots in pins */ 1373 for (i = 0; i < spec->num_nids; i++) { 1374 if (!test_bit(i, &spec->pcm_bitmap)) 1375 return i; 1376 } 1377 return -EBUSY; 1378 } 1379 1380 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, 1381 struct hdmi_spec_per_pin *per_pin) 1382 { 1383 int idx; 1384 1385 /* pcm already be attached to the pin */ 1386 if (per_pin->pcm) 1387 return; 1388 idx = hdmi_find_pcm_slot(spec, per_pin); 1389 if (idx == -EBUSY) 1390 return; 1391 per_pin->pcm_idx = idx; 1392 per_pin->pcm = get_hdmi_pcm(spec, idx); 1393 set_bit(idx, &spec->pcm_bitmap); 1394 } 1395 1396 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, 1397 struct hdmi_spec_per_pin *per_pin) 1398 { 1399 int idx; 1400 1401 /* pcm already be detached from the pin */ 1402 if (!per_pin->pcm) 1403 return; 1404 idx = per_pin->pcm_idx; 1405 per_pin->pcm_idx = -1; 1406 per_pin->pcm = NULL; 1407 if (idx >= 0 && idx < spec->pcm_used) 1408 clear_bit(idx, &spec->pcm_bitmap); 1409 } 1410 1411 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, 1412 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) 1413 { 1414 int mux_idx; 1415 1416 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1417 if (per_pin->mux_nids[mux_idx] == cvt_nid) 1418 break; 1419 return mux_idx; 1420 } 1421 1422 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); 1423 1424 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, 1425 struct hdmi_spec_per_pin *per_pin) 1426 { 1427 struct hda_codec *codec = per_pin->codec; 1428 struct hda_pcm *pcm; 1429 struct hda_pcm_stream *hinfo; 1430 struct snd_pcm_substream *substream; 1431 int mux_idx; 1432 bool non_pcm; 1433 1434 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1435 pcm = get_pcm_rec(spec, per_pin->pcm_idx); 1436 else 1437 return; 1438 if (!pcm->pcm) 1439 return; 1440 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) 1441 return; 1442 1443 /* hdmi audio only uses playback and one substream */ 1444 hinfo = pcm->stream; 1445 substream = pcm->pcm->streams[0].substream; 1446 1447 per_pin->cvt_nid = hinfo->nid; 1448 1449 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); 1450 if (mux_idx < per_pin->num_mux_nids) { 1451 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1452 per_pin->dev_id); 1453 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1454 AC_VERB_SET_CONNECT_SEL, 1455 mux_idx); 1456 } 1457 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); 1458 1459 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); 1460 if (substream->runtime) 1461 per_pin->channels = substream->runtime->channels; 1462 per_pin->setup = true; 1463 per_pin->mux_idx = mux_idx; 1464 1465 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1466 } 1467 1468 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, 1469 struct hdmi_spec_per_pin *per_pin) 1470 { 1471 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1472 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); 1473 1474 per_pin->chmap_set = false; 1475 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1476 1477 per_pin->setup = false; 1478 per_pin->channels = 0; 1479 } 1480 1481 static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec, 1482 struct hdmi_spec_per_pin *per_pin) 1483 { 1484 struct hdmi_spec *spec = codec->spec; 1485 1486 if (per_pin->pcm_idx >= 0) 1487 return spec->pcm_rec[per_pin->pcm_idx].jack; 1488 else 1489 return NULL; 1490 } 1491 1492 /* update per_pin ELD from the given new ELD; 1493 * setup info frame and notification accordingly 1494 * also notify ELD kctl and report jack status changes 1495 */ 1496 static void update_eld(struct hda_codec *codec, 1497 struct hdmi_spec_per_pin *per_pin, 1498 struct hdmi_eld *eld, 1499 int repoll) 1500 { 1501 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 1502 struct hdmi_spec *spec = codec->spec; 1503 struct snd_jack *pcm_jack; 1504 bool old_eld_valid = pin_eld->eld_valid; 1505 bool eld_changed; 1506 int pcm_idx; 1507 1508 if (eld->eld_valid) { 1509 if (eld->eld_size <= 0 || 1510 snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, 1511 eld->eld_size) < 0) { 1512 eld->eld_valid = false; 1513 if (repoll) { 1514 schedule_delayed_work(&per_pin->work, 1515 msecs_to_jiffies(300)); 1516 return; 1517 } 1518 } 1519 } 1520 1521 if (!eld->eld_valid || eld->eld_size <= 0) { 1522 eld->eld_valid = false; 1523 eld->eld_size = 0; 1524 } 1525 1526 /* for monitor disconnection, save pcm_idx firstly */ 1527 pcm_idx = per_pin->pcm_idx; 1528 1529 /* 1530 * pcm_idx >=0 before update_eld() means it is in monitor 1531 * disconnected event. Jack must be fetched before update_eld(). 1532 */ 1533 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); 1534 1535 if (spec->dyn_pcm_assign) { 1536 if (eld->eld_valid) { 1537 hdmi_attach_hda_pcm(spec, per_pin); 1538 hdmi_pcm_setup_pin(spec, per_pin); 1539 } else { 1540 hdmi_pcm_reset_pin(spec, per_pin); 1541 hdmi_detach_hda_pcm(spec, per_pin); 1542 } 1543 } 1544 /* if pcm_idx == -1, it means this is in monitor connection event 1545 * we can get the correct pcm_idx now. 1546 */ 1547 if (pcm_idx == -1) 1548 pcm_idx = per_pin->pcm_idx; 1549 if (!pcm_jack) 1550 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); 1551 1552 if (eld->eld_valid) 1553 snd_hdmi_show_eld(codec, &eld->info); 1554 1555 eld_changed = (pin_eld->eld_valid != eld->eld_valid); 1556 eld_changed |= (pin_eld->monitor_present != eld->monitor_present); 1557 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid) 1558 if (pin_eld->eld_size != eld->eld_size || 1559 memcmp(pin_eld->eld_buffer, eld->eld_buffer, 1560 eld->eld_size) != 0) 1561 eld_changed = true; 1562 1563 if (eld_changed) { 1564 pin_eld->monitor_present = eld->monitor_present; 1565 pin_eld->eld_valid = eld->eld_valid; 1566 pin_eld->eld_size = eld->eld_size; 1567 if (eld->eld_valid) 1568 memcpy(pin_eld->eld_buffer, eld->eld_buffer, 1569 eld->eld_size); 1570 pin_eld->info = eld->info; 1571 } 1572 1573 /* 1574 * Re-setup pin and infoframe. This is needed e.g. when 1575 * - sink is first plugged-in 1576 * - transcoder can change during stream playback on Haswell 1577 * and this can make HW reset converter selection on a pin. 1578 */ 1579 if (eld->eld_valid && !old_eld_valid && per_pin->setup) { 1580 pin_cvt_fixup(codec, per_pin, 0); 1581 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1582 } 1583 1584 if (eld_changed && pcm_idx >= 0) 1585 snd_ctl_notify(codec->card, 1586 SNDRV_CTL_EVENT_MASK_VALUE | 1587 SNDRV_CTL_EVENT_MASK_INFO, 1588 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); 1589 1590 if (eld_changed && pcm_jack) 1591 snd_jack_report(pcm_jack, 1592 (eld->monitor_present && eld->eld_valid) ? 1593 SND_JACK_AVOUT : 0); 1594 } 1595 1596 /* update ELD and jack state via HD-audio verbs */ 1597 static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, 1598 int repoll) 1599 { 1600 struct hda_codec *codec = per_pin->codec; 1601 struct hdmi_spec *spec = codec->spec; 1602 struct hdmi_eld *eld = &spec->temp_eld; 1603 hda_nid_t pin_nid = per_pin->pin_nid; 1604 int dev_id = per_pin->dev_id; 1605 /* 1606 * Always execute a GetPinSense verb here, even when called from 1607 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited 1608 * response's PD bit is not the real PD value, but indicates that 1609 * the real PD value changed. An older version of the HD-audio 1610 * specification worked this way. Hence, we just ignore the data in 1611 * the unsolicited response to avoid custom WARs. 1612 */ 1613 int present; 1614 int ret; 1615 1616 ret = snd_hda_power_up_pm(codec); 1617 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) 1618 goto out; 1619 1620 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id); 1621 1622 mutex_lock(&per_pin->lock); 1623 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); 1624 if (eld->monitor_present) 1625 eld->eld_valid = !!(present & AC_PINSENSE_ELDV); 1626 else 1627 eld->eld_valid = false; 1628 1629 codec_dbg(codec, 1630 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n", 1631 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); 1632 1633 if (eld->eld_valid) { 1634 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id, 1635 eld->eld_buffer, &eld->eld_size) < 0) 1636 eld->eld_valid = false; 1637 } 1638 1639 update_eld(codec, per_pin, eld, repoll); 1640 mutex_unlock(&per_pin->lock); 1641 out: 1642 snd_hda_power_down_pm(codec); 1643 } 1644 1645 static void silent_stream_enable(struct hda_codec *codec, 1646 struct hdmi_spec_per_pin *per_pin) 1647 { 1648 unsigned int newval, oldval; 1649 1650 codec_dbg(codec, "hdmi: enabling silent stream for NID %d\n", 1651 per_pin->pin_nid); 1652 1653 mutex_lock(&per_pin->lock); 1654 1655 if (!per_pin->channels) 1656 per_pin->channels = 2; 1657 1658 oldval = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 1659 AC_VERB_GET_CONV, 0); 1660 newval = (oldval & 0xF0) | 0xF; 1661 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 1662 AC_VERB_SET_CHANNEL_STREAMID, newval); 1663 1664 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1665 1666 mutex_unlock(&per_pin->lock); 1667 } 1668 1669 /* update ELD and jack state via audio component */ 1670 static void sync_eld_via_acomp(struct hda_codec *codec, 1671 struct hdmi_spec_per_pin *per_pin) 1672 { 1673 struct hdmi_spec *spec = codec->spec; 1674 struct hdmi_eld *eld = &spec->temp_eld; 1675 bool monitor_prev, monitor_next; 1676 1677 mutex_lock(&per_pin->lock); 1678 eld->monitor_present = false; 1679 monitor_prev = per_pin->sink_eld.monitor_present; 1680 eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, 1681 per_pin->dev_id, &eld->monitor_present, 1682 eld->eld_buffer, ELD_MAX_SIZE); 1683 eld->eld_valid = (eld->eld_size > 0); 1684 update_eld(codec, per_pin, eld, 0); 1685 monitor_next = per_pin->sink_eld.monitor_present; 1686 mutex_unlock(&per_pin->lock); 1687 1688 /* 1689 * Power-up will call hdmi_present_sense, so the PM calls 1690 * have to be done without mutex held. 1691 */ 1692 1693 if (spec->send_silent_stream) { 1694 int pm_ret; 1695 1696 if (!monitor_prev && monitor_next) { 1697 pm_ret = snd_hda_power_up_pm(codec); 1698 if (pm_ret < 0) 1699 codec_err(codec, 1700 "Monitor plugged-in, Failed to power up codec ret=[%d]\n", 1701 pm_ret); 1702 silent_stream_enable(codec, per_pin); 1703 } else if (monitor_prev && !monitor_next) { 1704 pm_ret = snd_hda_power_down_pm(codec); 1705 if (pm_ret < 0) 1706 codec_err(codec, 1707 "Monitor plugged-out, Failed to power down codec ret=[%d]\n", 1708 pm_ret); 1709 } 1710 } 1711 } 1712 1713 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) 1714 { 1715 struct hda_codec *codec = per_pin->codec; 1716 1717 if (!codec_has_acomp(codec)) 1718 hdmi_present_sense_via_verbs(per_pin, repoll); 1719 else 1720 sync_eld_via_acomp(codec, per_pin); 1721 } 1722 1723 static void hdmi_repoll_eld(struct work_struct *work) 1724 { 1725 struct hdmi_spec_per_pin *per_pin = 1726 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); 1727 struct hda_codec *codec = per_pin->codec; 1728 struct hdmi_spec *spec = codec->spec; 1729 struct hda_jack_tbl *jack; 1730 1731 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid, 1732 per_pin->dev_id); 1733 if (jack) 1734 jack->jack_dirty = 1; 1735 1736 if (per_pin->repoll_count++ > 6) 1737 per_pin->repoll_count = 0; 1738 1739 mutex_lock(&spec->pcm_lock); 1740 hdmi_present_sense(per_pin, per_pin->repoll_count); 1741 mutex_unlock(&spec->pcm_lock); 1742 } 1743 1744 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) 1745 { 1746 struct hdmi_spec *spec = codec->spec; 1747 unsigned int caps, config; 1748 int pin_idx; 1749 struct hdmi_spec_per_pin *per_pin; 1750 int err; 1751 int dev_num, i; 1752 1753 caps = snd_hda_query_pin_caps(codec, pin_nid); 1754 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) 1755 return 0; 1756 1757 /* 1758 * For DP MST audio, Configuration Default is the same for 1759 * all device entries on the same pin 1760 */ 1761 config = snd_hda_codec_get_pincfg(codec, pin_nid); 1762 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE && 1763 !spec->force_connect) 1764 return 0; 1765 1766 /* 1767 * To simplify the implementation, malloc all 1768 * the virtual pins in the initialization statically 1769 */ 1770 if (spec->intel_hsw_fixup) { 1771 /* 1772 * On Intel platforms, device entries number is 1773 * changed dynamically. If there is a DP MST 1774 * hub connected, the device entries number is 3. 1775 * Otherwise, it is 1. 1776 * Here we manually set dev_num to 3, so that 1777 * we can initialize all the device entries when 1778 * bootup statically. 1779 */ 1780 dev_num = 3; 1781 spec->dev_num = 3; 1782 } else if (spec->dyn_pcm_assign && codec->dp_mst) { 1783 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; 1784 /* 1785 * spec->dev_num is the maxinum number of device entries 1786 * among all the pins 1787 */ 1788 spec->dev_num = (spec->dev_num > dev_num) ? 1789 spec->dev_num : dev_num; 1790 } else { 1791 /* 1792 * If the platform doesn't support DP MST, 1793 * manually set dev_num to 1. This means 1794 * the pin has only one device entry. 1795 */ 1796 dev_num = 1; 1797 spec->dev_num = 1; 1798 } 1799 1800 for (i = 0; i < dev_num; i++) { 1801 pin_idx = spec->num_pins; 1802 per_pin = snd_array_new(&spec->pins); 1803 1804 if (!per_pin) 1805 return -ENOMEM; 1806 1807 if (spec->dyn_pcm_assign) { 1808 per_pin->pcm = NULL; 1809 per_pin->pcm_idx = -1; 1810 } else { 1811 per_pin->pcm = get_hdmi_pcm(spec, pin_idx); 1812 per_pin->pcm_idx = pin_idx; 1813 } 1814 per_pin->pin_nid = pin_nid; 1815 per_pin->pin_nid_idx = spec->num_nids; 1816 per_pin->dev_id = i; 1817 per_pin->non_pcm = false; 1818 snd_hda_set_dev_select(codec, pin_nid, i); 1819 err = hdmi_read_pin_conn(codec, pin_idx); 1820 if (err < 0) 1821 return err; 1822 spec->num_pins++; 1823 } 1824 spec->num_nids++; 1825 1826 return 0; 1827 } 1828 1829 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1830 { 1831 struct hdmi_spec *spec = codec->spec; 1832 struct hdmi_spec_per_cvt *per_cvt; 1833 unsigned int chans; 1834 int err; 1835 1836 chans = get_wcaps(codec, cvt_nid); 1837 chans = get_wcaps_channels(chans); 1838 1839 per_cvt = snd_array_new(&spec->cvts); 1840 if (!per_cvt) 1841 return -ENOMEM; 1842 1843 per_cvt->cvt_nid = cvt_nid; 1844 per_cvt->channels_min = 2; 1845 if (chans <= 16) { 1846 per_cvt->channels_max = chans; 1847 if (chans > spec->chmap.channels_max) 1848 spec->chmap.channels_max = chans; 1849 } 1850 1851 err = snd_hda_query_supported_pcm(codec, cvt_nid, 1852 &per_cvt->rates, 1853 &per_cvt->formats, 1854 &per_cvt->maxbps); 1855 if (err < 0) 1856 return err; 1857 1858 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) 1859 spec->cvt_nids[spec->num_cvts] = cvt_nid; 1860 spec->num_cvts++; 1861 1862 return 0; 1863 } 1864 1865 static const struct snd_pci_quirk force_connect_list[] = { 1866 SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1), 1867 {} 1868 }; 1869 1870 static int hdmi_parse_codec(struct hda_codec *codec) 1871 { 1872 struct hdmi_spec *spec = codec->spec; 1873 hda_nid_t start_nid; 1874 unsigned int caps; 1875 int i, nodes; 1876 const struct snd_pci_quirk *q; 1877 1878 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid); 1879 if (!start_nid || nodes < 0) { 1880 codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); 1881 return -EINVAL; 1882 } 1883 1884 q = snd_pci_quirk_lookup(codec->bus->pci, force_connect_list); 1885 1886 if (q && q->value) 1887 spec->force_connect = true; 1888 1889 /* 1890 * hdmi_add_pin() assumes total amount of converters to 1891 * be known, so first discover all converters 1892 */ 1893 for (i = 0; i < nodes; i++) { 1894 hda_nid_t nid = start_nid + i; 1895 1896 caps = get_wcaps(codec, nid); 1897 1898 if (!(caps & AC_WCAP_DIGITAL)) 1899 continue; 1900 1901 if (get_wcaps_type(caps) == AC_WID_AUD_OUT) 1902 hdmi_add_cvt(codec, nid); 1903 } 1904 1905 /* discover audio pins */ 1906 for (i = 0; i < nodes; i++) { 1907 hda_nid_t nid = start_nid + i; 1908 1909 caps = get_wcaps(codec, nid); 1910 1911 if (!(caps & AC_WCAP_DIGITAL)) 1912 continue; 1913 1914 if (get_wcaps_type(caps) == AC_WID_PIN) 1915 hdmi_add_pin(codec, nid); 1916 } 1917 1918 return 0; 1919 } 1920 1921 /* 1922 */ 1923 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1924 { 1925 struct hda_spdif_out *spdif; 1926 bool non_pcm; 1927 1928 mutex_lock(&codec->spdif_mutex); 1929 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); 1930 /* Add sanity check to pass klockwork check. 1931 * This should never happen. 1932 */ 1933 if (WARN_ON(spdif == NULL)) { 1934 mutex_unlock(&codec->spdif_mutex); 1935 return true; 1936 } 1937 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); 1938 mutex_unlock(&codec->spdif_mutex); 1939 return non_pcm; 1940 } 1941 1942 /* 1943 * HDMI callbacks 1944 */ 1945 1946 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 1947 struct hda_codec *codec, 1948 unsigned int stream_tag, 1949 unsigned int format, 1950 struct snd_pcm_substream *substream) 1951 { 1952 hda_nid_t cvt_nid = hinfo->nid; 1953 struct hdmi_spec *spec = codec->spec; 1954 int pin_idx; 1955 struct hdmi_spec_per_pin *per_pin; 1956 struct snd_pcm_runtime *runtime = substream->runtime; 1957 bool non_pcm; 1958 int pinctl, stripe; 1959 int err = 0; 1960 1961 mutex_lock(&spec->pcm_lock); 1962 pin_idx = hinfo_to_pin_index(codec, hinfo); 1963 if (spec->dyn_pcm_assign && pin_idx < 0) { 1964 /* when dyn_pcm_assign and pcm is not bound to a pin 1965 * skip pin setup and return 0 to make audio playback 1966 * be ongoing 1967 */ 1968 pin_cvt_fixup(codec, NULL, cvt_nid); 1969 snd_hda_codec_setup_stream(codec, cvt_nid, 1970 stream_tag, 0, format); 1971 goto unlock; 1972 } 1973 1974 if (snd_BUG_ON(pin_idx < 0)) { 1975 err = -EINVAL; 1976 goto unlock; 1977 } 1978 per_pin = get_pin(spec, pin_idx); 1979 1980 /* Verify pin:cvt selections to avoid silent audio after S3. 1981 * After S3, the audio driver restores pin:cvt selections 1982 * but this can happen before gfx is ready and such selection 1983 * is overlooked by HW. Thus multiple pins can share a same 1984 * default convertor and mute control will affect each other, 1985 * which can cause a resumed audio playback become silent 1986 * after S3. 1987 */ 1988 pin_cvt_fixup(codec, per_pin, 0); 1989 1990 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ 1991 /* Todo: add DP1.2 MST audio support later */ 1992 if (codec_has_acomp(codec)) 1993 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, 1994 per_pin->dev_id, runtime->rate); 1995 1996 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); 1997 mutex_lock(&per_pin->lock); 1998 per_pin->channels = substream->runtime->channels; 1999 per_pin->setup = true; 2000 2001 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) { 2002 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core, 2003 substream); 2004 snd_hda_codec_write(codec, cvt_nid, 0, 2005 AC_VERB_SET_STRIPE_CONTROL, 2006 stripe); 2007 } 2008 2009 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 2010 mutex_unlock(&per_pin->lock); 2011 if (spec->dyn_pin_out) { 2012 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2013 per_pin->dev_id); 2014 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2015 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2016 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2017 AC_VERB_SET_PIN_WIDGET_CONTROL, 2018 pinctl | PIN_OUT); 2019 } 2020 2021 /* snd_hda_set_dev_select() has been called before */ 2022 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid, 2023 per_pin->dev_id, stream_tag, format); 2024 unlock: 2025 mutex_unlock(&spec->pcm_lock); 2026 return err; 2027 } 2028 2029 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 2030 struct hda_codec *codec, 2031 struct snd_pcm_substream *substream) 2032 { 2033 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 2034 return 0; 2035 } 2036 2037 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, 2038 struct hda_codec *codec, 2039 struct snd_pcm_substream *substream) 2040 { 2041 struct hdmi_spec *spec = codec->spec; 2042 int cvt_idx, pin_idx, pcm_idx; 2043 struct hdmi_spec_per_cvt *per_cvt; 2044 struct hdmi_spec_per_pin *per_pin; 2045 int pinctl; 2046 int err = 0; 2047 2048 if (hinfo->nid) { 2049 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 2050 if (snd_BUG_ON(pcm_idx < 0)) 2051 return -EINVAL; 2052 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); 2053 if (snd_BUG_ON(cvt_idx < 0)) 2054 return -EINVAL; 2055 per_cvt = get_cvt(spec, cvt_idx); 2056 2057 snd_BUG_ON(!per_cvt->assigned); 2058 per_cvt->assigned = 0; 2059 hinfo->nid = 0; 2060 2061 azx_stream(get_azx_dev(substream))->stripe = 0; 2062 2063 mutex_lock(&spec->pcm_lock); 2064 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2065 clear_bit(pcm_idx, &spec->pcm_in_use); 2066 pin_idx = hinfo_to_pin_index(codec, hinfo); 2067 if (spec->dyn_pcm_assign && pin_idx < 0) 2068 goto unlock; 2069 2070 if (snd_BUG_ON(pin_idx < 0)) { 2071 err = -EINVAL; 2072 goto unlock; 2073 } 2074 per_pin = get_pin(spec, pin_idx); 2075 2076 if (spec->dyn_pin_out) { 2077 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2078 per_pin->dev_id); 2079 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2080 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2081 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2082 AC_VERB_SET_PIN_WIDGET_CONTROL, 2083 pinctl & ~PIN_OUT); 2084 } 2085 2086 mutex_lock(&per_pin->lock); 2087 per_pin->chmap_set = false; 2088 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 2089 2090 per_pin->setup = false; 2091 per_pin->channels = 0; 2092 mutex_unlock(&per_pin->lock); 2093 unlock: 2094 mutex_unlock(&spec->pcm_lock); 2095 } 2096 2097 return err; 2098 } 2099 2100 static const struct hda_pcm_ops generic_ops = { 2101 .open = hdmi_pcm_open, 2102 .close = hdmi_pcm_close, 2103 .prepare = generic_hdmi_playback_pcm_prepare, 2104 .cleanup = generic_hdmi_playback_pcm_cleanup, 2105 }; 2106 2107 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) 2108 { 2109 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2110 struct hdmi_spec *spec = codec->spec; 2111 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2112 2113 if (!per_pin) 2114 return 0; 2115 2116 return per_pin->sink_eld.info.spk_alloc; 2117 } 2118 2119 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, 2120 unsigned char *chmap) 2121 { 2122 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2123 struct hdmi_spec *spec = codec->spec; 2124 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2125 2126 /* chmap is already set to 0 in caller */ 2127 if (!per_pin) 2128 return; 2129 2130 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); 2131 } 2132 2133 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, 2134 unsigned char *chmap, int prepared) 2135 { 2136 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2137 struct hdmi_spec *spec = codec->spec; 2138 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2139 2140 if (!per_pin) 2141 return; 2142 mutex_lock(&per_pin->lock); 2143 per_pin->chmap_set = true; 2144 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); 2145 if (prepared) 2146 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 2147 mutex_unlock(&per_pin->lock); 2148 } 2149 2150 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) 2151 { 2152 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2153 struct hdmi_spec *spec = codec->spec; 2154 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2155 2156 return per_pin ? true:false; 2157 } 2158 2159 static int generic_hdmi_build_pcms(struct hda_codec *codec) 2160 { 2161 struct hdmi_spec *spec = codec->spec; 2162 int idx, pcm_num; 2163 2164 /* 2165 * for non-mst mode, pcm number is the same as before 2166 * for DP MST mode without extra PCM, pcm number is same 2167 * for DP MST mode with extra PCMs, pcm number is 2168 * (nid number + dev_num - 1) 2169 * dev_num is the device entry number in a pin 2170 */ 2171 2172 if (codec->mst_no_extra_pcms) 2173 pcm_num = spec->num_nids; 2174 else 2175 pcm_num = spec->num_nids + spec->dev_num - 1; 2176 2177 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num); 2178 2179 for (idx = 0; idx < pcm_num; idx++) { 2180 struct hda_pcm *info; 2181 struct hda_pcm_stream *pstr; 2182 2183 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); 2184 if (!info) 2185 return -ENOMEM; 2186 2187 spec->pcm_rec[idx].pcm = info; 2188 spec->pcm_used++; 2189 info->pcm_type = HDA_PCM_TYPE_HDMI; 2190 info->own_chmap = true; 2191 2192 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2193 pstr->substreams = 1; 2194 pstr->ops = generic_ops; 2195 /* pcm number is less than 16 */ 2196 if (spec->pcm_used >= 16) 2197 break; 2198 /* other pstr fields are set in open */ 2199 } 2200 2201 return 0; 2202 } 2203 2204 static void free_hdmi_jack_priv(struct snd_jack *jack) 2205 { 2206 struct hdmi_pcm *pcm = jack->private_data; 2207 2208 pcm->jack = NULL; 2209 } 2210 2211 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) 2212 { 2213 char hdmi_str[32] = "HDMI/DP"; 2214 struct hdmi_spec *spec = codec->spec; 2215 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pcm_idx); 2216 struct snd_jack *jack; 2217 int pcmdev = get_pcm_rec(spec, pcm_idx)->device; 2218 int err; 2219 2220 if (pcmdev > 0) 2221 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); 2222 if (!spec->dyn_pcm_assign && 2223 !is_jack_detectable(codec, per_pin->pin_nid)) 2224 strncat(hdmi_str, " Phantom", 2225 sizeof(hdmi_str) - strlen(hdmi_str) - 1); 2226 2227 err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack, 2228 true, false); 2229 if (err < 0) 2230 return err; 2231 2232 spec->pcm_rec[pcm_idx].jack = jack; 2233 jack->private_data = &spec->pcm_rec[pcm_idx]; 2234 jack->private_free = free_hdmi_jack_priv; 2235 return 0; 2236 } 2237 2238 static int generic_hdmi_build_controls(struct hda_codec *codec) 2239 { 2240 struct hdmi_spec *spec = codec->spec; 2241 int dev, err; 2242 int pin_idx, pcm_idx; 2243 2244 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2245 if (!get_pcm_rec(spec, pcm_idx)->pcm) { 2246 /* no PCM: mark this for skipping permanently */ 2247 set_bit(pcm_idx, &spec->pcm_bitmap); 2248 continue; 2249 } 2250 2251 err = generic_hdmi_build_jack(codec, pcm_idx); 2252 if (err < 0) 2253 return err; 2254 2255 /* create the spdif for each pcm 2256 * pin will be bound when monitor is connected 2257 */ 2258 if (spec->dyn_pcm_assign) 2259 err = snd_hda_create_dig_out_ctls(codec, 2260 0, spec->cvt_nids[0], 2261 HDA_PCM_TYPE_HDMI); 2262 else { 2263 struct hdmi_spec_per_pin *per_pin = 2264 get_pin(spec, pcm_idx); 2265 err = snd_hda_create_dig_out_ctls(codec, 2266 per_pin->pin_nid, 2267 per_pin->mux_nids[0], 2268 HDA_PCM_TYPE_HDMI); 2269 } 2270 if (err < 0) 2271 return err; 2272 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2273 2274 dev = get_pcm_rec(spec, pcm_idx)->device; 2275 if (dev != SNDRV_PCM_INVALID_DEVICE) { 2276 /* add control for ELD Bytes */ 2277 err = hdmi_create_eld_ctl(codec, pcm_idx, dev); 2278 if (err < 0) 2279 return err; 2280 } 2281 } 2282 2283 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2284 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2285 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 2286 2287 pin_eld->eld_valid = false; 2288 hdmi_present_sense(per_pin, 0); 2289 } 2290 2291 /* add channel maps */ 2292 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2293 struct hda_pcm *pcm; 2294 2295 pcm = get_pcm_rec(spec, pcm_idx); 2296 if (!pcm || !pcm->pcm) 2297 break; 2298 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); 2299 if (err < 0) 2300 return err; 2301 } 2302 2303 return 0; 2304 } 2305 2306 static int generic_hdmi_init_per_pins(struct hda_codec *codec) 2307 { 2308 struct hdmi_spec *spec = codec->spec; 2309 int pin_idx; 2310 2311 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2312 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2313 2314 per_pin->codec = codec; 2315 mutex_init(&per_pin->lock); 2316 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); 2317 eld_proc_new(per_pin, pin_idx); 2318 } 2319 return 0; 2320 } 2321 2322 static int generic_hdmi_init(struct hda_codec *codec) 2323 { 2324 struct hdmi_spec *spec = codec->spec; 2325 int pin_idx; 2326 2327 mutex_lock(&spec->bind_lock); 2328 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2329 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2330 hda_nid_t pin_nid = per_pin->pin_nid; 2331 int dev_id = per_pin->dev_id; 2332 2333 snd_hda_set_dev_select(codec, pin_nid, dev_id); 2334 hdmi_init_pin(codec, pin_nid); 2335 if (codec_has_acomp(codec)) 2336 continue; 2337 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id, 2338 jack_callback); 2339 } 2340 mutex_unlock(&spec->bind_lock); 2341 return 0; 2342 } 2343 2344 static void hdmi_array_init(struct hdmi_spec *spec, int nums) 2345 { 2346 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); 2347 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); 2348 } 2349 2350 static void hdmi_array_free(struct hdmi_spec *spec) 2351 { 2352 snd_array_free(&spec->pins); 2353 snd_array_free(&spec->cvts); 2354 } 2355 2356 static void generic_spec_free(struct hda_codec *codec) 2357 { 2358 struct hdmi_spec *spec = codec->spec; 2359 2360 if (spec) { 2361 hdmi_array_free(spec); 2362 kfree(spec); 2363 codec->spec = NULL; 2364 } 2365 codec->dp_mst = false; 2366 } 2367 2368 static void generic_hdmi_free(struct hda_codec *codec) 2369 { 2370 struct hdmi_spec *spec = codec->spec; 2371 int pin_idx, pcm_idx; 2372 2373 if (spec->acomp_registered) { 2374 snd_hdac_acomp_exit(&codec->bus->core); 2375 } else if (codec_has_acomp(codec)) { 2376 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL); 2377 } 2378 codec->relaxed_resume = 0; 2379 2380 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2381 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2382 cancel_delayed_work_sync(&per_pin->work); 2383 eld_proc_free(per_pin); 2384 } 2385 2386 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2387 if (spec->pcm_rec[pcm_idx].jack == NULL) 2388 continue; 2389 if (spec->dyn_pcm_assign) 2390 snd_device_free(codec->card, 2391 spec->pcm_rec[pcm_idx].jack); 2392 else 2393 spec->pcm_rec[pcm_idx].jack = NULL; 2394 } 2395 2396 generic_spec_free(codec); 2397 } 2398 2399 #ifdef CONFIG_PM 2400 static int generic_hdmi_resume(struct hda_codec *codec) 2401 { 2402 struct hdmi_spec *spec = codec->spec; 2403 int pin_idx; 2404 2405 codec->patch_ops.init(codec); 2406 snd_hda_regmap_sync(codec); 2407 2408 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2409 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2410 hdmi_present_sense(per_pin, 1); 2411 } 2412 return 0; 2413 } 2414 #endif 2415 2416 static const struct hda_codec_ops generic_hdmi_patch_ops = { 2417 .init = generic_hdmi_init, 2418 .free = generic_hdmi_free, 2419 .build_pcms = generic_hdmi_build_pcms, 2420 .build_controls = generic_hdmi_build_controls, 2421 .unsol_event = hdmi_unsol_event, 2422 #ifdef CONFIG_PM 2423 .resume = generic_hdmi_resume, 2424 #endif 2425 }; 2426 2427 static const struct hdmi_ops generic_standard_hdmi_ops = { 2428 .pin_get_eld = hdmi_pin_get_eld, 2429 .pin_setup_infoframe = hdmi_pin_setup_infoframe, 2430 .pin_hbr_setup = hdmi_pin_hbr_setup, 2431 .setup_stream = hdmi_setup_stream, 2432 }; 2433 2434 /* allocate codec->spec and assign/initialize generic parser ops */ 2435 static int alloc_generic_hdmi(struct hda_codec *codec) 2436 { 2437 struct hdmi_spec *spec; 2438 2439 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2440 if (!spec) 2441 return -ENOMEM; 2442 2443 spec->codec = codec; 2444 spec->ops = generic_standard_hdmi_ops; 2445 spec->dev_num = 1; /* initialize to 1 */ 2446 mutex_init(&spec->pcm_lock); 2447 mutex_init(&spec->bind_lock); 2448 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); 2449 2450 spec->chmap.ops.get_chmap = hdmi_get_chmap; 2451 spec->chmap.ops.set_chmap = hdmi_set_chmap; 2452 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; 2453 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc, 2454 2455 codec->spec = spec; 2456 hdmi_array_init(spec, 4); 2457 2458 codec->patch_ops = generic_hdmi_patch_ops; 2459 2460 return 0; 2461 } 2462 2463 /* generic HDMI parser */ 2464 static int patch_generic_hdmi(struct hda_codec *codec) 2465 { 2466 int err; 2467 2468 err = alloc_generic_hdmi(codec); 2469 if (err < 0) 2470 return err; 2471 2472 err = hdmi_parse_codec(codec); 2473 if (err < 0) { 2474 generic_spec_free(codec); 2475 return err; 2476 } 2477 2478 generic_hdmi_init_per_pins(codec); 2479 return 0; 2480 } 2481 2482 /* 2483 * generic audio component binding 2484 */ 2485 2486 /* turn on / off the unsol event jack detection dynamically */ 2487 static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid, 2488 int dev_id, bool use_acomp) 2489 { 2490 struct hda_jack_tbl *tbl; 2491 2492 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id); 2493 if (tbl) { 2494 /* clear unsol even if component notifier is used, or re-enable 2495 * if notifier is cleared 2496 */ 2497 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag); 2498 snd_hda_codec_write_cache(codec, nid, 0, 2499 AC_VERB_SET_UNSOLICITED_ENABLE, val); 2500 } 2501 } 2502 2503 /* set up / clear component notifier dynamically */ 2504 static void generic_acomp_notifier_set(struct drm_audio_component *acomp, 2505 bool use_acomp) 2506 { 2507 struct hdmi_spec *spec; 2508 int i; 2509 2510 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops); 2511 mutex_lock(&spec->bind_lock); 2512 spec->use_acomp_notifier = use_acomp; 2513 spec->codec->relaxed_resume = use_acomp; 2514 spec->codec->bus->keep_power = 0; 2515 /* reprogram each jack detection logic depending on the notifier */ 2516 for (i = 0; i < spec->num_pins; i++) 2517 reprogram_jack_detect(spec->codec, 2518 get_pin(spec, i)->pin_nid, 2519 get_pin(spec, i)->dev_id, 2520 use_acomp); 2521 mutex_unlock(&spec->bind_lock); 2522 } 2523 2524 /* enable / disable the notifier via master bind / unbind */ 2525 static int generic_acomp_master_bind(struct device *dev, 2526 struct drm_audio_component *acomp) 2527 { 2528 generic_acomp_notifier_set(acomp, true); 2529 return 0; 2530 } 2531 2532 static void generic_acomp_master_unbind(struct device *dev, 2533 struct drm_audio_component *acomp) 2534 { 2535 generic_acomp_notifier_set(acomp, false); 2536 } 2537 2538 /* check whether both HD-audio and DRM PCI devices belong to the same bus */ 2539 static int match_bound_vga(struct device *dev, int subtype, void *data) 2540 { 2541 struct hdac_bus *bus = data; 2542 struct pci_dev *pci, *master; 2543 2544 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev)) 2545 return 0; 2546 master = to_pci_dev(bus->dev); 2547 pci = to_pci_dev(dev); 2548 return master->bus == pci->bus; 2549 } 2550 2551 /* audio component notifier for AMD/Nvidia HDMI codecs */ 2552 static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id) 2553 { 2554 struct hda_codec *codec = audio_ptr; 2555 struct hdmi_spec *spec = codec->spec; 2556 hda_nid_t pin_nid = spec->port2pin(codec, port); 2557 2558 if (!pin_nid) 2559 return; 2560 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN) 2561 return; 2562 /* skip notification during system suspend (but not in runtime PM); 2563 * the state will be updated at resume 2564 */ 2565 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) 2566 return; 2567 /* ditto during suspend/resume process itself */ 2568 if (snd_hdac_is_in_pm(&codec->core)) 2569 return; 2570 2571 check_presence_and_report(codec, pin_nid, dev_id); 2572 } 2573 2574 /* set up the private drm_audio_ops from the template */ 2575 static void setup_drm_audio_ops(struct hda_codec *codec, 2576 const struct drm_audio_component_audio_ops *ops) 2577 { 2578 struct hdmi_spec *spec = codec->spec; 2579 2580 spec->drm_audio_ops.audio_ptr = codec; 2581 /* intel_audio_codec_enable() or intel_audio_codec_disable() 2582 * will call pin_eld_notify with using audio_ptr pointer 2583 * We need make sure audio_ptr is really setup 2584 */ 2585 wmb(); 2586 spec->drm_audio_ops.pin2port = ops->pin2port; 2587 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify; 2588 spec->drm_audio_ops.master_bind = ops->master_bind; 2589 spec->drm_audio_ops.master_unbind = ops->master_unbind; 2590 } 2591 2592 /* initialize the generic HDMI audio component */ 2593 static void generic_acomp_init(struct hda_codec *codec, 2594 const struct drm_audio_component_audio_ops *ops, 2595 int (*port2pin)(struct hda_codec *, int)) 2596 { 2597 struct hdmi_spec *spec = codec->spec; 2598 2599 if (!enable_acomp) { 2600 codec_info(codec, "audio component disabled by module option\n"); 2601 return; 2602 } 2603 2604 spec->port2pin = port2pin; 2605 setup_drm_audio_ops(codec, ops); 2606 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops, 2607 match_bound_vga, 0)) { 2608 spec->acomp_registered = true; 2609 } 2610 } 2611 2612 /* 2613 * Intel codec parsers and helpers 2614 */ 2615 2616 #define INTEL_GET_VENDOR_VERB 0xf81 2617 #define INTEL_SET_VENDOR_VERB 0x781 2618 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ 2619 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ 2620 2621 static void intel_haswell_enable_all_pins(struct hda_codec *codec, 2622 bool update_tree) 2623 { 2624 unsigned int vendor_param; 2625 struct hdmi_spec *spec = codec->spec; 2626 2627 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2628 INTEL_GET_VENDOR_VERB, 0); 2629 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) 2630 return; 2631 2632 vendor_param |= INTEL_EN_ALL_PIN_CVTS; 2633 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2634 INTEL_SET_VENDOR_VERB, vendor_param); 2635 if (vendor_param == -1) 2636 return; 2637 2638 if (update_tree) 2639 snd_hda_codec_update_widgets(codec); 2640 } 2641 2642 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) 2643 { 2644 unsigned int vendor_param; 2645 struct hdmi_spec *spec = codec->spec; 2646 2647 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2648 INTEL_GET_VENDOR_VERB, 0); 2649 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) 2650 return; 2651 2652 /* enable DP1.2 mode */ 2653 vendor_param |= INTEL_EN_DP12; 2654 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); 2655 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, 2656 INTEL_SET_VENDOR_VERB, vendor_param); 2657 } 2658 2659 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. 2660 * Otherwise you may get severe h/w communication errors. 2661 */ 2662 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, 2663 unsigned int power_state) 2664 { 2665 if (power_state == AC_PWRST_D0) { 2666 intel_haswell_enable_all_pins(codec, false); 2667 intel_haswell_fixup_enable_dp12(codec); 2668 } 2669 2670 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); 2671 snd_hda_codec_set_power_to_all(codec, fg, power_state); 2672 } 2673 2674 /* There is a fixed mapping between audio pin node and display port. 2675 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL: 2676 * Pin Widget 5 - PORT B (port = 1 in i915 driver) 2677 * Pin Widget 6 - PORT C (port = 2 in i915 driver) 2678 * Pin Widget 7 - PORT D (port = 3 in i915 driver) 2679 * 2680 * on VLV, ILK: 2681 * Pin Widget 4 - PORT B (port = 1 in i915 driver) 2682 * Pin Widget 5 - PORT C (port = 2 in i915 driver) 2683 * Pin Widget 6 - PORT D (port = 3 in i915 driver) 2684 */ 2685 static int intel_base_nid(struct hda_codec *codec) 2686 { 2687 switch (codec->core.vendor_id) { 2688 case 0x80860054: /* ILK */ 2689 case 0x80862804: /* ILK */ 2690 case 0x80862882: /* VLV */ 2691 return 4; 2692 default: 2693 return 5; 2694 } 2695 } 2696 2697 static int intel_pin2port(void *audio_ptr, int pin_nid) 2698 { 2699 struct hda_codec *codec = audio_ptr; 2700 struct hdmi_spec *spec = codec->spec; 2701 int base_nid, i; 2702 2703 if (!spec->port_num) { 2704 base_nid = intel_base_nid(codec); 2705 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3)) 2706 return -1; 2707 return pin_nid - base_nid + 1; 2708 } 2709 2710 /* 2711 * looking for the pin number in the mapping table and return 2712 * the index which indicate the port number 2713 */ 2714 for (i = 0; i < spec->port_num; i++) { 2715 if (pin_nid == spec->port_map[i]) 2716 return i; 2717 } 2718 2719 codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid); 2720 return -1; 2721 } 2722 2723 static int intel_port2pin(struct hda_codec *codec, int port) 2724 { 2725 struct hdmi_spec *spec = codec->spec; 2726 2727 if (!spec->port_num) { 2728 /* we assume only from port-B to port-D */ 2729 if (port < 1 || port > 3) 2730 return 0; 2731 return port + intel_base_nid(codec) - 1; 2732 } 2733 2734 if (port < 0 || port >= spec->port_num) 2735 return 0; 2736 return spec->port_map[port]; 2737 } 2738 2739 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) 2740 { 2741 struct hda_codec *codec = audio_ptr; 2742 int pin_nid; 2743 int dev_id = pipe; 2744 2745 pin_nid = intel_port2pin(codec, port); 2746 if (!pin_nid) 2747 return; 2748 /* skip notification during system suspend (but not in runtime PM); 2749 * the state will be updated at resume 2750 */ 2751 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) 2752 return; 2753 /* ditto during suspend/resume process itself */ 2754 if (snd_hdac_is_in_pm(&codec->core)) 2755 return; 2756 2757 snd_hdac_i915_set_bclk(&codec->bus->core); 2758 check_presence_and_report(codec, pin_nid, dev_id); 2759 } 2760 2761 static const struct drm_audio_component_audio_ops intel_audio_ops = { 2762 .pin2port = intel_pin2port, 2763 .pin_eld_notify = intel_pin_eld_notify, 2764 }; 2765 2766 /* register i915 component pin_eld_notify callback */ 2767 static void register_i915_notifier(struct hda_codec *codec) 2768 { 2769 struct hdmi_spec *spec = codec->spec; 2770 2771 spec->use_acomp_notifier = true; 2772 spec->port2pin = intel_port2pin; 2773 setup_drm_audio_ops(codec, &intel_audio_ops); 2774 snd_hdac_acomp_register_notifier(&codec->bus->core, 2775 &spec->drm_audio_ops); 2776 /* no need for forcible resume for jack check thanks to notifier */ 2777 codec->relaxed_resume = 1; 2778 } 2779 2780 /* setup_stream ops override for HSW+ */ 2781 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 2782 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 2783 int format) 2784 { 2785 haswell_verify_D0(codec, cvt_nid, pin_nid); 2786 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 2787 stream_tag, format); 2788 } 2789 2790 /* pin_cvt_fixup ops override for HSW+ and VLV+ */ 2791 static void i915_pin_cvt_fixup(struct hda_codec *codec, 2792 struct hdmi_spec_per_pin *per_pin, 2793 hda_nid_t cvt_nid) 2794 { 2795 if (per_pin) { 2796 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2797 per_pin->dev_id); 2798 intel_verify_pin_cvt_connect(codec, per_pin); 2799 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, 2800 per_pin->dev_id, per_pin->mux_idx); 2801 } else { 2802 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); 2803 } 2804 } 2805 2806 /* precondition and allocation for Intel codecs */ 2807 static int alloc_intel_hdmi(struct hda_codec *codec) 2808 { 2809 int err; 2810 2811 /* requires i915 binding */ 2812 if (!codec->bus->core.audio_component) { 2813 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); 2814 /* set probe_id here to prevent generic fallback binding */ 2815 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE; 2816 return -ENODEV; 2817 } 2818 2819 err = alloc_generic_hdmi(codec); 2820 if (err < 0) 2821 return err; 2822 /* no need to handle unsol events */ 2823 codec->patch_ops.unsol_event = NULL; 2824 return 0; 2825 } 2826 2827 /* parse and post-process for Intel codecs */ 2828 static int parse_intel_hdmi(struct hda_codec *codec) 2829 { 2830 int err, retries = 3; 2831 2832 do { 2833 err = hdmi_parse_codec(codec); 2834 } while (err < 0 && retries--); 2835 2836 if (err < 0) { 2837 generic_spec_free(codec); 2838 return err; 2839 } 2840 2841 generic_hdmi_init_per_pins(codec); 2842 register_i915_notifier(codec); 2843 return 0; 2844 } 2845 2846 /* Intel Haswell and onwards; audio component with eld notifier */ 2847 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid, 2848 const int *port_map, int port_num) 2849 { 2850 struct hdmi_spec *spec; 2851 int err; 2852 2853 err = alloc_intel_hdmi(codec); 2854 if (err < 0) 2855 return err; 2856 spec = codec->spec; 2857 codec->dp_mst = true; 2858 spec->dyn_pcm_assign = true; 2859 spec->vendor_nid = vendor_nid; 2860 spec->port_map = port_map; 2861 spec->port_num = port_num; 2862 spec->intel_hsw_fixup = true; 2863 2864 intel_haswell_enable_all_pins(codec, true); 2865 intel_haswell_fixup_enable_dp12(codec); 2866 2867 codec->display_power_control = 1; 2868 2869 codec->patch_ops.set_power_state = haswell_set_power_state; 2870 codec->depop_delay = 0; 2871 codec->auto_runtime_pm = 1; 2872 2873 spec->ops.setup_stream = i915_hsw_setup_stream; 2874 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2875 2876 /* 2877 * Enable silent stream feature, if it is enabled via 2878 * module param or Kconfig option 2879 */ 2880 if (enable_silent_stream) 2881 spec->send_silent_stream = true; 2882 2883 return parse_intel_hdmi(codec); 2884 } 2885 2886 static int patch_i915_hsw_hdmi(struct hda_codec *codec) 2887 { 2888 return intel_hsw_common_init(codec, 0x08, NULL, 0); 2889 } 2890 2891 static int patch_i915_glk_hdmi(struct hda_codec *codec) 2892 { 2893 return intel_hsw_common_init(codec, 0x0b, NULL, 0); 2894 } 2895 2896 static int patch_i915_icl_hdmi(struct hda_codec *codec) 2897 { 2898 /* 2899 * pin to port mapping table where the value indicate the pin number and 2900 * the index indicate the port number. 2901 */ 2902 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb}; 2903 2904 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map)); 2905 } 2906 2907 static int patch_i915_tgl_hdmi(struct hda_codec *codec) 2908 { 2909 /* 2910 * pin to port mapping table where the value indicate the pin number and 2911 * the index indicate the port number. 2912 */ 2913 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf}; 2914 2915 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map)); 2916 } 2917 2918 /* Intel Baytrail and Braswell; with eld notifier */ 2919 static int patch_i915_byt_hdmi(struct hda_codec *codec) 2920 { 2921 struct hdmi_spec *spec; 2922 int err; 2923 2924 err = alloc_intel_hdmi(codec); 2925 if (err < 0) 2926 return err; 2927 spec = codec->spec; 2928 2929 /* For Valleyview/Cherryview, only the display codec is in the display 2930 * power well and can use link_power ops to request/release the power. 2931 */ 2932 codec->display_power_control = 1; 2933 2934 codec->depop_delay = 0; 2935 codec->auto_runtime_pm = 1; 2936 2937 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2938 2939 return parse_intel_hdmi(codec); 2940 } 2941 2942 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ 2943 static int patch_i915_cpt_hdmi(struct hda_codec *codec) 2944 { 2945 int err; 2946 2947 err = alloc_intel_hdmi(codec); 2948 if (err < 0) 2949 return err; 2950 return parse_intel_hdmi(codec); 2951 } 2952 2953 /* 2954 * Shared non-generic implementations 2955 */ 2956 2957 static int simple_playback_build_pcms(struct hda_codec *codec) 2958 { 2959 struct hdmi_spec *spec = codec->spec; 2960 struct hda_pcm *info; 2961 unsigned int chans; 2962 struct hda_pcm_stream *pstr; 2963 struct hdmi_spec_per_cvt *per_cvt; 2964 2965 per_cvt = get_cvt(spec, 0); 2966 chans = get_wcaps(codec, per_cvt->cvt_nid); 2967 chans = get_wcaps_channels(chans); 2968 2969 info = snd_hda_codec_pcm_new(codec, "HDMI 0"); 2970 if (!info) 2971 return -ENOMEM; 2972 spec->pcm_rec[0].pcm = info; 2973 info->pcm_type = HDA_PCM_TYPE_HDMI; 2974 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2975 *pstr = spec->pcm_playback; 2976 pstr->nid = per_cvt->cvt_nid; 2977 if (pstr->channels_max <= 2 && chans && chans <= 16) 2978 pstr->channels_max = chans; 2979 2980 return 0; 2981 } 2982 2983 /* unsolicited event for jack sensing */ 2984 static void simple_hdmi_unsol_event(struct hda_codec *codec, 2985 unsigned int res) 2986 { 2987 snd_hda_jack_set_dirty_all(codec); 2988 snd_hda_jack_report_sync(codec); 2989 } 2990 2991 /* generic_hdmi_build_jack can be used for simple_hdmi, too, 2992 * as long as spec->pins[] is set correctly 2993 */ 2994 #define simple_hdmi_build_jack generic_hdmi_build_jack 2995 2996 static int simple_playback_build_controls(struct hda_codec *codec) 2997 { 2998 struct hdmi_spec *spec = codec->spec; 2999 struct hdmi_spec_per_cvt *per_cvt; 3000 int err; 3001 3002 per_cvt = get_cvt(spec, 0); 3003 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, 3004 per_cvt->cvt_nid, 3005 HDA_PCM_TYPE_HDMI); 3006 if (err < 0) 3007 return err; 3008 return simple_hdmi_build_jack(codec, 0); 3009 } 3010 3011 static int simple_playback_init(struct hda_codec *codec) 3012 { 3013 struct hdmi_spec *spec = codec->spec; 3014 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); 3015 hda_nid_t pin = per_pin->pin_nid; 3016 3017 snd_hda_codec_write(codec, pin, 0, 3018 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); 3019 /* some codecs require to unmute the pin */ 3020 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 3021 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, 3022 AMP_OUT_UNMUTE); 3023 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id); 3024 return 0; 3025 } 3026 3027 static void simple_playback_free(struct hda_codec *codec) 3028 { 3029 struct hdmi_spec *spec = codec->spec; 3030 3031 hdmi_array_free(spec); 3032 kfree(spec); 3033 } 3034 3035 /* 3036 * Nvidia specific implementations 3037 */ 3038 3039 #define Nv_VERB_SET_Channel_Allocation 0xF79 3040 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A 3041 #define Nv_VERB_SET_Audio_Protection_On 0xF98 3042 #define Nv_VERB_SET_Audio_Protection_Off 0xF99 3043 3044 #define nvhdmi_master_con_nid_7x 0x04 3045 #define nvhdmi_master_pin_nid_7x 0x05 3046 3047 static const hda_nid_t nvhdmi_con_nids_7x[4] = { 3048 /*front, rear, clfe, rear_surr */ 3049 0x6, 0x8, 0xa, 0xc, 3050 }; 3051 3052 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { 3053 /* set audio protect on */ 3054 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3055 /* enable digital output on pin widget */ 3056 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3057 {} /* terminator */ 3058 }; 3059 3060 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { 3061 /* set audio protect on */ 3062 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3063 /* enable digital output on pin widget */ 3064 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3065 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3066 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3067 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3068 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3069 {} /* terminator */ 3070 }; 3071 3072 #ifdef LIMITED_RATE_FMT_SUPPORT 3073 /* support only the safe format and rate */ 3074 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 3075 #define SUPPORTED_MAXBPS 16 3076 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE 3077 #else 3078 /* support all rates and formats */ 3079 #define SUPPORTED_RATES \ 3080 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ 3081 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ 3082 SNDRV_PCM_RATE_192000) 3083 #define SUPPORTED_MAXBPS 24 3084 #define SUPPORTED_FORMATS \ 3085 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 3086 #endif 3087 3088 static int nvhdmi_7x_init_2ch(struct hda_codec *codec) 3089 { 3090 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); 3091 return 0; 3092 } 3093 3094 static int nvhdmi_7x_init_8ch(struct hda_codec *codec) 3095 { 3096 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); 3097 return 0; 3098 } 3099 3100 static const unsigned int channels_2_6_8[] = { 3101 2, 6, 8 3102 }; 3103 3104 static const unsigned int channels_2_8[] = { 3105 2, 8 3106 }; 3107 3108 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { 3109 .count = ARRAY_SIZE(channels_2_6_8), 3110 .list = channels_2_6_8, 3111 .mask = 0, 3112 }; 3113 3114 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { 3115 .count = ARRAY_SIZE(channels_2_8), 3116 .list = channels_2_8, 3117 .mask = 0, 3118 }; 3119 3120 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, 3121 struct hda_codec *codec, 3122 struct snd_pcm_substream *substream) 3123 { 3124 struct hdmi_spec *spec = codec->spec; 3125 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; 3126 3127 switch (codec->preset->vendor_id) { 3128 case 0x10de0002: 3129 case 0x10de0003: 3130 case 0x10de0005: 3131 case 0x10de0006: 3132 hw_constraints_channels = &hw_constraints_2_8_channels; 3133 break; 3134 case 0x10de0007: 3135 hw_constraints_channels = &hw_constraints_2_6_8_channels; 3136 break; 3137 default: 3138 break; 3139 } 3140 3141 if (hw_constraints_channels != NULL) { 3142 snd_pcm_hw_constraint_list(substream->runtime, 0, 3143 SNDRV_PCM_HW_PARAM_CHANNELS, 3144 hw_constraints_channels); 3145 } else { 3146 snd_pcm_hw_constraint_step(substream->runtime, 0, 3147 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 3148 } 3149 3150 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3151 } 3152 3153 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, 3154 struct hda_codec *codec, 3155 struct snd_pcm_substream *substream) 3156 { 3157 struct hdmi_spec *spec = codec->spec; 3158 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3159 } 3160 3161 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3162 struct hda_codec *codec, 3163 unsigned int stream_tag, 3164 unsigned int format, 3165 struct snd_pcm_substream *substream) 3166 { 3167 struct hdmi_spec *spec = codec->spec; 3168 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3169 stream_tag, format, substream); 3170 } 3171 3172 static const struct hda_pcm_stream simple_pcm_playback = { 3173 .substreams = 1, 3174 .channels_min = 2, 3175 .channels_max = 2, 3176 .ops = { 3177 .open = simple_playback_pcm_open, 3178 .close = simple_playback_pcm_close, 3179 .prepare = simple_playback_pcm_prepare 3180 }, 3181 }; 3182 3183 static const struct hda_codec_ops simple_hdmi_patch_ops = { 3184 .build_controls = simple_playback_build_controls, 3185 .build_pcms = simple_playback_build_pcms, 3186 .init = simple_playback_init, 3187 .free = simple_playback_free, 3188 .unsol_event = simple_hdmi_unsol_event, 3189 }; 3190 3191 static int patch_simple_hdmi(struct hda_codec *codec, 3192 hda_nid_t cvt_nid, hda_nid_t pin_nid) 3193 { 3194 struct hdmi_spec *spec; 3195 struct hdmi_spec_per_cvt *per_cvt; 3196 struct hdmi_spec_per_pin *per_pin; 3197 3198 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 3199 if (!spec) 3200 return -ENOMEM; 3201 3202 spec->codec = codec; 3203 codec->spec = spec; 3204 hdmi_array_init(spec, 1); 3205 3206 spec->multiout.num_dacs = 0; /* no analog */ 3207 spec->multiout.max_channels = 2; 3208 spec->multiout.dig_out_nid = cvt_nid; 3209 spec->num_cvts = 1; 3210 spec->num_pins = 1; 3211 per_pin = snd_array_new(&spec->pins); 3212 per_cvt = snd_array_new(&spec->cvts); 3213 if (!per_pin || !per_cvt) { 3214 simple_playback_free(codec); 3215 return -ENOMEM; 3216 } 3217 per_cvt->cvt_nid = cvt_nid; 3218 per_pin->pin_nid = pin_nid; 3219 spec->pcm_playback = simple_pcm_playback; 3220 3221 codec->patch_ops = simple_hdmi_patch_ops; 3222 3223 return 0; 3224 } 3225 3226 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, 3227 int channels) 3228 { 3229 unsigned int chanmask; 3230 int chan = channels ? (channels - 1) : 1; 3231 3232 switch (channels) { 3233 default: 3234 case 0: 3235 case 2: 3236 chanmask = 0x00; 3237 break; 3238 case 4: 3239 chanmask = 0x08; 3240 break; 3241 case 6: 3242 chanmask = 0x0b; 3243 break; 3244 case 8: 3245 chanmask = 0x13; 3246 break; 3247 } 3248 3249 /* Set the audio infoframe channel allocation and checksum fields. The 3250 * channel count is computed implicitly by the hardware. */ 3251 snd_hda_codec_write(codec, 0x1, 0, 3252 Nv_VERB_SET_Channel_Allocation, chanmask); 3253 3254 snd_hda_codec_write(codec, 0x1, 0, 3255 Nv_VERB_SET_Info_Frame_Checksum, 3256 (0x71 - chan - chanmask)); 3257 } 3258 3259 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, 3260 struct hda_codec *codec, 3261 struct snd_pcm_substream *substream) 3262 { 3263 struct hdmi_spec *spec = codec->spec; 3264 int i; 3265 3266 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 3267 0, AC_VERB_SET_CHANNEL_STREAMID, 0); 3268 for (i = 0; i < 4; i++) { 3269 /* set the stream id */ 3270 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3271 AC_VERB_SET_CHANNEL_STREAMID, 0); 3272 /* set the stream format */ 3273 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3274 AC_VERB_SET_STREAM_FORMAT, 0); 3275 } 3276 3277 /* The audio hardware sends a channel count of 0x7 (8ch) when all the 3278 * streams are disabled. */ 3279 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3280 3281 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3282 } 3283 3284 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, 3285 struct hda_codec *codec, 3286 unsigned int stream_tag, 3287 unsigned int format, 3288 struct snd_pcm_substream *substream) 3289 { 3290 int chs; 3291 unsigned int dataDCC2, channel_id; 3292 int i; 3293 struct hdmi_spec *spec = codec->spec; 3294 struct hda_spdif_out *spdif; 3295 struct hdmi_spec_per_cvt *per_cvt; 3296 3297 mutex_lock(&codec->spdif_mutex); 3298 per_cvt = get_cvt(spec, 0); 3299 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); 3300 3301 chs = substream->runtime->channels; 3302 3303 dataDCC2 = 0x2; 3304 3305 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ 3306 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) 3307 snd_hda_codec_write(codec, 3308 nvhdmi_master_con_nid_7x, 3309 0, 3310 AC_VERB_SET_DIGI_CONVERT_1, 3311 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3312 3313 /* set the stream id */ 3314 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3315 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); 3316 3317 /* set the stream format */ 3318 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3319 AC_VERB_SET_STREAM_FORMAT, format); 3320 3321 /* turn on again (if needed) */ 3322 /* enable and set the channel status audio/data flag */ 3323 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { 3324 snd_hda_codec_write(codec, 3325 nvhdmi_master_con_nid_7x, 3326 0, 3327 AC_VERB_SET_DIGI_CONVERT_1, 3328 spdif->ctls & 0xff); 3329 snd_hda_codec_write(codec, 3330 nvhdmi_master_con_nid_7x, 3331 0, 3332 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3333 } 3334 3335 for (i = 0; i < 4; i++) { 3336 if (chs == 2) 3337 channel_id = 0; 3338 else 3339 channel_id = i * 2; 3340 3341 /* turn off SPDIF once; 3342 *otherwise the IEC958 bits won't be updated 3343 */ 3344 if (codec->spdif_status_reset && 3345 (spdif->ctls & AC_DIG1_ENABLE)) 3346 snd_hda_codec_write(codec, 3347 nvhdmi_con_nids_7x[i], 3348 0, 3349 AC_VERB_SET_DIGI_CONVERT_1, 3350 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3351 /* set the stream id */ 3352 snd_hda_codec_write(codec, 3353 nvhdmi_con_nids_7x[i], 3354 0, 3355 AC_VERB_SET_CHANNEL_STREAMID, 3356 (stream_tag << 4) | channel_id); 3357 /* set the stream format */ 3358 snd_hda_codec_write(codec, 3359 nvhdmi_con_nids_7x[i], 3360 0, 3361 AC_VERB_SET_STREAM_FORMAT, 3362 format); 3363 /* turn on again (if needed) */ 3364 /* enable and set the channel status audio/data flag */ 3365 if (codec->spdif_status_reset && 3366 (spdif->ctls & AC_DIG1_ENABLE)) { 3367 snd_hda_codec_write(codec, 3368 nvhdmi_con_nids_7x[i], 3369 0, 3370 AC_VERB_SET_DIGI_CONVERT_1, 3371 spdif->ctls & 0xff); 3372 snd_hda_codec_write(codec, 3373 nvhdmi_con_nids_7x[i], 3374 0, 3375 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3376 } 3377 } 3378 3379 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); 3380 3381 mutex_unlock(&codec->spdif_mutex); 3382 return 0; 3383 } 3384 3385 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { 3386 .substreams = 1, 3387 .channels_min = 2, 3388 .channels_max = 8, 3389 .nid = nvhdmi_master_con_nid_7x, 3390 .rates = SUPPORTED_RATES, 3391 .maxbps = SUPPORTED_MAXBPS, 3392 .formats = SUPPORTED_FORMATS, 3393 .ops = { 3394 .open = simple_playback_pcm_open, 3395 .close = nvhdmi_8ch_7x_pcm_close, 3396 .prepare = nvhdmi_8ch_7x_pcm_prepare 3397 }, 3398 }; 3399 3400 static int patch_nvhdmi_2ch(struct hda_codec *codec) 3401 { 3402 struct hdmi_spec *spec; 3403 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, 3404 nvhdmi_master_pin_nid_7x); 3405 if (err < 0) 3406 return err; 3407 3408 codec->patch_ops.init = nvhdmi_7x_init_2ch; 3409 /* override the PCM rates, etc, as the codec doesn't give full list */ 3410 spec = codec->spec; 3411 spec->pcm_playback.rates = SUPPORTED_RATES; 3412 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; 3413 spec->pcm_playback.formats = SUPPORTED_FORMATS; 3414 return 0; 3415 } 3416 3417 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) 3418 { 3419 struct hdmi_spec *spec = codec->spec; 3420 int err = simple_playback_build_pcms(codec); 3421 if (!err) { 3422 struct hda_pcm *info = get_pcm_rec(spec, 0); 3423 info->own_chmap = true; 3424 } 3425 return err; 3426 } 3427 3428 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) 3429 { 3430 struct hdmi_spec *spec = codec->spec; 3431 struct hda_pcm *info; 3432 struct snd_pcm_chmap *chmap; 3433 int err; 3434 3435 err = simple_playback_build_controls(codec); 3436 if (err < 0) 3437 return err; 3438 3439 /* add channel maps */ 3440 info = get_pcm_rec(spec, 0); 3441 err = snd_pcm_add_chmap_ctls(info->pcm, 3442 SNDRV_PCM_STREAM_PLAYBACK, 3443 snd_pcm_alt_chmaps, 8, 0, &chmap); 3444 if (err < 0) 3445 return err; 3446 switch (codec->preset->vendor_id) { 3447 case 0x10de0002: 3448 case 0x10de0003: 3449 case 0x10de0005: 3450 case 0x10de0006: 3451 chmap->channel_mask = (1U << 2) | (1U << 8); 3452 break; 3453 case 0x10de0007: 3454 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); 3455 } 3456 return 0; 3457 } 3458 3459 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) 3460 { 3461 struct hdmi_spec *spec; 3462 int err = patch_nvhdmi_2ch(codec); 3463 if (err < 0) 3464 return err; 3465 spec = codec->spec; 3466 spec->multiout.max_channels = 8; 3467 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; 3468 codec->patch_ops.init = nvhdmi_7x_init_8ch; 3469 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; 3470 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; 3471 3472 /* Initialize the audio infoframe channel mask and checksum to something 3473 * valid */ 3474 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3475 3476 return 0; 3477 } 3478 3479 /* 3480 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: 3481 * - 0x10de0015 3482 * - 0x10de0040 3483 */ 3484 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, 3485 struct hdac_cea_channel_speaker_allocation *cap, int channels) 3486 { 3487 if (cap->ca_index == 0x00 && channels == 2) 3488 return SNDRV_CTL_TLVT_CHMAP_FIXED; 3489 3490 /* If the speaker allocation matches the channel count, it is OK. */ 3491 if (cap->channels != channels) 3492 return -1; 3493 3494 /* all channels are remappable freely */ 3495 return SNDRV_CTL_TLVT_CHMAP_VAR; 3496 } 3497 3498 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, 3499 int ca, int chs, unsigned char *map) 3500 { 3501 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) 3502 return -EINVAL; 3503 3504 return 0; 3505 } 3506 3507 /* map from pin NID to port; port is 0-based */ 3508 /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */ 3509 static int nvhdmi_pin2port(void *audio_ptr, int pin_nid) 3510 { 3511 return pin_nid - 4; 3512 } 3513 3514 /* reverse-map from port to pin NID: see above */ 3515 static int nvhdmi_port2pin(struct hda_codec *codec, int port) 3516 { 3517 return port + 4; 3518 } 3519 3520 static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = { 3521 .pin2port = nvhdmi_pin2port, 3522 .pin_eld_notify = generic_acomp_pin_eld_notify, 3523 .master_bind = generic_acomp_master_bind, 3524 .master_unbind = generic_acomp_master_unbind, 3525 }; 3526 3527 static int patch_nvhdmi(struct hda_codec *codec) 3528 { 3529 struct hdmi_spec *spec; 3530 int err; 3531 3532 err = alloc_generic_hdmi(codec); 3533 if (err < 0) 3534 return err; 3535 codec->dp_mst = true; 3536 3537 spec = codec->spec; 3538 spec->dyn_pcm_assign = true; 3539 3540 err = hdmi_parse_codec(codec); 3541 if (err < 0) { 3542 generic_spec_free(codec); 3543 return err; 3544 } 3545 3546 generic_hdmi_init_per_pins(codec); 3547 3548 spec->dyn_pin_out = true; 3549 3550 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3551 nvhdmi_chmap_cea_alloc_validate_get_type; 3552 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3553 3554 codec->link_down_at_suspend = 1; 3555 3556 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin); 3557 3558 return 0; 3559 } 3560 3561 static int patch_nvhdmi_legacy(struct hda_codec *codec) 3562 { 3563 struct hdmi_spec *spec; 3564 int err; 3565 3566 err = patch_generic_hdmi(codec); 3567 if (err) 3568 return err; 3569 3570 spec = codec->spec; 3571 spec->dyn_pin_out = true; 3572 3573 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3574 nvhdmi_chmap_cea_alloc_validate_get_type; 3575 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3576 3577 codec->link_down_at_suspend = 1; 3578 3579 return 0; 3580 } 3581 3582 /* 3583 * The HDA codec on NVIDIA Tegra contains two scratch registers that are 3584 * accessed using vendor-defined verbs. These registers can be used for 3585 * interoperability between the HDA and HDMI drivers. 3586 */ 3587 3588 /* Audio Function Group node */ 3589 #define NVIDIA_AFG_NID 0x01 3590 3591 /* 3592 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio 3593 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to 3594 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This 3595 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an 3596 * additional bit (at position 30) to signal the validity of the format. 3597 * 3598 * | 31 | 30 | 29 16 | 15 0 | 3599 * +---------+-------+--------+--------+ 3600 * | TRIGGER | VALID | UNUSED | FORMAT | 3601 * +-----------------------------------| 3602 * 3603 * Note that for the trigger bit to take effect it needs to change value 3604 * (i.e. it needs to be toggled). 3605 */ 3606 #define NVIDIA_GET_SCRATCH0 0xfa6 3607 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 3608 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 3609 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 3610 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa 3611 #define NVIDIA_SCRATCH_TRIGGER (1 << 7) 3612 #define NVIDIA_SCRATCH_VALID (1 << 6) 3613 3614 #define NVIDIA_GET_SCRATCH1 0xfab 3615 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac 3616 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad 3617 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae 3618 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf 3619 3620 /* 3621 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, 3622 * the format is invalidated so that the HDMI codec can be disabled. 3623 */ 3624 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format) 3625 { 3626 unsigned int value; 3627 3628 /* bits [31:30] contain the trigger and valid bits */ 3629 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0, 3630 NVIDIA_GET_SCRATCH0, 0); 3631 value = (value >> 24) & 0xff; 3632 3633 /* bits [15:0] are used to store the HDA format */ 3634 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3635 NVIDIA_SET_SCRATCH0_BYTE0, 3636 (format >> 0) & 0xff); 3637 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3638 NVIDIA_SET_SCRATCH0_BYTE1, 3639 (format >> 8) & 0xff); 3640 3641 /* bits [16:24] are unused */ 3642 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3643 NVIDIA_SET_SCRATCH0_BYTE2, 0); 3644 3645 /* 3646 * Bit 30 signals that the data is valid and hence that HDMI audio can 3647 * be enabled. 3648 */ 3649 if (format == 0) 3650 value &= ~NVIDIA_SCRATCH_VALID; 3651 else 3652 value |= NVIDIA_SCRATCH_VALID; 3653 3654 /* 3655 * Whenever the trigger bit is toggled, an interrupt is raised in the 3656 * HDMI codec. The HDMI driver will use that as trigger to update its 3657 * configuration. 3658 */ 3659 value ^= NVIDIA_SCRATCH_TRIGGER; 3660 3661 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3662 NVIDIA_SET_SCRATCH0_BYTE3, value); 3663 } 3664 3665 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, 3666 struct hda_codec *codec, 3667 unsigned int stream_tag, 3668 unsigned int format, 3669 struct snd_pcm_substream *substream) 3670 { 3671 int err; 3672 3673 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, 3674 format, substream); 3675 if (err < 0) 3676 return err; 3677 3678 /* notify the HDMI codec of the format change */ 3679 tegra_hdmi_set_format(codec, format); 3680 3681 return 0; 3682 } 3683 3684 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, 3685 struct hda_codec *codec, 3686 struct snd_pcm_substream *substream) 3687 { 3688 /* invalidate the format in the HDMI codec */ 3689 tegra_hdmi_set_format(codec, 0); 3690 3691 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); 3692 } 3693 3694 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) 3695 { 3696 struct hdmi_spec *spec = codec->spec; 3697 unsigned int i; 3698 3699 for (i = 0; i < spec->num_pins; i++) { 3700 struct hda_pcm *pcm = get_pcm_rec(spec, i); 3701 3702 if (pcm->pcm_type == type) 3703 return pcm; 3704 } 3705 3706 return NULL; 3707 } 3708 3709 static int tegra_hdmi_build_pcms(struct hda_codec *codec) 3710 { 3711 struct hda_pcm_stream *stream; 3712 struct hda_pcm *pcm; 3713 int err; 3714 3715 err = generic_hdmi_build_pcms(codec); 3716 if (err < 0) 3717 return err; 3718 3719 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); 3720 if (!pcm) 3721 return -ENODEV; 3722 3723 /* 3724 * Override ->prepare() and ->cleanup() operations to notify the HDMI 3725 * codec about format changes. 3726 */ 3727 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3728 stream->ops.prepare = tegra_hdmi_pcm_prepare; 3729 stream->ops.cleanup = tegra_hdmi_pcm_cleanup; 3730 3731 return 0; 3732 } 3733 3734 static int patch_tegra_hdmi(struct hda_codec *codec) 3735 { 3736 int err; 3737 3738 err = patch_generic_hdmi(codec); 3739 if (err) 3740 return err; 3741 3742 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; 3743 3744 return 0; 3745 } 3746 3747 /* 3748 * ATI/AMD-specific implementations 3749 */ 3750 3751 #define is_amdhdmi_rev3_or_later(codec) \ 3752 ((codec)->core.vendor_id == 0x1002aa01 && \ 3753 ((codec)->core.revision_id & 0xff00) >= 0x0300) 3754 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) 3755 3756 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ 3757 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 3758 #define ATI_VERB_SET_DOWNMIX_INFO 0x772 3759 #define ATI_VERB_SET_MULTICHANNEL_01 0x777 3760 #define ATI_VERB_SET_MULTICHANNEL_23 0x778 3761 #define ATI_VERB_SET_MULTICHANNEL_45 0x779 3762 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a 3763 #define ATI_VERB_SET_HBR_CONTROL 0x77c 3764 #define ATI_VERB_SET_MULTICHANNEL_1 0x785 3765 #define ATI_VERB_SET_MULTICHANNEL_3 0x786 3766 #define ATI_VERB_SET_MULTICHANNEL_5 0x787 3767 #define ATI_VERB_SET_MULTICHANNEL_7 0x788 3768 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 3769 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 3770 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 3771 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 3772 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 3773 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 3774 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a 3775 #define ATI_VERB_GET_HBR_CONTROL 0xf7c 3776 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 3777 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 3778 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 3779 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 3780 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 3781 3782 /* AMD specific HDA cvt verbs */ 3783 #define ATI_VERB_SET_RAMP_RATE 0x770 3784 #define ATI_VERB_GET_RAMP_RATE 0xf70 3785 3786 #define ATI_OUT_ENABLE 0x1 3787 3788 #define ATI_MULTICHANNEL_MODE_PAIRED 0 3789 #define ATI_MULTICHANNEL_MODE_SINGLE 1 3790 3791 #define ATI_HBR_CAPABLE 0x01 3792 #define ATI_HBR_ENABLE 0x10 3793 3794 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 3795 int dev_id, unsigned char *buf, int *eld_size) 3796 { 3797 WARN_ON(dev_id != 0); 3798 /* call hda_eld.c ATI/AMD-specific function */ 3799 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, 3800 is_amdhdmi_rev3_or_later(codec)); 3801 } 3802 3803 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, 3804 hda_nid_t pin_nid, int dev_id, int ca, 3805 int active_channels, int conn_type) 3806 { 3807 WARN_ON(dev_id != 0); 3808 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); 3809 } 3810 3811 static int atihdmi_paired_swap_fc_lfe(int pos) 3812 { 3813 /* 3814 * ATI/AMD have automatic FC/LFE swap built-in 3815 * when in pairwise mapping mode. 3816 */ 3817 3818 switch (pos) { 3819 /* see channel_allocations[].speakers[] */ 3820 case 2: return 3; 3821 case 3: return 2; 3822 default: break; 3823 } 3824 3825 return pos; 3826 } 3827 3828 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, 3829 int ca, int chs, unsigned char *map) 3830 { 3831 struct hdac_cea_channel_speaker_allocation *cap; 3832 int i, j; 3833 3834 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ 3835 3836 cap = snd_hdac_get_ch_alloc_from_ca(ca); 3837 for (i = 0; i < chs; ++i) { 3838 int mask = snd_hdac_chmap_to_spk_mask(map[i]); 3839 bool ok = false; 3840 bool companion_ok = false; 3841 3842 if (!mask) 3843 continue; 3844 3845 for (j = 0 + i % 2; j < 8; j += 2) { 3846 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); 3847 if (cap->speakers[chan_idx] == mask) { 3848 /* channel is in a supported position */ 3849 ok = true; 3850 3851 if (i % 2 == 0 && i + 1 < chs) { 3852 /* even channel, check the odd companion */ 3853 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); 3854 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); 3855 int comp_mask_act = cap->speakers[comp_chan_idx]; 3856 3857 if (comp_mask_req == comp_mask_act) 3858 companion_ok = true; 3859 else 3860 return -EINVAL; 3861 } 3862 break; 3863 } 3864 } 3865 3866 if (!ok) 3867 return -EINVAL; 3868 3869 if (companion_ok) 3870 i++; /* companion channel already checked */ 3871 } 3872 3873 return 0; 3874 } 3875 3876 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, 3877 hda_nid_t pin_nid, int hdmi_slot, int stream_channel) 3878 { 3879 struct hda_codec *codec = hdac_to_hda_codec(hdac); 3880 int verb; 3881 int ati_channel_setup = 0; 3882 3883 if (hdmi_slot > 7) 3884 return -EINVAL; 3885 3886 if (!has_amd_full_remap_support(codec)) { 3887 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); 3888 3889 /* In case this is an odd slot but without stream channel, do not 3890 * disable the slot since the corresponding even slot could have a 3891 * channel. In case neither have a channel, the slot pair will be 3892 * disabled when this function is called for the even slot. */ 3893 if (hdmi_slot % 2 != 0 && stream_channel == 0xf) 3894 return 0; 3895 3896 hdmi_slot -= hdmi_slot % 2; 3897 3898 if (stream_channel != 0xf) 3899 stream_channel -= stream_channel % 2; 3900 } 3901 3902 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; 3903 3904 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ 3905 3906 if (stream_channel != 0xf) 3907 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; 3908 3909 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); 3910 } 3911 3912 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, 3913 hda_nid_t pin_nid, int asp_slot) 3914 { 3915 struct hda_codec *codec = hdac_to_hda_codec(hdac); 3916 bool was_odd = false; 3917 int ati_asp_slot = asp_slot; 3918 int verb; 3919 int ati_channel_setup; 3920 3921 if (asp_slot > 7) 3922 return -EINVAL; 3923 3924 if (!has_amd_full_remap_support(codec)) { 3925 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); 3926 if (ati_asp_slot % 2 != 0) { 3927 ati_asp_slot -= 1; 3928 was_odd = true; 3929 } 3930 } 3931 3932 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; 3933 3934 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); 3935 3936 if (!(ati_channel_setup & ATI_OUT_ENABLE)) 3937 return 0xf; 3938 3939 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; 3940 } 3941 3942 static int atihdmi_paired_chmap_cea_alloc_validate_get_type( 3943 struct hdac_chmap *chmap, 3944 struct hdac_cea_channel_speaker_allocation *cap, 3945 int channels) 3946 { 3947 int c; 3948 3949 /* 3950 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so 3951 * we need to take that into account (a single channel may take 2 3952 * channel slots if we need to carry a silent channel next to it). 3953 * On Rev3+ AMD codecs this function is not used. 3954 */ 3955 int chanpairs = 0; 3956 3957 /* We only produce even-numbered channel count TLVs */ 3958 if ((channels % 2) != 0) 3959 return -1; 3960 3961 for (c = 0; c < 7; c += 2) { 3962 if (cap->speakers[c] || cap->speakers[c+1]) 3963 chanpairs++; 3964 } 3965 3966 if (chanpairs * 2 != channels) 3967 return -1; 3968 3969 return SNDRV_CTL_TLVT_CHMAP_PAIRED; 3970 } 3971 3972 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, 3973 struct hdac_cea_channel_speaker_allocation *cap, 3974 unsigned int *chmap, int channels) 3975 { 3976 /* produce paired maps for pre-rev3 ATI/AMD codecs */ 3977 int count = 0; 3978 int c; 3979 3980 for (c = 7; c >= 0; c--) { 3981 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); 3982 int spk = cap->speakers[chan]; 3983 if (!spk) { 3984 /* add N/A channel if the companion channel is occupied */ 3985 if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) 3986 chmap[count++] = SNDRV_CHMAP_NA; 3987 3988 continue; 3989 } 3990 3991 chmap[count++] = snd_hdac_spk_to_chmap(spk); 3992 } 3993 3994 WARN_ON(count != channels); 3995 } 3996 3997 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 3998 int dev_id, bool hbr) 3999 { 4000 int hbr_ctl, hbr_ctl_new; 4001 4002 WARN_ON(dev_id != 0); 4003 4004 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); 4005 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { 4006 if (hbr) 4007 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; 4008 else 4009 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; 4010 4011 codec_dbg(codec, 4012 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", 4013 pin_nid, 4014 hbr_ctl == hbr_ctl_new ? "" : "new-", 4015 hbr_ctl_new); 4016 4017 if (hbr_ctl != hbr_ctl_new) 4018 snd_hda_codec_write(codec, pin_nid, 0, 4019 ATI_VERB_SET_HBR_CONTROL, 4020 hbr_ctl_new); 4021 4022 } else if (hbr) 4023 return -EINVAL; 4024 4025 return 0; 4026 } 4027 4028 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 4029 hda_nid_t pin_nid, int dev_id, 4030 u32 stream_tag, int format) 4031 { 4032 if (is_amdhdmi_rev3_or_later(codec)) { 4033 int ramp_rate = 180; /* default as per AMD spec */ 4034 /* disable ramp-up/down for non-pcm as per AMD spec */ 4035 if (format & AC_FMT_TYPE_NON_PCM) 4036 ramp_rate = 0; 4037 4038 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); 4039 } 4040 4041 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 4042 stream_tag, format); 4043 } 4044 4045 4046 static int atihdmi_init(struct hda_codec *codec) 4047 { 4048 struct hdmi_spec *spec = codec->spec; 4049 int pin_idx, err; 4050 4051 err = generic_hdmi_init(codec); 4052 4053 if (err) 4054 return err; 4055 4056 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 4057 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 4058 4059 /* make sure downmix information in infoframe is zero */ 4060 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); 4061 4062 /* enable channel-wise remap mode if supported */ 4063 if (has_amd_full_remap_support(codec)) 4064 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 4065 ATI_VERB_SET_MULTICHANNEL_MODE, 4066 ATI_MULTICHANNEL_MODE_SINGLE); 4067 } 4068 codec->auto_runtime_pm = 1; 4069 4070 return 0; 4071 } 4072 4073 /* map from pin NID to port; port is 0-based */ 4074 /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */ 4075 static int atihdmi_pin2port(void *audio_ptr, int pin_nid) 4076 { 4077 return pin_nid / 2 - 1; 4078 } 4079 4080 /* reverse-map from port to pin NID: see above */ 4081 static int atihdmi_port2pin(struct hda_codec *codec, int port) 4082 { 4083 return port * 2 + 3; 4084 } 4085 4086 static const struct drm_audio_component_audio_ops atihdmi_audio_ops = { 4087 .pin2port = atihdmi_pin2port, 4088 .pin_eld_notify = generic_acomp_pin_eld_notify, 4089 .master_bind = generic_acomp_master_bind, 4090 .master_unbind = generic_acomp_master_unbind, 4091 }; 4092 4093 static int patch_atihdmi(struct hda_codec *codec) 4094 { 4095 struct hdmi_spec *spec; 4096 struct hdmi_spec_per_cvt *per_cvt; 4097 int err, cvt_idx; 4098 4099 err = patch_generic_hdmi(codec); 4100 4101 if (err) 4102 return err; 4103 4104 codec->patch_ops.init = atihdmi_init; 4105 4106 spec = codec->spec; 4107 4108 spec->ops.pin_get_eld = atihdmi_pin_get_eld; 4109 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; 4110 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; 4111 spec->ops.setup_stream = atihdmi_setup_stream; 4112 4113 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; 4114 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; 4115 4116 if (!has_amd_full_remap_support(codec)) { 4117 /* override to ATI/AMD-specific versions with pairwise mapping */ 4118 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4119 atihdmi_paired_chmap_cea_alloc_validate_get_type; 4120 spec->chmap.ops.cea_alloc_to_tlv_chmap = 4121 atihdmi_paired_cea_alloc_to_tlv_chmap; 4122 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; 4123 } 4124 4125 /* ATI/AMD converters do not advertise all of their capabilities */ 4126 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 4127 per_cvt = get_cvt(spec, cvt_idx); 4128 per_cvt->channels_max = max(per_cvt->channels_max, 8u); 4129 per_cvt->rates |= SUPPORTED_RATES; 4130 per_cvt->formats |= SUPPORTED_FORMATS; 4131 per_cvt->maxbps = max(per_cvt->maxbps, 24u); 4132 } 4133 4134 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); 4135 4136 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing 4137 * the link-down as is. Tell the core to allow it. 4138 */ 4139 codec->link_down_at_suspend = 1; 4140 4141 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin); 4142 4143 return 0; 4144 } 4145 4146 /* VIA HDMI Implementation */ 4147 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ 4148 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ 4149 4150 static int patch_via_hdmi(struct hda_codec *codec) 4151 { 4152 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); 4153 } 4154 4155 /* 4156 * patch entries 4157 */ 4158 static const struct hda_device_id snd_hda_id_hdmi[] = { 4159 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), 4160 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), 4161 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), 4162 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), 4163 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), 4164 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), 4165 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), 4166 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch), 4167 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4168 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4169 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x), 4170 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4171 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4172 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), 4173 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy), 4174 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy), 4175 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy), 4176 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy), 4177 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy), 4178 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy), 4179 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy), 4180 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy), 4181 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy), 4182 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy), 4183 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy), 4184 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy), 4185 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy), 4186 /* 17 is known to be absent */ 4187 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy), 4188 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy), 4189 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy), 4190 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy), 4191 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy), 4192 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), 4193 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), 4194 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), 4195 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), 4196 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi), 4197 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi), 4198 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), 4199 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), 4200 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), 4201 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), 4202 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), 4203 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), 4204 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), 4205 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi), 4206 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi), 4207 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), 4208 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi), 4209 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), 4210 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi), 4211 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi), 4212 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), 4213 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), 4214 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), 4215 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), 4216 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi), 4217 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi), 4218 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi), 4219 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi), 4220 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi), 4221 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), 4222 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi), 4223 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), 4224 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi), 4225 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), 4226 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), 4227 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi), 4228 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi), 4229 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi), 4230 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi), 4231 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi), 4232 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi), 4233 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi), 4234 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi), 4235 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), 4236 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), 4237 HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi), 4238 HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi), 4239 HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi), 4240 HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi), 4241 HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi), 4242 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), 4243 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), 4244 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), 4245 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), 4246 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), 4247 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), 4248 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4249 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), 4250 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), 4251 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), 4252 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), 4253 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4254 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), 4255 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), 4256 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), 4257 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), 4258 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), 4259 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), 4260 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), 4261 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), 4262 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), 4263 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi), 4264 HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi), 4265 HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi), 4266 HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi), 4267 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), 4268 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), 4269 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), 4270 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), 4271 /* special ID for generic HDMI */ 4272 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), 4273 {} /* terminator */ 4274 }; 4275 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); 4276 4277 MODULE_LICENSE("GPL"); 4278 MODULE_DESCRIPTION("HDMI HD-audio codec"); 4279 MODULE_ALIAS("snd-hda-codec-intelhdmi"); 4280 MODULE_ALIAS("snd-hda-codec-nvhdmi"); 4281 MODULE_ALIAS("snd-hda-codec-atihdmi"); 4282 4283 static struct hda_codec_driver hdmi_driver = { 4284 .id = snd_hda_id_hdmi, 4285 }; 4286 4287 module_hda_codec_driver(hdmi_driver); 4288