1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs 5 * 6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. 7 * Copyright (c) 2006 ATI Technologies Inc. 8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved. 9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com> 10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> 11 * 12 * Authors: 13 * Wu Fengguang <wfg@linux.intel.com> 14 * 15 * Maintained by: 16 * Wu Fengguang <wfg@linux.intel.com> 17 */ 18 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/pci.h> 22 #include <linux/slab.h> 23 #include <linux/module.h> 24 #include <linux/pm_runtime.h> 25 #include <sound/core.h> 26 #include <sound/jack.h> 27 #include <sound/asoundef.h> 28 #include <sound/tlv.h> 29 #include <sound/hdaudio.h> 30 #include <sound/hda_i915.h> 31 #include <sound/hda_chmap.h> 32 #include <sound/hda_codec.h> 33 #include "hda_local.h" 34 #include "hda_jack.h" 35 #include "hda_controller.h" 36 37 static bool static_hdmi_pcm; 38 module_param(static_hdmi_pcm, bool, 0644); 39 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); 40 41 static bool enable_acomp = true; 42 module_param(enable_acomp, bool, 0444); 43 MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)"); 44 45 static bool enable_silent_stream = 46 IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM); 47 module_param(enable_silent_stream, bool, 0644); 48 MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices"); 49 50 static bool enable_all_pins; 51 module_param(enable_all_pins, bool, 0444); 52 MODULE_PARM_DESC(enable_all_pins, "Forcibly enable all pins"); 53 54 struct hdmi_spec_per_cvt { 55 hda_nid_t cvt_nid; 56 int assigned; 57 unsigned int channels_min; 58 unsigned int channels_max; 59 u32 rates; 60 u64 formats; 61 unsigned int maxbps; 62 }; 63 64 /* max. connections to a widget */ 65 #define HDA_MAX_CONNECTIONS 32 66 67 struct hdmi_spec_per_pin { 68 hda_nid_t pin_nid; 69 int dev_id; 70 /* pin idx, different device entries on the same pin use the same idx */ 71 int pin_nid_idx; 72 int num_mux_nids; 73 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; 74 int mux_idx; 75 hda_nid_t cvt_nid; 76 77 struct hda_codec *codec; 78 struct hdmi_eld sink_eld; 79 struct mutex lock; 80 struct delayed_work work; 81 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ 82 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ 83 int repoll_count; 84 bool setup; /* the stream has been set up by prepare callback */ 85 bool silent_stream; 86 int channels; /* current number of channels */ 87 bool non_pcm; 88 bool chmap_set; /* channel-map override by ALSA API? */ 89 unsigned char chmap[8]; /* ALSA API channel-map */ 90 #ifdef CONFIG_SND_PROC_FS 91 struct snd_info_entry *proc_entry; 92 #endif 93 }; 94 95 /* operations used by generic code that can be overridden by patches */ 96 struct hdmi_ops { 97 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, 98 int dev_id, unsigned char *buf, int *eld_size); 99 100 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, 101 int dev_id, 102 int ca, int active_channels, int conn_type); 103 104 /* enable/disable HBR (HD passthrough) */ 105 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, 106 int dev_id, bool hbr); 107 108 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, 109 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 110 int format); 111 112 void (*pin_cvt_fixup)(struct hda_codec *codec, 113 struct hdmi_spec_per_pin *per_pin, 114 hda_nid_t cvt_nid); 115 }; 116 117 struct hdmi_pcm { 118 struct hda_pcm *pcm; 119 struct snd_jack *jack; 120 struct snd_kcontrol *eld_ctl; 121 }; 122 123 enum { 124 SILENT_STREAM_OFF = 0, 125 SILENT_STREAM_KAE, /* use standard HDA Keep-Alive */ 126 SILENT_STREAM_I915, /* Intel i915 extension */ 127 }; 128 129 struct hdmi_spec { 130 struct hda_codec *codec; 131 int num_cvts; 132 struct snd_array cvts; /* struct hdmi_spec_per_cvt */ 133 hda_nid_t cvt_nids[4]; /* only for haswell fix */ 134 135 /* 136 * num_pins is the number of virtual pins 137 * for example, there are 3 pins, and each pin 138 * has 4 device entries, then the num_pins is 12 139 */ 140 int num_pins; 141 /* 142 * num_nids is the number of real pins 143 * In the above example, num_nids is 3 144 */ 145 int num_nids; 146 /* 147 * dev_num is the number of device entries 148 * on each pin. 149 * In the above example, dev_num is 4 150 */ 151 int dev_num; 152 struct snd_array pins; /* struct hdmi_spec_per_pin */ 153 struct hdmi_pcm pcm_rec[16]; 154 struct mutex pcm_lock; 155 struct mutex bind_lock; /* for audio component binding */ 156 /* pcm_bitmap means which pcms have been assigned to pins*/ 157 unsigned long pcm_bitmap; 158 int pcm_used; /* counter of pcm_rec[] */ 159 /* bitmap shows whether the pcm is opened in user space 160 * bit 0 means the first playback PCM (PCM3); 161 * bit 1 means the second playback PCM, and so on. 162 */ 163 unsigned long pcm_in_use; 164 165 struct hdmi_eld temp_eld; 166 struct hdmi_ops ops; 167 168 bool dyn_pin_out; 169 bool dyn_pcm_assign; 170 bool dyn_pcm_no_legacy; 171 /* hdmi interrupt trigger control flag for Nvidia codec */ 172 bool hdmi_intr_trig_ctrl; 173 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */ 174 /* 175 * Non-generic VIA/NVIDIA specific 176 */ 177 struct hda_multi_out multiout; 178 struct hda_pcm_stream pcm_playback; 179 180 bool use_acomp_notifier; /* use eld_notify callback for hotplug */ 181 bool acomp_registered; /* audio component registered in this driver */ 182 bool force_connect; /* force connectivity */ 183 struct drm_audio_component_audio_ops drm_audio_ops; 184 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */ 185 186 struct hdac_chmap chmap; 187 hda_nid_t vendor_nid; 188 const int *port_map; 189 int port_num; 190 int silent_stream_type; 191 }; 192 193 #ifdef CONFIG_SND_HDA_COMPONENT 194 static inline bool codec_has_acomp(struct hda_codec *codec) 195 { 196 struct hdmi_spec *spec = codec->spec; 197 return spec->use_acomp_notifier; 198 } 199 #else 200 #define codec_has_acomp(codec) false 201 #endif 202 203 struct hdmi_audio_infoframe { 204 u8 type; /* 0x84 */ 205 u8 ver; /* 0x01 */ 206 u8 len; /* 0x0a */ 207 208 u8 checksum; 209 210 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ 211 u8 SS01_SF24; 212 u8 CXT04; 213 u8 CA; 214 u8 LFEPBL01_LSV36_DM_INH7; 215 }; 216 217 struct dp_audio_infoframe { 218 u8 type; /* 0x84 */ 219 u8 len; /* 0x1b */ 220 u8 ver; /* 0x11 << 2 */ 221 222 u8 CC02_CT47; /* match with HDMI infoframe from this on */ 223 u8 SS01_SF24; 224 u8 CXT04; 225 u8 CA; 226 u8 LFEPBL01_LSV36_DM_INH7; 227 }; 228 229 union audio_infoframe { 230 struct hdmi_audio_infoframe hdmi; 231 struct dp_audio_infoframe dp; 232 u8 bytes[0]; 233 }; 234 235 /* 236 * HDMI routines 237 */ 238 239 #define get_pin(spec, idx) \ 240 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) 241 #define get_cvt(spec, idx) \ 242 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) 243 /* obtain hdmi_pcm object assigned to idx */ 244 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) 245 /* obtain hda_pcm object assigned to idx */ 246 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) 247 248 static int pin_id_to_pin_index(struct hda_codec *codec, 249 hda_nid_t pin_nid, int dev_id) 250 { 251 struct hdmi_spec *spec = codec->spec; 252 int pin_idx; 253 struct hdmi_spec_per_pin *per_pin; 254 255 /* 256 * (dev_id == -1) means it is NON-MST pin 257 * return the first virtual pin on this port 258 */ 259 if (dev_id == -1) 260 dev_id = 0; 261 262 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 263 per_pin = get_pin(spec, pin_idx); 264 if ((per_pin->pin_nid == pin_nid) && 265 (per_pin->dev_id == dev_id)) 266 return pin_idx; 267 } 268 269 codec_warn(codec, "HDMI: pin NID 0x%x not registered\n", pin_nid); 270 return -EINVAL; 271 } 272 273 static int hinfo_to_pcm_index(struct hda_codec *codec, 274 struct hda_pcm_stream *hinfo) 275 { 276 struct hdmi_spec *spec = codec->spec; 277 int pcm_idx; 278 279 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) 280 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) 281 return pcm_idx; 282 283 codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo); 284 return -EINVAL; 285 } 286 287 static int hinfo_to_pin_index(struct hda_codec *codec, 288 struct hda_pcm_stream *hinfo) 289 { 290 struct hdmi_spec *spec = codec->spec; 291 struct hdmi_spec_per_pin *per_pin; 292 int pin_idx; 293 294 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 295 per_pin = get_pin(spec, pin_idx); 296 if (per_pin->pcm && 297 per_pin->pcm->pcm->stream == hinfo) 298 return pin_idx; 299 } 300 301 codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo, 302 hinfo_to_pcm_index(codec, hinfo)); 303 return -EINVAL; 304 } 305 306 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, 307 int pcm_idx) 308 { 309 int i; 310 struct hdmi_spec_per_pin *per_pin; 311 312 for (i = 0; i < spec->num_pins; i++) { 313 per_pin = get_pin(spec, i); 314 if (per_pin->pcm_idx == pcm_idx) 315 return per_pin; 316 } 317 return NULL; 318 } 319 320 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) 321 { 322 struct hdmi_spec *spec = codec->spec; 323 int cvt_idx; 324 325 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) 326 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) 327 return cvt_idx; 328 329 codec_warn(codec, "HDMI: cvt NID 0x%x not registered\n", cvt_nid); 330 return -EINVAL; 331 } 332 333 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, 334 struct snd_ctl_elem_info *uinfo) 335 { 336 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 337 struct hdmi_spec *spec = codec->spec; 338 struct hdmi_spec_per_pin *per_pin; 339 struct hdmi_eld *eld; 340 int pcm_idx; 341 342 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 343 344 pcm_idx = kcontrol->private_value; 345 mutex_lock(&spec->pcm_lock); 346 per_pin = pcm_idx_to_pin(spec, pcm_idx); 347 if (!per_pin) { 348 /* no pin is bound to the pcm */ 349 uinfo->count = 0; 350 goto unlock; 351 } 352 eld = &per_pin->sink_eld; 353 uinfo->count = eld->eld_valid ? eld->eld_size : 0; 354 355 unlock: 356 mutex_unlock(&spec->pcm_lock); 357 return 0; 358 } 359 360 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, 361 struct snd_ctl_elem_value *ucontrol) 362 { 363 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 364 struct hdmi_spec *spec = codec->spec; 365 struct hdmi_spec_per_pin *per_pin; 366 struct hdmi_eld *eld; 367 int pcm_idx; 368 int err = 0; 369 370 pcm_idx = kcontrol->private_value; 371 mutex_lock(&spec->pcm_lock); 372 per_pin = pcm_idx_to_pin(spec, pcm_idx); 373 if (!per_pin) { 374 /* no pin is bound to the pcm */ 375 memset(ucontrol->value.bytes.data, 0, 376 ARRAY_SIZE(ucontrol->value.bytes.data)); 377 goto unlock; 378 } 379 380 eld = &per_pin->sink_eld; 381 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || 382 eld->eld_size > ELD_MAX_SIZE) { 383 snd_BUG(); 384 err = -EINVAL; 385 goto unlock; 386 } 387 388 memset(ucontrol->value.bytes.data, 0, 389 ARRAY_SIZE(ucontrol->value.bytes.data)); 390 if (eld->eld_valid) 391 memcpy(ucontrol->value.bytes.data, eld->eld_buffer, 392 eld->eld_size); 393 394 unlock: 395 mutex_unlock(&spec->pcm_lock); 396 return err; 397 } 398 399 static const struct snd_kcontrol_new eld_bytes_ctl = { 400 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE | 401 SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK, 402 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 403 .name = "ELD", 404 .info = hdmi_eld_ctl_info, 405 .get = hdmi_eld_ctl_get, 406 }; 407 408 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, 409 int device) 410 { 411 struct snd_kcontrol *kctl; 412 struct hdmi_spec *spec = codec->spec; 413 int err; 414 415 kctl = snd_ctl_new1(&eld_bytes_ctl, codec); 416 if (!kctl) 417 return -ENOMEM; 418 kctl->private_value = pcm_idx; 419 kctl->id.device = device; 420 421 /* no pin nid is associated with the kctl now 422 * tbd: associate pin nid to eld ctl later 423 */ 424 err = snd_hda_ctl_add(codec, 0, kctl); 425 if (err < 0) 426 return err; 427 428 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; 429 return 0; 430 } 431 432 #ifdef BE_PARANOID 433 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 434 int *packet_index, int *byte_index) 435 { 436 int val; 437 438 val = snd_hda_codec_read(codec, pin_nid, 0, 439 AC_VERB_GET_HDMI_DIP_INDEX, 0); 440 441 *packet_index = val >> 5; 442 *byte_index = val & 0x1f; 443 } 444 #endif 445 446 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 447 int packet_index, int byte_index) 448 { 449 int val; 450 451 val = (packet_index << 5) | (byte_index & 0x1f); 452 453 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); 454 } 455 456 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, 457 unsigned char val) 458 { 459 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); 460 } 461 462 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) 463 { 464 struct hdmi_spec *spec = codec->spec; 465 int pin_out; 466 467 /* Unmute */ 468 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 469 snd_hda_codec_write(codec, pin_nid, 0, 470 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); 471 472 if (spec->dyn_pin_out) 473 /* Disable pin out until stream is active */ 474 pin_out = 0; 475 else 476 /* Enable pin out: some machines with GM965 gets broken output 477 * when the pin is disabled or changed while using with HDMI 478 */ 479 pin_out = PIN_OUT; 480 481 snd_hda_codec_write(codec, pin_nid, 0, 482 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); 483 } 484 485 /* 486 * ELD proc files 487 */ 488 489 #ifdef CONFIG_SND_PROC_FS 490 static void print_eld_info(struct snd_info_entry *entry, 491 struct snd_info_buffer *buffer) 492 { 493 struct hdmi_spec_per_pin *per_pin = entry->private_data; 494 495 mutex_lock(&per_pin->lock); 496 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer); 497 mutex_unlock(&per_pin->lock); 498 } 499 500 static void write_eld_info(struct snd_info_entry *entry, 501 struct snd_info_buffer *buffer) 502 { 503 struct hdmi_spec_per_pin *per_pin = entry->private_data; 504 505 mutex_lock(&per_pin->lock); 506 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); 507 mutex_unlock(&per_pin->lock); 508 } 509 510 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) 511 { 512 char name[32]; 513 struct hda_codec *codec = per_pin->codec; 514 struct snd_info_entry *entry; 515 int err; 516 517 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); 518 err = snd_card_proc_new(codec->card, name, &entry); 519 if (err < 0) 520 return err; 521 522 snd_info_set_text_ops(entry, per_pin, print_eld_info); 523 entry->c.text.write = write_eld_info; 524 entry->mode |= 0200; 525 per_pin->proc_entry = entry; 526 527 return 0; 528 } 529 530 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 531 { 532 if (!per_pin->codec->bus->shutdown) { 533 snd_info_free_entry(per_pin->proc_entry); 534 per_pin->proc_entry = NULL; 535 } 536 } 537 #else 538 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, 539 int index) 540 { 541 return 0; 542 } 543 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 544 { 545 } 546 #endif 547 548 /* 549 * Audio InfoFrame routines 550 */ 551 552 /* 553 * Enable Audio InfoFrame Transmission 554 */ 555 static void hdmi_start_infoframe_trans(struct hda_codec *codec, 556 hda_nid_t pin_nid) 557 { 558 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 559 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 560 AC_DIPXMIT_BEST); 561 } 562 563 /* 564 * Disable Audio InfoFrame Transmission 565 */ 566 static void hdmi_stop_infoframe_trans(struct hda_codec *codec, 567 hda_nid_t pin_nid) 568 { 569 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 570 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 571 AC_DIPXMIT_DISABLE); 572 } 573 574 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) 575 { 576 #ifdef CONFIG_SND_DEBUG_VERBOSE 577 int i; 578 int size; 579 580 size = snd_hdmi_get_eld_size(codec, pin_nid); 581 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); 582 583 for (i = 0; i < 8; i++) { 584 size = snd_hda_codec_read(codec, pin_nid, 0, 585 AC_VERB_GET_HDMI_DIP_SIZE, i); 586 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); 587 } 588 #endif 589 } 590 591 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) 592 { 593 #ifdef BE_PARANOID 594 int i, j; 595 int size; 596 int pi, bi; 597 for (i = 0; i < 8; i++) { 598 size = snd_hda_codec_read(codec, pin_nid, 0, 599 AC_VERB_GET_HDMI_DIP_SIZE, i); 600 if (size == 0) 601 continue; 602 603 hdmi_set_dip_index(codec, pin_nid, i, 0x0); 604 for (j = 1; j < 1000; j++) { 605 hdmi_write_dip_byte(codec, pin_nid, 0x0); 606 hdmi_get_dip_index(codec, pin_nid, &pi, &bi); 607 if (pi != i) 608 codec_dbg(codec, "dip index %d: %d != %d\n", 609 bi, pi, i); 610 if (bi == 0) /* byte index wrapped around */ 611 break; 612 } 613 codec_dbg(codec, 614 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", 615 i, size, j); 616 } 617 #endif 618 } 619 620 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) 621 { 622 u8 *bytes = (u8 *)hdmi_ai; 623 u8 sum = 0; 624 int i; 625 626 hdmi_ai->checksum = 0; 627 628 for (i = 0; i < sizeof(*hdmi_ai); i++) 629 sum += bytes[i]; 630 631 hdmi_ai->checksum = -sum; 632 } 633 634 static void hdmi_fill_audio_infoframe(struct hda_codec *codec, 635 hda_nid_t pin_nid, 636 u8 *dip, int size) 637 { 638 int i; 639 640 hdmi_debug_dip_size(codec, pin_nid); 641 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ 642 643 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 644 for (i = 0; i < size; i++) 645 hdmi_write_dip_byte(codec, pin_nid, dip[i]); 646 } 647 648 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, 649 u8 *dip, int size) 650 { 651 u8 val; 652 int i; 653 654 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 655 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) 656 != AC_DIPXMIT_BEST) 657 return false; 658 659 for (i = 0; i < size; i++) { 660 val = snd_hda_codec_read(codec, pin_nid, 0, 661 AC_VERB_GET_HDMI_DIP_DATA, 0); 662 if (val != dip[i]) 663 return false; 664 } 665 666 return true; 667 } 668 669 static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 670 int dev_id, unsigned char *buf, int *eld_size) 671 { 672 snd_hda_set_dev_select(codec, nid, dev_id); 673 674 return snd_hdmi_get_eld(codec, nid, buf, eld_size); 675 } 676 677 static void hdmi_pin_setup_infoframe(struct hda_codec *codec, 678 hda_nid_t pin_nid, int dev_id, 679 int ca, int active_channels, 680 int conn_type) 681 { 682 union audio_infoframe ai; 683 684 memset(&ai, 0, sizeof(ai)); 685 if (conn_type == 0) { /* HDMI */ 686 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; 687 688 hdmi_ai->type = 0x84; 689 hdmi_ai->ver = 0x01; 690 hdmi_ai->len = 0x0a; 691 hdmi_ai->CC02_CT47 = active_channels - 1; 692 hdmi_ai->CA = ca; 693 hdmi_checksum_audio_infoframe(hdmi_ai); 694 } else if (conn_type == 1) { /* DisplayPort */ 695 struct dp_audio_infoframe *dp_ai = &ai.dp; 696 697 dp_ai->type = 0x84; 698 dp_ai->len = 0x1b; 699 dp_ai->ver = 0x11 << 2; 700 dp_ai->CC02_CT47 = active_channels - 1; 701 dp_ai->CA = ca; 702 } else { 703 codec_dbg(codec, "HDMI: unknown connection type at pin NID 0x%x\n", pin_nid); 704 return; 705 } 706 707 snd_hda_set_dev_select(codec, pin_nid, dev_id); 708 709 /* 710 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or 711 * sizeof(*dp_ai) to avoid partial match/update problems when 712 * the user switches between HDMI/DP monitors. 713 */ 714 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, 715 sizeof(ai))) { 716 codec_dbg(codec, "%s: pin NID=0x%x channels=%d ca=0x%02x\n", 717 __func__, pin_nid, active_channels, ca); 718 hdmi_stop_infoframe_trans(codec, pin_nid); 719 hdmi_fill_audio_infoframe(codec, pin_nid, 720 ai.bytes, sizeof(ai)); 721 hdmi_start_infoframe_trans(codec, pin_nid); 722 } 723 } 724 725 static void hdmi_setup_audio_infoframe(struct hda_codec *codec, 726 struct hdmi_spec_per_pin *per_pin, 727 bool non_pcm) 728 { 729 struct hdmi_spec *spec = codec->spec; 730 struct hdac_chmap *chmap = &spec->chmap; 731 hda_nid_t pin_nid = per_pin->pin_nid; 732 int dev_id = per_pin->dev_id; 733 int channels = per_pin->channels; 734 int active_channels; 735 struct hdmi_eld *eld; 736 int ca; 737 738 if (!channels) 739 return; 740 741 snd_hda_set_dev_select(codec, pin_nid, dev_id); 742 743 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ 744 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 745 snd_hda_codec_write(codec, pin_nid, 0, 746 AC_VERB_SET_AMP_GAIN_MUTE, 747 AMP_OUT_UNMUTE); 748 749 eld = &per_pin->sink_eld; 750 751 ca = snd_hdac_channel_allocation(&codec->core, 752 eld->info.spk_alloc, channels, 753 per_pin->chmap_set, non_pcm, per_pin->chmap); 754 755 active_channels = snd_hdac_get_active_channels(ca); 756 757 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, 758 active_channels); 759 760 /* 761 * always configure channel mapping, it may have been changed by the 762 * user in the meantime 763 */ 764 snd_hdac_setup_channel_mapping(&spec->chmap, 765 pin_nid, non_pcm, ca, channels, 766 per_pin->chmap, per_pin->chmap_set); 767 768 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id, 769 ca, active_channels, eld->info.conn_type); 770 771 per_pin->non_pcm = non_pcm; 772 } 773 774 /* 775 * Unsolicited events 776 */ 777 778 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); 779 780 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, 781 int dev_id) 782 { 783 struct hdmi_spec *spec = codec->spec; 784 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); 785 786 if (pin_idx < 0) 787 return; 788 mutex_lock(&spec->pcm_lock); 789 hdmi_present_sense(get_pin(spec, pin_idx), 1); 790 mutex_unlock(&spec->pcm_lock); 791 } 792 793 static void jack_callback(struct hda_codec *codec, 794 struct hda_jack_callback *jack) 795 { 796 /* stop polling when notification is enabled */ 797 if (codec_has_acomp(codec)) 798 return; 799 800 check_presence_and_report(codec, jack->nid, jack->dev_id); 801 } 802 803 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res, 804 struct hda_jack_tbl *jack) 805 { 806 jack->jack_dirty = 1; 807 808 codec_dbg(codec, 809 "HDMI hot plug event: Codec=%d NID=0x%x Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", 810 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA), 811 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); 812 813 check_presence_and_report(codec, jack->nid, jack->dev_id); 814 } 815 816 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) 817 { 818 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 819 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 820 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); 821 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); 822 823 codec_info(codec, 824 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", 825 codec->addr, 826 tag, 827 subtag, 828 cp_state, 829 cp_ready); 830 831 /* TODO */ 832 if (cp_state) { 833 ; 834 } 835 if (cp_ready) { 836 ; 837 } 838 } 839 840 841 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) 842 { 843 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 844 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 845 struct hda_jack_tbl *jack; 846 847 if (codec_has_acomp(codec)) 848 return; 849 850 if (codec->dp_mst) { 851 int dev_entry = 852 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 853 854 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry); 855 } else { 856 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0); 857 } 858 859 if (!jack) { 860 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); 861 return; 862 } 863 864 if (subtag == 0) 865 hdmi_intrinsic_event(codec, res, jack); 866 else 867 hdmi_non_intrinsic_event(codec, res); 868 } 869 870 static void haswell_verify_D0(struct hda_codec *codec, 871 hda_nid_t cvt_nid, hda_nid_t nid) 872 { 873 int pwr; 874 875 /* For Haswell, the converter 1/2 may keep in D3 state after bootup, 876 * thus pins could only choose converter 0 for use. Make sure the 877 * converters are in correct power state */ 878 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) 879 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); 880 881 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { 882 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, 883 AC_PWRST_D0); 884 msleep(40); 885 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); 886 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; 887 codec_dbg(codec, "Haswell HDMI audio: Power for NID 0x%x is now D%d\n", nid, pwr); 888 } 889 } 890 891 /* 892 * Callbacks 893 */ 894 895 /* HBR should be Non-PCM, 8 channels */ 896 #define is_hbr_format(format) \ 897 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) 898 899 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 900 int dev_id, bool hbr) 901 { 902 int pinctl, new_pinctl; 903 904 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { 905 snd_hda_set_dev_select(codec, pin_nid, dev_id); 906 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 907 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 908 909 if (pinctl < 0) 910 return hbr ? -EINVAL : 0; 911 912 new_pinctl = pinctl & ~AC_PINCTL_EPT; 913 if (hbr) 914 new_pinctl |= AC_PINCTL_EPT_HBR; 915 else 916 new_pinctl |= AC_PINCTL_EPT_NATIVE; 917 918 codec_dbg(codec, 919 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", 920 pin_nid, 921 pinctl == new_pinctl ? "" : "new-", 922 new_pinctl); 923 924 if (pinctl != new_pinctl) 925 snd_hda_codec_write(codec, pin_nid, 0, 926 AC_VERB_SET_PIN_WIDGET_CONTROL, 927 new_pinctl); 928 } else if (hbr) 929 return -EINVAL; 930 931 return 0; 932 } 933 934 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 935 hda_nid_t pin_nid, int dev_id, 936 u32 stream_tag, int format) 937 { 938 struct hdmi_spec *spec = codec->spec; 939 unsigned int param; 940 int err; 941 942 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id, 943 is_hbr_format(format)); 944 945 if (err) { 946 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); 947 return err; 948 } 949 950 if (spec->intel_hsw_fixup) { 951 952 /* 953 * on recent platforms IEC Coding Type is required for HBR 954 * support, read current Digital Converter settings and set 955 * ICT bitfield if needed. 956 */ 957 param = snd_hda_codec_read(codec, cvt_nid, 0, 958 AC_VERB_GET_DIGI_CONVERT_1, 0); 959 960 param = (param >> 16) & ~(AC_DIG3_ICT); 961 962 /* on recent platforms ICT mode is required for HBR support */ 963 if (is_hbr_format(format)) 964 param |= 0x1; 965 966 snd_hda_codec_write(codec, cvt_nid, 0, 967 AC_VERB_SET_DIGI_CONVERT_3, param); 968 } 969 970 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); 971 return 0; 972 } 973 974 /* Try to find an available converter 975 * If pin_idx is less then zero, just try to find an available converter. 976 * Otherwise, try to find an available converter and get the cvt mux index 977 * of the pin. 978 */ 979 static int hdmi_choose_cvt(struct hda_codec *codec, 980 int pin_idx, int *cvt_id) 981 { 982 struct hdmi_spec *spec = codec->spec; 983 struct hdmi_spec_per_pin *per_pin; 984 struct hdmi_spec_per_cvt *per_cvt = NULL; 985 int cvt_idx, mux_idx = 0; 986 987 /* pin_idx < 0 means no pin will be bound to the converter */ 988 if (pin_idx < 0) 989 per_pin = NULL; 990 else 991 per_pin = get_pin(spec, pin_idx); 992 993 if (per_pin && per_pin->silent_stream) { 994 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid); 995 if (cvt_id) 996 *cvt_id = cvt_idx; 997 return 0; 998 } 999 1000 /* Dynamically assign converter to stream */ 1001 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1002 per_cvt = get_cvt(spec, cvt_idx); 1003 1004 /* Must not already be assigned */ 1005 if (per_cvt->assigned) 1006 continue; 1007 if (per_pin == NULL) 1008 break; 1009 /* Must be in pin's mux's list of converters */ 1010 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1011 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) 1012 break; 1013 /* Not in mux list */ 1014 if (mux_idx == per_pin->num_mux_nids) 1015 continue; 1016 break; 1017 } 1018 1019 /* No free converters */ 1020 if (cvt_idx == spec->num_cvts) 1021 return -EBUSY; 1022 1023 if (per_pin != NULL) 1024 per_pin->mux_idx = mux_idx; 1025 1026 if (cvt_id) 1027 *cvt_id = cvt_idx; 1028 1029 return 0; 1030 } 1031 1032 /* Assure the pin select the right convetor */ 1033 static void intel_verify_pin_cvt_connect(struct hda_codec *codec, 1034 struct hdmi_spec_per_pin *per_pin) 1035 { 1036 hda_nid_t pin_nid = per_pin->pin_nid; 1037 int mux_idx, curr; 1038 1039 mux_idx = per_pin->mux_idx; 1040 curr = snd_hda_codec_read(codec, pin_nid, 0, 1041 AC_VERB_GET_CONNECT_SEL, 0); 1042 if (curr != mux_idx) 1043 snd_hda_codec_write_cache(codec, pin_nid, 0, 1044 AC_VERB_SET_CONNECT_SEL, 1045 mux_idx); 1046 } 1047 1048 /* get the mux index for the converter of the pins 1049 * converter's mux index is the same for all pins on Intel platform 1050 */ 1051 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, 1052 hda_nid_t cvt_nid) 1053 { 1054 int i; 1055 1056 for (i = 0; i < spec->num_cvts; i++) 1057 if (spec->cvt_nids[i] == cvt_nid) 1058 return i; 1059 return -EINVAL; 1060 } 1061 1062 /* Intel HDMI workaround to fix audio routing issue: 1063 * For some Intel display codecs, pins share the same connection list. 1064 * So a conveter can be selected by multiple pins and playback on any of these 1065 * pins will generate sound on the external display, because audio flows from 1066 * the same converter to the display pipeline. Also muting one pin may make 1067 * other pins have no sound output. 1068 * So this function assures that an assigned converter for a pin is not selected 1069 * by any other pins. 1070 */ 1071 static void intel_not_share_assigned_cvt(struct hda_codec *codec, 1072 hda_nid_t pin_nid, 1073 int dev_id, int mux_idx) 1074 { 1075 struct hdmi_spec *spec = codec->spec; 1076 hda_nid_t nid; 1077 int cvt_idx, curr; 1078 struct hdmi_spec_per_cvt *per_cvt; 1079 struct hdmi_spec_per_pin *per_pin; 1080 int pin_idx; 1081 1082 /* configure the pins connections */ 1083 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 1084 int dev_id_saved; 1085 int dev_num; 1086 1087 per_pin = get_pin(spec, pin_idx); 1088 /* 1089 * pin not connected to monitor 1090 * no need to operate on it 1091 */ 1092 if (!per_pin->pcm) 1093 continue; 1094 1095 if ((per_pin->pin_nid == pin_nid) && 1096 (per_pin->dev_id == dev_id)) 1097 continue; 1098 1099 /* 1100 * if per_pin->dev_id >= dev_num, 1101 * snd_hda_get_dev_select() will fail, 1102 * and the following operation is unpredictable. 1103 * So skip this situation. 1104 */ 1105 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; 1106 if (per_pin->dev_id >= dev_num) 1107 continue; 1108 1109 nid = per_pin->pin_nid; 1110 1111 /* 1112 * Calling this function should not impact 1113 * on the device entry selection 1114 * So let's save the dev id for each pin, 1115 * and restore it when return 1116 */ 1117 dev_id_saved = snd_hda_get_dev_select(codec, nid); 1118 snd_hda_set_dev_select(codec, nid, per_pin->dev_id); 1119 curr = snd_hda_codec_read(codec, nid, 0, 1120 AC_VERB_GET_CONNECT_SEL, 0); 1121 if (curr != mux_idx) { 1122 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1123 continue; 1124 } 1125 1126 1127 /* choose an unassigned converter. The conveters in the 1128 * connection list are in the same order as in the codec. 1129 */ 1130 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1131 per_cvt = get_cvt(spec, cvt_idx); 1132 if (!per_cvt->assigned) { 1133 codec_dbg(codec, 1134 "choose cvt %d for pin NID 0x%x\n", 1135 cvt_idx, nid); 1136 snd_hda_codec_write_cache(codec, nid, 0, 1137 AC_VERB_SET_CONNECT_SEL, 1138 cvt_idx); 1139 break; 1140 } 1141 } 1142 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1143 } 1144 } 1145 1146 /* A wrapper of intel_not_share_asigned_cvt() */ 1147 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, 1148 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) 1149 { 1150 int mux_idx; 1151 struct hdmi_spec *spec = codec->spec; 1152 1153 /* On Intel platform, the mapping of converter nid to 1154 * mux index of the pins are always the same. 1155 * The pin nid may be 0, this means all pins will not 1156 * share the converter. 1157 */ 1158 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); 1159 if (mux_idx >= 0) 1160 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); 1161 } 1162 1163 /* skeleton caller of pin_cvt_fixup ops */ 1164 static void pin_cvt_fixup(struct hda_codec *codec, 1165 struct hdmi_spec_per_pin *per_pin, 1166 hda_nid_t cvt_nid) 1167 { 1168 struct hdmi_spec *spec = codec->spec; 1169 1170 if (spec->ops.pin_cvt_fixup) 1171 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); 1172 } 1173 1174 /* called in hdmi_pcm_open when no pin is assigned to the PCM 1175 * in dyn_pcm_assign mode. 1176 */ 1177 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, 1178 struct hda_codec *codec, 1179 struct snd_pcm_substream *substream) 1180 { 1181 struct hdmi_spec *spec = codec->spec; 1182 struct snd_pcm_runtime *runtime = substream->runtime; 1183 int cvt_idx, pcm_idx; 1184 struct hdmi_spec_per_cvt *per_cvt = NULL; 1185 int err; 1186 1187 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1188 if (pcm_idx < 0) 1189 return -EINVAL; 1190 1191 err = hdmi_choose_cvt(codec, -1, &cvt_idx); 1192 if (err) 1193 return err; 1194 1195 per_cvt = get_cvt(spec, cvt_idx); 1196 per_cvt->assigned = 1; 1197 hinfo->nid = per_cvt->cvt_nid; 1198 1199 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); 1200 1201 set_bit(pcm_idx, &spec->pcm_in_use); 1202 /* todo: setup spdif ctls assign */ 1203 1204 /* Initially set the converter's capabilities */ 1205 hinfo->channels_min = per_cvt->channels_min; 1206 hinfo->channels_max = per_cvt->channels_max; 1207 hinfo->rates = per_cvt->rates; 1208 hinfo->formats = per_cvt->formats; 1209 hinfo->maxbps = per_cvt->maxbps; 1210 1211 /* Store the updated parameters */ 1212 runtime->hw.channels_min = hinfo->channels_min; 1213 runtime->hw.channels_max = hinfo->channels_max; 1214 runtime->hw.formats = hinfo->formats; 1215 runtime->hw.rates = hinfo->rates; 1216 1217 snd_pcm_hw_constraint_step(substream->runtime, 0, 1218 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1219 return 0; 1220 } 1221 1222 /* 1223 * HDA PCM callbacks 1224 */ 1225 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, 1226 struct hda_codec *codec, 1227 struct snd_pcm_substream *substream) 1228 { 1229 struct hdmi_spec *spec = codec->spec; 1230 struct snd_pcm_runtime *runtime = substream->runtime; 1231 int pin_idx, cvt_idx, pcm_idx; 1232 struct hdmi_spec_per_pin *per_pin; 1233 struct hdmi_eld *eld; 1234 struct hdmi_spec_per_cvt *per_cvt = NULL; 1235 int err; 1236 1237 /* Validate hinfo */ 1238 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1239 if (pcm_idx < 0) 1240 return -EINVAL; 1241 1242 mutex_lock(&spec->pcm_lock); 1243 pin_idx = hinfo_to_pin_index(codec, hinfo); 1244 if (!spec->dyn_pcm_assign) { 1245 if (snd_BUG_ON(pin_idx < 0)) { 1246 err = -EINVAL; 1247 goto unlock; 1248 } 1249 } else { 1250 /* no pin is assigned to the PCM 1251 * PA need pcm open successfully when probe 1252 */ 1253 if (pin_idx < 0) { 1254 err = hdmi_pcm_open_no_pin(hinfo, codec, substream); 1255 goto unlock; 1256 } 1257 } 1258 1259 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx); 1260 if (err < 0) 1261 goto unlock; 1262 1263 per_cvt = get_cvt(spec, cvt_idx); 1264 /* Claim converter */ 1265 per_cvt->assigned = 1; 1266 1267 set_bit(pcm_idx, &spec->pcm_in_use); 1268 per_pin = get_pin(spec, pin_idx); 1269 per_pin->cvt_nid = per_cvt->cvt_nid; 1270 hinfo->nid = per_cvt->cvt_nid; 1271 1272 /* flip stripe flag for the assigned stream if supported */ 1273 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE) 1274 azx_stream(get_azx_dev(substream))->stripe = 1; 1275 1276 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1277 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1278 AC_VERB_SET_CONNECT_SEL, 1279 per_pin->mux_idx); 1280 1281 /* configure unused pins to choose other converters */ 1282 pin_cvt_fixup(codec, per_pin, 0); 1283 1284 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); 1285 1286 /* Initially set the converter's capabilities */ 1287 hinfo->channels_min = per_cvt->channels_min; 1288 hinfo->channels_max = per_cvt->channels_max; 1289 hinfo->rates = per_cvt->rates; 1290 hinfo->formats = per_cvt->formats; 1291 hinfo->maxbps = per_cvt->maxbps; 1292 1293 eld = &per_pin->sink_eld; 1294 /* Restrict capabilities by ELD if this isn't disabled */ 1295 if (!static_hdmi_pcm && eld->eld_valid) { 1296 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); 1297 if (hinfo->channels_min > hinfo->channels_max || 1298 !hinfo->rates || !hinfo->formats) { 1299 per_cvt->assigned = 0; 1300 hinfo->nid = 0; 1301 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1302 err = -ENODEV; 1303 goto unlock; 1304 } 1305 } 1306 1307 /* Store the updated parameters */ 1308 runtime->hw.channels_min = hinfo->channels_min; 1309 runtime->hw.channels_max = hinfo->channels_max; 1310 runtime->hw.formats = hinfo->formats; 1311 runtime->hw.rates = hinfo->rates; 1312 1313 snd_pcm_hw_constraint_step(substream->runtime, 0, 1314 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1315 unlock: 1316 mutex_unlock(&spec->pcm_lock); 1317 return err; 1318 } 1319 1320 /* 1321 * HDA/HDMI auto parsing 1322 */ 1323 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) 1324 { 1325 struct hdmi_spec *spec = codec->spec; 1326 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1327 hda_nid_t pin_nid = per_pin->pin_nid; 1328 int dev_id = per_pin->dev_id; 1329 int conns; 1330 1331 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { 1332 codec_warn(codec, 1333 "HDMI: pin NID 0x%x wcaps %#x does not support connection list\n", 1334 pin_nid, get_wcaps(codec, pin_nid)); 1335 return -EINVAL; 1336 } 1337 1338 snd_hda_set_dev_select(codec, pin_nid, dev_id); 1339 1340 if (spec->intel_hsw_fixup) { 1341 conns = spec->num_cvts; 1342 memcpy(per_pin->mux_nids, spec->cvt_nids, 1343 sizeof(hda_nid_t) * conns); 1344 } else { 1345 conns = snd_hda_get_raw_connections(codec, pin_nid, 1346 per_pin->mux_nids, 1347 HDA_MAX_CONNECTIONS); 1348 } 1349 1350 /* all the device entries on the same pin have the same conn list */ 1351 per_pin->num_mux_nids = conns; 1352 1353 return 0; 1354 } 1355 1356 static int hdmi_find_pcm_slot(struct hdmi_spec *spec, 1357 struct hdmi_spec_per_pin *per_pin) 1358 { 1359 int i; 1360 1361 /* on the new machines, try to assign the pcm slot dynamically, 1362 * not use the preferred fixed map (legacy way) anymore. 1363 */ 1364 if (spec->dyn_pcm_no_legacy) 1365 goto last_try; 1366 1367 /* 1368 * generic_hdmi_build_pcms() may allocate extra PCMs on some 1369 * platforms (with maximum of 'num_nids + dev_num - 1') 1370 * 1371 * The per_pin of pin_nid_idx=n and dev_id=m prefers to get pcm-n 1372 * if m==0. This guarantees that dynamic pcm assignments are compatible 1373 * with the legacy static per_pin-pcm assignment that existed in the 1374 * days before DP-MST. 1375 * 1376 * Intel DP-MST prefers this legacy behavior for compatibility, too. 1377 * 1378 * per_pin of m!=0 prefers to get pcm=(num_nids + (m - 1)). 1379 */ 1380 1381 if (per_pin->dev_id == 0 || spec->intel_hsw_fixup) { 1382 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap)) 1383 return per_pin->pin_nid_idx; 1384 } else { 1385 i = spec->num_nids + (per_pin->dev_id - 1); 1386 if (i < spec->pcm_used && !(test_bit(i, &spec->pcm_bitmap))) 1387 return i; 1388 } 1389 1390 /* have a second try; check the area over num_nids */ 1391 for (i = spec->num_nids; i < spec->pcm_used; i++) { 1392 if (!test_bit(i, &spec->pcm_bitmap)) 1393 return i; 1394 } 1395 1396 last_try: 1397 /* the last try; check the empty slots in pins */ 1398 for (i = 0; i < spec->pcm_used; i++) { 1399 if (!test_bit(i, &spec->pcm_bitmap)) 1400 return i; 1401 } 1402 return -EBUSY; 1403 } 1404 1405 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, 1406 struct hdmi_spec_per_pin *per_pin) 1407 { 1408 int idx; 1409 1410 /* pcm already be attached to the pin */ 1411 if (per_pin->pcm) 1412 return; 1413 idx = hdmi_find_pcm_slot(spec, per_pin); 1414 if (idx == -EBUSY) 1415 return; 1416 per_pin->pcm_idx = idx; 1417 per_pin->pcm = get_hdmi_pcm(spec, idx); 1418 set_bit(idx, &spec->pcm_bitmap); 1419 } 1420 1421 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, 1422 struct hdmi_spec_per_pin *per_pin) 1423 { 1424 int idx; 1425 1426 /* pcm already be detached from the pin */ 1427 if (!per_pin->pcm) 1428 return; 1429 idx = per_pin->pcm_idx; 1430 per_pin->pcm_idx = -1; 1431 per_pin->pcm = NULL; 1432 if (idx >= 0 && idx < spec->pcm_used) 1433 clear_bit(idx, &spec->pcm_bitmap); 1434 } 1435 1436 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, 1437 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) 1438 { 1439 int mux_idx; 1440 1441 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1442 if (per_pin->mux_nids[mux_idx] == cvt_nid) 1443 break; 1444 return mux_idx; 1445 } 1446 1447 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); 1448 1449 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, 1450 struct hdmi_spec_per_pin *per_pin) 1451 { 1452 struct hda_codec *codec = per_pin->codec; 1453 struct hda_pcm *pcm; 1454 struct hda_pcm_stream *hinfo; 1455 struct snd_pcm_substream *substream; 1456 int mux_idx; 1457 bool non_pcm; 1458 1459 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1460 pcm = get_pcm_rec(spec, per_pin->pcm_idx); 1461 else 1462 return; 1463 if (!pcm->pcm) 1464 return; 1465 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) 1466 return; 1467 1468 /* hdmi audio only uses playback and one substream */ 1469 hinfo = pcm->stream; 1470 substream = pcm->pcm->streams[0].substream; 1471 1472 per_pin->cvt_nid = hinfo->nid; 1473 1474 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); 1475 if (mux_idx < per_pin->num_mux_nids) { 1476 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1477 per_pin->dev_id); 1478 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1479 AC_VERB_SET_CONNECT_SEL, 1480 mux_idx); 1481 } 1482 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); 1483 1484 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); 1485 if (substream->runtime) 1486 per_pin->channels = substream->runtime->channels; 1487 per_pin->setup = true; 1488 per_pin->mux_idx = mux_idx; 1489 1490 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1491 } 1492 1493 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, 1494 struct hdmi_spec_per_pin *per_pin) 1495 { 1496 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1497 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); 1498 1499 per_pin->chmap_set = false; 1500 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1501 1502 per_pin->setup = false; 1503 per_pin->channels = 0; 1504 } 1505 1506 static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec, 1507 struct hdmi_spec_per_pin *per_pin) 1508 { 1509 struct hdmi_spec *spec = codec->spec; 1510 1511 if (per_pin->pcm_idx >= 0) 1512 return spec->pcm_rec[per_pin->pcm_idx].jack; 1513 else 1514 return NULL; 1515 } 1516 1517 /* update per_pin ELD from the given new ELD; 1518 * setup info frame and notification accordingly 1519 * also notify ELD kctl and report jack status changes 1520 */ 1521 static void update_eld(struct hda_codec *codec, 1522 struct hdmi_spec_per_pin *per_pin, 1523 struct hdmi_eld *eld, 1524 int repoll) 1525 { 1526 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 1527 struct hdmi_spec *spec = codec->spec; 1528 struct snd_jack *pcm_jack; 1529 bool old_eld_valid = pin_eld->eld_valid; 1530 bool eld_changed; 1531 int pcm_idx; 1532 1533 if (eld->eld_valid) { 1534 if (eld->eld_size <= 0 || 1535 snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, 1536 eld->eld_size) < 0) { 1537 eld->eld_valid = false; 1538 if (repoll) { 1539 schedule_delayed_work(&per_pin->work, 1540 msecs_to_jiffies(300)); 1541 return; 1542 } 1543 } 1544 } 1545 1546 if (!eld->eld_valid || eld->eld_size <= 0 || eld->info.sad_count <= 0) { 1547 eld->eld_valid = false; 1548 eld->eld_size = 0; 1549 } 1550 1551 /* for monitor disconnection, save pcm_idx firstly */ 1552 pcm_idx = per_pin->pcm_idx; 1553 1554 /* 1555 * pcm_idx >=0 before update_eld() means it is in monitor 1556 * disconnected event. Jack must be fetched before update_eld(). 1557 */ 1558 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); 1559 1560 if (spec->dyn_pcm_assign) { 1561 if (eld->eld_valid) { 1562 hdmi_attach_hda_pcm(spec, per_pin); 1563 hdmi_pcm_setup_pin(spec, per_pin); 1564 } else { 1565 hdmi_pcm_reset_pin(spec, per_pin); 1566 hdmi_detach_hda_pcm(spec, per_pin); 1567 } 1568 } 1569 /* if pcm_idx == -1, it means this is in monitor connection event 1570 * we can get the correct pcm_idx now. 1571 */ 1572 if (pcm_idx == -1) 1573 pcm_idx = per_pin->pcm_idx; 1574 if (!pcm_jack) 1575 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); 1576 1577 if (eld->eld_valid) 1578 snd_hdmi_show_eld(codec, &eld->info); 1579 1580 eld_changed = (pin_eld->eld_valid != eld->eld_valid); 1581 eld_changed |= (pin_eld->monitor_present != eld->monitor_present); 1582 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid) 1583 if (pin_eld->eld_size != eld->eld_size || 1584 memcmp(pin_eld->eld_buffer, eld->eld_buffer, 1585 eld->eld_size) != 0) 1586 eld_changed = true; 1587 1588 if (eld_changed) { 1589 pin_eld->monitor_present = eld->monitor_present; 1590 pin_eld->eld_valid = eld->eld_valid; 1591 pin_eld->eld_size = eld->eld_size; 1592 if (eld->eld_valid) 1593 memcpy(pin_eld->eld_buffer, eld->eld_buffer, 1594 eld->eld_size); 1595 pin_eld->info = eld->info; 1596 } 1597 1598 /* 1599 * Re-setup pin and infoframe. This is needed e.g. when 1600 * - sink is first plugged-in 1601 * - transcoder can change during stream playback on Haswell 1602 * and this can make HW reset converter selection on a pin. 1603 */ 1604 if (eld->eld_valid && !old_eld_valid && per_pin->setup) { 1605 pin_cvt_fixup(codec, per_pin, 0); 1606 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1607 } 1608 1609 if (eld_changed && pcm_idx >= 0) 1610 snd_ctl_notify(codec->card, 1611 SNDRV_CTL_EVENT_MASK_VALUE | 1612 SNDRV_CTL_EVENT_MASK_INFO, 1613 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); 1614 1615 if (eld_changed && pcm_jack) 1616 snd_jack_report(pcm_jack, 1617 (eld->monitor_present && eld->eld_valid) ? 1618 SND_JACK_AVOUT : 0); 1619 } 1620 1621 /* update ELD and jack state via HD-audio verbs */ 1622 static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, 1623 int repoll) 1624 { 1625 struct hda_codec *codec = per_pin->codec; 1626 struct hdmi_spec *spec = codec->spec; 1627 struct hdmi_eld *eld = &spec->temp_eld; 1628 struct device *dev = hda_codec_dev(codec); 1629 hda_nid_t pin_nid = per_pin->pin_nid; 1630 int dev_id = per_pin->dev_id; 1631 /* 1632 * Always execute a GetPinSense verb here, even when called from 1633 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited 1634 * response's PD bit is not the real PD value, but indicates that 1635 * the real PD value changed. An older version of the HD-audio 1636 * specification worked this way. Hence, we just ignore the data in 1637 * the unsolicited response to avoid custom WARs. 1638 */ 1639 int present; 1640 int ret; 1641 1642 #ifdef CONFIG_PM 1643 if (dev->power.runtime_status == RPM_SUSPENDING) 1644 return; 1645 #endif 1646 1647 ret = snd_hda_power_up_pm(codec); 1648 if (ret < 0 && pm_runtime_suspended(dev)) 1649 goto out; 1650 1651 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id); 1652 1653 mutex_lock(&per_pin->lock); 1654 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); 1655 if (eld->monitor_present) 1656 eld->eld_valid = !!(present & AC_PINSENSE_ELDV); 1657 else 1658 eld->eld_valid = false; 1659 1660 codec_dbg(codec, 1661 "HDMI status: Codec=%d NID=0x%x Presence_Detect=%d ELD_Valid=%d\n", 1662 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); 1663 1664 if (eld->eld_valid) { 1665 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id, 1666 eld->eld_buffer, &eld->eld_size) < 0) 1667 eld->eld_valid = false; 1668 } 1669 1670 update_eld(codec, per_pin, eld, repoll); 1671 mutex_unlock(&per_pin->lock); 1672 out: 1673 snd_hda_power_down_pm(codec); 1674 } 1675 1676 #define I915_SILENT_RATE 48000 1677 #define I915_SILENT_CHANNELS 2 1678 #define I915_SILENT_FORMAT SNDRV_PCM_FORMAT_S16_LE 1679 #define I915_SILENT_FORMAT_BITS 16 1680 #define I915_SILENT_FMT_MASK 0xf 1681 1682 static void silent_stream_enable_i915(struct hda_codec *codec, 1683 struct hdmi_spec_per_pin *per_pin) 1684 { 1685 unsigned int format; 1686 1687 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, 1688 per_pin->dev_id, I915_SILENT_RATE); 1689 1690 /* trigger silent stream generation in hw */ 1691 format = snd_hdac_calc_stream_format(I915_SILENT_RATE, I915_SILENT_CHANNELS, 1692 I915_SILENT_FORMAT, I915_SILENT_FORMAT_BITS, 0); 1693 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, 1694 I915_SILENT_FMT_MASK, I915_SILENT_FMT_MASK, format); 1695 usleep_range(100, 200); 1696 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, I915_SILENT_FMT_MASK, 0, format); 1697 1698 per_pin->channels = I915_SILENT_CHANNELS; 1699 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1700 } 1701 1702 static void silent_stream_set_kae(struct hda_codec *codec, 1703 struct hdmi_spec_per_pin *per_pin, 1704 bool enable) 1705 { 1706 unsigned int param; 1707 1708 codec_dbg(codec, "HDMI: KAE %d cvt-NID=0x%x\n", enable, per_pin->cvt_nid); 1709 1710 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, AC_VERB_GET_DIGI_CONVERT_1, 0); 1711 param = (param >> 16) & 0xff; 1712 1713 if (enable) 1714 param |= AC_DIG3_KAE; 1715 else 1716 param &= ~AC_DIG3_KAE; 1717 1718 snd_hda_codec_write(codec, per_pin->cvt_nid, 0, AC_VERB_SET_DIGI_CONVERT_3, param); 1719 } 1720 1721 static void silent_stream_enable(struct hda_codec *codec, 1722 struct hdmi_spec_per_pin *per_pin) 1723 { 1724 struct hdmi_spec *spec = codec->spec; 1725 struct hdmi_spec_per_cvt *per_cvt; 1726 int cvt_idx, pin_idx, err; 1727 int keep_power = 0; 1728 1729 /* 1730 * Power-up will call hdmi_present_sense, so the PM calls 1731 * have to be done without mutex held. 1732 */ 1733 1734 err = snd_hda_power_up_pm(codec); 1735 if (err < 0 && err != -EACCES) { 1736 codec_err(codec, 1737 "Failed to power up codec for silent stream enable ret=[%d]\n", err); 1738 snd_hda_power_down_pm(codec); 1739 return; 1740 } 1741 1742 mutex_lock(&per_pin->lock); 1743 1744 if (per_pin->setup) { 1745 codec_dbg(codec, "hdmi: PCM already open, no silent stream\n"); 1746 err = -EBUSY; 1747 goto unlock_out; 1748 } 1749 1750 pin_idx = pin_id_to_pin_index(codec, per_pin->pin_nid, per_pin->dev_id); 1751 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx); 1752 if (err) { 1753 codec_err(codec, "hdmi: no free converter to enable silent mode\n"); 1754 goto unlock_out; 1755 } 1756 1757 per_cvt = get_cvt(spec, cvt_idx); 1758 per_cvt->assigned = 1; 1759 per_pin->cvt_nid = per_cvt->cvt_nid; 1760 per_pin->silent_stream = true; 1761 1762 codec_dbg(codec, "hdmi: enabling silent stream pin-NID=0x%x cvt-NID=0x%x\n", 1763 per_pin->pin_nid, per_cvt->cvt_nid); 1764 1765 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1766 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1767 AC_VERB_SET_CONNECT_SEL, 1768 per_pin->mux_idx); 1769 1770 /* configure unused pins to choose other converters */ 1771 pin_cvt_fixup(codec, per_pin, 0); 1772 1773 switch (spec->silent_stream_type) { 1774 case SILENT_STREAM_KAE: 1775 silent_stream_set_kae(codec, per_pin, true); 1776 break; 1777 case SILENT_STREAM_I915: 1778 silent_stream_enable_i915(codec, per_pin); 1779 keep_power = 1; 1780 break; 1781 default: 1782 break; 1783 } 1784 1785 unlock_out: 1786 mutex_unlock(&per_pin->lock); 1787 1788 if (err || !keep_power) 1789 snd_hda_power_down_pm(codec); 1790 } 1791 1792 static void silent_stream_disable(struct hda_codec *codec, 1793 struct hdmi_spec_per_pin *per_pin) 1794 { 1795 struct hdmi_spec *spec = codec->spec; 1796 struct hdmi_spec_per_cvt *per_cvt; 1797 int cvt_idx, err; 1798 1799 err = snd_hda_power_up_pm(codec); 1800 if (err < 0 && err != -EACCES) { 1801 codec_err(codec, 1802 "Failed to power up codec for silent stream disable ret=[%d]\n", 1803 err); 1804 snd_hda_power_down_pm(codec); 1805 return; 1806 } 1807 1808 mutex_lock(&per_pin->lock); 1809 if (!per_pin->silent_stream) 1810 goto unlock_out; 1811 1812 codec_dbg(codec, "HDMI: disable silent stream on pin-NID=0x%x cvt-NID=0x%x\n", 1813 per_pin->pin_nid, per_pin->cvt_nid); 1814 1815 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid); 1816 if (cvt_idx >= 0 && cvt_idx < spec->num_cvts) { 1817 per_cvt = get_cvt(spec, cvt_idx); 1818 per_cvt->assigned = 0; 1819 } 1820 1821 if (spec->silent_stream_type == SILENT_STREAM_I915) { 1822 /* release ref taken in silent_stream_enable() */ 1823 snd_hda_power_down_pm(codec); 1824 } else if (spec->silent_stream_type == SILENT_STREAM_KAE) { 1825 silent_stream_set_kae(codec, per_pin, false); 1826 } 1827 1828 per_pin->cvt_nid = 0; 1829 per_pin->silent_stream = false; 1830 1831 unlock_out: 1832 mutex_unlock(&per_pin->lock); 1833 1834 snd_hda_power_down_pm(codec); 1835 } 1836 1837 /* update ELD and jack state via audio component */ 1838 static void sync_eld_via_acomp(struct hda_codec *codec, 1839 struct hdmi_spec_per_pin *per_pin) 1840 { 1841 struct hdmi_spec *spec = codec->spec; 1842 struct hdmi_eld *eld = &spec->temp_eld; 1843 bool monitor_prev, monitor_next; 1844 1845 mutex_lock(&per_pin->lock); 1846 eld->monitor_present = false; 1847 monitor_prev = per_pin->sink_eld.monitor_present; 1848 eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, 1849 per_pin->dev_id, &eld->monitor_present, 1850 eld->eld_buffer, ELD_MAX_SIZE); 1851 eld->eld_valid = (eld->eld_size > 0); 1852 update_eld(codec, per_pin, eld, 0); 1853 monitor_next = per_pin->sink_eld.monitor_present; 1854 mutex_unlock(&per_pin->lock); 1855 1856 if (spec->silent_stream_type) { 1857 if (!monitor_prev && monitor_next) 1858 silent_stream_enable(codec, per_pin); 1859 else if (monitor_prev && !monitor_next) 1860 silent_stream_disable(codec, per_pin); 1861 } 1862 } 1863 1864 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) 1865 { 1866 struct hda_codec *codec = per_pin->codec; 1867 1868 if (!codec_has_acomp(codec)) 1869 hdmi_present_sense_via_verbs(per_pin, repoll); 1870 else 1871 sync_eld_via_acomp(codec, per_pin); 1872 } 1873 1874 static void hdmi_repoll_eld(struct work_struct *work) 1875 { 1876 struct hdmi_spec_per_pin *per_pin = 1877 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); 1878 struct hda_codec *codec = per_pin->codec; 1879 struct hdmi_spec *spec = codec->spec; 1880 struct hda_jack_tbl *jack; 1881 1882 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid, 1883 per_pin->dev_id); 1884 if (jack) 1885 jack->jack_dirty = 1; 1886 1887 if (per_pin->repoll_count++ > 6) 1888 per_pin->repoll_count = 0; 1889 1890 mutex_lock(&spec->pcm_lock); 1891 hdmi_present_sense(per_pin, per_pin->repoll_count); 1892 mutex_unlock(&spec->pcm_lock); 1893 } 1894 1895 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) 1896 { 1897 struct hdmi_spec *spec = codec->spec; 1898 unsigned int caps, config; 1899 int pin_idx; 1900 struct hdmi_spec_per_pin *per_pin; 1901 int err; 1902 int dev_num, i; 1903 1904 caps = snd_hda_query_pin_caps(codec, pin_nid); 1905 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) 1906 return 0; 1907 1908 /* 1909 * For DP MST audio, Configuration Default is the same for 1910 * all device entries on the same pin 1911 */ 1912 config = snd_hda_codec_get_pincfg(codec, pin_nid); 1913 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE && 1914 !spec->force_connect) 1915 return 0; 1916 1917 /* 1918 * To simplify the implementation, malloc all 1919 * the virtual pins in the initialization statically 1920 */ 1921 if (spec->intel_hsw_fixup) { 1922 /* 1923 * On Intel platforms, device entries count returned 1924 * by AC_PAR_DEVLIST_LEN is dynamic, and depends on 1925 * the type of receiver that is connected. Allocate pin 1926 * structures based on worst case. 1927 */ 1928 dev_num = spec->dev_num; 1929 } else if (spec->dyn_pcm_assign && codec->dp_mst) { 1930 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; 1931 /* 1932 * spec->dev_num is the maxinum number of device entries 1933 * among all the pins 1934 */ 1935 spec->dev_num = (spec->dev_num > dev_num) ? 1936 spec->dev_num : dev_num; 1937 } else { 1938 /* 1939 * If the platform doesn't support DP MST, 1940 * manually set dev_num to 1. This means 1941 * the pin has only one device entry. 1942 */ 1943 dev_num = 1; 1944 spec->dev_num = 1; 1945 } 1946 1947 for (i = 0; i < dev_num; i++) { 1948 pin_idx = spec->num_pins; 1949 per_pin = snd_array_new(&spec->pins); 1950 1951 if (!per_pin) 1952 return -ENOMEM; 1953 1954 if (spec->dyn_pcm_assign) { 1955 per_pin->pcm = NULL; 1956 per_pin->pcm_idx = -1; 1957 } else { 1958 per_pin->pcm = get_hdmi_pcm(spec, pin_idx); 1959 per_pin->pcm_idx = pin_idx; 1960 } 1961 per_pin->pin_nid = pin_nid; 1962 per_pin->pin_nid_idx = spec->num_nids; 1963 per_pin->dev_id = i; 1964 per_pin->non_pcm = false; 1965 snd_hda_set_dev_select(codec, pin_nid, i); 1966 err = hdmi_read_pin_conn(codec, pin_idx); 1967 if (err < 0) 1968 return err; 1969 spec->num_pins++; 1970 } 1971 spec->num_nids++; 1972 1973 return 0; 1974 } 1975 1976 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1977 { 1978 struct hdmi_spec *spec = codec->spec; 1979 struct hdmi_spec_per_cvt *per_cvt; 1980 unsigned int chans; 1981 int err; 1982 1983 chans = get_wcaps(codec, cvt_nid); 1984 chans = get_wcaps_channels(chans); 1985 1986 per_cvt = snd_array_new(&spec->cvts); 1987 if (!per_cvt) 1988 return -ENOMEM; 1989 1990 per_cvt->cvt_nid = cvt_nid; 1991 per_cvt->channels_min = 2; 1992 if (chans <= 16) { 1993 per_cvt->channels_max = chans; 1994 if (chans > spec->chmap.channels_max) 1995 spec->chmap.channels_max = chans; 1996 } 1997 1998 err = snd_hda_query_supported_pcm(codec, cvt_nid, 1999 &per_cvt->rates, 2000 &per_cvt->formats, 2001 &per_cvt->maxbps); 2002 if (err < 0) 2003 return err; 2004 2005 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) 2006 spec->cvt_nids[spec->num_cvts] = cvt_nid; 2007 spec->num_cvts++; 2008 2009 return 0; 2010 } 2011 2012 static const struct snd_pci_quirk force_connect_list[] = { 2013 SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1), 2014 SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1), 2015 SND_PCI_QUIRK(0x1462, 0xec94, "MS-7C94", 1), 2016 SND_PCI_QUIRK(0x8086, 0x2081, "Intel NUC 10", 1), 2017 {} 2018 }; 2019 2020 static int hdmi_parse_codec(struct hda_codec *codec) 2021 { 2022 struct hdmi_spec *spec = codec->spec; 2023 hda_nid_t start_nid; 2024 unsigned int caps; 2025 int i, nodes; 2026 const struct snd_pci_quirk *q; 2027 2028 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid); 2029 if (!start_nid || nodes < 0) { 2030 codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); 2031 return -EINVAL; 2032 } 2033 2034 if (enable_all_pins) 2035 spec->force_connect = true; 2036 2037 q = snd_pci_quirk_lookup(codec->bus->pci, force_connect_list); 2038 2039 if (q && q->value) 2040 spec->force_connect = true; 2041 2042 /* 2043 * hdmi_add_pin() assumes total amount of converters to 2044 * be known, so first discover all converters 2045 */ 2046 for (i = 0; i < nodes; i++) { 2047 hda_nid_t nid = start_nid + i; 2048 2049 caps = get_wcaps(codec, nid); 2050 2051 if (!(caps & AC_WCAP_DIGITAL)) 2052 continue; 2053 2054 if (get_wcaps_type(caps) == AC_WID_AUD_OUT) 2055 hdmi_add_cvt(codec, nid); 2056 } 2057 2058 /* discover audio pins */ 2059 for (i = 0; i < nodes; i++) { 2060 hda_nid_t nid = start_nid + i; 2061 2062 caps = get_wcaps(codec, nid); 2063 2064 if (!(caps & AC_WCAP_DIGITAL)) 2065 continue; 2066 2067 if (get_wcaps_type(caps) == AC_WID_PIN) 2068 hdmi_add_pin(codec, nid); 2069 } 2070 2071 return 0; 2072 } 2073 2074 /* 2075 */ 2076 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 2077 { 2078 struct hda_spdif_out *spdif; 2079 bool non_pcm; 2080 2081 mutex_lock(&codec->spdif_mutex); 2082 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); 2083 /* Add sanity check to pass klockwork check. 2084 * This should never happen. 2085 */ 2086 if (WARN_ON(spdif == NULL)) { 2087 mutex_unlock(&codec->spdif_mutex); 2088 return true; 2089 } 2090 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); 2091 mutex_unlock(&codec->spdif_mutex); 2092 return non_pcm; 2093 } 2094 2095 /* 2096 * HDMI callbacks 2097 */ 2098 2099 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 2100 struct hda_codec *codec, 2101 unsigned int stream_tag, 2102 unsigned int format, 2103 struct snd_pcm_substream *substream) 2104 { 2105 hda_nid_t cvt_nid = hinfo->nid; 2106 struct hdmi_spec *spec = codec->spec; 2107 int pin_idx; 2108 struct hdmi_spec_per_pin *per_pin; 2109 struct snd_pcm_runtime *runtime = substream->runtime; 2110 bool non_pcm; 2111 int pinctl, stripe; 2112 int err = 0; 2113 2114 mutex_lock(&spec->pcm_lock); 2115 pin_idx = hinfo_to_pin_index(codec, hinfo); 2116 if (spec->dyn_pcm_assign && pin_idx < 0) { 2117 /* when dyn_pcm_assign and pcm is not bound to a pin 2118 * skip pin setup and return 0 to make audio playback 2119 * be ongoing 2120 */ 2121 pin_cvt_fixup(codec, NULL, cvt_nid); 2122 snd_hda_codec_setup_stream(codec, cvt_nid, 2123 stream_tag, 0, format); 2124 goto unlock; 2125 } 2126 2127 if (snd_BUG_ON(pin_idx < 0)) { 2128 err = -EINVAL; 2129 goto unlock; 2130 } 2131 per_pin = get_pin(spec, pin_idx); 2132 2133 /* Verify pin:cvt selections to avoid silent audio after S3. 2134 * After S3, the audio driver restores pin:cvt selections 2135 * but this can happen before gfx is ready and such selection 2136 * is overlooked by HW. Thus multiple pins can share a same 2137 * default convertor and mute control will affect each other, 2138 * which can cause a resumed audio playback become silent 2139 * after S3. 2140 */ 2141 pin_cvt_fixup(codec, per_pin, 0); 2142 2143 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ 2144 /* Todo: add DP1.2 MST audio support later */ 2145 if (codec_has_acomp(codec)) 2146 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, 2147 per_pin->dev_id, runtime->rate); 2148 2149 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); 2150 mutex_lock(&per_pin->lock); 2151 per_pin->channels = substream->runtime->channels; 2152 per_pin->setup = true; 2153 2154 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) { 2155 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core, 2156 substream); 2157 snd_hda_codec_write(codec, cvt_nid, 0, 2158 AC_VERB_SET_STRIPE_CONTROL, 2159 stripe); 2160 } 2161 2162 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 2163 mutex_unlock(&per_pin->lock); 2164 if (spec->dyn_pin_out) { 2165 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2166 per_pin->dev_id); 2167 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2168 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2169 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2170 AC_VERB_SET_PIN_WIDGET_CONTROL, 2171 pinctl | PIN_OUT); 2172 } 2173 2174 /* snd_hda_set_dev_select() has been called before */ 2175 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid, 2176 per_pin->dev_id, stream_tag, format); 2177 unlock: 2178 mutex_unlock(&spec->pcm_lock); 2179 return err; 2180 } 2181 2182 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 2183 struct hda_codec *codec, 2184 struct snd_pcm_substream *substream) 2185 { 2186 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 2187 return 0; 2188 } 2189 2190 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, 2191 struct hda_codec *codec, 2192 struct snd_pcm_substream *substream) 2193 { 2194 struct hdmi_spec *spec = codec->spec; 2195 int cvt_idx, pin_idx, pcm_idx; 2196 struct hdmi_spec_per_cvt *per_cvt; 2197 struct hdmi_spec_per_pin *per_pin; 2198 int pinctl; 2199 int err = 0; 2200 2201 mutex_lock(&spec->pcm_lock); 2202 if (hinfo->nid) { 2203 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 2204 if (snd_BUG_ON(pcm_idx < 0)) { 2205 err = -EINVAL; 2206 goto unlock; 2207 } 2208 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); 2209 if (snd_BUG_ON(cvt_idx < 0)) { 2210 err = -EINVAL; 2211 goto unlock; 2212 } 2213 per_cvt = get_cvt(spec, cvt_idx); 2214 per_cvt->assigned = 0; 2215 hinfo->nid = 0; 2216 2217 azx_stream(get_azx_dev(substream))->stripe = 0; 2218 2219 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2220 clear_bit(pcm_idx, &spec->pcm_in_use); 2221 pin_idx = hinfo_to_pin_index(codec, hinfo); 2222 if (spec->dyn_pcm_assign && pin_idx < 0) 2223 goto unlock; 2224 2225 if (snd_BUG_ON(pin_idx < 0)) { 2226 err = -EINVAL; 2227 goto unlock; 2228 } 2229 per_pin = get_pin(spec, pin_idx); 2230 2231 if (spec->dyn_pin_out) { 2232 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2233 per_pin->dev_id); 2234 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2235 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2236 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2237 AC_VERB_SET_PIN_WIDGET_CONTROL, 2238 pinctl & ~PIN_OUT); 2239 } 2240 2241 mutex_lock(&per_pin->lock); 2242 per_pin->chmap_set = false; 2243 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 2244 2245 per_pin->setup = false; 2246 per_pin->channels = 0; 2247 mutex_unlock(&per_pin->lock); 2248 } 2249 2250 unlock: 2251 mutex_unlock(&spec->pcm_lock); 2252 2253 return err; 2254 } 2255 2256 static const struct hda_pcm_ops generic_ops = { 2257 .open = hdmi_pcm_open, 2258 .close = hdmi_pcm_close, 2259 .prepare = generic_hdmi_playback_pcm_prepare, 2260 .cleanup = generic_hdmi_playback_pcm_cleanup, 2261 }; 2262 2263 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) 2264 { 2265 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2266 struct hdmi_spec *spec = codec->spec; 2267 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2268 2269 if (!per_pin) 2270 return 0; 2271 2272 return per_pin->sink_eld.info.spk_alloc; 2273 } 2274 2275 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, 2276 unsigned char *chmap) 2277 { 2278 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2279 struct hdmi_spec *spec = codec->spec; 2280 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2281 2282 /* chmap is already set to 0 in caller */ 2283 if (!per_pin) 2284 return; 2285 2286 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); 2287 } 2288 2289 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, 2290 unsigned char *chmap, int prepared) 2291 { 2292 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2293 struct hdmi_spec *spec = codec->spec; 2294 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2295 2296 if (!per_pin) 2297 return; 2298 mutex_lock(&per_pin->lock); 2299 per_pin->chmap_set = true; 2300 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); 2301 if (prepared) 2302 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 2303 mutex_unlock(&per_pin->lock); 2304 } 2305 2306 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) 2307 { 2308 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2309 struct hdmi_spec *spec = codec->spec; 2310 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2311 2312 return per_pin ? true:false; 2313 } 2314 2315 static int generic_hdmi_build_pcms(struct hda_codec *codec) 2316 { 2317 struct hdmi_spec *spec = codec->spec; 2318 int idx, pcm_num; 2319 2320 /* 2321 * for non-mst mode, pcm number is the same as before 2322 * for DP MST mode without extra PCM, pcm number is same 2323 * for DP MST mode with extra PCMs, pcm number is 2324 * (nid number + dev_num - 1) 2325 * dev_num is the device entry number in a pin 2326 */ 2327 2328 if (spec->dyn_pcm_no_legacy && codec->mst_no_extra_pcms) 2329 pcm_num = spec->num_cvts; 2330 else if (codec->mst_no_extra_pcms) 2331 pcm_num = spec->num_nids; 2332 else 2333 pcm_num = spec->num_nids + spec->dev_num - 1; 2334 2335 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num); 2336 2337 for (idx = 0; idx < pcm_num; idx++) { 2338 struct hda_pcm *info; 2339 struct hda_pcm_stream *pstr; 2340 2341 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); 2342 if (!info) 2343 return -ENOMEM; 2344 2345 spec->pcm_rec[idx].pcm = info; 2346 spec->pcm_used++; 2347 info->pcm_type = HDA_PCM_TYPE_HDMI; 2348 info->own_chmap = true; 2349 2350 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2351 pstr->substreams = 1; 2352 pstr->ops = generic_ops; 2353 /* pcm number is less than 16 */ 2354 if (spec->pcm_used >= 16) 2355 break; 2356 /* other pstr fields are set in open */ 2357 } 2358 2359 return 0; 2360 } 2361 2362 static void free_hdmi_jack_priv(struct snd_jack *jack) 2363 { 2364 struct hdmi_pcm *pcm = jack->private_data; 2365 2366 pcm->jack = NULL; 2367 } 2368 2369 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) 2370 { 2371 char hdmi_str[32] = "HDMI/DP"; 2372 struct hdmi_spec *spec = codec->spec; 2373 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pcm_idx); 2374 struct snd_jack *jack; 2375 int pcmdev = get_pcm_rec(spec, pcm_idx)->device; 2376 int err; 2377 2378 if (pcmdev > 0) 2379 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); 2380 if (!spec->dyn_pcm_assign && 2381 !is_jack_detectable(codec, per_pin->pin_nid)) 2382 strncat(hdmi_str, " Phantom", 2383 sizeof(hdmi_str) - strlen(hdmi_str) - 1); 2384 2385 err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack, 2386 true, false); 2387 if (err < 0) 2388 return err; 2389 2390 spec->pcm_rec[pcm_idx].jack = jack; 2391 jack->private_data = &spec->pcm_rec[pcm_idx]; 2392 jack->private_free = free_hdmi_jack_priv; 2393 return 0; 2394 } 2395 2396 static int generic_hdmi_build_controls(struct hda_codec *codec) 2397 { 2398 struct hdmi_spec *spec = codec->spec; 2399 int dev, err; 2400 int pin_idx, pcm_idx; 2401 2402 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2403 if (!get_pcm_rec(spec, pcm_idx)->pcm) { 2404 /* no PCM: mark this for skipping permanently */ 2405 set_bit(pcm_idx, &spec->pcm_bitmap); 2406 continue; 2407 } 2408 2409 err = generic_hdmi_build_jack(codec, pcm_idx); 2410 if (err < 0) 2411 return err; 2412 2413 /* create the spdif for each pcm 2414 * pin will be bound when monitor is connected 2415 */ 2416 if (spec->dyn_pcm_assign) 2417 err = snd_hda_create_dig_out_ctls(codec, 2418 0, spec->cvt_nids[0], 2419 HDA_PCM_TYPE_HDMI); 2420 else { 2421 struct hdmi_spec_per_pin *per_pin = 2422 get_pin(spec, pcm_idx); 2423 err = snd_hda_create_dig_out_ctls(codec, 2424 per_pin->pin_nid, 2425 per_pin->mux_nids[0], 2426 HDA_PCM_TYPE_HDMI); 2427 } 2428 if (err < 0) 2429 return err; 2430 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2431 2432 dev = get_pcm_rec(spec, pcm_idx)->device; 2433 if (dev != SNDRV_PCM_INVALID_DEVICE) { 2434 /* add control for ELD Bytes */ 2435 err = hdmi_create_eld_ctl(codec, pcm_idx, dev); 2436 if (err < 0) 2437 return err; 2438 } 2439 } 2440 2441 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2442 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2443 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 2444 2445 pin_eld->eld_valid = false; 2446 hdmi_present_sense(per_pin, 0); 2447 } 2448 2449 /* add channel maps */ 2450 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2451 struct hda_pcm *pcm; 2452 2453 pcm = get_pcm_rec(spec, pcm_idx); 2454 if (!pcm || !pcm->pcm) 2455 break; 2456 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); 2457 if (err < 0) 2458 return err; 2459 } 2460 2461 return 0; 2462 } 2463 2464 static int generic_hdmi_init_per_pins(struct hda_codec *codec) 2465 { 2466 struct hdmi_spec *spec = codec->spec; 2467 int pin_idx; 2468 2469 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2470 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2471 2472 per_pin->codec = codec; 2473 mutex_init(&per_pin->lock); 2474 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); 2475 eld_proc_new(per_pin, pin_idx); 2476 } 2477 return 0; 2478 } 2479 2480 static int generic_hdmi_init(struct hda_codec *codec) 2481 { 2482 struct hdmi_spec *spec = codec->spec; 2483 int pin_idx; 2484 2485 mutex_lock(&spec->bind_lock); 2486 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2487 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2488 hda_nid_t pin_nid = per_pin->pin_nid; 2489 int dev_id = per_pin->dev_id; 2490 2491 snd_hda_set_dev_select(codec, pin_nid, dev_id); 2492 hdmi_init_pin(codec, pin_nid); 2493 if (codec_has_acomp(codec)) 2494 continue; 2495 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id, 2496 jack_callback); 2497 } 2498 mutex_unlock(&spec->bind_lock); 2499 return 0; 2500 } 2501 2502 static void hdmi_array_init(struct hdmi_spec *spec, int nums) 2503 { 2504 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); 2505 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); 2506 } 2507 2508 static void hdmi_array_free(struct hdmi_spec *spec) 2509 { 2510 snd_array_free(&spec->pins); 2511 snd_array_free(&spec->cvts); 2512 } 2513 2514 static void generic_spec_free(struct hda_codec *codec) 2515 { 2516 struct hdmi_spec *spec = codec->spec; 2517 2518 if (spec) { 2519 hdmi_array_free(spec); 2520 kfree(spec); 2521 codec->spec = NULL; 2522 } 2523 codec->dp_mst = false; 2524 } 2525 2526 static void generic_hdmi_free(struct hda_codec *codec) 2527 { 2528 struct hdmi_spec *spec = codec->spec; 2529 int pin_idx, pcm_idx; 2530 2531 if (spec->acomp_registered) { 2532 snd_hdac_acomp_exit(&codec->bus->core); 2533 } else if (codec_has_acomp(codec)) { 2534 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL); 2535 } 2536 codec->relaxed_resume = 0; 2537 2538 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2539 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2540 cancel_delayed_work_sync(&per_pin->work); 2541 eld_proc_free(per_pin); 2542 } 2543 2544 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2545 if (spec->pcm_rec[pcm_idx].jack == NULL) 2546 continue; 2547 if (spec->dyn_pcm_assign) 2548 snd_device_free(codec->card, 2549 spec->pcm_rec[pcm_idx].jack); 2550 else 2551 spec->pcm_rec[pcm_idx].jack = NULL; 2552 } 2553 2554 generic_spec_free(codec); 2555 } 2556 2557 #ifdef CONFIG_PM 2558 static int generic_hdmi_suspend(struct hda_codec *codec) 2559 { 2560 struct hdmi_spec *spec = codec->spec; 2561 int pin_idx; 2562 2563 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2564 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2565 cancel_delayed_work_sync(&per_pin->work); 2566 } 2567 return 0; 2568 } 2569 2570 static int generic_hdmi_resume(struct hda_codec *codec) 2571 { 2572 struct hdmi_spec *spec = codec->spec; 2573 int pin_idx; 2574 2575 codec->patch_ops.init(codec); 2576 snd_hda_regmap_sync(codec); 2577 2578 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2579 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2580 hdmi_present_sense(per_pin, 1); 2581 } 2582 return 0; 2583 } 2584 #endif 2585 2586 static const struct hda_codec_ops generic_hdmi_patch_ops = { 2587 .init = generic_hdmi_init, 2588 .free = generic_hdmi_free, 2589 .build_pcms = generic_hdmi_build_pcms, 2590 .build_controls = generic_hdmi_build_controls, 2591 .unsol_event = hdmi_unsol_event, 2592 #ifdef CONFIG_PM 2593 .suspend = generic_hdmi_suspend, 2594 .resume = generic_hdmi_resume, 2595 #endif 2596 }; 2597 2598 static const struct hdmi_ops generic_standard_hdmi_ops = { 2599 .pin_get_eld = hdmi_pin_get_eld, 2600 .pin_setup_infoframe = hdmi_pin_setup_infoframe, 2601 .pin_hbr_setup = hdmi_pin_hbr_setup, 2602 .setup_stream = hdmi_setup_stream, 2603 }; 2604 2605 /* allocate codec->spec and assign/initialize generic parser ops */ 2606 static int alloc_generic_hdmi(struct hda_codec *codec) 2607 { 2608 struct hdmi_spec *spec; 2609 2610 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2611 if (!spec) 2612 return -ENOMEM; 2613 2614 spec->codec = codec; 2615 spec->ops = generic_standard_hdmi_ops; 2616 spec->dev_num = 1; /* initialize to 1 */ 2617 mutex_init(&spec->pcm_lock); 2618 mutex_init(&spec->bind_lock); 2619 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); 2620 2621 spec->chmap.ops.get_chmap = hdmi_get_chmap; 2622 spec->chmap.ops.set_chmap = hdmi_set_chmap; 2623 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; 2624 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc; 2625 2626 codec->spec = spec; 2627 hdmi_array_init(spec, 4); 2628 2629 codec->patch_ops = generic_hdmi_patch_ops; 2630 2631 return 0; 2632 } 2633 2634 /* generic HDMI parser */ 2635 static int patch_generic_hdmi(struct hda_codec *codec) 2636 { 2637 int err; 2638 2639 err = alloc_generic_hdmi(codec); 2640 if (err < 0) 2641 return err; 2642 2643 err = hdmi_parse_codec(codec); 2644 if (err < 0) { 2645 generic_spec_free(codec); 2646 return err; 2647 } 2648 2649 generic_hdmi_init_per_pins(codec); 2650 return 0; 2651 } 2652 2653 /* 2654 * generic audio component binding 2655 */ 2656 2657 /* turn on / off the unsol event jack detection dynamically */ 2658 static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid, 2659 int dev_id, bool use_acomp) 2660 { 2661 struct hda_jack_tbl *tbl; 2662 2663 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id); 2664 if (tbl) { 2665 /* clear unsol even if component notifier is used, or re-enable 2666 * if notifier is cleared 2667 */ 2668 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag); 2669 snd_hda_codec_write_cache(codec, nid, 0, 2670 AC_VERB_SET_UNSOLICITED_ENABLE, val); 2671 } 2672 } 2673 2674 /* set up / clear component notifier dynamically */ 2675 static void generic_acomp_notifier_set(struct drm_audio_component *acomp, 2676 bool use_acomp) 2677 { 2678 struct hdmi_spec *spec; 2679 int i; 2680 2681 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops); 2682 mutex_lock(&spec->bind_lock); 2683 spec->use_acomp_notifier = use_acomp; 2684 spec->codec->relaxed_resume = use_acomp; 2685 spec->codec->bus->keep_power = 0; 2686 /* reprogram each jack detection logic depending on the notifier */ 2687 for (i = 0; i < spec->num_pins; i++) 2688 reprogram_jack_detect(spec->codec, 2689 get_pin(spec, i)->pin_nid, 2690 get_pin(spec, i)->dev_id, 2691 use_acomp); 2692 mutex_unlock(&spec->bind_lock); 2693 } 2694 2695 /* enable / disable the notifier via master bind / unbind */ 2696 static int generic_acomp_master_bind(struct device *dev, 2697 struct drm_audio_component *acomp) 2698 { 2699 generic_acomp_notifier_set(acomp, true); 2700 return 0; 2701 } 2702 2703 static void generic_acomp_master_unbind(struct device *dev, 2704 struct drm_audio_component *acomp) 2705 { 2706 generic_acomp_notifier_set(acomp, false); 2707 } 2708 2709 /* check whether both HD-audio and DRM PCI devices belong to the same bus */ 2710 static int match_bound_vga(struct device *dev, int subtype, void *data) 2711 { 2712 struct hdac_bus *bus = data; 2713 struct pci_dev *pci, *master; 2714 2715 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev)) 2716 return 0; 2717 master = to_pci_dev(bus->dev); 2718 pci = to_pci_dev(dev); 2719 return master->bus == pci->bus; 2720 } 2721 2722 /* audio component notifier for AMD/Nvidia HDMI codecs */ 2723 static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id) 2724 { 2725 struct hda_codec *codec = audio_ptr; 2726 struct hdmi_spec *spec = codec->spec; 2727 hda_nid_t pin_nid = spec->port2pin(codec, port); 2728 2729 if (!pin_nid) 2730 return; 2731 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN) 2732 return; 2733 /* skip notification during system suspend (but not in runtime PM); 2734 * the state will be updated at resume 2735 */ 2736 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND) 2737 return; 2738 /* ditto during suspend/resume process itself */ 2739 if (snd_hdac_is_in_pm(&codec->core)) 2740 return; 2741 2742 check_presence_and_report(codec, pin_nid, dev_id); 2743 } 2744 2745 /* set up the private drm_audio_ops from the template */ 2746 static void setup_drm_audio_ops(struct hda_codec *codec, 2747 const struct drm_audio_component_audio_ops *ops) 2748 { 2749 struct hdmi_spec *spec = codec->spec; 2750 2751 spec->drm_audio_ops.audio_ptr = codec; 2752 /* intel_audio_codec_enable() or intel_audio_codec_disable() 2753 * will call pin_eld_notify with using audio_ptr pointer 2754 * We need make sure audio_ptr is really setup 2755 */ 2756 wmb(); 2757 spec->drm_audio_ops.pin2port = ops->pin2port; 2758 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify; 2759 spec->drm_audio_ops.master_bind = ops->master_bind; 2760 spec->drm_audio_ops.master_unbind = ops->master_unbind; 2761 } 2762 2763 /* initialize the generic HDMI audio component */ 2764 static void generic_acomp_init(struct hda_codec *codec, 2765 const struct drm_audio_component_audio_ops *ops, 2766 int (*port2pin)(struct hda_codec *, int)) 2767 { 2768 struct hdmi_spec *spec = codec->spec; 2769 2770 if (!enable_acomp) { 2771 codec_info(codec, "audio component disabled by module option\n"); 2772 return; 2773 } 2774 2775 spec->port2pin = port2pin; 2776 setup_drm_audio_ops(codec, ops); 2777 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops, 2778 match_bound_vga, 0)) { 2779 spec->acomp_registered = true; 2780 } 2781 } 2782 2783 /* 2784 * Intel codec parsers and helpers 2785 */ 2786 2787 #define INTEL_GET_VENDOR_VERB 0xf81 2788 #define INTEL_SET_VENDOR_VERB 0x781 2789 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ 2790 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ 2791 2792 static void intel_haswell_enable_all_pins(struct hda_codec *codec, 2793 bool update_tree) 2794 { 2795 unsigned int vendor_param; 2796 struct hdmi_spec *spec = codec->spec; 2797 2798 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2799 INTEL_GET_VENDOR_VERB, 0); 2800 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) 2801 return; 2802 2803 vendor_param |= INTEL_EN_ALL_PIN_CVTS; 2804 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2805 INTEL_SET_VENDOR_VERB, vendor_param); 2806 if (vendor_param == -1) 2807 return; 2808 2809 if (update_tree) 2810 snd_hda_codec_update_widgets(codec); 2811 } 2812 2813 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) 2814 { 2815 unsigned int vendor_param; 2816 struct hdmi_spec *spec = codec->spec; 2817 2818 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2819 INTEL_GET_VENDOR_VERB, 0); 2820 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) 2821 return; 2822 2823 /* enable DP1.2 mode */ 2824 vendor_param |= INTEL_EN_DP12; 2825 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); 2826 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, 2827 INTEL_SET_VENDOR_VERB, vendor_param); 2828 } 2829 2830 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. 2831 * Otherwise you may get severe h/w communication errors. 2832 */ 2833 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, 2834 unsigned int power_state) 2835 { 2836 if (power_state == AC_PWRST_D0) { 2837 intel_haswell_enable_all_pins(codec, false); 2838 intel_haswell_fixup_enable_dp12(codec); 2839 } 2840 2841 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); 2842 snd_hda_codec_set_power_to_all(codec, fg, power_state); 2843 } 2844 2845 /* There is a fixed mapping between audio pin node and display port. 2846 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL: 2847 * Pin Widget 5 - PORT B (port = 1 in i915 driver) 2848 * Pin Widget 6 - PORT C (port = 2 in i915 driver) 2849 * Pin Widget 7 - PORT D (port = 3 in i915 driver) 2850 * 2851 * on VLV, ILK: 2852 * Pin Widget 4 - PORT B (port = 1 in i915 driver) 2853 * Pin Widget 5 - PORT C (port = 2 in i915 driver) 2854 * Pin Widget 6 - PORT D (port = 3 in i915 driver) 2855 */ 2856 static int intel_base_nid(struct hda_codec *codec) 2857 { 2858 switch (codec->core.vendor_id) { 2859 case 0x80860054: /* ILK */ 2860 case 0x80862804: /* ILK */ 2861 case 0x80862882: /* VLV */ 2862 return 4; 2863 default: 2864 return 5; 2865 } 2866 } 2867 2868 static int intel_pin2port(void *audio_ptr, int pin_nid) 2869 { 2870 struct hda_codec *codec = audio_ptr; 2871 struct hdmi_spec *spec = codec->spec; 2872 int base_nid, i; 2873 2874 if (!spec->port_num) { 2875 base_nid = intel_base_nid(codec); 2876 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3)) 2877 return -1; 2878 return pin_nid - base_nid + 1; 2879 } 2880 2881 /* 2882 * looking for the pin number in the mapping table and return 2883 * the index which indicate the port number 2884 */ 2885 for (i = 0; i < spec->port_num; i++) { 2886 if (pin_nid == spec->port_map[i]) 2887 return i; 2888 } 2889 2890 codec_info(codec, "Can't find the HDMI/DP port for pin NID 0x%x\n", pin_nid); 2891 return -1; 2892 } 2893 2894 static int intel_port2pin(struct hda_codec *codec, int port) 2895 { 2896 struct hdmi_spec *spec = codec->spec; 2897 2898 if (!spec->port_num) { 2899 /* we assume only from port-B to port-D */ 2900 if (port < 1 || port > 3) 2901 return 0; 2902 return port + intel_base_nid(codec) - 1; 2903 } 2904 2905 if (port < 0 || port >= spec->port_num) 2906 return 0; 2907 return spec->port_map[port]; 2908 } 2909 2910 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) 2911 { 2912 struct hda_codec *codec = audio_ptr; 2913 int pin_nid; 2914 int dev_id = pipe; 2915 2916 pin_nid = intel_port2pin(codec, port); 2917 if (!pin_nid) 2918 return; 2919 /* skip notification during system suspend (but not in runtime PM); 2920 * the state will be updated at resume 2921 */ 2922 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND) 2923 return; 2924 /* ditto during suspend/resume process itself */ 2925 if (snd_hdac_is_in_pm(&codec->core)) 2926 return; 2927 2928 snd_hdac_i915_set_bclk(&codec->bus->core); 2929 check_presence_and_report(codec, pin_nid, dev_id); 2930 } 2931 2932 static const struct drm_audio_component_audio_ops intel_audio_ops = { 2933 .pin2port = intel_pin2port, 2934 .pin_eld_notify = intel_pin_eld_notify, 2935 }; 2936 2937 /* register i915 component pin_eld_notify callback */ 2938 static void register_i915_notifier(struct hda_codec *codec) 2939 { 2940 struct hdmi_spec *spec = codec->spec; 2941 2942 spec->use_acomp_notifier = true; 2943 spec->port2pin = intel_port2pin; 2944 setup_drm_audio_ops(codec, &intel_audio_ops); 2945 snd_hdac_acomp_register_notifier(&codec->bus->core, 2946 &spec->drm_audio_ops); 2947 /* no need for forcible resume for jack check thanks to notifier */ 2948 codec->relaxed_resume = 1; 2949 } 2950 2951 /* setup_stream ops override for HSW+ */ 2952 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 2953 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 2954 int format) 2955 { 2956 haswell_verify_D0(codec, cvt_nid, pin_nid); 2957 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 2958 stream_tag, format); 2959 } 2960 2961 /* pin_cvt_fixup ops override for HSW+ and VLV+ */ 2962 static void i915_pin_cvt_fixup(struct hda_codec *codec, 2963 struct hdmi_spec_per_pin *per_pin, 2964 hda_nid_t cvt_nid) 2965 { 2966 if (per_pin) { 2967 haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid); 2968 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2969 per_pin->dev_id); 2970 intel_verify_pin_cvt_connect(codec, per_pin); 2971 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, 2972 per_pin->dev_id, per_pin->mux_idx); 2973 } else { 2974 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); 2975 } 2976 } 2977 2978 /* precondition and allocation for Intel codecs */ 2979 static int alloc_intel_hdmi(struct hda_codec *codec) 2980 { 2981 int err; 2982 2983 /* requires i915 binding */ 2984 if (!codec->bus->core.audio_component) { 2985 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); 2986 /* set probe_id here to prevent generic fallback binding */ 2987 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE; 2988 return -ENODEV; 2989 } 2990 2991 err = alloc_generic_hdmi(codec); 2992 if (err < 0) 2993 return err; 2994 /* no need to handle unsol events */ 2995 codec->patch_ops.unsol_event = NULL; 2996 return 0; 2997 } 2998 2999 /* parse and post-process for Intel codecs */ 3000 static int parse_intel_hdmi(struct hda_codec *codec) 3001 { 3002 int err, retries = 3; 3003 3004 do { 3005 err = hdmi_parse_codec(codec); 3006 } while (err < 0 && retries--); 3007 3008 if (err < 0) { 3009 generic_spec_free(codec); 3010 return err; 3011 } 3012 3013 generic_hdmi_init_per_pins(codec); 3014 register_i915_notifier(codec); 3015 return 0; 3016 } 3017 3018 /* Intel Haswell and onwards; audio component with eld notifier */ 3019 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid, 3020 const int *port_map, int port_num, int dev_num, 3021 bool send_silent_stream) 3022 { 3023 struct hdmi_spec *spec; 3024 int err; 3025 3026 err = alloc_intel_hdmi(codec); 3027 if (err < 0) 3028 return err; 3029 spec = codec->spec; 3030 codec->dp_mst = true; 3031 spec->dyn_pcm_assign = true; 3032 spec->vendor_nid = vendor_nid; 3033 spec->port_map = port_map; 3034 spec->port_num = port_num; 3035 spec->intel_hsw_fixup = true; 3036 spec->dev_num = dev_num; 3037 3038 intel_haswell_enable_all_pins(codec, true); 3039 intel_haswell_fixup_enable_dp12(codec); 3040 3041 codec->display_power_control = 1; 3042 3043 codec->patch_ops.set_power_state = haswell_set_power_state; 3044 codec->depop_delay = 0; 3045 codec->auto_runtime_pm = 1; 3046 3047 spec->ops.setup_stream = i915_hsw_setup_stream; 3048 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 3049 3050 /* 3051 * Enable silent stream feature, if it is enabled via 3052 * module param or Kconfig option 3053 */ 3054 if (send_silent_stream) 3055 spec->silent_stream_type = SILENT_STREAM_I915; 3056 3057 return parse_intel_hdmi(codec); 3058 } 3059 3060 static int patch_i915_hsw_hdmi(struct hda_codec *codec) 3061 { 3062 return intel_hsw_common_init(codec, 0x08, NULL, 0, 3, 3063 enable_silent_stream); 3064 } 3065 3066 static int patch_i915_glk_hdmi(struct hda_codec *codec) 3067 { 3068 /* 3069 * Silent stream calls audio component .get_power() from 3070 * .pin_eld_notify(). On GLK this will deadlock in i915 due 3071 * to the audio vs. CDCLK workaround. 3072 */ 3073 return intel_hsw_common_init(codec, 0x0b, NULL, 0, 3, false); 3074 } 3075 3076 static int patch_i915_icl_hdmi(struct hda_codec *codec) 3077 { 3078 /* 3079 * pin to port mapping table where the value indicate the pin number and 3080 * the index indicate the port number. 3081 */ 3082 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb}; 3083 3084 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 3, 3085 enable_silent_stream); 3086 } 3087 3088 static int patch_i915_tgl_hdmi(struct hda_codec *codec) 3089 { 3090 /* 3091 * pin to port mapping table where the value indicate the pin number and 3092 * the index indicate the port number. 3093 */ 3094 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf}; 3095 int ret; 3096 3097 ret = intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 4, 3098 enable_silent_stream); 3099 if (!ret) { 3100 struct hdmi_spec *spec = codec->spec; 3101 3102 spec->dyn_pcm_no_legacy = true; 3103 } 3104 3105 return ret; 3106 } 3107 3108 static int patch_i915_adlp_hdmi(struct hda_codec *codec) 3109 { 3110 struct hdmi_spec *spec; 3111 int res; 3112 3113 res = patch_i915_tgl_hdmi(codec); 3114 if (!res) { 3115 spec = codec->spec; 3116 3117 if (spec->silent_stream_type) 3118 spec->silent_stream_type = SILENT_STREAM_KAE; 3119 } 3120 3121 return res; 3122 } 3123 3124 /* Intel Baytrail and Braswell; with eld notifier */ 3125 static int patch_i915_byt_hdmi(struct hda_codec *codec) 3126 { 3127 struct hdmi_spec *spec; 3128 int err; 3129 3130 err = alloc_intel_hdmi(codec); 3131 if (err < 0) 3132 return err; 3133 spec = codec->spec; 3134 3135 /* For Valleyview/Cherryview, only the display codec is in the display 3136 * power well and can use link_power ops to request/release the power. 3137 */ 3138 codec->display_power_control = 1; 3139 3140 codec->depop_delay = 0; 3141 codec->auto_runtime_pm = 1; 3142 3143 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 3144 3145 return parse_intel_hdmi(codec); 3146 } 3147 3148 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ 3149 static int patch_i915_cpt_hdmi(struct hda_codec *codec) 3150 { 3151 int err; 3152 3153 err = alloc_intel_hdmi(codec); 3154 if (err < 0) 3155 return err; 3156 return parse_intel_hdmi(codec); 3157 } 3158 3159 /* 3160 * Shared non-generic implementations 3161 */ 3162 3163 static int simple_playback_build_pcms(struct hda_codec *codec) 3164 { 3165 struct hdmi_spec *spec = codec->spec; 3166 struct hda_pcm *info; 3167 unsigned int chans; 3168 struct hda_pcm_stream *pstr; 3169 struct hdmi_spec_per_cvt *per_cvt; 3170 3171 per_cvt = get_cvt(spec, 0); 3172 chans = get_wcaps(codec, per_cvt->cvt_nid); 3173 chans = get_wcaps_channels(chans); 3174 3175 info = snd_hda_codec_pcm_new(codec, "HDMI 0"); 3176 if (!info) 3177 return -ENOMEM; 3178 spec->pcm_rec[0].pcm = info; 3179 info->pcm_type = HDA_PCM_TYPE_HDMI; 3180 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3181 *pstr = spec->pcm_playback; 3182 pstr->nid = per_cvt->cvt_nid; 3183 if (pstr->channels_max <= 2 && chans && chans <= 16) 3184 pstr->channels_max = chans; 3185 3186 return 0; 3187 } 3188 3189 /* unsolicited event for jack sensing */ 3190 static void simple_hdmi_unsol_event(struct hda_codec *codec, 3191 unsigned int res) 3192 { 3193 snd_hda_jack_set_dirty_all(codec); 3194 snd_hda_jack_report_sync(codec); 3195 } 3196 3197 /* generic_hdmi_build_jack can be used for simple_hdmi, too, 3198 * as long as spec->pins[] is set correctly 3199 */ 3200 #define simple_hdmi_build_jack generic_hdmi_build_jack 3201 3202 static int simple_playback_build_controls(struct hda_codec *codec) 3203 { 3204 struct hdmi_spec *spec = codec->spec; 3205 struct hdmi_spec_per_cvt *per_cvt; 3206 int err; 3207 3208 per_cvt = get_cvt(spec, 0); 3209 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, 3210 per_cvt->cvt_nid, 3211 HDA_PCM_TYPE_HDMI); 3212 if (err < 0) 3213 return err; 3214 return simple_hdmi_build_jack(codec, 0); 3215 } 3216 3217 static int simple_playback_init(struct hda_codec *codec) 3218 { 3219 struct hdmi_spec *spec = codec->spec; 3220 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); 3221 hda_nid_t pin = per_pin->pin_nid; 3222 3223 snd_hda_codec_write(codec, pin, 0, 3224 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); 3225 /* some codecs require to unmute the pin */ 3226 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 3227 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, 3228 AMP_OUT_UNMUTE); 3229 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id); 3230 return 0; 3231 } 3232 3233 static void simple_playback_free(struct hda_codec *codec) 3234 { 3235 struct hdmi_spec *spec = codec->spec; 3236 3237 hdmi_array_free(spec); 3238 kfree(spec); 3239 } 3240 3241 /* 3242 * Nvidia specific implementations 3243 */ 3244 3245 #define Nv_VERB_SET_Channel_Allocation 0xF79 3246 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A 3247 #define Nv_VERB_SET_Audio_Protection_On 0xF98 3248 #define Nv_VERB_SET_Audio_Protection_Off 0xF99 3249 3250 #define nvhdmi_master_con_nid_7x 0x04 3251 #define nvhdmi_master_pin_nid_7x 0x05 3252 3253 static const hda_nid_t nvhdmi_con_nids_7x[4] = { 3254 /*front, rear, clfe, rear_surr */ 3255 0x6, 0x8, 0xa, 0xc, 3256 }; 3257 3258 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { 3259 /* set audio protect on */ 3260 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3261 /* enable digital output on pin widget */ 3262 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3263 {} /* terminator */ 3264 }; 3265 3266 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { 3267 /* set audio protect on */ 3268 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3269 /* enable digital output on pin widget */ 3270 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3271 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3272 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3273 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3274 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3275 {} /* terminator */ 3276 }; 3277 3278 #ifdef LIMITED_RATE_FMT_SUPPORT 3279 /* support only the safe format and rate */ 3280 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 3281 #define SUPPORTED_MAXBPS 16 3282 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE 3283 #else 3284 /* support all rates and formats */ 3285 #define SUPPORTED_RATES \ 3286 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ 3287 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ 3288 SNDRV_PCM_RATE_192000) 3289 #define SUPPORTED_MAXBPS 24 3290 #define SUPPORTED_FORMATS \ 3291 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 3292 #endif 3293 3294 static int nvhdmi_7x_init_2ch(struct hda_codec *codec) 3295 { 3296 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); 3297 return 0; 3298 } 3299 3300 static int nvhdmi_7x_init_8ch(struct hda_codec *codec) 3301 { 3302 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); 3303 return 0; 3304 } 3305 3306 static const unsigned int channels_2_6_8[] = { 3307 2, 6, 8 3308 }; 3309 3310 static const unsigned int channels_2_8[] = { 3311 2, 8 3312 }; 3313 3314 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { 3315 .count = ARRAY_SIZE(channels_2_6_8), 3316 .list = channels_2_6_8, 3317 .mask = 0, 3318 }; 3319 3320 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { 3321 .count = ARRAY_SIZE(channels_2_8), 3322 .list = channels_2_8, 3323 .mask = 0, 3324 }; 3325 3326 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, 3327 struct hda_codec *codec, 3328 struct snd_pcm_substream *substream) 3329 { 3330 struct hdmi_spec *spec = codec->spec; 3331 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; 3332 3333 switch (codec->preset->vendor_id) { 3334 case 0x10de0002: 3335 case 0x10de0003: 3336 case 0x10de0005: 3337 case 0x10de0006: 3338 hw_constraints_channels = &hw_constraints_2_8_channels; 3339 break; 3340 case 0x10de0007: 3341 hw_constraints_channels = &hw_constraints_2_6_8_channels; 3342 break; 3343 default: 3344 break; 3345 } 3346 3347 if (hw_constraints_channels != NULL) { 3348 snd_pcm_hw_constraint_list(substream->runtime, 0, 3349 SNDRV_PCM_HW_PARAM_CHANNELS, 3350 hw_constraints_channels); 3351 } else { 3352 snd_pcm_hw_constraint_step(substream->runtime, 0, 3353 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 3354 } 3355 3356 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3357 } 3358 3359 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, 3360 struct hda_codec *codec, 3361 struct snd_pcm_substream *substream) 3362 { 3363 struct hdmi_spec *spec = codec->spec; 3364 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3365 } 3366 3367 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3368 struct hda_codec *codec, 3369 unsigned int stream_tag, 3370 unsigned int format, 3371 struct snd_pcm_substream *substream) 3372 { 3373 struct hdmi_spec *spec = codec->spec; 3374 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3375 stream_tag, format, substream); 3376 } 3377 3378 static const struct hda_pcm_stream simple_pcm_playback = { 3379 .substreams = 1, 3380 .channels_min = 2, 3381 .channels_max = 2, 3382 .ops = { 3383 .open = simple_playback_pcm_open, 3384 .close = simple_playback_pcm_close, 3385 .prepare = simple_playback_pcm_prepare 3386 }, 3387 }; 3388 3389 static const struct hda_codec_ops simple_hdmi_patch_ops = { 3390 .build_controls = simple_playback_build_controls, 3391 .build_pcms = simple_playback_build_pcms, 3392 .init = simple_playback_init, 3393 .free = simple_playback_free, 3394 .unsol_event = simple_hdmi_unsol_event, 3395 }; 3396 3397 static int patch_simple_hdmi(struct hda_codec *codec, 3398 hda_nid_t cvt_nid, hda_nid_t pin_nid) 3399 { 3400 struct hdmi_spec *spec; 3401 struct hdmi_spec_per_cvt *per_cvt; 3402 struct hdmi_spec_per_pin *per_pin; 3403 3404 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 3405 if (!spec) 3406 return -ENOMEM; 3407 3408 spec->codec = codec; 3409 codec->spec = spec; 3410 hdmi_array_init(spec, 1); 3411 3412 spec->multiout.num_dacs = 0; /* no analog */ 3413 spec->multiout.max_channels = 2; 3414 spec->multiout.dig_out_nid = cvt_nid; 3415 spec->num_cvts = 1; 3416 spec->num_pins = 1; 3417 per_pin = snd_array_new(&spec->pins); 3418 per_cvt = snd_array_new(&spec->cvts); 3419 if (!per_pin || !per_cvt) { 3420 simple_playback_free(codec); 3421 return -ENOMEM; 3422 } 3423 per_cvt->cvt_nid = cvt_nid; 3424 per_pin->pin_nid = pin_nid; 3425 spec->pcm_playback = simple_pcm_playback; 3426 3427 codec->patch_ops = simple_hdmi_patch_ops; 3428 3429 return 0; 3430 } 3431 3432 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, 3433 int channels) 3434 { 3435 unsigned int chanmask; 3436 int chan = channels ? (channels - 1) : 1; 3437 3438 switch (channels) { 3439 default: 3440 case 0: 3441 case 2: 3442 chanmask = 0x00; 3443 break; 3444 case 4: 3445 chanmask = 0x08; 3446 break; 3447 case 6: 3448 chanmask = 0x0b; 3449 break; 3450 case 8: 3451 chanmask = 0x13; 3452 break; 3453 } 3454 3455 /* Set the audio infoframe channel allocation and checksum fields. The 3456 * channel count is computed implicitly by the hardware. */ 3457 snd_hda_codec_write(codec, 0x1, 0, 3458 Nv_VERB_SET_Channel_Allocation, chanmask); 3459 3460 snd_hda_codec_write(codec, 0x1, 0, 3461 Nv_VERB_SET_Info_Frame_Checksum, 3462 (0x71 - chan - chanmask)); 3463 } 3464 3465 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, 3466 struct hda_codec *codec, 3467 struct snd_pcm_substream *substream) 3468 { 3469 struct hdmi_spec *spec = codec->spec; 3470 int i; 3471 3472 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 3473 0, AC_VERB_SET_CHANNEL_STREAMID, 0); 3474 for (i = 0; i < 4; i++) { 3475 /* set the stream id */ 3476 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3477 AC_VERB_SET_CHANNEL_STREAMID, 0); 3478 /* set the stream format */ 3479 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3480 AC_VERB_SET_STREAM_FORMAT, 0); 3481 } 3482 3483 /* The audio hardware sends a channel count of 0x7 (8ch) when all the 3484 * streams are disabled. */ 3485 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3486 3487 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3488 } 3489 3490 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, 3491 struct hda_codec *codec, 3492 unsigned int stream_tag, 3493 unsigned int format, 3494 struct snd_pcm_substream *substream) 3495 { 3496 int chs; 3497 unsigned int dataDCC2, channel_id; 3498 int i; 3499 struct hdmi_spec *spec = codec->spec; 3500 struct hda_spdif_out *spdif; 3501 struct hdmi_spec_per_cvt *per_cvt; 3502 3503 mutex_lock(&codec->spdif_mutex); 3504 per_cvt = get_cvt(spec, 0); 3505 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); 3506 3507 chs = substream->runtime->channels; 3508 3509 dataDCC2 = 0x2; 3510 3511 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ 3512 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) 3513 snd_hda_codec_write(codec, 3514 nvhdmi_master_con_nid_7x, 3515 0, 3516 AC_VERB_SET_DIGI_CONVERT_1, 3517 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3518 3519 /* set the stream id */ 3520 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3521 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); 3522 3523 /* set the stream format */ 3524 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3525 AC_VERB_SET_STREAM_FORMAT, format); 3526 3527 /* turn on again (if needed) */ 3528 /* enable and set the channel status audio/data flag */ 3529 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { 3530 snd_hda_codec_write(codec, 3531 nvhdmi_master_con_nid_7x, 3532 0, 3533 AC_VERB_SET_DIGI_CONVERT_1, 3534 spdif->ctls & 0xff); 3535 snd_hda_codec_write(codec, 3536 nvhdmi_master_con_nid_7x, 3537 0, 3538 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3539 } 3540 3541 for (i = 0; i < 4; i++) { 3542 if (chs == 2) 3543 channel_id = 0; 3544 else 3545 channel_id = i * 2; 3546 3547 /* turn off SPDIF once; 3548 *otherwise the IEC958 bits won't be updated 3549 */ 3550 if (codec->spdif_status_reset && 3551 (spdif->ctls & AC_DIG1_ENABLE)) 3552 snd_hda_codec_write(codec, 3553 nvhdmi_con_nids_7x[i], 3554 0, 3555 AC_VERB_SET_DIGI_CONVERT_1, 3556 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3557 /* set the stream id */ 3558 snd_hda_codec_write(codec, 3559 nvhdmi_con_nids_7x[i], 3560 0, 3561 AC_VERB_SET_CHANNEL_STREAMID, 3562 (stream_tag << 4) | channel_id); 3563 /* set the stream format */ 3564 snd_hda_codec_write(codec, 3565 nvhdmi_con_nids_7x[i], 3566 0, 3567 AC_VERB_SET_STREAM_FORMAT, 3568 format); 3569 /* turn on again (if needed) */ 3570 /* enable and set the channel status audio/data flag */ 3571 if (codec->spdif_status_reset && 3572 (spdif->ctls & AC_DIG1_ENABLE)) { 3573 snd_hda_codec_write(codec, 3574 nvhdmi_con_nids_7x[i], 3575 0, 3576 AC_VERB_SET_DIGI_CONVERT_1, 3577 spdif->ctls & 0xff); 3578 snd_hda_codec_write(codec, 3579 nvhdmi_con_nids_7x[i], 3580 0, 3581 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3582 } 3583 } 3584 3585 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); 3586 3587 mutex_unlock(&codec->spdif_mutex); 3588 return 0; 3589 } 3590 3591 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { 3592 .substreams = 1, 3593 .channels_min = 2, 3594 .channels_max = 8, 3595 .nid = nvhdmi_master_con_nid_7x, 3596 .rates = SUPPORTED_RATES, 3597 .maxbps = SUPPORTED_MAXBPS, 3598 .formats = SUPPORTED_FORMATS, 3599 .ops = { 3600 .open = simple_playback_pcm_open, 3601 .close = nvhdmi_8ch_7x_pcm_close, 3602 .prepare = nvhdmi_8ch_7x_pcm_prepare 3603 }, 3604 }; 3605 3606 static int patch_nvhdmi_2ch(struct hda_codec *codec) 3607 { 3608 struct hdmi_spec *spec; 3609 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, 3610 nvhdmi_master_pin_nid_7x); 3611 if (err < 0) 3612 return err; 3613 3614 codec->patch_ops.init = nvhdmi_7x_init_2ch; 3615 /* override the PCM rates, etc, as the codec doesn't give full list */ 3616 spec = codec->spec; 3617 spec->pcm_playback.rates = SUPPORTED_RATES; 3618 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; 3619 spec->pcm_playback.formats = SUPPORTED_FORMATS; 3620 return 0; 3621 } 3622 3623 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) 3624 { 3625 struct hdmi_spec *spec = codec->spec; 3626 int err = simple_playback_build_pcms(codec); 3627 if (!err) { 3628 struct hda_pcm *info = get_pcm_rec(spec, 0); 3629 info->own_chmap = true; 3630 } 3631 return err; 3632 } 3633 3634 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) 3635 { 3636 struct hdmi_spec *spec = codec->spec; 3637 struct hda_pcm *info; 3638 struct snd_pcm_chmap *chmap; 3639 int err; 3640 3641 err = simple_playback_build_controls(codec); 3642 if (err < 0) 3643 return err; 3644 3645 /* add channel maps */ 3646 info = get_pcm_rec(spec, 0); 3647 err = snd_pcm_add_chmap_ctls(info->pcm, 3648 SNDRV_PCM_STREAM_PLAYBACK, 3649 snd_pcm_alt_chmaps, 8, 0, &chmap); 3650 if (err < 0) 3651 return err; 3652 switch (codec->preset->vendor_id) { 3653 case 0x10de0002: 3654 case 0x10de0003: 3655 case 0x10de0005: 3656 case 0x10de0006: 3657 chmap->channel_mask = (1U << 2) | (1U << 8); 3658 break; 3659 case 0x10de0007: 3660 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); 3661 } 3662 return 0; 3663 } 3664 3665 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) 3666 { 3667 struct hdmi_spec *spec; 3668 int err = patch_nvhdmi_2ch(codec); 3669 if (err < 0) 3670 return err; 3671 spec = codec->spec; 3672 spec->multiout.max_channels = 8; 3673 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; 3674 codec->patch_ops.init = nvhdmi_7x_init_8ch; 3675 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; 3676 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; 3677 3678 /* Initialize the audio infoframe channel mask and checksum to something 3679 * valid */ 3680 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3681 3682 return 0; 3683 } 3684 3685 /* 3686 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: 3687 * - 0x10de0015 3688 * - 0x10de0040 3689 */ 3690 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, 3691 struct hdac_cea_channel_speaker_allocation *cap, int channels) 3692 { 3693 if (cap->ca_index == 0x00 && channels == 2) 3694 return SNDRV_CTL_TLVT_CHMAP_FIXED; 3695 3696 /* If the speaker allocation matches the channel count, it is OK. */ 3697 if (cap->channels != channels) 3698 return -1; 3699 3700 /* all channels are remappable freely */ 3701 return SNDRV_CTL_TLVT_CHMAP_VAR; 3702 } 3703 3704 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, 3705 int ca, int chs, unsigned char *map) 3706 { 3707 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) 3708 return -EINVAL; 3709 3710 return 0; 3711 } 3712 3713 /* map from pin NID to port; port is 0-based */ 3714 /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */ 3715 static int nvhdmi_pin2port(void *audio_ptr, int pin_nid) 3716 { 3717 return pin_nid - 4; 3718 } 3719 3720 /* reverse-map from port to pin NID: see above */ 3721 static int nvhdmi_port2pin(struct hda_codec *codec, int port) 3722 { 3723 return port + 4; 3724 } 3725 3726 static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = { 3727 .pin2port = nvhdmi_pin2port, 3728 .pin_eld_notify = generic_acomp_pin_eld_notify, 3729 .master_bind = generic_acomp_master_bind, 3730 .master_unbind = generic_acomp_master_unbind, 3731 }; 3732 3733 static int patch_nvhdmi(struct hda_codec *codec) 3734 { 3735 struct hdmi_spec *spec; 3736 int err; 3737 3738 err = alloc_generic_hdmi(codec); 3739 if (err < 0) 3740 return err; 3741 codec->dp_mst = true; 3742 3743 spec = codec->spec; 3744 spec->dyn_pcm_assign = true; 3745 3746 err = hdmi_parse_codec(codec); 3747 if (err < 0) { 3748 generic_spec_free(codec); 3749 return err; 3750 } 3751 3752 generic_hdmi_init_per_pins(codec); 3753 3754 spec->dyn_pin_out = true; 3755 3756 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3757 nvhdmi_chmap_cea_alloc_validate_get_type; 3758 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3759 3760 codec->link_down_at_suspend = 1; 3761 3762 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin); 3763 3764 return 0; 3765 } 3766 3767 static int patch_nvhdmi_legacy(struct hda_codec *codec) 3768 { 3769 struct hdmi_spec *spec; 3770 int err; 3771 3772 err = patch_generic_hdmi(codec); 3773 if (err) 3774 return err; 3775 3776 spec = codec->spec; 3777 spec->dyn_pin_out = true; 3778 3779 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3780 nvhdmi_chmap_cea_alloc_validate_get_type; 3781 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3782 3783 codec->link_down_at_suspend = 1; 3784 3785 return 0; 3786 } 3787 3788 /* 3789 * The HDA codec on NVIDIA Tegra contains two scratch registers that are 3790 * accessed using vendor-defined verbs. These registers can be used for 3791 * interoperability between the HDA and HDMI drivers. 3792 */ 3793 3794 /* Audio Function Group node */ 3795 #define NVIDIA_AFG_NID 0x01 3796 3797 /* 3798 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio 3799 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to 3800 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This 3801 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an 3802 * additional bit (at position 30) to signal the validity of the format. 3803 * 3804 * | 31 | 30 | 29 16 | 15 0 | 3805 * +---------+-------+--------+--------+ 3806 * | TRIGGER | VALID | UNUSED | FORMAT | 3807 * +-----------------------------------| 3808 * 3809 * Note that for the trigger bit to take effect it needs to change value 3810 * (i.e. it needs to be toggled). The trigger bit is not applicable from 3811 * TEGRA234 chip onwards, as new verb id 0xf80 will be used for interrupt 3812 * trigger to hdmi. 3813 */ 3814 #define NVIDIA_SET_HOST_INTR 0xf80 3815 #define NVIDIA_GET_SCRATCH0 0xfa6 3816 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 3817 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 3818 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 3819 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa 3820 #define NVIDIA_SCRATCH_TRIGGER (1 << 7) 3821 #define NVIDIA_SCRATCH_VALID (1 << 6) 3822 3823 #define NVIDIA_GET_SCRATCH1 0xfab 3824 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac 3825 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad 3826 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae 3827 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf 3828 3829 /* 3830 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, 3831 * the format is invalidated so that the HDMI codec can be disabled. 3832 */ 3833 static void tegra_hdmi_set_format(struct hda_codec *codec, 3834 hda_nid_t cvt_nid, 3835 unsigned int format) 3836 { 3837 unsigned int value; 3838 unsigned int nid = NVIDIA_AFG_NID; 3839 struct hdmi_spec *spec = codec->spec; 3840 3841 /* 3842 * Tegra HDA codec design from TEGRA234 chip onwards support DP MST. 3843 * This resulted in moving scratch registers from audio function 3844 * group to converter widget context. So CVT NID should be used for 3845 * scratch register read/write for DP MST supported Tegra HDA codec. 3846 */ 3847 if (codec->dp_mst) 3848 nid = cvt_nid; 3849 3850 /* bits [31:30] contain the trigger and valid bits */ 3851 value = snd_hda_codec_read(codec, nid, 0, 3852 NVIDIA_GET_SCRATCH0, 0); 3853 value = (value >> 24) & 0xff; 3854 3855 /* bits [15:0] are used to store the HDA format */ 3856 snd_hda_codec_write(codec, nid, 0, 3857 NVIDIA_SET_SCRATCH0_BYTE0, 3858 (format >> 0) & 0xff); 3859 snd_hda_codec_write(codec, nid, 0, 3860 NVIDIA_SET_SCRATCH0_BYTE1, 3861 (format >> 8) & 0xff); 3862 3863 /* bits [16:24] are unused */ 3864 snd_hda_codec_write(codec, nid, 0, 3865 NVIDIA_SET_SCRATCH0_BYTE2, 0); 3866 3867 /* 3868 * Bit 30 signals that the data is valid and hence that HDMI audio can 3869 * be enabled. 3870 */ 3871 if (format == 0) 3872 value &= ~NVIDIA_SCRATCH_VALID; 3873 else 3874 value |= NVIDIA_SCRATCH_VALID; 3875 3876 if (spec->hdmi_intr_trig_ctrl) { 3877 /* 3878 * For Tegra HDA Codec design from TEGRA234 onwards, the 3879 * Interrupt to hdmi driver is triggered by writing 3880 * non-zero values to verb 0xF80 instead of 31st bit of 3881 * scratch register. 3882 */ 3883 snd_hda_codec_write(codec, nid, 0, 3884 NVIDIA_SET_SCRATCH0_BYTE3, value); 3885 snd_hda_codec_write(codec, nid, 0, 3886 NVIDIA_SET_HOST_INTR, 0x1); 3887 } else { 3888 /* 3889 * Whenever the 31st trigger bit is toggled, an interrupt is raised 3890 * in the HDMI codec. The HDMI driver will use that as trigger 3891 * to update its configuration. 3892 */ 3893 value ^= NVIDIA_SCRATCH_TRIGGER; 3894 3895 snd_hda_codec_write(codec, nid, 0, 3896 NVIDIA_SET_SCRATCH0_BYTE3, value); 3897 } 3898 } 3899 3900 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, 3901 struct hda_codec *codec, 3902 unsigned int stream_tag, 3903 unsigned int format, 3904 struct snd_pcm_substream *substream) 3905 { 3906 int err; 3907 3908 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, 3909 format, substream); 3910 if (err < 0) 3911 return err; 3912 3913 /* notify the HDMI codec of the format change */ 3914 tegra_hdmi_set_format(codec, hinfo->nid, format); 3915 3916 return 0; 3917 } 3918 3919 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, 3920 struct hda_codec *codec, 3921 struct snd_pcm_substream *substream) 3922 { 3923 /* invalidate the format in the HDMI codec */ 3924 tegra_hdmi_set_format(codec, hinfo->nid, 0); 3925 3926 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); 3927 } 3928 3929 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) 3930 { 3931 struct hdmi_spec *spec = codec->spec; 3932 unsigned int i; 3933 3934 for (i = 0; i < spec->num_pins; i++) { 3935 struct hda_pcm *pcm = get_pcm_rec(spec, i); 3936 3937 if (pcm->pcm_type == type) 3938 return pcm; 3939 } 3940 3941 return NULL; 3942 } 3943 3944 static int tegra_hdmi_build_pcms(struct hda_codec *codec) 3945 { 3946 struct hda_pcm_stream *stream; 3947 struct hda_pcm *pcm; 3948 int err; 3949 3950 err = generic_hdmi_build_pcms(codec); 3951 if (err < 0) 3952 return err; 3953 3954 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); 3955 if (!pcm) 3956 return -ENODEV; 3957 3958 /* 3959 * Override ->prepare() and ->cleanup() operations to notify the HDMI 3960 * codec about format changes. 3961 */ 3962 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3963 stream->ops.prepare = tegra_hdmi_pcm_prepare; 3964 stream->ops.cleanup = tegra_hdmi_pcm_cleanup; 3965 3966 return 0; 3967 } 3968 3969 static int tegra_hdmi_init(struct hda_codec *codec) 3970 { 3971 struct hdmi_spec *spec = codec->spec; 3972 int i, err; 3973 3974 err = hdmi_parse_codec(codec); 3975 if (err < 0) { 3976 generic_spec_free(codec); 3977 return err; 3978 } 3979 3980 for (i = 0; i < spec->num_cvts; i++) 3981 snd_hda_codec_write(codec, spec->cvt_nids[i], 0, 3982 AC_VERB_SET_DIGI_CONVERT_1, 3983 AC_DIG1_ENABLE); 3984 3985 generic_hdmi_init_per_pins(codec); 3986 3987 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; 3988 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3989 nvhdmi_chmap_cea_alloc_validate_get_type; 3990 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3991 3992 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3993 nvhdmi_chmap_cea_alloc_validate_get_type; 3994 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3995 3996 return 0; 3997 } 3998 3999 static int patch_tegra_hdmi(struct hda_codec *codec) 4000 { 4001 int err; 4002 4003 err = alloc_generic_hdmi(codec); 4004 if (err < 0) 4005 return err; 4006 4007 return tegra_hdmi_init(codec); 4008 } 4009 4010 static int patch_tegra234_hdmi(struct hda_codec *codec) 4011 { 4012 struct hdmi_spec *spec; 4013 int err; 4014 4015 err = alloc_generic_hdmi(codec); 4016 if (err < 0) 4017 return err; 4018 4019 codec->dp_mst = true; 4020 codec->mst_no_extra_pcms = true; 4021 spec = codec->spec; 4022 spec->dyn_pin_out = true; 4023 spec->dyn_pcm_assign = true; 4024 spec->hdmi_intr_trig_ctrl = true; 4025 4026 return tegra_hdmi_init(codec); 4027 } 4028 4029 /* 4030 * ATI/AMD-specific implementations 4031 */ 4032 4033 #define is_amdhdmi_rev3_or_later(codec) \ 4034 ((codec)->core.vendor_id == 0x1002aa01 && \ 4035 ((codec)->core.revision_id & 0xff00) >= 0x0300) 4036 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) 4037 4038 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ 4039 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 4040 #define ATI_VERB_SET_DOWNMIX_INFO 0x772 4041 #define ATI_VERB_SET_MULTICHANNEL_01 0x777 4042 #define ATI_VERB_SET_MULTICHANNEL_23 0x778 4043 #define ATI_VERB_SET_MULTICHANNEL_45 0x779 4044 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a 4045 #define ATI_VERB_SET_HBR_CONTROL 0x77c 4046 #define ATI_VERB_SET_MULTICHANNEL_1 0x785 4047 #define ATI_VERB_SET_MULTICHANNEL_3 0x786 4048 #define ATI_VERB_SET_MULTICHANNEL_5 0x787 4049 #define ATI_VERB_SET_MULTICHANNEL_7 0x788 4050 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 4051 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 4052 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 4053 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 4054 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 4055 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 4056 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a 4057 #define ATI_VERB_GET_HBR_CONTROL 0xf7c 4058 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 4059 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 4060 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 4061 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 4062 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 4063 4064 /* AMD specific HDA cvt verbs */ 4065 #define ATI_VERB_SET_RAMP_RATE 0x770 4066 #define ATI_VERB_GET_RAMP_RATE 0xf70 4067 4068 #define ATI_OUT_ENABLE 0x1 4069 4070 #define ATI_MULTICHANNEL_MODE_PAIRED 0 4071 #define ATI_MULTICHANNEL_MODE_SINGLE 1 4072 4073 #define ATI_HBR_CAPABLE 0x01 4074 #define ATI_HBR_ENABLE 0x10 4075 4076 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 4077 int dev_id, unsigned char *buf, int *eld_size) 4078 { 4079 WARN_ON(dev_id != 0); 4080 /* call hda_eld.c ATI/AMD-specific function */ 4081 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, 4082 is_amdhdmi_rev3_or_later(codec)); 4083 } 4084 4085 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, 4086 hda_nid_t pin_nid, int dev_id, int ca, 4087 int active_channels, int conn_type) 4088 { 4089 WARN_ON(dev_id != 0); 4090 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); 4091 } 4092 4093 static int atihdmi_paired_swap_fc_lfe(int pos) 4094 { 4095 /* 4096 * ATI/AMD have automatic FC/LFE swap built-in 4097 * when in pairwise mapping mode. 4098 */ 4099 4100 switch (pos) { 4101 /* see channel_allocations[].speakers[] */ 4102 case 2: return 3; 4103 case 3: return 2; 4104 default: break; 4105 } 4106 4107 return pos; 4108 } 4109 4110 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, 4111 int ca, int chs, unsigned char *map) 4112 { 4113 struct hdac_cea_channel_speaker_allocation *cap; 4114 int i, j; 4115 4116 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ 4117 4118 cap = snd_hdac_get_ch_alloc_from_ca(ca); 4119 for (i = 0; i < chs; ++i) { 4120 int mask = snd_hdac_chmap_to_spk_mask(map[i]); 4121 bool ok = false; 4122 bool companion_ok = false; 4123 4124 if (!mask) 4125 continue; 4126 4127 for (j = 0 + i % 2; j < 8; j += 2) { 4128 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); 4129 if (cap->speakers[chan_idx] == mask) { 4130 /* channel is in a supported position */ 4131 ok = true; 4132 4133 if (i % 2 == 0 && i + 1 < chs) { 4134 /* even channel, check the odd companion */ 4135 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); 4136 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); 4137 int comp_mask_act = cap->speakers[comp_chan_idx]; 4138 4139 if (comp_mask_req == comp_mask_act) 4140 companion_ok = true; 4141 else 4142 return -EINVAL; 4143 } 4144 break; 4145 } 4146 } 4147 4148 if (!ok) 4149 return -EINVAL; 4150 4151 if (companion_ok) 4152 i++; /* companion channel already checked */ 4153 } 4154 4155 return 0; 4156 } 4157 4158 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, 4159 hda_nid_t pin_nid, int hdmi_slot, int stream_channel) 4160 { 4161 struct hda_codec *codec = hdac_to_hda_codec(hdac); 4162 int verb; 4163 int ati_channel_setup = 0; 4164 4165 if (hdmi_slot > 7) 4166 return -EINVAL; 4167 4168 if (!has_amd_full_remap_support(codec)) { 4169 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); 4170 4171 /* In case this is an odd slot but without stream channel, do not 4172 * disable the slot since the corresponding even slot could have a 4173 * channel. In case neither have a channel, the slot pair will be 4174 * disabled when this function is called for the even slot. */ 4175 if (hdmi_slot % 2 != 0 && stream_channel == 0xf) 4176 return 0; 4177 4178 hdmi_slot -= hdmi_slot % 2; 4179 4180 if (stream_channel != 0xf) 4181 stream_channel -= stream_channel % 2; 4182 } 4183 4184 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; 4185 4186 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ 4187 4188 if (stream_channel != 0xf) 4189 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; 4190 4191 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); 4192 } 4193 4194 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, 4195 hda_nid_t pin_nid, int asp_slot) 4196 { 4197 struct hda_codec *codec = hdac_to_hda_codec(hdac); 4198 bool was_odd = false; 4199 int ati_asp_slot = asp_slot; 4200 int verb; 4201 int ati_channel_setup; 4202 4203 if (asp_slot > 7) 4204 return -EINVAL; 4205 4206 if (!has_amd_full_remap_support(codec)) { 4207 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); 4208 if (ati_asp_slot % 2 != 0) { 4209 ati_asp_slot -= 1; 4210 was_odd = true; 4211 } 4212 } 4213 4214 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; 4215 4216 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); 4217 4218 if (!(ati_channel_setup & ATI_OUT_ENABLE)) 4219 return 0xf; 4220 4221 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; 4222 } 4223 4224 static int atihdmi_paired_chmap_cea_alloc_validate_get_type( 4225 struct hdac_chmap *chmap, 4226 struct hdac_cea_channel_speaker_allocation *cap, 4227 int channels) 4228 { 4229 int c; 4230 4231 /* 4232 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so 4233 * we need to take that into account (a single channel may take 2 4234 * channel slots if we need to carry a silent channel next to it). 4235 * On Rev3+ AMD codecs this function is not used. 4236 */ 4237 int chanpairs = 0; 4238 4239 /* We only produce even-numbered channel count TLVs */ 4240 if ((channels % 2) != 0) 4241 return -1; 4242 4243 for (c = 0; c < 7; c += 2) { 4244 if (cap->speakers[c] || cap->speakers[c+1]) 4245 chanpairs++; 4246 } 4247 4248 if (chanpairs * 2 != channels) 4249 return -1; 4250 4251 return SNDRV_CTL_TLVT_CHMAP_PAIRED; 4252 } 4253 4254 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, 4255 struct hdac_cea_channel_speaker_allocation *cap, 4256 unsigned int *chmap, int channels) 4257 { 4258 /* produce paired maps for pre-rev3 ATI/AMD codecs */ 4259 int count = 0; 4260 int c; 4261 4262 for (c = 7; c >= 0; c--) { 4263 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); 4264 int spk = cap->speakers[chan]; 4265 if (!spk) { 4266 /* add N/A channel if the companion channel is occupied */ 4267 if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) 4268 chmap[count++] = SNDRV_CHMAP_NA; 4269 4270 continue; 4271 } 4272 4273 chmap[count++] = snd_hdac_spk_to_chmap(spk); 4274 } 4275 4276 WARN_ON(count != channels); 4277 } 4278 4279 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 4280 int dev_id, bool hbr) 4281 { 4282 int hbr_ctl, hbr_ctl_new; 4283 4284 WARN_ON(dev_id != 0); 4285 4286 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); 4287 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { 4288 if (hbr) 4289 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; 4290 else 4291 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; 4292 4293 codec_dbg(codec, 4294 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", 4295 pin_nid, 4296 hbr_ctl == hbr_ctl_new ? "" : "new-", 4297 hbr_ctl_new); 4298 4299 if (hbr_ctl != hbr_ctl_new) 4300 snd_hda_codec_write(codec, pin_nid, 0, 4301 ATI_VERB_SET_HBR_CONTROL, 4302 hbr_ctl_new); 4303 4304 } else if (hbr) 4305 return -EINVAL; 4306 4307 return 0; 4308 } 4309 4310 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 4311 hda_nid_t pin_nid, int dev_id, 4312 u32 stream_tag, int format) 4313 { 4314 if (is_amdhdmi_rev3_or_later(codec)) { 4315 int ramp_rate = 180; /* default as per AMD spec */ 4316 /* disable ramp-up/down for non-pcm as per AMD spec */ 4317 if (format & AC_FMT_TYPE_NON_PCM) 4318 ramp_rate = 0; 4319 4320 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); 4321 } 4322 4323 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 4324 stream_tag, format); 4325 } 4326 4327 4328 static int atihdmi_init(struct hda_codec *codec) 4329 { 4330 struct hdmi_spec *spec = codec->spec; 4331 int pin_idx, err; 4332 4333 err = generic_hdmi_init(codec); 4334 4335 if (err) 4336 return err; 4337 4338 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 4339 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 4340 4341 /* make sure downmix information in infoframe is zero */ 4342 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); 4343 4344 /* enable channel-wise remap mode if supported */ 4345 if (has_amd_full_remap_support(codec)) 4346 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 4347 ATI_VERB_SET_MULTICHANNEL_MODE, 4348 ATI_MULTICHANNEL_MODE_SINGLE); 4349 } 4350 codec->auto_runtime_pm = 1; 4351 4352 return 0; 4353 } 4354 4355 /* map from pin NID to port; port is 0-based */ 4356 /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */ 4357 static int atihdmi_pin2port(void *audio_ptr, int pin_nid) 4358 { 4359 return pin_nid / 2 - 1; 4360 } 4361 4362 /* reverse-map from port to pin NID: see above */ 4363 static int atihdmi_port2pin(struct hda_codec *codec, int port) 4364 { 4365 return port * 2 + 3; 4366 } 4367 4368 static const struct drm_audio_component_audio_ops atihdmi_audio_ops = { 4369 .pin2port = atihdmi_pin2port, 4370 .pin_eld_notify = generic_acomp_pin_eld_notify, 4371 .master_bind = generic_acomp_master_bind, 4372 .master_unbind = generic_acomp_master_unbind, 4373 }; 4374 4375 static int patch_atihdmi(struct hda_codec *codec) 4376 { 4377 struct hdmi_spec *spec; 4378 struct hdmi_spec_per_cvt *per_cvt; 4379 int err, cvt_idx; 4380 4381 err = patch_generic_hdmi(codec); 4382 4383 if (err) 4384 return err; 4385 4386 codec->patch_ops.init = atihdmi_init; 4387 4388 spec = codec->spec; 4389 4390 spec->ops.pin_get_eld = atihdmi_pin_get_eld; 4391 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; 4392 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; 4393 spec->ops.setup_stream = atihdmi_setup_stream; 4394 4395 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; 4396 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; 4397 4398 if (!has_amd_full_remap_support(codec)) { 4399 /* override to ATI/AMD-specific versions with pairwise mapping */ 4400 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4401 atihdmi_paired_chmap_cea_alloc_validate_get_type; 4402 spec->chmap.ops.cea_alloc_to_tlv_chmap = 4403 atihdmi_paired_cea_alloc_to_tlv_chmap; 4404 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; 4405 } 4406 4407 /* ATI/AMD converters do not advertise all of their capabilities */ 4408 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 4409 per_cvt = get_cvt(spec, cvt_idx); 4410 per_cvt->channels_max = max(per_cvt->channels_max, 8u); 4411 per_cvt->rates |= SUPPORTED_RATES; 4412 per_cvt->formats |= SUPPORTED_FORMATS; 4413 per_cvt->maxbps = max(per_cvt->maxbps, 24u); 4414 } 4415 4416 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); 4417 4418 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing 4419 * the link-down as is. Tell the core to allow it. 4420 */ 4421 codec->link_down_at_suspend = 1; 4422 4423 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin); 4424 4425 return 0; 4426 } 4427 4428 /* VIA HDMI Implementation */ 4429 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ 4430 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ 4431 4432 static int patch_via_hdmi(struct hda_codec *codec) 4433 { 4434 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); 4435 } 4436 4437 /* 4438 * patch entries 4439 */ 4440 static const struct hda_device_id snd_hda_id_hdmi[] = { 4441 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), 4442 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), 4443 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), 4444 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), 4445 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), 4446 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), 4447 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), 4448 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch), 4449 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4450 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4451 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x), 4452 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4453 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4454 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), 4455 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy), 4456 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy), 4457 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy), 4458 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy), 4459 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy), 4460 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy), 4461 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy), 4462 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy), 4463 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy), 4464 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy), 4465 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy), 4466 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy), 4467 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy), 4468 /* 17 is known to be absent */ 4469 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy), 4470 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy), 4471 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy), 4472 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy), 4473 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy), 4474 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), 4475 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), 4476 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), 4477 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), 4478 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi), 4479 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi), 4480 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), 4481 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), 4482 HDA_CODEC_ENTRY(0x10de0031, "Tegra234 HDMI/DP", patch_tegra234_hdmi), 4483 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), 4484 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), 4485 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), 4486 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), 4487 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), 4488 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi), 4489 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi), 4490 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), 4491 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi), 4492 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), 4493 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi), 4494 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi), 4495 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), 4496 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), 4497 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), 4498 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), 4499 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi), 4500 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi), 4501 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi), 4502 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi), 4503 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi), 4504 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), 4505 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi), 4506 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), 4507 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi), 4508 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), 4509 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), 4510 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi), 4511 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi), 4512 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi), 4513 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi), 4514 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi), 4515 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi), 4516 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi), 4517 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi), 4518 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), 4519 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), 4520 HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi), 4521 HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi), 4522 HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi), 4523 HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi), 4524 HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi), 4525 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), 4526 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), 4527 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), 4528 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), 4529 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), 4530 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), 4531 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4532 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), 4533 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), 4534 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), 4535 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), 4536 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4537 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), 4538 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), 4539 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), 4540 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), 4541 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), 4542 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), 4543 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), 4544 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), 4545 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), 4546 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi), 4547 HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi), 4548 HDA_CODEC_ENTRY(0x80862814, "DG1 HDMI", patch_i915_tgl_hdmi), 4549 HDA_CODEC_ENTRY(0x80862815, "Alderlake HDMI", patch_i915_tgl_hdmi), 4550 HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI", patch_i915_tgl_hdmi), 4551 HDA_CODEC_ENTRY(0x80862818, "Raptorlake HDMI", patch_i915_tgl_hdmi), 4552 HDA_CODEC_ENTRY(0x80862819, "DG2 HDMI", patch_i915_adlp_hdmi), 4553 HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi), 4554 HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi), 4555 HDA_CODEC_ENTRY(0x8086281c, "Alderlake-P HDMI", patch_i915_adlp_hdmi), 4556 HDA_CODEC_ENTRY(0x8086281f, "Raptorlake-P HDMI", patch_i915_adlp_hdmi), 4557 HDA_CODEC_ENTRY(0x8086281d, "Meteorlake HDMI", patch_i915_adlp_hdmi), 4558 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), 4559 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), 4560 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), 4561 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), 4562 /* special ID for generic HDMI */ 4563 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), 4564 {} /* terminator */ 4565 }; 4566 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); 4567 4568 MODULE_LICENSE("GPL"); 4569 MODULE_DESCRIPTION("HDMI HD-audio codec"); 4570 MODULE_ALIAS("snd-hda-codec-intelhdmi"); 4571 MODULE_ALIAS("snd-hda-codec-nvhdmi"); 4572 MODULE_ALIAS("snd-hda-codec-atihdmi"); 4573 4574 static struct hda_codec_driver hdmi_driver = { 4575 .id = snd_hda_id_hdmi, 4576 }; 4577 4578 module_hda_codec_driver(hdmi_driver); 4579