1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs 5 * 6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. 7 * Copyright (c) 2006 ATI Technologies Inc. 8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved. 9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com> 10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> 11 * 12 * Authors: 13 * Wu Fengguang <wfg@linux.intel.com> 14 * 15 * Maintained by: 16 * Wu Fengguang <wfg@linux.intel.com> 17 */ 18 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/slab.h> 22 #include <linux/module.h> 23 #include <linux/pm_runtime.h> 24 #include <sound/core.h> 25 #include <sound/jack.h> 26 #include <sound/asoundef.h> 27 #include <sound/tlv.h> 28 #include <sound/hdaudio.h> 29 #include <sound/hda_i915.h> 30 #include <sound/hda_chmap.h> 31 #include <sound/hda_codec.h> 32 #include "hda_local.h" 33 #include "hda_jack.h" 34 35 static bool static_hdmi_pcm; 36 module_param(static_hdmi_pcm, bool, 0644); 37 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); 38 39 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807) 40 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808) 41 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809) 42 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a) 43 #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b) 44 #define is_geminilake(codec) (((codec)->core.vendor_id == 0x8086280d) || \ 45 ((codec)->core.vendor_id == 0x80862800)) 46 #define is_cannonlake(codec) ((codec)->core.vendor_id == 0x8086280c) 47 #define is_icelake(codec) ((codec)->core.vendor_id == 0x8086280f) 48 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \ 49 || is_skylake(codec) || is_broxton(codec) \ 50 || is_kabylake(codec) || is_geminilake(codec) \ 51 || is_cannonlake(codec) || is_icelake(codec)) 52 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882) 53 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883) 54 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec)) 55 56 struct hdmi_spec_per_cvt { 57 hda_nid_t cvt_nid; 58 int assigned; 59 unsigned int channels_min; 60 unsigned int channels_max; 61 u32 rates; 62 u64 formats; 63 unsigned int maxbps; 64 }; 65 66 /* max. connections to a widget */ 67 #define HDA_MAX_CONNECTIONS 32 68 69 struct hdmi_spec_per_pin { 70 hda_nid_t pin_nid; 71 int dev_id; 72 /* pin idx, different device entries on the same pin use the same idx */ 73 int pin_nid_idx; 74 int num_mux_nids; 75 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; 76 int mux_idx; 77 hda_nid_t cvt_nid; 78 79 struct hda_codec *codec; 80 struct hdmi_eld sink_eld; 81 struct mutex lock; 82 struct delayed_work work; 83 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ 84 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ 85 int repoll_count; 86 bool setup; /* the stream has been set up by prepare callback */ 87 int channels; /* current number of channels */ 88 bool non_pcm; 89 bool chmap_set; /* channel-map override by ALSA API? */ 90 unsigned char chmap[8]; /* ALSA API channel-map */ 91 #ifdef CONFIG_SND_PROC_FS 92 struct snd_info_entry *proc_entry; 93 #endif 94 }; 95 96 /* operations used by generic code that can be overridden by patches */ 97 struct hdmi_ops { 98 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, 99 unsigned char *buf, int *eld_size); 100 101 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, 102 int ca, int active_channels, int conn_type); 103 104 /* enable/disable HBR (HD passthrough) */ 105 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr); 106 107 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, 108 hda_nid_t pin_nid, u32 stream_tag, int format); 109 110 void (*pin_cvt_fixup)(struct hda_codec *codec, 111 struct hdmi_spec_per_pin *per_pin, 112 hda_nid_t cvt_nid); 113 }; 114 115 struct hdmi_pcm { 116 struct hda_pcm *pcm; 117 struct snd_jack *jack; 118 struct snd_kcontrol *eld_ctl; 119 }; 120 121 struct hdmi_spec { 122 int num_cvts; 123 struct snd_array cvts; /* struct hdmi_spec_per_cvt */ 124 hda_nid_t cvt_nids[4]; /* only for haswell fix */ 125 126 /* 127 * num_pins is the number of virtual pins 128 * for example, there are 3 pins, and each pin 129 * has 4 device entries, then the num_pins is 12 130 */ 131 int num_pins; 132 /* 133 * num_nids is the number of real pins 134 * In the above example, num_nids is 3 135 */ 136 int num_nids; 137 /* 138 * dev_num is the number of device entries 139 * on each pin. 140 * In the above example, dev_num is 4 141 */ 142 int dev_num; 143 struct snd_array pins; /* struct hdmi_spec_per_pin */ 144 struct hdmi_pcm pcm_rec[16]; 145 struct mutex pcm_lock; 146 /* pcm_bitmap means which pcms have been assigned to pins*/ 147 unsigned long pcm_bitmap; 148 int pcm_used; /* counter of pcm_rec[] */ 149 /* bitmap shows whether the pcm is opened in user space 150 * bit 0 means the first playback PCM (PCM3); 151 * bit 1 means the second playback PCM, and so on. 152 */ 153 unsigned long pcm_in_use; 154 155 struct hdmi_eld temp_eld; 156 struct hdmi_ops ops; 157 158 bool dyn_pin_out; 159 bool dyn_pcm_assign; 160 /* 161 * Non-generic VIA/NVIDIA specific 162 */ 163 struct hda_multi_out multiout; 164 struct hda_pcm_stream pcm_playback; 165 166 /* i915/powerwell (Haswell+/Valleyview+) specific */ 167 bool use_acomp_notifier; /* use i915 eld_notify callback for hotplug */ 168 struct drm_audio_component_audio_ops drm_audio_ops; 169 170 struct hdac_chmap chmap; 171 hda_nid_t vendor_nid; 172 const int *port_map; 173 int port_num; 174 }; 175 176 #ifdef CONFIG_SND_HDA_COMPONENT 177 static inline bool codec_has_acomp(struct hda_codec *codec) 178 { 179 struct hdmi_spec *spec = codec->spec; 180 return spec->use_acomp_notifier; 181 } 182 #else 183 #define codec_has_acomp(codec) false 184 #endif 185 186 struct hdmi_audio_infoframe { 187 u8 type; /* 0x84 */ 188 u8 ver; /* 0x01 */ 189 u8 len; /* 0x0a */ 190 191 u8 checksum; 192 193 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ 194 u8 SS01_SF24; 195 u8 CXT04; 196 u8 CA; 197 u8 LFEPBL01_LSV36_DM_INH7; 198 }; 199 200 struct dp_audio_infoframe { 201 u8 type; /* 0x84 */ 202 u8 len; /* 0x1b */ 203 u8 ver; /* 0x11 << 2 */ 204 205 u8 CC02_CT47; /* match with HDMI infoframe from this on */ 206 u8 SS01_SF24; 207 u8 CXT04; 208 u8 CA; 209 u8 LFEPBL01_LSV36_DM_INH7; 210 }; 211 212 union audio_infoframe { 213 struct hdmi_audio_infoframe hdmi; 214 struct dp_audio_infoframe dp; 215 u8 bytes[0]; 216 }; 217 218 /* 219 * HDMI routines 220 */ 221 222 #define get_pin(spec, idx) \ 223 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) 224 #define get_cvt(spec, idx) \ 225 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) 226 /* obtain hdmi_pcm object assigned to idx */ 227 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) 228 /* obtain hda_pcm object assigned to idx */ 229 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) 230 231 static int pin_id_to_pin_index(struct hda_codec *codec, 232 hda_nid_t pin_nid, int dev_id) 233 { 234 struct hdmi_spec *spec = codec->spec; 235 int pin_idx; 236 struct hdmi_spec_per_pin *per_pin; 237 238 /* 239 * (dev_id == -1) means it is NON-MST pin 240 * return the first virtual pin on this port 241 */ 242 if (dev_id == -1) 243 dev_id = 0; 244 245 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 246 per_pin = get_pin(spec, pin_idx); 247 if ((per_pin->pin_nid == pin_nid) && 248 (per_pin->dev_id == dev_id)) 249 return pin_idx; 250 } 251 252 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid); 253 return -EINVAL; 254 } 255 256 static int hinfo_to_pcm_index(struct hda_codec *codec, 257 struct hda_pcm_stream *hinfo) 258 { 259 struct hdmi_spec *spec = codec->spec; 260 int pcm_idx; 261 262 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) 263 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) 264 return pcm_idx; 265 266 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo); 267 return -EINVAL; 268 } 269 270 static int hinfo_to_pin_index(struct hda_codec *codec, 271 struct hda_pcm_stream *hinfo) 272 { 273 struct hdmi_spec *spec = codec->spec; 274 struct hdmi_spec_per_pin *per_pin; 275 int pin_idx; 276 277 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 278 per_pin = get_pin(spec, pin_idx); 279 if (per_pin->pcm && 280 per_pin->pcm->pcm->stream == hinfo) 281 return pin_idx; 282 } 283 284 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo); 285 return -EINVAL; 286 } 287 288 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, 289 int pcm_idx) 290 { 291 int i; 292 struct hdmi_spec_per_pin *per_pin; 293 294 for (i = 0; i < spec->num_pins; i++) { 295 per_pin = get_pin(spec, i); 296 if (per_pin->pcm_idx == pcm_idx) 297 return per_pin; 298 } 299 return NULL; 300 } 301 302 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) 303 { 304 struct hdmi_spec *spec = codec->spec; 305 int cvt_idx; 306 307 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) 308 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) 309 return cvt_idx; 310 311 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid); 312 return -EINVAL; 313 } 314 315 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, 316 struct snd_ctl_elem_info *uinfo) 317 { 318 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 319 struct hdmi_spec *spec = codec->spec; 320 struct hdmi_spec_per_pin *per_pin; 321 struct hdmi_eld *eld; 322 int pcm_idx; 323 324 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 325 326 pcm_idx = kcontrol->private_value; 327 mutex_lock(&spec->pcm_lock); 328 per_pin = pcm_idx_to_pin(spec, pcm_idx); 329 if (!per_pin) { 330 /* no pin is bound to the pcm */ 331 uinfo->count = 0; 332 goto unlock; 333 } 334 eld = &per_pin->sink_eld; 335 uinfo->count = eld->eld_valid ? eld->eld_size : 0; 336 337 unlock: 338 mutex_unlock(&spec->pcm_lock); 339 return 0; 340 } 341 342 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, 343 struct snd_ctl_elem_value *ucontrol) 344 { 345 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 346 struct hdmi_spec *spec = codec->spec; 347 struct hdmi_spec_per_pin *per_pin; 348 struct hdmi_eld *eld; 349 int pcm_idx; 350 int err = 0; 351 352 pcm_idx = kcontrol->private_value; 353 mutex_lock(&spec->pcm_lock); 354 per_pin = pcm_idx_to_pin(spec, pcm_idx); 355 if (!per_pin) { 356 /* no pin is bound to the pcm */ 357 memset(ucontrol->value.bytes.data, 0, 358 ARRAY_SIZE(ucontrol->value.bytes.data)); 359 goto unlock; 360 } 361 362 eld = &per_pin->sink_eld; 363 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || 364 eld->eld_size > ELD_MAX_SIZE) { 365 snd_BUG(); 366 err = -EINVAL; 367 goto unlock; 368 } 369 370 memset(ucontrol->value.bytes.data, 0, 371 ARRAY_SIZE(ucontrol->value.bytes.data)); 372 if (eld->eld_valid) 373 memcpy(ucontrol->value.bytes.data, eld->eld_buffer, 374 eld->eld_size); 375 376 unlock: 377 mutex_unlock(&spec->pcm_lock); 378 return err; 379 } 380 381 static const struct snd_kcontrol_new eld_bytes_ctl = { 382 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, 383 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 384 .name = "ELD", 385 .info = hdmi_eld_ctl_info, 386 .get = hdmi_eld_ctl_get, 387 }; 388 389 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, 390 int device) 391 { 392 struct snd_kcontrol *kctl; 393 struct hdmi_spec *spec = codec->spec; 394 int err; 395 396 kctl = snd_ctl_new1(&eld_bytes_ctl, codec); 397 if (!kctl) 398 return -ENOMEM; 399 kctl->private_value = pcm_idx; 400 kctl->id.device = device; 401 402 /* no pin nid is associated with the kctl now 403 * tbd: associate pin nid to eld ctl later 404 */ 405 err = snd_hda_ctl_add(codec, 0, kctl); 406 if (err < 0) 407 return err; 408 409 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; 410 return 0; 411 } 412 413 #ifdef BE_PARANOID 414 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 415 int *packet_index, int *byte_index) 416 { 417 int val; 418 419 val = snd_hda_codec_read(codec, pin_nid, 0, 420 AC_VERB_GET_HDMI_DIP_INDEX, 0); 421 422 *packet_index = val >> 5; 423 *byte_index = val & 0x1f; 424 } 425 #endif 426 427 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 428 int packet_index, int byte_index) 429 { 430 int val; 431 432 val = (packet_index << 5) | (byte_index & 0x1f); 433 434 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); 435 } 436 437 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, 438 unsigned char val) 439 { 440 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); 441 } 442 443 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) 444 { 445 struct hdmi_spec *spec = codec->spec; 446 int pin_out; 447 448 /* Unmute */ 449 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 450 snd_hda_codec_write(codec, pin_nid, 0, 451 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); 452 453 if (spec->dyn_pin_out) 454 /* Disable pin out until stream is active */ 455 pin_out = 0; 456 else 457 /* Enable pin out: some machines with GM965 gets broken output 458 * when the pin is disabled or changed while using with HDMI 459 */ 460 pin_out = PIN_OUT; 461 462 snd_hda_codec_write(codec, pin_nid, 0, 463 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); 464 } 465 466 /* 467 * ELD proc files 468 */ 469 470 #ifdef CONFIG_SND_PROC_FS 471 static void print_eld_info(struct snd_info_entry *entry, 472 struct snd_info_buffer *buffer) 473 { 474 struct hdmi_spec_per_pin *per_pin = entry->private_data; 475 476 mutex_lock(&per_pin->lock); 477 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer); 478 mutex_unlock(&per_pin->lock); 479 } 480 481 static void write_eld_info(struct snd_info_entry *entry, 482 struct snd_info_buffer *buffer) 483 { 484 struct hdmi_spec_per_pin *per_pin = entry->private_data; 485 486 mutex_lock(&per_pin->lock); 487 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); 488 mutex_unlock(&per_pin->lock); 489 } 490 491 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) 492 { 493 char name[32]; 494 struct hda_codec *codec = per_pin->codec; 495 struct snd_info_entry *entry; 496 int err; 497 498 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); 499 err = snd_card_proc_new(codec->card, name, &entry); 500 if (err < 0) 501 return err; 502 503 snd_info_set_text_ops(entry, per_pin, print_eld_info); 504 entry->c.text.write = write_eld_info; 505 entry->mode |= 0200; 506 per_pin->proc_entry = entry; 507 508 return 0; 509 } 510 511 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 512 { 513 if (!per_pin->codec->bus->shutdown) { 514 snd_info_free_entry(per_pin->proc_entry); 515 per_pin->proc_entry = NULL; 516 } 517 } 518 #else 519 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, 520 int index) 521 { 522 return 0; 523 } 524 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 525 { 526 } 527 #endif 528 529 /* 530 * Audio InfoFrame routines 531 */ 532 533 /* 534 * Enable Audio InfoFrame Transmission 535 */ 536 static void hdmi_start_infoframe_trans(struct hda_codec *codec, 537 hda_nid_t pin_nid) 538 { 539 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 540 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 541 AC_DIPXMIT_BEST); 542 } 543 544 /* 545 * Disable Audio InfoFrame Transmission 546 */ 547 static void hdmi_stop_infoframe_trans(struct hda_codec *codec, 548 hda_nid_t pin_nid) 549 { 550 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 551 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 552 AC_DIPXMIT_DISABLE); 553 } 554 555 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) 556 { 557 #ifdef CONFIG_SND_DEBUG_VERBOSE 558 int i; 559 int size; 560 561 size = snd_hdmi_get_eld_size(codec, pin_nid); 562 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); 563 564 for (i = 0; i < 8; i++) { 565 size = snd_hda_codec_read(codec, pin_nid, 0, 566 AC_VERB_GET_HDMI_DIP_SIZE, i); 567 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); 568 } 569 #endif 570 } 571 572 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) 573 { 574 #ifdef BE_PARANOID 575 int i, j; 576 int size; 577 int pi, bi; 578 for (i = 0; i < 8; i++) { 579 size = snd_hda_codec_read(codec, pin_nid, 0, 580 AC_VERB_GET_HDMI_DIP_SIZE, i); 581 if (size == 0) 582 continue; 583 584 hdmi_set_dip_index(codec, pin_nid, i, 0x0); 585 for (j = 1; j < 1000; j++) { 586 hdmi_write_dip_byte(codec, pin_nid, 0x0); 587 hdmi_get_dip_index(codec, pin_nid, &pi, &bi); 588 if (pi != i) 589 codec_dbg(codec, "dip index %d: %d != %d\n", 590 bi, pi, i); 591 if (bi == 0) /* byte index wrapped around */ 592 break; 593 } 594 codec_dbg(codec, 595 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", 596 i, size, j); 597 } 598 #endif 599 } 600 601 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) 602 { 603 u8 *bytes = (u8 *)hdmi_ai; 604 u8 sum = 0; 605 int i; 606 607 hdmi_ai->checksum = 0; 608 609 for (i = 0; i < sizeof(*hdmi_ai); i++) 610 sum += bytes[i]; 611 612 hdmi_ai->checksum = -sum; 613 } 614 615 static void hdmi_fill_audio_infoframe(struct hda_codec *codec, 616 hda_nid_t pin_nid, 617 u8 *dip, int size) 618 { 619 int i; 620 621 hdmi_debug_dip_size(codec, pin_nid); 622 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ 623 624 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 625 for (i = 0; i < size; i++) 626 hdmi_write_dip_byte(codec, pin_nid, dip[i]); 627 } 628 629 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, 630 u8 *dip, int size) 631 { 632 u8 val; 633 int i; 634 635 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) 636 != AC_DIPXMIT_BEST) 637 return false; 638 639 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 640 for (i = 0; i < size; i++) { 641 val = snd_hda_codec_read(codec, pin_nid, 0, 642 AC_VERB_GET_HDMI_DIP_DATA, 0); 643 if (val != dip[i]) 644 return false; 645 } 646 647 return true; 648 } 649 650 static void hdmi_pin_setup_infoframe(struct hda_codec *codec, 651 hda_nid_t pin_nid, 652 int ca, int active_channels, 653 int conn_type) 654 { 655 union audio_infoframe ai; 656 657 memset(&ai, 0, sizeof(ai)); 658 if (conn_type == 0) { /* HDMI */ 659 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; 660 661 hdmi_ai->type = 0x84; 662 hdmi_ai->ver = 0x01; 663 hdmi_ai->len = 0x0a; 664 hdmi_ai->CC02_CT47 = active_channels - 1; 665 hdmi_ai->CA = ca; 666 hdmi_checksum_audio_infoframe(hdmi_ai); 667 } else if (conn_type == 1) { /* DisplayPort */ 668 struct dp_audio_infoframe *dp_ai = &ai.dp; 669 670 dp_ai->type = 0x84; 671 dp_ai->len = 0x1b; 672 dp_ai->ver = 0x11 << 2; 673 dp_ai->CC02_CT47 = active_channels - 1; 674 dp_ai->CA = ca; 675 } else { 676 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n", 677 pin_nid); 678 return; 679 } 680 681 /* 682 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or 683 * sizeof(*dp_ai) to avoid partial match/update problems when 684 * the user switches between HDMI/DP monitors. 685 */ 686 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, 687 sizeof(ai))) { 688 codec_dbg(codec, 689 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n", 690 pin_nid, 691 active_channels, ca); 692 hdmi_stop_infoframe_trans(codec, pin_nid); 693 hdmi_fill_audio_infoframe(codec, pin_nid, 694 ai.bytes, sizeof(ai)); 695 hdmi_start_infoframe_trans(codec, pin_nid); 696 } 697 } 698 699 static void hdmi_setup_audio_infoframe(struct hda_codec *codec, 700 struct hdmi_spec_per_pin *per_pin, 701 bool non_pcm) 702 { 703 struct hdmi_spec *spec = codec->spec; 704 struct hdac_chmap *chmap = &spec->chmap; 705 hda_nid_t pin_nid = per_pin->pin_nid; 706 int channels = per_pin->channels; 707 int active_channels; 708 struct hdmi_eld *eld; 709 int ca; 710 711 if (!channels) 712 return; 713 714 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ 715 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 716 snd_hda_codec_write(codec, pin_nid, 0, 717 AC_VERB_SET_AMP_GAIN_MUTE, 718 AMP_OUT_UNMUTE); 719 720 eld = &per_pin->sink_eld; 721 722 ca = snd_hdac_channel_allocation(&codec->core, 723 eld->info.spk_alloc, channels, 724 per_pin->chmap_set, non_pcm, per_pin->chmap); 725 726 active_channels = snd_hdac_get_active_channels(ca); 727 728 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, 729 active_channels); 730 731 /* 732 * always configure channel mapping, it may have been changed by the 733 * user in the meantime 734 */ 735 snd_hdac_setup_channel_mapping(&spec->chmap, 736 pin_nid, non_pcm, ca, channels, 737 per_pin->chmap, per_pin->chmap_set); 738 739 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels, 740 eld->info.conn_type); 741 742 per_pin->non_pcm = non_pcm; 743 } 744 745 /* 746 * Unsolicited events 747 */ 748 749 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); 750 751 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, 752 int dev_id) 753 { 754 struct hdmi_spec *spec = codec->spec; 755 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); 756 757 if (pin_idx < 0) 758 return; 759 mutex_lock(&spec->pcm_lock); 760 if (hdmi_present_sense(get_pin(spec, pin_idx), 1)) 761 snd_hda_jack_report_sync(codec); 762 mutex_unlock(&spec->pcm_lock); 763 } 764 765 static void jack_callback(struct hda_codec *codec, 766 struct hda_jack_callback *jack) 767 { 768 /* hda_jack don't support DP MST */ 769 check_presence_and_report(codec, jack->nid, 0); 770 } 771 772 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res) 773 { 774 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 775 struct hda_jack_tbl *jack; 776 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 777 778 /* 779 * assume DP MST uses dyn_pcm_assign and acomp and 780 * never comes here 781 * if DP MST supports unsol event, below code need 782 * consider dev_entry 783 */ 784 jack = snd_hda_jack_tbl_get_from_tag(codec, tag); 785 if (!jack) 786 return; 787 jack->jack_dirty = 1; 788 789 codec_dbg(codec, 790 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", 791 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA), 792 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); 793 794 /* hda_jack don't support DP MST */ 795 check_presence_and_report(codec, jack->nid, 0); 796 } 797 798 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) 799 { 800 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 801 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 802 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); 803 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); 804 805 codec_info(codec, 806 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", 807 codec->addr, 808 tag, 809 subtag, 810 cp_state, 811 cp_ready); 812 813 /* TODO */ 814 if (cp_state) 815 ; 816 if (cp_ready) 817 ; 818 } 819 820 821 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) 822 { 823 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 824 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 825 826 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) { 827 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); 828 return; 829 } 830 831 if (subtag == 0) 832 hdmi_intrinsic_event(codec, res); 833 else 834 hdmi_non_intrinsic_event(codec, res); 835 } 836 837 static void haswell_verify_D0(struct hda_codec *codec, 838 hda_nid_t cvt_nid, hda_nid_t nid) 839 { 840 int pwr; 841 842 /* For Haswell, the converter 1/2 may keep in D3 state after bootup, 843 * thus pins could only choose converter 0 for use. Make sure the 844 * converters are in correct power state */ 845 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) 846 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); 847 848 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { 849 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, 850 AC_PWRST_D0); 851 msleep(40); 852 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); 853 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; 854 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr); 855 } 856 } 857 858 /* 859 * Callbacks 860 */ 861 862 /* HBR should be Non-PCM, 8 channels */ 863 #define is_hbr_format(format) \ 864 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) 865 866 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 867 bool hbr) 868 { 869 int pinctl, new_pinctl; 870 871 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { 872 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 873 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 874 875 if (pinctl < 0) 876 return hbr ? -EINVAL : 0; 877 878 new_pinctl = pinctl & ~AC_PINCTL_EPT; 879 if (hbr) 880 new_pinctl |= AC_PINCTL_EPT_HBR; 881 else 882 new_pinctl |= AC_PINCTL_EPT_NATIVE; 883 884 codec_dbg(codec, 885 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", 886 pin_nid, 887 pinctl == new_pinctl ? "" : "new-", 888 new_pinctl); 889 890 if (pinctl != new_pinctl) 891 snd_hda_codec_write(codec, pin_nid, 0, 892 AC_VERB_SET_PIN_WIDGET_CONTROL, 893 new_pinctl); 894 } else if (hbr) 895 return -EINVAL; 896 897 return 0; 898 } 899 900 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 901 hda_nid_t pin_nid, u32 stream_tag, int format) 902 { 903 struct hdmi_spec *spec = codec->spec; 904 unsigned int param; 905 int err; 906 907 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format)); 908 909 if (err) { 910 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); 911 return err; 912 } 913 914 if (is_haswell_plus(codec)) { 915 916 /* 917 * on recent platforms IEC Coding Type is required for HBR 918 * support, read current Digital Converter settings and set 919 * ICT bitfield if needed. 920 */ 921 param = snd_hda_codec_read(codec, cvt_nid, 0, 922 AC_VERB_GET_DIGI_CONVERT_1, 0); 923 924 param = (param >> 16) & ~(AC_DIG3_ICT); 925 926 /* on recent platforms ICT mode is required for HBR support */ 927 if (is_hbr_format(format)) 928 param |= 0x1; 929 930 snd_hda_codec_write(codec, cvt_nid, 0, 931 AC_VERB_SET_DIGI_CONVERT_3, param); 932 } 933 934 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); 935 return 0; 936 } 937 938 /* Try to find an available converter 939 * If pin_idx is less then zero, just try to find an available converter. 940 * Otherwise, try to find an available converter and get the cvt mux index 941 * of the pin. 942 */ 943 static int hdmi_choose_cvt(struct hda_codec *codec, 944 int pin_idx, int *cvt_id) 945 { 946 struct hdmi_spec *spec = codec->spec; 947 struct hdmi_spec_per_pin *per_pin; 948 struct hdmi_spec_per_cvt *per_cvt = NULL; 949 int cvt_idx, mux_idx = 0; 950 951 /* pin_idx < 0 means no pin will be bound to the converter */ 952 if (pin_idx < 0) 953 per_pin = NULL; 954 else 955 per_pin = get_pin(spec, pin_idx); 956 957 /* Dynamically assign converter to stream */ 958 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 959 per_cvt = get_cvt(spec, cvt_idx); 960 961 /* Must not already be assigned */ 962 if (per_cvt->assigned) 963 continue; 964 if (per_pin == NULL) 965 break; 966 /* Must be in pin's mux's list of converters */ 967 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 968 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) 969 break; 970 /* Not in mux list */ 971 if (mux_idx == per_pin->num_mux_nids) 972 continue; 973 break; 974 } 975 976 /* No free converters */ 977 if (cvt_idx == spec->num_cvts) 978 return -EBUSY; 979 980 if (per_pin != NULL) 981 per_pin->mux_idx = mux_idx; 982 983 if (cvt_id) 984 *cvt_id = cvt_idx; 985 986 return 0; 987 } 988 989 /* Assure the pin select the right convetor */ 990 static void intel_verify_pin_cvt_connect(struct hda_codec *codec, 991 struct hdmi_spec_per_pin *per_pin) 992 { 993 hda_nid_t pin_nid = per_pin->pin_nid; 994 int mux_idx, curr; 995 996 mux_idx = per_pin->mux_idx; 997 curr = snd_hda_codec_read(codec, pin_nid, 0, 998 AC_VERB_GET_CONNECT_SEL, 0); 999 if (curr != mux_idx) 1000 snd_hda_codec_write_cache(codec, pin_nid, 0, 1001 AC_VERB_SET_CONNECT_SEL, 1002 mux_idx); 1003 } 1004 1005 /* get the mux index for the converter of the pins 1006 * converter's mux index is the same for all pins on Intel platform 1007 */ 1008 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, 1009 hda_nid_t cvt_nid) 1010 { 1011 int i; 1012 1013 for (i = 0; i < spec->num_cvts; i++) 1014 if (spec->cvt_nids[i] == cvt_nid) 1015 return i; 1016 return -EINVAL; 1017 } 1018 1019 /* Intel HDMI workaround to fix audio routing issue: 1020 * For some Intel display codecs, pins share the same connection list. 1021 * So a conveter can be selected by multiple pins and playback on any of these 1022 * pins will generate sound on the external display, because audio flows from 1023 * the same converter to the display pipeline. Also muting one pin may make 1024 * other pins have no sound output. 1025 * So this function assures that an assigned converter for a pin is not selected 1026 * by any other pins. 1027 */ 1028 static void intel_not_share_assigned_cvt(struct hda_codec *codec, 1029 hda_nid_t pin_nid, 1030 int dev_id, int mux_idx) 1031 { 1032 struct hdmi_spec *spec = codec->spec; 1033 hda_nid_t nid; 1034 int cvt_idx, curr; 1035 struct hdmi_spec_per_cvt *per_cvt; 1036 struct hdmi_spec_per_pin *per_pin; 1037 int pin_idx; 1038 1039 /* configure the pins connections */ 1040 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 1041 int dev_id_saved; 1042 int dev_num; 1043 1044 per_pin = get_pin(spec, pin_idx); 1045 /* 1046 * pin not connected to monitor 1047 * no need to operate on it 1048 */ 1049 if (!per_pin->pcm) 1050 continue; 1051 1052 if ((per_pin->pin_nid == pin_nid) && 1053 (per_pin->dev_id == dev_id)) 1054 continue; 1055 1056 /* 1057 * if per_pin->dev_id >= dev_num, 1058 * snd_hda_get_dev_select() will fail, 1059 * and the following operation is unpredictable. 1060 * So skip this situation. 1061 */ 1062 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; 1063 if (per_pin->dev_id >= dev_num) 1064 continue; 1065 1066 nid = per_pin->pin_nid; 1067 1068 /* 1069 * Calling this function should not impact 1070 * on the device entry selection 1071 * So let's save the dev id for each pin, 1072 * and restore it when return 1073 */ 1074 dev_id_saved = snd_hda_get_dev_select(codec, nid); 1075 snd_hda_set_dev_select(codec, nid, per_pin->dev_id); 1076 curr = snd_hda_codec_read(codec, nid, 0, 1077 AC_VERB_GET_CONNECT_SEL, 0); 1078 if (curr != mux_idx) { 1079 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1080 continue; 1081 } 1082 1083 1084 /* choose an unassigned converter. The conveters in the 1085 * connection list are in the same order as in the codec. 1086 */ 1087 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1088 per_cvt = get_cvt(spec, cvt_idx); 1089 if (!per_cvt->assigned) { 1090 codec_dbg(codec, 1091 "choose cvt %d for pin nid %d\n", 1092 cvt_idx, nid); 1093 snd_hda_codec_write_cache(codec, nid, 0, 1094 AC_VERB_SET_CONNECT_SEL, 1095 cvt_idx); 1096 break; 1097 } 1098 } 1099 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1100 } 1101 } 1102 1103 /* A wrapper of intel_not_share_asigned_cvt() */ 1104 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, 1105 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) 1106 { 1107 int mux_idx; 1108 struct hdmi_spec *spec = codec->spec; 1109 1110 /* On Intel platform, the mapping of converter nid to 1111 * mux index of the pins are always the same. 1112 * The pin nid may be 0, this means all pins will not 1113 * share the converter. 1114 */ 1115 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); 1116 if (mux_idx >= 0) 1117 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); 1118 } 1119 1120 /* skeleton caller of pin_cvt_fixup ops */ 1121 static void pin_cvt_fixup(struct hda_codec *codec, 1122 struct hdmi_spec_per_pin *per_pin, 1123 hda_nid_t cvt_nid) 1124 { 1125 struct hdmi_spec *spec = codec->spec; 1126 1127 if (spec->ops.pin_cvt_fixup) 1128 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); 1129 } 1130 1131 /* called in hdmi_pcm_open when no pin is assigned to the PCM 1132 * in dyn_pcm_assign mode. 1133 */ 1134 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, 1135 struct hda_codec *codec, 1136 struct snd_pcm_substream *substream) 1137 { 1138 struct hdmi_spec *spec = codec->spec; 1139 struct snd_pcm_runtime *runtime = substream->runtime; 1140 int cvt_idx, pcm_idx; 1141 struct hdmi_spec_per_cvt *per_cvt = NULL; 1142 int err; 1143 1144 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1145 if (pcm_idx < 0) 1146 return -EINVAL; 1147 1148 err = hdmi_choose_cvt(codec, -1, &cvt_idx); 1149 if (err) 1150 return err; 1151 1152 per_cvt = get_cvt(spec, cvt_idx); 1153 per_cvt->assigned = 1; 1154 hinfo->nid = per_cvt->cvt_nid; 1155 1156 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); 1157 1158 set_bit(pcm_idx, &spec->pcm_in_use); 1159 /* todo: setup spdif ctls assign */ 1160 1161 /* Initially set the converter's capabilities */ 1162 hinfo->channels_min = per_cvt->channels_min; 1163 hinfo->channels_max = per_cvt->channels_max; 1164 hinfo->rates = per_cvt->rates; 1165 hinfo->formats = per_cvt->formats; 1166 hinfo->maxbps = per_cvt->maxbps; 1167 1168 /* Store the updated parameters */ 1169 runtime->hw.channels_min = hinfo->channels_min; 1170 runtime->hw.channels_max = hinfo->channels_max; 1171 runtime->hw.formats = hinfo->formats; 1172 runtime->hw.rates = hinfo->rates; 1173 1174 snd_pcm_hw_constraint_step(substream->runtime, 0, 1175 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1176 return 0; 1177 } 1178 1179 /* 1180 * HDA PCM callbacks 1181 */ 1182 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, 1183 struct hda_codec *codec, 1184 struct snd_pcm_substream *substream) 1185 { 1186 struct hdmi_spec *spec = codec->spec; 1187 struct snd_pcm_runtime *runtime = substream->runtime; 1188 int pin_idx, cvt_idx, pcm_idx; 1189 struct hdmi_spec_per_pin *per_pin; 1190 struct hdmi_eld *eld; 1191 struct hdmi_spec_per_cvt *per_cvt = NULL; 1192 int err; 1193 1194 /* Validate hinfo */ 1195 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1196 if (pcm_idx < 0) 1197 return -EINVAL; 1198 1199 mutex_lock(&spec->pcm_lock); 1200 pin_idx = hinfo_to_pin_index(codec, hinfo); 1201 if (!spec->dyn_pcm_assign) { 1202 if (snd_BUG_ON(pin_idx < 0)) { 1203 err = -EINVAL; 1204 goto unlock; 1205 } 1206 } else { 1207 /* no pin is assigned to the PCM 1208 * PA need pcm open successfully when probe 1209 */ 1210 if (pin_idx < 0) { 1211 err = hdmi_pcm_open_no_pin(hinfo, codec, substream); 1212 goto unlock; 1213 } 1214 } 1215 1216 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx); 1217 if (err < 0) 1218 goto unlock; 1219 1220 per_cvt = get_cvt(spec, cvt_idx); 1221 /* Claim converter */ 1222 per_cvt->assigned = 1; 1223 1224 set_bit(pcm_idx, &spec->pcm_in_use); 1225 per_pin = get_pin(spec, pin_idx); 1226 per_pin->cvt_nid = per_cvt->cvt_nid; 1227 hinfo->nid = per_cvt->cvt_nid; 1228 1229 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1230 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1231 AC_VERB_SET_CONNECT_SEL, 1232 per_pin->mux_idx); 1233 1234 /* configure unused pins to choose other converters */ 1235 pin_cvt_fixup(codec, per_pin, 0); 1236 1237 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); 1238 1239 /* Initially set the converter's capabilities */ 1240 hinfo->channels_min = per_cvt->channels_min; 1241 hinfo->channels_max = per_cvt->channels_max; 1242 hinfo->rates = per_cvt->rates; 1243 hinfo->formats = per_cvt->formats; 1244 hinfo->maxbps = per_cvt->maxbps; 1245 1246 eld = &per_pin->sink_eld; 1247 /* Restrict capabilities by ELD if this isn't disabled */ 1248 if (!static_hdmi_pcm && eld->eld_valid) { 1249 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); 1250 if (hinfo->channels_min > hinfo->channels_max || 1251 !hinfo->rates || !hinfo->formats) { 1252 per_cvt->assigned = 0; 1253 hinfo->nid = 0; 1254 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1255 err = -ENODEV; 1256 goto unlock; 1257 } 1258 } 1259 1260 /* Store the updated parameters */ 1261 runtime->hw.channels_min = hinfo->channels_min; 1262 runtime->hw.channels_max = hinfo->channels_max; 1263 runtime->hw.formats = hinfo->formats; 1264 runtime->hw.rates = hinfo->rates; 1265 1266 snd_pcm_hw_constraint_step(substream->runtime, 0, 1267 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1268 unlock: 1269 mutex_unlock(&spec->pcm_lock); 1270 return err; 1271 } 1272 1273 /* 1274 * HDA/HDMI auto parsing 1275 */ 1276 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) 1277 { 1278 struct hdmi_spec *spec = codec->spec; 1279 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1280 hda_nid_t pin_nid = per_pin->pin_nid; 1281 1282 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { 1283 codec_warn(codec, 1284 "HDMI: pin %d wcaps %#x does not support connection list\n", 1285 pin_nid, get_wcaps(codec, pin_nid)); 1286 return -EINVAL; 1287 } 1288 1289 /* all the device entries on the same pin have the same conn list */ 1290 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid, 1291 per_pin->mux_nids, 1292 HDA_MAX_CONNECTIONS); 1293 1294 return 0; 1295 } 1296 1297 static int hdmi_find_pcm_slot(struct hdmi_spec *spec, 1298 struct hdmi_spec_per_pin *per_pin) 1299 { 1300 int i; 1301 1302 /* try the prefer PCM */ 1303 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap)) 1304 return per_pin->pin_nid_idx; 1305 1306 /* have a second try; check the "reserved area" over num_pins */ 1307 for (i = spec->num_nids; i < spec->pcm_used; i++) { 1308 if (!test_bit(i, &spec->pcm_bitmap)) 1309 return i; 1310 } 1311 1312 /* the last try; check the empty slots in pins */ 1313 for (i = 0; i < spec->num_nids; i++) { 1314 if (!test_bit(i, &spec->pcm_bitmap)) 1315 return i; 1316 } 1317 return -EBUSY; 1318 } 1319 1320 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, 1321 struct hdmi_spec_per_pin *per_pin) 1322 { 1323 int idx; 1324 1325 /* pcm already be attached to the pin */ 1326 if (per_pin->pcm) 1327 return; 1328 idx = hdmi_find_pcm_slot(spec, per_pin); 1329 if (idx == -EBUSY) 1330 return; 1331 per_pin->pcm_idx = idx; 1332 per_pin->pcm = get_hdmi_pcm(spec, idx); 1333 set_bit(idx, &spec->pcm_bitmap); 1334 } 1335 1336 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, 1337 struct hdmi_spec_per_pin *per_pin) 1338 { 1339 int idx; 1340 1341 /* pcm already be detached from the pin */ 1342 if (!per_pin->pcm) 1343 return; 1344 idx = per_pin->pcm_idx; 1345 per_pin->pcm_idx = -1; 1346 per_pin->pcm = NULL; 1347 if (idx >= 0 && idx < spec->pcm_used) 1348 clear_bit(idx, &spec->pcm_bitmap); 1349 } 1350 1351 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, 1352 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) 1353 { 1354 int mux_idx; 1355 1356 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1357 if (per_pin->mux_nids[mux_idx] == cvt_nid) 1358 break; 1359 return mux_idx; 1360 } 1361 1362 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); 1363 1364 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, 1365 struct hdmi_spec_per_pin *per_pin) 1366 { 1367 struct hda_codec *codec = per_pin->codec; 1368 struct hda_pcm *pcm; 1369 struct hda_pcm_stream *hinfo; 1370 struct snd_pcm_substream *substream; 1371 int mux_idx; 1372 bool non_pcm; 1373 1374 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1375 pcm = get_pcm_rec(spec, per_pin->pcm_idx); 1376 else 1377 return; 1378 if (!pcm->pcm) 1379 return; 1380 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) 1381 return; 1382 1383 /* hdmi audio only uses playback and one substream */ 1384 hinfo = pcm->stream; 1385 substream = pcm->pcm->streams[0].substream; 1386 1387 per_pin->cvt_nid = hinfo->nid; 1388 1389 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); 1390 if (mux_idx < per_pin->num_mux_nids) { 1391 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1392 per_pin->dev_id); 1393 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1394 AC_VERB_SET_CONNECT_SEL, 1395 mux_idx); 1396 } 1397 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); 1398 1399 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); 1400 if (substream->runtime) 1401 per_pin->channels = substream->runtime->channels; 1402 per_pin->setup = true; 1403 per_pin->mux_idx = mux_idx; 1404 1405 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1406 } 1407 1408 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, 1409 struct hdmi_spec_per_pin *per_pin) 1410 { 1411 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1412 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); 1413 1414 per_pin->chmap_set = false; 1415 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1416 1417 per_pin->setup = false; 1418 per_pin->channels = 0; 1419 } 1420 1421 /* update per_pin ELD from the given new ELD; 1422 * setup info frame and notification accordingly 1423 */ 1424 static void update_eld(struct hda_codec *codec, 1425 struct hdmi_spec_per_pin *per_pin, 1426 struct hdmi_eld *eld) 1427 { 1428 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 1429 struct hdmi_spec *spec = codec->spec; 1430 bool old_eld_valid = pin_eld->eld_valid; 1431 bool eld_changed; 1432 int pcm_idx = -1; 1433 1434 /* for monitor disconnection, save pcm_idx firstly */ 1435 pcm_idx = per_pin->pcm_idx; 1436 if (spec->dyn_pcm_assign) { 1437 if (eld->eld_valid) { 1438 hdmi_attach_hda_pcm(spec, per_pin); 1439 hdmi_pcm_setup_pin(spec, per_pin); 1440 } else { 1441 hdmi_pcm_reset_pin(spec, per_pin); 1442 hdmi_detach_hda_pcm(spec, per_pin); 1443 } 1444 } 1445 /* if pcm_idx == -1, it means this is in monitor connection event 1446 * we can get the correct pcm_idx now. 1447 */ 1448 if (pcm_idx == -1) 1449 pcm_idx = per_pin->pcm_idx; 1450 1451 if (eld->eld_valid) 1452 snd_hdmi_show_eld(codec, &eld->info); 1453 1454 eld_changed = (pin_eld->eld_valid != eld->eld_valid); 1455 if (eld->eld_valid && pin_eld->eld_valid) 1456 if (pin_eld->eld_size != eld->eld_size || 1457 memcmp(pin_eld->eld_buffer, eld->eld_buffer, 1458 eld->eld_size) != 0) 1459 eld_changed = true; 1460 1461 pin_eld->monitor_present = eld->monitor_present; 1462 pin_eld->eld_valid = eld->eld_valid; 1463 pin_eld->eld_size = eld->eld_size; 1464 if (eld->eld_valid) 1465 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size); 1466 pin_eld->info = eld->info; 1467 1468 /* 1469 * Re-setup pin and infoframe. This is needed e.g. when 1470 * - sink is first plugged-in 1471 * - transcoder can change during stream playback on Haswell 1472 * and this can make HW reset converter selection on a pin. 1473 */ 1474 if (eld->eld_valid && !old_eld_valid && per_pin->setup) { 1475 pin_cvt_fixup(codec, per_pin, 0); 1476 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1477 } 1478 1479 if (eld_changed && pcm_idx >= 0) 1480 snd_ctl_notify(codec->card, 1481 SNDRV_CTL_EVENT_MASK_VALUE | 1482 SNDRV_CTL_EVENT_MASK_INFO, 1483 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); 1484 } 1485 1486 /* update ELD and jack state via HD-audio verbs */ 1487 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, 1488 int repoll) 1489 { 1490 struct hda_jack_tbl *jack; 1491 struct hda_codec *codec = per_pin->codec; 1492 struct hdmi_spec *spec = codec->spec; 1493 struct hdmi_eld *eld = &spec->temp_eld; 1494 hda_nid_t pin_nid = per_pin->pin_nid; 1495 /* 1496 * Always execute a GetPinSense verb here, even when called from 1497 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited 1498 * response's PD bit is not the real PD value, but indicates that 1499 * the real PD value changed. An older version of the HD-audio 1500 * specification worked this way. Hence, we just ignore the data in 1501 * the unsolicited response to avoid custom WARs. 1502 */ 1503 int present; 1504 bool ret; 1505 bool do_repoll = false; 1506 1507 present = snd_hda_pin_sense(codec, pin_nid); 1508 1509 mutex_lock(&per_pin->lock); 1510 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); 1511 if (eld->monitor_present) 1512 eld->eld_valid = !!(present & AC_PINSENSE_ELDV); 1513 else 1514 eld->eld_valid = false; 1515 1516 codec_dbg(codec, 1517 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n", 1518 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); 1519 1520 if (eld->eld_valid) { 1521 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer, 1522 &eld->eld_size) < 0) 1523 eld->eld_valid = false; 1524 else { 1525 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, 1526 eld->eld_size) < 0) 1527 eld->eld_valid = false; 1528 } 1529 if (!eld->eld_valid && repoll) 1530 do_repoll = true; 1531 } 1532 1533 if (do_repoll) 1534 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300)); 1535 else 1536 update_eld(codec, per_pin, eld); 1537 1538 ret = !repoll || !eld->monitor_present || eld->eld_valid; 1539 1540 jack = snd_hda_jack_tbl_get(codec, pin_nid); 1541 if (jack) { 1542 jack->block_report = !ret; 1543 jack->pin_sense = (eld->monitor_present && eld->eld_valid) ? 1544 AC_PINSENSE_PRESENCE : 0; 1545 } 1546 mutex_unlock(&per_pin->lock); 1547 return ret; 1548 } 1549 1550 static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec, 1551 struct hdmi_spec_per_pin *per_pin) 1552 { 1553 struct hdmi_spec *spec = codec->spec; 1554 struct snd_jack *jack = NULL; 1555 struct hda_jack_tbl *jack_tbl; 1556 1557 /* if !dyn_pcm_assign, get jack from hda_jack_tbl 1558 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not 1559 * NULL even after snd_hda_jack_tbl_clear() is called to 1560 * free snd_jack. This may cause access invalid memory 1561 * when calling snd_jack_report 1562 */ 1563 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign) 1564 jack = spec->pcm_rec[per_pin->pcm_idx].jack; 1565 else if (!spec->dyn_pcm_assign) { 1566 /* 1567 * jack tbl doesn't support DP MST 1568 * DP MST will use dyn_pcm_assign, 1569 * so DP MST will never come here 1570 */ 1571 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid); 1572 if (jack_tbl) 1573 jack = jack_tbl->jack; 1574 } 1575 return jack; 1576 } 1577 1578 /* update ELD and jack state via audio component */ 1579 static void sync_eld_via_acomp(struct hda_codec *codec, 1580 struct hdmi_spec_per_pin *per_pin) 1581 { 1582 struct hdmi_spec *spec = codec->spec; 1583 struct hdmi_eld *eld = &spec->temp_eld; 1584 struct snd_jack *jack = NULL; 1585 int size; 1586 1587 mutex_lock(&per_pin->lock); 1588 eld->monitor_present = false; 1589 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, 1590 per_pin->dev_id, &eld->monitor_present, 1591 eld->eld_buffer, ELD_MAX_SIZE); 1592 if (size > 0) { 1593 size = min(size, ELD_MAX_SIZE); 1594 if (snd_hdmi_parse_eld(codec, &eld->info, 1595 eld->eld_buffer, size) < 0) 1596 size = -EINVAL; 1597 } 1598 1599 if (size > 0) { 1600 eld->eld_valid = true; 1601 eld->eld_size = size; 1602 } else { 1603 eld->eld_valid = false; 1604 eld->eld_size = 0; 1605 } 1606 1607 /* pcm_idx >=0 before update_eld() means it is in monitor 1608 * disconnected event. Jack must be fetched before update_eld() 1609 */ 1610 jack = pin_idx_to_jack(codec, per_pin); 1611 update_eld(codec, per_pin, eld); 1612 if (jack == NULL) 1613 jack = pin_idx_to_jack(codec, per_pin); 1614 if (jack == NULL) 1615 goto unlock; 1616 snd_jack_report(jack, 1617 (eld->monitor_present && eld->eld_valid) ? 1618 SND_JACK_AVOUT : 0); 1619 unlock: 1620 mutex_unlock(&per_pin->lock); 1621 } 1622 1623 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) 1624 { 1625 struct hda_codec *codec = per_pin->codec; 1626 int ret; 1627 1628 /* no temporary power up/down needed for component notifier */ 1629 if (!codec_has_acomp(codec)) { 1630 ret = snd_hda_power_up_pm(codec); 1631 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) { 1632 snd_hda_power_down_pm(codec); 1633 return false; 1634 } 1635 } 1636 1637 if (codec_has_acomp(codec)) { 1638 sync_eld_via_acomp(codec, per_pin); 1639 ret = false; /* don't call snd_hda_jack_report_sync() */ 1640 } else { 1641 ret = hdmi_present_sense_via_verbs(per_pin, repoll); 1642 } 1643 1644 if (!codec_has_acomp(codec)) 1645 snd_hda_power_down_pm(codec); 1646 1647 return ret; 1648 } 1649 1650 static void hdmi_repoll_eld(struct work_struct *work) 1651 { 1652 struct hdmi_spec_per_pin *per_pin = 1653 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); 1654 struct hda_codec *codec = per_pin->codec; 1655 struct hdmi_spec *spec = codec->spec; 1656 struct hda_jack_tbl *jack; 1657 1658 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid); 1659 if (jack) 1660 jack->jack_dirty = 1; 1661 1662 if (per_pin->repoll_count++ > 6) 1663 per_pin->repoll_count = 0; 1664 1665 mutex_lock(&spec->pcm_lock); 1666 if (hdmi_present_sense(per_pin, per_pin->repoll_count)) 1667 snd_hda_jack_report_sync(per_pin->codec); 1668 mutex_unlock(&spec->pcm_lock); 1669 } 1670 1671 static void intel_haswell_fixup_connect_list(struct hda_codec *codec, 1672 hda_nid_t nid); 1673 1674 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) 1675 { 1676 struct hdmi_spec *spec = codec->spec; 1677 unsigned int caps, config; 1678 int pin_idx; 1679 struct hdmi_spec_per_pin *per_pin; 1680 int err; 1681 int dev_num, i; 1682 1683 caps = snd_hda_query_pin_caps(codec, pin_nid); 1684 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) 1685 return 0; 1686 1687 /* 1688 * For DP MST audio, Configuration Default is the same for 1689 * all device entries on the same pin 1690 */ 1691 config = snd_hda_codec_get_pincfg(codec, pin_nid); 1692 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE) 1693 return 0; 1694 1695 /* 1696 * To simplify the implementation, malloc all 1697 * the virtual pins in the initialization statically 1698 */ 1699 if (is_haswell_plus(codec)) { 1700 /* 1701 * On Intel platforms, device entries number is 1702 * changed dynamically. If there is a DP MST 1703 * hub connected, the device entries number is 3. 1704 * Otherwise, it is 1. 1705 * Here we manually set dev_num to 3, so that 1706 * we can initialize all the device entries when 1707 * bootup statically. 1708 */ 1709 dev_num = 3; 1710 spec->dev_num = 3; 1711 } else if (spec->dyn_pcm_assign && codec->dp_mst) { 1712 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; 1713 /* 1714 * spec->dev_num is the maxinum number of device entries 1715 * among all the pins 1716 */ 1717 spec->dev_num = (spec->dev_num > dev_num) ? 1718 spec->dev_num : dev_num; 1719 } else { 1720 /* 1721 * If the platform doesn't support DP MST, 1722 * manually set dev_num to 1. This means 1723 * the pin has only one device entry. 1724 */ 1725 dev_num = 1; 1726 spec->dev_num = 1; 1727 } 1728 1729 for (i = 0; i < dev_num; i++) { 1730 pin_idx = spec->num_pins; 1731 per_pin = snd_array_new(&spec->pins); 1732 1733 if (!per_pin) 1734 return -ENOMEM; 1735 1736 if (spec->dyn_pcm_assign) { 1737 per_pin->pcm = NULL; 1738 per_pin->pcm_idx = -1; 1739 } else { 1740 per_pin->pcm = get_hdmi_pcm(spec, pin_idx); 1741 per_pin->pcm_idx = pin_idx; 1742 } 1743 per_pin->pin_nid = pin_nid; 1744 per_pin->pin_nid_idx = spec->num_nids; 1745 per_pin->dev_id = i; 1746 per_pin->non_pcm = false; 1747 snd_hda_set_dev_select(codec, pin_nid, i); 1748 if (is_haswell_plus(codec)) 1749 intel_haswell_fixup_connect_list(codec, pin_nid); 1750 err = hdmi_read_pin_conn(codec, pin_idx); 1751 if (err < 0) 1752 return err; 1753 spec->num_pins++; 1754 } 1755 spec->num_nids++; 1756 1757 return 0; 1758 } 1759 1760 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1761 { 1762 struct hdmi_spec *spec = codec->spec; 1763 struct hdmi_spec_per_cvt *per_cvt; 1764 unsigned int chans; 1765 int err; 1766 1767 chans = get_wcaps(codec, cvt_nid); 1768 chans = get_wcaps_channels(chans); 1769 1770 per_cvt = snd_array_new(&spec->cvts); 1771 if (!per_cvt) 1772 return -ENOMEM; 1773 1774 per_cvt->cvt_nid = cvt_nid; 1775 per_cvt->channels_min = 2; 1776 if (chans <= 16) { 1777 per_cvt->channels_max = chans; 1778 if (chans > spec->chmap.channels_max) 1779 spec->chmap.channels_max = chans; 1780 } 1781 1782 err = snd_hda_query_supported_pcm(codec, cvt_nid, 1783 &per_cvt->rates, 1784 &per_cvt->formats, 1785 &per_cvt->maxbps); 1786 if (err < 0) 1787 return err; 1788 1789 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) 1790 spec->cvt_nids[spec->num_cvts] = cvt_nid; 1791 spec->num_cvts++; 1792 1793 return 0; 1794 } 1795 1796 static int hdmi_parse_codec(struct hda_codec *codec) 1797 { 1798 hda_nid_t nid; 1799 int i, nodes; 1800 1801 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid); 1802 if (!nid || nodes < 0) { 1803 codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); 1804 return -EINVAL; 1805 } 1806 1807 for (i = 0; i < nodes; i++, nid++) { 1808 unsigned int caps; 1809 unsigned int type; 1810 1811 caps = get_wcaps(codec, nid); 1812 type = get_wcaps_type(caps); 1813 1814 if (!(caps & AC_WCAP_DIGITAL)) 1815 continue; 1816 1817 switch (type) { 1818 case AC_WID_AUD_OUT: 1819 hdmi_add_cvt(codec, nid); 1820 break; 1821 case AC_WID_PIN: 1822 hdmi_add_pin(codec, nid); 1823 break; 1824 } 1825 } 1826 1827 return 0; 1828 } 1829 1830 /* 1831 */ 1832 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1833 { 1834 struct hda_spdif_out *spdif; 1835 bool non_pcm; 1836 1837 mutex_lock(&codec->spdif_mutex); 1838 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); 1839 /* Add sanity check to pass klockwork check. 1840 * This should never happen. 1841 */ 1842 if (WARN_ON(spdif == NULL)) 1843 return true; 1844 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); 1845 mutex_unlock(&codec->spdif_mutex); 1846 return non_pcm; 1847 } 1848 1849 /* 1850 * HDMI callbacks 1851 */ 1852 1853 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 1854 struct hda_codec *codec, 1855 unsigned int stream_tag, 1856 unsigned int format, 1857 struct snd_pcm_substream *substream) 1858 { 1859 hda_nid_t cvt_nid = hinfo->nid; 1860 struct hdmi_spec *spec = codec->spec; 1861 int pin_idx; 1862 struct hdmi_spec_per_pin *per_pin; 1863 hda_nid_t pin_nid; 1864 struct snd_pcm_runtime *runtime = substream->runtime; 1865 bool non_pcm; 1866 int pinctl, stripe; 1867 int err = 0; 1868 1869 mutex_lock(&spec->pcm_lock); 1870 pin_idx = hinfo_to_pin_index(codec, hinfo); 1871 if (spec->dyn_pcm_assign && pin_idx < 0) { 1872 /* when dyn_pcm_assign and pcm is not bound to a pin 1873 * skip pin setup and return 0 to make audio playback 1874 * be ongoing 1875 */ 1876 pin_cvt_fixup(codec, NULL, cvt_nid); 1877 snd_hda_codec_setup_stream(codec, cvt_nid, 1878 stream_tag, 0, format); 1879 goto unlock; 1880 } 1881 1882 if (snd_BUG_ON(pin_idx < 0)) { 1883 err = -EINVAL; 1884 goto unlock; 1885 } 1886 per_pin = get_pin(spec, pin_idx); 1887 pin_nid = per_pin->pin_nid; 1888 1889 /* Verify pin:cvt selections to avoid silent audio after S3. 1890 * After S3, the audio driver restores pin:cvt selections 1891 * but this can happen before gfx is ready and such selection 1892 * is overlooked by HW. Thus multiple pins can share a same 1893 * default convertor and mute control will affect each other, 1894 * which can cause a resumed audio playback become silent 1895 * after S3. 1896 */ 1897 pin_cvt_fixup(codec, per_pin, 0); 1898 1899 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ 1900 /* Todo: add DP1.2 MST audio support later */ 1901 if (codec_has_acomp(codec)) 1902 snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id, 1903 runtime->rate); 1904 1905 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); 1906 mutex_lock(&per_pin->lock); 1907 per_pin->channels = substream->runtime->channels; 1908 per_pin->setup = true; 1909 1910 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) { 1911 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core, 1912 substream); 1913 snd_hda_codec_write(codec, cvt_nid, 0, 1914 AC_VERB_SET_STRIPE_CONTROL, 1915 stripe); 1916 } 1917 1918 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1919 mutex_unlock(&per_pin->lock); 1920 if (spec->dyn_pin_out) { 1921 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 1922 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 1923 snd_hda_codec_write(codec, pin_nid, 0, 1924 AC_VERB_SET_PIN_WIDGET_CONTROL, 1925 pinctl | PIN_OUT); 1926 } 1927 1928 /* snd_hda_set_dev_select() has been called before */ 1929 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid, 1930 stream_tag, format); 1931 unlock: 1932 mutex_unlock(&spec->pcm_lock); 1933 return err; 1934 } 1935 1936 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 1937 struct hda_codec *codec, 1938 struct snd_pcm_substream *substream) 1939 { 1940 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 1941 return 0; 1942 } 1943 1944 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, 1945 struct hda_codec *codec, 1946 struct snd_pcm_substream *substream) 1947 { 1948 struct hdmi_spec *spec = codec->spec; 1949 int cvt_idx, pin_idx, pcm_idx; 1950 struct hdmi_spec_per_cvt *per_cvt; 1951 struct hdmi_spec_per_pin *per_pin; 1952 int pinctl; 1953 int err = 0; 1954 1955 if (hinfo->nid) { 1956 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1957 if (snd_BUG_ON(pcm_idx < 0)) 1958 return -EINVAL; 1959 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); 1960 if (snd_BUG_ON(cvt_idx < 0)) 1961 return -EINVAL; 1962 per_cvt = get_cvt(spec, cvt_idx); 1963 1964 snd_BUG_ON(!per_cvt->assigned); 1965 per_cvt->assigned = 0; 1966 hinfo->nid = 0; 1967 1968 mutex_lock(&spec->pcm_lock); 1969 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1970 clear_bit(pcm_idx, &spec->pcm_in_use); 1971 pin_idx = hinfo_to_pin_index(codec, hinfo); 1972 if (spec->dyn_pcm_assign && pin_idx < 0) 1973 goto unlock; 1974 1975 if (snd_BUG_ON(pin_idx < 0)) { 1976 err = -EINVAL; 1977 goto unlock; 1978 } 1979 per_pin = get_pin(spec, pin_idx); 1980 1981 if (spec->dyn_pin_out) { 1982 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 1983 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 1984 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 1985 AC_VERB_SET_PIN_WIDGET_CONTROL, 1986 pinctl & ~PIN_OUT); 1987 } 1988 1989 mutex_lock(&per_pin->lock); 1990 per_pin->chmap_set = false; 1991 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1992 1993 per_pin->setup = false; 1994 per_pin->channels = 0; 1995 mutex_unlock(&per_pin->lock); 1996 unlock: 1997 mutex_unlock(&spec->pcm_lock); 1998 } 1999 2000 return err; 2001 } 2002 2003 static const struct hda_pcm_ops generic_ops = { 2004 .open = hdmi_pcm_open, 2005 .close = hdmi_pcm_close, 2006 .prepare = generic_hdmi_playback_pcm_prepare, 2007 .cleanup = generic_hdmi_playback_pcm_cleanup, 2008 }; 2009 2010 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) 2011 { 2012 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2013 struct hdmi_spec *spec = codec->spec; 2014 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2015 2016 if (!per_pin) 2017 return 0; 2018 2019 return per_pin->sink_eld.info.spk_alloc; 2020 } 2021 2022 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, 2023 unsigned char *chmap) 2024 { 2025 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2026 struct hdmi_spec *spec = codec->spec; 2027 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2028 2029 /* chmap is already set to 0 in caller */ 2030 if (!per_pin) 2031 return; 2032 2033 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); 2034 } 2035 2036 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, 2037 unsigned char *chmap, int prepared) 2038 { 2039 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2040 struct hdmi_spec *spec = codec->spec; 2041 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2042 2043 if (!per_pin) 2044 return; 2045 mutex_lock(&per_pin->lock); 2046 per_pin->chmap_set = true; 2047 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); 2048 if (prepared) 2049 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 2050 mutex_unlock(&per_pin->lock); 2051 } 2052 2053 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) 2054 { 2055 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2056 struct hdmi_spec *spec = codec->spec; 2057 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2058 2059 return per_pin ? true:false; 2060 } 2061 2062 static int generic_hdmi_build_pcms(struct hda_codec *codec) 2063 { 2064 struct hdmi_spec *spec = codec->spec; 2065 int idx; 2066 2067 /* 2068 * for non-mst mode, pcm number is the same as before 2069 * for DP MST mode, pcm number is (nid number + dev_num - 1) 2070 * dev_num is the device entry number in a pin 2071 * 2072 */ 2073 for (idx = 0; idx < spec->num_nids + spec->dev_num - 1; idx++) { 2074 struct hda_pcm *info; 2075 struct hda_pcm_stream *pstr; 2076 2077 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); 2078 if (!info) 2079 return -ENOMEM; 2080 2081 spec->pcm_rec[idx].pcm = info; 2082 spec->pcm_used++; 2083 info->pcm_type = HDA_PCM_TYPE_HDMI; 2084 info->own_chmap = true; 2085 2086 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2087 pstr->substreams = 1; 2088 pstr->ops = generic_ops; 2089 /* pcm number is less than 16 */ 2090 if (spec->pcm_used >= 16) 2091 break; 2092 /* other pstr fields are set in open */ 2093 } 2094 2095 return 0; 2096 } 2097 2098 static void free_hdmi_jack_priv(struct snd_jack *jack) 2099 { 2100 struct hdmi_pcm *pcm = jack->private_data; 2101 2102 pcm->jack = NULL; 2103 } 2104 2105 static int add_hdmi_jack_kctl(struct hda_codec *codec, 2106 struct hdmi_spec *spec, 2107 int pcm_idx, 2108 const char *name) 2109 { 2110 struct snd_jack *jack; 2111 int err; 2112 2113 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack, 2114 true, false); 2115 if (err < 0) 2116 return err; 2117 2118 spec->pcm_rec[pcm_idx].jack = jack; 2119 jack->private_data = &spec->pcm_rec[pcm_idx]; 2120 jack->private_free = free_hdmi_jack_priv; 2121 return 0; 2122 } 2123 2124 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) 2125 { 2126 char hdmi_str[32] = "HDMI/DP"; 2127 struct hdmi_spec *spec = codec->spec; 2128 struct hdmi_spec_per_pin *per_pin; 2129 struct hda_jack_tbl *jack; 2130 int pcmdev = get_pcm_rec(spec, pcm_idx)->device; 2131 bool phantom_jack; 2132 int ret; 2133 2134 if (pcmdev > 0) 2135 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); 2136 2137 if (spec->dyn_pcm_assign) 2138 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str); 2139 2140 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */ 2141 /* if !dyn_pcm_assign, it must be non-MST mode. 2142 * This means pcms and pins are statically mapped. 2143 * And pcm_idx is pin_idx. 2144 */ 2145 per_pin = get_pin(spec, pcm_idx); 2146 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid); 2147 if (phantom_jack) 2148 strncat(hdmi_str, " Phantom", 2149 sizeof(hdmi_str) - strlen(hdmi_str) - 1); 2150 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 2151 phantom_jack, 0, NULL); 2152 if (ret < 0) 2153 return ret; 2154 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid); 2155 if (jack == NULL) 2156 return 0; 2157 /* assign jack->jack to pcm_rec[].jack to 2158 * align with dyn_pcm_assign mode 2159 */ 2160 spec->pcm_rec[pcm_idx].jack = jack->jack; 2161 return 0; 2162 } 2163 2164 static int generic_hdmi_build_controls(struct hda_codec *codec) 2165 { 2166 struct hdmi_spec *spec = codec->spec; 2167 int dev, err; 2168 int pin_idx, pcm_idx; 2169 2170 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2171 if (!get_pcm_rec(spec, pcm_idx)->pcm) { 2172 /* no PCM: mark this for skipping permanently */ 2173 set_bit(pcm_idx, &spec->pcm_bitmap); 2174 continue; 2175 } 2176 2177 err = generic_hdmi_build_jack(codec, pcm_idx); 2178 if (err < 0) 2179 return err; 2180 2181 /* create the spdif for each pcm 2182 * pin will be bound when monitor is connected 2183 */ 2184 if (spec->dyn_pcm_assign) 2185 err = snd_hda_create_dig_out_ctls(codec, 2186 0, spec->cvt_nids[0], 2187 HDA_PCM_TYPE_HDMI); 2188 else { 2189 struct hdmi_spec_per_pin *per_pin = 2190 get_pin(spec, pcm_idx); 2191 err = snd_hda_create_dig_out_ctls(codec, 2192 per_pin->pin_nid, 2193 per_pin->mux_nids[0], 2194 HDA_PCM_TYPE_HDMI); 2195 } 2196 if (err < 0) 2197 return err; 2198 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2199 2200 dev = get_pcm_rec(spec, pcm_idx)->device; 2201 if (dev != SNDRV_PCM_INVALID_DEVICE) { 2202 /* add control for ELD Bytes */ 2203 err = hdmi_create_eld_ctl(codec, pcm_idx, dev); 2204 if (err < 0) 2205 return err; 2206 } 2207 } 2208 2209 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2210 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2211 2212 hdmi_present_sense(per_pin, 0); 2213 } 2214 2215 /* add channel maps */ 2216 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2217 struct hda_pcm *pcm; 2218 2219 pcm = get_pcm_rec(spec, pcm_idx); 2220 if (!pcm || !pcm->pcm) 2221 break; 2222 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); 2223 if (err < 0) 2224 return err; 2225 } 2226 2227 return 0; 2228 } 2229 2230 static int generic_hdmi_init_per_pins(struct hda_codec *codec) 2231 { 2232 struct hdmi_spec *spec = codec->spec; 2233 int pin_idx; 2234 2235 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2236 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2237 2238 per_pin->codec = codec; 2239 mutex_init(&per_pin->lock); 2240 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); 2241 eld_proc_new(per_pin, pin_idx); 2242 } 2243 return 0; 2244 } 2245 2246 static int generic_hdmi_init(struct hda_codec *codec) 2247 { 2248 struct hdmi_spec *spec = codec->spec; 2249 int pin_idx; 2250 2251 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2252 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2253 hda_nid_t pin_nid = per_pin->pin_nid; 2254 int dev_id = per_pin->dev_id; 2255 2256 snd_hda_set_dev_select(codec, pin_nid, dev_id); 2257 hdmi_init_pin(codec, pin_nid); 2258 if (!codec_has_acomp(codec)) 2259 snd_hda_jack_detect_enable_callback(codec, pin_nid, 2260 codec->jackpoll_interval > 0 ? 2261 jack_callback : NULL); 2262 } 2263 return 0; 2264 } 2265 2266 static void hdmi_array_init(struct hdmi_spec *spec, int nums) 2267 { 2268 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); 2269 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); 2270 } 2271 2272 static void hdmi_array_free(struct hdmi_spec *spec) 2273 { 2274 snd_array_free(&spec->pins); 2275 snd_array_free(&spec->cvts); 2276 } 2277 2278 static void generic_spec_free(struct hda_codec *codec) 2279 { 2280 struct hdmi_spec *spec = codec->spec; 2281 2282 if (spec) { 2283 hdmi_array_free(spec); 2284 kfree(spec); 2285 codec->spec = NULL; 2286 } 2287 codec->dp_mst = false; 2288 } 2289 2290 static void generic_hdmi_free(struct hda_codec *codec) 2291 { 2292 struct hdmi_spec *spec = codec->spec; 2293 int pin_idx, pcm_idx; 2294 2295 if (codec_has_acomp(codec)) { 2296 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL); 2297 codec->relaxed_resume = 0; 2298 } 2299 2300 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2301 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2302 cancel_delayed_work_sync(&per_pin->work); 2303 eld_proc_free(per_pin); 2304 } 2305 2306 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2307 if (spec->pcm_rec[pcm_idx].jack == NULL) 2308 continue; 2309 if (spec->dyn_pcm_assign) 2310 snd_device_free(codec->card, 2311 spec->pcm_rec[pcm_idx].jack); 2312 else 2313 spec->pcm_rec[pcm_idx].jack = NULL; 2314 } 2315 2316 generic_spec_free(codec); 2317 } 2318 2319 #ifdef CONFIG_PM 2320 static int generic_hdmi_resume(struct hda_codec *codec) 2321 { 2322 struct hdmi_spec *spec = codec->spec; 2323 int pin_idx; 2324 2325 codec->patch_ops.init(codec); 2326 regcache_sync(codec->core.regmap); 2327 2328 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2329 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2330 hdmi_present_sense(per_pin, 1); 2331 } 2332 return 0; 2333 } 2334 #endif 2335 2336 static const struct hda_codec_ops generic_hdmi_patch_ops = { 2337 .init = generic_hdmi_init, 2338 .free = generic_hdmi_free, 2339 .build_pcms = generic_hdmi_build_pcms, 2340 .build_controls = generic_hdmi_build_controls, 2341 .unsol_event = hdmi_unsol_event, 2342 #ifdef CONFIG_PM 2343 .resume = generic_hdmi_resume, 2344 #endif 2345 }; 2346 2347 static const struct hdmi_ops generic_standard_hdmi_ops = { 2348 .pin_get_eld = snd_hdmi_get_eld, 2349 .pin_setup_infoframe = hdmi_pin_setup_infoframe, 2350 .pin_hbr_setup = hdmi_pin_hbr_setup, 2351 .setup_stream = hdmi_setup_stream, 2352 }; 2353 2354 /* allocate codec->spec and assign/initialize generic parser ops */ 2355 static int alloc_generic_hdmi(struct hda_codec *codec) 2356 { 2357 struct hdmi_spec *spec; 2358 2359 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2360 if (!spec) 2361 return -ENOMEM; 2362 2363 spec->ops = generic_standard_hdmi_ops; 2364 spec->dev_num = 1; /* initialize to 1 */ 2365 mutex_init(&spec->pcm_lock); 2366 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); 2367 2368 spec->chmap.ops.get_chmap = hdmi_get_chmap; 2369 spec->chmap.ops.set_chmap = hdmi_set_chmap; 2370 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; 2371 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc, 2372 2373 codec->spec = spec; 2374 hdmi_array_init(spec, 4); 2375 2376 codec->patch_ops = generic_hdmi_patch_ops; 2377 2378 return 0; 2379 } 2380 2381 /* generic HDMI parser */ 2382 static int patch_generic_hdmi(struct hda_codec *codec) 2383 { 2384 int err; 2385 2386 err = alloc_generic_hdmi(codec); 2387 if (err < 0) 2388 return err; 2389 2390 err = hdmi_parse_codec(codec); 2391 if (err < 0) { 2392 generic_spec_free(codec); 2393 return err; 2394 } 2395 2396 generic_hdmi_init_per_pins(codec); 2397 return 0; 2398 } 2399 2400 /* 2401 * Intel codec parsers and helpers 2402 */ 2403 2404 static void intel_haswell_fixup_connect_list(struct hda_codec *codec, 2405 hda_nid_t nid) 2406 { 2407 struct hdmi_spec *spec = codec->spec; 2408 hda_nid_t conns[4]; 2409 int nconns; 2410 2411 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns)); 2412 if (nconns == spec->num_cvts && 2413 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t))) 2414 return; 2415 2416 /* override pins connection list */ 2417 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid); 2418 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids); 2419 } 2420 2421 #define INTEL_GET_VENDOR_VERB 0xf81 2422 #define INTEL_SET_VENDOR_VERB 0x781 2423 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ 2424 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ 2425 2426 static void intel_haswell_enable_all_pins(struct hda_codec *codec, 2427 bool update_tree) 2428 { 2429 unsigned int vendor_param; 2430 struct hdmi_spec *spec = codec->spec; 2431 2432 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2433 INTEL_GET_VENDOR_VERB, 0); 2434 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) 2435 return; 2436 2437 vendor_param |= INTEL_EN_ALL_PIN_CVTS; 2438 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2439 INTEL_SET_VENDOR_VERB, vendor_param); 2440 if (vendor_param == -1) 2441 return; 2442 2443 if (update_tree) 2444 snd_hda_codec_update_widgets(codec); 2445 } 2446 2447 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) 2448 { 2449 unsigned int vendor_param; 2450 struct hdmi_spec *spec = codec->spec; 2451 2452 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2453 INTEL_GET_VENDOR_VERB, 0); 2454 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) 2455 return; 2456 2457 /* enable DP1.2 mode */ 2458 vendor_param |= INTEL_EN_DP12; 2459 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); 2460 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, 2461 INTEL_SET_VENDOR_VERB, vendor_param); 2462 } 2463 2464 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. 2465 * Otherwise you may get severe h/w communication errors. 2466 */ 2467 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, 2468 unsigned int power_state) 2469 { 2470 if (power_state == AC_PWRST_D0) { 2471 intel_haswell_enable_all_pins(codec, false); 2472 intel_haswell_fixup_enable_dp12(codec); 2473 } 2474 2475 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); 2476 snd_hda_codec_set_power_to_all(codec, fg, power_state); 2477 } 2478 2479 /* There is a fixed mapping between audio pin node and display port. 2480 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL: 2481 * Pin Widget 5 - PORT B (port = 1 in i915 driver) 2482 * Pin Widget 6 - PORT C (port = 2 in i915 driver) 2483 * Pin Widget 7 - PORT D (port = 3 in i915 driver) 2484 * 2485 * on VLV, ILK: 2486 * Pin Widget 4 - PORT B (port = 1 in i915 driver) 2487 * Pin Widget 5 - PORT C (port = 2 in i915 driver) 2488 * Pin Widget 6 - PORT D (port = 3 in i915 driver) 2489 */ 2490 static int intel_base_nid(struct hda_codec *codec) 2491 { 2492 switch (codec->core.vendor_id) { 2493 case 0x80860054: /* ILK */ 2494 case 0x80862804: /* ILK */ 2495 case 0x80862882: /* VLV */ 2496 return 4; 2497 default: 2498 return 5; 2499 } 2500 } 2501 2502 static int intel_pin2port(void *audio_ptr, int pin_nid) 2503 { 2504 struct hda_codec *codec = audio_ptr; 2505 struct hdmi_spec *spec = codec->spec; 2506 int base_nid, i; 2507 2508 if (!spec->port_num) { 2509 base_nid = intel_base_nid(codec); 2510 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3)) 2511 return -1; 2512 return pin_nid - base_nid + 1; /* intel port is 1-based */ 2513 } 2514 2515 /* 2516 * looking for the pin number in the mapping table and return 2517 * the index which indicate the port number 2518 */ 2519 for (i = 0; i < spec->port_num; i++) { 2520 if (pin_nid == spec->port_map[i]) 2521 return i + 1; 2522 } 2523 2524 /* return -1 if pin number exceeds our expectation */ 2525 codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid); 2526 return -1; 2527 } 2528 2529 static int intel_port2pin(struct hda_codec *codec, int port) 2530 { 2531 struct hdmi_spec *spec = codec->spec; 2532 2533 if (!spec->port_num) { 2534 /* we assume only from port-B to port-D */ 2535 if (port < 1 || port > 3) 2536 return 0; 2537 /* intel port is 1-based */ 2538 return port + intel_base_nid(codec) - 1; 2539 } 2540 2541 if (port < 1 || port > spec->port_num) 2542 return 0; 2543 return spec->port_map[port - 1]; 2544 } 2545 2546 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) 2547 { 2548 struct hda_codec *codec = audio_ptr; 2549 int pin_nid; 2550 int dev_id = pipe; 2551 2552 pin_nid = intel_port2pin(codec, port); 2553 if (!pin_nid) 2554 return; 2555 /* skip notification during system suspend (but not in runtime PM); 2556 * the state will be updated at resume 2557 */ 2558 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) 2559 return; 2560 /* ditto during suspend/resume process itself */ 2561 if (snd_hdac_is_in_pm(&codec->core)) 2562 return; 2563 2564 snd_hdac_i915_set_bclk(&codec->bus->core); 2565 check_presence_and_report(codec, pin_nid, dev_id); 2566 } 2567 2568 /* register i915 component pin_eld_notify callback */ 2569 static void register_i915_notifier(struct hda_codec *codec) 2570 { 2571 struct hdmi_spec *spec = codec->spec; 2572 2573 spec->use_acomp_notifier = true; 2574 spec->drm_audio_ops.audio_ptr = codec; 2575 /* intel_audio_codec_enable() or intel_audio_codec_disable() 2576 * will call pin_eld_notify with using audio_ptr pointer 2577 * We need make sure audio_ptr is really setup 2578 */ 2579 wmb(); 2580 spec->drm_audio_ops.pin2port = intel_pin2port; 2581 spec->drm_audio_ops.pin_eld_notify = intel_pin_eld_notify; 2582 snd_hdac_acomp_register_notifier(&codec->bus->core, 2583 &spec->drm_audio_ops); 2584 /* no need for forcible resume for jack check thanks to notifier */ 2585 codec->relaxed_resume = 1; 2586 } 2587 2588 /* setup_stream ops override for HSW+ */ 2589 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 2590 hda_nid_t pin_nid, u32 stream_tag, int format) 2591 { 2592 haswell_verify_D0(codec, cvt_nid, pin_nid); 2593 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format); 2594 } 2595 2596 /* pin_cvt_fixup ops override for HSW+ and VLV+ */ 2597 static void i915_pin_cvt_fixup(struct hda_codec *codec, 2598 struct hdmi_spec_per_pin *per_pin, 2599 hda_nid_t cvt_nid) 2600 { 2601 if (per_pin) { 2602 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2603 per_pin->dev_id); 2604 intel_verify_pin_cvt_connect(codec, per_pin); 2605 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, 2606 per_pin->dev_id, per_pin->mux_idx); 2607 } else { 2608 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); 2609 } 2610 } 2611 2612 /* precondition and allocation for Intel codecs */ 2613 static int alloc_intel_hdmi(struct hda_codec *codec) 2614 { 2615 /* requires i915 binding */ 2616 if (!codec->bus->core.audio_component) { 2617 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); 2618 /* set probe_id here to prevent generic fallback binding */ 2619 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE; 2620 return -ENODEV; 2621 } 2622 2623 return alloc_generic_hdmi(codec); 2624 } 2625 2626 /* parse and post-process for Intel codecs */ 2627 static int parse_intel_hdmi(struct hda_codec *codec) 2628 { 2629 int err; 2630 2631 err = hdmi_parse_codec(codec); 2632 if (err < 0) { 2633 generic_spec_free(codec); 2634 return err; 2635 } 2636 2637 generic_hdmi_init_per_pins(codec); 2638 register_i915_notifier(codec); 2639 return 0; 2640 } 2641 2642 /* Intel Haswell and onwards; audio component with eld notifier */ 2643 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid, 2644 const int *port_map, int port_num) 2645 { 2646 struct hdmi_spec *spec; 2647 int err; 2648 2649 err = alloc_intel_hdmi(codec); 2650 if (err < 0) 2651 return err; 2652 spec = codec->spec; 2653 codec->dp_mst = true; 2654 spec->dyn_pcm_assign = true; 2655 spec->vendor_nid = vendor_nid; 2656 spec->port_map = port_map; 2657 spec->port_num = port_num; 2658 2659 intel_haswell_enable_all_pins(codec, true); 2660 intel_haswell_fixup_enable_dp12(codec); 2661 2662 codec->display_power_control = 1; 2663 2664 codec->patch_ops.set_power_state = haswell_set_power_state; 2665 codec->depop_delay = 0; 2666 codec->auto_runtime_pm = 1; 2667 2668 spec->ops.setup_stream = i915_hsw_setup_stream; 2669 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2670 2671 return parse_intel_hdmi(codec); 2672 } 2673 2674 static int patch_i915_hsw_hdmi(struct hda_codec *codec) 2675 { 2676 return intel_hsw_common_init(codec, 0x08, NULL, 0); 2677 } 2678 2679 static int patch_i915_glk_hdmi(struct hda_codec *codec) 2680 { 2681 return intel_hsw_common_init(codec, 0x0b, NULL, 0); 2682 } 2683 2684 static int patch_i915_icl_hdmi(struct hda_codec *codec) 2685 { 2686 /* 2687 * pin to port mapping table where the value indicate the pin number and 2688 * the index indicate the port number with 1 base. 2689 */ 2690 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb}; 2691 2692 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map)); 2693 } 2694 2695 /* Intel Baytrail and Braswell; with eld notifier */ 2696 static int patch_i915_byt_hdmi(struct hda_codec *codec) 2697 { 2698 struct hdmi_spec *spec; 2699 int err; 2700 2701 err = alloc_intel_hdmi(codec); 2702 if (err < 0) 2703 return err; 2704 spec = codec->spec; 2705 2706 /* For Valleyview/Cherryview, only the display codec is in the display 2707 * power well and can use link_power ops to request/release the power. 2708 */ 2709 codec->display_power_control = 1; 2710 2711 codec->depop_delay = 0; 2712 codec->auto_runtime_pm = 1; 2713 2714 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2715 2716 return parse_intel_hdmi(codec); 2717 } 2718 2719 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ 2720 static int patch_i915_cpt_hdmi(struct hda_codec *codec) 2721 { 2722 int err; 2723 2724 err = alloc_intel_hdmi(codec); 2725 if (err < 0) 2726 return err; 2727 return parse_intel_hdmi(codec); 2728 } 2729 2730 /* 2731 * Shared non-generic implementations 2732 */ 2733 2734 static int simple_playback_build_pcms(struct hda_codec *codec) 2735 { 2736 struct hdmi_spec *spec = codec->spec; 2737 struct hda_pcm *info; 2738 unsigned int chans; 2739 struct hda_pcm_stream *pstr; 2740 struct hdmi_spec_per_cvt *per_cvt; 2741 2742 per_cvt = get_cvt(spec, 0); 2743 chans = get_wcaps(codec, per_cvt->cvt_nid); 2744 chans = get_wcaps_channels(chans); 2745 2746 info = snd_hda_codec_pcm_new(codec, "HDMI 0"); 2747 if (!info) 2748 return -ENOMEM; 2749 spec->pcm_rec[0].pcm = info; 2750 info->pcm_type = HDA_PCM_TYPE_HDMI; 2751 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2752 *pstr = spec->pcm_playback; 2753 pstr->nid = per_cvt->cvt_nid; 2754 if (pstr->channels_max <= 2 && chans && chans <= 16) 2755 pstr->channels_max = chans; 2756 2757 return 0; 2758 } 2759 2760 /* unsolicited event for jack sensing */ 2761 static void simple_hdmi_unsol_event(struct hda_codec *codec, 2762 unsigned int res) 2763 { 2764 snd_hda_jack_set_dirty_all(codec); 2765 snd_hda_jack_report_sync(codec); 2766 } 2767 2768 /* generic_hdmi_build_jack can be used for simple_hdmi, too, 2769 * as long as spec->pins[] is set correctly 2770 */ 2771 #define simple_hdmi_build_jack generic_hdmi_build_jack 2772 2773 static int simple_playback_build_controls(struct hda_codec *codec) 2774 { 2775 struct hdmi_spec *spec = codec->spec; 2776 struct hdmi_spec_per_cvt *per_cvt; 2777 int err; 2778 2779 per_cvt = get_cvt(spec, 0); 2780 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, 2781 per_cvt->cvt_nid, 2782 HDA_PCM_TYPE_HDMI); 2783 if (err < 0) 2784 return err; 2785 return simple_hdmi_build_jack(codec, 0); 2786 } 2787 2788 static int simple_playback_init(struct hda_codec *codec) 2789 { 2790 struct hdmi_spec *spec = codec->spec; 2791 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); 2792 hda_nid_t pin = per_pin->pin_nid; 2793 2794 snd_hda_codec_write(codec, pin, 0, 2795 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); 2796 /* some codecs require to unmute the pin */ 2797 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 2798 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, 2799 AMP_OUT_UNMUTE); 2800 snd_hda_jack_detect_enable(codec, pin); 2801 return 0; 2802 } 2803 2804 static void simple_playback_free(struct hda_codec *codec) 2805 { 2806 struct hdmi_spec *spec = codec->spec; 2807 2808 hdmi_array_free(spec); 2809 kfree(spec); 2810 } 2811 2812 /* 2813 * Nvidia specific implementations 2814 */ 2815 2816 #define Nv_VERB_SET_Channel_Allocation 0xF79 2817 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A 2818 #define Nv_VERB_SET_Audio_Protection_On 0xF98 2819 #define Nv_VERB_SET_Audio_Protection_Off 0xF99 2820 2821 #define nvhdmi_master_con_nid_7x 0x04 2822 #define nvhdmi_master_pin_nid_7x 0x05 2823 2824 static const hda_nid_t nvhdmi_con_nids_7x[4] = { 2825 /*front, rear, clfe, rear_surr */ 2826 0x6, 0x8, 0xa, 0xc, 2827 }; 2828 2829 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { 2830 /* set audio protect on */ 2831 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 2832 /* enable digital output on pin widget */ 2833 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2834 {} /* terminator */ 2835 }; 2836 2837 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { 2838 /* set audio protect on */ 2839 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 2840 /* enable digital output on pin widget */ 2841 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2842 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2843 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2844 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2845 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2846 {} /* terminator */ 2847 }; 2848 2849 #ifdef LIMITED_RATE_FMT_SUPPORT 2850 /* support only the safe format and rate */ 2851 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 2852 #define SUPPORTED_MAXBPS 16 2853 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE 2854 #else 2855 /* support all rates and formats */ 2856 #define SUPPORTED_RATES \ 2857 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ 2858 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ 2859 SNDRV_PCM_RATE_192000) 2860 #define SUPPORTED_MAXBPS 24 2861 #define SUPPORTED_FORMATS \ 2862 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 2863 #endif 2864 2865 static int nvhdmi_7x_init_2ch(struct hda_codec *codec) 2866 { 2867 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); 2868 return 0; 2869 } 2870 2871 static int nvhdmi_7x_init_8ch(struct hda_codec *codec) 2872 { 2873 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); 2874 return 0; 2875 } 2876 2877 static const unsigned int channels_2_6_8[] = { 2878 2, 6, 8 2879 }; 2880 2881 static const unsigned int channels_2_8[] = { 2882 2, 8 2883 }; 2884 2885 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { 2886 .count = ARRAY_SIZE(channels_2_6_8), 2887 .list = channels_2_6_8, 2888 .mask = 0, 2889 }; 2890 2891 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { 2892 .count = ARRAY_SIZE(channels_2_8), 2893 .list = channels_2_8, 2894 .mask = 0, 2895 }; 2896 2897 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, 2898 struct hda_codec *codec, 2899 struct snd_pcm_substream *substream) 2900 { 2901 struct hdmi_spec *spec = codec->spec; 2902 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; 2903 2904 switch (codec->preset->vendor_id) { 2905 case 0x10de0002: 2906 case 0x10de0003: 2907 case 0x10de0005: 2908 case 0x10de0006: 2909 hw_constraints_channels = &hw_constraints_2_8_channels; 2910 break; 2911 case 0x10de0007: 2912 hw_constraints_channels = &hw_constraints_2_6_8_channels; 2913 break; 2914 default: 2915 break; 2916 } 2917 2918 if (hw_constraints_channels != NULL) { 2919 snd_pcm_hw_constraint_list(substream->runtime, 0, 2920 SNDRV_PCM_HW_PARAM_CHANNELS, 2921 hw_constraints_channels); 2922 } else { 2923 snd_pcm_hw_constraint_step(substream->runtime, 0, 2924 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 2925 } 2926 2927 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 2928 } 2929 2930 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, 2931 struct hda_codec *codec, 2932 struct snd_pcm_substream *substream) 2933 { 2934 struct hdmi_spec *spec = codec->spec; 2935 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 2936 } 2937 2938 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 2939 struct hda_codec *codec, 2940 unsigned int stream_tag, 2941 unsigned int format, 2942 struct snd_pcm_substream *substream) 2943 { 2944 struct hdmi_spec *spec = codec->spec; 2945 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 2946 stream_tag, format, substream); 2947 } 2948 2949 static const struct hda_pcm_stream simple_pcm_playback = { 2950 .substreams = 1, 2951 .channels_min = 2, 2952 .channels_max = 2, 2953 .ops = { 2954 .open = simple_playback_pcm_open, 2955 .close = simple_playback_pcm_close, 2956 .prepare = simple_playback_pcm_prepare 2957 }, 2958 }; 2959 2960 static const struct hda_codec_ops simple_hdmi_patch_ops = { 2961 .build_controls = simple_playback_build_controls, 2962 .build_pcms = simple_playback_build_pcms, 2963 .init = simple_playback_init, 2964 .free = simple_playback_free, 2965 .unsol_event = simple_hdmi_unsol_event, 2966 }; 2967 2968 static int patch_simple_hdmi(struct hda_codec *codec, 2969 hda_nid_t cvt_nid, hda_nid_t pin_nid) 2970 { 2971 struct hdmi_spec *spec; 2972 struct hdmi_spec_per_cvt *per_cvt; 2973 struct hdmi_spec_per_pin *per_pin; 2974 2975 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2976 if (!spec) 2977 return -ENOMEM; 2978 2979 codec->spec = spec; 2980 hdmi_array_init(spec, 1); 2981 2982 spec->multiout.num_dacs = 0; /* no analog */ 2983 spec->multiout.max_channels = 2; 2984 spec->multiout.dig_out_nid = cvt_nid; 2985 spec->num_cvts = 1; 2986 spec->num_pins = 1; 2987 per_pin = snd_array_new(&spec->pins); 2988 per_cvt = snd_array_new(&spec->cvts); 2989 if (!per_pin || !per_cvt) { 2990 simple_playback_free(codec); 2991 return -ENOMEM; 2992 } 2993 per_cvt->cvt_nid = cvt_nid; 2994 per_pin->pin_nid = pin_nid; 2995 spec->pcm_playback = simple_pcm_playback; 2996 2997 codec->patch_ops = simple_hdmi_patch_ops; 2998 2999 return 0; 3000 } 3001 3002 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, 3003 int channels) 3004 { 3005 unsigned int chanmask; 3006 int chan = channels ? (channels - 1) : 1; 3007 3008 switch (channels) { 3009 default: 3010 case 0: 3011 case 2: 3012 chanmask = 0x00; 3013 break; 3014 case 4: 3015 chanmask = 0x08; 3016 break; 3017 case 6: 3018 chanmask = 0x0b; 3019 break; 3020 case 8: 3021 chanmask = 0x13; 3022 break; 3023 } 3024 3025 /* Set the audio infoframe channel allocation and checksum fields. The 3026 * channel count is computed implicitly by the hardware. */ 3027 snd_hda_codec_write(codec, 0x1, 0, 3028 Nv_VERB_SET_Channel_Allocation, chanmask); 3029 3030 snd_hda_codec_write(codec, 0x1, 0, 3031 Nv_VERB_SET_Info_Frame_Checksum, 3032 (0x71 - chan - chanmask)); 3033 } 3034 3035 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, 3036 struct hda_codec *codec, 3037 struct snd_pcm_substream *substream) 3038 { 3039 struct hdmi_spec *spec = codec->spec; 3040 int i; 3041 3042 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 3043 0, AC_VERB_SET_CHANNEL_STREAMID, 0); 3044 for (i = 0; i < 4; i++) { 3045 /* set the stream id */ 3046 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3047 AC_VERB_SET_CHANNEL_STREAMID, 0); 3048 /* set the stream format */ 3049 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3050 AC_VERB_SET_STREAM_FORMAT, 0); 3051 } 3052 3053 /* The audio hardware sends a channel count of 0x7 (8ch) when all the 3054 * streams are disabled. */ 3055 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3056 3057 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3058 } 3059 3060 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, 3061 struct hda_codec *codec, 3062 unsigned int stream_tag, 3063 unsigned int format, 3064 struct snd_pcm_substream *substream) 3065 { 3066 int chs; 3067 unsigned int dataDCC2, channel_id; 3068 int i; 3069 struct hdmi_spec *spec = codec->spec; 3070 struct hda_spdif_out *spdif; 3071 struct hdmi_spec_per_cvt *per_cvt; 3072 3073 mutex_lock(&codec->spdif_mutex); 3074 per_cvt = get_cvt(spec, 0); 3075 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); 3076 3077 chs = substream->runtime->channels; 3078 3079 dataDCC2 = 0x2; 3080 3081 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ 3082 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) 3083 snd_hda_codec_write(codec, 3084 nvhdmi_master_con_nid_7x, 3085 0, 3086 AC_VERB_SET_DIGI_CONVERT_1, 3087 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3088 3089 /* set the stream id */ 3090 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3091 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); 3092 3093 /* set the stream format */ 3094 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3095 AC_VERB_SET_STREAM_FORMAT, format); 3096 3097 /* turn on again (if needed) */ 3098 /* enable and set the channel status audio/data flag */ 3099 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { 3100 snd_hda_codec_write(codec, 3101 nvhdmi_master_con_nid_7x, 3102 0, 3103 AC_VERB_SET_DIGI_CONVERT_1, 3104 spdif->ctls & 0xff); 3105 snd_hda_codec_write(codec, 3106 nvhdmi_master_con_nid_7x, 3107 0, 3108 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3109 } 3110 3111 for (i = 0; i < 4; i++) { 3112 if (chs == 2) 3113 channel_id = 0; 3114 else 3115 channel_id = i * 2; 3116 3117 /* turn off SPDIF once; 3118 *otherwise the IEC958 bits won't be updated 3119 */ 3120 if (codec->spdif_status_reset && 3121 (spdif->ctls & AC_DIG1_ENABLE)) 3122 snd_hda_codec_write(codec, 3123 nvhdmi_con_nids_7x[i], 3124 0, 3125 AC_VERB_SET_DIGI_CONVERT_1, 3126 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3127 /* set the stream id */ 3128 snd_hda_codec_write(codec, 3129 nvhdmi_con_nids_7x[i], 3130 0, 3131 AC_VERB_SET_CHANNEL_STREAMID, 3132 (stream_tag << 4) | channel_id); 3133 /* set the stream format */ 3134 snd_hda_codec_write(codec, 3135 nvhdmi_con_nids_7x[i], 3136 0, 3137 AC_VERB_SET_STREAM_FORMAT, 3138 format); 3139 /* turn on again (if needed) */ 3140 /* enable and set the channel status audio/data flag */ 3141 if (codec->spdif_status_reset && 3142 (spdif->ctls & AC_DIG1_ENABLE)) { 3143 snd_hda_codec_write(codec, 3144 nvhdmi_con_nids_7x[i], 3145 0, 3146 AC_VERB_SET_DIGI_CONVERT_1, 3147 spdif->ctls & 0xff); 3148 snd_hda_codec_write(codec, 3149 nvhdmi_con_nids_7x[i], 3150 0, 3151 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3152 } 3153 } 3154 3155 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); 3156 3157 mutex_unlock(&codec->spdif_mutex); 3158 return 0; 3159 } 3160 3161 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { 3162 .substreams = 1, 3163 .channels_min = 2, 3164 .channels_max = 8, 3165 .nid = nvhdmi_master_con_nid_7x, 3166 .rates = SUPPORTED_RATES, 3167 .maxbps = SUPPORTED_MAXBPS, 3168 .formats = SUPPORTED_FORMATS, 3169 .ops = { 3170 .open = simple_playback_pcm_open, 3171 .close = nvhdmi_8ch_7x_pcm_close, 3172 .prepare = nvhdmi_8ch_7x_pcm_prepare 3173 }, 3174 }; 3175 3176 static int patch_nvhdmi_2ch(struct hda_codec *codec) 3177 { 3178 struct hdmi_spec *spec; 3179 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, 3180 nvhdmi_master_pin_nid_7x); 3181 if (err < 0) 3182 return err; 3183 3184 codec->patch_ops.init = nvhdmi_7x_init_2ch; 3185 /* override the PCM rates, etc, as the codec doesn't give full list */ 3186 spec = codec->spec; 3187 spec->pcm_playback.rates = SUPPORTED_RATES; 3188 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; 3189 spec->pcm_playback.formats = SUPPORTED_FORMATS; 3190 return 0; 3191 } 3192 3193 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) 3194 { 3195 struct hdmi_spec *spec = codec->spec; 3196 int err = simple_playback_build_pcms(codec); 3197 if (!err) { 3198 struct hda_pcm *info = get_pcm_rec(spec, 0); 3199 info->own_chmap = true; 3200 } 3201 return err; 3202 } 3203 3204 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) 3205 { 3206 struct hdmi_spec *spec = codec->spec; 3207 struct hda_pcm *info; 3208 struct snd_pcm_chmap *chmap; 3209 int err; 3210 3211 err = simple_playback_build_controls(codec); 3212 if (err < 0) 3213 return err; 3214 3215 /* add channel maps */ 3216 info = get_pcm_rec(spec, 0); 3217 err = snd_pcm_add_chmap_ctls(info->pcm, 3218 SNDRV_PCM_STREAM_PLAYBACK, 3219 snd_pcm_alt_chmaps, 8, 0, &chmap); 3220 if (err < 0) 3221 return err; 3222 switch (codec->preset->vendor_id) { 3223 case 0x10de0002: 3224 case 0x10de0003: 3225 case 0x10de0005: 3226 case 0x10de0006: 3227 chmap->channel_mask = (1U << 2) | (1U << 8); 3228 break; 3229 case 0x10de0007: 3230 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); 3231 } 3232 return 0; 3233 } 3234 3235 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) 3236 { 3237 struct hdmi_spec *spec; 3238 int err = patch_nvhdmi_2ch(codec); 3239 if (err < 0) 3240 return err; 3241 spec = codec->spec; 3242 spec->multiout.max_channels = 8; 3243 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; 3244 codec->patch_ops.init = nvhdmi_7x_init_8ch; 3245 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; 3246 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; 3247 3248 /* Initialize the audio infoframe channel mask and checksum to something 3249 * valid */ 3250 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3251 3252 return 0; 3253 } 3254 3255 /* 3256 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: 3257 * - 0x10de0015 3258 * - 0x10de0040 3259 */ 3260 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, 3261 struct hdac_cea_channel_speaker_allocation *cap, int channels) 3262 { 3263 if (cap->ca_index == 0x00 && channels == 2) 3264 return SNDRV_CTL_TLVT_CHMAP_FIXED; 3265 3266 /* If the speaker allocation matches the channel count, it is OK. */ 3267 if (cap->channels != channels) 3268 return -1; 3269 3270 /* all channels are remappable freely */ 3271 return SNDRV_CTL_TLVT_CHMAP_VAR; 3272 } 3273 3274 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, 3275 int ca, int chs, unsigned char *map) 3276 { 3277 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) 3278 return -EINVAL; 3279 3280 return 0; 3281 } 3282 3283 static int patch_nvhdmi(struct hda_codec *codec) 3284 { 3285 struct hdmi_spec *spec; 3286 int err; 3287 3288 err = patch_generic_hdmi(codec); 3289 if (err) 3290 return err; 3291 3292 spec = codec->spec; 3293 spec->dyn_pin_out = true; 3294 3295 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3296 nvhdmi_chmap_cea_alloc_validate_get_type; 3297 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3298 3299 return 0; 3300 } 3301 3302 /* 3303 * The HDA codec on NVIDIA Tegra contains two scratch registers that are 3304 * accessed using vendor-defined verbs. These registers can be used for 3305 * interoperability between the HDA and HDMI drivers. 3306 */ 3307 3308 /* Audio Function Group node */ 3309 #define NVIDIA_AFG_NID 0x01 3310 3311 /* 3312 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio 3313 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to 3314 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This 3315 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an 3316 * additional bit (at position 30) to signal the validity of the format. 3317 * 3318 * | 31 | 30 | 29 16 | 15 0 | 3319 * +---------+-------+--------+--------+ 3320 * | TRIGGER | VALID | UNUSED | FORMAT | 3321 * +-----------------------------------| 3322 * 3323 * Note that for the trigger bit to take effect it needs to change value 3324 * (i.e. it needs to be toggled). 3325 */ 3326 #define NVIDIA_GET_SCRATCH0 0xfa6 3327 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 3328 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 3329 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 3330 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa 3331 #define NVIDIA_SCRATCH_TRIGGER (1 << 7) 3332 #define NVIDIA_SCRATCH_VALID (1 << 6) 3333 3334 #define NVIDIA_GET_SCRATCH1 0xfab 3335 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac 3336 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad 3337 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae 3338 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf 3339 3340 /* 3341 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, 3342 * the format is invalidated so that the HDMI codec can be disabled. 3343 */ 3344 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format) 3345 { 3346 unsigned int value; 3347 3348 /* bits [31:30] contain the trigger and valid bits */ 3349 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0, 3350 NVIDIA_GET_SCRATCH0, 0); 3351 value = (value >> 24) & 0xff; 3352 3353 /* bits [15:0] are used to store the HDA format */ 3354 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3355 NVIDIA_SET_SCRATCH0_BYTE0, 3356 (format >> 0) & 0xff); 3357 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3358 NVIDIA_SET_SCRATCH0_BYTE1, 3359 (format >> 8) & 0xff); 3360 3361 /* bits [16:24] are unused */ 3362 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3363 NVIDIA_SET_SCRATCH0_BYTE2, 0); 3364 3365 /* 3366 * Bit 30 signals that the data is valid and hence that HDMI audio can 3367 * be enabled. 3368 */ 3369 if (format == 0) 3370 value &= ~NVIDIA_SCRATCH_VALID; 3371 else 3372 value |= NVIDIA_SCRATCH_VALID; 3373 3374 /* 3375 * Whenever the trigger bit is toggled, an interrupt is raised in the 3376 * HDMI codec. The HDMI driver will use that as trigger to update its 3377 * configuration. 3378 */ 3379 value ^= NVIDIA_SCRATCH_TRIGGER; 3380 3381 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3382 NVIDIA_SET_SCRATCH0_BYTE3, value); 3383 } 3384 3385 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, 3386 struct hda_codec *codec, 3387 unsigned int stream_tag, 3388 unsigned int format, 3389 struct snd_pcm_substream *substream) 3390 { 3391 int err; 3392 3393 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, 3394 format, substream); 3395 if (err < 0) 3396 return err; 3397 3398 /* notify the HDMI codec of the format change */ 3399 tegra_hdmi_set_format(codec, format); 3400 3401 return 0; 3402 } 3403 3404 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, 3405 struct hda_codec *codec, 3406 struct snd_pcm_substream *substream) 3407 { 3408 /* invalidate the format in the HDMI codec */ 3409 tegra_hdmi_set_format(codec, 0); 3410 3411 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); 3412 } 3413 3414 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) 3415 { 3416 struct hdmi_spec *spec = codec->spec; 3417 unsigned int i; 3418 3419 for (i = 0; i < spec->num_pins; i++) { 3420 struct hda_pcm *pcm = get_pcm_rec(spec, i); 3421 3422 if (pcm->pcm_type == type) 3423 return pcm; 3424 } 3425 3426 return NULL; 3427 } 3428 3429 static int tegra_hdmi_build_pcms(struct hda_codec *codec) 3430 { 3431 struct hda_pcm_stream *stream; 3432 struct hda_pcm *pcm; 3433 int err; 3434 3435 err = generic_hdmi_build_pcms(codec); 3436 if (err < 0) 3437 return err; 3438 3439 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); 3440 if (!pcm) 3441 return -ENODEV; 3442 3443 /* 3444 * Override ->prepare() and ->cleanup() operations to notify the HDMI 3445 * codec about format changes. 3446 */ 3447 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3448 stream->ops.prepare = tegra_hdmi_pcm_prepare; 3449 stream->ops.cleanup = tegra_hdmi_pcm_cleanup; 3450 3451 return 0; 3452 } 3453 3454 static int patch_tegra_hdmi(struct hda_codec *codec) 3455 { 3456 int err; 3457 3458 err = patch_generic_hdmi(codec); 3459 if (err) 3460 return err; 3461 3462 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; 3463 3464 return 0; 3465 } 3466 3467 /* 3468 * ATI/AMD-specific implementations 3469 */ 3470 3471 #define is_amdhdmi_rev3_or_later(codec) \ 3472 ((codec)->core.vendor_id == 0x1002aa01 && \ 3473 ((codec)->core.revision_id & 0xff00) >= 0x0300) 3474 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) 3475 3476 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ 3477 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 3478 #define ATI_VERB_SET_DOWNMIX_INFO 0x772 3479 #define ATI_VERB_SET_MULTICHANNEL_01 0x777 3480 #define ATI_VERB_SET_MULTICHANNEL_23 0x778 3481 #define ATI_VERB_SET_MULTICHANNEL_45 0x779 3482 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a 3483 #define ATI_VERB_SET_HBR_CONTROL 0x77c 3484 #define ATI_VERB_SET_MULTICHANNEL_1 0x785 3485 #define ATI_VERB_SET_MULTICHANNEL_3 0x786 3486 #define ATI_VERB_SET_MULTICHANNEL_5 0x787 3487 #define ATI_VERB_SET_MULTICHANNEL_7 0x788 3488 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 3489 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 3490 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 3491 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 3492 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 3493 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 3494 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a 3495 #define ATI_VERB_GET_HBR_CONTROL 0xf7c 3496 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 3497 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 3498 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 3499 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 3500 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 3501 3502 /* AMD specific HDA cvt verbs */ 3503 #define ATI_VERB_SET_RAMP_RATE 0x770 3504 #define ATI_VERB_GET_RAMP_RATE 0xf70 3505 3506 #define ATI_OUT_ENABLE 0x1 3507 3508 #define ATI_MULTICHANNEL_MODE_PAIRED 0 3509 #define ATI_MULTICHANNEL_MODE_SINGLE 1 3510 3511 #define ATI_HBR_CAPABLE 0x01 3512 #define ATI_HBR_ENABLE 0x10 3513 3514 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 3515 unsigned char *buf, int *eld_size) 3516 { 3517 /* call hda_eld.c ATI/AMD-specific function */ 3518 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, 3519 is_amdhdmi_rev3_or_later(codec)); 3520 } 3521 3522 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca, 3523 int active_channels, int conn_type) 3524 { 3525 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); 3526 } 3527 3528 static int atihdmi_paired_swap_fc_lfe(int pos) 3529 { 3530 /* 3531 * ATI/AMD have automatic FC/LFE swap built-in 3532 * when in pairwise mapping mode. 3533 */ 3534 3535 switch (pos) { 3536 /* see channel_allocations[].speakers[] */ 3537 case 2: return 3; 3538 case 3: return 2; 3539 default: break; 3540 } 3541 3542 return pos; 3543 } 3544 3545 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, 3546 int ca, int chs, unsigned char *map) 3547 { 3548 struct hdac_cea_channel_speaker_allocation *cap; 3549 int i, j; 3550 3551 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ 3552 3553 cap = snd_hdac_get_ch_alloc_from_ca(ca); 3554 for (i = 0; i < chs; ++i) { 3555 int mask = snd_hdac_chmap_to_spk_mask(map[i]); 3556 bool ok = false; 3557 bool companion_ok = false; 3558 3559 if (!mask) 3560 continue; 3561 3562 for (j = 0 + i % 2; j < 8; j += 2) { 3563 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); 3564 if (cap->speakers[chan_idx] == mask) { 3565 /* channel is in a supported position */ 3566 ok = true; 3567 3568 if (i % 2 == 0 && i + 1 < chs) { 3569 /* even channel, check the odd companion */ 3570 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); 3571 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); 3572 int comp_mask_act = cap->speakers[comp_chan_idx]; 3573 3574 if (comp_mask_req == comp_mask_act) 3575 companion_ok = true; 3576 else 3577 return -EINVAL; 3578 } 3579 break; 3580 } 3581 } 3582 3583 if (!ok) 3584 return -EINVAL; 3585 3586 if (companion_ok) 3587 i++; /* companion channel already checked */ 3588 } 3589 3590 return 0; 3591 } 3592 3593 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, 3594 hda_nid_t pin_nid, int hdmi_slot, int stream_channel) 3595 { 3596 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 3597 int verb; 3598 int ati_channel_setup = 0; 3599 3600 if (hdmi_slot > 7) 3601 return -EINVAL; 3602 3603 if (!has_amd_full_remap_support(codec)) { 3604 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); 3605 3606 /* In case this is an odd slot but without stream channel, do not 3607 * disable the slot since the corresponding even slot could have a 3608 * channel. In case neither have a channel, the slot pair will be 3609 * disabled when this function is called for the even slot. */ 3610 if (hdmi_slot % 2 != 0 && stream_channel == 0xf) 3611 return 0; 3612 3613 hdmi_slot -= hdmi_slot % 2; 3614 3615 if (stream_channel != 0xf) 3616 stream_channel -= stream_channel % 2; 3617 } 3618 3619 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; 3620 3621 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ 3622 3623 if (stream_channel != 0xf) 3624 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; 3625 3626 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); 3627 } 3628 3629 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, 3630 hda_nid_t pin_nid, int asp_slot) 3631 { 3632 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 3633 bool was_odd = false; 3634 int ati_asp_slot = asp_slot; 3635 int verb; 3636 int ati_channel_setup; 3637 3638 if (asp_slot > 7) 3639 return -EINVAL; 3640 3641 if (!has_amd_full_remap_support(codec)) { 3642 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); 3643 if (ati_asp_slot % 2 != 0) { 3644 ati_asp_slot -= 1; 3645 was_odd = true; 3646 } 3647 } 3648 3649 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; 3650 3651 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); 3652 3653 if (!(ati_channel_setup & ATI_OUT_ENABLE)) 3654 return 0xf; 3655 3656 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; 3657 } 3658 3659 static int atihdmi_paired_chmap_cea_alloc_validate_get_type( 3660 struct hdac_chmap *chmap, 3661 struct hdac_cea_channel_speaker_allocation *cap, 3662 int channels) 3663 { 3664 int c; 3665 3666 /* 3667 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so 3668 * we need to take that into account (a single channel may take 2 3669 * channel slots if we need to carry a silent channel next to it). 3670 * On Rev3+ AMD codecs this function is not used. 3671 */ 3672 int chanpairs = 0; 3673 3674 /* We only produce even-numbered channel count TLVs */ 3675 if ((channels % 2) != 0) 3676 return -1; 3677 3678 for (c = 0; c < 7; c += 2) { 3679 if (cap->speakers[c] || cap->speakers[c+1]) 3680 chanpairs++; 3681 } 3682 3683 if (chanpairs * 2 != channels) 3684 return -1; 3685 3686 return SNDRV_CTL_TLVT_CHMAP_PAIRED; 3687 } 3688 3689 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, 3690 struct hdac_cea_channel_speaker_allocation *cap, 3691 unsigned int *chmap, int channels) 3692 { 3693 /* produce paired maps for pre-rev3 ATI/AMD codecs */ 3694 int count = 0; 3695 int c; 3696 3697 for (c = 7; c >= 0; c--) { 3698 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); 3699 int spk = cap->speakers[chan]; 3700 if (!spk) { 3701 /* add N/A channel if the companion channel is occupied */ 3702 if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) 3703 chmap[count++] = SNDRV_CHMAP_NA; 3704 3705 continue; 3706 } 3707 3708 chmap[count++] = snd_hdac_spk_to_chmap(spk); 3709 } 3710 3711 WARN_ON(count != channels); 3712 } 3713 3714 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 3715 bool hbr) 3716 { 3717 int hbr_ctl, hbr_ctl_new; 3718 3719 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); 3720 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { 3721 if (hbr) 3722 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; 3723 else 3724 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; 3725 3726 codec_dbg(codec, 3727 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", 3728 pin_nid, 3729 hbr_ctl == hbr_ctl_new ? "" : "new-", 3730 hbr_ctl_new); 3731 3732 if (hbr_ctl != hbr_ctl_new) 3733 snd_hda_codec_write(codec, pin_nid, 0, 3734 ATI_VERB_SET_HBR_CONTROL, 3735 hbr_ctl_new); 3736 3737 } else if (hbr) 3738 return -EINVAL; 3739 3740 return 0; 3741 } 3742 3743 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 3744 hda_nid_t pin_nid, u32 stream_tag, int format) 3745 { 3746 3747 if (is_amdhdmi_rev3_or_later(codec)) { 3748 int ramp_rate = 180; /* default as per AMD spec */ 3749 /* disable ramp-up/down for non-pcm as per AMD spec */ 3750 if (format & AC_FMT_TYPE_NON_PCM) 3751 ramp_rate = 0; 3752 3753 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); 3754 } 3755 3756 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format); 3757 } 3758 3759 3760 static int atihdmi_init(struct hda_codec *codec) 3761 { 3762 struct hdmi_spec *spec = codec->spec; 3763 int pin_idx, err; 3764 3765 err = generic_hdmi_init(codec); 3766 3767 if (err) 3768 return err; 3769 3770 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 3771 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 3772 3773 /* make sure downmix information in infoframe is zero */ 3774 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); 3775 3776 /* enable channel-wise remap mode if supported */ 3777 if (has_amd_full_remap_support(codec)) 3778 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 3779 ATI_VERB_SET_MULTICHANNEL_MODE, 3780 ATI_MULTICHANNEL_MODE_SINGLE); 3781 } 3782 3783 return 0; 3784 } 3785 3786 static int patch_atihdmi(struct hda_codec *codec) 3787 { 3788 struct hdmi_spec *spec; 3789 struct hdmi_spec_per_cvt *per_cvt; 3790 int err, cvt_idx; 3791 3792 err = patch_generic_hdmi(codec); 3793 3794 if (err) 3795 return err; 3796 3797 codec->patch_ops.init = atihdmi_init; 3798 3799 spec = codec->spec; 3800 3801 spec->ops.pin_get_eld = atihdmi_pin_get_eld; 3802 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; 3803 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; 3804 spec->ops.setup_stream = atihdmi_setup_stream; 3805 3806 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; 3807 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; 3808 3809 if (!has_amd_full_remap_support(codec)) { 3810 /* override to ATI/AMD-specific versions with pairwise mapping */ 3811 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3812 atihdmi_paired_chmap_cea_alloc_validate_get_type; 3813 spec->chmap.ops.cea_alloc_to_tlv_chmap = 3814 atihdmi_paired_cea_alloc_to_tlv_chmap; 3815 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; 3816 } 3817 3818 /* ATI/AMD converters do not advertise all of their capabilities */ 3819 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 3820 per_cvt = get_cvt(spec, cvt_idx); 3821 per_cvt->channels_max = max(per_cvt->channels_max, 8u); 3822 per_cvt->rates |= SUPPORTED_RATES; 3823 per_cvt->formats |= SUPPORTED_FORMATS; 3824 per_cvt->maxbps = max(per_cvt->maxbps, 24u); 3825 } 3826 3827 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); 3828 3829 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing 3830 * the link-down as is. Tell the core to allow it. 3831 */ 3832 codec->link_down_at_suspend = 1; 3833 3834 return 0; 3835 } 3836 3837 /* VIA HDMI Implementation */ 3838 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ 3839 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ 3840 3841 static int patch_via_hdmi(struct hda_codec *codec) 3842 { 3843 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); 3844 } 3845 3846 /* 3847 * patch entries 3848 */ 3849 static const struct hda_device_id snd_hda_id_hdmi[] = { 3850 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), 3851 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), 3852 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), 3853 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), 3854 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), 3855 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), 3856 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), 3857 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch), 3858 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 3859 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 3860 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x), 3861 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 3862 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 3863 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), 3864 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi), 3865 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi), 3866 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi), 3867 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi), 3868 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi), 3869 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi), 3870 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi), 3871 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi), 3872 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi), 3873 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi), 3874 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi), 3875 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi), 3876 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi), 3877 /* 17 is known to be absent */ 3878 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi), 3879 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi), 3880 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi), 3881 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi), 3882 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi), 3883 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), 3884 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), 3885 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), 3886 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), 3887 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi), 3888 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi), 3889 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), 3890 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), 3891 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), 3892 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), 3893 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), 3894 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), 3895 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), 3896 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi), 3897 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi), 3898 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), 3899 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi), 3900 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), 3901 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi), 3902 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi), 3903 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), 3904 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), 3905 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), 3906 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), 3907 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi), 3908 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi), 3909 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi), 3910 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi), 3911 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi), 3912 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), 3913 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi), 3914 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), 3915 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi), 3916 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), 3917 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), 3918 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi), 3919 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi), 3920 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi), 3921 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi), 3922 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi), 3923 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi), 3924 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi), 3925 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi), 3926 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), 3927 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), 3928 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), 3929 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), 3930 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), 3931 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), 3932 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), 3933 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), 3934 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), 3935 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), 3936 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), 3937 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), 3938 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), 3939 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), 3940 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), 3941 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), 3942 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), 3943 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), 3944 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), 3945 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), 3946 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), 3947 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), 3948 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), 3949 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi), 3950 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), 3951 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), 3952 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), 3953 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), 3954 /* special ID for generic HDMI */ 3955 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), 3956 {} /* terminator */ 3957 }; 3958 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); 3959 3960 MODULE_LICENSE("GPL"); 3961 MODULE_DESCRIPTION("HDMI HD-audio codec"); 3962 MODULE_ALIAS("snd-hda-codec-intelhdmi"); 3963 MODULE_ALIAS("snd-hda-codec-nvhdmi"); 3964 MODULE_ALIAS("snd-hda-codec-atihdmi"); 3965 3966 static struct hda_codec_driver hdmi_driver = { 3967 .id = snd_hda_id_hdmi, 3968 }; 3969 3970 module_hda_codec_driver(hdmi_driver); 3971