xref: /openbmc/linux/sound/pci/hda/patch_hdmi.c (revision b58c6630)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *
4  *  patch_hdmi.c - routines for HDMI/DisplayPort codecs
5  *
6  *  Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
7  *  Copyright (c) 2006 ATI Technologies Inc.
8  *  Copyright (c) 2008 NVIDIA Corp.  All rights reserved.
9  *  Copyright (c) 2008 Wei Ni <wni@nvidia.com>
10  *  Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
11  *
12  *  Authors:
13  *			Wu Fengguang <wfg@linux.intel.com>
14  *
15  *  Maintained by:
16  *			Wu Fengguang <wfg@linux.intel.com>
17  */
18 
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/pci.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/pm_runtime.h>
25 #include <sound/core.h>
26 #include <sound/jack.h>
27 #include <sound/asoundef.h>
28 #include <sound/tlv.h>
29 #include <sound/hdaudio.h>
30 #include <sound/hda_i915.h>
31 #include <sound/hda_chmap.h>
32 #include <sound/hda_codec.h>
33 #include "hda_local.h"
34 #include "hda_jack.h"
35 #include "hda_controller.h"
36 
37 static bool static_hdmi_pcm;
38 module_param(static_hdmi_pcm, bool, 0644);
39 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
40 
41 static bool enable_acomp = true;
42 module_param(enable_acomp, bool, 0444);
43 MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)");
44 
45 struct hdmi_spec_per_cvt {
46 	hda_nid_t cvt_nid;
47 	int assigned;
48 	unsigned int channels_min;
49 	unsigned int channels_max;
50 	u32 rates;
51 	u64 formats;
52 	unsigned int maxbps;
53 };
54 
55 /* max. connections to a widget */
56 #define HDA_MAX_CONNECTIONS	32
57 
58 struct hdmi_spec_per_pin {
59 	hda_nid_t pin_nid;
60 	int dev_id;
61 	/* pin idx, different device entries on the same pin use the same idx */
62 	int pin_nid_idx;
63 	int num_mux_nids;
64 	hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
65 	int mux_idx;
66 	hda_nid_t cvt_nid;
67 
68 	struct hda_codec *codec;
69 	struct hdmi_eld sink_eld;
70 	struct mutex lock;
71 	struct delayed_work work;
72 	struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
73 	int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
74 	int repoll_count;
75 	bool setup; /* the stream has been set up by prepare callback */
76 	int channels; /* current number of channels */
77 	bool non_pcm;
78 	bool chmap_set;		/* channel-map override by ALSA API? */
79 	unsigned char chmap[8]; /* ALSA API channel-map */
80 #ifdef CONFIG_SND_PROC_FS
81 	struct snd_info_entry *proc_entry;
82 #endif
83 };
84 
85 /* operations used by generic code that can be overridden by patches */
86 struct hdmi_ops {
87 	int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
88 			   int dev_id, unsigned char *buf, int *eld_size);
89 
90 	void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
91 				    int dev_id,
92 				    int ca, int active_channels, int conn_type);
93 
94 	/* enable/disable HBR (HD passthrough) */
95 	int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid,
96 			     int dev_id, bool hbr);
97 
98 	int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
99 			    hda_nid_t pin_nid, int dev_id, u32 stream_tag,
100 			    int format);
101 
102 	void (*pin_cvt_fixup)(struct hda_codec *codec,
103 			      struct hdmi_spec_per_pin *per_pin,
104 			      hda_nid_t cvt_nid);
105 };
106 
107 struct hdmi_pcm {
108 	struct hda_pcm *pcm;
109 	struct snd_jack *jack;
110 	struct snd_kcontrol *eld_ctl;
111 };
112 
113 struct hdmi_spec {
114 	struct hda_codec *codec;
115 	int num_cvts;
116 	struct snd_array cvts; /* struct hdmi_spec_per_cvt */
117 	hda_nid_t cvt_nids[4]; /* only for haswell fix */
118 
119 	/*
120 	 * num_pins is the number of virtual pins
121 	 * for example, there are 3 pins, and each pin
122 	 * has 4 device entries, then the num_pins is 12
123 	 */
124 	int num_pins;
125 	/*
126 	 * num_nids is the number of real pins
127 	 * In the above example, num_nids is 3
128 	 */
129 	int num_nids;
130 	/*
131 	 * dev_num is the number of device entries
132 	 * on each pin.
133 	 * In the above example, dev_num is 4
134 	 */
135 	int dev_num;
136 	struct snd_array pins; /* struct hdmi_spec_per_pin */
137 	struct hdmi_pcm pcm_rec[16];
138 	struct mutex pcm_lock;
139 	struct mutex bind_lock; /* for audio component binding */
140 	/* pcm_bitmap means which pcms have been assigned to pins*/
141 	unsigned long pcm_bitmap;
142 	int pcm_used;	/* counter of pcm_rec[] */
143 	/* bitmap shows whether the pcm is opened in user space
144 	 * bit 0 means the first playback PCM (PCM3);
145 	 * bit 1 means the second playback PCM, and so on.
146 	 */
147 	unsigned long pcm_in_use;
148 
149 	struct hdmi_eld temp_eld;
150 	struct hdmi_ops ops;
151 
152 	bool dyn_pin_out;
153 	bool dyn_pcm_assign;
154 	bool intel_hsw_fixup;	/* apply Intel platform-specific fixups */
155 	/*
156 	 * Non-generic VIA/NVIDIA specific
157 	 */
158 	struct hda_multi_out multiout;
159 	struct hda_pcm_stream pcm_playback;
160 
161 	bool use_acomp_notifier; /* use eld_notify callback for hotplug */
162 	bool acomp_registered; /* audio component registered in this driver */
163 	struct drm_audio_component_audio_ops drm_audio_ops;
164 	int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */
165 
166 	struct hdac_chmap chmap;
167 	hda_nid_t vendor_nid;
168 	const int *port_map;
169 	int port_num;
170 };
171 
172 #ifdef CONFIG_SND_HDA_COMPONENT
173 static inline bool codec_has_acomp(struct hda_codec *codec)
174 {
175 	struct hdmi_spec *spec = codec->spec;
176 	return spec->use_acomp_notifier;
177 }
178 #else
179 #define codec_has_acomp(codec)	false
180 #endif
181 
182 struct hdmi_audio_infoframe {
183 	u8 type; /* 0x84 */
184 	u8 ver;  /* 0x01 */
185 	u8 len;  /* 0x0a */
186 
187 	u8 checksum;
188 
189 	u8 CC02_CT47;	/* CC in bits 0:2, CT in 4:7 */
190 	u8 SS01_SF24;
191 	u8 CXT04;
192 	u8 CA;
193 	u8 LFEPBL01_LSV36_DM_INH7;
194 };
195 
196 struct dp_audio_infoframe {
197 	u8 type; /* 0x84 */
198 	u8 len;  /* 0x1b */
199 	u8 ver;  /* 0x11 << 2 */
200 
201 	u8 CC02_CT47;	/* match with HDMI infoframe from this on */
202 	u8 SS01_SF24;
203 	u8 CXT04;
204 	u8 CA;
205 	u8 LFEPBL01_LSV36_DM_INH7;
206 };
207 
208 union audio_infoframe {
209 	struct hdmi_audio_infoframe hdmi;
210 	struct dp_audio_infoframe dp;
211 	u8 bytes[0];
212 };
213 
214 /*
215  * HDMI routines
216  */
217 
218 #define get_pin(spec, idx) \
219 	((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
220 #define get_cvt(spec, idx) \
221 	((struct hdmi_spec_per_cvt  *)snd_array_elem(&spec->cvts, idx))
222 /* obtain hdmi_pcm object assigned to idx */
223 #define get_hdmi_pcm(spec, idx)	(&(spec)->pcm_rec[idx])
224 /* obtain hda_pcm object assigned to idx */
225 #define get_pcm_rec(spec, idx)	(get_hdmi_pcm(spec, idx)->pcm)
226 
227 static int pin_id_to_pin_index(struct hda_codec *codec,
228 			       hda_nid_t pin_nid, int dev_id)
229 {
230 	struct hdmi_spec *spec = codec->spec;
231 	int pin_idx;
232 	struct hdmi_spec_per_pin *per_pin;
233 
234 	/*
235 	 * (dev_id == -1) means it is NON-MST pin
236 	 * return the first virtual pin on this port
237 	 */
238 	if (dev_id == -1)
239 		dev_id = 0;
240 
241 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
242 		per_pin = get_pin(spec, pin_idx);
243 		if ((per_pin->pin_nid == pin_nid) &&
244 			(per_pin->dev_id == dev_id))
245 			return pin_idx;
246 	}
247 
248 	codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
249 	return -EINVAL;
250 }
251 
252 static int hinfo_to_pcm_index(struct hda_codec *codec,
253 			struct hda_pcm_stream *hinfo)
254 {
255 	struct hdmi_spec *spec = codec->spec;
256 	int pcm_idx;
257 
258 	for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
259 		if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
260 			return pcm_idx;
261 
262 	codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
263 	return -EINVAL;
264 }
265 
266 static int hinfo_to_pin_index(struct hda_codec *codec,
267 			      struct hda_pcm_stream *hinfo)
268 {
269 	struct hdmi_spec *spec = codec->spec;
270 	struct hdmi_spec_per_pin *per_pin;
271 	int pin_idx;
272 
273 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
274 		per_pin = get_pin(spec, pin_idx);
275 		if (per_pin->pcm &&
276 			per_pin->pcm->pcm->stream == hinfo)
277 			return pin_idx;
278 	}
279 
280 	codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
281 	return -EINVAL;
282 }
283 
284 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
285 						int pcm_idx)
286 {
287 	int i;
288 	struct hdmi_spec_per_pin *per_pin;
289 
290 	for (i = 0; i < spec->num_pins; i++) {
291 		per_pin = get_pin(spec, i);
292 		if (per_pin->pcm_idx == pcm_idx)
293 			return per_pin;
294 	}
295 	return NULL;
296 }
297 
298 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
299 {
300 	struct hdmi_spec *spec = codec->spec;
301 	int cvt_idx;
302 
303 	for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
304 		if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
305 			return cvt_idx;
306 
307 	codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
308 	return -EINVAL;
309 }
310 
311 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
312 			struct snd_ctl_elem_info *uinfo)
313 {
314 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
315 	struct hdmi_spec *spec = codec->spec;
316 	struct hdmi_spec_per_pin *per_pin;
317 	struct hdmi_eld *eld;
318 	int pcm_idx;
319 
320 	uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
321 
322 	pcm_idx = kcontrol->private_value;
323 	mutex_lock(&spec->pcm_lock);
324 	per_pin = pcm_idx_to_pin(spec, pcm_idx);
325 	if (!per_pin) {
326 		/* no pin is bound to the pcm */
327 		uinfo->count = 0;
328 		goto unlock;
329 	}
330 	eld = &per_pin->sink_eld;
331 	uinfo->count = eld->eld_valid ? eld->eld_size : 0;
332 
333  unlock:
334 	mutex_unlock(&spec->pcm_lock);
335 	return 0;
336 }
337 
338 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
339 			struct snd_ctl_elem_value *ucontrol)
340 {
341 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
342 	struct hdmi_spec *spec = codec->spec;
343 	struct hdmi_spec_per_pin *per_pin;
344 	struct hdmi_eld *eld;
345 	int pcm_idx;
346 	int err = 0;
347 
348 	pcm_idx = kcontrol->private_value;
349 	mutex_lock(&spec->pcm_lock);
350 	per_pin = pcm_idx_to_pin(spec, pcm_idx);
351 	if (!per_pin) {
352 		/* no pin is bound to the pcm */
353 		memset(ucontrol->value.bytes.data, 0,
354 		       ARRAY_SIZE(ucontrol->value.bytes.data));
355 		goto unlock;
356 	}
357 
358 	eld = &per_pin->sink_eld;
359 	if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
360 	    eld->eld_size > ELD_MAX_SIZE) {
361 		snd_BUG();
362 		err = -EINVAL;
363 		goto unlock;
364 	}
365 
366 	memset(ucontrol->value.bytes.data, 0,
367 	       ARRAY_SIZE(ucontrol->value.bytes.data));
368 	if (eld->eld_valid)
369 		memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
370 		       eld->eld_size);
371 
372  unlock:
373 	mutex_unlock(&spec->pcm_lock);
374 	return err;
375 }
376 
377 static const struct snd_kcontrol_new eld_bytes_ctl = {
378 	.access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE |
379 		SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK,
380 	.iface = SNDRV_CTL_ELEM_IFACE_PCM,
381 	.name = "ELD",
382 	.info = hdmi_eld_ctl_info,
383 	.get = hdmi_eld_ctl_get,
384 };
385 
386 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
387 			int device)
388 {
389 	struct snd_kcontrol *kctl;
390 	struct hdmi_spec *spec = codec->spec;
391 	int err;
392 
393 	kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
394 	if (!kctl)
395 		return -ENOMEM;
396 	kctl->private_value = pcm_idx;
397 	kctl->id.device = device;
398 
399 	/* no pin nid is associated with the kctl now
400 	 * tbd: associate pin nid to eld ctl later
401 	 */
402 	err = snd_hda_ctl_add(codec, 0, kctl);
403 	if (err < 0)
404 		return err;
405 
406 	get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
407 	return 0;
408 }
409 
410 #ifdef BE_PARANOID
411 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
412 				int *packet_index, int *byte_index)
413 {
414 	int val;
415 
416 	val = snd_hda_codec_read(codec, pin_nid, 0,
417 				 AC_VERB_GET_HDMI_DIP_INDEX, 0);
418 
419 	*packet_index = val >> 5;
420 	*byte_index = val & 0x1f;
421 }
422 #endif
423 
424 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
425 				int packet_index, int byte_index)
426 {
427 	int val;
428 
429 	val = (packet_index << 5) | (byte_index & 0x1f);
430 
431 	snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
432 }
433 
434 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
435 				unsigned char val)
436 {
437 	snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
438 }
439 
440 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
441 {
442 	struct hdmi_spec *spec = codec->spec;
443 	int pin_out;
444 
445 	/* Unmute */
446 	if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
447 		snd_hda_codec_write(codec, pin_nid, 0,
448 				AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
449 
450 	if (spec->dyn_pin_out)
451 		/* Disable pin out until stream is active */
452 		pin_out = 0;
453 	else
454 		/* Enable pin out: some machines with GM965 gets broken output
455 		 * when the pin is disabled or changed while using with HDMI
456 		 */
457 		pin_out = PIN_OUT;
458 
459 	snd_hda_codec_write(codec, pin_nid, 0,
460 			    AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
461 }
462 
463 /*
464  * ELD proc files
465  */
466 
467 #ifdef CONFIG_SND_PROC_FS
468 static void print_eld_info(struct snd_info_entry *entry,
469 			   struct snd_info_buffer *buffer)
470 {
471 	struct hdmi_spec_per_pin *per_pin = entry->private_data;
472 
473 	mutex_lock(&per_pin->lock);
474 	snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
475 	mutex_unlock(&per_pin->lock);
476 }
477 
478 static void write_eld_info(struct snd_info_entry *entry,
479 			   struct snd_info_buffer *buffer)
480 {
481 	struct hdmi_spec_per_pin *per_pin = entry->private_data;
482 
483 	mutex_lock(&per_pin->lock);
484 	snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
485 	mutex_unlock(&per_pin->lock);
486 }
487 
488 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
489 {
490 	char name[32];
491 	struct hda_codec *codec = per_pin->codec;
492 	struct snd_info_entry *entry;
493 	int err;
494 
495 	snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
496 	err = snd_card_proc_new(codec->card, name, &entry);
497 	if (err < 0)
498 		return err;
499 
500 	snd_info_set_text_ops(entry, per_pin, print_eld_info);
501 	entry->c.text.write = write_eld_info;
502 	entry->mode |= 0200;
503 	per_pin->proc_entry = entry;
504 
505 	return 0;
506 }
507 
508 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
509 {
510 	if (!per_pin->codec->bus->shutdown) {
511 		snd_info_free_entry(per_pin->proc_entry);
512 		per_pin->proc_entry = NULL;
513 	}
514 }
515 #else
516 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
517 			       int index)
518 {
519 	return 0;
520 }
521 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
522 {
523 }
524 #endif
525 
526 /*
527  * Audio InfoFrame routines
528  */
529 
530 /*
531  * Enable Audio InfoFrame Transmission
532  */
533 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
534 				       hda_nid_t pin_nid)
535 {
536 	hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
537 	snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
538 						AC_DIPXMIT_BEST);
539 }
540 
541 /*
542  * Disable Audio InfoFrame Transmission
543  */
544 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
545 				      hda_nid_t pin_nid)
546 {
547 	hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
548 	snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
549 						AC_DIPXMIT_DISABLE);
550 }
551 
552 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
553 {
554 #ifdef CONFIG_SND_DEBUG_VERBOSE
555 	int i;
556 	int size;
557 
558 	size = snd_hdmi_get_eld_size(codec, pin_nid);
559 	codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
560 
561 	for (i = 0; i < 8; i++) {
562 		size = snd_hda_codec_read(codec, pin_nid, 0,
563 						AC_VERB_GET_HDMI_DIP_SIZE, i);
564 		codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
565 	}
566 #endif
567 }
568 
569 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
570 {
571 #ifdef BE_PARANOID
572 	int i, j;
573 	int size;
574 	int pi, bi;
575 	for (i = 0; i < 8; i++) {
576 		size = snd_hda_codec_read(codec, pin_nid, 0,
577 						AC_VERB_GET_HDMI_DIP_SIZE, i);
578 		if (size == 0)
579 			continue;
580 
581 		hdmi_set_dip_index(codec, pin_nid, i, 0x0);
582 		for (j = 1; j < 1000; j++) {
583 			hdmi_write_dip_byte(codec, pin_nid, 0x0);
584 			hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
585 			if (pi != i)
586 				codec_dbg(codec, "dip index %d: %d != %d\n",
587 						bi, pi, i);
588 			if (bi == 0) /* byte index wrapped around */
589 				break;
590 		}
591 		codec_dbg(codec,
592 			"HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
593 			i, size, j);
594 	}
595 #endif
596 }
597 
598 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
599 {
600 	u8 *bytes = (u8 *)hdmi_ai;
601 	u8 sum = 0;
602 	int i;
603 
604 	hdmi_ai->checksum = 0;
605 
606 	for (i = 0; i < sizeof(*hdmi_ai); i++)
607 		sum += bytes[i];
608 
609 	hdmi_ai->checksum = -sum;
610 }
611 
612 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
613 				      hda_nid_t pin_nid,
614 				      u8 *dip, int size)
615 {
616 	int i;
617 
618 	hdmi_debug_dip_size(codec, pin_nid);
619 	hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
620 
621 	hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
622 	for (i = 0; i < size; i++)
623 		hdmi_write_dip_byte(codec, pin_nid, dip[i]);
624 }
625 
626 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
627 				    u8 *dip, int size)
628 {
629 	u8 val;
630 	int i;
631 
632 	if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
633 							    != AC_DIPXMIT_BEST)
634 		return false;
635 
636 	hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
637 	for (i = 0; i < size; i++) {
638 		val = snd_hda_codec_read(codec, pin_nid, 0,
639 					 AC_VERB_GET_HDMI_DIP_DATA, 0);
640 		if (val != dip[i])
641 			return false;
642 	}
643 
644 	return true;
645 }
646 
647 static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
648 			    int dev_id, unsigned char *buf, int *eld_size)
649 {
650 	snd_hda_set_dev_select(codec, nid, dev_id);
651 
652 	return snd_hdmi_get_eld(codec, nid, buf, eld_size);
653 }
654 
655 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
656 				     hda_nid_t pin_nid, int dev_id,
657 				     int ca, int active_channels,
658 				     int conn_type)
659 {
660 	union audio_infoframe ai;
661 
662 	memset(&ai, 0, sizeof(ai));
663 	if (conn_type == 0) { /* HDMI */
664 		struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
665 
666 		hdmi_ai->type		= 0x84;
667 		hdmi_ai->ver		= 0x01;
668 		hdmi_ai->len		= 0x0a;
669 		hdmi_ai->CC02_CT47	= active_channels - 1;
670 		hdmi_ai->CA		= ca;
671 		hdmi_checksum_audio_infoframe(hdmi_ai);
672 	} else if (conn_type == 1) { /* DisplayPort */
673 		struct dp_audio_infoframe *dp_ai = &ai.dp;
674 
675 		dp_ai->type		= 0x84;
676 		dp_ai->len		= 0x1b;
677 		dp_ai->ver		= 0x11 << 2;
678 		dp_ai->CC02_CT47	= active_channels - 1;
679 		dp_ai->CA		= ca;
680 	} else {
681 		codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
682 			    pin_nid);
683 		return;
684 	}
685 
686 	snd_hda_set_dev_select(codec, pin_nid, dev_id);
687 
688 	/*
689 	 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
690 	 * sizeof(*dp_ai) to avoid partial match/update problems when
691 	 * the user switches between HDMI/DP monitors.
692 	 */
693 	if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
694 					sizeof(ai))) {
695 		codec_dbg(codec,
696 			  "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
697 			    pin_nid,
698 			    active_channels, ca);
699 		hdmi_stop_infoframe_trans(codec, pin_nid);
700 		hdmi_fill_audio_infoframe(codec, pin_nid,
701 					    ai.bytes, sizeof(ai));
702 		hdmi_start_infoframe_trans(codec, pin_nid);
703 	}
704 }
705 
706 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
707 				       struct hdmi_spec_per_pin *per_pin,
708 				       bool non_pcm)
709 {
710 	struct hdmi_spec *spec = codec->spec;
711 	struct hdac_chmap *chmap = &spec->chmap;
712 	hda_nid_t pin_nid = per_pin->pin_nid;
713 	int dev_id = per_pin->dev_id;
714 	int channels = per_pin->channels;
715 	int active_channels;
716 	struct hdmi_eld *eld;
717 	int ca;
718 
719 	if (!channels)
720 		return;
721 
722 	snd_hda_set_dev_select(codec, pin_nid, dev_id);
723 
724 	/* some HW (e.g. HSW+) needs reprogramming the amp at each time */
725 	if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
726 		snd_hda_codec_write(codec, pin_nid, 0,
727 					    AC_VERB_SET_AMP_GAIN_MUTE,
728 					    AMP_OUT_UNMUTE);
729 
730 	eld = &per_pin->sink_eld;
731 
732 	ca = snd_hdac_channel_allocation(&codec->core,
733 			eld->info.spk_alloc, channels,
734 			per_pin->chmap_set, non_pcm, per_pin->chmap);
735 
736 	active_channels = snd_hdac_get_active_channels(ca);
737 
738 	chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
739 						active_channels);
740 
741 	/*
742 	 * always configure channel mapping, it may have been changed by the
743 	 * user in the meantime
744 	 */
745 	snd_hdac_setup_channel_mapping(&spec->chmap,
746 				pin_nid, non_pcm, ca, channels,
747 				per_pin->chmap, per_pin->chmap_set);
748 
749 	spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id,
750 				      ca, active_channels, eld->info.conn_type);
751 
752 	per_pin->non_pcm = non_pcm;
753 }
754 
755 /*
756  * Unsolicited events
757  */
758 
759 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
760 
761 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
762 				      int dev_id)
763 {
764 	struct hdmi_spec *spec = codec->spec;
765 	int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
766 
767 	if (pin_idx < 0)
768 		return;
769 	mutex_lock(&spec->pcm_lock);
770 	hdmi_present_sense(get_pin(spec, pin_idx), 1);
771 	mutex_unlock(&spec->pcm_lock);
772 }
773 
774 static void jack_callback(struct hda_codec *codec,
775 			  struct hda_jack_callback *jack)
776 {
777 	/* stop polling when notification is enabled */
778 	if (codec_has_acomp(codec))
779 		return;
780 
781 	check_presence_and_report(codec, jack->nid, jack->dev_id);
782 }
783 
784 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res,
785 				 struct hda_jack_tbl *jack)
786 {
787 	jack->jack_dirty = 1;
788 
789 	codec_dbg(codec,
790 		"HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
791 		codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA),
792 		!!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
793 
794 	check_presence_and_report(codec, jack->nid, jack->dev_id);
795 }
796 
797 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
798 {
799 	int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
800 	int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
801 	int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
802 	int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
803 
804 	codec_info(codec,
805 		"HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
806 		codec->addr,
807 		tag,
808 		subtag,
809 		cp_state,
810 		cp_ready);
811 
812 	/* TODO */
813 	if (cp_state) {
814 		;
815 	}
816 	if (cp_ready) {
817 		;
818 	}
819 }
820 
821 
822 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
823 {
824 	int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
825 	int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
826 	struct hda_jack_tbl *jack;
827 
828 	if (codec_has_acomp(codec))
829 		return;
830 
831 	if (codec->dp_mst) {
832 		int dev_entry =
833 			(res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
834 
835 		jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry);
836 	} else {
837 		jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0);
838 	}
839 
840 	if (!jack) {
841 		codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
842 		return;
843 	}
844 
845 	if (subtag == 0)
846 		hdmi_intrinsic_event(codec, res, jack);
847 	else
848 		hdmi_non_intrinsic_event(codec, res);
849 }
850 
851 static void haswell_verify_D0(struct hda_codec *codec,
852 		hda_nid_t cvt_nid, hda_nid_t nid)
853 {
854 	int pwr;
855 
856 	/* For Haswell, the converter 1/2 may keep in D3 state after bootup,
857 	 * thus pins could only choose converter 0 for use. Make sure the
858 	 * converters are in correct power state */
859 	if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
860 		snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
861 
862 	if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
863 		snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
864 				    AC_PWRST_D0);
865 		msleep(40);
866 		pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
867 		pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
868 		codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
869 	}
870 }
871 
872 /*
873  * Callbacks
874  */
875 
876 /* HBR should be Non-PCM, 8 channels */
877 #define is_hbr_format(format) \
878 	((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
879 
880 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
881 			      int dev_id, bool hbr)
882 {
883 	int pinctl, new_pinctl;
884 
885 	if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
886 		snd_hda_set_dev_select(codec, pin_nid, dev_id);
887 		pinctl = snd_hda_codec_read(codec, pin_nid, 0,
888 					    AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
889 
890 		if (pinctl < 0)
891 			return hbr ? -EINVAL : 0;
892 
893 		new_pinctl = pinctl & ~AC_PINCTL_EPT;
894 		if (hbr)
895 			new_pinctl |= AC_PINCTL_EPT_HBR;
896 		else
897 			new_pinctl |= AC_PINCTL_EPT_NATIVE;
898 
899 		codec_dbg(codec,
900 			  "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
901 			    pin_nid,
902 			    pinctl == new_pinctl ? "" : "new-",
903 			    new_pinctl);
904 
905 		if (pinctl != new_pinctl)
906 			snd_hda_codec_write(codec, pin_nid, 0,
907 					    AC_VERB_SET_PIN_WIDGET_CONTROL,
908 					    new_pinctl);
909 	} else if (hbr)
910 		return -EINVAL;
911 
912 	return 0;
913 }
914 
915 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
916 			      hda_nid_t pin_nid, int dev_id,
917 			      u32 stream_tag, int format)
918 {
919 	struct hdmi_spec *spec = codec->spec;
920 	unsigned int param;
921 	int err;
922 
923 	err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id,
924 				      is_hbr_format(format));
925 
926 	if (err) {
927 		codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
928 		return err;
929 	}
930 
931 	if (spec->intel_hsw_fixup) {
932 
933 		/*
934 		 * on recent platforms IEC Coding Type is required for HBR
935 		 * support, read current Digital Converter settings and set
936 		 * ICT bitfield if needed.
937 		 */
938 		param = snd_hda_codec_read(codec, cvt_nid, 0,
939 					   AC_VERB_GET_DIGI_CONVERT_1, 0);
940 
941 		param = (param >> 16) & ~(AC_DIG3_ICT);
942 
943 		/* on recent platforms ICT mode is required for HBR support */
944 		if (is_hbr_format(format))
945 			param |= 0x1;
946 
947 		snd_hda_codec_write(codec, cvt_nid, 0,
948 				    AC_VERB_SET_DIGI_CONVERT_3, param);
949 	}
950 
951 	snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
952 	return 0;
953 }
954 
955 /* Try to find an available converter
956  * If pin_idx is less then zero, just try to find an available converter.
957  * Otherwise, try to find an available converter and get the cvt mux index
958  * of the pin.
959  */
960 static int hdmi_choose_cvt(struct hda_codec *codec,
961 			   int pin_idx, int *cvt_id)
962 {
963 	struct hdmi_spec *spec = codec->spec;
964 	struct hdmi_spec_per_pin *per_pin;
965 	struct hdmi_spec_per_cvt *per_cvt = NULL;
966 	int cvt_idx, mux_idx = 0;
967 
968 	/* pin_idx < 0 means no pin will be bound to the converter */
969 	if (pin_idx < 0)
970 		per_pin = NULL;
971 	else
972 		per_pin = get_pin(spec, pin_idx);
973 
974 	/* Dynamically assign converter to stream */
975 	for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
976 		per_cvt = get_cvt(spec, cvt_idx);
977 
978 		/* Must not already be assigned */
979 		if (per_cvt->assigned)
980 			continue;
981 		if (per_pin == NULL)
982 			break;
983 		/* Must be in pin's mux's list of converters */
984 		for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
985 			if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
986 				break;
987 		/* Not in mux list */
988 		if (mux_idx == per_pin->num_mux_nids)
989 			continue;
990 		break;
991 	}
992 
993 	/* No free converters */
994 	if (cvt_idx == spec->num_cvts)
995 		return -EBUSY;
996 
997 	if (per_pin != NULL)
998 		per_pin->mux_idx = mux_idx;
999 
1000 	if (cvt_id)
1001 		*cvt_id = cvt_idx;
1002 
1003 	return 0;
1004 }
1005 
1006 /* Assure the pin select the right convetor */
1007 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1008 			struct hdmi_spec_per_pin *per_pin)
1009 {
1010 	hda_nid_t pin_nid = per_pin->pin_nid;
1011 	int mux_idx, curr;
1012 
1013 	mux_idx = per_pin->mux_idx;
1014 	curr = snd_hda_codec_read(codec, pin_nid, 0,
1015 					  AC_VERB_GET_CONNECT_SEL, 0);
1016 	if (curr != mux_idx)
1017 		snd_hda_codec_write_cache(codec, pin_nid, 0,
1018 					    AC_VERB_SET_CONNECT_SEL,
1019 					    mux_idx);
1020 }
1021 
1022 /* get the mux index for the converter of the pins
1023  * converter's mux index is the same for all pins on Intel platform
1024  */
1025 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1026 			hda_nid_t cvt_nid)
1027 {
1028 	int i;
1029 
1030 	for (i = 0; i < spec->num_cvts; i++)
1031 		if (spec->cvt_nids[i] == cvt_nid)
1032 			return i;
1033 	return -EINVAL;
1034 }
1035 
1036 /* Intel HDMI workaround to fix audio routing issue:
1037  * For some Intel display codecs, pins share the same connection list.
1038  * So a conveter can be selected by multiple pins and playback on any of these
1039  * pins will generate sound on the external display, because audio flows from
1040  * the same converter to the display pipeline. Also muting one pin may make
1041  * other pins have no sound output.
1042  * So this function assures that an assigned converter for a pin is not selected
1043  * by any other pins.
1044  */
1045 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1046 					 hda_nid_t pin_nid,
1047 					 int dev_id, int mux_idx)
1048 {
1049 	struct hdmi_spec *spec = codec->spec;
1050 	hda_nid_t nid;
1051 	int cvt_idx, curr;
1052 	struct hdmi_spec_per_cvt *per_cvt;
1053 	struct hdmi_spec_per_pin *per_pin;
1054 	int pin_idx;
1055 
1056 	/* configure the pins connections */
1057 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1058 		int dev_id_saved;
1059 		int dev_num;
1060 
1061 		per_pin = get_pin(spec, pin_idx);
1062 		/*
1063 		 * pin not connected to monitor
1064 		 * no need to operate on it
1065 		 */
1066 		if (!per_pin->pcm)
1067 			continue;
1068 
1069 		if ((per_pin->pin_nid == pin_nid) &&
1070 			(per_pin->dev_id == dev_id))
1071 			continue;
1072 
1073 		/*
1074 		 * if per_pin->dev_id >= dev_num,
1075 		 * snd_hda_get_dev_select() will fail,
1076 		 * and the following operation is unpredictable.
1077 		 * So skip this situation.
1078 		 */
1079 		dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1080 		if (per_pin->dev_id >= dev_num)
1081 			continue;
1082 
1083 		nid = per_pin->pin_nid;
1084 
1085 		/*
1086 		 * Calling this function should not impact
1087 		 * on the device entry selection
1088 		 * So let's save the dev id for each pin,
1089 		 * and restore it when return
1090 		 */
1091 		dev_id_saved = snd_hda_get_dev_select(codec, nid);
1092 		snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1093 		curr = snd_hda_codec_read(codec, nid, 0,
1094 					  AC_VERB_GET_CONNECT_SEL, 0);
1095 		if (curr != mux_idx) {
1096 			snd_hda_set_dev_select(codec, nid, dev_id_saved);
1097 			continue;
1098 		}
1099 
1100 
1101 		/* choose an unassigned converter. The conveters in the
1102 		 * connection list are in the same order as in the codec.
1103 		 */
1104 		for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1105 			per_cvt = get_cvt(spec, cvt_idx);
1106 			if (!per_cvt->assigned) {
1107 				codec_dbg(codec,
1108 					  "choose cvt %d for pin nid %d\n",
1109 					cvt_idx, nid);
1110 				snd_hda_codec_write_cache(codec, nid, 0,
1111 					    AC_VERB_SET_CONNECT_SEL,
1112 					    cvt_idx);
1113 				break;
1114 			}
1115 		}
1116 		snd_hda_set_dev_select(codec, nid, dev_id_saved);
1117 	}
1118 }
1119 
1120 /* A wrapper of intel_not_share_asigned_cvt() */
1121 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1122 			hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1123 {
1124 	int mux_idx;
1125 	struct hdmi_spec *spec = codec->spec;
1126 
1127 	/* On Intel platform, the mapping of converter nid to
1128 	 * mux index of the pins are always the same.
1129 	 * The pin nid may be 0, this means all pins will not
1130 	 * share the converter.
1131 	 */
1132 	mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1133 	if (mux_idx >= 0)
1134 		intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1135 }
1136 
1137 /* skeleton caller of pin_cvt_fixup ops */
1138 static void pin_cvt_fixup(struct hda_codec *codec,
1139 			  struct hdmi_spec_per_pin *per_pin,
1140 			  hda_nid_t cvt_nid)
1141 {
1142 	struct hdmi_spec *spec = codec->spec;
1143 
1144 	if (spec->ops.pin_cvt_fixup)
1145 		spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1146 }
1147 
1148 /* called in hdmi_pcm_open when no pin is assigned to the PCM
1149  * in dyn_pcm_assign mode.
1150  */
1151 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1152 			 struct hda_codec *codec,
1153 			 struct snd_pcm_substream *substream)
1154 {
1155 	struct hdmi_spec *spec = codec->spec;
1156 	struct snd_pcm_runtime *runtime = substream->runtime;
1157 	int cvt_idx, pcm_idx;
1158 	struct hdmi_spec_per_cvt *per_cvt = NULL;
1159 	int err;
1160 
1161 	pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1162 	if (pcm_idx < 0)
1163 		return -EINVAL;
1164 
1165 	err = hdmi_choose_cvt(codec, -1, &cvt_idx);
1166 	if (err)
1167 		return err;
1168 
1169 	per_cvt = get_cvt(spec, cvt_idx);
1170 	per_cvt->assigned = 1;
1171 	hinfo->nid = per_cvt->cvt_nid;
1172 
1173 	pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1174 
1175 	set_bit(pcm_idx, &spec->pcm_in_use);
1176 	/* todo: setup spdif ctls assign */
1177 
1178 	/* Initially set the converter's capabilities */
1179 	hinfo->channels_min = per_cvt->channels_min;
1180 	hinfo->channels_max = per_cvt->channels_max;
1181 	hinfo->rates = per_cvt->rates;
1182 	hinfo->formats = per_cvt->formats;
1183 	hinfo->maxbps = per_cvt->maxbps;
1184 
1185 	/* Store the updated parameters */
1186 	runtime->hw.channels_min = hinfo->channels_min;
1187 	runtime->hw.channels_max = hinfo->channels_max;
1188 	runtime->hw.formats = hinfo->formats;
1189 	runtime->hw.rates = hinfo->rates;
1190 
1191 	snd_pcm_hw_constraint_step(substream->runtime, 0,
1192 				   SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1193 	return 0;
1194 }
1195 
1196 /*
1197  * HDA PCM callbacks
1198  */
1199 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1200 			 struct hda_codec *codec,
1201 			 struct snd_pcm_substream *substream)
1202 {
1203 	struct hdmi_spec *spec = codec->spec;
1204 	struct snd_pcm_runtime *runtime = substream->runtime;
1205 	int pin_idx, cvt_idx, pcm_idx;
1206 	struct hdmi_spec_per_pin *per_pin;
1207 	struct hdmi_eld *eld;
1208 	struct hdmi_spec_per_cvt *per_cvt = NULL;
1209 	int err;
1210 
1211 	/* Validate hinfo */
1212 	pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1213 	if (pcm_idx < 0)
1214 		return -EINVAL;
1215 
1216 	mutex_lock(&spec->pcm_lock);
1217 	pin_idx = hinfo_to_pin_index(codec, hinfo);
1218 	if (!spec->dyn_pcm_assign) {
1219 		if (snd_BUG_ON(pin_idx < 0)) {
1220 			err = -EINVAL;
1221 			goto unlock;
1222 		}
1223 	} else {
1224 		/* no pin is assigned to the PCM
1225 		 * PA need pcm open successfully when probe
1226 		 */
1227 		if (pin_idx < 0) {
1228 			err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1229 			goto unlock;
1230 		}
1231 	}
1232 
1233 	err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1234 	if (err < 0)
1235 		goto unlock;
1236 
1237 	per_cvt = get_cvt(spec, cvt_idx);
1238 	/* Claim converter */
1239 	per_cvt->assigned = 1;
1240 
1241 	set_bit(pcm_idx, &spec->pcm_in_use);
1242 	per_pin = get_pin(spec, pin_idx);
1243 	per_pin->cvt_nid = per_cvt->cvt_nid;
1244 	hinfo->nid = per_cvt->cvt_nid;
1245 
1246 	/* flip stripe flag for the assigned stream if supported */
1247 	if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE)
1248 		azx_stream(get_azx_dev(substream))->stripe = 1;
1249 
1250 	snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1251 	snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1252 			    AC_VERB_SET_CONNECT_SEL,
1253 			    per_pin->mux_idx);
1254 
1255 	/* configure unused pins to choose other converters */
1256 	pin_cvt_fixup(codec, per_pin, 0);
1257 
1258 	snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1259 
1260 	/* Initially set the converter's capabilities */
1261 	hinfo->channels_min = per_cvt->channels_min;
1262 	hinfo->channels_max = per_cvt->channels_max;
1263 	hinfo->rates = per_cvt->rates;
1264 	hinfo->formats = per_cvt->formats;
1265 	hinfo->maxbps = per_cvt->maxbps;
1266 
1267 	eld = &per_pin->sink_eld;
1268 	/* Restrict capabilities by ELD if this isn't disabled */
1269 	if (!static_hdmi_pcm && eld->eld_valid) {
1270 		snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1271 		if (hinfo->channels_min > hinfo->channels_max ||
1272 		    !hinfo->rates || !hinfo->formats) {
1273 			per_cvt->assigned = 0;
1274 			hinfo->nid = 0;
1275 			snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1276 			err = -ENODEV;
1277 			goto unlock;
1278 		}
1279 	}
1280 
1281 	/* Store the updated parameters */
1282 	runtime->hw.channels_min = hinfo->channels_min;
1283 	runtime->hw.channels_max = hinfo->channels_max;
1284 	runtime->hw.formats = hinfo->formats;
1285 	runtime->hw.rates = hinfo->rates;
1286 
1287 	snd_pcm_hw_constraint_step(substream->runtime, 0,
1288 				   SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1289  unlock:
1290 	mutex_unlock(&spec->pcm_lock);
1291 	return err;
1292 }
1293 
1294 /*
1295  * HDA/HDMI auto parsing
1296  */
1297 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1298 {
1299 	struct hdmi_spec *spec = codec->spec;
1300 	struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1301 	hda_nid_t pin_nid = per_pin->pin_nid;
1302 	int dev_id = per_pin->dev_id;
1303 	int conns;
1304 
1305 	if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1306 		codec_warn(codec,
1307 			   "HDMI: pin %d wcaps %#x does not support connection list\n",
1308 			   pin_nid, get_wcaps(codec, pin_nid));
1309 		return -EINVAL;
1310 	}
1311 
1312 	snd_hda_set_dev_select(codec, pin_nid, dev_id);
1313 
1314 	if (spec->intel_hsw_fixup) {
1315 		conns = spec->num_cvts;
1316 		memcpy(per_pin->mux_nids, spec->cvt_nids,
1317 		       sizeof(hda_nid_t) * conns);
1318 	} else {
1319 		conns = snd_hda_get_raw_connections(codec, pin_nid,
1320 						    per_pin->mux_nids,
1321 						    HDA_MAX_CONNECTIONS);
1322 	}
1323 
1324 	/* all the device entries on the same pin have the same conn list */
1325 	per_pin->num_mux_nids = conns;
1326 
1327 	return 0;
1328 }
1329 
1330 static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1331 			      struct hdmi_spec_per_pin *per_pin)
1332 {
1333 	int i;
1334 
1335 	/*
1336 	 * generic_hdmi_build_pcms() may allocate extra PCMs on some
1337 	 * platforms (with maximum of 'num_nids + dev_num - 1')
1338 	 *
1339 	 * The per_pin of pin_nid_idx=n and dev_id=m prefers to get pcm-n
1340 	 * if m==0. This guarantees that dynamic pcm assignments are compatible
1341 	 * with the legacy static per_pin-pcm assignment that existed in the
1342 	 * days before DP-MST.
1343 	 *
1344 	 * Intel DP-MST prefers this legacy behavior for compatibility, too.
1345 	 *
1346 	 * per_pin of m!=0 prefers to get pcm=(num_nids + (m - 1)).
1347 	 */
1348 
1349 	if (per_pin->dev_id == 0 || spec->intel_hsw_fixup) {
1350 		if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1351 			return per_pin->pin_nid_idx;
1352 	} else {
1353 		i = spec->num_nids + (per_pin->dev_id - 1);
1354 		if (i < spec->pcm_used && !(test_bit(i, &spec->pcm_bitmap)))
1355 			return i;
1356 	}
1357 
1358 	/* have a second try; check the area over num_nids */
1359 	for (i = spec->num_nids; i < spec->pcm_used; i++) {
1360 		if (!test_bit(i, &spec->pcm_bitmap))
1361 			return i;
1362 	}
1363 
1364 	/* the last try; check the empty slots in pins */
1365 	for (i = 0; i < spec->num_nids; i++) {
1366 		if (!test_bit(i, &spec->pcm_bitmap))
1367 			return i;
1368 	}
1369 	return -EBUSY;
1370 }
1371 
1372 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1373 				struct hdmi_spec_per_pin *per_pin)
1374 {
1375 	int idx;
1376 
1377 	/* pcm already be attached to the pin */
1378 	if (per_pin->pcm)
1379 		return;
1380 	idx = hdmi_find_pcm_slot(spec, per_pin);
1381 	if (idx == -EBUSY)
1382 		return;
1383 	per_pin->pcm_idx = idx;
1384 	per_pin->pcm = get_hdmi_pcm(spec, idx);
1385 	set_bit(idx, &spec->pcm_bitmap);
1386 }
1387 
1388 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1389 				struct hdmi_spec_per_pin *per_pin)
1390 {
1391 	int idx;
1392 
1393 	/* pcm already be detached from the pin */
1394 	if (!per_pin->pcm)
1395 		return;
1396 	idx = per_pin->pcm_idx;
1397 	per_pin->pcm_idx = -1;
1398 	per_pin->pcm = NULL;
1399 	if (idx >= 0 && idx < spec->pcm_used)
1400 		clear_bit(idx, &spec->pcm_bitmap);
1401 }
1402 
1403 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1404 		struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1405 {
1406 	int mux_idx;
1407 
1408 	for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1409 		if (per_pin->mux_nids[mux_idx] == cvt_nid)
1410 			break;
1411 	return mux_idx;
1412 }
1413 
1414 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1415 
1416 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1417 			   struct hdmi_spec_per_pin *per_pin)
1418 {
1419 	struct hda_codec *codec = per_pin->codec;
1420 	struct hda_pcm *pcm;
1421 	struct hda_pcm_stream *hinfo;
1422 	struct snd_pcm_substream *substream;
1423 	int mux_idx;
1424 	bool non_pcm;
1425 
1426 	if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1427 		pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1428 	else
1429 		return;
1430 	if (!pcm->pcm)
1431 		return;
1432 	if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1433 		return;
1434 
1435 	/* hdmi audio only uses playback and one substream */
1436 	hinfo = pcm->stream;
1437 	substream = pcm->pcm->streams[0].substream;
1438 
1439 	per_pin->cvt_nid = hinfo->nid;
1440 
1441 	mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1442 	if (mux_idx < per_pin->num_mux_nids) {
1443 		snd_hda_set_dev_select(codec, per_pin->pin_nid,
1444 				   per_pin->dev_id);
1445 		snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1446 				AC_VERB_SET_CONNECT_SEL,
1447 				mux_idx);
1448 	}
1449 	snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1450 
1451 	non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1452 	if (substream->runtime)
1453 		per_pin->channels = substream->runtime->channels;
1454 	per_pin->setup = true;
1455 	per_pin->mux_idx = mux_idx;
1456 
1457 	hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1458 }
1459 
1460 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1461 			   struct hdmi_spec_per_pin *per_pin)
1462 {
1463 	if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1464 		snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1465 
1466 	per_pin->chmap_set = false;
1467 	memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1468 
1469 	per_pin->setup = false;
1470 	per_pin->channels = 0;
1471 }
1472 
1473 static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec,
1474 					    struct hdmi_spec_per_pin *per_pin)
1475 {
1476 	struct hdmi_spec *spec = codec->spec;
1477 
1478 	if (per_pin->pcm_idx >= 0)
1479 		return spec->pcm_rec[per_pin->pcm_idx].jack;
1480 	else
1481 		return NULL;
1482 }
1483 
1484 /* update per_pin ELD from the given new ELD;
1485  * setup info frame and notification accordingly
1486  * also notify ELD kctl and report jack status changes
1487  */
1488 static void update_eld(struct hda_codec *codec,
1489 		       struct hdmi_spec_per_pin *per_pin,
1490 		       struct hdmi_eld *eld,
1491 		       int repoll)
1492 {
1493 	struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1494 	struct hdmi_spec *spec = codec->spec;
1495 	struct snd_jack *pcm_jack;
1496 	bool old_eld_valid = pin_eld->eld_valid;
1497 	bool eld_changed;
1498 	int pcm_idx;
1499 
1500 	if (eld->eld_valid) {
1501 		if (eld->eld_size <= 0 ||
1502 		    snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1503 				       eld->eld_size) < 0) {
1504 			eld->eld_valid = false;
1505 			if (repoll) {
1506 				schedule_delayed_work(&per_pin->work,
1507 						      msecs_to_jiffies(300));
1508 				return;
1509 			}
1510 		}
1511 	}
1512 
1513 	if (!eld->eld_valid || eld->eld_size <= 0) {
1514 		eld->eld_valid = false;
1515 		eld->eld_size = 0;
1516 	}
1517 
1518 	/* for monitor disconnection, save pcm_idx firstly */
1519 	pcm_idx = per_pin->pcm_idx;
1520 
1521 	/*
1522 	 * pcm_idx >=0 before update_eld() means it is in monitor
1523 	 * disconnected event. Jack must be fetched before update_eld().
1524 	 */
1525 	pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1526 
1527 	if (spec->dyn_pcm_assign) {
1528 		if (eld->eld_valid) {
1529 			hdmi_attach_hda_pcm(spec, per_pin);
1530 			hdmi_pcm_setup_pin(spec, per_pin);
1531 		} else {
1532 			hdmi_pcm_reset_pin(spec, per_pin);
1533 			hdmi_detach_hda_pcm(spec, per_pin);
1534 		}
1535 	}
1536 	/* if pcm_idx == -1, it means this is in monitor connection event
1537 	 * we can get the correct pcm_idx now.
1538 	 */
1539 	if (pcm_idx == -1)
1540 		pcm_idx = per_pin->pcm_idx;
1541 	if (!pcm_jack)
1542 		pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1543 
1544 	if (eld->eld_valid)
1545 		snd_hdmi_show_eld(codec, &eld->info);
1546 
1547 	eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1548 	eld_changed |= (pin_eld->monitor_present != eld->monitor_present);
1549 	if (!eld_changed && eld->eld_valid && pin_eld->eld_valid)
1550 		if (pin_eld->eld_size != eld->eld_size ||
1551 		    memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1552 			   eld->eld_size) != 0)
1553 			eld_changed = true;
1554 
1555 	if (eld_changed) {
1556 		pin_eld->monitor_present = eld->monitor_present;
1557 		pin_eld->eld_valid = eld->eld_valid;
1558 		pin_eld->eld_size = eld->eld_size;
1559 		if (eld->eld_valid)
1560 			memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1561 			       eld->eld_size);
1562 		pin_eld->info = eld->info;
1563 	}
1564 
1565 	/*
1566 	 * Re-setup pin and infoframe. This is needed e.g. when
1567 	 * - sink is first plugged-in
1568 	 * - transcoder can change during stream playback on Haswell
1569 	 *   and this can make HW reset converter selection on a pin.
1570 	 */
1571 	if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1572 		pin_cvt_fixup(codec, per_pin, 0);
1573 		hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1574 	}
1575 
1576 	if (eld_changed && pcm_idx >= 0)
1577 		snd_ctl_notify(codec->card,
1578 			       SNDRV_CTL_EVENT_MASK_VALUE |
1579 			       SNDRV_CTL_EVENT_MASK_INFO,
1580 			       &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1581 
1582 	if (eld_changed && pcm_jack)
1583 		snd_jack_report(pcm_jack,
1584 				(eld->monitor_present && eld->eld_valid) ?
1585 				SND_JACK_AVOUT : 0);
1586 }
1587 
1588 /* update ELD and jack state via HD-audio verbs */
1589 static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1590 					 int repoll)
1591 {
1592 	struct hda_codec *codec = per_pin->codec;
1593 	struct hdmi_spec *spec = codec->spec;
1594 	struct hdmi_eld *eld = &spec->temp_eld;
1595 	hda_nid_t pin_nid = per_pin->pin_nid;
1596 	int dev_id = per_pin->dev_id;
1597 	/*
1598 	 * Always execute a GetPinSense verb here, even when called from
1599 	 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1600 	 * response's PD bit is not the real PD value, but indicates that
1601 	 * the real PD value changed. An older version of the HD-audio
1602 	 * specification worked this way. Hence, we just ignore the data in
1603 	 * the unsolicited response to avoid custom WARs.
1604 	 */
1605 	int present;
1606 	int ret;
1607 
1608 	ret = snd_hda_power_up_pm(codec);
1609 	if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec)))
1610 		goto out;
1611 
1612 	present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id);
1613 
1614 	mutex_lock(&per_pin->lock);
1615 	eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1616 	if (eld->monitor_present)
1617 		eld->eld_valid  = !!(present & AC_PINSENSE_ELDV);
1618 	else
1619 		eld->eld_valid = false;
1620 
1621 	codec_dbg(codec,
1622 		"HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1623 		codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1624 
1625 	if (eld->eld_valid) {
1626 		if (spec->ops.pin_get_eld(codec, pin_nid, dev_id,
1627 					  eld->eld_buffer, &eld->eld_size) < 0)
1628 			eld->eld_valid = false;
1629 	}
1630 
1631 	update_eld(codec, per_pin, eld, repoll);
1632 	mutex_unlock(&per_pin->lock);
1633  out:
1634 	snd_hda_power_down_pm(codec);
1635 }
1636 
1637 /* update ELD and jack state via audio component */
1638 static void sync_eld_via_acomp(struct hda_codec *codec,
1639 			       struct hdmi_spec_per_pin *per_pin)
1640 {
1641 	struct hdmi_spec *spec = codec->spec;
1642 	struct hdmi_eld *eld = &spec->temp_eld;
1643 
1644 	mutex_lock(&per_pin->lock);
1645 	eld->monitor_present = false;
1646 	eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1647 				      per_pin->dev_id, &eld->monitor_present,
1648 				      eld->eld_buffer, ELD_MAX_SIZE);
1649 	eld->eld_valid = (eld->eld_size > 0);
1650 	update_eld(codec, per_pin, eld, 0);
1651 	mutex_unlock(&per_pin->lock);
1652 }
1653 
1654 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1655 {
1656 	struct hda_codec *codec = per_pin->codec;
1657 
1658 	if (!codec_has_acomp(codec))
1659 		hdmi_present_sense_via_verbs(per_pin, repoll);
1660 	else
1661 		sync_eld_via_acomp(codec, per_pin);
1662 }
1663 
1664 static void hdmi_repoll_eld(struct work_struct *work)
1665 {
1666 	struct hdmi_spec_per_pin *per_pin =
1667 	container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1668 	struct hda_codec *codec = per_pin->codec;
1669 	struct hdmi_spec *spec = codec->spec;
1670 	struct hda_jack_tbl *jack;
1671 
1672 	jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid,
1673 					per_pin->dev_id);
1674 	if (jack)
1675 		jack->jack_dirty = 1;
1676 
1677 	if (per_pin->repoll_count++ > 6)
1678 		per_pin->repoll_count = 0;
1679 
1680 	mutex_lock(&spec->pcm_lock);
1681 	hdmi_present_sense(per_pin, per_pin->repoll_count);
1682 	mutex_unlock(&spec->pcm_lock);
1683 }
1684 
1685 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1686 {
1687 	struct hdmi_spec *spec = codec->spec;
1688 	unsigned int caps, config;
1689 	int pin_idx;
1690 	struct hdmi_spec_per_pin *per_pin;
1691 	int err;
1692 	int dev_num, i;
1693 
1694 	caps = snd_hda_query_pin_caps(codec, pin_nid);
1695 	if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1696 		return 0;
1697 
1698 	/*
1699 	 * For DP MST audio, Configuration Default is the same for
1700 	 * all device entries on the same pin
1701 	 */
1702 	config = snd_hda_codec_get_pincfg(codec, pin_nid);
1703 	if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1704 		return 0;
1705 
1706 	/*
1707 	 * To simplify the implementation, malloc all
1708 	 * the virtual pins in the initialization statically
1709 	 */
1710 	if (spec->intel_hsw_fixup) {
1711 		/*
1712 		 * On Intel platforms, device entries number is
1713 		 * changed dynamically. If there is a DP MST
1714 		 * hub connected, the device entries number is 3.
1715 		 * Otherwise, it is 1.
1716 		 * Here we manually set dev_num to 3, so that
1717 		 * we can initialize all the device entries when
1718 		 * bootup statically.
1719 		 */
1720 		dev_num = 3;
1721 		spec->dev_num = 3;
1722 	} else if (spec->dyn_pcm_assign && codec->dp_mst) {
1723 		dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1724 		/*
1725 		 * spec->dev_num is the maxinum number of device entries
1726 		 * among all the pins
1727 		 */
1728 		spec->dev_num = (spec->dev_num > dev_num) ?
1729 			spec->dev_num : dev_num;
1730 	} else {
1731 		/*
1732 		 * If the platform doesn't support DP MST,
1733 		 * manually set dev_num to 1. This means
1734 		 * the pin has only one device entry.
1735 		 */
1736 		dev_num = 1;
1737 		spec->dev_num = 1;
1738 	}
1739 
1740 	for (i = 0; i < dev_num; i++) {
1741 		pin_idx = spec->num_pins;
1742 		per_pin = snd_array_new(&spec->pins);
1743 
1744 		if (!per_pin)
1745 			return -ENOMEM;
1746 
1747 		if (spec->dyn_pcm_assign) {
1748 			per_pin->pcm = NULL;
1749 			per_pin->pcm_idx = -1;
1750 		} else {
1751 			per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1752 			per_pin->pcm_idx = pin_idx;
1753 		}
1754 		per_pin->pin_nid = pin_nid;
1755 		per_pin->pin_nid_idx = spec->num_nids;
1756 		per_pin->dev_id = i;
1757 		per_pin->non_pcm = false;
1758 		snd_hda_set_dev_select(codec, pin_nid, i);
1759 		err = hdmi_read_pin_conn(codec, pin_idx);
1760 		if (err < 0)
1761 			return err;
1762 		spec->num_pins++;
1763 	}
1764 	spec->num_nids++;
1765 
1766 	return 0;
1767 }
1768 
1769 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1770 {
1771 	struct hdmi_spec *spec = codec->spec;
1772 	struct hdmi_spec_per_cvt *per_cvt;
1773 	unsigned int chans;
1774 	int err;
1775 
1776 	chans = get_wcaps(codec, cvt_nid);
1777 	chans = get_wcaps_channels(chans);
1778 
1779 	per_cvt = snd_array_new(&spec->cvts);
1780 	if (!per_cvt)
1781 		return -ENOMEM;
1782 
1783 	per_cvt->cvt_nid = cvt_nid;
1784 	per_cvt->channels_min = 2;
1785 	if (chans <= 16) {
1786 		per_cvt->channels_max = chans;
1787 		if (chans > spec->chmap.channels_max)
1788 			spec->chmap.channels_max = chans;
1789 	}
1790 
1791 	err = snd_hda_query_supported_pcm(codec, cvt_nid,
1792 					  &per_cvt->rates,
1793 					  &per_cvt->formats,
1794 					  &per_cvt->maxbps);
1795 	if (err < 0)
1796 		return err;
1797 
1798 	if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1799 		spec->cvt_nids[spec->num_cvts] = cvt_nid;
1800 	spec->num_cvts++;
1801 
1802 	return 0;
1803 }
1804 
1805 static int hdmi_parse_codec(struct hda_codec *codec)
1806 {
1807 	hda_nid_t nid;
1808 	int i, nodes;
1809 
1810 	nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1811 	if (!nid || nodes < 0) {
1812 		codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1813 		return -EINVAL;
1814 	}
1815 
1816 	for (i = 0; i < nodes; i++, nid++) {
1817 		unsigned int caps;
1818 		unsigned int type;
1819 
1820 		caps = get_wcaps(codec, nid);
1821 		type = get_wcaps_type(caps);
1822 
1823 		if (!(caps & AC_WCAP_DIGITAL))
1824 			continue;
1825 
1826 		switch (type) {
1827 		case AC_WID_AUD_OUT:
1828 			hdmi_add_cvt(codec, nid);
1829 			break;
1830 		case AC_WID_PIN:
1831 			hdmi_add_pin(codec, nid);
1832 			break;
1833 		}
1834 	}
1835 
1836 	return 0;
1837 }
1838 
1839 /*
1840  */
1841 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1842 {
1843 	struct hda_spdif_out *spdif;
1844 	bool non_pcm;
1845 
1846 	mutex_lock(&codec->spdif_mutex);
1847 	spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1848 	/* Add sanity check to pass klockwork check.
1849 	 * This should never happen.
1850 	 */
1851 	if (WARN_ON(spdif == NULL))
1852 		return true;
1853 	non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1854 	mutex_unlock(&codec->spdif_mutex);
1855 	return non_pcm;
1856 }
1857 
1858 /*
1859  * HDMI callbacks
1860  */
1861 
1862 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1863 					   struct hda_codec *codec,
1864 					   unsigned int stream_tag,
1865 					   unsigned int format,
1866 					   struct snd_pcm_substream *substream)
1867 {
1868 	hda_nid_t cvt_nid = hinfo->nid;
1869 	struct hdmi_spec *spec = codec->spec;
1870 	int pin_idx;
1871 	struct hdmi_spec_per_pin *per_pin;
1872 	struct snd_pcm_runtime *runtime = substream->runtime;
1873 	bool non_pcm;
1874 	int pinctl, stripe;
1875 	int err = 0;
1876 
1877 	mutex_lock(&spec->pcm_lock);
1878 	pin_idx = hinfo_to_pin_index(codec, hinfo);
1879 	if (spec->dyn_pcm_assign && pin_idx < 0) {
1880 		/* when dyn_pcm_assign and pcm is not bound to a pin
1881 		 * skip pin setup and return 0 to make audio playback
1882 		 * be ongoing
1883 		 */
1884 		pin_cvt_fixup(codec, NULL, cvt_nid);
1885 		snd_hda_codec_setup_stream(codec, cvt_nid,
1886 					stream_tag, 0, format);
1887 		goto unlock;
1888 	}
1889 
1890 	if (snd_BUG_ON(pin_idx < 0)) {
1891 		err = -EINVAL;
1892 		goto unlock;
1893 	}
1894 	per_pin = get_pin(spec, pin_idx);
1895 
1896 	/* Verify pin:cvt selections to avoid silent audio after S3.
1897 	 * After S3, the audio driver restores pin:cvt selections
1898 	 * but this can happen before gfx is ready and such selection
1899 	 * is overlooked by HW. Thus multiple pins can share a same
1900 	 * default convertor and mute control will affect each other,
1901 	 * which can cause a resumed audio playback become silent
1902 	 * after S3.
1903 	 */
1904 	pin_cvt_fixup(codec, per_pin, 0);
1905 
1906 	/* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1907 	/* Todo: add DP1.2 MST audio support later */
1908 	if (codec_has_acomp(codec))
1909 		snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
1910 					 per_pin->dev_id, runtime->rate);
1911 
1912 	non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1913 	mutex_lock(&per_pin->lock);
1914 	per_pin->channels = substream->runtime->channels;
1915 	per_pin->setup = true;
1916 
1917 	if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) {
1918 		stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core,
1919 							substream);
1920 		snd_hda_codec_write(codec, cvt_nid, 0,
1921 				    AC_VERB_SET_STRIPE_CONTROL,
1922 				    stripe);
1923 	}
1924 
1925 	hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1926 	mutex_unlock(&per_pin->lock);
1927 	if (spec->dyn_pin_out) {
1928 		snd_hda_set_dev_select(codec, per_pin->pin_nid,
1929 				       per_pin->dev_id);
1930 		pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1931 					    AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1932 		snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1933 				    AC_VERB_SET_PIN_WIDGET_CONTROL,
1934 				    pinctl | PIN_OUT);
1935 	}
1936 
1937 	/* snd_hda_set_dev_select() has been called before */
1938 	err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid,
1939 				     per_pin->dev_id, stream_tag, format);
1940  unlock:
1941 	mutex_unlock(&spec->pcm_lock);
1942 	return err;
1943 }
1944 
1945 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1946 					     struct hda_codec *codec,
1947 					     struct snd_pcm_substream *substream)
1948 {
1949 	snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1950 	return 0;
1951 }
1952 
1953 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1954 			  struct hda_codec *codec,
1955 			  struct snd_pcm_substream *substream)
1956 {
1957 	struct hdmi_spec *spec = codec->spec;
1958 	int cvt_idx, pin_idx, pcm_idx;
1959 	struct hdmi_spec_per_cvt *per_cvt;
1960 	struct hdmi_spec_per_pin *per_pin;
1961 	int pinctl;
1962 	int err = 0;
1963 
1964 	if (hinfo->nid) {
1965 		pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1966 		if (snd_BUG_ON(pcm_idx < 0))
1967 			return -EINVAL;
1968 		cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1969 		if (snd_BUG_ON(cvt_idx < 0))
1970 			return -EINVAL;
1971 		per_cvt = get_cvt(spec, cvt_idx);
1972 
1973 		snd_BUG_ON(!per_cvt->assigned);
1974 		per_cvt->assigned = 0;
1975 		hinfo->nid = 0;
1976 
1977 		azx_stream(get_azx_dev(substream))->stripe = 0;
1978 
1979 		mutex_lock(&spec->pcm_lock);
1980 		snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1981 		clear_bit(pcm_idx, &spec->pcm_in_use);
1982 		pin_idx = hinfo_to_pin_index(codec, hinfo);
1983 		if (spec->dyn_pcm_assign && pin_idx < 0)
1984 			goto unlock;
1985 
1986 		if (snd_BUG_ON(pin_idx < 0)) {
1987 			err = -EINVAL;
1988 			goto unlock;
1989 		}
1990 		per_pin = get_pin(spec, pin_idx);
1991 
1992 		if (spec->dyn_pin_out) {
1993 			snd_hda_set_dev_select(codec, per_pin->pin_nid,
1994 					       per_pin->dev_id);
1995 			pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1996 					AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1997 			snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1998 					    AC_VERB_SET_PIN_WIDGET_CONTROL,
1999 					    pinctl & ~PIN_OUT);
2000 		}
2001 
2002 		mutex_lock(&per_pin->lock);
2003 		per_pin->chmap_set = false;
2004 		memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
2005 
2006 		per_pin->setup = false;
2007 		per_pin->channels = 0;
2008 		mutex_unlock(&per_pin->lock);
2009 	unlock:
2010 		mutex_unlock(&spec->pcm_lock);
2011 	}
2012 
2013 	return err;
2014 }
2015 
2016 static const struct hda_pcm_ops generic_ops = {
2017 	.open = hdmi_pcm_open,
2018 	.close = hdmi_pcm_close,
2019 	.prepare = generic_hdmi_playback_pcm_prepare,
2020 	.cleanup = generic_hdmi_playback_pcm_cleanup,
2021 };
2022 
2023 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
2024 {
2025 	struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2026 	struct hdmi_spec *spec = codec->spec;
2027 	struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2028 
2029 	if (!per_pin)
2030 		return 0;
2031 
2032 	return per_pin->sink_eld.info.spk_alloc;
2033 }
2034 
2035 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2036 					unsigned char *chmap)
2037 {
2038 	struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2039 	struct hdmi_spec *spec = codec->spec;
2040 	struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2041 
2042 	/* chmap is already set to 0 in caller */
2043 	if (!per_pin)
2044 		return;
2045 
2046 	memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2047 }
2048 
2049 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2050 				unsigned char *chmap, int prepared)
2051 {
2052 	struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2053 	struct hdmi_spec *spec = codec->spec;
2054 	struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2055 
2056 	if (!per_pin)
2057 		return;
2058 	mutex_lock(&per_pin->lock);
2059 	per_pin->chmap_set = true;
2060 	memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2061 	if (prepared)
2062 		hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2063 	mutex_unlock(&per_pin->lock);
2064 }
2065 
2066 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2067 {
2068 	struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2069 	struct hdmi_spec *spec = codec->spec;
2070 	struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2071 
2072 	return per_pin ? true:false;
2073 }
2074 
2075 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2076 {
2077 	struct hdmi_spec *spec = codec->spec;
2078 	int idx, pcm_num;
2079 
2080 	/*
2081 	 * for non-mst mode, pcm number is the same as before
2082 	 * for DP MST mode without extra PCM, pcm number is same
2083 	 * for DP MST mode with extra PCMs, pcm number is
2084 	 *  (nid number + dev_num - 1)
2085 	 * dev_num is the device entry number in a pin
2086 	 */
2087 
2088 	if (codec->mst_no_extra_pcms)
2089 		pcm_num = spec->num_nids;
2090 	else
2091 		pcm_num = spec->num_nids + spec->dev_num - 1;
2092 
2093 	codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num);
2094 
2095 	for (idx = 0; idx < pcm_num; idx++) {
2096 		struct hda_pcm *info;
2097 		struct hda_pcm_stream *pstr;
2098 
2099 		info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2100 		if (!info)
2101 			return -ENOMEM;
2102 
2103 		spec->pcm_rec[idx].pcm = info;
2104 		spec->pcm_used++;
2105 		info->pcm_type = HDA_PCM_TYPE_HDMI;
2106 		info->own_chmap = true;
2107 
2108 		pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2109 		pstr->substreams = 1;
2110 		pstr->ops = generic_ops;
2111 		/* pcm number is less than 16 */
2112 		if (spec->pcm_used >= 16)
2113 			break;
2114 		/* other pstr fields are set in open */
2115 	}
2116 
2117 	return 0;
2118 }
2119 
2120 static void free_hdmi_jack_priv(struct snd_jack *jack)
2121 {
2122 	struct hdmi_pcm *pcm = jack->private_data;
2123 
2124 	pcm->jack = NULL;
2125 }
2126 
2127 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2128 {
2129 	char hdmi_str[32] = "HDMI/DP";
2130 	struct hdmi_spec *spec = codec->spec;
2131 	struct hdmi_spec_per_pin *per_pin = get_pin(spec, pcm_idx);
2132 	struct snd_jack *jack;
2133 	int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2134 	int err;
2135 
2136 	if (pcmdev > 0)
2137 		sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2138 	if (!spec->dyn_pcm_assign &&
2139 	    !is_jack_detectable(codec, per_pin->pin_nid))
2140 		strncat(hdmi_str, " Phantom",
2141 			sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2142 
2143 	err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack,
2144 			   true, false);
2145 	if (err < 0)
2146 		return err;
2147 
2148 	spec->pcm_rec[pcm_idx].jack = jack;
2149 	jack->private_data = &spec->pcm_rec[pcm_idx];
2150 	jack->private_free = free_hdmi_jack_priv;
2151 	return 0;
2152 }
2153 
2154 static int generic_hdmi_build_controls(struct hda_codec *codec)
2155 {
2156 	struct hdmi_spec *spec = codec->spec;
2157 	int dev, err;
2158 	int pin_idx, pcm_idx;
2159 
2160 	for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2161 		if (!get_pcm_rec(spec, pcm_idx)->pcm) {
2162 			/* no PCM: mark this for skipping permanently */
2163 			set_bit(pcm_idx, &spec->pcm_bitmap);
2164 			continue;
2165 		}
2166 
2167 		err = generic_hdmi_build_jack(codec, pcm_idx);
2168 		if (err < 0)
2169 			return err;
2170 
2171 		/* create the spdif for each pcm
2172 		 * pin will be bound when monitor is connected
2173 		 */
2174 		if (spec->dyn_pcm_assign)
2175 			err = snd_hda_create_dig_out_ctls(codec,
2176 					  0, spec->cvt_nids[0],
2177 					  HDA_PCM_TYPE_HDMI);
2178 		else {
2179 			struct hdmi_spec_per_pin *per_pin =
2180 				get_pin(spec, pcm_idx);
2181 			err = snd_hda_create_dig_out_ctls(codec,
2182 						  per_pin->pin_nid,
2183 						  per_pin->mux_nids[0],
2184 						  HDA_PCM_TYPE_HDMI);
2185 		}
2186 		if (err < 0)
2187 			return err;
2188 		snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2189 
2190 		dev = get_pcm_rec(spec, pcm_idx)->device;
2191 		if (dev != SNDRV_PCM_INVALID_DEVICE) {
2192 			/* add control for ELD Bytes */
2193 			err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2194 			if (err < 0)
2195 				return err;
2196 		}
2197 	}
2198 
2199 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2200 		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2201 
2202 		hdmi_present_sense(per_pin, 0);
2203 	}
2204 
2205 	/* add channel maps */
2206 	for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2207 		struct hda_pcm *pcm;
2208 
2209 		pcm = get_pcm_rec(spec, pcm_idx);
2210 		if (!pcm || !pcm->pcm)
2211 			break;
2212 		err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2213 		if (err < 0)
2214 			return err;
2215 	}
2216 
2217 	return 0;
2218 }
2219 
2220 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2221 {
2222 	struct hdmi_spec *spec = codec->spec;
2223 	int pin_idx;
2224 
2225 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2226 		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2227 
2228 		per_pin->codec = codec;
2229 		mutex_init(&per_pin->lock);
2230 		INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2231 		eld_proc_new(per_pin, pin_idx);
2232 	}
2233 	return 0;
2234 }
2235 
2236 static int generic_hdmi_init(struct hda_codec *codec)
2237 {
2238 	struct hdmi_spec *spec = codec->spec;
2239 	int pin_idx;
2240 
2241 	mutex_lock(&spec->bind_lock);
2242 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2243 		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2244 		hda_nid_t pin_nid = per_pin->pin_nid;
2245 		int dev_id = per_pin->dev_id;
2246 
2247 		snd_hda_set_dev_select(codec, pin_nid, dev_id);
2248 		hdmi_init_pin(codec, pin_nid);
2249 		if (codec_has_acomp(codec))
2250 			continue;
2251 		snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id,
2252 							jack_callback);
2253 	}
2254 	mutex_unlock(&spec->bind_lock);
2255 	return 0;
2256 }
2257 
2258 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2259 {
2260 	snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2261 	snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2262 }
2263 
2264 static void hdmi_array_free(struct hdmi_spec *spec)
2265 {
2266 	snd_array_free(&spec->pins);
2267 	snd_array_free(&spec->cvts);
2268 }
2269 
2270 static void generic_spec_free(struct hda_codec *codec)
2271 {
2272 	struct hdmi_spec *spec = codec->spec;
2273 
2274 	if (spec) {
2275 		hdmi_array_free(spec);
2276 		kfree(spec);
2277 		codec->spec = NULL;
2278 	}
2279 	codec->dp_mst = false;
2280 }
2281 
2282 static void generic_hdmi_free(struct hda_codec *codec)
2283 {
2284 	struct hdmi_spec *spec = codec->spec;
2285 	int pin_idx, pcm_idx;
2286 
2287 	if (spec->acomp_registered) {
2288 		snd_hdac_acomp_exit(&codec->bus->core);
2289 	} else if (codec_has_acomp(codec)) {
2290 		snd_hdac_acomp_register_notifier(&codec->bus->core, NULL);
2291 	}
2292 	codec->relaxed_resume = 0;
2293 
2294 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2295 		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2296 		cancel_delayed_work_sync(&per_pin->work);
2297 		eld_proc_free(per_pin);
2298 	}
2299 
2300 	for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2301 		if (spec->pcm_rec[pcm_idx].jack == NULL)
2302 			continue;
2303 		if (spec->dyn_pcm_assign)
2304 			snd_device_free(codec->card,
2305 					spec->pcm_rec[pcm_idx].jack);
2306 		else
2307 			spec->pcm_rec[pcm_idx].jack = NULL;
2308 	}
2309 
2310 	generic_spec_free(codec);
2311 }
2312 
2313 #ifdef CONFIG_PM
2314 static int generic_hdmi_resume(struct hda_codec *codec)
2315 {
2316 	struct hdmi_spec *spec = codec->spec;
2317 	int pin_idx;
2318 
2319 	codec->patch_ops.init(codec);
2320 	snd_hda_regmap_sync(codec);
2321 
2322 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2323 		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2324 		hdmi_present_sense(per_pin, 1);
2325 	}
2326 	return 0;
2327 }
2328 #endif
2329 
2330 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2331 	.init			= generic_hdmi_init,
2332 	.free			= generic_hdmi_free,
2333 	.build_pcms		= generic_hdmi_build_pcms,
2334 	.build_controls		= generic_hdmi_build_controls,
2335 	.unsol_event		= hdmi_unsol_event,
2336 #ifdef CONFIG_PM
2337 	.resume			= generic_hdmi_resume,
2338 #endif
2339 };
2340 
2341 static const struct hdmi_ops generic_standard_hdmi_ops = {
2342 	.pin_get_eld				= hdmi_pin_get_eld,
2343 	.pin_setup_infoframe			= hdmi_pin_setup_infoframe,
2344 	.pin_hbr_setup				= hdmi_pin_hbr_setup,
2345 	.setup_stream				= hdmi_setup_stream,
2346 };
2347 
2348 /* allocate codec->spec and assign/initialize generic parser ops */
2349 static int alloc_generic_hdmi(struct hda_codec *codec)
2350 {
2351 	struct hdmi_spec *spec;
2352 
2353 	spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2354 	if (!spec)
2355 		return -ENOMEM;
2356 
2357 	spec->codec = codec;
2358 	spec->ops = generic_standard_hdmi_ops;
2359 	spec->dev_num = 1;	/* initialize to 1 */
2360 	mutex_init(&spec->pcm_lock);
2361 	mutex_init(&spec->bind_lock);
2362 	snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2363 
2364 	spec->chmap.ops.get_chmap = hdmi_get_chmap;
2365 	spec->chmap.ops.set_chmap = hdmi_set_chmap;
2366 	spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2367 	spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc,
2368 
2369 	codec->spec = spec;
2370 	hdmi_array_init(spec, 4);
2371 
2372 	codec->patch_ops = generic_hdmi_patch_ops;
2373 
2374 	return 0;
2375 }
2376 
2377 /* generic HDMI parser */
2378 static int patch_generic_hdmi(struct hda_codec *codec)
2379 {
2380 	int err;
2381 
2382 	err = alloc_generic_hdmi(codec);
2383 	if (err < 0)
2384 		return err;
2385 
2386 	err = hdmi_parse_codec(codec);
2387 	if (err < 0) {
2388 		generic_spec_free(codec);
2389 		return err;
2390 	}
2391 
2392 	generic_hdmi_init_per_pins(codec);
2393 	return 0;
2394 }
2395 
2396 /*
2397  * generic audio component binding
2398  */
2399 
2400 /* turn on / off the unsol event jack detection dynamically */
2401 static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid,
2402 				  int dev_id, bool use_acomp)
2403 {
2404 	struct hda_jack_tbl *tbl;
2405 
2406 	tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id);
2407 	if (tbl) {
2408 		/* clear unsol even if component notifier is used, or re-enable
2409 		 * if notifier is cleared
2410 		 */
2411 		unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag);
2412 		snd_hda_codec_write_cache(codec, nid, 0,
2413 					  AC_VERB_SET_UNSOLICITED_ENABLE, val);
2414 	}
2415 }
2416 
2417 /* set up / clear component notifier dynamically */
2418 static void generic_acomp_notifier_set(struct drm_audio_component *acomp,
2419 				       bool use_acomp)
2420 {
2421 	struct hdmi_spec *spec;
2422 	int i;
2423 
2424 	spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops);
2425 	mutex_lock(&spec->bind_lock);
2426 	spec->use_acomp_notifier = use_acomp;
2427 	spec->codec->relaxed_resume = use_acomp;
2428 	/* reprogram each jack detection logic depending on the notifier */
2429 	for (i = 0; i < spec->num_pins; i++)
2430 		reprogram_jack_detect(spec->codec,
2431 				      get_pin(spec, i)->pin_nid,
2432 				      get_pin(spec, i)->dev_id,
2433 				      use_acomp);
2434 	mutex_unlock(&spec->bind_lock);
2435 }
2436 
2437 /* enable / disable the notifier via master bind / unbind */
2438 static int generic_acomp_master_bind(struct device *dev,
2439 				     struct drm_audio_component *acomp)
2440 {
2441 	generic_acomp_notifier_set(acomp, true);
2442 	return 0;
2443 }
2444 
2445 static void generic_acomp_master_unbind(struct device *dev,
2446 					struct drm_audio_component *acomp)
2447 {
2448 	generic_acomp_notifier_set(acomp, false);
2449 }
2450 
2451 /* check whether both HD-audio and DRM PCI devices belong to the same bus */
2452 static int match_bound_vga(struct device *dev, int subtype, void *data)
2453 {
2454 	struct hdac_bus *bus = data;
2455 	struct pci_dev *pci, *master;
2456 
2457 	if (!dev_is_pci(dev) || !dev_is_pci(bus->dev))
2458 		return 0;
2459 	master = to_pci_dev(bus->dev);
2460 	pci = to_pci_dev(dev);
2461 	return master->bus == pci->bus;
2462 }
2463 
2464 /* audio component notifier for AMD/Nvidia HDMI codecs */
2465 static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id)
2466 {
2467 	struct hda_codec *codec = audio_ptr;
2468 	struct hdmi_spec *spec = codec->spec;
2469 	hda_nid_t pin_nid = spec->port2pin(codec, port);
2470 
2471 	if (!pin_nid)
2472 		return;
2473 	if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN)
2474 		return;
2475 	/* skip notification during system suspend (but not in runtime PM);
2476 	 * the state will be updated at resume
2477 	 */
2478 	if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2479 		return;
2480 	/* ditto during suspend/resume process itself */
2481 	if (snd_hdac_is_in_pm(&codec->core))
2482 		return;
2483 
2484 	check_presence_and_report(codec, pin_nid, dev_id);
2485 }
2486 
2487 /* set up the private drm_audio_ops from the template */
2488 static void setup_drm_audio_ops(struct hda_codec *codec,
2489 				const struct drm_audio_component_audio_ops *ops)
2490 {
2491 	struct hdmi_spec *spec = codec->spec;
2492 
2493 	spec->drm_audio_ops.audio_ptr = codec;
2494 	/* intel_audio_codec_enable() or intel_audio_codec_disable()
2495 	 * will call pin_eld_notify with using audio_ptr pointer
2496 	 * We need make sure audio_ptr is really setup
2497 	 */
2498 	wmb();
2499 	spec->drm_audio_ops.pin2port = ops->pin2port;
2500 	spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify;
2501 	spec->drm_audio_ops.master_bind = ops->master_bind;
2502 	spec->drm_audio_ops.master_unbind = ops->master_unbind;
2503 }
2504 
2505 /* initialize the generic HDMI audio component */
2506 static void generic_acomp_init(struct hda_codec *codec,
2507 			       const struct drm_audio_component_audio_ops *ops,
2508 			       int (*port2pin)(struct hda_codec *, int))
2509 {
2510 	struct hdmi_spec *spec = codec->spec;
2511 
2512 	if (!enable_acomp) {
2513 		codec_info(codec, "audio component disabled by module option\n");
2514 		return;
2515 	}
2516 
2517 	spec->port2pin = port2pin;
2518 	setup_drm_audio_ops(codec, ops);
2519 	if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops,
2520 				 match_bound_vga, 0)) {
2521 		spec->acomp_registered = true;
2522 		codec->bus->keep_power = 0;
2523 	}
2524 }
2525 
2526 /*
2527  * Intel codec parsers and helpers
2528  */
2529 
2530 #define INTEL_GET_VENDOR_VERB	0xf81
2531 #define INTEL_SET_VENDOR_VERB	0x781
2532 #define INTEL_EN_DP12		0x02	/* enable DP 1.2 features */
2533 #define INTEL_EN_ALL_PIN_CVTS	0x01	/* enable 2nd & 3rd pins and convertors */
2534 
2535 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2536 					  bool update_tree)
2537 {
2538 	unsigned int vendor_param;
2539 	struct hdmi_spec *spec = codec->spec;
2540 
2541 	vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2542 				INTEL_GET_VENDOR_VERB, 0);
2543 	if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2544 		return;
2545 
2546 	vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2547 	vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2548 				INTEL_SET_VENDOR_VERB, vendor_param);
2549 	if (vendor_param == -1)
2550 		return;
2551 
2552 	if (update_tree)
2553 		snd_hda_codec_update_widgets(codec);
2554 }
2555 
2556 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2557 {
2558 	unsigned int vendor_param;
2559 	struct hdmi_spec *spec = codec->spec;
2560 
2561 	vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2562 				INTEL_GET_VENDOR_VERB, 0);
2563 	if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2564 		return;
2565 
2566 	/* enable DP1.2 mode */
2567 	vendor_param |= INTEL_EN_DP12;
2568 	snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2569 	snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2570 				INTEL_SET_VENDOR_VERB, vendor_param);
2571 }
2572 
2573 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2574  * Otherwise you may get severe h/w communication errors.
2575  */
2576 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2577 				unsigned int power_state)
2578 {
2579 	if (power_state == AC_PWRST_D0) {
2580 		intel_haswell_enable_all_pins(codec, false);
2581 		intel_haswell_fixup_enable_dp12(codec);
2582 	}
2583 
2584 	snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2585 	snd_hda_codec_set_power_to_all(codec, fg, power_state);
2586 }
2587 
2588 /* There is a fixed mapping between audio pin node and display port.
2589  * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:
2590  * Pin Widget 5 - PORT B (port = 1 in i915 driver)
2591  * Pin Widget 6 - PORT C (port = 2 in i915 driver)
2592  * Pin Widget 7 - PORT D (port = 3 in i915 driver)
2593  *
2594  * on VLV, ILK:
2595  * Pin Widget 4 - PORT B (port = 1 in i915 driver)
2596  * Pin Widget 5 - PORT C (port = 2 in i915 driver)
2597  * Pin Widget 6 - PORT D (port = 3 in i915 driver)
2598  */
2599 static int intel_base_nid(struct hda_codec *codec)
2600 {
2601 	switch (codec->core.vendor_id) {
2602 	case 0x80860054: /* ILK */
2603 	case 0x80862804: /* ILK */
2604 	case 0x80862882: /* VLV */
2605 		return 4;
2606 	default:
2607 		return 5;
2608 	}
2609 }
2610 
2611 static int intel_pin2port(void *audio_ptr, int pin_nid)
2612 {
2613 	struct hda_codec *codec = audio_ptr;
2614 	struct hdmi_spec *spec = codec->spec;
2615 	int base_nid, i;
2616 
2617 	if (!spec->port_num) {
2618 		base_nid = intel_base_nid(codec);
2619 		if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3))
2620 			return -1;
2621 		return pin_nid - base_nid + 1;
2622 	}
2623 
2624 	/*
2625 	 * looking for the pin number in the mapping table and return
2626 	 * the index which indicate the port number
2627 	 */
2628 	for (i = 0; i < spec->port_num; i++) {
2629 		if (pin_nid == spec->port_map[i])
2630 			return i;
2631 	}
2632 
2633 	codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid);
2634 	return -1;
2635 }
2636 
2637 static int intel_port2pin(struct hda_codec *codec, int port)
2638 {
2639 	struct hdmi_spec *spec = codec->spec;
2640 
2641 	if (!spec->port_num) {
2642 		/* we assume only from port-B to port-D */
2643 		if (port < 1 || port > 3)
2644 			return 0;
2645 		return port + intel_base_nid(codec) - 1;
2646 	}
2647 
2648 	if (port < 0 || port >= spec->port_num)
2649 		return 0;
2650 	return spec->port_map[port];
2651 }
2652 
2653 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2654 {
2655 	struct hda_codec *codec = audio_ptr;
2656 	int pin_nid;
2657 	int dev_id = pipe;
2658 
2659 	pin_nid = intel_port2pin(codec, port);
2660 	if (!pin_nid)
2661 		return;
2662 	/* skip notification during system suspend (but not in runtime PM);
2663 	 * the state will be updated at resume
2664 	 */
2665 	if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2666 		return;
2667 	/* ditto during suspend/resume process itself */
2668 	if (snd_hdac_is_in_pm(&codec->core))
2669 		return;
2670 
2671 	snd_hdac_i915_set_bclk(&codec->bus->core);
2672 	check_presence_and_report(codec, pin_nid, dev_id);
2673 }
2674 
2675 static const struct drm_audio_component_audio_ops intel_audio_ops = {
2676 	.pin2port = intel_pin2port,
2677 	.pin_eld_notify = intel_pin_eld_notify,
2678 };
2679 
2680 /* register i915 component pin_eld_notify callback */
2681 static void register_i915_notifier(struct hda_codec *codec)
2682 {
2683 	struct hdmi_spec *spec = codec->spec;
2684 
2685 	spec->use_acomp_notifier = true;
2686 	spec->port2pin = intel_port2pin;
2687 	setup_drm_audio_ops(codec, &intel_audio_ops);
2688 	snd_hdac_acomp_register_notifier(&codec->bus->core,
2689 					&spec->drm_audio_ops);
2690 	/* no need for forcible resume for jack check thanks to notifier */
2691 	codec->relaxed_resume = 1;
2692 }
2693 
2694 /* setup_stream ops override for HSW+ */
2695 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2696 				 hda_nid_t pin_nid, int dev_id, u32 stream_tag,
2697 				 int format)
2698 {
2699 	haswell_verify_D0(codec, cvt_nid, pin_nid);
2700 	return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
2701 				 stream_tag, format);
2702 }
2703 
2704 /* pin_cvt_fixup ops override for HSW+ and VLV+ */
2705 static void i915_pin_cvt_fixup(struct hda_codec *codec,
2706 			       struct hdmi_spec_per_pin *per_pin,
2707 			       hda_nid_t cvt_nid)
2708 {
2709 	if (per_pin) {
2710 		snd_hda_set_dev_select(codec, per_pin->pin_nid,
2711 			       per_pin->dev_id);
2712 		intel_verify_pin_cvt_connect(codec, per_pin);
2713 		intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2714 				     per_pin->dev_id, per_pin->mux_idx);
2715 	} else {
2716 		intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2717 	}
2718 }
2719 
2720 /* precondition and allocation for Intel codecs */
2721 static int alloc_intel_hdmi(struct hda_codec *codec)
2722 {
2723 	int err;
2724 
2725 	/* requires i915 binding */
2726 	if (!codec->bus->core.audio_component) {
2727 		codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2728 		/* set probe_id here to prevent generic fallback binding */
2729 		codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
2730 		return -ENODEV;
2731 	}
2732 
2733 	err = alloc_generic_hdmi(codec);
2734 	if (err < 0)
2735 		return err;
2736 	/* no need to handle unsol events */
2737 	codec->patch_ops.unsol_event = NULL;
2738 	return 0;
2739 }
2740 
2741 /* parse and post-process for Intel codecs */
2742 static int parse_intel_hdmi(struct hda_codec *codec)
2743 {
2744 	int err, retries = 3;
2745 
2746 	do {
2747 		err = hdmi_parse_codec(codec);
2748 	} while (err < 0 && retries--);
2749 
2750 	if (err < 0) {
2751 		generic_spec_free(codec);
2752 		return err;
2753 	}
2754 
2755 	generic_hdmi_init_per_pins(codec);
2756 	register_i915_notifier(codec);
2757 	return 0;
2758 }
2759 
2760 /* Intel Haswell and onwards; audio component with eld notifier */
2761 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid,
2762 				 const int *port_map, int port_num)
2763 {
2764 	struct hdmi_spec *spec;
2765 	int err;
2766 
2767 	err = alloc_intel_hdmi(codec);
2768 	if (err < 0)
2769 		return err;
2770 	spec = codec->spec;
2771 	codec->dp_mst = true;
2772 	spec->dyn_pcm_assign = true;
2773 	spec->vendor_nid = vendor_nid;
2774 	spec->port_map = port_map;
2775 	spec->port_num = port_num;
2776 	spec->intel_hsw_fixup = true;
2777 
2778 	intel_haswell_enable_all_pins(codec, true);
2779 	intel_haswell_fixup_enable_dp12(codec);
2780 
2781 	codec->display_power_control = 1;
2782 
2783 	codec->patch_ops.set_power_state = haswell_set_power_state;
2784 	codec->depop_delay = 0;
2785 	codec->auto_runtime_pm = 1;
2786 
2787 	spec->ops.setup_stream = i915_hsw_setup_stream;
2788 	spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2789 
2790 	return parse_intel_hdmi(codec);
2791 }
2792 
2793 static int patch_i915_hsw_hdmi(struct hda_codec *codec)
2794 {
2795 	return intel_hsw_common_init(codec, 0x08, NULL, 0);
2796 }
2797 
2798 static int patch_i915_glk_hdmi(struct hda_codec *codec)
2799 {
2800 	return intel_hsw_common_init(codec, 0x0b, NULL, 0);
2801 }
2802 
2803 static int patch_i915_icl_hdmi(struct hda_codec *codec)
2804 {
2805 	/*
2806 	 * pin to port mapping table where the value indicate the pin number and
2807 	 * the index indicate the port number.
2808 	 */
2809 	static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb};
2810 
2811 	return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map));
2812 }
2813 
2814 static int patch_i915_tgl_hdmi(struct hda_codec *codec)
2815 {
2816 	/*
2817 	 * pin to port mapping table where the value indicate the pin number and
2818 	 * the index indicate the port number.
2819 	 */
2820 	static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf};
2821 
2822 	return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map));
2823 }
2824 
2825 /* Intel Baytrail and Braswell; with eld notifier */
2826 static int patch_i915_byt_hdmi(struct hda_codec *codec)
2827 {
2828 	struct hdmi_spec *spec;
2829 	int err;
2830 
2831 	err = alloc_intel_hdmi(codec);
2832 	if (err < 0)
2833 		return err;
2834 	spec = codec->spec;
2835 
2836 	/* For Valleyview/Cherryview, only the display codec is in the display
2837 	 * power well and can use link_power ops to request/release the power.
2838 	 */
2839 	codec->display_power_control = 1;
2840 
2841 	codec->depop_delay = 0;
2842 	codec->auto_runtime_pm = 1;
2843 
2844 	spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2845 
2846 	return parse_intel_hdmi(codec);
2847 }
2848 
2849 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
2850 static int patch_i915_cpt_hdmi(struct hda_codec *codec)
2851 {
2852 	int err;
2853 
2854 	err = alloc_intel_hdmi(codec);
2855 	if (err < 0)
2856 		return err;
2857 	return parse_intel_hdmi(codec);
2858 }
2859 
2860 /*
2861  * Shared non-generic implementations
2862  */
2863 
2864 static int simple_playback_build_pcms(struct hda_codec *codec)
2865 {
2866 	struct hdmi_spec *spec = codec->spec;
2867 	struct hda_pcm *info;
2868 	unsigned int chans;
2869 	struct hda_pcm_stream *pstr;
2870 	struct hdmi_spec_per_cvt *per_cvt;
2871 
2872 	per_cvt = get_cvt(spec, 0);
2873 	chans = get_wcaps(codec, per_cvt->cvt_nid);
2874 	chans = get_wcaps_channels(chans);
2875 
2876 	info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2877 	if (!info)
2878 		return -ENOMEM;
2879 	spec->pcm_rec[0].pcm = info;
2880 	info->pcm_type = HDA_PCM_TYPE_HDMI;
2881 	pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2882 	*pstr = spec->pcm_playback;
2883 	pstr->nid = per_cvt->cvt_nid;
2884 	if (pstr->channels_max <= 2 && chans && chans <= 16)
2885 		pstr->channels_max = chans;
2886 
2887 	return 0;
2888 }
2889 
2890 /* unsolicited event for jack sensing */
2891 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2892 				    unsigned int res)
2893 {
2894 	snd_hda_jack_set_dirty_all(codec);
2895 	snd_hda_jack_report_sync(codec);
2896 }
2897 
2898 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2899  * as long as spec->pins[] is set correctly
2900  */
2901 #define simple_hdmi_build_jack	generic_hdmi_build_jack
2902 
2903 static int simple_playback_build_controls(struct hda_codec *codec)
2904 {
2905 	struct hdmi_spec *spec = codec->spec;
2906 	struct hdmi_spec_per_cvt *per_cvt;
2907 	int err;
2908 
2909 	per_cvt = get_cvt(spec, 0);
2910 	err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2911 					  per_cvt->cvt_nid,
2912 					  HDA_PCM_TYPE_HDMI);
2913 	if (err < 0)
2914 		return err;
2915 	return simple_hdmi_build_jack(codec, 0);
2916 }
2917 
2918 static int simple_playback_init(struct hda_codec *codec)
2919 {
2920 	struct hdmi_spec *spec = codec->spec;
2921 	struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2922 	hda_nid_t pin = per_pin->pin_nid;
2923 
2924 	snd_hda_codec_write(codec, pin, 0,
2925 			    AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2926 	/* some codecs require to unmute the pin */
2927 	if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2928 		snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2929 				    AMP_OUT_UNMUTE);
2930 	snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id);
2931 	return 0;
2932 }
2933 
2934 static void simple_playback_free(struct hda_codec *codec)
2935 {
2936 	struct hdmi_spec *spec = codec->spec;
2937 
2938 	hdmi_array_free(spec);
2939 	kfree(spec);
2940 }
2941 
2942 /*
2943  * Nvidia specific implementations
2944  */
2945 
2946 #define Nv_VERB_SET_Channel_Allocation          0xF79
2947 #define Nv_VERB_SET_Info_Frame_Checksum         0xF7A
2948 #define Nv_VERB_SET_Audio_Protection_On         0xF98
2949 #define Nv_VERB_SET_Audio_Protection_Off        0xF99
2950 
2951 #define nvhdmi_master_con_nid_7x	0x04
2952 #define nvhdmi_master_pin_nid_7x	0x05
2953 
2954 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2955 	/*front, rear, clfe, rear_surr */
2956 	0x6, 0x8, 0xa, 0xc,
2957 };
2958 
2959 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2960 	/* set audio protect on */
2961 	{ 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2962 	/* enable digital output on pin widget */
2963 	{ 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2964 	{} /* terminator */
2965 };
2966 
2967 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2968 	/* set audio protect on */
2969 	{ 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2970 	/* enable digital output on pin widget */
2971 	{ 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2972 	{ 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2973 	{ 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2974 	{ 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2975 	{ 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2976 	{} /* terminator */
2977 };
2978 
2979 #ifdef LIMITED_RATE_FMT_SUPPORT
2980 /* support only the safe format and rate */
2981 #define SUPPORTED_RATES		SNDRV_PCM_RATE_48000
2982 #define SUPPORTED_MAXBPS	16
2983 #define SUPPORTED_FORMATS	SNDRV_PCM_FMTBIT_S16_LE
2984 #else
2985 /* support all rates and formats */
2986 #define SUPPORTED_RATES \
2987 	(SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2988 	SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2989 	 SNDRV_PCM_RATE_192000)
2990 #define SUPPORTED_MAXBPS	24
2991 #define SUPPORTED_FORMATS \
2992 	(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2993 #endif
2994 
2995 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2996 {
2997 	snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2998 	return 0;
2999 }
3000 
3001 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
3002 {
3003 	snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
3004 	return 0;
3005 }
3006 
3007 static const unsigned int channels_2_6_8[] = {
3008 	2, 6, 8
3009 };
3010 
3011 static const unsigned int channels_2_8[] = {
3012 	2, 8
3013 };
3014 
3015 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
3016 	.count = ARRAY_SIZE(channels_2_6_8),
3017 	.list = channels_2_6_8,
3018 	.mask = 0,
3019 };
3020 
3021 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
3022 	.count = ARRAY_SIZE(channels_2_8),
3023 	.list = channels_2_8,
3024 	.mask = 0,
3025 };
3026 
3027 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
3028 				    struct hda_codec *codec,
3029 				    struct snd_pcm_substream *substream)
3030 {
3031 	struct hdmi_spec *spec = codec->spec;
3032 	const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
3033 
3034 	switch (codec->preset->vendor_id) {
3035 	case 0x10de0002:
3036 	case 0x10de0003:
3037 	case 0x10de0005:
3038 	case 0x10de0006:
3039 		hw_constraints_channels = &hw_constraints_2_8_channels;
3040 		break;
3041 	case 0x10de0007:
3042 		hw_constraints_channels = &hw_constraints_2_6_8_channels;
3043 		break;
3044 	default:
3045 		break;
3046 	}
3047 
3048 	if (hw_constraints_channels != NULL) {
3049 		snd_pcm_hw_constraint_list(substream->runtime, 0,
3050 				SNDRV_PCM_HW_PARAM_CHANNELS,
3051 				hw_constraints_channels);
3052 	} else {
3053 		snd_pcm_hw_constraint_step(substream->runtime, 0,
3054 					   SNDRV_PCM_HW_PARAM_CHANNELS, 2);
3055 	}
3056 
3057 	return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3058 }
3059 
3060 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
3061 				     struct hda_codec *codec,
3062 				     struct snd_pcm_substream *substream)
3063 {
3064 	struct hdmi_spec *spec = codec->spec;
3065 	return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3066 }
3067 
3068 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3069 				       struct hda_codec *codec,
3070 				       unsigned int stream_tag,
3071 				       unsigned int format,
3072 				       struct snd_pcm_substream *substream)
3073 {
3074 	struct hdmi_spec *spec = codec->spec;
3075 	return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3076 					     stream_tag, format, substream);
3077 }
3078 
3079 static const struct hda_pcm_stream simple_pcm_playback = {
3080 	.substreams = 1,
3081 	.channels_min = 2,
3082 	.channels_max = 2,
3083 	.ops = {
3084 		.open = simple_playback_pcm_open,
3085 		.close = simple_playback_pcm_close,
3086 		.prepare = simple_playback_pcm_prepare
3087 	},
3088 };
3089 
3090 static const struct hda_codec_ops simple_hdmi_patch_ops = {
3091 	.build_controls = simple_playback_build_controls,
3092 	.build_pcms = simple_playback_build_pcms,
3093 	.init = simple_playback_init,
3094 	.free = simple_playback_free,
3095 	.unsol_event = simple_hdmi_unsol_event,
3096 };
3097 
3098 static int patch_simple_hdmi(struct hda_codec *codec,
3099 			     hda_nid_t cvt_nid, hda_nid_t pin_nid)
3100 {
3101 	struct hdmi_spec *spec;
3102 	struct hdmi_spec_per_cvt *per_cvt;
3103 	struct hdmi_spec_per_pin *per_pin;
3104 
3105 	spec = kzalloc(sizeof(*spec), GFP_KERNEL);
3106 	if (!spec)
3107 		return -ENOMEM;
3108 
3109 	spec->codec = codec;
3110 	codec->spec = spec;
3111 	hdmi_array_init(spec, 1);
3112 
3113 	spec->multiout.num_dacs = 0;  /* no analog */
3114 	spec->multiout.max_channels = 2;
3115 	spec->multiout.dig_out_nid = cvt_nid;
3116 	spec->num_cvts = 1;
3117 	spec->num_pins = 1;
3118 	per_pin = snd_array_new(&spec->pins);
3119 	per_cvt = snd_array_new(&spec->cvts);
3120 	if (!per_pin || !per_cvt) {
3121 		simple_playback_free(codec);
3122 		return -ENOMEM;
3123 	}
3124 	per_cvt->cvt_nid = cvt_nid;
3125 	per_pin->pin_nid = pin_nid;
3126 	spec->pcm_playback = simple_pcm_playback;
3127 
3128 	codec->patch_ops = simple_hdmi_patch_ops;
3129 
3130 	return 0;
3131 }
3132 
3133 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
3134 						    int channels)
3135 {
3136 	unsigned int chanmask;
3137 	int chan = channels ? (channels - 1) : 1;
3138 
3139 	switch (channels) {
3140 	default:
3141 	case 0:
3142 	case 2:
3143 		chanmask = 0x00;
3144 		break;
3145 	case 4:
3146 		chanmask = 0x08;
3147 		break;
3148 	case 6:
3149 		chanmask = 0x0b;
3150 		break;
3151 	case 8:
3152 		chanmask = 0x13;
3153 		break;
3154 	}
3155 
3156 	/* Set the audio infoframe channel allocation and checksum fields.  The
3157 	 * channel count is computed implicitly by the hardware. */
3158 	snd_hda_codec_write(codec, 0x1, 0,
3159 			Nv_VERB_SET_Channel_Allocation, chanmask);
3160 
3161 	snd_hda_codec_write(codec, 0x1, 0,
3162 			Nv_VERB_SET_Info_Frame_Checksum,
3163 			(0x71 - chan - chanmask));
3164 }
3165 
3166 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
3167 				   struct hda_codec *codec,
3168 				   struct snd_pcm_substream *substream)
3169 {
3170 	struct hdmi_spec *spec = codec->spec;
3171 	int i;
3172 
3173 	snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
3174 			0, AC_VERB_SET_CHANNEL_STREAMID, 0);
3175 	for (i = 0; i < 4; i++) {
3176 		/* set the stream id */
3177 		snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3178 				AC_VERB_SET_CHANNEL_STREAMID, 0);
3179 		/* set the stream format */
3180 		snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3181 				AC_VERB_SET_STREAM_FORMAT, 0);
3182 	}
3183 
3184 	/* The audio hardware sends a channel count of 0x7 (8ch) when all the
3185 	 * streams are disabled. */
3186 	nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3187 
3188 	return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3189 }
3190 
3191 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
3192 				     struct hda_codec *codec,
3193 				     unsigned int stream_tag,
3194 				     unsigned int format,
3195 				     struct snd_pcm_substream *substream)
3196 {
3197 	int chs;
3198 	unsigned int dataDCC2, channel_id;
3199 	int i;
3200 	struct hdmi_spec *spec = codec->spec;
3201 	struct hda_spdif_out *spdif;
3202 	struct hdmi_spec_per_cvt *per_cvt;
3203 
3204 	mutex_lock(&codec->spdif_mutex);
3205 	per_cvt = get_cvt(spec, 0);
3206 	spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
3207 
3208 	chs = substream->runtime->channels;
3209 
3210 	dataDCC2 = 0x2;
3211 
3212 	/* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
3213 	if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
3214 		snd_hda_codec_write(codec,
3215 				nvhdmi_master_con_nid_7x,
3216 				0,
3217 				AC_VERB_SET_DIGI_CONVERT_1,
3218 				spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3219 
3220 	/* set the stream id */
3221 	snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3222 			AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3223 
3224 	/* set the stream format */
3225 	snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3226 			AC_VERB_SET_STREAM_FORMAT, format);
3227 
3228 	/* turn on again (if needed) */
3229 	/* enable and set the channel status audio/data flag */
3230 	if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
3231 		snd_hda_codec_write(codec,
3232 				nvhdmi_master_con_nid_7x,
3233 				0,
3234 				AC_VERB_SET_DIGI_CONVERT_1,
3235 				spdif->ctls & 0xff);
3236 		snd_hda_codec_write(codec,
3237 				nvhdmi_master_con_nid_7x,
3238 				0,
3239 				AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3240 	}
3241 
3242 	for (i = 0; i < 4; i++) {
3243 		if (chs == 2)
3244 			channel_id = 0;
3245 		else
3246 			channel_id = i * 2;
3247 
3248 		/* turn off SPDIF once;
3249 		 *otherwise the IEC958 bits won't be updated
3250 		 */
3251 		if (codec->spdif_status_reset &&
3252 		(spdif->ctls & AC_DIG1_ENABLE))
3253 			snd_hda_codec_write(codec,
3254 				nvhdmi_con_nids_7x[i],
3255 				0,
3256 				AC_VERB_SET_DIGI_CONVERT_1,
3257 				spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3258 		/* set the stream id */
3259 		snd_hda_codec_write(codec,
3260 				nvhdmi_con_nids_7x[i],
3261 				0,
3262 				AC_VERB_SET_CHANNEL_STREAMID,
3263 				(stream_tag << 4) | channel_id);
3264 		/* set the stream format */
3265 		snd_hda_codec_write(codec,
3266 				nvhdmi_con_nids_7x[i],
3267 				0,
3268 				AC_VERB_SET_STREAM_FORMAT,
3269 				format);
3270 		/* turn on again (if needed) */
3271 		/* enable and set the channel status audio/data flag */
3272 		if (codec->spdif_status_reset &&
3273 		(spdif->ctls & AC_DIG1_ENABLE)) {
3274 			snd_hda_codec_write(codec,
3275 					nvhdmi_con_nids_7x[i],
3276 					0,
3277 					AC_VERB_SET_DIGI_CONVERT_1,
3278 					spdif->ctls & 0xff);
3279 			snd_hda_codec_write(codec,
3280 					nvhdmi_con_nids_7x[i],
3281 					0,
3282 					AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3283 		}
3284 	}
3285 
3286 	nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3287 
3288 	mutex_unlock(&codec->spdif_mutex);
3289 	return 0;
3290 }
3291 
3292 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3293 	.substreams = 1,
3294 	.channels_min = 2,
3295 	.channels_max = 8,
3296 	.nid = nvhdmi_master_con_nid_7x,
3297 	.rates = SUPPORTED_RATES,
3298 	.maxbps = SUPPORTED_MAXBPS,
3299 	.formats = SUPPORTED_FORMATS,
3300 	.ops = {
3301 		.open = simple_playback_pcm_open,
3302 		.close = nvhdmi_8ch_7x_pcm_close,
3303 		.prepare = nvhdmi_8ch_7x_pcm_prepare
3304 	},
3305 };
3306 
3307 static int patch_nvhdmi_2ch(struct hda_codec *codec)
3308 {
3309 	struct hdmi_spec *spec;
3310 	int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3311 				    nvhdmi_master_pin_nid_7x);
3312 	if (err < 0)
3313 		return err;
3314 
3315 	codec->patch_ops.init = nvhdmi_7x_init_2ch;
3316 	/* override the PCM rates, etc, as the codec doesn't give full list */
3317 	spec = codec->spec;
3318 	spec->pcm_playback.rates = SUPPORTED_RATES;
3319 	spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3320 	spec->pcm_playback.formats = SUPPORTED_FORMATS;
3321 	return 0;
3322 }
3323 
3324 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3325 {
3326 	struct hdmi_spec *spec = codec->spec;
3327 	int err = simple_playback_build_pcms(codec);
3328 	if (!err) {
3329 		struct hda_pcm *info = get_pcm_rec(spec, 0);
3330 		info->own_chmap = true;
3331 	}
3332 	return err;
3333 }
3334 
3335 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3336 {
3337 	struct hdmi_spec *spec = codec->spec;
3338 	struct hda_pcm *info;
3339 	struct snd_pcm_chmap *chmap;
3340 	int err;
3341 
3342 	err = simple_playback_build_controls(codec);
3343 	if (err < 0)
3344 		return err;
3345 
3346 	/* add channel maps */
3347 	info = get_pcm_rec(spec, 0);
3348 	err = snd_pcm_add_chmap_ctls(info->pcm,
3349 				     SNDRV_PCM_STREAM_PLAYBACK,
3350 				     snd_pcm_alt_chmaps, 8, 0, &chmap);
3351 	if (err < 0)
3352 		return err;
3353 	switch (codec->preset->vendor_id) {
3354 	case 0x10de0002:
3355 	case 0x10de0003:
3356 	case 0x10de0005:
3357 	case 0x10de0006:
3358 		chmap->channel_mask = (1U << 2) | (1U << 8);
3359 		break;
3360 	case 0x10de0007:
3361 		chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3362 	}
3363 	return 0;
3364 }
3365 
3366 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3367 {
3368 	struct hdmi_spec *spec;
3369 	int err = patch_nvhdmi_2ch(codec);
3370 	if (err < 0)
3371 		return err;
3372 	spec = codec->spec;
3373 	spec->multiout.max_channels = 8;
3374 	spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3375 	codec->patch_ops.init = nvhdmi_7x_init_8ch;
3376 	codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3377 	codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3378 
3379 	/* Initialize the audio infoframe channel mask and checksum to something
3380 	 * valid */
3381 	nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3382 
3383 	return 0;
3384 }
3385 
3386 /*
3387  * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3388  * - 0x10de0015
3389  * - 0x10de0040
3390  */
3391 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3392 		struct hdac_cea_channel_speaker_allocation *cap, int channels)
3393 {
3394 	if (cap->ca_index == 0x00 && channels == 2)
3395 		return SNDRV_CTL_TLVT_CHMAP_FIXED;
3396 
3397 	/* If the speaker allocation matches the channel count, it is OK. */
3398 	if (cap->channels != channels)
3399 		return -1;
3400 
3401 	/* all channels are remappable freely */
3402 	return SNDRV_CTL_TLVT_CHMAP_VAR;
3403 }
3404 
3405 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3406 		int ca, int chs, unsigned char *map)
3407 {
3408 	if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3409 		return -EINVAL;
3410 
3411 	return 0;
3412 }
3413 
3414 /* map from pin NID to port; port is 0-based */
3415 /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */
3416 static int nvhdmi_pin2port(void *audio_ptr, int pin_nid)
3417 {
3418 	return pin_nid - 4;
3419 }
3420 
3421 /* reverse-map from port to pin NID: see above */
3422 static int nvhdmi_port2pin(struct hda_codec *codec, int port)
3423 {
3424 	return port + 4;
3425 }
3426 
3427 static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = {
3428 	.pin2port = nvhdmi_pin2port,
3429 	.pin_eld_notify = generic_acomp_pin_eld_notify,
3430 	.master_bind = generic_acomp_master_bind,
3431 	.master_unbind = generic_acomp_master_unbind,
3432 };
3433 
3434 static int patch_nvhdmi(struct hda_codec *codec)
3435 {
3436 	struct hdmi_spec *spec;
3437 	int err;
3438 
3439 	err = alloc_generic_hdmi(codec);
3440 	if (err < 0)
3441 		return err;
3442 	codec->dp_mst = true;
3443 
3444 	spec = codec->spec;
3445 	spec->dyn_pcm_assign = true;
3446 
3447 	err = hdmi_parse_codec(codec);
3448 	if (err < 0) {
3449 		generic_spec_free(codec);
3450 		return err;
3451 	}
3452 
3453 	generic_hdmi_init_per_pins(codec);
3454 
3455 	spec->dyn_pin_out = true;
3456 
3457 	spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3458 		nvhdmi_chmap_cea_alloc_validate_get_type;
3459 	spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3460 
3461 	codec->link_down_at_suspend = 1;
3462 
3463 	generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin);
3464 
3465 	return 0;
3466 }
3467 
3468 static int patch_nvhdmi_legacy(struct hda_codec *codec)
3469 {
3470 	struct hdmi_spec *spec;
3471 	int err;
3472 
3473 	err = patch_generic_hdmi(codec);
3474 	if (err)
3475 		return err;
3476 
3477 	spec = codec->spec;
3478 	spec->dyn_pin_out = true;
3479 
3480 	spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3481 		nvhdmi_chmap_cea_alloc_validate_get_type;
3482 	spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3483 
3484 	codec->link_down_at_suspend = 1;
3485 
3486 	return 0;
3487 }
3488 
3489 /*
3490  * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3491  * accessed using vendor-defined verbs. These registers can be used for
3492  * interoperability between the HDA and HDMI drivers.
3493  */
3494 
3495 /* Audio Function Group node */
3496 #define NVIDIA_AFG_NID 0x01
3497 
3498 /*
3499  * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3500  * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3501  * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3502  * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3503  * additional bit (at position 30) to signal the validity of the format.
3504  *
3505  * | 31      | 30    | 29  16 | 15   0 |
3506  * +---------+-------+--------+--------+
3507  * | TRIGGER | VALID | UNUSED | FORMAT |
3508  * +-----------------------------------|
3509  *
3510  * Note that for the trigger bit to take effect it needs to change value
3511  * (i.e. it needs to be toggled).
3512  */
3513 #define NVIDIA_GET_SCRATCH0		0xfa6
3514 #define NVIDIA_SET_SCRATCH0_BYTE0	0xfa7
3515 #define NVIDIA_SET_SCRATCH0_BYTE1	0xfa8
3516 #define NVIDIA_SET_SCRATCH0_BYTE2	0xfa9
3517 #define NVIDIA_SET_SCRATCH0_BYTE3	0xfaa
3518 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3519 #define NVIDIA_SCRATCH_VALID   (1 << 6)
3520 
3521 #define NVIDIA_GET_SCRATCH1		0xfab
3522 #define NVIDIA_SET_SCRATCH1_BYTE0	0xfac
3523 #define NVIDIA_SET_SCRATCH1_BYTE1	0xfad
3524 #define NVIDIA_SET_SCRATCH1_BYTE2	0xfae
3525 #define NVIDIA_SET_SCRATCH1_BYTE3	0xfaf
3526 
3527 /*
3528  * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3529  * the format is invalidated so that the HDMI codec can be disabled.
3530  */
3531 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3532 {
3533 	unsigned int value;
3534 
3535 	/* bits [31:30] contain the trigger and valid bits */
3536 	value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3537 				   NVIDIA_GET_SCRATCH0, 0);
3538 	value = (value >> 24) & 0xff;
3539 
3540 	/* bits [15:0] are used to store the HDA format */
3541 	snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3542 			    NVIDIA_SET_SCRATCH0_BYTE0,
3543 			    (format >> 0) & 0xff);
3544 	snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3545 			    NVIDIA_SET_SCRATCH0_BYTE1,
3546 			    (format >> 8) & 0xff);
3547 
3548 	/* bits [16:24] are unused */
3549 	snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3550 			    NVIDIA_SET_SCRATCH0_BYTE2, 0);
3551 
3552 	/*
3553 	 * Bit 30 signals that the data is valid and hence that HDMI audio can
3554 	 * be enabled.
3555 	 */
3556 	if (format == 0)
3557 		value &= ~NVIDIA_SCRATCH_VALID;
3558 	else
3559 		value |= NVIDIA_SCRATCH_VALID;
3560 
3561 	/*
3562 	 * Whenever the trigger bit is toggled, an interrupt is raised in the
3563 	 * HDMI codec. The HDMI driver will use that as trigger to update its
3564 	 * configuration.
3565 	 */
3566 	value ^= NVIDIA_SCRATCH_TRIGGER;
3567 
3568 	snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3569 			    NVIDIA_SET_SCRATCH0_BYTE3, value);
3570 }
3571 
3572 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3573 				  struct hda_codec *codec,
3574 				  unsigned int stream_tag,
3575 				  unsigned int format,
3576 				  struct snd_pcm_substream *substream)
3577 {
3578 	int err;
3579 
3580 	err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3581 						format, substream);
3582 	if (err < 0)
3583 		return err;
3584 
3585 	/* notify the HDMI codec of the format change */
3586 	tegra_hdmi_set_format(codec, format);
3587 
3588 	return 0;
3589 }
3590 
3591 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3592 				  struct hda_codec *codec,
3593 				  struct snd_pcm_substream *substream)
3594 {
3595 	/* invalidate the format in the HDMI codec */
3596 	tegra_hdmi_set_format(codec, 0);
3597 
3598 	return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3599 }
3600 
3601 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3602 {
3603 	struct hdmi_spec *spec = codec->spec;
3604 	unsigned int i;
3605 
3606 	for (i = 0; i < spec->num_pins; i++) {
3607 		struct hda_pcm *pcm = get_pcm_rec(spec, i);
3608 
3609 		if (pcm->pcm_type == type)
3610 			return pcm;
3611 	}
3612 
3613 	return NULL;
3614 }
3615 
3616 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3617 {
3618 	struct hda_pcm_stream *stream;
3619 	struct hda_pcm *pcm;
3620 	int err;
3621 
3622 	err = generic_hdmi_build_pcms(codec);
3623 	if (err < 0)
3624 		return err;
3625 
3626 	pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3627 	if (!pcm)
3628 		return -ENODEV;
3629 
3630 	/*
3631 	 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3632 	 * codec about format changes.
3633 	 */
3634 	stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3635 	stream->ops.prepare = tegra_hdmi_pcm_prepare;
3636 	stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3637 
3638 	return 0;
3639 }
3640 
3641 static int patch_tegra_hdmi(struct hda_codec *codec)
3642 {
3643 	int err;
3644 
3645 	err = patch_generic_hdmi(codec);
3646 	if (err)
3647 		return err;
3648 
3649 	codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3650 
3651 	return 0;
3652 }
3653 
3654 /*
3655  * ATI/AMD-specific implementations
3656  */
3657 
3658 #define is_amdhdmi_rev3_or_later(codec) \
3659 	((codec)->core.vendor_id == 0x1002aa01 && \
3660 	 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3661 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3662 
3663 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3664 #define ATI_VERB_SET_CHANNEL_ALLOCATION	0x771
3665 #define ATI_VERB_SET_DOWNMIX_INFO	0x772
3666 #define ATI_VERB_SET_MULTICHANNEL_01	0x777
3667 #define ATI_VERB_SET_MULTICHANNEL_23	0x778
3668 #define ATI_VERB_SET_MULTICHANNEL_45	0x779
3669 #define ATI_VERB_SET_MULTICHANNEL_67	0x77a
3670 #define ATI_VERB_SET_HBR_CONTROL	0x77c
3671 #define ATI_VERB_SET_MULTICHANNEL_1	0x785
3672 #define ATI_VERB_SET_MULTICHANNEL_3	0x786
3673 #define ATI_VERB_SET_MULTICHANNEL_5	0x787
3674 #define ATI_VERB_SET_MULTICHANNEL_7	0x788
3675 #define ATI_VERB_SET_MULTICHANNEL_MODE	0x789
3676 #define ATI_VERB_GET_CHANNEL_ALLOCATION	0xf71
3677 #define ATI_VERB_GET_DOWNMIX_INFO	0xf72
3678 #define ATI_VERB_GET_MULTICHANNEL_01	0xf77
3679 #define ATI_VERB_GET_MULTICHANNEL_23	0xf78
3680 #define ATI_VERB_GET_MULTICHANNEL_45	0xf79
3681 #define ATI_VERB_GET_MULTICHANNEL_67	0xf7a
3682 #define ATI_VERB_GET_HBR_CONTROL	0xf7c
3683 #define ATI_VERB_GET_MULTICHANNEL_1	0xf85
3684 #define ATI_VERB_GET_MULTICHANNEL_3	0xf86
3685 #define ATI_VERB_GET_MULTICHANNEL_5	0xf87
3686 #define ATI_VERB_GET_MULTICHANNEL_7	0xf88
3687 #define ATI_VERB_GET_MULTICHANNEL_MODE	0xf89
3688 
3689 /* AMD specific HDA cvt verbs */
3690 #define ATI_VERB_SET_RAMP_RATE		0x770
3691 #define ATI_VERB_GET_RAMP_RATE		0xf70
3692 
3693 #define ATI_OUT_ENABLE 0x1
3694 
3695 #define ATI_MULTICHANNEL_MODE_PAIRED	0
3696 #define ATI_MULTICHANNEL_MODE_SINGLE	1
3697 
3698 #define ATI_HBR_CAPABLE 0x01
3699 #define ATI_HBR_ENABLE 0x10
3700 
3701 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3702 			       int dev_id, unsigned char *buf, int *eld_size)
3703 {
3704 	WARN_ON(dev_id != 0);
3705 	/* call hda_eld.c ATI/AMD-specific function */
3706 	return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3707 				    is_amdhdmi_rev3_or_later(codec));
3708 }
3709 
3710 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec,
3711 					hda_nid_t pin_nid, int dev_id, int ca,
3712 					int active_channels, int conn_type)
3713 {
3714 	WARN_ON(dev_id != 0);
3715 	snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3716 }
3717 
3718 static int atihdmi_paired_swap_fc_lfe(int pos)
3719 {
3720 	/*
3721 	 * ATI/AMD have automatic FC/LFE swap built-in
3722 	 * when in pairwise mapping mode.
3723 	 */
3724 
3725 	switch (pos) {
3726 		/* see channel_allocations[].speakers[] */
3727 		case 2: return 3;
3728 		case 3: return 2;
3729 		default: break;
3730 	}
3731 
3732 	return pos;
3733 }
3734 
3735 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3736 			int ca, int chs, unsigned char *map)
3737 {
3738 	struct hdac_cea_channel_speaker_allocation *cap;
3739 	int i, j;
3740 
3741 	/* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3742 
3743 	cap = snd_hdac_get_ch_alloc_from_ca(ca);
3744 	for (i = 0; i < chs; ++i) {
3745 		int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3746 		bool ok = false;
3747 		bool companion_ok = false;
3748 
3749 		if (!mask)
3750 			continue;
3751 
3752 		for (j = 0 + i % 2; j < 8; j += 2) {
3753 			int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3754 			if (cap->speakers[chan_idx] == mask) {
3755 				/* channel is in a supported position */
3756 				ok = true;
3757 
3758 				if (i % 2 == 0 && i + 1 < chs) {
3759 					/* even channel, check the odd companion */
3760 					int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3761 					int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
3762 					int comp_mask_act = cap->speakers[comp_chan_idx];
3763 
3764 					if (comp_mask_req == comp_mask_act)
3765 						companion_ok = true;
3766 					else
3767 						return -EINVAL;
3768 				}
3769 				break;
3770 			}
3771 		}
3772 
3773 		if (!ok)
3774 			return -EINVAL;
3775 
3776 		if (companion_ok)
3777 			i++; /* companion channel already checked */
3778 	}
3779 
3780 	return 0;
3781 }
3782 
3783 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3784 		hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
3785 {
3786 	struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3787 	int verb;
3788 	int ati_channel_setup = 0;
3789 
3790 	if (hdmi_slot > 7)
3791 		return -EINVAL;
3792 
3793 	if (!has_amd_full_remap_support(codec)) {
3794 		hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3795 
3796 		/* In case this is an odd slot but without stream channel, do not
3797 		 * disable the slot since the corresponding even slot could have a
3798 		 * channel. In case neither have a channel, the slot pair will be
3799 		 * disabled when this function is called for the even slot. */
3800 		if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3801 			return 0;
3802 
3803 		hdmi_slot -= hdmi_slot % 2;
3804 
3805 		if (stream_channel != 0xf)
3806 			stream_channel -= stream_channel % 2;
3807 	}
3808 
3809 	verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3810 
3811 	/* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3812 
3813 	if (stream_channel != 0xf)
3814 		ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3815 
3816 	return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3817 }
3818 
3819 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3820 				hda_nid_t pin_nid, int asp_slot)
3821 {
3822 	struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3823 	bool was_odd = false;
3824 	int ati_asp_slot = asp_slot;
3825 	int verb;
3826 	int ati_channel_setup;
3827 
3828 	if (asp_slot > 7)
3829 		return -EINVAL;
3830 
3831 	if (!has_amd_full_remap_support(codec)) {
3832 		ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3833 		if (ati_asp_slot % 2 != 0) {
3834 			ati_asp_slot -= 1;
3835 			was_odd = true;
3836 		}
3837 	}
3838 
3839 	verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3840 
3841 	ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3842 
3843 	if (!(ati_channel_setup & ATI_OUT_ENABLE))
3844 		return 0xf;
3845 
3846 	return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3847 }
3848 
3849 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3850 		struct hdac_chmap *chmap,
3851 		struct hdac_cea_channel_speaker_allocation *cap,
3852 		int channels)
3853 {
3854 	int c;
3855 
3856 	/*
3857 	 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3858 	 * we need to take that into account (a single channel may take 2
3859 	 * channel slots if we need to carry a silent channel next to it).
3860 	 * On Rev3+ AMD codecs this function is not used.
3861 	 */
3862 	int chanpairs = 0;
3863 
3864 	/* We only produce even-numbered channel count TLVs */
3865 	if ((channels % 2) != 0)
3866 		return -1;
3867 
3868 	for (c = 0; c < 7; c += 2) {
3869 		if (cap->speakers[c] || cap->speakers[c+1])
3870 			chanpairs++;
3871 	}
3872 
3873 	if (chanpairs * 2 != channels)
3874 		return -1;
3875 
3876 	return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3877 }
3878 
3879 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
3880 		struct hdac_cea_channel_speaker_allocation *cap,
3881 		unsigned int *chmap, int channels)
3882 {
3883 	/* produce paired maps for pre-rev3 ATI/AMD codecs */
3884 	int count = 0;
3885 	int c;
3886 
3887 	for (c = 7; c >= 0; c--) {
3888 		int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3889 		int spk = cap->speakers[chan];
3890 		if (!spk) {
3891 			/* add N/A channel if the companion channel is occupied */
3892 			if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3893 				chmap[count++] = SNDRV_CHMAP_NA;
3894 
3895 			continue;
3896 		}
3897 
3898 		chmap[count++] = snd_hdac_spk_to_chmap(spk);
3899 	}
3900 
3901 	WARN_ON(count != channels);
3902 }
3903 
3904 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3905 				 int dev_id, bool hbr)
3906 {
3907 	int hbr_ctl, hbr_ctl_new;
3908 
3909 	WARN_ON(dev_id != 0);
3910 
3911 	hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3912 	if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3913 		if (hbr)
3914 			hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3915 		else
3916 			hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3917 
3918 		codec_dbg(codec,
3919 			  "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3920 				pin_nid,
3921 				hbr_ctl == hbr_ctl_new ? "" : "new-",
3922 				hbr_ctl_new);
3923 
3924 		if (hbr_ctl != hbr_ctl_new)
3925 			snd_hda_codec_write(codec, pin_nid, 0,
3926 						ATI_VERB_SET_HBR_CONTROL,
3927 						hbr_ctl_new);
3928 
3929 	} else if (hbr)
3930 		return -EINVAL;
3931 
3932 	return 0;
3933 }
3934 
3935 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3936 				hda_nid_t pin_nid, int dev_id,
3937 				u32 stream_tag, int format)
3938 {
3939 	if (is_amdhdmi_rev3_or_later(codec)) {
3940 		int ramp_rate = 180; /* default as per AMD spec */
3941 		/* disable ramp-up/down for non-pcm as per AMD spec */
3942 		if (format & AC_FMT_TYPE_NON_PCM)
3943 			ramp_rate = 0;
3944 
3945 		snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3946 	}
3947 
3948 	return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
3949 				 stream_tag, format);
3950 }
3951 
3952 
3953 static int atihdmi_init(struct hda_codec *codec)
3954 {
3955 	struct hdmi_spec *spec = codec->spec;
3956 	int pin_idx, err;
3957 
3958 	err = generic_hdmi_init(codec);
3959 
3960 	if (err)
3961 		return err;
3962 
3963 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3964 		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3965 
3966 		/* make sure downmix information in infoframe is zero */
3967 		snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3968 
3969 		/* enable channel-wise remap mode if supported */
3970 		if (has_amd_full_remap_support(codec))
3971 			snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3972 					    ATI_VERB_SET_MULTICHANNEL_MODE,
3973 					    ATI_MULTICHANNEL_MODE_SINGLE);
3974 	}
3975 	codec->auto_runtime_pm = 1;
3976 
3977 	return 0;
3978 }
3979 
3980 /* map from pin NID to port; port is 0-based */
3981 /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */
3982 static int atihdmi_pin2port(void *audio_ptr, int pin_nid)
3983 {
3984 	return pin_nid / 2 - 1;
3985 }
3986 
3987 /* reverse-map from port to pin NID: see above */
3988 static int atihdmi_port2pin(struct hda_codec *codec, int port)
3989 {
3990 	return port * 2 + 3;
3991 }
3992 
3993 static const struct drm_audio_component_audio_ops atihdmi_audio_ops = {
3994 	.pin2port = atihdmi_pin2port,
3995 	.pin_eld_notify = generic_acomp_pin_eld_notify,
3996 	.master_bind = generic_acomp_master_bind,
3997 	.master_unbind = generic_acomp_master_unbind,
3998 };
3999 
4000 static int patch_atihdmi(struct hda_codec *codec)
4001 {
4002 	struct hdmi_spec *spec;
4003 	struct hdmi_spec_per_cvt *per_cvt;
4004 	int err, cvt_idx;
4005 
4006 	err = patch_generic_hdmi(codec);
4007 
4008 	if (err)
4009 		return err;
4010 
4011 	codec->patch_ops.init = atihdmi_init;
4012 
4013 	spec = codec->spec;
4014 
4015 	spec->ops.pin_get_eld = atihdmi_pin_get_eld;
4016 	spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
4017 	spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
4018 	spec->ops.setup_stream = atihdmi_setup_stream;
4019 
4020 	spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
4021 	spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
4022 
4023 	if (!has_amd_full_remap_support(codec)) {
4024 		/* override to ATI/AMD-specific versions with pairwise mapping */
4025 		spec->chmap.ops.chmap_cea_alloc_validate_get_type =
4026 			atihdmi_paired_chmap_cea_alloc_validate_get_type;
4027 		spec->chmap.ops.cea_alloc_to_tlv_chmap =
4028 				atihdmi_paired_cea_alloc_to_tlv_chmap;
4029 		spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
4030 	}
4031 
4032 	/* ATI/AMD converters do not advertise all of their capabilities */
4033 	for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
4034 		per_cvt = get_cvt(spec, cvt_idx);
4035 		per_cvt->channels_max = max(per_cvt->channels_max, 8u);
4036 		per_cvt->rates |= SUPPORTED_RATES;
4037 		per_cvt->formats |= SUPPORTED_FORMATS;
4038 		per_cvt->maxbps = max(per_cvt->maxbps, 24u);
4039 	}
4040 
4041 	spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
4042 
4043 	/* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing
4044 	 * the link-down as is.  Tell the core to allow it.
4045 	 */
4046 	codec->link_down_at_suspend = 1;
4047 
4048 	generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin);
4049 
4050 	return 0;
4051 }
4052 
4053 /* VIA HDMI Implementation */
4054 #define VIAHDMI_CVT_NID	0x02	/* audio converter1 */
4055 #define VIAHDMI_PIN_NID	0x03	/* HDMI output pin1 */
4056 
4057 static int patch_via_hdmi(struct hda_codec *codec)
4058 {
4059 	return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
4060 }
4061 
4062 /*
4063  * patch entries
4064  */
4065 static const struct hda_device_id snd_hda_id_hdmi[] = {
4066 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI",	patch_atihdmi),
4067 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI",	patch_atihdmi),
4068 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI",	patch_atihdmi),
4069 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI",	patch_atihdmi),
4070 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI",	patch_generic_hdmi),
4071 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI",	patch_generic_hdmi),
4072 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI",	patch_generic_hdmi),
4073 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI",	patch_nvhdmi_2ch),
4074 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI",	patch_nvhdmi_8ch_7x),
4075 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI",	patch_nvhdmi_8ch_7x),
4076 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI",	patch_nvhdmi_8ch_7x),
4077 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI",	patch_nvhdmi_8ch_7x),
4078 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI",	patch_nvhdmi_8ch_7x),
4079 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI",	patch_nvhdmi_8ch_7x),
4080 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP",	patch_nvhdmi_legacy),
4081 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP",	patch_nvhdmi_legacy),
4082 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP",	patch_nvhdmi_legacy),
4083 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP",	patch_nvhdmi_legacy),
4084 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI",	patch_nvhdmi_legacy),
4085 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP",	patch_nvhdmi_legacy),
4086 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP",	patch_nvhdmi_legacy),
4087 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP",	patch_nvhdmi_legacy),
4088 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP",	patch_nvhdmi_legacy),
4089 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP",	patch_nvhdmi_legacy),
4090 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP",	patch_nvhdmi_legacy),
4091 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP",	patch_nvhdmi_legacy),
4092 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP",	patch_nvhdmi_legacy),
4093 /* 17 is known to be absent */
4094 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP",	patch_nvhdmi_legacy),
4095 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP",	patch_nvhdmi_legacy),
4096 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP",	patch_nvhdmi_legacy),
4097 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP",	patch_nvhdmi_legacy),
4098 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP",	patch_nvhdmi_legacy),
4099 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI",	patch_tegra_hdmi),
4100 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI",	patch_tegra_hdmi),
4101 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI",	patch_tegra_hdmi),
4102 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP",	patch_tegra_hdmi),
4103 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi),
4104 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),
4105 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi),
4106 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi),
4107 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP",	patch_nvhdmi),
4108 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP",	patch_nvhdmi),
4109 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP",	patch_nvhdmi),
4110 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP",	patch_nvhdmi),
4111 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP",	patch_nvhdmi),
4112 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP",	patch_nvhdmi),
4113 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP",	patch_nvhdmi),
4114 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP",	patch_nvhdmi),
4115 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP",	patch_nvhdmi),
4116 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP",	patch_nvhdmi),
4117 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP",	patch_nvhdmi),
4118 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP",	patch_nvhdmi),
4119 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI",	patch_nvhdmi_2ch),
4120 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP",	patch_nvhdmi),
4121 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP",	patch_nvhdmi),
4122 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP",	patch_nvhdmi),
4123 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP",	patch_nvhdmi),
4124 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP",	patch_nvhdmi),
4125 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP",	patch_nvhdmi),
4126 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP",	patch_nvhdmi),
4127 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP",	patch_nvhdmi),
4128 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP",	patch_nvhdmi),
4129 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP",	patch_nvhdmi),
4130 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP",	patch_nvhdmi),
4131 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP",	patch_nvhdmi),
4132 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP",	patch_nvhdmi),
4133 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP",	patch_nvhdmi),
4134 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP",	patch_nvhdmi),
4135 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP",	patch_nvhdmi),
4136 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP",	patch_nvhdmi),
4137 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP",	patch_nvhdmi),
4138 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP",	patch_nvhdmi),
4139 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP",	patch_nvhdmi),
4140 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP",	patch_nvhdmi),
4141 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP",	patch_nvhdmi),
4142 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP",	patch_nvhdmi),
4143 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP",	patch_nvhdmi),
4144 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI",	patch_nvhdmi_2ch),
4145 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI",	patch_nvhdmi_2ch),
4146 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP",	patch_via_hdmi),
4147 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP",	patch_via_hdmi),
4148 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP",	patch_generic_hdmi),
4149 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP",	patch_generic_hdmi),
4150 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI",	patch_i915_cpt_hdmi),
4151 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI",	patch_i915_glk_hdmi),
4152 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI",	patch_generic_hdmi),
4153 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI",	patch_generic_hdmi),
4154 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI",	patch_generic_hdmi),
4155 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI",	patch_i915_cpt_hdmi),
4156 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI",	patch_i915_cpt_hdmi),
4157 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
4158 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI",	patch_i915_hsw_hdmi),
4159 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI",	patch_i915_hsw_hdmi),
4160 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI",	patch_i915_hsw_hdmi),
4161 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI",	patch_i915_hsw_hdmi),
4162 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI",	patch_i915_hsw_hdmi),
4163 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI",	patch_i915_glk_hdmi),
4164 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI",	patch_i915_glk_hdmi),
4165 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI",	patch_i915_icl_hdmi),
4166 HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI",	patch_i915_tgl_hdmi),
4167 HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI",	patch_i915_icl_hdmi),
4168 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI",	patch_generic_hdmi),
4169 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI",	patch_i915_byt_hdmi),
4170 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI",	patch_i915_byt_hdmi),
4171 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI",	patch_generic_hdmi),
4172 /* special ID for generic HDMI */
4173 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
4174 {} /* terminator */
4175 };
4176 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
4177 
4178 MODULE_LICENSE("GPL");
4179 MODULE_DESCRIPTION("HDMI HD-audio codec");
4180 MODULE_ALIAS("snd-hda-codec-intelhdmi");
4181 MODULE_ALIAS("snd-hda-codec-nvhdmi");
4182 MODULE_ALIAS("snd-hda-codec-atihdmi");
4183 
4184 static struct hda_codec_driver hdmi_driver = {
4185 	.id = snd_hda_id_hdmi,
4186 };
4187 
4188 module_hda_codec_driver(hdmi_driver);
4189