1 /* 2 * 3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs 4 * 5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. 6 * Copyright (c) 2006 ATI Technologies Inc. 7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved. 8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com> 9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> 10 * 11 * Authors: 12 * Wu Fengguang <wfg@linux.intel.com> 13 * 14 * Maintained by: 15 * Wu Fengguang <wfg@linux.intel.com> 16 * 17 * This program is free software; you can redistribute it and/or modify it 18 * under the terms of the GNU General Public License as published by the Free 19 * Software Foundation; either version 2 of the License, or (at your option) 20 * any later version. 21 * 22 * This program is distributed in the hope that it will be useful, but 23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 25 * for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software Foundation, 29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 30 */ 31 32 #include <linux/init.h> 33 #include <linux/delay.h> 34 #include <linux/slab.h> 35 #include <linux/module.h> 36 #include <sound/core.h> 37 #include <sound/jack.h> 38 #include <sound/asoundef.h> 39 #include <sound/tlv.h> 40 #include "hda_codec.h" 41 #include "hda_local.h" 42 #include "hda_jack.h" 43 44 static bool static_hdmi_pcm; 45 module_param(static_hdmi_pcm, bool, 0644); 46 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); 47 48 #define is_haswell(codec) ((codec)->vendor_id == 0x80862807) 49 #define is_broadwell(codec) ((codec)->vendor_id == 0x80862808) 50 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec)) 51 52 #define is_valleyview(codec) ((codec)->vendor_id == 0x80862882) 53 54 struct hdmi_spec_per_cvt { 55 hda_nid_t cvt_nid; 56 int assigned; 57 unsigned int channels_min; 58 unsigned int channels_max; 59 u32 rates; 60 u64 formats; 61 unsigned int maxbps; 62 }; 63 64 /* max. connections to a widget */ 65 #define HDA_MAX_CONNECTIONS 32 66 67 struct hdmi_spec_per_pin { 68 hda_nid_t pin_nid; 69 int num_mux_nids; 70 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; 71 int mux_idx; 72 hda_nid_t cvt_nid; 73 74 struct hda_codec *codec; 75 struct hdmi_eld sink_eld; 76 struct mutex lock; 77 struct delayed_work work; 78 struct snd_kcontrol *eld_ctl; 79 int repoll_count; 80 bool setup; /* the stream has been set up by prepare callback */ 81 int channels; /* current number of channels */ 82 bool non_pcm; 83 bool chmap_set; /* channel-map override by ALSA API? */ 84 unsigned char chmap[8]; /* ALSA API channel-map */ 85 char pcm_name[8]; /* filled in build_pcm callbacks */ 86 #ifdef CONFIG_PROC_FS 87 struct snd_info_entry *proc_entry; 88 #endif 89 }; 90 91 struct cea_channel_speaker_allocation; 92 93 /* operations used by generic code that can be overridden by patches */ 94 struct hdmi_ops { 95 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, 96 unsigned char *buf, int *eld_size); 97 98 /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */ 99 int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid, 100 int asp_slot); 101 int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid, 102 int asp_slot, int channel); 103 104 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, 105 int ca, int active_channels, int conn_type); 106 107 /* enable/disable HBR (HD passthrough) */ 108 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr); 109 110 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, 111 hda_nid_t pin_nid, u32 stream_tag, int format); 112 113 /* Helpers for producing the channel map TLVs. These can be overridden 114 * for devices that have non-standard mapping requirements. */ 115 int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap, 116 int channels); 117 void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap, 118 unsigned int *chmap, int channels); 119 120 /* check that the user-given chmap is supported */ 121 int (*chmap_validate)(int ca, int channels, unsigned char *chmap); 122 }; 123 124 struct hdmi_spec { 125 int num_cvts; 126 struct snd_array cvts; /* struct hdmi_spec_per_cvt */ 127 hda_nid_t cvt_nids[4]; /* only for haswell fix */ 128 129 int num_pins; 130 struct snd_array pins; /* struct hdmi_spec_per_pin */ 131 struct snd_array pcm_rec; /* struct hda_pcm */ 132 unsigned int channels_max; /* max over all cvts */ 133 134 struct hdmi_eld temp_eld; 135 struct hdmi_ops ops; 136 137 bool dyn_pin_out; 138 139 /* 140 * Non-generic VIA/NVIDIA specific 141 */ 142 struct hda_multi_out multiout; 143 struct hda_pcm_stream pcm_playback; 144 }; 145 146 147 struct hdmi_audio_infoframe { 148 u8 type; /* 0x84 */ 149 u8 ver; /* 0x01 */ 150 u8 len; /* 0x0a */ 151 152 u8 checksum; 153 154 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ 155 u8 SS01_SF24; 156 u8 CXT04; 157 u8 CA; 158 u8 LFEPBL01_LSV36_DM_INH7; 159 }; 160 161 struct dp_audio_infoframe { 162 u8 type; /* 0x84 */ 163 u8 len; /* 0x1b */ 164 u8 ver; /* 0x11 << 2 */ 165 166 u8 CC02_CT47; /* match with HDMI infoframe from this on */ 167 u8 SS01_SF24; 168 u8 CXT04; 169 u8 CA; 170 u8 LFEPBL01_LSV36_DM_INH7; 171 }; 172 173 union audio_infoframe { 174 struct hdmi_audio_infoframe hdmi; 175 struct dp_audio_infoframe dp; 176 u8 bytes[0]; 177 }; 178 179 /* 180 * CEA speaker placement: 181 * 182 * FLH FCH FRH 183 * FLW FL FLC FC FRC FR FRW 184 * 185 * LFE 186 * TC 187 * 188 * RL RLC RC RRC RR 189 * 190 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to 191 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC. 192 */ 193 enum cea_speaker_placement { 194 FL = (1 << 0), /* Front Left */ 195 FC = (1 << 1), /* Front Center */ 196 FR = (1 << 2), /* Front Right */ 197 FLC = (1 << 3), /* Front Left Center */ 198 FRC = (1 << 4), /* Front Right Center */ 199 RL = (1 << 5), /* Rear Left */ 200 RC = (1 << 6), /* Rear Center */ 201 RR = (1 << 7), /* Rear Right */ 202 RLC = (1 << 8), /* Rear Left Center */ 203 RRC = (1 << 9), /* Rear Right Center */ 204 LFE = (1 << 10), /* Low Frequency Effect */ 205 FLW = (1 << 11), /* Front Left Wide */ 206 FRW = (1 << 12), /* Front Right Wide */ 207 FLH = (1 << 13), /* Front Left High */ 208 FCH = (1 << 14), /* Front Center High */ 209 FRH = (1 << 15), /* Front Right High */ 210 TC = (1 << 16), /* Top Center */ 211 }; 212 213 /* 214 * ELD SA bits in the CEA Speaker Allocation data block 215 */ 216 static int eld_speaker_allocation_bits[] = { 217 [0] = FL | FR, 218 [1] = LFE, 219 [2] = FC, 220 [3] = RL | RR, 221 [4] = RC, 222 [5] = FLC | FRC, 223 [6] = RLC | RRC, 224 /* the following are not defined in ELD yet */ 225 [7] = FLW | FRW, 226 [8] = FLH | FRH, 227 [9] = TC, 228 [10] = FCH, 229 }; 230 231 struct cea_channel_speaker_allocation { 232 int ca_index; 233 int speakers[8]; 234 235 /* derived values, just for convenience */ 236 int channels; 237 int spk_mask; 238 }; 239 240 /* 241 * ALSA sequence is: 242 * 243 * surround40 surround41 surround50 surround51 surround71 244 * ch0 front left = = = = 245 * ch1 front right = = = = 246 * ch2 rear left = = = = 247 * ch3 rear right = = = = 248 * ch4 LFE center center center 249 * ch5 LFE LFE 250 * ch6 side left 251 * ch7 side right 252 * 253 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR} 254 */ 255 static int hdmi_channel_mapping[0x32][8] = { 256 /* stereo */ 257 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }, 258 /* 2.1 */ 259 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }, 260 /* Dolby Surround */ 261 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 }, 262 /* surround40 */ 263 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 }, 264 /* 4ch */ 265 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 }, 266 /* surround41 */ 267 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 }, 268 /* surround50 */ 269 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 }, 270 /* surround51 */ 271 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 }, 272 /* 7.1 */ 273 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 }, 274 }; 275 276 /* 277 * This is an ordered list! 278 * 279 * The preceding ones have better chances to be selected by 280 * hdmi_channel_allocation(). 281 */ 282 static struct cea_channel_speaker_allocation channel_allocations[] = { 283 /* channel: 7 6 5 4 3 2 1 0 */ 284 { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } }, 285 /* 2.1 */ 286 { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } }, 287 /* Dolby Surround */ 288 { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } }, 289 /* surround40 */ 290 { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } }, 291 /* surround41 */ 292 { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } }, 293 /* surround50 */ 294 { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } }, 295 /* surround51 */ 296 { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } }, 297 /* 6.1 */ 298 { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } }, 299 /* surround71 */ 300 { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } }, 301 302 { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } }, 303 { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } }, 304 { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } }, 305 { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } }, 306 { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } }, 307 { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } }, 308 { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } }, 309 { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } }, 310 { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } }, 311 { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } }, 312 { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } }, 313 { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } }, 314 { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } }, 315 { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } }, 316 { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } }, 317 { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } }, 318 { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } }, 319 { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } }, 320 { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } }, 321 { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } }, 322 { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } }, 323 { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } }, 324 { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } }, 325 { .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } }, 326 { .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } }, 327 { .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } }, 328 { .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } }, 329 { .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } }, 330 { .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } }, 331 { .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } }, 332 { .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } }, 333 { .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } }, 334 { .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } }, 335 { .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } }, 336 { .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } }, 337 { .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } }, 338 { .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } }, 339 { .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } }, 340 { .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } }, 341 { .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } }, 342 { .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } }, 343 }; 344 345 346 /* 347 * HDMI routines 348 */ 349 350 #define get_pin(spec, idx) \ 351 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) 352 #define get_cvt(spec, idx) \ 353 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) 354 #define get_pcm_rec(spec, idx) \ 355 ((struct hda_pcm *)snd_array_elem(&spec->pcm_rec, idx)) 356 357 static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid) 358 { 359 struct hdmi_spec *spec = codec->spec; 360 int pin_idx; 361 362 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) 363 if (get_pin(spec, pin_idx)->pin_nid == pin_nid) 364 return pin_idx; 365 366 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid); 367 return -EINVAL; 368 } 369 370 static int hinfo_to_pin_index(struct hda_codec *codec, 371 struct hda_pcm_stream *hinfo) 372 { 373 struct hdmi_spec *spec = codec->spec; 374 int pin_idx; 375 376 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) 377 if (get_pcm_rec(spec, pin_idx)->stream == hinfo) 378 return pin_idx; 379 380 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo); 381 return -EINVAL; 382 } 383 384 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) 385 { 386 struct hdmi_spec *spec = codec->spec; 387 int cvt_idx; 388 389 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) 390 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) 391 return cvt_idx; 392 393 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid); 394 return -EINVAL; 395 } 396 397 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, 398 struct snd_ctl_elem_info *uinfo) 399 { 400 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 401 struct hdmi_spec *spec = codec->spec; 402 struct hdmi_spec_per_pin *per_pin; 403 struct hdmi_eld *eld; 404 int pin_idx; 405 406 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 407 408 pin_idx = kcontrol->private_value; 409 per_pin = get_pin(spec, pin_idx); 410 eld = &per_pin->sink_eld; 411 412 mutex_lock(&per_pin->lock); 413 uinfo->count = eld->eld_valid ? eld->eld_size : 0; 414 mutex_unlock(&per_pin->lock); 415 416 return 0; 417 } 418 419 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, 420 struct snd_ctl_elem_value *ucontrol) 421 { 422 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 423 struct hdmi_spec *spec = codec->spec; 424 struct hdmi_spec_per_pin *per_pin; 425 struct hdmi_eld *eld; 426 int pin_idx; 427 428 pin_idx = kcontrol->private_value; 429 per_pin = get_pin(spec, pin_idx); 430 eld = &per_pin->sink_eld; 431 432 mutex_lock(&per_pin->lock); 433 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) { 434 mutex_unlock(&per_pin->lock); 435 snd_BUG(); 436 return -EINVAL; 437 } 438 439 memset(ucontrol->value.bytes.data, 0, 440 ARRAY_SIZE(ucontrol->value.bytes.data)); 441 if (eld->eld_valid) 442 memcpy(ucontrol->value.bytes.data, eld->eld_buffer, 443 eld->eld_size); 444 mutex_unlock(&per_pin->lock); 445 446 return 0; 447 } 448 449 static struct snd_kcontrol_new eld_bytes_ctl = { 450 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, 451 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 452 .name = "ELD", 453 .info = hdmi_eld_ctl_info, 454 .get = hdmi_eld_ctl_get, 455 }; 456 457 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx, 458 int device) 459 { 460 struct snd_kcontrol *kctl; 461 struct hdmi_spec *spec = codec->spec; 462 int err; 463 464 kctl = snd_ctl_new1(&eld_bytes_ctl, codec); 465 if (!kctl) 466 return -ENOMEM; 467 kctl->private_value = pin_idx; 468 kctl->id.device = device; 469 470 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl); 471 if (err < 0) 472 return err; 473 474 get_pin(spec, pin_idx)->eld_ctl = kctl; 475 return 0; 476 } 477 478 #ifdef BE_PARANOID 479 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 480 int *packet_index, int *byte_index) 481 { 482 int val; 483 484 val = snd_hda_codec_read(codec, pin_nid, 0, 485 AC_VERB_GET_HDMI_DIP_INDEX, 0); 486 487 *packet_index = val >> 5; 488 *byte_index = val & 0x1f; 489 } 490 #endif 491 492 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 493 int packet_index, int byte_index) 494 { 495 int val; 496 497 val = (packet_index << 5) | (byte_index & 0x1f); 498 499 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); 500 } 501 502 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, 503 unsigned char val) 504 { 505 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); 506 } 507 508 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) 509 { 510 struct hdmi_spec *spec = codec->spec; 511 int pin_out; 512 513 /* Unmute */ 514 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 515 snd_hda_codec_write(codec, pin_nid, 0, 516 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); 517 518 if (spec->dyn_pin_out) 519 /* Disable pin out until stream is active */ 520 pin_out = 0; 521 else 522 /* Enable pin out: some machines with GM965 gets broken output 523 * when the pin is disabled or changed while using with HDMI 524 */ 525 pin_out = PIN_OUT; 526 527 snd_hda_codec_write(codec, pin_nid, 0, 528 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); 529 } 530 531 static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid) 532 { 533 return 1 + snd_hda_codec_read(codec, cvt_nid, 0, 534 AC_VERB_GET_CVT_CHAN_COUNT, 0); 535 } 536 537 static void hdmi_set_channel_count(struct hda_codec *codec, 538 hda_nid_t cvt_nid, int chs) 539 { 540 if (chs != hdmi_get_channel_count(codec, cvt_nid)) 541 snd_hda_codec_write(codec, cvt_nid, 0, 542 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1); 543 } 544 545 /* 546 * ELD proc files 547 */ 548 549 #ifdef CONFIG_PROC_FS 550 static void print_eld_info(struct snd_info_entry *entry, 551 struct snd_info_buffer *buffer) 552 { 553 struct hdmi_spec_per_pin *per_pin = entry->private_data; 554 555 mutex_lock(&per_pin->lock); 556 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer); 557 mutex_unlock(&per_pin->lock); 558 } 559 560 static void write_eld_info(struct snd_info_entry *entry, 561 struct snd_info_buffer *buffer) 562 { 563 struct hdmi_spec_per_pin *per_pin = entry->private_data; 564 565 mutex_lock(&per_pin->lock); 566 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); 567 mutex_unlock(&per_pin->lock); 568 } 569 570 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) 571 { 572 char name[32]; 573 struct hda_codec *codec = per_pin->codec; 574 struct snd_info_entry *entry; 575 int err; 576 577 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); 578 err = snd_card_proc_new(codec->bus->card, name, &entry); 579 if (err < 0) 580 return err; 581 582 snd_info_set_text_ops(entry, per_pin, print_eld_info); 583 entry->c.text.write = write_eld_info; 584 entry->mode |= S_IWUSR; 585 per_pin->proc_entry = entry; 586 587 return 0; 588 } 589 590 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 591 { 592 if (!per_pin->codec->bus->shutdown && per_pin->proc_entry) { 593 snd_device_free(per_pin->codec->bus->card, per_pin->proc_entry); 594 per_pin->proc_entry = NULL; 595 } 596 } 597 #else 598 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, 599 int index) 600 { 601 return 0; 602 } 603 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 604 { 605 } 606 #endif 607 608 /* 609 * Channel mapping routines 610 */ 611 612 /* 613 * Compute derived values in channel_allocations[]. 614 */ 615 static void init_channel_allocations(void) 616 { 617 int i, j; 618 struct cea_channel_speaker_allocation *p; 619 620 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 621 p = channel_allocations + i; 622 p->channels = 0; 623 p->spk_mask = 0; 624 for (j = 0; j < ARRAY_SIZE(p->speakers); j++) 625 if (p->speakers[j]) { 626 p->channels++; 627 p->spk_mask |= p->speakers[j]; 628 } 629 } 630 } 631 632 static int get_channel_allocation_order(int ca) 633 { 634 int i; 635 636 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 637 if (channel_allocations[i].ca_index == ca) 638 break; 639 } 640 return i; 641 } 642 643 /* 644 * The transformation takes two steps: 645 * 646 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask 647 * spk_mask => (channel_allocations[]) => ai->CA 648 * 649 * TODO: it could select the wrong CA from multiple candidates. 650 */ 651 static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels) 652 { 653 int i; 654 int ca = 0; 655 int spk_mask = 0; 656 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE]; 657 658 /* 659 * CA defaults to 0 for basic stereo audio 660 */ 661 if (channels <= 2) 662 return 0; 663 664 /* 665 * expand ELD's speaker allocation mask 666 * 667 * ELD tells the speaker mask in a compact(paired) form, 668 * expand ELD's notions to match the ones used by Audio InfoFrame. 669 */ 670 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) { 671 if (eld->info.spk_alloc & (1 << i)) 672 spk_mask |= eld_speaker_allocation_bits[i]; 673 } 674 675 /* search for the first working match in the CA table */ 676 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 677 if (channels == channel_allocations[i].channels && 678 (spk_mask & channel_allocations[i].spk_mask) == 679 channel_allocations[i].spk_mask) { 680 ca = channel_allocations[i].ca_index; 681 break; 682 } 683 } 684 685 if (!ca) { 686 /* if there was no match, select the regular ALSA channel 687 * allocation with the matching number of channels */ 688 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 689 if (channels == channel_allocations[i].channels) { 690 ca = channel_allocations[i].ca_index; 691 break; 692 } 693 } 694 } 695 696 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf)); 697 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n", 698 ca, channels, buf); 699 700 return ca; 701 } 702 703 static void hdmi_debug_channel_mapping(struct hda_codec *codec, 704 hda_nid_t pin_nid) 705 { 706 #ifdef CONFIG_SND_DEBUG_VERBOSE 707 struct hdmi_spec *spec = codec->spec; 708 int i; 709 int channel; 710 711 for (i = 0; i < 8; i++) { 712 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i); 713 codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n", 714 channel, i); 715 } 716 #endif 717 } 718 719 static void hdmi_std_setup_channel_mapping(struct hda_codec *codec, 720 hda_nid_t pin_nid, 721 bool non_pcm, 722 int ca) 723 { 724 struct hdmi_spec *spec = codec->spec; 725 struct cea_channel_speaker_allocation *ch_alloc; 726 int i; 727 int err; 728 int order; 729 int non_pcm_mapping[8]; 730 731 order = get_channel_allocation_order(ca); 732 ch_alloc = &channel_allocations[order]; 733 734 if (hdmi_channel_mapping[ca][1] == 0) { 735 int hdmi_slot = 0; 736 /* fill actual channel mappings in ALSA channel (i) order */ 737 for (i = 0; i < ch_alloc->channels; i++) { 738 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8)) 739 hdmi_slot++; /* skip zero slots */ 740 741 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++; 742 } 743 /* fill the rest of the slots with ALSA channel 0xf */ 744 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) 745 if (!ch_alloc->speakers[7 - hdmi_slot]) 746 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot; 747 } 748 749 if (non_pcm) { 750 for (i = 0; i < ch_alloc->channels; i++) 751 non_pcm_mapping[i] = (i << 4) | i; 752 for (; i < 8; i++) 753 non_pcm_mapping[i] = (0xf << 4) | i; 754 } 755 756 for (i = 0; i < 8; i++) { 757 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i]; 758 int hdmi_slot = slotsetup & 0x0f; 759 int channel = (slotsetup & 0xf0) >> 4; 760 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel); 761 if (err) { 762 codec_dbg(codec, "HDMI: channel mapping failed\n"); 763 break; 764 } 765 } 766 } 767 768 struct channel_map_table { 769 unsigned char map; /* ALSA API channel map position */ 770 int spk_mask; /* speaker position bit mask */ 771 }; 772 773 static struct channel_map_table map_tables[] = { 774 { SNDRV_CHMAP_FL, FL }, 775 { SNDRV_CHMAP_FR, FR }, 776 { SNDRV_CHMAP_RL, RL }, 777 { SNDRV_CHMAP_RR, RR }, 778 { SNDRV_CHMAP_LFE, LFE }, 779 { SNDRV_CHMAP_FC, FC }, 780 { SNDRV_CHMAP_RLC, RLC }, 781 { SNDRV_CHMAP_RRC, RRC }, 782 { SNDRV_CHMAP_RC, RC }, 783 { SNDRV_CHMAP_FLC, FLC }, 784 { SNDRV_CHMAP_FRC, FRC }, 785 { SNDRV_CHMAP_TFL, FLH }, 786 { SNDRV_CHMAP_TFR, FRH }, 787 { SNDRV_CHMAP_FLW, FLW }, 788 { SNDRV_CHMAP_FRW, FRW }, 789 { SNDRV_CHMAP_TC, TC }, 790 { SNDRV_CHMAP_TFC, FCH }, 791 {} /* terminator */ 792 }; 793 794 /* from ALSA API channel position to speaker bit mask */ 795 static int to_spk_mask(unsigned char c) 796 { 797 struct channel_map_table *t = map_tables; 798 for (; t->map; t++) { 799 if (t->map == c) 800 return t->spk_mask; 801 } 802 return 0; 803 } 804 805 /* from ALSA API channel position to CEA slot */ 806 static int to_cea_slot(int ordered_ca, unsigned char pos) 807 { 808 int mask = to_spk_mask(pos); 809 int i; 810 811 if (mask) { 812 for (i = 0; i < 8; i++) { 813 if (channel_allocations[ordered_ca].speakers[7 - i] == mask) 814 return i; 815 } 816 } 817 818 return -1; 819 } 820 821 /* from speaker bit mask to ALSA API channel position */ 822 static int spk_to_chmap(int spk) 823 { 824 struct channel_map_table *t = map_tables; 825 for (; t->map; t++) { 826 if (t->spk_mask == spk) 827 return t->map; 828 } 829 return 0; 830 } 831 832 /* from CEA slot to ALSA API channel position */ 833 static int from_cea_slot(int ordered_ca, unsigned char slot) 834 { 835 int mask = channel_allocations[ordered_ca].speakers[7 - slot]; 836 837 return spk_to_chmap(mask); 838 } 839 840 /* get the CA index corresponding to the given ALSA API channel map */ 841 static int hdmi_manual_channel_allocation(int chs, unsigned char *map) 842 { 843 int i, spks = 0, spk_mask = 0; 844 845 for (i = 0; i < chs; i++) { 846 int mask = to_spk_mask(map[i]); 847 if (mask) { 848 spk_mask |= mask; 849 spks++; 850 } 851 } 852 853 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 854 if ((chs == channel_allocations[i].channels || 855 spks == channel_allocations[i].channels) && 856 (spk_mask & channel_allocations[i].spk_mask) == 857 channel_allocations[i].spk_mask) 858 return channel_allocations[i].ca_index; 859 } 860 return -1; 861 } 862 863 /* set up the channel slots for the given ALSA API channel map */ 864 static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec, 865 hda_nid_t pin_nid, 866 int chs, unsigned char *map, 867 int ca) 868 { 869 struct hdmi_spec *spec = codec->spec; 870 int ordered_ca = get_channel_allocation_order(ca); 871 int alsa_pos, hdmi_slot; 872 int assignments[8] = {[0 ... 7] = 0xf}; 873 874 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) { 875 876 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]); 877 878 if (hdmi_slot < 0) 879 continue; /* unassigned channel */ 880 881 assignments[hdmi_slot] = alsa_pos; 882 } 883 884 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) { 885 int err; 886 887 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, 888 assignments[hdmi_slot]); 889 if (err) 890 return -EINVAL; 891 } 892 return 0; 893 } 894 895 /* store ALSA API channel map from the current default map */ 896 static void hdmi_setup_fake_chmap(unsigned char *map, int ca) 897 { 898 int i; 899 int ordered_ca = get_channel_allocation_order(ca); 900 for (i = 0; i < 8; i++) { 901 if (i < channel_allocations[ordered_ca].channels) 902 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f); 903 else 904 map[i] = 0; 905 } 906 } 907 908 static void hdmi_setup_channel_mapping(struct hda_codec *codec, 909 hda_nid_t pin_nid, bool non_pcm, int ca, 910 int channels, unsigned char *map, 911 bool chmap_set) 912 { 913 if (!non_pcm && chmap_set) { 914 hdmi_manual_setup_channel_mapping(codec, pin_nid, 915 channels, map, ca); 916 } else { 917 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca); 918 hdmi_setup_fake_chmap(map, ca); 919 } 920 921 hdmi_debug_channel_mapping(codec, pin_nid); 922 } 923 924 static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid, 925 int asp_slot, int channel) 926 { 927 return snd_hda_codec_write(codec, pin_nid, 0, 928 AC_VERB_SET_HDMI_CHAN_SLOT, 929 (channel << 4) | asp_slot); 930 } 931 932 static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid, 933 int asp_slot) 934 { 935 return (snd_hda_codec_read(codec, pin_nid, 0, 936 AC_VERB_GET_HDMI_CHAN_SLOT, 937 asp_slot) & 0xf0) >> 4; 938 } 939 940 /* 941 * Audio InfoFrame routines 942 */ 943 944 /* 945 * Enable Audio InfoFrame Transmission 946 */ 947 static void hdmi_start_infoframe_trans(struct hda_codec *codec, 948 hda_nid_t pin_nid) 949 { 950 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 951 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 952 AC_DIPXMIT_BEST); 953 } 954 955 /* 956 * Disable Audio InfoFrame Transmission 957 */ 958 static void hdmi_stop_infoframe_trans(struct hda_codec *codec, 959 hda_nid_t pin_nid) 960 { 961 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 962 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 963 AC_DIPXMIT_DISABLE); 964 } 965 966 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) 967 { 968 #ifdef CONFIG_SND_DEBUG_VERBOSE 969 int i; 970 int size; 971 972 size = snd_hdmi_get_eld_size(codec, pin_nid); 973 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); 974 975 for (i = 0; i < 8; i++) { 976 size = snd_hda_codec_read(codec, pin_nid, 0, 977 AC_VERB_GET_HDMI_DIP_SIZE, i); 978 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); 979 } 980 #endif 981 } 982 983 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) 984 { 985 #ifdef BE_PARANOID 986 int i, j; 987 int size; 988 int pi, bi; 989 for (i = 0; i < 8; i++) { 990 size = snd_hda_codec_read(codec, pin_nid, 0, 991 AC_VERB_GET_HDMI_DIP_SIZE, i); 992 if (size == 0) 993 continue; 994 995 hdmi_set_dip_index(codec, pin_nid, i, 0x0); 996 for (j = 1; j < 1000; j++) { 997 hdmi_write_dip_byte(codec, pin_nid, 0x0); 998 hdmi_get_dip_index(codec, pin_nid, &pi, &bi); 999 if (pi != i) 1000 codec_dbg(codec, "dip index %d: %d != %d\n", 1001 bi, pi, i); 1002 if (bi == 0) /* byte index wrapped around */ 1003 break; 1004 } 1005 codec_dbg(codec, 1006 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", 1007 i, size, j); 1008 } 1009 #endif 1010 } 1011 1012 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) 1013 { 1014 u8 *bytes = (u8 *)hdmi_ai; 1015 u8 sum = 0; 1016 int i; 1017 1018 hdmi_ai->checksum = 0; 1019 1020 for (i = 0; i < sizeof(*hdmi_ai); i++) 1021 sum += bytes[i]; 1022 1023 hdmi_ai->checksum = -sum; 1024 } 1025 1026 static void hdmi_fill_audio_infoframe(struct hda_codec *codec, 1027 hda_nid_t pin_nid, 1028 u8 *dip, int size) 1029 { 1030 int i; 1031 1032 hdmi_debug_dip_size(codec, pin_nid); 1033 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ 1034 1035 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 1036 for (i = 0; i < size; i++) 1037 hdmi_write_dip_byte(codec, pin_nid, dip[i]); 1038 } 1039 1040 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, 1041 u8 *dip, int size) 1042 { 1043 u8 val; 1044 int i; 1045 1046 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) 1047 != AC_DIPXMIT_BEST) 1048 return false; 1049 1050 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 1051 for (i = 0; i < size; i++) { 1052 val = snd_hda_codec_read(codec, pin_nid, 0, 1053 AC_VERB_GET_HDMI_DIP_DATA, 0); 1054 if (val != dip[i]) 1055 return false; 1056 } 1057 1058 return true; 1059 } 1060 1061 static void hdmi_pin_setup_infoframe(struct hda_codec *codec, 1062 hda_nid_t pin_nid, 1063 int ca, int active_channels, 1064 int conn_type) 1065 { 1066 union audio_infoframe ai; 1067 1068 memset(&ai, 0, sizeof(ai)); 1069 if (conn_type == 0) { /* HDMI */ 1070 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; 1071 1072 hdmi_ai->type = 0x84; 1073 hdmi_ai->ver = 0x01; 1074 hdmi_ai->len = 0x0a; 1075 hdmi_ai->CC02_CT47 = active_channels - 1; 1076 hdmi_ai->CA = ca; 1077 hdmi_checksum_audio_infoframe(hdmi_ai); 1078 } else if (conn_type == 1) { /* DisplayPort */ 1079 struct dp_audio_infoframe *dp_ai = &ai.dp; 1080 1081 dp_ai->type = 0x84; 1082 dp_ai->len = 0x1b; 1083 dp_ai->ver = 0x11 << 2; 1084 dp_ai->CC02_CT47 = active_channels - 1; 1085 dp_ai->CA = ca; 1086 } else { 1087 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n", 1088 pin_nid); 1089 return; 1090 } 1091 1092 /* 1093 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or 1094 * sizeof(*dp_ai) to avoid partial match/update problems when 1095 * the user switches between HDMI/DP monitors. 1096 */ 1097 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, 1098 sizeof(ai))) { 1099 codec_dbg(codec, 1100 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n", 1101 pin_nid, 1102 active_channels, ca); 1103 hdmi_stop_infoframe_trans(codec, pin_nid); 1104 hdmi_fill_audio_infoframe(codec, pin_nid, 1105 ai.bytes, sizeof(ai)); 1106 hdmi_start_infoframe_trans(codec, pin_nid); 1107 } 1108 } 1109 1110 static void hdmi_setup_audio_infoframe(struct hda_codec *codec, 1111 struct hdmi_spec_per_pin *per_pin, 1112 bool non_pcm) 1113 { 1114 struct hdmi_spec *spec = codec->spec; 1115 hda_nid_t pin_nid = per_pin->pin_nid; 1116 int channels = per_pin->channels; 1117 int active_channels; 1118 struct hdmi_eld *eld; 1119 int ca, ordered_ca; 1120 1121 if (!channels) 1122 return; 1123 1124 if (is_haswell_plus(codec)) 1125 snd_hda_codec_write(codec, pin_nid, 0, 1126 AC_VERB_SET_AMP_GAIN_MUTE, 1127 AMP_OUT_UNMUTE); 1128 1129 eld = &per_pin->sink_eld; 1130 if (!eld->monitor_present) 1131 return; 1132 1133 if (!non_pcm && per_pin->chmap_set) 1134 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap); 1135 else 1136 ca = hdmi_channel_allocation(eld, channels); 1137 if (ca < 0) 1138 ca = 0; 1139 1140 ordered_ca = get_channel_allocation_order(ca); 1141 active_channels = channel_allocations[ordered_ca].channels; 1142 1143 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels); 1144 1145 /* 1146 * always configure channel mapping, it may have been changed by the 1147 * user in the meantime 1148 */ 1149 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca, 1150 channels, per_pin->chmap, 1151 per_pin->chmap_set); 1152 1153 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels, 1154 eld->info.conn_type); 1155 1156 per_pin->non_pcm = non_pcm; 1157 } 1158 1159 /* 1160 * Unsolicited events 1161 */ 1162 1163 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); 1164 1165 static void jack_callback(struct hda_codec *codec, struct hda_jack_tbl *jack) 1166 { 1167 struct hdmi_spec *spec = codec->spec; 1168 int pin_idx = pin_nid_to_pin_index(codec, jack->nid); 1169 if (pin_idx < 0) 1170 return; 1171 1172 if (hdmi_present_sense(get_pin(spec, pin_idx), 1)) 1173 snd_hda_jack_report_sync(codec); 1174 } 1175 1176 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res) 1177 { 1178 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 1179 struct hda_jack_tbl *jack; 1180 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 1181 1182 jack = snd_hda_jack_tbl_get_from_tag(codec, tag); 1183 if (!jack) 1184 return; 1185 jack->jack_dirty = 1; 1186 1187 codec_dbg(codec, 1188 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", 1189 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA), 1190 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); 1191 1192 jack_callback(codec, jack); 1193 } 1194 1195 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) 1196 { 1197 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 1198 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 1199 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); 1200 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); 1201 1202 codec_info(codec, 1203 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", 1204 codec->addr, 1205 tag, 1206 subtag, 1207 cp_state, 1208 cp_ready); 1209 1210 /* TODO */ 1211 if (cp_state) 1212 ; 1213 if (cp_ready) 1214 ; 1215 } 1216 1217 1218 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) 1219 { 1220 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 1221 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 1222 1223 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) { 1224 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); 1225 return; 1226 } 1227 1228 if (subtag == 0) 1229 hdmi_intrinsic_event(codec, res); 1230 else 1231 hdmi_non_intrinsic_event(codec, res); 1232 } 1233 1234 static void haswell_verify_D0(struct hda_codec *codec, 1235 hda_nid_t cvt_nid, hda_nid_t nid) 1236 { 1237 int pwr; 1238 1239 /* For Haswell, the converter 1/2 may keep in D3 state after bootup, 1240 * thus pins could only choose converter 0 for use. Make sure the 1241 * converters are in correct power state */ 1242 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) 1243 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); 1244 1245 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { 1246 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, 1247 AC_PWRST_D0); 1248 msleep(40); 1249 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); 1250 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; 1251 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr); 1252 } 1253 } 1254 1255 /* 1256 * Callbacks 1257 */ 1258 1259 /* HBR should be Non-PCM, 8 channels */ 1260 #define is_hbr_format(format) \ 1261 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) 1262 1263 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 1264 bool hbr) 1265 { 1266 int pinctl, new_pinctl; 1267 1268 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { 1269 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 1270 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 1271 1272 if (pinctl < 0) 1273 return hbr ? -EINVAL : 0; 1274 1275 new_pinctl = pinctl & ~AC_PINCTL_EPT; 1276 if (hbr) 1277 new_pinctl |= AC_PINCTL_EPT_HBR; 1278 else 1279 new_pinctl |= AC_PINCTL_EPT_NATIVE; 1280 1281 codec_dbg(codec, 1282 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", 1283 pin_nid, 1284 pinctl == new_pinctl ? "" : "new-", 1285 new_pinctl); 1286 1287 if (pinctl != new_pinctl) 1288 snd_hda_codec_write(codec, pin_nid, 0, 1289 AC_VERB_SET_PIN_WIDGET_CONTROL, 1290 new_pinctl); 1291 } else if (hbr) 1292 return -EINVAL; 1293 1294 return 0; 1295 } 1296 1297 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 1298 hda_nid_t pin_nid, u32 stream_tag, int format) 1299 { 1300 struct hdmi_spec *spec = codec->spec; 1301 int err; 1302 1303 if (is_haswell_plus(codec)) 1304 haswell_verify_D0(codec, cvt_nid, pin_nid); 1305 1306 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format)); 1307 1308 if (err) { 1309 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); 1310 return err; 1311 } 1312 1313 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); 1314 return 0; 1315 } 1316 1317 static int hdmi_choose_cvt(struct hda_codec *codec, 1318 int pin_idx, int *cvt_id, int *mux_id) 1319 { 1320 struct hdmi_spec *spec = codec->spec; 1321 struct hdmi_spec_per_pin *per_pin; 1322 struct hdmi_spec_per_cvt *per_cvt = NULL; 1323 int cvt_idx, mux_idx = 0; 1324 1325 per_pin = get_pin(spec, pin_idx); 1326 1327 /* Dynamically assign converter to stream */ 1328 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1329 per_cvt = get_cvt(spec, cvt_idx); 1330 1331 /* Must not already be assigned */ 1332 if (per_cvt->assigned) 1333 continue; 1334 /* Must be in pin's mux's list of converters */ 1335 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1336 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) 1337 break; 1338 /* Not in mux list */ 1339 if (mux_idx == per_pin->num_mux_nids) 1340 continue; 1341 break; 1342 } 1343 1344 /* No free converters */ 1345 if (cvt_idx == spec->num_cvts) 1346 return -ENODEV; 1347 1348 per_pin->mux_idx = mux_idx; 1349 1350 if (cvt_id) 1351 *cvt_id = cvt_idx; 1352 if (mux_id) 1353 *mux_id = mux_idx; 1354 1355 return 0; 1356 } 1357 1358 /* Assure the pin select the right convetor */ 1359 static void intel_verify_pin_cvt_connect(struct hda_codec *codec, 1360 struct hdmi_spec_per_pin *per_pin) 1361 { 1362 hda_nid_t pin_nid = per_pin->pin_nid; 1363 int mux_idx, curr; 1364 1365 mux_idx = per_pin->mux_idx; 1366 curr = snd_hda_codec_read(codec, pin_nid, 0, 1367 AC_VERB_GET_CONNECT_SEL, 0); 1368 if (curr != mux_idx) 1369 snd_hda_codec_write_cache(codec, pin_nid, 0, 1370 AC_VERB_SET_CONNECT_SEL, 1371 mux_idx); 1372 } 1373 1374 /* Intel HDMI workaround to fix audio routing issue: 1375 * For some Intel display codecs, pins share the same connection list. 1376 * So a conveter can be selected by multiple pins and playback on any of these 1377 * pins will generate sound on the external display, because audio flows from 1378 * the same converter to the display pipeline. Also muting one pin may make 1379 * other pins have no sound output. 1380 * So this function assures that an assigned converter for a pin is not selected 1381 * by any other pins. 1382 */ 1383 static void intel_not_share_assigned_cvt(struct hda_codec *codec, 1384 hda_nid_t pin_nid, int mux_idx) 1385 { 1386 struct hdmi_spec *spec = codec->spec; 1387 hda_nid_t nid, end_nid; 1388 int cvt_idx, curr; 1389 struct hdmi_spec_per_cvt *per_cvt; 1390 1391 /* configure all pins, including "no physical connection" ones */ 1392 end_nid = codec->start_nid + codec->num_nodes; 1393 for (nid = codec->start_nid; nid < end_nid; nid++) { 1394 unsigned int wid_caps = get_wcaps(codec, nid); 1395 unsigned int wid_type = get_wcaps_type(wid_caps); 1396 1397 if (wid_type != AC_WID_PIN) 1398 continue; 1399 1400 if (nid == pin_nid) 1401 continue; 1402 1403 curr = snd_hda_codec_read(codec, nid, 0, 1404 AC_VERB_GET_CONNECT_SEL, 0); 1405 if (curr != mux_idx) 1406 continue; 1407 1408 /* choose an unassigned converter. The conveters in the 1409 * connection list are in the same order as in the codec. 1410 */ 1411 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1412 per_cvt = get_cvt(spec, cvt_idx); 1413 if (!per_cvt->assigned) { 1414 codec_dbg(codec, 1415 "choose cvt %d for pin nid %d\n", 1416 cvt_idx, nid); 1417 snd_hda_codec_write_cache(codec, nid, 0, 1418 AC_VERB_SET_CONNECT_SEL, 1419 cvt_idx); 1420 break; 1421 } 1422 } 1423 } 1424 } 1425 1426 /* 1427 * HDA PCM callbacks 1428 */ 1429 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, 1430 struct hda_codec *codec, 1431 struct snd_pcm_substream *substream) 1432 { 1433 struct hdmi_spec *spec = codec->spec; 1434 struct snd_pcm_runtime *runtime = substream->runtime; 1435 int pin_idx, cvt_idx, mux_idx = 0; 1436 struct hdmi_spec_per_pin *per_pin; 1437 struct hdmi_eld *eld; 1438 struct hdmi_spec_per_cvt *per_cvt = NULL; 1439 int err; 1440 1441 /* Validate hinfo */ 1442 pin_idx = hinfo_to_pin_index(codec, hinfo); 1443 if (snd_BUG_ON(pin_idx < 0)) 1444 return -EINVAL; 1445 per_pin = get_pin(spec, pin_idx); 1446 eld = &per_pin->sink_eld; 1447 1448 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx); 1449 if (err < 0) 1450 return err; 1451 1452 per_cvt = get_cvt(spec, cvt_idx); 1453 /* Claim converter */ 1454 per_cvt->assigned = 1; 1455 per_pin->cvt_nid = per_cvt->cvt_nid; 1456 hinfo->nid = per_cvt->cvt_nid; 1457 1458 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1459 AC_VERB_SET_CONNECT_SEL, 1460 mux_idx); 1461 1462 /* configure unused pins to choose other converters */ 1463 if (is_haswell_plus(codec) || is_valleyview(codec)) 1464 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx); 1465 1466 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid); 1467 1468 /* Initially set the converter's capabilities */ 1469 hinfo->channels_min = per_cvt->channels_min; 1470 hinfo->channels_max = per_cvt->channels_max; 1471 hinfo->rates = per_cvt->rates; 1472 hinfo->formats = per_cvt->formats; 1473 hinfo->maxbps = per_cvt->maxbps; 1474 1475 /* Restrict capabilities by ELD if this isn't disabled */ 1476 if (!static_hdmi_pcm && eld->eld_valid) { 1477 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); 1478 if (hinfo->channels_min > hinfo->channels_max || 1479 !hinfo->rates || !hinfo->formats) { 1480 per_cvt->assigned = 0; 1481 hinfo->nid = 0; 1482 snd_hda_spdif_ctls_unassign(codec, pin_idx); 1483 return -ENODEV; 1484 } 1485 } 1486 1487 /* Store the updated parameters */ 1488 runtime->hw.channels_min = hinfo->channels_min; 1489 runtime->hw.channels_max = hinfo->channels_max; 1490 runtime->hw.formats = hinfo->formats; 1491 runtime->hw.rates = hinfo->rates; 1492 1493 snd_pcm_hw_constraint_step(substream->runtime, 0, 1494 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1495 return 0; 1496 } 1497 1498 /* 1499 * HDA/HDMI auto parsing 1500 */ 1501 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) 1502 { 1503 struct hdmi_spec *spec = codec->spec; 1504 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1505 hda_nid_t pin_nid = per_pin->pin_nid; 1506 1507 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { 1508 codec_warn(codec, 1509 "HDMI: pin %d wcaps %#x does not support connection list\n", 1510 pin_nid, get_wcaps(codec, pin_nid)); 1511 return -EINVAL; 1512 } 1513 1514 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid, 1515 per_pin->mux_nids, 1516 HDA_MAX_CONNECTIONS); 1517 1518 return 0; 1519 } 1520 1521 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) 1522 { 1523 struct hda_jack_tbl *jack; 1524 struct hda_codec *codec = per_pin->codec; 1525 struct hdmi_spec *spec = codec->spec; 1526 struct hdmi_eld *eld = &spec->temp_eld; 1527 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 1528 hda_nid_t pin_nid = per_pin->pin_nid; 1529 /* 1530 * Always execute a GetPinSense verb here, even when called from 1531 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited 1532 * response's PD bit is not the real PD value, but indicates that 1533 * the real PD value changed. An older version of the HD-audio 1534 * specification worked this way. Hence, we just ignore the data in 1535 * the unsolicited response to avoid custom WARs. 1536 */ 1537 int present; 1538 bool update_eld = false; 1539 bool eld_changed = false; 1540 bool ret; 1541 1542 snd_hda_power_up(codec); 1543 present = snd_hda_pin_sense(codec, pin_nid); 1544 1545 mutex_lock(&per_pin->lock); 1546 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); 1547 if (pin_eld->monitor_present) 1548 eld->eld_valid = !!(present & AC_PINSENSE_ELDV); 1549 else 1550 eld->eld_valid = false; 1551 1552 codec_dbg(codec, 1553 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n", 1554 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid); 1555 1556 if (eld->eld_valid) { 1557 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer, 1558 &eld->eld_size) < 0) 1559 eld->eld_valid = false; 1560 else { 1561 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld)); 1562 if (snd_hdmi_parse_eld(&eld->info, eld->eld_buffer, 1563 eld->eld_size) < 0) 1564 eld->eld_valid = false; 1565 } 1566 1567 if (eld->eld_valid) { 1568 snd_hdmi_show_eld(&eld->info); 1569 update_eld = true; 1570 } 1571 else if (repoll) { 1572 queue_delayed_work(codec->bus->workq, 1573 &per_pin->work, 1574 msecs_to_jiffies(300)); 1575 goto unlock; 1576 } 1577 } 1578 1579 if (pin_eld->eld_valid && !eld->eld_valid) { 1580 update_eld = true; 1581 eld_changed = true; 1582 } 1583 if (update_eld) { 1584 bool old_eld_valid = pin_eld->eld_valid; 1585 pin_eld->eld_valid = eld->eld_valid; 1586 eld_changed = pin_eld->eld_size != eld->eld_size || 1587 memcmp(pin_eld->eld_buffer, eld->eld_buffer, 1588 eld->eld_size) != 0; 1589 if (eld_changed) 1590 memcpy(pin_eld->eld_buffer, eld->eld_buffer, 1591 eld->eld_size); 1592 pin_eld->eld_size = eld->eld_size; 1593 pin_eld->info = eld->info; 1594 1595 /* 1596 * Re-setup pin and infoframe. This is needed e.g. when 1597 * - sink is first plugged-in (infoframe is not set up if !monitor_present) 1598 * - transcoder can change during stream playback on Haswell 1599 */ 1600 if (eld->eld_valid && !old_eld_valid && per_pin->setup) 1601 hdmi_setup_audio_infoframe(codec, per_pin, 1602 per_pin->non_pcm); 1603 } 1604 1605 if (eld_changed) 1606 snd_ctl_notify(codec->bus->card, 1607 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO, 1608 &per_pin->eld_ctl->id); 1609 unlock: 1610 ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid; 1611 1612 jack = snd_hda_jack_tbl_get(codec, pin_nid); 1613 if (jack) 1614 jack->block_report = !ret; 1615 1616 mutex_unlock(&per_pin->lock); 1617 snd_hda_power_down(codec); 1618 return ret; 1619 } 1620 1621 static void hdmi_repoll_eld(struct work_struct *work) 1622 { 1623 struct hdmi_spec_per_pin *per_pin = 1624 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); 1625 1626 if (per_pin->repoll_count++ > 6) 1627 per_pin->repoll_count = 0; 1628 1629 if (hdmi_present_sense(per_pin, per_pin->repoll_count)) 1630 snd_hda_jack_report_sync(per_pin->codec); 1631 } 1632 1633 static void intel_haswell_fixup_connect_list(struct hda_codec *codec, 1634 hda_nid_t nid); 1635 1636 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) 1637 { 1638 struct hdmi_spec *spec = codec->spec; 1639 unsigned int caps, config; 1640 int pin_idx; 1641 struct hdmi_spec_per_pin *per_pin; 1642 int err; 1643 1644 caps = snd_hda_query_pin_caps(codec, pin_nid); 1645 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) 1646 return 0; 1647 1648 config = snd_hda_codec_get_pincfg(codec, pin_nid); 1649 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE) 1650 return 0; 1651 1652 if (is_haswell_plus(codec)) 1653 intel_haswell_fixup_connect_list(codec, pin_nid); 1654 1655 pin_idx = spec->num_pins; 1656 per_pin = snd_array_new(&spec->pins); 1657 if (!per_pin) 1658 return -ENOMEM; 1659 1660 per_pin->pin_nid = pin_nid; 1661 per_pin->non_pcm = false; 1662 1663 err = hdmi_read_pin_conn(codec, pin_idx); 1664 if (err < 0) 1665 return err; 1666 1667 spec->num_pins++; 1668 1669 return 0; 1670 } 1671 1672 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1673 { 1674 struct hdmi_spec *spec = codec->spec; 1675 struct hdmi_spec_per_cvt *per_cvt; 1676 unsigned int chans; 1677 int err; 1678 1679 chans = get_wcaps(codec, cvt_nid); 1680 chans = get_wcaps_channels(chans); 1681 1682 per_cvt = snd_array_new(&spec->cvts); 1683 if (!per_cvt) 1684 return -ENOMEM; 1685 1686 per_cvt->cvt_nid = cvt_nid; 1687 per_cvt->channels_min = 2; 1688 if (chans <= 16) { 1689 per_cvt->channels_max = chans; 1690 if (chans > spec->channels_max) 1691 spec->channels_max = chans; 1692 } 1693 1694 err = snd_hda_query_supported_pcm(codec, cvt_nid, 1695 &per_cvt->rates, 1696 &per_cvt->formats, 1697 &per_cvt->maxbps); 1698 if (err < 0) 1699 return err; 1700 1701 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) 1702 spec->cvt_nids[spec->num_cvts] = cvt_nid; 1703 spec->num_cvts++; 1704 1705 return 0; 1706 } 1707 1708 static int hdmi_parse_codec(struct hda_codec *codec) 1709 { 1710 hda_nid_t nid; 1711 int i, nodes; 1712 1713 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid); 1714 if (!nid || nodes < 0) { 1715 codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); 1716 return -EINVAL; 1717 } 1718 1719 for (i = 0; i < nodes; i++, nid++) { 1720 unsigned int caps; 1721 unsigned int type; 1722 1723 caps = get_wcaps(codec, nid); 1724 type = get_wcaps_type(caps); 1725 1726 if (!(caps & AC_WCAP_DIGITAL)) 1727 continue; 1728 1729 switch (type) { 1730 case AC_WID_AUD_OUT: 1731 hdmi_add_cvt(codec, nid); 1732 break; 1733 case AC_WID_PIN: 1734 hdmi_add_pin(codec, nid); 1735 break; 1736 } 1737 } 1738 1739 return 0; 1740 } 1741 1742 /* 1743 */ 1744 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1745 { 1746 struct hda_spdif_out *spdif; 1747 bool non_pcm; 1748 1749 mutex_lock(&codec->spdif_mutex); 1750 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); 1751 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); 1752 mutex_unlock(&codec->spdif_mutex); 1753 return non_pcm; 1754 } 1755 1756 1757 /* 1758 * HDMI callbacks 1759 */ 1760 1761 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 1762 struct hda_codec *codec, 1763 unsigned int stream_tag, 1764 unsigned int format, 1765 struct snd_pcm_substream *substream) 1766 { 1767 hda_nid_t cvt_nid = hinfo->nid; 1768 struct hdmi_spec *spec = codec->spec; 1769 int pin_idx = hinfo_to_pin_index(codec, hinfo); 1770 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1771 hda_nid_t pin_nid = per_pin->pin_nid; 1772 bool non_pcm; 1773 int pinctl; 1774 1775 if (is_haswell_plus(codec) || is_valleyview(codec)) { 1776 /* Verify pin:cvt selections to avoid silent audio after S3. 1777 * After S3, the audio driver restores pin:cvt selections 1778 * but this can happen before gfx is ready and such selection 1779 * is overlooked by HW. Thus multiple pins can share a same 1780 * default convertor and mute control will affect each other, 1781 * which can cause a resumed audio playback become silent 1782 * after S3. 1783 */ 1784 intel_verify_pin_cvt_connect(codec, per_pin); 1785 intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx); 1786 } 1787 1788 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); 1789 mutex_lock(&per_pin->lock); 1790 per_pin->channels = substream->runtime->channels; 1791 per_pin->setup = true; 1792 1793 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1794 mutex_unlock(&per_pin->lock); 1795 1796 if (spec->dyn_pin_out) { 1797 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 1798 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 1799 snd_hda_codec_write(codec, pin_nid, 0, 1800 AC_VERB_SET_PIN_WIDGET_CONTROL, 1801 pinctl | PIN_OUT); 1802 } 1803 1804 return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format); 1805 } 1806 1807 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 1808 struct hda_codec *codec, 1809 struct snd_pcm_substream *substream) 1810 { 1811 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 1812 return 0; 1813 } 1814 1815 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, 1816 struct hda_codec *codec, 1817 struct snd_pcm_substream *substream) 1818 { 1819 struct hdmi_spec *spec = codec->spec; 1820 int cvt_idx, pin_idx; 1821 struct hdmi_spec_per_cvt *per_cvt; 1822 struct hdmi_spec_per_pin *per_pin; 1823 int pinctl; 1824 1825 if (hinfo->nid) { 1826 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); 1827 if (snd_BUG_ON(cvt_idx < 0)) 1828 return -EINVAL; 1829 per_cvt = get_cvt(spec, cvt_idx); 1830 1831 snd_BUG_ON(!per_cvt->assigned); 1832 per_cvt->assigned = 0; 1833 hinfo->nid = 0; 1834 1835 pin_idx = hinfo_to_pin_index(codec, hinfo); 1836 if (snd_BUG_ON(pin_idx < 0)) 1837 return -EINVAL; 1838 per_pin = get_pin(spec, pin_idx); 1839 1840 if (spec->dyn_pin_out) { 1841 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 1842 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 1843 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 1844 AC_VERB_SET_PIN_WIDGET_CONTROL, 1845 pinctl & ~PIN_OUT); 1846 } 1847 1848 snd_hda_spdif_ctls_unassign(codec, pin_idx); 1849 1850 mutex_lock(&per_pin->lock); 1851 per_pin->chmap_set = false; 1852 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1853 1854 per_pin->setup = false; 1855 per_pin->channels = 0; 1856 mutex_unlock(&per_pin->lock); 1857 } 1858 1859 return 0; 1860 } 1861 1862 static const struct hda_pcm_ops generic_ops = { 1863 .open = hdmi_pcm_open, 1864 .close = hdmi_pcm_close, 1865 .prepare = generic_hdmi_playback_pcm_prepare, 1866 .cleanup = generic_hdmi_playback_pcm_cleanup, 1867 }; 1868 1869 /* 1870 * ALSA API channel-map control callbacks 1871 */ 1872 static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol, 1873 struct snd_ctl_elem_info *uinfo) 1874 { 1875 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol); 1876 struct hda_codec *codec = info->private_data; 1877 struct hdmi_spec *spec = codec->spec; 1878 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1879 uinfo->count = spec->channels_max; 1880 uinfo->value.integer.min = 0; 1881 uinfo->value.integer.max = SNDRV_CHMAP_LAST; 1882 return 0; 1883 } 1884 1885 static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap, 1886 int channels) 1887 { 1888 /* If the speaker allocation matches the channel count, it is OK.*/ 1889 if (cap->channels != channels) 1890 return -1; 1891 1892 /* all channels are remappable freely */ 1893 return SNDRV_CTL_TLVT_CHMAP_VAR; 1894 } 1895 1896 static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap, 1897 unsigned int *chmap, int channels) 1898 { 1899 int count = 0; 1900 int c; 1901 1902 for (c = 7; c >= 0; c--) { 1903 int spk = cap->speakers[c]; 1904 if (!spk) 1905 continue; 1906 1907 chmap[count++] = spk_to_chmap(spk); 1908 } 1909 1910 WARN_ON(count != channels); 1911 } 1912 1913 static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag, 1914 unsigned int size, unsigned int __user *tlv) 1915 { 1916 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol); 1917 struct hda_codec *codec = info->private_data; 1918 struct hdmi_spec *spec = codec->spec; 1919 unsigned int __user *dst; 1920 int chs, count = 0; 1921 1922 if (size < 8) 1923 return -ENOMEM; 1924 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv)) 1925 return -EFAULT; 1926 size -= 8; 1927 dst = tlv + 2; 1928 for (chs = 2; chs <= spec->channels_max; chs++) { 1929 int i; 1930 struct cea_channel_speaker_allocation *cap; 1931 cap = channel_allocations; 1932 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) { 1933 int chs_bytes = chs * 4; 1934 int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs); 1935 unsigned int tlv_chmap[8]; 1936 1937 if (type < 0) 1938 continue; 1939 if (size < 8) 1940 return -ENOMEM; 1941 if (put_user(type, dst) || 1942 put_user(chs_bytes, dst + 1)) 1943 return -EFAULT; 1944 dst += 2; 1945 size -= 8; 1946 count += 8; 1947 if (size < chs_bytes) 1948 return -ENOMEM; 1949 size -= chs_bytes; 1950 count += chs_bytes; 1951 spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs); 1952 if (copy_to_user(dst, tlv_chmap, chs_bytes)) 1953 return -EFAULT; 1954 dst += chs; 1955 } 1956 } 1957 if (put_user(count, tlv + 1)) 1958 return -EFAULT; 1959 return 0; 1960 } 1961 1962 static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol, 1963 struct snd_ctl_elem_value *ucontrol) 1964 { 1965 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol); 1966 struct hda_codec *codec = info->private_data; 1967 struct hdmi_spec *spec = codec->spec; 1968 int pin_idx = kcontrol->private_value; 1969 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1970 int i; 1971 1972 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++) 1973 ucontrol->value.integer.value[i] = per_pin->chmap[i]; 1974 return 0; 1975 } 1976 1977 static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol, 1978 struct snd_ctl_elem_value *ucontrol) 1979 { 1980 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol); 1981 struct hda_codec *codec = info->private_data; 1982 struct hdmi_spec *spec = codec->spec; 1983 int pin_idx = kcontrol->private_value; 1984 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1985 unsigned int ctl_idx; 1986 struct snd_pcm_substream *substream; 1987 unsigned char chmap[8]; 1988 int i, err, ca, prepared = 0; 1989 1990 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 1991 substream = snd_pcm_chmap_substream(info, ctl_idx); 1992 if (!substream || !substream->runtime) 1993 return 0; /* just for avoiding error from alsactl restore */ 1994 switch (substream->runtime->status->state) { 1995 case SNDRV_PCM_STATE_OPEN: 1996 case SNDRV_PCM_STATE_SETUP: 1997 break; 1998 case SNDRV_PCM_STATE_PREPARED: 1999 prepared = 1; 2000 break; 2001 default: 2002 return -EBUSY; 2003 } 2004 memset(chmap, 0, sizeof(chmap)); 2005 for (i = 0; i < ARRAY_SIZE(chmap); i++) 2006 chmap[i] = ucontrol->value.integer.value[i]; 2007 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap))) 2008 return 0; 2009 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap); 2010 if (ca < 0) 2011 return -EINVAL; 2012 if (spec->ops.chmap_validate) { 2013 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap); 2014 if (err) 2015 return err; 2016 } 2017 mutex_lock(&per_pin->lock); 2018 per_pin->chmap_set = true; 2019 memcpy(per_pin->chmap, chmap, sizeof(chmap)); 2020 if (prepared) 2021 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 2022 mutex_unlock(&per_pin->lock); 2023 2024 return 0; 2025 } 2026 2027 static int generic_hdmi_build_pcms(struct hda_codec *codec) 2028 { 2029 struct hdmi_spec *spec = codec->spec; 2030 int pin_idx; 2031 2032 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2033 struct hda_pcm *info; 2034 struct hda_pcm_stream *pstr; 2035 struct hdmi_spec_per_pin *per_pin; 2036 2037 per_pin = get_pin(spec, pin_idx); 2038 sprintf(per_pin->pcm_name, "HDMI %d", pin_idx); 2039 info = snd_array_new(&spec->pcm_rec); 2040 if (!info) 2041 return -ENOMEM; 2042 info->name = per_pin->pcm_name; 2043 info->pcm_type = HDA_PCM_TYPE_HDMI; 2044 info->own_chmap = true; 2045 2046 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2047 pstr->substreams = 1; 2048 pstr->ops = generic_ops; 2049 /* other pstr fields are set in open */ 2050 } 2051 2052 codec->num_pcms = spec->num_pins; 2053 codec->pcm_info = spec->pcm_rec.list; 2054 2055 return 0; 2056 } 2057 2058 static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx) 2059 { 2060 char hdmi_str[32] = "HDMI/DP"; 2061 struct hdmi_spec *spec = codec->spec; 2062 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2063 int pcmdev = get_pcm_rec(spec, pin_idx)->device; 2064 2065 if (pcmdev > 0) 2066 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); 2067 if (!is_jack_detectable(codec, per_pin->pin_nid)) 2068 strncat(hdmi_str, " Phantom", 2069 sizeof(hdmi_str) - strlen(hdmi_str) - 1); 2070 2071 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0); 2072 } 2073 2074 static int generic_hdmi_build_controls(struct hda_codec *codec) 2075 { 2076 struct hdmi_spec *spec = codec->spec; 2077 int err; 2078 int pin_idx; 2079 2080 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2081 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2082 2083 err = generic_hdmi_build_jack(codec, pin_idx); 2084 if (err < 0) 2085 return err; 2086 2087 err = snd_hda_create_dig_out_ctls(codec, 2088 per_pin->pin_nid, 2089 per_pin->mux_nids[0], 2090 HDA_PCM_TYPE_HDMI); 2091 if (err < 0) 2092 return err; 2093 snd_hda_spdif_ctls_unassign(codec, pin_idx); 2094 2095 /* add control for ELD Bytes */ 2096 err = hdmi_create_eld_ctl(codec, pin_idx, 2097 get_pcm_rec(spec, pin_idx)->device); 2098 2099 if (err < 0) 2100 return err; 2101 2102 hdmi_present_sense(per_pin, 0); 2103 } 2104 2105 /* add channel maps */ 2106 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2107 struct snd_pcm_chmap *chmap; 2108 struct snd_kcontrol *kctl; 2109 int i; 2110 2111 if (!codec->pcm_info[pin_idx].pcm) 2112 break; 2113 err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm, 2114 SNDRV_PCM_STREAM_PLAYBACK, 2115 NULL, 0, pin_idx, &chmap); 2116 if (err < 0) 2117 return err; 2118 /* override handlers */ 2119 chmap->private_data = codec; 2120 kctl = chmap->kctl; 2121 for (i = 0; i < kctl->count; i++) 2122 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE; 2123 kctl->info = hdmi_chmap_ctl_info; 2124 kctl->get = hdmi_chmap_ctl_get; 2125 kctl->put = hdmi_chmap_ctl_put; 2126 kctl->tlv.c = hdmi_chmap_ctl_tlv; 2127 } 2128 2129 return 0; 2130 } 2131 2132 static int generic_hdmi_init_per_pins(struct hda_codec *codec) 2133 { 2134 struct hdmi_spec *spec = codec->spec; 2135 int pin_idx; 2136 2137 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2138 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2139 2140 per_pin->codec = codec; 2141 mutex_init(&per_pin->lock); 2142 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); 2143 eld_proc_new(per_pin, pin_idx); 2144 } 2145 return 0; 2146 } 2147 2148 static int generic_hdmi_init(struct hda_codec *codec) 2149 { 2150 struct hdmi_spec *spec = codec->spec; 2151 int pin_idx; 2152 2153 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2154 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2155 hda_nid_t pin_nid = per_pin->pin_nid; 2156 2157 hdmi_init_pin(codec, pin_nid); 2158 snd_hda_jack_detect_enable_callback(codec, pin_nid, pin_nid, 2159 codec->jackpoll_interval > 0 ? jack_callback : NULL); 2160 } 2161 return 0; 2162 } 2163 2164 static void hdmi_array_init(struct hdmi_spec *spec, int nums) 2165 { 2166 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); 2167 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); 2168 snd_array_init(&spec->pcm_rec, sizeof(struct hda_pcm), nums); 2169 } 2170 2171 static void hdmi_array_free(struct hdmi_spec *spec) 2172 { 2173 snd_array_free(&spec->pins); 2174 snd_array_free(&spec->cvts); 2175 snd_array_free(&spec->pcm_rec); 2176 } 2177 2178 static void generic_hdmi_free(struct hda_codec *codec) 2179 { 2180 struct hdmi_spec *spec = codec->spec; 2181 int pin_idx; 2182 2183 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2184 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2185 2186 cancel_delayed_work(&per_pin->work); 2187 eld_proc_free(per_pin); 2188 } 2189 2190 flush_workqueue(codec->bus->workq); 2191 hdmi_array_free(spec); 2192 kfree(spec); 2193 } 2194 2195 #ifdef CONFIG_PM 2196 static int generic_hdmi_resume(struct hda_codec *codec) 2197 { 2198 struct hdmi_spec *spec = codec->spec; 2199 int pin_idx; 2200 2201 generic_hdmi_init(codec); 2202 snd_hda_codec_resume_amp(codec); 2203 snd_hda_codec_resume_cache(codec); 2204 2205 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2206 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2207 hdmi_present_sense(per_pin, 1); 2208 } 2209 return 0; 2210 } 2211 #endif 2212 2213 static const struct hda_codec_ops generic_hdmi_patch_ops = { 2214 .init = generic_hdmi_init, 2215 .free = generic_hdmi_free, 2216 .build_pcms = generic_hdmi_build_pcms, 2217 .build_controls = generic_hdmi_build_controls, 2218 .unsol_event = hdmi_unsol_event, 2219 #ifdef CONFIG_PM 2220 .resume = generic_hdmi_resume, 2221 #endif 2222 }; 2223 2224 static const struct hdmi_ops generic_standard_hdmi_ops = { 2225 .pin_get_eld = snd_hdmi_get_eld, 2226 .pin_get_slot_channel = hdmi_pin_get_slot_channel, 2227 .pin_set_slot_channel = hdmi_pin_set_slot_channel, 2228 .pin_setup_infoframe = hdmi_pin_setup_infoframe, 2229 .pin_hbr_setup = hdmi_pin_hbr_setup, 2230 .setup_stream = hdmi_setup_stream, 2231 .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type, 2232 .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap, 2233 }; 2234 2235 2236 static void intel_haswell_fixup_connect_list(struct hda_codec *codec, 2237 hda_nid_t nid) 2238 { 2239 struct hdmi_spec *spec = codec->spec; 2240 hda_nid_t conns[4]; 2241 int nconns; 2242 2243 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns)); 2244 if (nconns == spec->num_cvts && 2245 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t))) 2246 return; 2247 2248 /* override pins connection list */ 2249 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid); 2250 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids); 2251 } 2252 2253 #define INTEL_VENDOR_NID 0x08 2254 #define INTEL_GET_VENDOR_VERB 0xf81 2255 #define INTEL_SET_VENDOR_VERB 0x781 2256 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ 2257 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ 2258 2259 static void intel_haswell_enable_all_pins(struct hda_codec *codec, 2260 bool update_tree) 2261 { 2262 unsigned int vendor_param; 2263 2264 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0, 2265 INTEL_GET_VENDOR_VERB, 0); 2266 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) 2267 return; 2268 2269 vendor_param |= INTEL_EN_ALL_PIN_CVTS; 2270 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0, 2271 INTEL_SET_VENDOR_VERB, vendor_param); 2272 if (vendor_param == -1) 2273 return; 2274 2275 if (update_tree) 2276 snd_hda_codec_update_widgets(codec); 2277 } 2278 2279 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) 2280 { 2281 unsigned int vendor_param; 2282 2283 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0, 2284 INTEL_GET_VENDOR_VERB, 0); 2285 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) 2286 return; 2287 2288 /* enable DP1.2 mode */ 2289 vendor_param |= INTEL_EN_DP12; 2290 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0, 2291 INTEL_SET_VENDOR_VERB, vendor_param); 2292 } 2293 2294 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. 2295 * Otherwise you may get severe h/w communication errors. 2296 */ 2297 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, 2298 unsigned int power_state) 2299 { 2300 if (power_state == AC_PWRST_D0) { 2301 intel_haswell_enable_all_pins(codec, false); 2302 intel_haswell_fixup_enable_dp12(codec); 2303 } 2304 2305 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); 2306 snd_hda_codec_set_power_to_all(codec, fg, power_state); 2307 } 2308 2309 static int patch_generic_hdmi(struct hda_codec *codec) 2310 { 2311 struct hdmi_spec *spec; 2312 2313 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2314 if (spec == NULL) 2315 return -ENOMEM; 2316 2317 spec->ops = generic_standard_hdmi_ops; 2318 codec->spec = spec; 2319 hdmi_array_init(spec, 4); 2320 2321 if (is_haswell_plus(codec)) { 2322 intel_haswell_enable_all_pins(codec, true); 2323 intel_haswell_fixup_enable_dp12(codec); 2324 } 2325 2326 if (is_haswell(codec) || is_valleyview(codec)) { 2327 codec->depop_delay = 0; 2328 } 2329 2330 if (hdmi_parse_codec(codec) < 0) { 2331 codec->spec = NULL; 2332 kfree(spec); 2333 return -EINVAL; 2334 } 2335 codec->patch_ops = generic_hdmi_patch_ops; 2336 if (is_haswell_plus(codec)) { 2337 codec->patch_ops.set_power_state = haswell_set_power_state; 2338 codec->dp_mst = true; 2339 } 2340 2341 generic_hdmi_init_per_pins(codec); 2342 2343 init_channel_allocations(); 2344 2345 return 0; 2346 } 2347 2348 /* 2349 * Shared non-generic implementations 2350 */ 2351 2352 static int simple_playback_build_pcms(struct hda_codec *codec) 2353 { 2354 struct hdmi_spec *spec = codec->spec; 2355 struct hda_pcm *info; 2356 unsigned int chans; 2357 struct hda_pcm_stream *pstr; 2358 struct hdmi_spec_per_cvt *per_cvt; 2359 2360 per_cvt = get_cvt(spec, 0); 2361 chans = get_wcaps(codec, per_cvt->cvt_nid); 2362 chans = get_wcaps_channels(chans); 2363 2364 info = snd_array_new(&spec->pcm_rec); 2365 if (!info) 2366 return -ENOMEM; 2367 info->name = get_pin(spec, 0)->pcm_name; 2368 sprintf(info->name, "HDMI 0"); 2369 info->pcm_type = HDA_PCM_TYPE_HDMI; 2370 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2371 *pstr = spec->pcm_playback; 2372 pstr->nid = per_cvt->cvt_nid; 2373 if (pstr->channels_max <= 2 && chans && chans <= 16) 2374 pstr->channels_max = chans; 2375 2376 codec->num_pcms = 1; 2377 codec->pcm_info = info; 2378 2379 return 0; 2380 } 2381 2382 /* unsolicited event for jack sensing */ 2383 static void simple_hdmi_unsol_event(struct hda_codec *codec, 2384 unsigned int res) 2385 { 2386 snd_hda_jack_set_dirty_all(codec); 2387 snd_hda_jack_report_sync(codec); 2388 } 2389 2390 /* generic_hdmi_build_jack can be used for simple_hdmi, too, 2391 * as long as spec->pins[] is set correctly 2392 */ 2393 #define simple_hdmi_build_jack generic_hdmi_build_jack 2394 2395 static int simple_playback_build_controls(struct hda_codec *codec) 2396 { 2397 struct hdmi_spec *spec = codec->spec; 2398 struct hdmi_spec_per_cvt *per_cvt; 2399 int err; 2400 2401 per_cvt = get_cvt(spec, 0); 2402 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, 2403 per_cvt->cvt_nid, 2404 HDA_PCM_TYPE_HDMI); 2405 if (err < 0) 2406 return err; 2407 return simple_hdmi_build_jack(codec, 0); 2408 } 2409 2410 static int simple_playback_init(struct hda_codec *codec) 2411 { 2412 struct hdmi_spec *spec = codec->spec; 2413 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); 2414 hda_nid_t pin = per_pin->pin_nid; 2415 2416 snd_hda_codec_write(codec, pin, 0, 2417 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); 2418 /* some codecs require to unmute the pin */ 2419 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 2420 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, 2421 AMP_OUT_UNMUTE); 2422 snd_hda_jack_detect_enable(codec, pin, pin); 2423 return 0; 2424 } 2425 2426 static void simple_playback_free(struct hda_codec *codec) 2427 { 2428 struct hdmi_spec *spec = codec->spec; 2429 2430 hdmi_array_free(spec); 2431 kfree(spec); 2432 } 2433 2434 /* 2435 * Nvidia specific implementations 2436 */ 2437 2438 #define Nv_VERB_SET_Channel_Allocation 0xF79 2439 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A 2440 #define Nv_VERB_SET_Audio_Protection_On 0xF98 2441 #define Nv_VERB_SET_Audio_Protection_Off 0xF99 2442 2443 #define nvhdmi_master_con_nid_7x 0x04 2444 #define nvhdmi_master_pin_nid_7x 0x05 2445 2446 static const hda_nid_t nvhdmi_con_nids_7x[4] = { 2447 /*front, rear, clfe, rear_surr */ 2448 0x6, 0x8, 0xa, 0xc, 2449 }; 2450 2451 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { 2452 /* set audio protect on */ 2453 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 2454 /* enable digital output on pin widget */ 2455 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2456 {} /* terminator */ 2457 }; 2458 2459 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { 2460 /* set audio protect on */ 2461 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 2462 /* enable digital output on pin widget */ 2463 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2464 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2465 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2466 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2467 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2468 {} /* terminator */ 2469 }; 2470 2471 #ifdef LIMITED_RATE_FMT_SUPPORT 2472 /* support only the safe format and rate */ 2473 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 2474 #define SUPPORTED_MAXBPS 16 2475 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE 2476 #else 2477 /* support all rates and formats */ 2478 #define SUPPORTED_RATES \ 2479 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ 2480 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ 2481 SNDRV_PCM_RATE_192000) 2482 #define SUPPORTED_MAXBPS 24 2483 #define SUPPORTED_FORMATS \ 2484 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 2485 #endif 2486 2487 static int nvhdmi_7x_init_2ch(struct hda_codec *codec) 2488 { 2489 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); 2490 return 0; 2491 } 2492 2493 static int nvhdmi_7x_init_8ch(struct hda_codec *codec) 2494 { 2495 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); 2496 return 0; 2497 } 2498 2499 static unsigned int channels_2_6_8[] = { 2500 2, 6, 8 2501 }; 2502 2503 static unsigned int channels_2_8[] = { 2504 2, 8 2505 }; 2506 2507 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { 2508 .count = ARRAY_SIZE(channels_2_6_8), 2509 .list = channels_2_6_8, 2510 .mask = 0, 2511 }; 2512 2513 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { 2514 .count = ARRAY_SIZE(channels_2_8), 2515 .list = channels_2_8, 2516 .mask = 0, 2517 }; 2518 2519 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, 2520 struct hda_codec *codec, 2521 struct snd_pcm_substream *substream) 2522 { 2523 struct hdmi_spec *spec = codec->spec; 2524 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; 2525 2526 switch (codec->preset->id) { 2527 case 0x10de0002: 2528 case 0x10de0003: 2529 case 0x10de0005: 2530 case 0x10de0006: 2531 hw_constraints_channels = &hw_constraints_2_8_channels; 2532 break; 2533 case 0x10de0007: 2534 hw_constraints_channels = &hw_constraints_2_6_8_channels; 2535 break; 2536 default: 2537 break; 2538 } 2539 2540 if (hw_constraints_channels != NULL) { 2541 snd_pcm_hw_constraint_list(substream->runtime, 0, 2542 SNDRV_PCM_HW_PARAM_CHANNELS, 2543 hw_constraints_channels); 2544 } else { 2545 snd_pcm_hw_constraint_step(substream->runtime, 0, 2546 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 2547 } 2548 2549 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 2550 } 2551 2552 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, 2553 struct hda_codec *codec, 2554 struct snd_pcm_substream *substream) 2555 { 2556 struct hdmi_spec *spec = codec->spec; 2557 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 2558 } 2559 2560 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 2561 struct hda_codec *codec, 2562 unsigned int stream_tag, 2563 unsigned int format, 2564 struct snd_pcm_substream *substream) 2565 { 2566 struct hdmi_spec *spec = codec->spec; 2567 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 2568 stream_tag, format, substream); 2569 } 2570 2571 static const struct hda_pcm_stream simple_pcm_playback = { 2572 .substreams = 1, 2573 .channels_min = 2, 2574 .channels_max = 2, 2575 .ops = { 2576 .open = simple_playback_pcm_open, 2577 .close = simple_playback_pcm_close, 2578 .prepare = simple_playback_pcm_prepare 2579 }, 2580 }; 2581 2582 static const struct hda_codec_ops simple_hdmi_patch_ops = { 2583 .build_controls = simple_playback_build_controls, 2584 .build_pcms = simple_playback_build_pcms, 2585 .init = simple_playback_init, 2586 .free = simple_playback_free, 2587 .unsol_event = simple_hdmi_unsol_event, 2588 }; 2589 2590 static int patch_simple_hdmi(struct hda_codec *codec, 2591 hda_nid_t cvt_nid, hda_nid_t pin_nid) 2592 { 2593 struct hdmi_spec *spec; 2594 struct hdmi_spec_per_cvt *per_cvt; 2595 struct hdmi_spec_per_pin *per_pin; 2596 2597 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2598 if (!spec) 2599 return -ENOMEM; 2600 2601 codec->spec = spec; 2602 hdmi_array_init(spec, 1); 2603 2604 spec->multiout.num_dacs = 0; /* no analog */ 2605 spec->multiout.max_channels = 2; 2606 spec->multiout.dig_out_nid = cvt_nid; 2607 spec->num_cvts = 1; 2608 spec->num_pins = 1; 2609 per_pin = snd_array_new(&spec->pins); 2610 per_cvt = snd_array_new(&spec->cvts); 2611 if (!per_pin || !per_cvt) { 2612 simple_playback_free(codec); 2613 return -ENOMEM; 2614 } 2615 per_cvt->cvt_nid = cvt_nid; 2616 per_pin->pin_nid = pin_nid; 2617 spec->pcm_playback = simple_pcm_playback; 2618 2619 codec->patch_ops = simple_hdmi_patch_ops; 2620 2621 return 0; 2622 } 2623 2624 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, 2625 int channels) 2626 { 2627 unsigned int chanmask; 2628 int chan = channels ? (channels - 1) : 1; 2629 2630 switch (channels) { 2631 default: 2632 case 0: 2633 case 2: 2634 chanmask = 0x00; 2635 break; 2636 case 4: 2637 chanmask = 0x08; 2638 break; 2639 case 6: 2640 chanmask = 0x0b; 2641 break; 2642 case 8: 2643 chanmask = 0x13; 2644 break; 2645 } 2646 2647 /* Set the audio infoframe channel allocation and checksum fields. The 2648 * channel count is computed implicitly by the hardware. */ 2649 snd_hda_codec_write(codec, 0x1, 0, 2650 Nv_VERB_SET_Channel_Allocation, chanmask); 2651 2652 snd_hda_codec_write(codec, 0x1, 0, 2653 Nv_VERB_SET_Info_Frame_Checksum, 2654 (0x71 - chan - chanmask)); 2655 } 2656 2657 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, 2658 struct hda_codec *codec, 2659 struct snd_pcm_substream *substream) 2660 { 2661 struct hdmi_spec *spec = codec->spec; 2662 int i; 2663 2664 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 2665 0, AC_VERB_SET_CHANNEL_STREAMID, 0); 2666 for (i = 0; i < 4; i++) { 2667 /* set the stream id */ 2668 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 2669 AC_VERB_SET_CHANNEL_STREAMID, 0); 2670 /* set the stream format */ 2671 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 2672 AC_VERB_SET_STREAM_FORMAT, 0); 2673 } 2674 2675 /* The audio hardware sends a channel count of 0x7 (8ch) when all the 2676 * streams are disabled. */ 2677 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 2678 2679 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 2680 } 2681 2682 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, 2683 struct hda_codec *codec, 2684 unsigned int stream_tag, 2685 unsigned int format, 2686 struct snd_pcm_substream *substream) 2687 { 2688 int chs; 2689 unsigned int dataDCC2, channel_id; 2690 int i; 2691 struct hdmi_spec *spec = codec->spec; 2692 struct hda_spdif_out *spdif; 2693 struct hdmi_spec_per_cvt *per_cvt; 2694 2695 mutex_lock(&codec->spdif_mutex); 2696 per_cvt = get_cvt(spec, 0); 2697 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); 2698 2699 chs = substream->runtime->channels; 2700 2701 dataDCC2 = 0x2; 2702 2703 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ 2704 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) 2705 snd_hda_codec_write(codec, 2706 nvhdmi_master_con_nid_7x, 2707 0, 2708 AC_VERB_SET_DIGI_CONVERT_1, 2709 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 2710 2711 /* set the stream id */ 2712 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 2713 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); 2714 2715 /* set the stream format */ 2716 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 2717 AC_VERB_SET_STREAM_FORMAT, format); 2718 2719 /* turn on again (if needed) */ 2720 /* enable and set the channel status audio/data flag */ 2721 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { 2722 snd_hda_codec_write(codec, 2723 nvhdmi_master_con_nid_7x, 2724 0, 2725 AC_VERB_SET_DIGI_CONVERT_1, 2726 spdif->ctls & 0xff); 2727 snd_hda_codec_write(codec, 2728 nvhdmi_master_con_nid_7x, 2729 0, 2730 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 2731 } 2732 2733 for (i = 0; i < 4; i++) { 2734 if (chs == 2) 2735 channel_id = 0; 2736 else 2737 channel_id = i * 2; 2738 2739 /* turn off SPDIF once; 2740 *otherwise the IEC958 bits won't be updated 2741 */ 2742 if (codec->spdif_status_reset && 2743 (spdif->ctls & AC_DIG1_ENABLE)) 2744 snd_hda_codec_write(codec, 2745 nvhdmi_con_nids_7x[i], 2746 0, 2747 AC_VERB_SET_DIGI_CONVERT_1, 2748 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 2749 /* set the stream id */ 2750 snd_hda_codec_write(codec, 2751 nvhdmi_con_nids_7x[i], 2752 0, 2753 AC_VERB_SET_CHANNEL_STREAMID, 2754 (stream_tag << 4) | channel_id); 2755 /* set the stream format */ 2756 snd_hda_codec_write(codec, 2757 nvhdmi_con_nids_7x[i], 2758 0, 2759 AC_VERB_SET_STREAM_FORMAT, 2760 format); 2761 /* turn on again (if needed) */ 2762 /* enable and set the channel status audio/data flag */ 2763 if (codec->spdif_status_reset && 2764 (spdif->ctls & AC_DIG1_ENABLE)) { 2765 snd_hda_codec_write(codec, 2766 nvhdmi_con_nids_7x[i], 2767 0, 2768 AC_VERB_SET_DIGI_CONVERT_1, 2769 spdif->ctls & 0xff); 2770 snd_hda_codec_write(codec, 2771 nvhdmi_con_nids_7x[i], 2772 0, 2773 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 2774 } 2775 } 2776 2777 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); 2778 2779 mutex_unlock(&codec->spdif_mutex); 2780 return 0; 2781 } 2782 2783 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { 2784 .substreams = 1, 2785 .channels_min = 2, 2786 .channels_max = 8, 2787 .nid = nvhdmi_master_con_nid_7x, 2788 .rates = SUPPORTED_RATES, 2789 .maxbps = SUPPORTED_MAXBPS, 2790 .formats = SUPPORTED_FORMATS, 2791 .ops = { 2792 .open = simple_playback_pcm_open, 2793 .close = nvhdmi_8ch_7x_pcm_close, 2794 .prepare = nvhdmi_8ch_7x_pcm_prepare 2795 }, 2796 }; 2797 2798 static int patch_nvhdmi_2ch(struct hda_codec *codec) 2799 { 2800 struct hdmi_spec *spec; 2801 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, 2802 nvhdmi_master_pin_nid_7x); 2803 if (err < 0) 2804 return err; 2805 2806 codec->patch_ops.init = nvhdmi_7x_init_2ch; 2807 /* override the PCM rates, etc, as the codec doesn't give full list */ 2808 spec = codec->spec; 2809 spec->pcm_playback.rates = SUPPORTED_RATES; 2810 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; 2811 spec->pcm_playback.formats = SUPPORTED_FORMATS; 2812 return 0; 2813 } 2814 2815 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) 2816 { 2817 struct hdmi_spec *spec = codec->spec; 2818 int err = simple_playback_build_pcms(codec); 2819 if (!err) { 2820 struct hda_pcm *info = get_pcm_rec(spec, 0); 2821 info->own_chmap = true; 2822 } 2823 return err; 2824 } 2825 2826 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) 2827 { 2828 struct hdmi_spec *spec = codec->spec; 2829 struct hda_pcm *info; 2830 struct snd_pcm_chmap *chmap; 2831 int err; 2832 2833 err = simple_playback_build_controls(codec); 2834 if (err < 0) 2835 return err; 2836 2837 /* add channel maps */ 2838 info = get_pcm_rec(spec, 0); 2839 err = snd_pcm_add_chmap_ctls(info->pcm, 2840 SNDRV_PCM_STREAM_PLAYBACK, 2841 snd_pcm_alt_chmaps, 8, 0, &chmap); 2842 if (err < 0) 2843 return err; 2844 switch (codec->preset->id) { 2845 case 0x10de0002: 2846 case 0x10de0003: 2847 case 0x10de0005: 2848 case 0x10de0006: 2849 chmap->channel_mask = (1U << 2) | (1U << 8); 2850 break; 2851 case 0x10de0007: 2852 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); 2853 } 2854 return 0; 2855 } 2856 2857 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) 2858 { 2859 struct hdmi_spec *spec; 2860 int err = patch_nvhdmi_2ch(codec); 2861 if (err < 0) 2862 return err; 2863 spec = codec->spec; 2864 spec->multiout.max_channels = 8; 2865 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; 2866 codec->patch_ops.init = nvhdmi_7x_init_8ch; 2867 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; 2868 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; 2869 2870 /* Initialize the audio infoframe channel mask and checksum to something 2871 * valid */ 2872 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 2873 2874 return 0; 2875 } 2876 2877 /* 2878 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: 2879 * - 0x10de0015 2880 * - 0x10de0040 2881 */ 2882 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap, 2883 int channels) 2884 { 2885 if (cap->ca_index == 0x00 && channels == 2) 2886 return SNDRV_CTL_TLVT_CHMAP_FIXED; 2887 2888 return hdmi_chmap_cea_alloc_validate_get_type(cap, channels); 2889 } 2890 2891 static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map) 2892 { 2893 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) 2894 return -EINVAL; 2895 2896 return 0; 2897 } 2898 2899 static int patch_nvhdmi(struct hda_codec *codec) 2900 { 2901 struct hdmi_spec *spec; 2902 int err; 2903 2904 err = patch_generic_hdmi(codec); 2905 if (err) 2906 return err; 2907 2908 spec = codec->spec; 2909 spec->dyn_pin_out = true; 2910 2911 spec->ops.chmap_cea_alloc_validate_get_type = 2912 nvhdmi_chmap_cea_alloc_validate_get_type; 2913 spec->ops.chmap_validate = nvhdmi_chmap_validate; 2914 2915 return 0; 2916 } 2917 2918 /* 2919 * ATI/AMD-specific implementations 2920 */ 2921 2922 #define is_amdhdmi_rev3_or_later(codec) \ 2923 ((codec)->vendor_id == 0x1002aa01 && ((codec)->revision_id & 0xff00) >= 0x0300) 2924 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) 2925 2926 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ 2927 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 2928 #define ATI_VERB_SET_DOWNMIX_INFO 0x772 2929 #define ATI_VERB_SET_MULTICHANNEL_01 0x777 2930 #define ATI_VERB_SET_MULTICHANNEL_23 0x778 2931 #define ATI_VERB_SET_MULTICHANNEL_45 0x779 2932 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a 2933 #define ATI_VERB_SET_HBR_CONTROL 0x77c 2934 #define ATI_VERB_SET_MULTICHANNEL_1 0x785 2935 #define ATI_VERB_SET_MULTICHANNEL_3 0x786 2936 #define ATI_VERB_SET_MULTICHANNEL_5 0x787 2937 #define ATI_VERB_SET_MULTICHANNEL_7 0x788 2938 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 2939 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 2940 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 2941 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 2942 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 2943 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 2944 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a 2945 #define ATI_VERB_GET_HBR_CONTROL 0xf7c 2946 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 2947 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 2948 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 2949 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 2950 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 2951 2952 /* AMD specific HDA cvt verbs */ 2953 #define ATI_VERB_SET_RAMP_RATE 0x770 2954 #define ATI_VERB_GET_RAMP_RATE 0xf70 2955 2956 #define ATI_OUT_ENABLE 0x1 2957 2958 #define ATI_MULTICHANNEL_MODE_PAIRED 0 2959 #define ATI_MULTICHANNEL_MODE_SINGLE 1 2960 2961 #define ATI_HBR_CAPABLE 0x01 2962 #define ATI_HBR_ENABLE 0x10 2963 2964 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 2965 unsigned char *buf, int *eld_size) 2966 { 2967 /* call hda_eld.c ATI/AMD-specific function */ 2968 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, 2969 is_amdhdmi_rev3_or_later(codec)); 2970 } 2971 2972 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca, 2973 int active_channels, int conn_type) 2974 { 2975 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); 2976 } 2977 2978 static int atihdmi_paired_swap_fc_lfe(int pos) 2979 { 2980 /* 2981 * ATI/AMD have automatic FC/LFE swap built-in 2982 * when in pairwise mapping mode. 2983 */ 2984 2985 switch (pos) { 2986 /* see channel_allocations[].speakers[] */ 2987 case 2: return 3; 2988 case 3: return 2; 2989 default: break; 2990 } 2991 2992 return pos; 2993 } 2994 2995 static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map) 2996 { 2997 struct cea_channel_speaker_allocation *cap; 2998 int i, j; 2999 3000 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ 3001 3002 cap = &channel_allocations[get_channel_allocation_order(ca)]; 3003 for (i = 0; i < chs; ++i) { 3004 int mask = to_spk_mask(map[i]); 3005 bool ok = false; 3006 bool companion_ok = false; 3007 3008 if (!mask) 3009 continue; 3010 3011 for (j = 0 + i % 2; j < 8; j += 2) { 3012 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); 3013 if (cap->speakers[chan_idx] == mask) { 3014 /* channel is in a supported position */ 3015 ok = true; 3016 3017 if (i % 2 == 0 && i + 1 < chs) { 3018 /* even channel, check the odd companion */ 3019 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); 3020 int comp_mask_req = to_spk_mask(map[i+1]); 3021 int comp_mask_act = cap->speakers[comp_chan_idx]; 3022 3023 if (comp_mask_req == comp_mask_act) 3024 companion_ok = true; 3025 else 3026 return -EINVAL; 3027 } 3028 break; 3029 } 3030 } 3031 3032 if (!ok) 3033 return -EINVAL; 3034 3035 if (companion_ok) 3036 i++; /* companion channel already checked */ 3037 } 3038 3039 return 0; 3040 } 3041 3042 static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid, 3043 int hdmi_slot, int stream_channel) 3044 { 3045 int verb; 3046 int ati_channel_setup = 0; 3047 3048 if (hdmi_slot > 7) 3049 return -EINVAL; 3050 3051 if (!has_amd_full_remap_support(codec)) { 3052 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); 3053 3054 /* In case this is an odd slot but without stream channel, do not 3055 * disable the slot since the corresponding even slot could have a 3056 * channel. In case neither have a channel, the slot pair will be 3057 * disabled when this function is called for the even slot. */ 3058 if (hdmi_slot % 2 != 0 && stream_channel == 0xf) 3059 return 0; 3060 3061 hdmi_slot -= hdmi_slot % 2; 3062 3063 if (stream_channel != 0xf) 3064 stream_channel -= stream_channel % 2; 3065 } 3066 3067 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; 3068 3069 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ 3070 3071 if (stream_channel != 0xf) 3072 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; 3073 3074 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); 3075 } 3076 3077 static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid, 3078 int asp_slot) 3079 { 3080 bool was_odd = false; 3081 int ati_asp_slot = asp_slot; 3082 int verb; 3083 int ati_channel_setup; 3084 3085 if (asp_slot > 7) 3086 return -EINVAL; 3087 3088 if (!has_amd_full_remap_support(codec)) { 3089 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); 3090 if (ati_asp_slot % 2 != 0) { 3091 ati_asp_slot -= 1; 3092 was_odd = true; 3093 } 3094 } 3095 3096 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; 3097 3098 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); 3099 3100 if (!(ati_channel_setup & ATI_OUT_ENABLE)) 3101 return 0xf; 3102 3103 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; 3104 } 3105 3106 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap, 3107 int channels) 3108 { 3109 int c; 3110 3111 /* 3112 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so 3113 * we need to take that into account (a single channel may take 2 3114 * channel slots if we need to carry a silent channel next to it). 3115 * On Rev3+ AMD codecs this function is not used. 3116 */ 3117 int chanpairs = 0; 3118 3119 /* We only produce even-numbered channel count TLVs */ 3120 if ((channels % 2) != 0) 3121 return -1; 3122 3123 for (c = 0; c < 7; c += 2) { 3124 if (cap->speakers[c] || cap->speakers[c+1]) 3125 chanpairs++; 3126 } 3127 3128 if (chanpairs * 2 != channels) 3129 return -1; 3130 3131 return SNDRV_CTL_TLVT_CHMAP_PAIRED; 3132 } 3133 3134 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap, 3135 unsigned int *chmap, int channels) 3136 { 3137 /* produce paired maps for pre-rev3 ATI/AMD codecs */ 3138 int count = 0; 3139 int c; 3140 3141 for (c = 7; c >= 0; c--) { 3142 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); 3143 int spk = cap->speakers[chan]; 3144 if (!spk) { 3145 /* add N/A channel if the companion channel is occupied */ 3146 if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) 3147 chmap[count++] = SNDRV_CHMAP_NA; 3148 3149 continue; 3150 } 3151 3152 chmap[count++] = spk_to_chmap(spk); 3153 } 3154 3155 WARN_ON(count != channels); 3156 } 3157 3158 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 3159 bool hbr) 3160 { 3161 int hbr_ctl, hbr_ctl_new; 3162 3163 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); 3164 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { 3165 if (hbr) 3166 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; 3167 else 3168 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; 3169 3170 codec_dbg(codec, 3171 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", 3172 pin_nid, 3173 hbr_ctl == hbr_ctl_new ? "" : "new-", 3174 hbr_ctl_new); 3175 3176 if (hbr_ctl != hbr_ctl_new) 3177 snd_hda_codec_write(codec, pin_nid, 0, 3178 ATI_VERB_SET_HBR_CONTROL, 3179 hbr_ctl_new); 3180 3181 } else if (hbr) 3182 return -EINVAL; 3183 3184 return 0; 3185 } 3186 3187 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 3188 hda_nid_t pin_nid, u32 stream_tag, int format) 3189 { 3190 3191 if (is_amdhdmi_rev3_or_later(codec)) { 3192 int ramp_rate = 180; /* default as per AMD spec */ 3193 /* disable ramp-up/down for non-pcm as per AMD spec */ 3194 if (format & AC_FMT_TYPE_NON_PCM) 3195 ramp_rate = 0; 3196 3197 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); 3198 } 3199 3200 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format); 3201 } 3202 3203 3204 static int atihdmi_init(struct hda_codec *codec) 3205 { 3206 struct hdmi_spec *spec = codec->spec; 3207 int pin_idx, err; 3208 3209 err = generic_hdmi_init(codec); 3210 3211 if (err) 3212 return err; 3213 3214 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 3215 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 3216 3217 /* make sure downmix information in infoframe is zero */ 3218 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); 3219 3220 /* enable channel-wise remap mode if supported */ 3221 if (has_amd_full_remap_support(codec)) 3222 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 3223 ATI_VERB_SET_MULTICHANNEL_MODE, 3224 ATI_MULTICHANNEL_MODE_SINGLE); 3225 } 3226 3227 return 0; 3228 } 3229 3230 static int patch_atihdmi(struct hda_codec *codec) 3231 { 3232 struct hdmi_spec *spec; 3233 struct hdmi_spec_per_cvt *per_cvt; 3234 int err, cvt_idx; 3235 3236 err = patch_generic_hdmi(codec); 3237 3238 if (err) 3239 return err; 3240 3241 codec->patch_ops.init = atihdmi_init; 3242 3243 spec = codec->spec; 3244 3245 spec->ops.pin_get_eld = atihdmi_pin_get_eld; 3246 spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; 3247 spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; 3248 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; 3249 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; 3250 spec->ops.setup_stream = atihdmi_setup_stream; 3251 3252 if (!has_amd_full_remap_support(codec)) { 3253 /* override to ATI/AMD-specific versions with pairwise mapping */ 3254 spec->ops.chmap_cea_alloc_validate_get_type = 3255 atihdmi_paired_chmap_cea_alloc_validate_get_type; 3256 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap; 3257 spec->ops.chmap_validate = atihdmi_paired_chmap_validate; 3258 } 3259 3260 /* ATI/AMD converters do not advertise all of their capabilities */ 3261 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 3262 per_cvt = get_cvt(spec, cvt_idx); 3263 per_cvt->channels_max = max(per_cvt->channels_max, 8u); 3264 per_cvt->rates |= SUPPORTED_RATES; 3265 per_cvt->formats |= SUPPORTED_FORMATS; 3266 per_cvt->maxbps = max(per_cvt->maxbps, 24u); 3267 } 3268 3269 spec->channels_max = max(spec->channels_max, 8u); 3270 3271 return 0; 3272 } 3273 3274 /* VIA HDMI Implementation */ 3275 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ 3276 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ 3277 3278 static int patch_via_hdmi(struct hda_codec *codec) 3279 { 3280 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); 3281 } 3282 3283 /* 3284 * called from hda_codec.c for generic HDMI support 3285 */ 3286 int snd_hda_parse_hdmi_codec(struct hda_codec *codec) 3287 { 3288 return patch_generic_hdmi(codec); 3289 } 3290 EXPORT_SYMBOL_GPL(snd_hda_parse_hdmi_codec); 3291 3292 /* 3293 * patch entries 3294 */ 3295 static const struct hda_codec_preset snd_hda_preset_hdmi[] = { 3296 { .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi }, 3297 { .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi }, 3298 { .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi }, 3299 { .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_atihdmi }, 3300 { .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi }, 3301 { .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi }, 3302 { .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi }, 3303 { .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x }, 3304 { .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x }, 3305 { .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x }, 3306 { .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x }, 3307 { .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x }, 3308 { .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_nvhdmi }, 3309 { .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_nvhdmi }, 3310 { .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_nvhdmi }, 3311 { .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_nvhdmi }, 3312 { .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_nvhdmi }, 3313 { .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_nvhdmi }, 3314 { .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_nvhdmi }, 3315 { .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_nvhdmi }, 3316 { .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_nvhdmi }, 3317 { .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_nvhdmi }, 3318 { .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_nvhdmi }, 3319 /* 17 is known to be absent */ 3320 { .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_nvhdmi }, 3321 { .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_nvhdmi }, 3322 { .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_nvhdmi }, 3323 { .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_nvhdmi }, 3324 { .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_nvhdmi }, 3325 { .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_nvhdmi }, 3326 { .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_nvhdmi }, 3327 { .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_nvhdmi }, 3328 { .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_nvhdmi }, 3329 { .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_nvhdmi }, 3330 { .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_nvhdmi }, 3331 { .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_nvhdmi }, 3332 { .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch }, 3333 { .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch }, 3334 { .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi }, 3335 { .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi }, 3336 { .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi }, 3337 { .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi }, 3338 { .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi }, 3339 { .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi }, 3340 { .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi }, 3341 { .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi }, 3342 { .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi }, 3343 { .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi }, 3344 { .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi }, 3345 { .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi }, 3346 { .id = 0x80862808, .name = "Broadwell HDMI", .patch = patch_generic_hdmi }, 3347 { .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi }, 3348 { .id = 0x80862882, .name = "Valleyview2 HDMI", .patch = patch_generic_hdmi }, 3349 { .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi }, 3350 {} /* terminator */ 3351 }; 3352 3353 MODULE_ALIAS("snd-hda-codec-id:1002793c"); 3354 MODULE_ALIAS("snd-hda-codec-id:10027919"); 3355 MODULE_ALIAS("snd-hda-codec-id:1002791a"); 3356 MODULE_ALIAS("snd-hda-codec-id:1002aa01"); 3357 MODULE_ALIAS("snd-hda-codec-id:10951390"); 3358 MODULE_ALIAS("snd-hda-codec-id:10951392"); 3359 MODULE_ALIAS("snd-hda-codec-id:10de0002"); 3360 MODULE_ALIAS("snd-hda-codec-id:10de0003"); 3361 MODULE_ALIAS("snd-hda-codec-id:10de0005"); 3362 MODULE_ALIAS("snd-hda-codec-id:10de0006"); 3363 MODULE_ALIAS("snd-hda-codec-id:10de0007"); 3364 MODULE_ALIAS("snd-hda-codec-id:10de000a"); 3365 MODULE_ALIAS("snd-hda-codec-id:10de000b"); 3366 MODULE_ALIAS("snd-hda-codec-id:10de000c"); 3367 MODULE_ALIAS("snd-hda-codec-id:10de000d"); 3368 MODULE_ALIAS("snd-hda-codec-id:10de0010"); 3369 MODULE_ALIAS("snd-hda-codec-id:10de0011"); 3370 MODULE_ALIAS("snd-hda-codec-id:10de0012"); 3371 MODULE_ALIAS("snd-hda-codec-id:10de0013"); 3372 MODULE_ALIAS("snd-hda-codec-id:10de0014"); 3373 MODULE_ALIAS("snd-hda-codec-id:10de0015"); 3374 MODULE_ALIAS("snd-hda-codec-id:10de0016"); 3375 MODULE_ALIAS("snd-hda-codec-id:10de0018"); 3376 MODULE_ALIAS("snd-hda-codec-id:10de0019"); 3377 MODULE_ALIAS("snd-hda-codec-id:10de001a"); 3378 MODULE_ALIAS("snd-hda-codec-id:10de001b"); 3379 MODULE_ALIAS("snd-hda-codec-id:10de001c"); 3380 MODULE_ALIAS("snd-hda-codec-id:10de0040"); 3381 MODULE_ALIAS("snd-hda-codec-id:10de0041"); 3382 MODULE_ALIAS("snd-hda-codec-id:10de0042"); 3383 MODULE_ALIAS("snd-hda-codec-id:10de0043"); 3384 MODULE_ALIAS("snd-hda-codec-id:10de0044"); 3385 MODULE_ALIAS("snd-hda-codec-id:10de0051"); 3386 MODULE_ALIAS("snd-hda-codec-id:10de0060"); 3387 MODULE_ALIAS("snd-hda-codec-id:10de0067"); 3388 MODULE_ALIAS("snd-hda-codec-id:10de8001"); 3389 MODULE_ALIAS("snd-hda-codec-id:11069f80"); 3390 MODULE_ALIAS("snd-hda-codec-id:11069f81"); 3391 MODULE_ALIAS("snd-hda-codec-id:11069f84"); 3392 MODULE_ALIAS("snd-hda-codec-id:11069f85"); 3393 MODULE_ALIAS("snd-hda-codec-id:17e80047"); 3394 MODULE_ALIAS("snd-hda-codec-id:80860054"); 3395 MODULE_ALIAS("snd-hda-codec-id:80862801"); 3396 MODULE_ALIAS("snd-hda-codec-id:80862802"); 3397 MODULE_ALIAS("snd-hda-codec-id:80862803"); 3398 MODULE_ALIAS("snd-hda-codec-id:80862804"); 3399 MODULE_ALIAS("snd-hda-codec-id:80862805"); 3400 MODULE_ALIAS("snd-hda-codec-id:80862806"); 3401 MODULE_ALIAS("snd-hda-codec-id:80862807"); 3402 MODULE_ALIAS("snd-hda-codec-id:80862808"); 3403 MODULE_ALIAS("snd-hda-codec-id:80862880"); 3404 MODULE_ALIAS("snd-hda-codec-id:80862882"); 3405 MODULE_ALIAS("snd-hda-codec-id:808629fb"); 3406 3407 MODULE_LICENSE("GPL"); 3408 MODULE_DESCRIPTION("HDMI HD-audio codec"); 3409 MODULE_ALIAS("snd-hda-codec-intelhdmi"); 3410 MODULE_ALIAS("snd-hda-codec-nvhdmi"); 3411 MODULE_ALIAS("snd-hda-codec-atihdmi"); 3412 3413 static struct hda_codec_preset_list intel_list = { 3414 .preset = snd_hda_preset_hdmi, 3415 .owner = THIS_MODULE, 3416 }; 3417 3418 static int __init patch_hdmi_init(void) 3419 { 3420 return snd_hda_add_codec_preset(&intel_list); 3421 } 3422 3423 static void __exit patch_hdmi_exit(void) 3424 { 3425 snd_hda_delete_codec_preset(&intel_list); 3426 } 3427 3428 module_init(patch_hdmi_init) 3429 module_exit(patch_hdmi_exit) 3430