1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs 5 * 6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. 7 * Copyright (c) 2006 ATI Technologies Inc. 8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved. 9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com> 10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> 11 * 12 * Authors: 13 * Wu Fengguang <wfg@linux.intel.com> 14 * 15 * Maintained by: 16 * Wu Fengguang <wfg@linux.intel.com> 17 */ 18 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/pci.h> 22 #include <linux/slab.h> 23 #include <linux/module.h> 24 #include <linux/pm_runtime.h> 25 #include <sound/core.h> 26 #include <sound/jack.h> 27 #include <sound/asoundef.h> 28 #include <sound/tlv.h> 29 #include <sound/hdaudio.h> 30 #include <sound/hda_i915.h> 31 #include <sound/hda_chmap.h> 32 #include <sound/hda_codec.h> 33 #include "hda_local.h" 34 #include "hda_jack.h" 35 #include "hda_controller.h" 36 37 static bool static_hdmi_pcm; 38 module_param(static_hdmi_pcm, bool, 0644); 39 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); 40 41 static bool enable_acomp = true; 42 module_param(enable_acomp, bool, 0444); 43 MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)"); 44 45 static bool enable_silent_stream = 46 IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM); 47 module_param(enable_silent_stream, bool, 0644); 48 MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices"); 49 50 static bool enable_all_pins; 51 module_param(enable_all_pins, bool, 0444); 52 MODULE_PARM_DESC(enable_all_pins, "Forcibly enable all pins"); 53 54 struct hdmi_spec_per_cvt { 55 hda_nid_t cvt_nid; 56 bool assigned; /* the stream has been assigned */ 57 bool silent_stream; /* silent stream activated */ 58 unsigned int channels_min; 59 unsigned int channels_max; 60 u32 rates; 61 u64 formats; 62 unsigned int maxbps; 63 }; 64 65 /* max. connections to a widget */ 66 #define HDA_MAX_CONNECTIONS 32 67 68 struct hdmi_spec_per_pin { 69 hda_nid_t pin_nid; 70 int dev_id; 71 /* pin idx, different device entries on the same pin use the same idx */ 72 int pin_nid_idx; 73 int num_mux_nids; 74 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; 75 int mux_idx; 76 hda_nid_t cvt_nid; 77 78 struct hda_codec *codec; 79 struct hdmi_eld sink_eld; 80 struct mutex lock; 81 struct delayed_work work; 82 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ 83 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ 84 int prev_pcm_idx; /* previously assigned pcm index */ 85 int repoll_count; 86 bool setup; /* the stream has been set up by prepare callback */ 87 bool silent_stream; 88 int channels; /* current number of channels */ 89 bool non_pcm; 90 bool chmap_set; /* channel-map override by ALSA API? */ 91 unsigned char chmap[8]; /* ALSA API channel-map */ 92 #ifdef CONFIG_SND_PROC_FS 93 struct snd_info_entry *proc_entry; 94 #endif 95 }; 96 97 /* operations used by generic code that can be overridden by patches */ 98 struct hdmi_ops { 99 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, 100 int dev_id, unsigned char *buf, int *eld_size); 101 102 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, 103 int dev_id, 104 int ca, int active_channels, int conn_type); 105 106 /* enable/disable HBR (HD passthrough) */ 107 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, 108 int dev_id, bool hbr); 109 110 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, 111 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 112 int format); 113 114 void (*pin_cvt_fixup)(struct hda_codec *codec, 115 struct hdmi_spec_per_pin *per_pin, 116 hda_nid_t cvt_nid); 117 }; 118 119 struct hdmi_pcm { 120 struct hda_pcm *pcm; 121 struct snd_jack *jack; 122 struct snd_kcontrol *eld_ctl; 123 }; 124 125 enum { 126 SILENT_STREAM_OFF = 0, 127 SILENT_STREAM_KAE, /* use standard HDA Keep-Alive */ 128 SILENT_STREAM_I915, /* Intel i915 extension */ 129 }; 130 131 struct hdmi_spec { 132 struct hda_codec *codec; 133 int num_cvts; 134 struct snd_array cvts; /* struct hdmi_spec_per_cvt */ 135 hda_nid_t cvt_nids[4]; /* only for haswell fix */ 136 137 /* 138 * num_pins is the number of virtual pins 139 * for example, there are 3 pins, and each pin 140 * has 4 device entries, then the num_pins is 12 141 */ 142 int num_pins; 143 /* 144 * num_nids is the number of real pins 145 * In the above example, num_nids is 3 146 */ 147 int num_nids; 148 /* 149 * dev_num is the number of device entries 150 * on each pin. 151 * In the above example, dev_num is 4 152 */ 153 int dev_num; 154 struct snd_array pins; /* struct hdmi_spec_per_pin */ 155 struct hdmi_pcm pcm_rec[8]; 156 struct mutex pcm_lock; 157 struct mutex bind_lock; /* for audio component binding */ 158 /* pcm_bitmap means which pcms have been assigned to pins*/ 159 unsigned long pcm_bitmap; 160 int pcm_used; /* counter of pcm_rec[] */ 161 /* bitmap shows whether the pcm is opened in user space 162 * bit 0 means the first playback PCM (PCM3); 163 * bit 1 means the second playback PCM, and so on. 164 */ 165 unsigned long pcm_in_use; 166 167 struct hdmi_eld temp_eld; 168 struct hdmi_ops ops; 169 170 bool dyn_pin_out; 171 bool static_pcm_mapping; 172 /* hdmi interrupt trigger control flag for Nvidia codec */ 173 bool hdmi_intr_trig_ctrl; 174 bool nv_dp_workaround; /* workaround DP audio infoframe for Nvidia */ 175 176 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */ 177 /* 178 * Non-generic VIA/NVIDIA specific 179 */ 180 struct hda_multi_out multiout; 181 struct hda_pcm_stream pcm_playback; 182 183 bool use_acomp_notifier; /* use eld_notify callback for hotplug */ 184 bool acomp_registered; /* audio component registered in this driver */ 185 bool force_connect; /* force connectivity */ 186 struct drm_audio_component_audio_ops drm_audio_ops; 187 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */ 188 189 struct hdac_chmap chmap; 190 hda_nid_t vendor_nid; 191 const int *port_map; 192 int port_num; 193 int silent_stream_type; 194 }; 195 196 #ifdef CONFIG_SND_HDA_COMPONENT 197 static inline bool codec_has_acomp(struct hda_codec *codec) 198 { 199 struct hdmi_spec *spec = codec->spec; 200 return spec->use_acomp_notifier; 201 } 202 #else 203 #define codec_has_acomp(codec) false 204 #endif 205 206 struct hdmi_audio_infoframe { 207 u8 type; /* 0x84 */ 208 u8 ver; /* 0x01 */ 209 u8 len; /* 0x0a */ 210 211 u8 checksum; 212 213 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ 214 u8 SS01_SF24; 215 u8 CXT04; 216 u8 CA; 217 u8 LFEPBL01_LSV36_DM_INH7; 218 }; 219 220 struct dp_audio_infoframe { 221 u8 type; /* 0x84 */ 222 u8 len; /* 0x1b */ 223 u8 ver; /* 0x11 << 2 */ 224 225 u8 CC02_CT47; /* match with HDMI infoframe from this on */ 226 u8 SS01_SF24; 227 u8 CXT04; 228 u8 CA; 229 u8 LFEPBL01_LSV36_DM_INH7; 230 }; 231 232 union audio_infoframe { 233 struct hdmi_audio_infoframe hdmi; 234 struct dp_audio_infoframe dp; 235 DECLARE_FLEX_ARRAY(u8, bytes); 236 }; 237 238 /* 239 * HDMI routines 240 */ 241 242 #define get_pin(spec, idx) \ 243 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) 244 #define get_cvt(spec, idx) \ 245 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) 246 /* obtain hdmi_pcm object assigned to idx */ 247 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) 248 /* obtain hda_pcm object assigned to idx */ 249 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) 250 251 static int pin_id_to_pin_index(struct hda_codec *codec, 252 hda_nid_t pin_nid, int dev_id) 253 { 254 struct hdmi_spec *spec = codec->spec; 255 int pin_idx; 256 struct hdmi_spec_per_pin *per_pin; 257 258 /* 259 * (dev_id == -1) means it is NON-MST pin 260 * return the first virtual pin on this port 261 */ 262 if (dev_id == -1) 263 dev_id = 0; 264 265 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 266 per_pin = get_pin(spec, pin_idx); 267 if ((per_pin->pin_nid == pin_nid) && 268 (per_pin->dev_id == dev_id)) 269 return pin_idx; 270 } 271 272 codec_warn(codec, "HDMI: pin NID 0x%x not registered\n", pin_nid); 273 return -EINVAL; 274 } 275 276 static int hinfo_to_pcm_index(struct hda_codec *codec, 277 struct hda_pcm_stream *hinfo) 278 { 279 struct hdmi_spec *spec = codec->spec; 280 int pcm_idx; 281 282 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) 283 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) 284 return pcm_idx; 285 286 codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo); 287 return -EINVAL; 288 } 289 290 static int hinfo_to_pin_index(struct hda_codec *codec, 291 struct hda_pcm_stream *hinfo) 292 { 293 struct hdmi_spec *spec = codec->spec; 294 struct hdmi_spec_per_pin *per_pin; 295 int pin_idx; 296 297 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 298 per_pin = get_pin(spec, pin_idx); 299 if (per_pin->pcm && 300 per_pin->pcm->pcm->stream == hinfo) 301 return pin_idx; 302 } 303 304 codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo, 305 hinfo_to_pcm_index(codec, hinfo)); 306 return -EINVAL; 307 } 308 309 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, 310 int pcm_idx) 311 { 312 int i; 313 struct hdmi_spec_per_pin *per_pin; 314 315 for (i = 0; i < spec->num_pins; i++) { 316 per_pin = get_pin(spec, i); 317 if (per_pin->pcm_idx == pcm_idx) 318 return per_pin; 319 } 320 return NULL; 321 } 322 323 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) 324 { 325 struct hdmi_spec *spec = codec->spec; 326 int cvt_idx; 327 328 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) 329 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) 330 return cvt_idx; 331 332 codec_warn(codec, "HDMI: cvt NID 0x%x not registered\n", cvt_nid); 333 return -EINVAL; 334 } 335 336 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, 337 struct snd_ctl_elem_info *uinfo) 338 { 339 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 340 struct hdmi_spec *spec = codec->spec; 341 struct hdmi_spec_per_pin *per_pin; 342 struct hdmi_eld *eld; 343 int pcm_idx; 344 345 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 346 347 pcm_idx = kcontrol->private_value; 348 mutex_lock(&spec->pcm_lock); 349 per_pin = pcm_idx_to_pin(spec, pcm_idx); 350 if (!per_pin) { 351 /* no pin is bound to the pcm */ 352 uinfo->count = 0; 353 goto unlock; 354 } 355 eld = &per_pin->sink_eld; 356 uinfo->count = eld->eld_valid ? eld->eld_size : 0; 357 358 unlock: 359 mutex_unlock(&spec->pcm_lock); 360 return 0; 361 } 362 363 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, 364 struct snd_ctl_elem_value *ucontrol) 365 { 366 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 367 struct hdmi_spec *spec = codec->spec; 368 struct hdmi_spec_per_pin *per_pin; 369 struct hdmi_eld *eld; 370 int pcm_idx; 371 int err = 0; 372 373 pcm_idx = kcontrol->private_value; 374 mutex_lock(&spec->pcm_lock); 375 per_pin = pcm_idx_to_pin(spec, pcm_idx); 376 if (!per_pin) { 377 /* no pin is bound to the pcm */ 378 memset(ucontrol->value.bytes.data, 0, 379 ARRAY_SIZE(ucontrol->value.bytes.data)); 380 goto unlock; 381 } 382 383 eld = &per_pin->sink_eld; 384 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || 385 eld->eld_size > ELD_MAX_SIZE) { 386 snd_BUG(); 387 err = -EINVAL; 388 goto unlock; 389 } 390 391 memset(ucontrol->value.bytes.data, 0, 392 ARRAY_SIZE(ucontrol->value.bytes.data)); 393 if (eld->eld_valid) 394 memcpy(ucontrol->value.bytes.data, eld->eld_buffer, 395 eld->eld_size); 396 397 unlock: 398 mutex_unlock(&spec->pcm_lock); 399 return err; 400 } 401 402 static const struct snd_kcontrol_new eld_bytes_ctl = { 403 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE | 404 SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK, 405 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 406 .name = "ELD", 407 .info = hdmi_eld_ctl_info, 408 .get = hdmi_eld_ctl_get, 409 }; 410 411 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, 412 int device) 413 { 414 struct snd_kcontrol *kctl; 415 struct hdmi_spec *spec = codec->spec; 416 int err; 417 418 kctl = snd_ctl_new1(&eld_bytes_ctl, codec); 419 if (!kctl) 420 return -ENOMEM; 421 kctl->private_value = pcm_idx; 422 kctl->id.device = device; 423 424 /* no pin nid is associated with the kctl now 425 * tbd: associate pin nid to eld ctl later 426 */ 427 err = snd_hda_ctl_add(codec, 0, kctl); 428 if (err < 0) 429 return err; 430 431 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; 432 return 0; 433 } 434 435 #ifdef BE_PARANOID 436 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 437 int *packet_index, int *byte_index) 438 { 439 int val; 440 441 val = snd_hda_codec_read(codec, pin_nid, 0, 442 AC_VERB_GET_HDMI_DIP_INDEX, 0); 443 444 *packet_index = val >> 5; 445 *byte_index = val & 0x1f; 446 } 447 #endif 448 449 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 450 int packet_index, int byte_index) 451 { 452 int val; 453 454 val = (packet_index << 5) | (byte_index & 0x1f); 455 456 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); 457 } 458 459 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, 460 unsigned char val) 461 { 462 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); 463 } 464 465 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) 466 { 467 struct hdmi_spec *spec = codec->spec; 468 int pin_out; 469 470 /* Unmute */ 471 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 472 snd_hda_codec_write(codec, pin_nid, 0, 473 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); 474 475 if (spec->dyn_pin_out) 476 /* Disable pin out until stream is active */ 477 pin_out = 0; 478 else 479 /* Enable pin out: some machines with GM965 gets broken output 480 * when the pin is disabled or changed while using with HDMI 481 */ 482 pin_out = PIN_OUT; 483 484 snd_hda_codec_write(codec, pin_nid, 0, 485 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); 486 } 487 488 /* 489 * ELD proc files 490 */ 491 492 #ifdef CONFIG_SND_PROC_FS 493 static void print_eld_info(struct snd_info_entry *entry, 494 struct snd_info_buffer *buffer) 495 { 496 struct hdmi_spec_per_pin *per_pin = entry->private_data; 497 498 mutex_lock(&per_pin->lock); 499 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer, per_pin->pin_nid, 500 per_pin->dev_id, per_pin->cvt_nid); 501 mutex_unlock(&per_pin->lock); 502 } 503 504 static void write_eld_info(struct snd_info_entry *entry, 505 struct snd_info_buffer *buffer) 506 { 507 struct hdmi_spec_per_pin *per_pin = entry->private_data; 508 509 mutex_lock(&per_pin->lock); 510 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); 511 mutex_unlock(&per_pin->lock); 512 } 513 514 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) 515 { 516 char name[32]; 517 struct hda_codec *codec = per_pin->codec; 518 struct snd_info_entry *entry; 519 int err; 520 521 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); 522 err = snd_card_proc_new(codec->card, name, &entry); 523 if (err < 0) 524 return err; 525 526 snd_info_set_text_ops(entry, per_pin, print_eld_info); 527 entry->c.text.write = write_eld_info; 528 entry->mode |= 0200; 529 per_pin->proc_entry = entry; 530 531 return 0; 532 } 533 534 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 535 { 536 if (!per_pin->codec->bus->shutdown) { 537 snd_info_free_entry(per_pin->proc_entry); 538 per_pin->proc_entry = NULL; 539 } 540 } 541 #else 542 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, 543 int index) 544 { 545 return 0; 546 } 547 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 548 { 549 } 550 #endif 551 552 /* 553 * Audio InfoFrame routines 554 */ 555 556 /* 557 * Enable Audio InfoFrame Transmission 558 */ 559 static void hdmi_start_infoframe_trans(struct hda_codec *codec, 560 hda_nid_t pin_nid) 561 { 562 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 563 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 564 AC_DIPXMIT_BEST); 565 } 566 567 /* 568 * Disable Audio InfoFrame Transmission 569 */ 570 static void hdmi_stop_infoframe_trans(struct hda_codec *codec, 571 hda_nid_t pin_nid) 572 { 573 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 574 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 575 AC_DIPXMIT_DISABLE); 576 } 577 578 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) 579 { 580 #ifdef CONFIG_SND_DEBUG_VERBOSE 581 int i; 582 int size; 583 584 size = snd_hdmi_get_eld_size(codec, pin_nid); 585 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); 586 587 for (i = 0; i < 8; i++) { 588 size = snd_hda_codec_read(codec, pin_nid, 0, 589 AC_VERB_GET_HDMI_DIP_SIZE, i); 590 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); 591 } 592 #endif 593 } 594 595 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) 596 { 597 #ifdef BE_PARANOID 598 int i, j; 599 int size; 600 int pi, bi; 601 for (i = 0; i < 8; i++) { 602 size = snd_hda_codec_read(codec, pin_nid, 0, 603 AC_VERB_GET_HDMI_DIP_SIZE, i); 604 if (size == 0) 605 continue; 606 607 hdmi_set_dip_index(codec, pin_nid, i, 0x0); 608 for (j = 1; j < 1000; j++) { 609 hdmi_write_dip_byte(codec, pin_nid, 0x0); 610 hdmi_get_dip_index(codec, pin_nid, &pi, &bi); 611 if (pi != i) 612 codec_dbg(codec, "dip index %d: %d != %d\n", 613 bi, pi, i); 614 if (bi == 0) /* byte index wrapped around */ 615 break; 616 } 617 codec_dbg(codec, 618 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", 619 i, size, j); 620 } 621 #endif 622 } 623 624 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) 625 { 626 u8 *bytes = (u8 *)hdmi_ai; 627 u8 sum = 0; 628 int i; 629 630 hdmi_ai->checksum = 0; 631 632 for (i = 0; i < sizeof(*hdmi_ai); i++) 633 sum += bytes[i]; 634 635 hdmi_ai->checksum = -sum; 636 } 637 638 static void hdmi_fill_audio_infoframe(struct hda_codec *codec, 639 hda_nid_t pin_nid, 640 u8 *dip, int size) 641 { 642 int i; 643 644 hdmi_debug_dip_size(codec, pin_nid); 645 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ 646 647 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 648 for (i = 0; i < size; i++) 649 hdmi_write_dip_byte(codec, pin_nid, dip[i]); 650 } 651 652 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, 653 u8 *dip, int size) 654 { 655 u8 val; 656 int i; 657 658 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 659 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) 660 != AC_DIPXMIT_BEST) 661 return false; 662 663 for (i = 0; i < size; i++) { 664 val = snd_hda_codec_read(codec, pin_nid, 0, 665 AC_VERB_GET_HDMI_DIP_DATA, 0); 666 if (val != dip[i]) 667 return false; 668 } 669 670 return true; 671 } 672 673 static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 674 int dev_id, unsigned char *buf, int *eld_size) 675 { 676 snd_hda_set_dev_select(codec, nid, dev_id); 677 678 return snd_hdmi_get_eld(codec, nid, buf, eld_size); 679 } 680 681 static void hdmi_pin_setup_infoframe(struct hda_codec *codec, 682 hda_nid_t pin_nid, int dev_id, 683 int ca, int active_channels, 684 int conn_type) 685 { 686 struct hdmi_spec *spec = codec->spec; 687 union audio_infoframe ai; 688 689 memset(&ai, 0, sizeof(ai)); 690 if ((conn_type == 0) || /* HDMI */ 691 /* Nvidia DisplayPort: Nvidia HW expects same layout as HDMI */ 692 (conn_type == 1 && spec->nv_dp_workaround)) { 693 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; 694 695 if (conn_type == 0) { /* HDMI */ 696 hdmi_ai->type = 0x84; 697 hdmi_ai->ver = 0x01; 698 hdmi_ai->len = 0x0a; 699 } else {/* Nvidia DP */ 700 hdmi_ai->type = 0x84; 701 hdmi_ai->ver = 0x1b; 702 hdmi_ai->len = 0x11 << 2; 703 } 704 hdmi_ai->CC02_CT47 = active_channels - 1; 705 hdmi_ai->CA = ca; 706 hdmi_checksum_audio_infoframe(hdmi_ai); 707 } else if (conn_type == 1) { /* DisplayPort */ 708 struct dp_audio_infoframe *dp_ai = &ai.dp; 709 710 dp_ai->type = 0x84; 711 dp_ai->len = 0x1b; 712 dp_ai->ver = 0x11 << 2; 713 dp_ai->CC02_CT47 = active_channels - 1; 714 dp_ai->CA = ca; 715 } else { 716 codec_dbg(codec, "HDMI: unknown connection type at pin NID 0x%x\n", pin_nid); 717 return; 718 } 719 720 snd_hda_set_dev_select(codec, pin_nid, dev_id); 721 722 /* 723 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or 724 * sizeof(*dp_ai) to avoid partial match/update problems when 725 * the user switches between HDMI/DP monitors. 726 */ 727 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, 728 sizeof(ai))) { 729 codec_dbg(codec, "%s: pin NID=0x%x channels=%d ca=0x%02x\n", 730 __func__, pin_nid, active_channels, ca); 731 hdmi_stop_infoframe_trans(codec, pin_nid); 732 hdmi_fill_audio_infoframe(codec, pin_nid, 733 ai.bytes, sizeof(ai)); 734 hdmi_start_infoframe_trans(codec, pin_nid); 735 } 736 } 737 738 static void hdmi_setup_audio_infoframe(struct hda_codec *codec, 739 struct hdmi_spec_per_pin *per_pin, 740 bool non_pcm) 741 { 742 struct hdmi_spec *spec = codec->spec; 743 struct hdac_chmap *chmap = &spec->chmap; 744 hda_nid_t pin_nid = per_pin->pin_nid; 745 int dev_id = per_pin->dev_id; 746 int channels = per_pin->channels; 747 int active_channels; 748 struct hdmi_eld *eld; 749 int ca; 750 751 if (!channels) 752 return; 753 754 snd_hda_set_dev_select(codec, pin_nid, dev_id); 755 756 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ 757 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 758 snd_hda_codec_write(codec, pin_nid, 0, 759 AC_VERB_SET_AMP_GAIN_MUTE, 760 AMP_OUT_UNMUTE); 761 762 eld = &per_pin->sink_eld; 763 764 ca = snd_hdac_channel_allocation(&codec->core, 765 eld->info.spk_alloc, channels, 766 per_pin->chmap_set, non_pcm, per_pin->chmap); 767 768 active_channels = snd_hdac_get_active_channels(ca); 769 770 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, 771 active_channels); 772 773 /* 774 * always configure channel mapping, it may have been changed by the 775 * user in the meantime 776 */ 777 snd_hdac_setup_channel_mapping(&spec->chmap, 778 pin_nid, non_pcm, ca, channels, 779 per_pin->chmap, per_pin->chmap_set); 780 781 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id, 782 ca, active_channels, eld->info.conn_type); 783 784 per_pin->non_pcm = non_pcm; 785 } 786 787 /* 788 * Unsolicited events 789 */ 790 791 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); 792 793 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, 794 int dev_id) 795 { 796 struct hdmi_spec *spec = codec->spec; 797 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); 798 799 if (pin_idx < 0) 800 return; 801 mutex_lock(&spec->pcm_lock); 802 hdmi_present_sense(get_pin(spec, pin_idx), 1); 803 mutex_unlock(&spec->pcm_lock); 804 } 805 806 static void jack_callback(struct hda_codec *codec, 807 struct hda_jack_callback *jack) 808 { 809 /* stop polling when notification is enabled */ 810 if (codec_has_acomp(codec)) 811 return; 812 813 check_presence_and_report(codec, jack->nid, jack->dev_id); 814 } 815 816 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res, 817 struct hda_jack_tbl *jack) 818 { 819 jack->jack_dirty = 1; 820 821 codec_dbg(codec, 822 "HDMI hot plug event: Codec=%d NID=0x%x Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", 823 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA), 824 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); 825 826 check_presence_and_report(codec, jack->nid, jack->dev_id); 827 } 828 829 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) 830 { 831 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 832 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 833 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); 834 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); 835 836 codec_info(codec, 837 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", 838 codec->addr, 839 tag, 840 subtag, 841 cp_state, 842 cp_ready); 843 844 /* TODO */ 845 if (cp_state) { 846 ; 847 } 848 if (cp_ready) { 849 ; 850 } 851 } 852 853 854 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) 855 { 856 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 857 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 858 struct hda_jack_tbl *jack; 859 860 if (codec_has_acomp(codec)) 861 return; 862 863 if (codec->dp_mst) { 864 int dev_entry = 865 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 866 867 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry); 868 } else { 869 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0); 870 } 871 872 if (!jack) { 873 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); 874 return; 875 } 876 877 if (subtag == 0) 878 hdmi_intrinsic_event(codec, res, jack); 879 else 880 hdmi_non_intrinsic_event(codec, res); 881 } 882 883 static void haswell_verify_D0(struct hda_codec *codec, 884 hda_nid_t cvt_nid, hda_nid_t nid) 885 { 886 int pwr; 887 888 /* For Haswell, the converter 1/2 may keep in D3 state after bootup, 889 * thus pins could only choose converter 0 for use. Make sure the 890 * converters are in correct power state */ 891 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) 892 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); 893 894 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { 895 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, 896 AC_PWRST_D0); 897 msleep(40); 898 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); 899 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; 900 codec_dbg(codec, "Haswell HDMI audio: Power for NID 0x%x is now D%d\n", nid, pwr); 901 } 902 } 903 904 /* 905 * Callbacks 906 */ 907 908 /* HBR should be Non-PCM, 8 channels */ 909 #define is_hbr_format(format) \ 910 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) 911 912 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 913 int dev_id, bool hbr) 914 { 915 int pinctl, new_pinctl; 916 917 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { 918 snd_hda_set_dev_select(codec, pin_nid, dev_id); 919 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 920 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 921 922 if (pinctl < 0) 923 return hbr ? -EINVAL : 0; 924 925 new_pinctl = pinctl & ~AC_PINCTL_EPT; 926 if (hbr) 927 new_pinctl |= AC_PINCTL_EPT_HBR; 928 else 929 new_pinctl |= AC_PINCTL_EPT_NATIVE; 930 931 codec_dbg(codec, 932 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", 933 pin_nid, 934 pinctl == new_pinctl ? "" : "new-", 935 new_pinctl); 936 937 if (pinctl != new_pinctl) 938 snd_hda_codec_write(codec, pin_nid, 0, 939 AC_VERB_SET_PIN_WIDGET_CONTROL, 940 new_pinctl); 941 } else if (hbr) 942 return -EINVAL; 943 944 return 0; 945 } 946 947 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 948 hda_nid_t pin_nid, int dev_id, 949 u32 stream_tag, int format) 950 { 951 struct hdmi_spec *spec = codec->spec; 952 unsigned int param; 953 int err; 954 955 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id, 956 is_hbr_format(format)); 957 958 if (err) { 959 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); 960 return err; 961 } 962 963 if (spec->intel_hsw_fixup) { 964 965 /* 966 * on recent platforms IEC Coding Type is required for HBR 967 * support, read current Digital Converter settings and set 968 * ICT bitfield if needed. 969 */ 970 param = snd_hda_codec_read(codec, cvt_nid, 0, 971 AC_VERB_GET_DIGI_CONVERT_1, 0); 972 973 param = (param >> 16) & ~(AC_DIG3_ICT); 974 975 /* on recent platforms ICT mode is required for HBR support */ 976 if (is_hbr_format(format)) 977 param |= 0x1; 978 979 snd_hda_codec_write(codec, cvt_nid, 0, 980 AC_VERB_SET_DIGI_CONVERT_3, param); 981 } 982 983 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); 984 return 0; 985 } 986 987 /* Try to find an available converter 988 * If pin_idx is less then zero, just try to find an available converter. 989 * Otherwise, try to find an available converter and get the cvt mux index 990 * of the pin. 991 */ 992 static int hdmi_choose_cvt(struct hda_codec *codec, 993 int pin_idx, int *cvt_id, 994 bool silent) 995 { 996 struct hdmi_spec *spec = codec->spec; 997 struct hdmi_spec_per_pin *per_pin; 998 struct hdmi_spec_per_cvt *per_cvt = NULL; 999 int cvt_idx, mux_idx = 0; 1000 1001 /* pin_idx < 0 means no pin will be bound to the converter */ 1002 if (pin_idx < 0) 1003 per_pin = NULL; 1004 else 1005 per_pin = get_pin(spec, pin_idx); 1006 1007 if (per_pin && per_pin->silent_stream) { 1008 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid); 1009 per_cvt = get_cvt(spec, cvt_idx); 1010 if (per_cvt->assigned && !silent) 1011 return -EBUSY; 1012 if (cvt_id) 1013 *cvt_id = cvt_idx; 1014 return 0; 1015 } 1016 1017 /* Dynamically assign converter to stream */ 1018 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1019 per_cvt = get_cvt(spec, cvt_idx); 1020 1021 /* Must not already be assigned */ 1022 if (per_cvt->assigned || per_cvt->silent_stream) 1023 continue; 1024 if (per_pin == NULL) 1025 break; 1026 /* Must be in pin's mux's list of converters */ 1027 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1028 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) 1029 break; 1030 /* Not in mux list */ 1031 if (mux_idx == per_pin->num_mux_nids) 1032 continue; 1033 break; 1034 } 1035 1036 /* No free converters */ 1037 if (cvt_idx == spec->num_cvts) 1038 return -EBUSY; 1039 1040 if (per_pin != NULL) 1041 per_pin->mux_idx = mux_idx; 1042 1043 if (cvt_id) 1044 *cvt_id = cvt_idx; 1045 1046 return 0; 1047 } 1048 1049 /* Assure the pin select the right convetor */ 1050 static void intel_verify_pin_cvt_connect(struct hda_codec *codec, 1051 struct hdmi_spec_per_pin *per_pin) 1052 { 1053 hda_nid_t pin_nid = per_pin->pin_nid; 1054 int mux_idx, curr; 1055 1056 mux_idx = per_pin->mux_idx; 1057 curr = snd_hda_codec_read(codec, pin_nid, 0, 1058 AC_VERB_GET_CONNECT_SEL, 0); 1059 if (curr != mux_idx) 1060 snd_hda_codec_write_cache(codec, pin_nid, 0, 1061 AC_VERB_SET_CONNECT_SEL, 1062 mux_idx); 1063 } 1064 1065 /* get the mux index for the converter of the pins 1066 * converter's mux index is the same for all pins on Intel platform 1067 */ 1068 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, 1069 hda_nid_t cvt_nid) 1070 { 1071 int i; 1072 1073 for (i = 0; i < spec->num_cvts; i++) 1074 if (spec->cvt_nids[i] == cvt_nid) 1075 return i; 1076 return -EINVAL; 1077 } 1078 1079 /* Intel HDMI workaround to fix audio routing issue: 1080 * For some Intel display codecs, pins share the same connection list. 1081 * So a conveter can be selected by multiple pins and playback on any of these 1082 * pins will generate sound on the external display, because audio flows from 1083 * the same converter to the display pipeline. Also muting one pin may make 1084 * other pins have no sound output. 1085 * So this function assures that an assigned converter for a pin is not selected 1086 * by any other pins. 1087 */ 1088 static void intel_not_share_assigned_cvt(struct hda_codec *codec, 1089 hda_nid_t pin_nid, 1090 int dev_id, int mux_idx) 1091 { 1092 struct hdmi_spec *spec = codec->spec; 1093 hda_nid_t nid; 1094 int cvt_idx, curr; 1095 struct hdmi_spec_per_cvt *per_cvt; 1096 struct hdmi_spec_per_pin *per_pin; 1097 int pin_idx; 1098 1099 /* configure the pins connections */ 1100 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 1101 int dev_id_saved; 1102 int dev_num; 1103 1104 per_pin = get_pin(spec, pin_idx); 1105 /* 1106 * pin not connected to monitor 1107 * no need to operate on it 1108 */ 1109 if (!per_pin->pcm) 1110 continue; 1111 1112 if ((per_pin->pin_nid == pin_nid) && 1113 (per_pin->dev_id == dev_id)) 1114 continue; 1115 1116 /* 1117 * if per_pin->dev_id >= dev_num, 1118 * snd_hda_get_dev_select() will fail, 1119 * and the following operation is unpredictable. 1120 * So skip this situation. 1121 */ 1122 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; 1123 if (per_pin->dev_id >= dev_num) 1124 continue; 1125 1126 nid = per_pin->pin_nid; 1127 1128 /* 1129 * Calling this function should not impact 1130 * on the device entry selection 1131 * So let's save the dev id for each pin, 1132 * and restore it when return 1133 */ 1134 dev_id_saved = snd_hda_get_dev_select(codec, nid); 1135 snd_hda_set_dev_select(codec, nid, per_pin->dev_id); 1136 curr = snd_hda_codec_read(codec, nid, 0, 1137 AC_VERB_GET_CONNECT_SEL, 0); 1138 if (curr != mux_idx) { 1139 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1140 continue; 1141 } 1142 1143 1144 /* choose an unassigned converter. The conveters in the 1145 * connection list are in the same order as in the codec. 1146 */ 1147 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1148 per_cvt = get_cvt(spec, cvt_idx); 1149 if (!per_cvt->assigned) { 1150 codec_dbg(codec, 1151 "choose cvt %d for pin NID 0x%x\n", 1152 cvt_idx, nid); 1153 snd_hda_codec_write_cache(codec, nid, 0, 1154 AC_VERB_SET_CONNECT_SEL, 1155 cvt_idx); 1156 break; 1157 } 1158 } 1159 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1160 } 1161 } 1162 1163 /* A wrapper of intel_not_share_asigned_cvt() */ 1164 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, 1165 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) 1166 { 1167 int mux_idx; 1168 struct hdmi_spec *spec = codec->spec; 1169 1170 /* On Intel platform, the mapping of converter nid to 1171 * mux index of the pins are always the same. 1172 * The pin nid may be 0, this means all pins will not 1173 * share the converter. 1174 */ 1175 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); 1176 if (mux_idx >= 0) 1177 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); 1178 } 1179 1180 /* skeleton caller of pin_cvt_fixup ops */ 1181 static void pin_cvt_fixup(struct hda_codec *codec, 1182 struct hdmi_spec_per_pin *per_pin, 1183 hda_nid_t cvt_nid) 1184 { 1185 struct hdmi_spec *spec = codec->spec; 1186 1187 if (spec->ops.pin_cvt_fixup) 1188 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); 1189 } 1190 1191 /* called in hdmi_pcm_open when no pin is assigned to the PCM */ 1192 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, 1193 struct hda_codec *codec, 1194 struct snd_pcm_substream *substream) 1195 { 1196 struct hdmi_spec *spec = codec->spec; 1197 struct snd_pcm_runtime *runtime = substream->runtime; 1198 int cvt_idx, pcm_idx; 1199 struct hdmi_spec_per_cvt *per_cvt = NULL; 1200 int err; 1201 1202 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1203 if (pcm_idx < 0) 1204 return -EINVAL; 1205 1206 err = hdmi_choose_cvt(codec, -1, &cvt_idx, false); 1207 if (err) 1208 return err; 1209 1210 per_cvt = get_cvt(spec, cvt_idx); 1211 per_cvt->assigned = true; 1212 hinfo->nid = per_cvt->cvt_nid; 1213 1214 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); 1215 1216 set_bit(pcm_idx, &spec->pcm_in_use); 1217 /* todo: setup spdif ctls assign */ 1218 1219 /* Initially set the converter's capabilities */ 1220 hinfo->channels_min = per_cvt->channels_min; 1221 hinfo->channels_max = per_cvt->channels_max; 1222 hinfo->rates = per_cvt->rates; 1223 hinfo->formats = per_cvt->formats; 1224 hinfo->maxbps = per_cvt->maxbps; 1225 1226 /* Store the updated parameters */ 1227 runtime->hw.channels_min = hinfo->channels_min; 1228 runtime->hw.channels_max = hinfo->channels_max; 1229 runtime->hw.formats = hinfo->formats; 1230 runtime->hw.rates = hinfo->rates; 1231 1232 snd_pcm_hw_constraint_step(substream->runtime, 0, 1233 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1234 return 0; 1235 } 1236 1237 /* 1238 * HDA PCM callbacks 1239 */ 1240 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, 1241 struct hda_codec *codec, 1242 struct snd_pcm_substream *substream) 1243 { 1244 struct hdmi_spec *spec = codec->spec; 1245 struct snd_pcm_runtime *runtime = substream->runtime; 1246 int pin_idx, cvt_idx, pcm_idx; 1247 struct hdmi_spec_per_pin *per_pin; 1248 struct hdmi_eld *eld; 1249 struct hdmi_spec_per_cvt *per_cvt = NULL; 1250 int err; 1251 1252 /* Validate hinfo */ 1253 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1254 if (pcm_idx < 0) 1255 return -EINVAL; 1256 1257 mutex_lock(&spec->pcm_lock); 1258 pin_idx = hinfo_to_pin_index(codec, hinfo); 1259 /* no pin is assigned to the PCM 1260 * PA need pcm open successfully when probe 1261 */ 1262 if (pin_idx < 0) { 1263 err = hdmi_pcm_open_no_pin(hinfo, codec, substream); 1264 goto unlock; 1265 } 1266 1267 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, false); 1268 if (err < 0) 1269 goto unlock; 1270 1271 per_cvt = get_cvt(spec, cvt_idx); 1272 /* Claim converter */ 1273 per_cvt->assigned = true; 1274 1275 set_bit(pcm_idx, &spec->pcm_in_use); 1276 per_pin = get_pin(spec, pin_idx); 1277 per_pin->cvt_nid = per_cvt->cvt_nid; 1278 hinfo->nid = per_cvt->cvt_nid; 1279 1280 /* flip stripe flag for the assigned stream if supported */ 1281 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE) 1282 azx_stream(get_azx_dev(substream))->stripe = 1; 1283 1284 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1285 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1286 AC_VERB_SET_CONNECT_SEL, 1287 per_pin->mux_idx); 1288 1289 /* configure unused pins to choose other converters */ 1290 pin_cvt_fixup(codec, per_pin, 0); 1291 1292 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); 1293 1294 /* Initially set the converter's capabilities */ 1295 hinfo->channels_min = per_cvt->channels_min; 1296 hinfo->channels_max = per_cvt->channels_max; 1297 hinfo->rates = per_cvt->rates; 1298 hinfo->formats = per_cvt->formats; 1299 hinfo->maxbps = per_cvt->maxbps; 1300 1301 eld = &per_pin->sink_eld; 1302 /* Restrict capabilities by ELD if this isn't disabled */ 1303 if (!static_hdmi_pcm && eld->eld_valid) { 1304 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); 1305 if (hinfo->channels_min > hinfo->channels_max || 1306 !hinfo->rates || !hinfo->formats) { 1307 per_cvt->assigned = false; 1308 hinfo->nid = 0; 1309 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1310 err = -ENODEV; 1311 goto unlock; 1312 } 1313 } 1314 1315 /* Store the updated parameters */ 1316 runtime->hw.channels_min = hinfo->channels_min; 1317 runtime->hw.channels_max = hinfo->channels_max; 1318 runtime->hw.formats = hinfo->formats; 1319 runtime->hw.rates = hinfo->rates; 1320 1321 snd_pcm_hw_constraint_step(substream->runtime, 0, 1322 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1323 unlock: 1324 mutex_unlock(&spec->pcm_lock); 1325 return err; 1326 } 1327 1328 /* 1329 * HDA/HDMI auto parsing 1330 */ 1331 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) 1332 { 1333 struct hdmi_spec *spec = codec->spec; 1334 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1335 hda_nid_t pin_nid = per_pin->pin_nid; 1336 int dev_id = per_pin->dev_id; 1337 int conns; 1338 1339 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { 1340 codec_warn(codec, 1341 "HDMI: pin NID 0x%x wcaps %#x does not support connection list\n", 1342 pin_nid, get_wcaps(codec, pin_nid)); 1343 return -EINVAL; 1344 } 1345 1346 snd_hda_set_dev_select(codec, pin_nid, dev_id); 1347 1348 if (spec->intel_hsw_fixup) { 1349 conns = spec->num_cvts; 1350 memcpy(per_pin->mux_nids, spec->cvt_nids, 1351 sizeof(hda_nid_t) * conns); 1352 } else { 1353 conns = snd_hda_get_raw_connections(codec, pin_nid, 1354 per_pin->mux_nids, 1355 HDA_MAX_CONNECTIONS); 1356 } 1357 1358 /* all the device entries on the same pin have the same conn list */ 1359 per_pin->num_mux_nids = conns; 1360 1361 return 0; 1362 } 1363 1364 static int hdmi_find_pcm_slot(struct hdmi_spec *spec, 1365 struct hdmi_spec_per_pin *per_pin) 1366 { 1367 int i; 1368 1369 for (i = 0; i < spec->pcm_used; i++) { 1370 if (!test_bit(i, &spec->pcm_bitmap)) 1371 return i; 1372 } 1373 return -EBUSY; 1374 } 1375 1376 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, 1377 struct hdmi_spec_per_pin *per_pin) 1378 { 1379 int idx; 1380 1381 /* pcm already be attached to the pin */ 1382 if (per_pin->pcm) 1383 return; 1384 /* try the previously used slot at first */ 1385 idx = per_pin->prev_pcm_idx; 1386 if (idx >= 0) { 1387 if (!test_bit(idx, &spec->pcm_bitmap)) 1388 goto found; 1389 per_pin->prev_pcm_idx = -1; /* no longer valid, clear it */ 1390 } 1391 idx = hdmi_find_pcm_slot(spec, per_pin); 1392 if (idx == -EBUSY) 1393 return; 1394 found: 1395 per_pin->pcm_idx = idx; 1396 per_pin->pcm = get_hdmi_pcm(spec, idx); 1397 set_bit(idx, &spec->pcm_bitmap); 1398 } 1399 1400 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, 1401 struct hdmi_spec_per_pin *per_pin) 1402 { 1403 int idx; 1404 1405 /* pcm already be detached from the pin */ 1406 if (!per_pin->pcm) 1407 return; 1408 idx = per_pin->pcm_idx; 1409 per_pin->pcm_idx = -1; 1410 per_pin->prev_pcm_idx = idx; /* remember the previous index */ 1411 per_pin->pcm = NULL; 1412 if (idx >= 0 && idx < spec->pcm_used) 1413 clear_bit(idx, &spec->pcm_bitmap); 1414 } 1415 1416 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, 1417 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) 1418 { 1419 int mux_idx; 1420 1421 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1422 if (per_pin->mux_nids[mux_idx] == cvt_nid) 1423 break; 1424 return mux_idx; 1425 } 1426 1427 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); 1428 1429 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, 1430 struct hdmi_spec_per_pin *per_pin) 1431 { 1432 struct hda_codec *codec = per_pin->codec; 1433 struct hda_pcm *pcm; 1434 struct hda_pcm_stream *hinfo; 1435 struct snd_pcm_substream *substream; 1436 int mux_idx; 1437 bool non_pcm; 1438 1439 if (per_pin->pcm_idx < 0 || per_pin->pcm_idx >= spec->pcm_used) 1440 return; 1441 pcm = get_pcm_rec(spec, per_pin->pcm_idx); 1442 if (!pcm->pcm) 1443 return; 1444 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) 1445 return; 1446 1447 /* hdmi audio only uses playback and one substream */ 1448 hinfo = pcm->stream; 1449 substream = pcm->pcm->streams[0].substream; 1450 1451 per_pin->cvt_nid = hinfo->nid; 1452 1453 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); 1454 if (mux_idx < per_pin->num_mux_nids) { 1455 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1456 per_pin->dev_id); 1457 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1458 AC_VERB_SET_CONNECT_SEL, 1459 mux_idx); 1460 } 1461 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); 1462 1463 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); 1464 if (substream->runtime) 1465 per_pin->channels = substream->runtime->channels; 1466 per_pin->setup = true; 1467 per_pin->mux_idx = mux_idx; 1468 1469 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1470 } 1471 1472 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, 1473 struct hdmi_spec_per_pin *per_pin) 1474 { 1475 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1476 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); 1477 1478 per_pin->chmap_set = false; 1479 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1480 1481 per_pin->setup = false; 1482 per_pin->channels = 0; 1483 } 1484 1485 static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec, 1486 struct hdmi_spec_per_pin *per_pin) 1487 { 1488 struct hdmi_spec *spec = codec->spec; 1489 1490 if (per_pin->pcm_idx >= 0) 1491 return spec->pcm_rec[per_pin->pcm_idx].jack; 1492 else 1493 return NULL; 1494 } 1495 1496 /* update per_pin ELD from the given new ELD; 1497 * setup info frame and notification accordingly 1498 * also notify ELD kctl and report jack status changes 1499 */ 1500 static void update_eld(struct hda_codec *codec, 1501 struct hdmi_spec_per_pin *per_pin, 1502 struct hdmi_eld *eld, 1503 int repoll) 1504 { 1505 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 1506 struct hdmi_spec *spec = codec->spec; 1507 struct snd_jack *pcm_jack; 1508 bool old_eld_valid = pin_eld->eld_valid; 1509 bool eld_changed; 1510 int pcm_idx; 1511 1512 if (eld->eld_valid) { 1513 if (eld->eld_size <= 0 || 1514 snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, 1515 eld->eld_size) < 0) { 1516 eld->eld_valid = false; 1517 if (repoll) { 1518 schedule_delayed_work(&per_pin->work, 1519 msecs_to_jiffies(300)); 1520 return; 1521 } 1522 } 1523 } 1524 1525 if (!eld->eld_valid || eld->eld_size <= 0 || eld->info.sad_count <= 0) { 1526 eld->eld_valid = false; 1527 eld->eld_size = 0; 1528 } 1529 1530 /* for monitor disconnection, save pcm_idx firstly */ 1531 pcm_idx = per_pin->pcm_idx; 1532 1533 /* 1534 * pcm_idx >=0 before update_eld() means it is in monitor 1535 * disconnected event. Jack must be fetched before update_eld(). 1536 */ 1537 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); 1538 1539 if (!spec->static_pcm_mapping) { 1540 if (eld->eld_valid) { 1541 hdmi_attach_hda_pcm(spec, per_pin); 1542 hdmi_pcm_setup_pin(spec, per_pin); 1543 } else { 1544 hdmi_pcm_reset_pin(spec, per_pin); 1545 hdmi_detach_hda_pcm(spec, per_pin); 1546 } 1547 } 1548 1549 /* if pcm_idx == -1, it means this is in monitor connection event 1550 * we can get the correct pcm_idx now. 1551 */ 1552 if (pcm_idx == -1) 1553 pcm_idx = per_pin->pcm_idx; 1554 if (!pcm_jack) 1555 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); 1556 1557 if (eld->eld_valid) 1558 snd_hdmi_show_eld(codec, &eld->info); 1559 1560 eld_changed = (pin_eld->eld_valid != eld->eld_valid); 1561 eld_changed |= (pin_eld->monitor_present != eld->monitor_present); 1562 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid) 1563 if (pin_eld->eld_size != eld->eld_size || 1564 memcmp(pin_eld->eld_buffer, eld->eld_buffer, 1565 eld->eld_size) != 0) 1566 eld_changed = true; 1567 1568 if (eld_changed) { 1569 pin_eld->monitor_present = eld->monitor_present; 1570 pin_eld->eld_valid = eld->eld_valid; 1571 pin_eld->eld_size = eld->eld_size; 1572 if (eld->eld_valid) 1573 memcpy(pin_eld->eld_buffer, eld->eld_buffer, 1574 eld->eld_size); 1575 pin_eld->info = eld->info; 1576 } 1577 1578 /* 1579 * Re-setup pin and infoframe. This is needed e.g. when 1580 * - sink is first plugged-in 1581 * - transcoder can change during stream playback on Haswell 1582 * and this can make HW reset converter selection on a pin. 1583 */ 1584 if (eld->eld_valid && !old_eld_valid && per_pin->setup) { 1585 pin_cvt_fixup(codec, per_pin, 0); 1586 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1587 } 1588 1589 if (eld_changed && pcm_idx >= 0) 1590 snd_ctl_notify(codec->card, 1591 SNDRV_CTL_EVENT_MASK_VALUE | 1592 SNDRV_CTL_EVENT_MASK_INFO, 1593 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); 1594 1595 if (eld_changed && pcm_jack) 1596 snd_jack_report(pcm_jack, 1597 (eld->monitor_present && eld->eld_valid) ? 1598 SND_JACK_AVOUT : 0); 1599 } 1600 1601 /* update ELD and jack state via HD-audio verbs */ 1602 static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, 1603 int repoll) 1604 { 1605 struct hda_codec *codec = per_pin->codec; 1606 struct hdmi_spec *spec = codec->spec; 1607 struct hdmi_eld *eld = &spec->temp_eld; 1608 struct device *dev = hda_codec_dev(codec); 1609 hda_nid_t pin_nid = per_pin->pin_nid; 1610 int dev_id = per_pin->dev_id; 1611 /* 1612 * Always execute a GetPinSense verb here, even when called from 1613 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited 1614 * response's PD bit is not the real PD value, but indicates that 1615 * the real PD value changed. An older version of the HD-audio 1616 * specification worked this way. Hence, we just ignore the data in 1617 * the unsolicited response to avoid custom WARs. 1618 */ 1619 int present; 1620 int ret; 1621 1622 #ifdef CONFIG_PM 1623 if (dev->power.runtime_status == RPM_SUSPENDING) 1624 return; 1625 #endif 1626 1627 ret = snd_hda_power_up_pm(codec); 1628 if (ret < 0 && pm_runtime_suspended(dev)) 1629 goto out; 1630 1631 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id); 1632 1633 mutex_lock(&per_pin->lock); 1634 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); 1635 if (eld->monitor_present) 1636 eld->eld_valid = !!(present & AC_PINSENSE_ELDV); 1637 else 1638 eld->eld_valid = false; 1639 1640 codec_dbg(codec, 1641 "HDMI status: Codec=%d NID=0x%x Presence_Detect=%d ELD_Valid=%d\n", 1642 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); 1643 1644 if (eld->eld_valid) { 1645 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id, 1646 eld->eld_buffer, &eld->eld_size) < 0) 1647 eld->eld_valid = false; 1648 } 1649 1650 update_eld(codec, per_pin, eld, repoll); 1651 mutex_unlock(&per_pin->lock); 1652 out: 1653 snd_hda_power_down_pm(codec); 1654 } 1655 1656 #define I915_SILENT_RATE 48000 1657 #define I915_SILENT_CHANNELS 2 1658 #define I915_SILENT_FORMAT SNDRV_PCM_FORMAT_S16_LE 1659 #define I915_SILENT_FORMAT_BITS 16 1660 #define I915_SILENT_FMT_MASK 0xf 1661 1662 static void silent_stream_enable_i915(struct hda_codec *codec, 1663 struct hdmi_spec_per_pin *per_pin) 1664 { 1665 unsigned int format; 1666 1667 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, 1668 per_pin->dev_id, I915_SILENT_RATE); 1669 1670 /* trigger silent stream generation in hw */ 1671 format = snd_hdac_calc_stream_format(I915_SILENT_RATE, I915_SILENT_CHANNELS, 1672 I915_SILENT_FORMAT, I915_SILENT_FORMAT_BITS, 0); 1673 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, 1674 I915_SILENT_FMT_MASK, I915_SILENT_FMT_MASK, format); 1675 usleep_range(100, 200); 1676 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, I915_SILENT_FMT_MASK, 0, format); 1677 1678 per_pin->channels = I915_SILENT_CHANNELS; 1679 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1680 } 1681 1682 static void silent_stream_set_kae(struct hda_codec *codec, 1683 struct hdmi_spec_per_pin *per_pin, 1684 bool enable) 1685 { 1686 unsigned int param; 1687 1688 codec_dbg(codec, "HDMI: KAE %d cvt-NID=0x%x\n", enable, per_pin->cvt_nid); 1689 1690 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, AC_VERB_GET_DIGI_CONVERT_1, 0); 1691 param = (param >> 16) & 0xff; 1692 1693 if (enable) 1694 param |= AC_DIG3_KAE; 1695 else 1696 param &= ~AC_DIG3_KAE; 1697 1698 snd_hda_codec_write(codec, per_pin->cvt_nid, 0, AC_VERB_SET_DIGI_CONVERT_3, param); 1699 } 1700 1701 static void silent_stream_enable(struct hda_codec *codec, 1702 struct hdmi_spec_per_pin *per_pin) 1703 { 1704 struct hdmi_spec *spec = codec->spec; 1705 struct hdmi_spec_per_cvt *per_cvt; 1706 int cvt_idx, pin_idx, err; 1707 int keep_power = 0; 1708 1709 /* 1710 * Power-up will call hdmi_present_sense, so the PM calls 1711 * have to be done without mutex held. 1712 */ 1713 1714 err = snd_hda_power_up_pm(codec); 1715 if (err < 0 && err != -EACCES) { 1716 codec_err(codec, 1717 "Failed to power up codec for silent stream enable ret=[%d]\n", err); 1718 snd_hda_power_down_pm(codec); 1719 return; 1720 } 1721 1722 mutex_lock(&per_pin->lock); 1723 1724 if (per_pin->setup) { 1725 codec_dbg(codec, "hdmi: PCM already open, no silent stream\n"); 1726 err = -EBUSY; 1727 goto unlock_out; 1728 } 1729 1730 pin_idx = pin_id_to_pin_index(codec, per_pin->pin_nid, per_pin->dev_id); 1731 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, true); 1732 if (err) { 1733 codec_err(codec, "hdmi: no free converter to enable silent mode\n"); 1734 goto unlock_out; 1735 } 1736 1737 per_cvt = get_cvt(spec, cvt_idx); 1738 per_cvt->silent_stream = true; 1739 per_pin->cvt_nid = per_cvt->cvt_nid; 1740 per_pin->silent_stream = true; 1741 1742 codec_dbg(codec, "hdmi: enabling silent stream pin-NID=0x%x cvt-NID=0x%x\n", 1743 per_pin->pin_nid, per_cvt->cvt_nid); 1744 1745 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1746 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1747 AC_VERB_SET_CONNECT_SEL, 1748 per_pin->mux_idx); 1749 1750 /* configure unused pins to choose other converters */ 1751 pin_cvt_fixup(codec, per_pin, 0); 1752 1753 switch (spec->silent_stream_type) { 1754 case SILENT_STREAM_KAE: 1755 silent_stream_enable_i915(codec, per_pin); 1756 silent_stream_set_kae(codec, per_pin, true); 1757 break; 1758 case SILENT_STREAM_I915: 1759 silent_stream_enable_i915(codec, per_pin); 1760 keep_power = 1; 1761 break; 1762 default: 1763 break; 1764 } 1765 1766 unlock_out: 1767 mutex_unlock(&per_pin->lock); 1768 1769 if (err || !keep_power) 1770 snd_hda_power_down_pm(codec); 1771 } 1772 1773 static void silent_stream_disable(struct hda_codec *codec, 1774 struct hdmi_spec_per_pin *per_pin) 1775 { 1776 struct hdmi_spec *spec = codec->spec; 1777 struct hdmi_spec_per_cvt *per_cvt; 1778 int cvt_idx, err; 1779 1780 err = snd_hda_power_up_pm(codec); 1781 if (err < 0 && err != -EACCES) { 1782 codec_err(codec, 1783 "Failed to power up codec for silent stream disable ret=[%d]\n", 1784 err); 1785 snd_hda_power_down_pm(codec); 1786 return; 1787 } 1788 1789 mutex_lock(&per_pin->lock); 1790 if (!per_pin->silent_stream) 1791 goto unlock_out; 1792 1793 codec_dbg(codec, "HDMI: disable silent stream on pin-NID=0x%x cvt-NID=0x%x\n", 1794 per_pin->pin_nid, per_pin->cvt_nid); 1795 1796 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid); 1797 if (cvt_idx >= 0 && cvt_idx < spec->num_cvts) { 1798 per_cvt = get_cvt(spec, cvt_idx); 1799 per_cvt->silent_stream = false; 1800 } 1801 1802 if (spec->silent_stream_type == SILENT_STREAM_I915) { 1803 /* release ref taken in silent_stream_enable() */ 1804 snd_hda_power_down_pm(codec); 1805 } else if (spec->silent_stream_type == SILENT_STREAM_KAE) { 1806 silent_stream_set_kae(codec, per_pin, false); 1807 } 1808 1809 per_pin->cvt_nid = 0; 1810 per_pin->silent_stream = false; 1811 1812 unlock_out: 1813 mutex_unlock(&per_pin->lock); 1814 1815 snd_hda_power_down_pm(codec); 1816 } 1817 1818 /* update ELD and jack state via audio component */ 1819 static void sync_eld_via_acomp(struct hda_codec *codec, 1820 struct hdmi_spec_per_pin *per_pin) 1821 { 1822 struct hdmi_spec *spec = codec->spec; 1823 struct hdmi_eld *eld = &spec->temp_eld; 1824 bool monitor_prev, monitor_next; 1825 1826 mutex_lock(&per_pin->lock); 1827 eld->monitor_present = false; 1828 monitor_prev = per_pin->sink_eld.monitor_present; 1829 eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, 1830 per_pin->dev_id, &eld->monitor_present, 1831 eld->eld_buffer, ELD_MAX_SIZE); 1832 eld->eld_valid = (eld->eld_size > 0); 1833 update_eld(codec, per_pin, eld, 0); 1834 monitor_next = per_pin->sink_eld.monitor_present; 1835 mutex_unlock(&per_pin->lock); 1836 1837 if (spec->silent_stream_type) { 1838 if (!monitor_prev && monitor_next) 1839 silent_stream_enable(codec, per_pin); 1840 else if (monitor_prev && !monitor_next) 1841 silent_stream_disable(codec, per_pin); 1842 } 1843 } 1844 1845 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) 1846 { 1847 struct hda_codec *codec = per_pin->codec; 1848 1849 if (!codec_has_acomp(codec)) 1850 hdmi_present_sense_via_verbs(per_pin, repoll); 1851 else 1852 sync_eld_via_acomp(codec, per_pin); 1853 } 1854 1855 static void hdmi_repoll_eld(struct work_struct *work) 1856 { 1857 struct hdmi_spec_per_pin *per_pin = 1858 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); 1859 struct hda_codec *codec = per_pin->codec; 1860 struct hdmi_spec *spec = codec->spec; 1861 struct hda_jack_tbl *jack; 1862 1863 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid, 1864 per_pin->dev_id); 1865 if (jack) 1866 jack->jack_dirty = 1; 1867 1868 if (per_pin->repoll_count++ > 6) 1869 per_pin->repoll_count = 0; 1870 1871 mutex_lock(&spec->pcm_lock); 1872 hdmi_present_sense(per_pin, per_pin->repoll_count); 1873 mutex_unlock(&spec->pcm_lock); 1874 } 1875 1876 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) 1877 { 1878 struct hdmi_spec *spec = codec->spec; 1879 unsigned int caps, config; 1880 int pin_idx; 1881 struct hdmi_spec_per_pin *per_pin; 1882 int err; 1883 int dev_num, i; 1884 1885 caps = snd_hda_query_pin_caps(codec, pin_nid); 1886 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) 1887 return 0; 1888 1889 /* 1890 * For DP MST audio, Configuration Default is the same for 1891 * all device entries on the same pin 1892 */ 1893 config = snd_hda_codec_get_pincfg(codec, pin_nid); 1894 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE && 1895 !spec->force_connect) 1896 return 0; 1897 1898 /* 1899 * To simplify the implementation, malloc all 1900 * the virtual pins in the initialization statically 1901 */ 1902 if (spec->intel_hsw_fixup) { 1903 /* 1904 * On Intel platforms, device entries count returned 1905 * by AC_PAR_DEVLIST_LEN is dynamic, and depends on 1906 * the type of receiver that is connected. Allocate pin 1907 * structures based on worst case. 1908 */ 1909 dev_num = spec->dev_num; 1910 } else if (codec->dp_mst) { 1911 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; 1912 /* 1913 * spec->dev_num is the maxinum number of device entries 1914 * among all the pins 1915 */ 1916 spec->dev_num = (spec->dev_num > dev_num) ? 1917 spec->dev_num : dev_num; 1918 } else { 1919 /* 1920 * If the platform doesn't support DP MST, 1921 * manually set dev_num to 1. This means 1922 * the pin has only one device entry. 1923 */ 1924 dev_num = 1; 1925 spec->dev_num = 1; 1926 } 1927 1928 for (i = 0; i < dev_num; i++) { 1929 pin_idx = spec->num_pins; 1930 per_pin = snd_array_new(&spec->pins); 1931 1932 if (!per_pin) 1933 return -ENOMEM; 1934 1935 per_pin->pcm = NULL; 1936 per_pin->pcm_idx = -1; 1937 per_pin->prev_pcm_idx = -1; 1938 per_pin->pin_nid = pin_nid; 1939 per_pin->pin_nid_idx = spec->num_nids; 1940 per_pin->dev_id = i; 1941 per_pin->non_pcm = false; 1942 snd_hda_set_dev_select(codec, pin_nid, i); 1943 err = hdmi_read_pin_conn(codec, pin_idx); 1944 if (err < 0) 1945 return err; 1946 if (!is_jack_detectable(codec, pin_nid)) 1947 codec_warn(codec, "HDMI: pin NID 0x%x - jack not detectable\n", pin_nid); 1948 spec->num_pins++; 1949 } 1950 spec->num_nids++; 1951 1952 return 0; 1953 } 1954 1955 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1956 { 1957 struct hdmi_spec *spec = codec->spec; 1958 struct hdmi_spec_per_cvt *per_cvt; 1959 unsigned int chans; 1960 int err; 1961 1962 chans = get_wcaps(codec, cvt_nid); 1963 chans = get_wcaps_channels(chans); 1964 1965 per_cvt = snd_array_new(&spec->cvts); 1966 if (!per_cvt) 1967 return -ENOMEM; 1968 1969 per_cvt->cvt_nid = cvt_nid; 1970 per_cvt->channels_min = 2; 1971 if (chans <= 16) { 1972 per_cvt->channels_max = chans; 1973 if (chans > spec->chmap.channels_max) 1974 spec->chmap.channels_max = chans; 1975 } 1976 1977 err = snd_hda_query_supported_pcm(codec, cvt_nid, 1978 &per_cvt->rates, 1979 &per_cvt->formats, 1980 &per_cvt->maxbps); 1981 if (err < 0) 1982 return err; 1983 1984 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) 1985 spec->cvt_nids[spec->num_cvts] = cvt_nid; 1986 spec->num_cvts++; 1987 1988 return 0; 1989 } 1990 1991 static const struct snd_pci_quirk force_connect_list[] = { 1992 SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1), 1993 SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1), 1994 SND_PCI_QUIRK(0x103c, 0x8711, "HP", 1), 1995 SND_PCI_QUIRK(0x103c, 0x8715, "HP", 1), 1996 SND_PCI_QUIRK(0x1462, 0xec94, "MS-7C94", 1), 1997 SND_PCI_QUIRK(0x8086, 0x2081, "Intel NUC 10", 1), 1998 {} 1999 }; 2000 2001 static int hdmi_parse_codec(struct hda_codec *codec) 2002 { 2003 struct hdmi_spec *spec = codec->spec; 2004 hda_nid_t start_nid; 2005 unsigned int caps; 2006 int i, nodes; 2007 const struct snd_pci_quirk *q; 2008 2009 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid); 2010 if (!start_nid || nodes < 0) { 2011 codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); 2012 return -EINVAL; 2013 } 2014 2015 if (enable_all_pins) 2016 spec->force_connect = true; 2017 2018 q = snd_pci_quirk_lookup(codec->bus->pci, force_connect_list); 2019 2020 if (q && q->value) 2021 spec->force_connect = true; 2022 2023 /* 2024 * hdmi_add_pin() assumes total amount of converters to 2025 * be known, so first discover all converters 2026 */ 2027 for (i = 0; i < nodes; i++) { 2028 hda_nid_t nid = start_nid + i; 2029 2030 caps = get_wcaps(codec, nid); 2031 2032 if (!(caps & AC_WCAP_DIGITAL)) 2033 continue; 2034 2035 if (get_wcaps_type(caps) == AC_WID_AUD_OUT) 2036 hdmi_add_cvt(codec, nid); 2037 } 2038 2039 /* discover audio pins */ 2040 for (i = 0; i < nodes; i++) { 2041 hda_nid_t nid = start_nid + i; 2042 2043 caps = get_wcaps(codec, nid); 2044 2045 if (!(caps & AC_WCAP_DIGITAL)) 2046 continue; 2047 2048 if (get_wcaps_type(caps) == AC_WID_PIN) 2049 hdmi_add_pin(codec, nid); 2050 } 2051 2052 return 0; 2053 } 2054 2055 /* 2056 */ 2057 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 2058 { 2059 struct hda_spdif_out *spdif; 2060 bool non_pcm; 2061 2062 mutex_lock(&codec->spdif_mutex); 2063 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); 2064 /* Add sanity check to pass klockwork check. 2065 * This should never happen. 2066 */ 2067 if (WARN_ON(spdif == NULL)) { 2068 mutex_unlock(&codec->spdif_mutex); 2069 return true; 2070 } 2071 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); 2072 mutex_unlock(&codec->spdif_mutex); 2073 return non_pcm; 2074 } 2075 2076 /* 2077 * HDMI callbacks 2078 */ 2079 2080 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 2081 struct hda_codec *codec, 2082 unsigned int stream_tag, 2083 unsigned int format, 2084 struct snd_pcm_substream *substream) 2085 { 2086 hda_nid_t cvt_nid = hinfo->nid; 2087 struct hdmi_spec *spec = codec->spec; 2088 int pin_idx; 2089 struct hdmi_spec_per_pin *per_pin; 2090 struct snd_pcm_runtime *runtime = substream->runtime; 2091 bool non_pcm; 2092 int pinctl, stripe; 2093 int err = 0; 2094 2095 mutex_lock(&spec->pcm_lock); 2096 pin_idx = hinfo_to_pin_index(codec, hinfo); 2097 if (pin_idx < 0) { 2098 /* when pcm is not bound to a pin skip pin setup and return 0 2099 * to make audio playback be ongoing 2100 */ 2101 pin_cvt_fixup(codec, NULL, cvt_nid); 2102 snd_hda_codec_setup_stream(codec, cvt_nid, 2103 stream_tag, 0, format); 2104 goto unlock; 2105 } 2106 2107 if (snd_BUG_ON(pin_idx < 0)) { 2108 err = -EINVAL; 2109 goto unlock; 2110 } 2111 per_pin = get_pin(spec, pin_idx); 2112 2113 /* Verify pin:cvt selections to avoid silent audio after S3. 2114 * After S3, the audio driver restores pin:cvt selections 2115 * but this can happen before gfx is ready and such selection 2116 * is overlooked by HW. Thus multiple pins can share a same 2117 * default convertor and mute control will affect each other, 2118 * which can cause a resumed audio playback become silent 2119 * after S3. 2120 */ 2121 pin_cvt_fixup(codec, per_pin, 0); 2122 2123 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ 2124 /* Todo: add DP1.2 MST audio support later */ 2125 if (codec_has_acomp(codec)) 2126 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, 2127 per_pin->dev_id, runtime->rate); 2128 2129 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); 2130 mutex_lock(&per_pin->lock); 2131 per_pin->channels = substream->runtime->channels; 2132 per_pin->setup = true; 2133 2134 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) { 2135 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core, 2136 substream); 2137 snd_hda_codec_write(codec, cvt_nid, 0, 2138 AC_VERB_SET_STRIPE_CONTROL, 2139 stripe); 2140 } 2141 2142 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 2143 mutex_unlock(&per_pin->lock); 2144 if (spec->dyn_pin_out) { 2145 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2146 per_pin->dev_id); 2147 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2148 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2149 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2150 AC_VERB_SET_PIN_WIDGET_CONTROL, 2151 pinctl | PIN_OUT); 2152 } 2153 2154 /* snd_hda_set_dev_select() has been called before */ 2155 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid, 2156 per_pin->dev_id, stream_tag, format); 2157 unlock: 2158 mutex_unlock(&spec->pcm_lock); 2159 return err; 2160 } 2161 2162 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 2163 struct hda_codec *codec, 2164 struct snd_pcm_substream *substream) 2165 { 2166 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 2167 return 0; 2168 } 2169 2170 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, 2171 struct hda_codec *codec, 2172 struct snd_pcm_substream *substream) 2173 { 2174 struct hdmi_spec *spec = codec->spec; 2175 int cvt_idx, pin_idx, pcm_idx; 2176 struct hdmi_spec_per_cvt *per_cvt; 2177 struct hdmi_spec_per_pin *per_pin; 2178 int pinctl; 2179 int err = 0; 2180 2181 mutex_lock(&spec->pcm_lock); 2182 if (hinfo->nid) { 2183 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 2184 if (snd_BUG_ON(pcm_idx < 0)) { 2185 err = -EINVAL; 2186 goto unlock; 2187 } 2188 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); 2189 if (snd_BUG_ON(cvt_idx < 0)) { 2190 err = -EINVAL; 2191 goto unlock; 2192 } 2193 per_cvt = get_cvt(spec, cvt_idx); 2194 per_cvt->assigned = false; 2195 hinfo->nid = 0; 2196 2197 azx_stream(get_azx_dev(substream))->stripe = 0; 2198 2199 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2200 clear_bit(pcm_idx, &spec->pcm_in_use); 2201 pin_idx = hinfo_to_pin_index(codec, hinfo); 2202 if (pin_idx < 0) 2203 goto unlock; 2204 2205 if (snd_BUG_ON(pin_idx < 0)) { 2206 err = -EINVAL; 2207 goto unlock; 2208 } 2209 per_pin = get_pin(spec, pin_idx); 2210 2211 if (spec->dyn_pin_out) { 2212 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2213 per_pin->dev_id); 2214 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2215 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2216 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2217 AC_VERB_SET_PIN_WIDGET_CONTROL, 2218 pinctl & ~PIN_OUT); 2219 } 2220 2221 mutex_lock(&per_pin->lock); 2222 per_pin->chmap_set = false; 2223 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 2224 2225 per_pin->setup = false; 2226 per_pin->channels = 0; 2227 mutex_unlock(&per_pin->lock); 2228 } 2229 2230 unlock: 2231 mutex_unlock(&spec->pcm_lock); 2232 2233 return err; 2234 } 2235 2236 static const struct hda_pcm_ops generic_ops = { 2237 .open = hdmi_pcm_open, 2238 .close = hdmi_pcm_close, 2239 .prepare = generic_hdmi_playback_pcm_prepare, 2240 .cleanup = generic_hdmi_playback_pcm_cleanup, 2241 }; 2242 2243 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) 2244 { 2245 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2246 struct hdmi_spec *spec = codec->spec; 2247 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2248 2249 if (!per_pin) 2250 return 0; 2251 2252 return per_pin->sink_eld.info.spk_alloc; 2253 } 2254 2255 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, 2256 unsigned char *chmap) 2257 { 2258 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2259 struct hdmi_spec *spec = codec->spec; 2260 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2261 2262 /* chmap is already set to 0 in caller */ 2263 if (!per_pin) 2264 return; 2265 2266 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); 2267 } 2268 2269 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, 2270 unsigned char *chmap, int prepared) 2271 { 2272 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2273 struct hdmi_spec *spec = codec->spec; 2274 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2275 2276 if (!per_pin) 2277 return; 2278 mutex_lock(&per_pin->lock); 2279 per_pin->chmap_set = true; 2280 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); 2281 if (prepared) 2282 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 2283 mutex_unlock(&per_pin->lock); 2284 } 2285 2286 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) 2287 { 2288 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2289 struct hdmi_spec *spec = codec->spec; 2290 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2291 2292 return per_pin ? true:false; 2293 } 2294 2295 static int generic_hdmi_build_pcms(struct hda_codec *codec) 2296 { 2297 struct hdmi_spec *spec = codec->spec; 2298 int idx, pcm_num; 2299 2300 /* limit the PCM devices to the codec converters or available PINs */ 2301 pcm_num = min(spec->num_cvts, spec->num_pins); 2302 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num); 2303 2304 for (idx = 0; idx < pcm_num; idx++) { 2305 struct hda_pcm *info; 2306 struct hda_pcm_stream *pstr; 2307 2308 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); 2309 if (!info) 2310 return -ENOMEM; 2311 2312 spec->pcm_rec[idx].pcm = info; 2313 spec->pcm_used++; 2314 info->pcm_type = HDA_PCM_TYPE_HDMI; 2315 info->own_chmap = true; 2316 2317 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2318 pstr->substreams = 1; 2319 pstr->ops = generic_ops; 2320 /* pcm number is less than pcm_rec array size */ 2321 if (spec->pcm_used >= ARRAY_SIZE(spec->pcm_rec)) 2322 break; 2323 /* other pstr fields are set in open */ 2324 } 2325 2326 return 0; 2327 } 2328 2329 static void free_hdmi_jack_priv(struct snd_jack *jack) 2330 { 2331 struct hdmi_pcm *pcm = jack->private_data; 2332 2333 pcm->jack = NULL; 2334 } 2335 2336 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) 2337 { 2338 char hdmi_str[32] = "HDMI/DP"; 2339 struct hdmi_spec *spec = codec->spec; 2340 struct snd_jack *jack; 2341 int pcmdev = get_pcm_rec(spec, pcm_idx)->device; 2342 int err; 2343 2344 if (pcmdev > 0) 2345 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); 2346 2347 err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack, 2348 true, false); 2349 if (err < 0) 2350 return err; 2351 2352 spec->pcm_rec[pcm_idx].jack = jack; 2353 jack->private_data = &spec->pcm_rec[pcm_idx]; 2354 jack->private_free = free_hdmi_jack_priv; 2355 return 0; 2356 } 2357 2358 static int generic_hdmi_build_controls(struct hda_codec *codec) 2359 { 2360 struct hdmi_spec *spec = codec->spec; 2361 int dev, err; 2362 int pin_idx, pcm_idx; 2363 2364 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2365 if (!get_pcm_rec(spec, pcm_idx)->pcm) { 2366 /* no PCM: mark this for skipping permanently */ 2367 set_bit(pcm_idx, &spec->pcm_bitmap); 2368 continue; 2369 } 2370 2371 err = generic_hdmi_build_jack(codec, pcm_idx); 2372 if (err < 0) 2373 return err; 2374 2375 /* create the spdif for each pcm 2376 * pin will be bound when monitor is connected 2377 */ 2378 err = snd_hda_create_dig_out_ctls(codec, 2379 0, spec->cvt_nids[0], 2380 HDA_PCM_TYPE_HDMI); 2381 if (err < 0) 2382 return err; 2383 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2384 2385 dev = get_pcm_rec(spec, pcm_idx)->device; 2386 if (dev != SNDRV_PCM_INVALID_DEVICE) { 2387 /* add control for ELD Bytes */ 2388 err = hdmi_create_eld_ctl(codec, pcm_idx, dev); 2389 if (err < 0) 2390 return err; 2391 } 2392 } 2393 2394 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2395 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2396 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 2397 2398 if (spec->static_pcm_mapping) { 2399 hdmi_attach_hda_pcm(spec, per_pin); 2400 hdmi_pcm_setup_pin(spec, per_pin); 2401 } 2402 2403 pin_eld->eld_valid = false; 2404 hdmi_present_sense(per_pin, 0); 2405 } 2406 2407 /* add channel maps */ 2408 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2409 struct hda_pcm *pcm; 2410 2411 pcm = get_pcm_rec(spec, pcm_idx); 2412 if (!pcm || !pcm->pcm) 2413 break; 2414 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); 2415 if (err < 0) 2416 return err; 2417 } 2418 2419 return 0; 2420 } 2421 2422 static int generic_hdmi_init_per_pins(struct hda_codec *codec) 2423 { 2424 struct hdmi_spec *spec = codec->spec; 2425 int pin_idx; 2426 2427 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2428 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2429 2430 per_pin->codec = codec; 2431 mutex_init(&per_pin->lock); 2432 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); 2433 eld_proc_new(per_pin, pin_idx); 2434 } 2435 return 0; 2436 } 2437 2438 static int generic_hdmi_init(struct hda_codec *codec) 2439 { 2440 struct hdmi_spec *spec = codec->spec; 2441 int pin_idx; 2442 2443 mutex_lock(&spec->bind_lock); 2444 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2445 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2446 hda_nid_t pin_nid = per_pin->pin_nid; 2447 int dev_id = per_pin->dev_id; 2448 2449 snd_hda_set_dev_select(codec, pin_nid, dev_id); 2450 hdmi_init_pin(codec, pin_nid); 2451 if (codec_has_acomp(codec)) 2452 continue; 2453 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id, 2454 jack_callback); 2455 } 2456 mutex_unlock(&spec->bind_lock); 2457 return 0; 2458 } 2459 2460 static void hdmi_array_init(struct hdmi_spec *spec, int nums) 2461 { 2462 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); 2463 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); 2464 } 2465 2466 static void hdmi_array_free(struct hdmi_spec *spec) 2467 { 2468 snd_array_free(&spec->pins); 2469 snd_array_free(&spec->cvts); 2470 } 2471 2472 static void generic_spec_free(struct hda_codec *codec) 2473 { 2474 struct hdmi_spec *spec = codec->spec; 2475 2476 if (spec) { 2477 hdmi_array_free(spec); 2478 kfree(spec); 2479 codec->spec = NULL; 2480 } 2481 codec->dp_mst = false; 2482 } 2483 2484 static void generic_hdmi_free(struct hda_codec *codec) 2485 { 2486 struct hdmi_spec *spec = codec->spec; 2487 int pin_idx, pcm_idx; 2488 2489 if (spec->acomp_registered) { 2490 snd_hdac_acomp_exit(&codec->bus->core); 2491 } else if (codec_has_acomp(codec)) { 2492 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL); 2493 } 2494 codec->relaxed_resume = 0; 2495 2496 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2497 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2498 cancel_delayed_work_sync(&per_pin->work); 2499 eld_proc_free(per_pin); 2500 } 2501 2502 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2503 if (spec->pcm_rec[pcm_idx].jack == NULL) 2504 continue; 2505 snd_device_free(codec->card, spec->pcm_rec[pcm_idx].jack); 2506 } 2507 2508 generic_spec_free(codec); 2509 } 2510 2511 #ifdef CONFIG_PM 2512 static int generic_hdmi_suspend(struct hda_codec *codec) 2513 { 2514 struct hdmi_spec *spec = codec->spec; 2515 int pin_idx; 2516 2517 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2518 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2519 cancel_delayed_work_sync(&per_pin->work); 2520 } 2521 return 0; 2522 } 2523 2524 static int generic_hdmi_resume(struct hda_codec *codec) 2525 { 2526 struct hdmi_spec *spec = codec->spec; 2527 int pin_idx; 2528 2529 codec->patch_ops.init(codec); 2530 snd_hda_regmap_sync(codec); 2531 2532 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2533 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2534 hdmi_present_sense(per_pin, 1); 2535 } 2536 return 0; 2537 } 2538 #endif 2539 2540 static const struct hda_codec_ops generic_hdmi_patch_ops = { 2541 .init = generic_hdmi_init, 2542 .free = generic_hdmi_free, 2543 .build_pcms = generic_hdmi_build_pcms, 2544 .build_controls = generic_hdmi_build_controls, 2545 .unsol_event = hdmi_unsol_event, 2546 #ifdef CONFIG_PM 2547 .suspend = generic_hdmi_suspend, 2548 .resume = generic_hdmi_resume, 2549 #endif 2550 }; 2551 2552 static const struct hdmi_ops generic_standard_hdmi_ops = { 2553 .pin_get_eld = hdmi_pin_get_eld, 2554 .pin_setup_infoframe = hdmi_pin_setup_infoframe, 2555 .pin_hbr_setup = hdmi_pin_hbr_setup, 2556 .setup_stream = hdmi_setup_stream, 2557 }; 2558 2559 /* allocate codec->spec and assign/initialize generic parser ops */ 2560 static int alloc_generic_hdmi(struct hda_codec *codec) 2561 { 2562 struct hdmi_spec *spec; 2563 2564 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2565 if (!spec) 2566 return -ENOMEM; 2567 2568 spec->codec = codec; 2569 spec->ops = generic_standard_hdmi_ops; 2570 spec->dev_num = 1; /* initialize to 1 */ 2571 mutex_init(&spec->pcm_lock); 2572 mutex_init(&spec->bind_lock); 2573 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); 2574 2575 spec->chmap.ops.get_chmap = hdmi_get_chmap; 2576 spec->chmap.ops.set_chmap = hdmi_set_chmap; 2577 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; 2578 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc; 2579 2580 codec->spec = spec; 2581 hdmi_array_init(spec, 4); 2582 2583 codec->patch_ops = generic_hdmi_patch_ops; 2584 2585 return 0; 2586 } 2587 2588 /* generic HDMI parser */ 2589 static int patch_generic_hdmi(struct hda_codec *codec) 2590 { 2591 int err; 2592 2593 err = alloc_generic_hdmi(codec); 2594 if (err < 0) 2595 return err; 2596 2597 err = hdmi_parse_codec(codec); 2598 if (err < 0) { 2599 generic_spec_free(codec); 2600 return err; 2601 } 2602 2603 generic_hdmi_init_per_pins(codec); 2604 return 0; 2605 } 2606 2607 /* 2608 * generic audio component binding 2609 */ 2610 2611 /* turn on / off the unsol event jack detection dynamically */ 2612 static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid, 2613 int dev_id, bool use_acomp) 2614 { 2615 struct hda_jack_tbl *tbl; 2616 2617 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id); 2618 if (tbl) { 2619 /* clear unsol even if component notifier is used, or re-enable 2620 * if notifier is cleared 2621 */ 2622 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag); 2623 snd_hda_codec_write_cache(codec, nid, 0, 2624 AC_VERB_SET_UNSOLICITED_ENABLE, val); 2625 } 2626 } 2627 2628 /* set up / clear component notifier dynamically */ 2629 static void generic_acomp_notifier_set(struct drm_audio_component *acomp, 2630 bool use_acomp) 2631 { 2632 struct hdmi_spec *spec; 2633 int i; 2634 2635 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops); 2636 mutex_lock(&spec->bind_lock); 2637 spec->use_acomp_notifier = use_acomp; 2638 spec->codec->relaxed_resume = use_acomp; 2639 spec->codec->bus->keep_power = 0; 2640 /* reprogram each jack detection logic depending on the notifier */ 2641 for (i = 0; i < spec->num_pins; i++) 2642 reprogram_jack_detect(spec->codec, 2643 get_pin(spec, i)->pin_nid, 2644 get_pin(spec, i)->dev_id, 2645 use_acomp); 2646 mutex_unlock(&spec->bind_lock); 2647 } 2648 2649 /* enable / disable the notifier via master bind / unbind */ 2650 static int generic_acomp_master_bind(struct device *dev, 2651 struct drm_audio_component *acomp) 2652 { 2653 generic_acomp_notifier_set(acomp, true); 2654 return 0; 2655 } 2656 2657 static void generic_acomp_master_unbind(struct device *dev, 2658 struct drm_audio_component *acomp) 2659 { 2660 generic_acomp_notifier_set(acomp, false); 2661 } 2662 2663 /* check whether both HD-audio and DRM PCI devices belong to the same bus */ 2664 static int match_bound_vga(struct device *dev, int subtype, void *data) 2665 { 2666 struct hdac_bus *bus = data; 2667 struct pci_dev *pci, *master; 2668 2669 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev)) 2670 return 0; 2671 master = to_pci_dev(bus->dev); 2672 pci = to_pci_dev(dev); 2673 return master->bus == pci->bus; 2674 } 2675 2676 /* audio component notifier for AMD/Nvidia HDMI codecs */ 2677 static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id) 2678 { 2679 struct hda_codec *codec = audio_ptr; 2680 struct hdmi_spec *spec = codec->spec; 2681 hda_nid_t pin_nid = spec->port2pin(codec, port); 2682 2683 if (!pin_nid) 2684 return; 2685 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN) 2686 return; 2687 /* skip notification during system suspend (but not in runtime PM); 2688 * the state will be updated at resume 2689 */ 2690 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND) 2691 return; 2692 2693 check_presence_and_report(codec, pin_nid, dev_id); 2694 } 2695 2696 /* set up the private drm_audio_ops from the template */ 2697 static void setup_drm_audio_ops(struct hda_codec *codec, 2698 const struct drm_audio_component_audio_ops *ops) 2699 { 2700 struct hdmi_spec *spec = codec->spec; 2701 2702 spec->drm_audio_ops.audio_ptr = codec; 2703 /* intel_audio_codec_enable() or intel_audio_codec_disable() 2704 * will call pin_eld_notify with using audio_ptr pointer 2705 * We need make sure audio_ptr is really setup 2706 */ 2707 wmb(); 2708 spec->drm_audio_ops.pin2port = ops->pin2port; 2709 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify; 2710 spec->drm_audio_ops.master_bind = ops->master_bind; 2711 spec->drm_audio_ops.master_unbind = ops->master_unbind; 2712 } 2713 2714 /* initialize the generic HDMI audio component */ 2715 static void generic_acomp_init(struct hda_codec *codec, 2716 const struct drm_audio_component_audio_ops *ops, 2717 int (*port2pin)(struct hda_codec *, int)) 2718 { 2719 struct hdmi_spec *spec = codec->spec; 2720 2721 if (!enable_acomp) { 2722 codec_info(codec, "audio component disabled by module option\n"); 2723 return; 2724 } 2725 2726 spec->port2pin = port2pin; 2727 setup_drm_audio_ops(codec, ops); 2728 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops, 2729 match_bound_vga, 0)) { 2730 spec->acomp_registered = true; 2731 } 2732 } 2733 2734 /* 2735 * Intel codec parsers and helpers 2736 */ 2737 2738 #define INTEL_GET_VENDOR_VERB 0xf81 2739 #define INTEL_SET_VENDOR_VERB 0x781 2740 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ 2741 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ 2742 2743 static void intel_haswell_enable_all_pins(struct hda_codec *codec, 2744 bool update_tree) 2745 { 2746 unsigned int vendor_param; 2747 struct hdmi_spec *spec = codec->spec; 2748 2749 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2750 INTEL_GET_VENDOR_VERB, 0); 2751 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) 2752 return; 2753 2754 vendor_param |= INTEL_EN_ALL_PIN_CVTS; 2755 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2756 INTEL_SET_VENDOR_VERB, vendor_param); 2757 if (vendor_param == -1) 2758 return; 2759 2760 if (update_tree) 2761 snd_hda_codec_update_widgets(codec); 2762 } 2763 2764 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) 2765 { 2766 unsigned int vendor_param; 2767 struct hdmi_spec *spec = codec->spec; 2768 2769 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2770 INTEL_GET_VENDOR_VERB, 0); 2771 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) 2772 return; 2773 2774 /* enable DP1.2 mode */ 2775 vendor_param |= INTEL_EN_DP12; 2776 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); 2777 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, 2778 INTEL_SET_VENDOR_VERB, vendor_param); 2779 } 2780 2781 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. 2782 * Otherwise you may get severe h/w communication errors. 2783 */ 2784 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, 2785 unsigned int power_state) 2786 { 2787 if (power_state == AC_PWRST_D0) { 2788 intel_haswell_enable_all_pins(codec, false); 2789 intel_haswell_fixup_enable_dp12(codec); 2790 } 2791 2792 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); 2793 snd_hda_codec_set_power_to_all(codec, fg, power_state); 2794 } 2795 2796 /* There is a fixed mapping between audio pin node and display port. 2797 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL: 2798 * Pin Widget 5 - PORT B (port = 1 in i915 driver) 2799 * Pin Widget 6 - PORT C (port = 2 in i915 driver) 2800 * Pin Widget 7 - PORT D (port = 3 in i915 driver) 2801 * 2802 * on VLV, ILK: 2803 * Pin Widget 4 - PORT B (port = 1 in i915 driver) 2804 * Pin Widget 5 - PORT C (port = 2 in i915 driver) 2805 * Pin Widget 6 - PORT D (port = 3 in i915 driver) 2806 */ 2807 static int intel_base_nid(struct hda_codec *codec) 2808 { 2809 switch (codec->core.vendor_id) { 2810 case 0x80860054: /* ILK */ 2811 case 0x80862804: /* ILK */ 2812 case 0x80862882: /* VLV */ 2813 return 4; 2814 default: 2815 return 5; 2816 } 2817 } 2818 2819 static int intel_pin2port(void *audio_ptr, int pin_nid) 2820 { 2821 struct hda_codec *codec = audio_ptr; 2822 struct hdmi_spec *spec = codec->spec; 2823 int base_nid, i; 2824 2825 if (!spec->port_num) { 2826 base_nid = intel_base_nid(codec); 2827 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3)) 2828 return -1; 2829 return pin_nid - base_nid + 1; 2830 } 2831 2832 /* 2833 * looking for the pin number in the mapping table and return 2834 * the index which indicate the port number 2835 */ 2836 for (i = 0; i < spec->port_num; i++) { 2837 if (pin_nid == spec->port_map[i]) 2838 return i; 2839 } 2840 2841 codec_info(codec, "Can't find the HDMI/DP port for pin NID 0x%x\n", pin_nid); 2842 return -1; 2843 } 2844 2845 static int intel_port2pin(struct hda_codec *codec, int port) 2846 { 2847 struct hdmi_spec *spec = codec->spec; 2848 2849 if (!spec->port_num) { 2850 /* we assume only from port-B to port-D */ 2851 if (port < 1 || port > 3) 2852 return 0; 2853 return port + intel_base_nid(codec) - 1; 2854 } 2855 2856 if (port < 0 || port >= spec->port_num) 2857 return 0; 2858 return spec->port_map[port]; 2859 } 2860 2861 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) 2862 { 2863 struct hda_codec *codec = audio_ptr; 2864 int pin_nid; 2865 int dev_id = pipe; 2866 2867 pin_nid = intel_port2pin(codec, port); 2868 if (!pin_nid) 2869 return; 2870 /* skip notification during system suspend (but not in runtime PM); 2871 * the state will be updated at resume 2872 */ 2873 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND) 2874 return; 2875 2876 snd_hdac_i915_set_bclk(&codec->bus->core); 2877 check_presence_and_report(codec, pin_nid, dev_id); 2878 } 2879 2880 static const struct drm_audio_component_audio_ops intel_audio_ops = { 2881 .pin2port = intel_pin2port, 2882 .pin_eld_notify = intel_pin_eld_notify, 2883 }; 2884 2885 /* register i915 component pin_eld_notify callback */ 2886 static void register_i915_notifier(struct hda_codec *codec) 2887 { 2888 struct hdmi_spec *spec = codec->spec; 2889 2890 spec->use_acomp_notifier = true; 2891 spec->port2pin = intel_port2pin; 2892 setup_drm_audio_ops(codec, &intel_audio_ops); 2893 snd_hdac_acomp_register_notifier(&codec->bus->core, 2894 &spec->drm_audio_ops); 2895 /* no need for forcible resume for jack check thanks to notifier */ 2896 codec->relaxed_resume = 1; 2897 } 2898 2899 /* setup_stream ops override for HSW+ */ 2900 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 2901 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 2902 int format) 2903 { 2904 struct hdmi_spec *spec = codec->spec; 2905 int pin_idx = pin_id_to_pin_index(codec, pin_nid, dev_id); 2906 struct hdmi_spec_per_pin *per_pin; 2907 int res; 2908 2909 if (pin_idx < 0) 2910 per_pin = NULL; 2911 else 2912 per_pin = get_pin(spec, pin_idx); 2913 2914 haswell_verify_D0(codec, cvt_nid, pin_nid); 2915 2916 if (spec->silent_stream_type == SILENT_STREAM_KAE && per_pin && per_pin->silent_stream) { 2917 silent_stream_set_kae(codec, per_pin, false); 2918 /* wait for pending transfers in codec to clear */ 2919 usleep_range(100, 200); 2920 } 2921 2922 res = hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 2923 stream_tag, format); 2924 2925 if (spec->silent_stream_type == SILENT_STREAM_KAE && per_pin && per_pin->silent_stream) { 2926 usleep_range(100, 200); 2927 silent_stream_set_kae(codec, per_pin, true); 2928 } 2929 2930 return res; 2931 } 2932 2933 /* pin_cvt_fixup ops override for HSW+ and VLV+ */ 2934 static void i915_pin_cvt_fixup(struct hda_codec *codec, 2935 struct hdmi_spec_per_pin *per_pin, 2936 hda_nid_t cvt_nid) 2937 { 2938 if (per_pin) { 2939 haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid); 2940 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2941 per_pin->dev_id); 2942 intel_verify_pin_cvt_connect(codec, per_pin); 2943 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, 2944 per_pin->dev_id, per_pin->mux_idx); 2945 } else { 2946 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); 2947 } 2948 } 2949 2950 #ifdef CONFIG_PM 2951 static int i915_adlp_hdmi_suspend(struct hda_codec *codec) 2952 { 2953 struct hdmi_spec *spec = codec->spec; 2954 bool silent_streams = false; 2955 int pin_idx, res; 2956 2957 res = generic_hdmi_suspend(codec); 2958 2959 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2960 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2961 2962 if (per_pin->silent_stream) { 2963 silent_streams = true; 2964 break; 2965 } 2966 } 2967 2968 if (silent_streams && spec->silent_stream_type == SILENT_STREAM_KAE) { 2969 /* 2970 * stream-id should remain programmed when codec goes 2971 * to runtime suspend 2972 */ 2973 codec->no_stream_clean_at_suspend = 1; 2974 2975 /* 2976 * the system might go to S3, in which case keep-alive 2977 * must be reprogrammed upon resume 2978 */ 2979 codec->forced_resume = 1; 2980 2981 codec_dbg(codec, "HDMI: KAE active at suspend\n"); 2982 } else { 2983 codec->no_stream_clean_at_suspend = 0; 2984 codec->forced_resume = 0; 2985 } 2986 2987 return res; 2988 } 2989 2990 static int i915_adlp_hdmi_resume(struct hda_codec *codec) 2991 { 2992 struct hdmi_spec *spec = codec->spec; 2993 int pin_idx, res; 2994 2995 res = generic_hdmi_resume(codec); 2996 2997 /* KAE not programmed at suspend, nothing to do here */ 2998 if (!codec->no_stream_clean_at_suspend) 2999 return res; 3000 3001 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 3002 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 3003 3004 /* 3005 * If system was in suspend with monitor connected, 3006 * the codec setting may have been lost. Re-enable 3007 * keep-alive. 3008 */ 3009 if (per_pin->silent_stream) { 3010 unsigned int param; 3011 3012 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, 3013 AC_VERB_GET_CONV, 0); 3014 if (!param) { 3015 codec_dbg(codec, "HDMI: KAE: restore stream id\n"); 3016 silent_stream_enable_i915(codec, per_pin); 3017 } 3018 3019 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, 3020 AC_VERB_GET_DIGI_CONVERT_1, 0); 3021 if (!(param & (AC_DIG3_KAE << 16))) { 3022 codec_dbg(codec, "HDMI: KAE: restore DIG3_KAE\n"); 3023 silent_stream_set_kae(codec, per_pin, true); 3024 } 3025 } 3026 } 3027 3028 return res; 3029 } 3030 #endif 3031 3032 /* precondition and allocation for Intel codecs */ 3033 static int alloc_intel_hdmi(struct hda_codec *codec) 3034 { 3035 int err; 3036 3037 /* requires i915 binding */ 3038 if (!codec->bus->core.audio_component) { 3039 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); 3040 /* set probe_id here to prevent generic fallback binding */ 3041 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE; 3042 return -ENODEV; 3043 } 3044 3045 err = alloc_generic_hdmi(codec); 3046 if (err < 0) 3047 return err; 3048 /* no need to handle unsol events */ 3049 codec->patch_ops.unsol_event = NULL; 3050 return 0; 3051 } 3052 3053 /* parse and post-process for Intel codecs */ 3054 static int parse_intel_hdmi(struct hda_codec *codec) 3055 { 3056 int err, retries = 3; 3057 3058 do { 3059 err = hdmi_parse_codec(codec); 3060 } while (err < 0 && retries--); 3061 3062 if (err < 0) { 3063 generic_spec_free(codec); 3064 return err; 3065 } 3066 3067 generic_hdmi_init_per_pins(codec); 3068 register_i915_notifier(codec); 3069 return 0; 3070 } 3071 3072 /* Intel Haswell and onwards; audio component with eld notifier */ 3073 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid, 3074 const int *port_map, int port_num, int dev_num, 3075 bool send_silent_stream) 3076 { 3077 struct hdmi_spec *spec; 3078 int err; 3079 3080 err = alloc_intel_hdmi(codec); 3081 if (err < 0) 3082 return err; 3083 spec = codec->spec; 3084 codec->dp_mst = true; 3085 spec->vendor_nid = vendor_nid; 3086 spec->port_map = port_map; 3087 spec->port_num = port_num; 3088 spec->intel_hsw_fixup = true; 3089 spec->dev_num = dev_num; 3090 3091 intel_haswell_enable_all_pins(codec, true); 3092 intel_haswell_fixup_enable_dp12(codec); 3093 3094 codec->display_power_control = 1; 3095 3096 codec->patch_ops.set_power_state = haswell_set_power_state; 3097 codec->depop_delay = 0; 3098 codec->auto_runtime_pm = 1; 3099 3100 spec->ops.setup_stream = i915_hsw_setup_stream; 3101 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 3102 3103 /* 3104 * Enable silent stream feature, if it is enabled via 3105 * module param or Kconfig option 3106 */ 3107 if (send_silent_stream) 3108 spec->silent_stream_type = SILENT_STREAM_I915; 3109 3110 return parse_intel_hdmi(codec); 3111 } 3112 3113 static int patch_i915_hsw_hdmi(struct hda_codec *codec) 3114 { 3115 return intel_hsw_common_init(codec, 0x08, NULL, 0, 3, 3116 enable_silent_stream); 3117 } 3118 3119 static int patch_i915_glk_hdmi(struct hda_codec *codec) 3120 { 3121 /* 3122 * Silent stream calls audio component .get_power() from 3123 * .pin_eld_notify(). On GLK this will deadlock in i915 due 3124 * to the audio vs. CDCLK workaround. 3125 */ 3126 return intel_hsw_common_init(codec, 0x0b, NULL, 0, 3, false); 3127 } 3128 3129 static int patch_i915_icl_hdmi(struct hda_codec *codec) 3130 { 3131 /* 3132 * pin to port mapping table where the value indicate the pin number and 3133 * the index indicate the port number. 3134 */ 3135 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb}; 3136 3137 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 3, 3138 enable_silent_stream); 3139 } 3140 3141 static int patch_i915_tgl_hdmi(struct hda_codec *codec) 3142 { 3143 /* 3144 * pin to port mapping table where the value indicate the pin number and 3145 * the index indicate the port number. 3146 */ 3147 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf}; 3148 3149 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 4, 3150 enable_silent_stream); 3151 } 3152 3153 static int patch_i915_adlp_hdmi(struct hda_codec *codec) 3154 { 3155 struct hdmi_spec *spec; 3156 int res; 3157 3158 res = patch_i915_tgl_hdmi(codec); 3159 if (!res) { 3160 spec = codec->spec; 3161 3162 if (spec->silent_stream_type) { 3163 spec->silent_stream_type = SILENT_STREAM_KAE; 3164 3165 #ifdef CONFIG_PM 3166 codec->patch_ops.resume = i915_adlp_hdmi_resume; 3167 codec->patch_ops.suspend = i915_adlp_hdmi_suspend; 3168 #endif 3169 } 3170 } 3171 3172 return res; 3173 } 3174 3175 /* Intel Baytrail and Braswell; with eld notifier */ 3176 static int patch_i915_byt_hdmi(struct hda_codec *codec) 3177 { 3178 struct hdmi_spec *spec; 3179 int err; 3180 3181 err = alloc_intel_hdmi(codec); 3182 if (err < 0) 3183 return err; 3184 spec = codec->spec; 3185 3186 /* For Valleyview/Cherryview, only the display codec is in the display 3187 * power well and can use link_power ops to request/release the power. 3188 */ 3189 codec->display_power_control = 1; 3190 3191 codec->depop_delay = 0; 3192 codec->auto_runtime_pm = 1; 3193 3194 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 3195 3196 return parse_intel_hdmi(codec); 3197 } 3198 3199 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ 3200 static int patch_i915_cpt_hdmi(struct hda_codec *codec) 3201 { 3202 int err; 3203 3204 err = alloc_intel_hdmi(codec); 3205 if (err < 0) 3206 return err; 3207 return parse_intel_hdmi(codec); 3208 } 3209 3210 /* 3211 * Shared non-generic implementations 3212 */ 3213 3214 static int simple_playback_build_pcms(struct hda_codec *codec) 3215 { 3216 struct hdmi_spec *spec = codec->spec; 3217 struct hda_pcm *info; 3218 unsigned int chans; 3219 struct hda_pcm_stream *pstr; 3220 struct hdmi_spec_per_cvt *per_cvt; 3221 3222 per_cvt = get_cvt(spec, 0); 3223 chans = get_wcaps(codec, per_cvt->cvt_nid); 3224 chans = get_wcaps_channels(chans); 3225 3226 info = snd_hda_codec_pcm_new(codec, "HDMI 0"); 3227 if (!info) 3228 return -ENOMEM; 3229 spec->pcm_rec[0].pcm = info; 3230 info->pcm_type = HDA_PCM_TYPE_HDMI; 3231 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3232 *pstr = spec->pcm_playback; 3233 pstr->nid = per_cvt->cvt_nid; 3234 if (pstr->channels_max <= 2 && chans && chans <= 16) 3235 pstr->channels_max = chans; 3236 3237 return 0; 3238 } 3239 3240 /* unsolicited event for jack sensing */ 3241 static void simple_hdmi_unsol_event(struct hda_codec *codec, 3242 unsigned int res) 3243 { 3244 snd_hda_jack_set_dirty_all(codec); 3245 snd_hda_jack_report_sync(codec); 3246 } 3247 3248 /* generic_hdmi_build_jack can be used for simple_hdmi, too, 3249 * as long as spec->pins[] is set correctly 3250 */ 3251 #define simple_hdmi_build_jack generic_hdmi_build_jack 3252 3253 static int simple_playback_build_controls(struct hda_codec *codec) 3254 { 3255 struct hdmi_spec *spec = codec->spec; 3256 struct hdmi_spec_per_cvt *per_cvt; 3257 int err; 3258 3259 per_cvt = get_cvt(spec, 0); 3260 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, 3261 per_cvt->cvt_nid, 3262 HDA_PCM_TYPE_HDMI); 3263 if (err < 0) 3264 return err; 3265 return simple_hdmi_build_jack(codec, 0); 3266 } 3267 3268 static int simple_playback_init(struct hda_codec *codec) 3269 { 3270 struct hdmi_spec *spec = codec->spec; 3271 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); 3272 hda_nid_t pin = per_pin->pin_nid; 3273 3274 snd_hda_codec_write(codec, pin, 0, 3275 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); 3276 /* some codecs require to unmute the pin */ 3277 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 3278 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, 3279 AMP_OUT_UNMUTE); 3280 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id); 3281 return 0; 3282 } 3283 3284 static void simple_playback_free(struct hda_codec *codec) 3285 { 3286 struct hdmi_spec *spec = codec->spec; 3287 3288 hdmi_array_free(spec); 3289 kfree(spec); 3290 } 3291 3292 /* 3293 * Nvidia specific implementations 3294 */ 3295 3296 #define Nv_VERB_SET_Channel_Allocation 0xF79 3297 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A 3298 #define Nv_VERB_SET_Audio_Protection_On 0xF98 3299 #define Nv_VERB_SET_Audio_Protection_Off 0xF99 3300 3301 #define nvhdmi_master_con_nid_7x 0x04 3302 #define nvhdmi_master_pin_nid_7x 0x05 3303 3304 static const hda_nid_t nvhdmi_con_nids_7x[4] = { 3305 /*front, rear, clfe, rear_surr */ 3306 0x6, 0x8, 0xa, 0xc, 3307 }; 3308 3309 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { 3310 /* set audio protect on */ 3311 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3312 /* enable digital output on pin widget */ 3313 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3314 {} /* terminator */ 3315 }; 3316 3317 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { 3318 /* set audio protect on */ 3319 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3320 /* enable digital output on pin widget */ 3321 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3322 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3323 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3324 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3325 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3326 {} /* terminator */ 3327 }; 3328 3329 #ifdef LIMITED_RATE_FMT_SUPPORT 3330 /* support only the safe format and rate */ 3331 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 3332 #define SUPPORTED_MAXBPS 16 3333 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE 3334 #else 3335 /* support all rates and formats */ 3336 #define SUPPORTED_RATES \ 3337 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ 3338 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ 3339 SNDRV_PCM_RATE_192000) 3340 #define SUPPORTED_MAXBPS 24 3341 #define SUPPORTED_FORMATS \ 3342 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 3343 #endif 3344 3345 static int nvhdmi_7x_init_2ch(struct hda_codec *codec) 3346 { 3347 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); 3348 return 0; 3349 } 3350 3351 static int nvhdmi_7x_init_8ch(struct hda_codec *codec) 3352 { 3353 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); 3354 return 0; 3355 } 3356 3357 static const unsigned int channels_2_6_8[] = { 3358 2, 6, 8 3359 }; 3360 3361 static const unsigned int channels_2_8[] = { 3362 2, 8 3363 }; 3364 3365 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { 3366 .count = ARRAY_SIZE(channels_2_6_8), 3367 .list = channels_2_6_8, 3368 .mask = 0, 3369 }; 3370 3371 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { 3372 .count = ARRAY_SIZE(channels_2_8), 3373 .list = channels_2_8, 3374 .mask = 0, 3375 }; 3376 3377 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, 3378 struct hda_codec *codec, 3379 struct snd_pcm_substream *substream) 3380 { 3381 struct hdmi_spec *spec = codec->spec; 3382 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; 3383 3384 switch (codec->preset->vendor_id) { 3385 case 0x10de0002: 3386 case 0x10de0003: 3387 case 0x10de0005: 3388 case 0x10de0006: 3389 hw_constraints_channels = &hw_constraints_2_8_channels; 3390 break; 3391 case 0x10de0007: 3392 hw_constraints_channels = &hw_constraints_2_6_8_channels; 3393 break; 3394 default: 3395 break; 3396 } 3397 3398 if (hw_constraints_channels != NULL) { 3399 snd_pcm_hw_constraint_list(substream->runtime, 0, 3400 SNDRV_PCM_HW_PARAM_CHANNELS, 3401 hw_constraints_channels); 3402 } else { 3403 snd_pcm_hw_constraint_step(substream->runtime, 0, 3404 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 3405 } 3406 3407 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3408 } 3409 3410 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, 3411 struct hda_codec *codec, 3412 struct snd_pcm_substream *substream) 3413 { 3414 struct hdmi_spec *spec = codec->spec; 3415 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3416 } 3417 3418 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3419 struct hda_codec *codec, 3420 unsigned int stream_tag, 3421 unsigned int format, 3422 struct snd_pcm_substream *substream) 3423 { 3424 struct hdmi_spec *spec = codec->spec; 3425 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3426 stream_tag, format, substream); 3427 } 3428 3429 static const struct hda_pcm_stream simple_pcm_playback = { 3430 .substreams = 1, 3431 .channels_min = 2, 3432 .channels_max = 2, 3433 .ops = { 3434 .open = simple_playback_pcm_open, 3435 .close = simple_playback_pcm_close, 3436 .prepare = simple_playback_pcm_prepare 3437 }, 3438 }; 3439 3440 static const struct hda_codec_ops simple_hdmi_patch_ops = { 3441 .build_controls = simple_playback_build_controls, 3442 .build_pcms = simple_playback_build_pcms, 3443 .init = simple_playback_init, 3444 .free = simple_playback_free, 3445 .unsol_event = simple_hdmi_unsol_event, 3446 }; 3447 3448 static int patch_simple_hdmi(struct hda_codec *codec, 3449 hda_nid_t cvt_nid, hda_nid_t pin_nid) 3450 { 3451 struct hdmi_spec *spec; 3452 struct hdmi_spec_per_cvt *per_cvt; 3453 struct hdmi_spec_per_pin *per_pin; 3454 3455 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 3456 if (!spec) 3457 return -ENOMEM; 3458 3459 spec->codec = codec; 3460 codec->spec = spec; 3461 hdmi_array_init(spec, 1); 3462 3463 spec->multiout.num_dacs = 0; /* no analog */ 3464 spec->multiout.max_channels = 2; 3465 spec->multiout.dig_out_nid = cvt_nid; 3466 spec->num_cvts = 1; 3467 spec->num_pins = 1; 3468 per_pin = snd_array_new(&spec->pins); 3469 per_cvt = snd_array_new(&spec->cvts); 3470 if (!per_pin || !per_cvt) { 3471 simple_playback_free(codec); 3472 return -ENOMEM; 3473 } 3474 per_cvt->cvt_nid = cvt_nid; 3475 per_pin->pin_nid = pin_nid; 3476 spec->pcm_playback = simple_pcm_playback; 3477 3478 codec->patch_ops = simple_hdmi_patch_ops; 3479 3480 return 0; 3481 } 3482 3483 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, 3484 int channels) 3485 { 3486 unsigned int chanmask; 3487 int chan = channels ? (channels - 1) : 1; 3488 3489 switch (channels) { 3490 default: 3491 case 0: 3492 case 2: 3493 chanmask = 0x00; 3494 break; 3495 case 4: 3496 chanmask = 0x08; 3497 break; 3498 case 6: 3499 chanmask = 0x0b; 3500 break; 3501 case 8: 3502 chanmask = 0x13; 3503 break; 3504 } 3505 3506 /* Set the audio infoframe channel allocation and checksum fields. The 3507 * channel count is computed implicitly by the hardware. */ 3508 snd_hda_codec_write(codec, 0x1, 0, 3509 Nv_VERB_SET_Channel_Allocation, chanmask); 3510 3511 snd_hda_codec_write(codec, 0x1, 0, 3512 Nv_VERB_SET_Info_Frame_Checksum, 3513 (0x71 - chan - chanmask)); 3514 } 3515 3516 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, 3517 struct hda_codec *codec, 3518 struct snd_pcm_substream *substream) 3519 { 3520 struct hdmi_spec *spec = codec->spec; 3521 int i; 3522 3523 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 3524 0, AC_VERB_SET_CHANNEL_STREAMID, 0); 3525 for (i = 0; i < 4; i++) { 3526 /* set the stream id */ 3527 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3528 AC_VERB_SET_CHANNEL_STREAMID, 0); 3529 /* set the stream format */ 3530 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3531 AC_VERB_SET_STREAM_FORMAT, 0); 3532 } 3533 3534 /* The audio hardware sends a channel count of 0x7 (8ch) when all the 3535 * streams are disabled. */ 3536 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3537 3538 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3539 } 3540 3541 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, 3542 struct hda_codec *codec, 3543 unsigned int stream_tag, 3544 unsigned int format, 3545 struct snd_pcm_substream *substream) 3546 { 3547 int chs; 3548 unsigned int dataDCC2, channel_id; 3549 int i; 3550 struct hdmi_spec *spec = codec->spec; 3551 struct hda_spdif_out *spdif; 3552 struct hdmi_spec_per_cvt *per_cvt; 3553 3554 mutex_lock(&codec->spdif_mutex); 3555 per_cvt = get_cvt(spec, 0); 3556 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); 3557 3558 chs = substream->runtime->channels; 3559 3560 dataDCC2 = 0x2; 3561 3562 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ 3563 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) 3564 snd_hda_codec_write(codec, 3565 nvhdmi_master_con_nid_7x, 3566 0, 3567 AC_VERB_SET_DIGI_CONVERT_1, 3568 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3569 3570 /* set the stream id */ 3571 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3572 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); 3573 3574 /* set the stream format */ 3575 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3576 AC_VERB_SET_STREAM_FORMAT, format); 3577 3578 /* turn on again (if needed) */ 3579 /* enable and set the channel status audio/data flag */ 3580 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { 3581 snd_hda_codec_write(codec, 3582 nvhdmi_master_con_nid_7x, 3583 0, 3584 AC_VERB_SET_DIGI_CONVERT_1, 3585 spdif->ctls & 0xff); 3586 snd_hda_codec_write(codec, 3587 nvhdmi_master_con_nid_7x, 3588 0, 3589 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3590 } 3591 3592 for (i = 0; i < 4; i++) { 3593 if (chs == 2) 3594 channel_id = 0; 3595 else 3596 channel_id = i * 2; 3597 3598 /* turn off SPDIF once; 3599 *otherwise the IEC958 bits won't be updated 3600 */ 3601 if (codec->spdif_status_reset && 3602 (spdif->ctls & AC_DIG1_ENABLE)) 3603 snd_hda_codec_write(codec, 3604 nvhdmi_con_nids_7x[i], 3605 0, 3606 AC_VERB_SET_DIGI_CONVERT_1, 3607 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3608 /* set the stream id */ 3609 snd_hda_codec_write(codec, 3610 nvhdmi_con_nids_7x[i], 3611 0, 3612 AC_VERB_SET_CHANNEL_STREAMID, 3613 (stream_tag << 4) | channel_id); 3614 /* set the stream format */ 3615 snd_hda_codec_write(codec, 3616 nvhdmi_con_nids_7x[i], 3617 0, 3618 AC_VERB_SET_STREAM_FORMAT, 3619 format); 3620 /* turn on again (if needed) */ 3621 /* enable and set the channel status audio/data flag */ 3622 if (codec->spdif_status_reset && 3623 (spdif->ctls & AC_DIG1_ENABLE)) { 3624 snd_hda_codec_write(codec, 3625 nvhdmi_con_nids_7x[i], 3626 0, 3627 AC_VERB_SET_DIGI_CONVERT_1, 3628 spdif->ctls & 0xff); 3629 snd_hda_codec_write(codec, 3630 nvhdmi_con_nids_7x[i], 3631 0, 3632 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3633 } 3634 } 3635 3636 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); 3637 3638 mutex_unlock(&codec->spdif_mutex); 3639 return 0; 3640 } 3641 3642 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { 3643 .substreams = 1, 3644 .channels_min = 2, 3645 .channels_max = 8, 3646 .nid = nvhdmi_master_con_nid_7x, 3647 .rates = SUPPORTED_RATES, 3648 .maxbps = SUPPORTED_MAXBPS, 3649 .formats = SUPPORTED_FORMATS, 3650 .ops = { 3651 .open = simple_playback_pcm_open, 3652 .close = nvhdmi_8ch_7x_pcm_close, 3653 .prepare = nvhdmi_8ch_7x_pcm_prepare 3654 }, 3655 }; 3656 3657 static int patch_nvhdmi_2ch(struct hda_codec *codec) 3658 { 3659 struct hdmi_spec *spec; 3660 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, 3661 nvhdmi_master_pin_nid_7x); 3662 if (err < 0) 3663 return err; 3664 3665 codec->patch_ops.init = nvhdmi_7x_init_2ch; 3666 /* override the PCM rates, etc, as the codec doesn't give full list */ 3667 spec = codec->spec; 3668 spec->pcm_playback.rates = SUPPORTED_RATES; 3669 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; 3670 spec->pcm_playback.formats = SUPPORTED_FORMATS; 3671 spec->nv_dp_workaround = true; 3672 return 0; 3673 } 3674 3675 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) 3676 { 3677 struct hdmi_spec *spec = codec->spec; 3678 int err = simple_playback_build_pcms(codec); 3679 if (!err) { 3680 struct hda_pcm *info = get_pcm_rec(spec, 0); 3681 info->own_chmap = true; 3682 } 3683 return err; 3684 } 3685 3686 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) 3687 { 3688 struct hdmi_spec *spec = codec->spec; 3689 struct hda_pcm *info; 3690 struct snd_pcm_chmap *chmap; 3691 int err; 3692 3693 err = simple_playback_build_controls(codec); 3694 if (err < 0) 3695 return err; 3696 3697 /* add channel maps */ 3698 info = get_pcm_rec(spec, 0); 3699 err = snd_pcm_add_chmap_ctls(info->pcm, 3700 SNDRV_PCM_STREAM_PLAYBACK, 3701 snd_pcm_alt_chmaps, 8, 0, &chmap); 3702 if (err < 0) 3703 return err; 3704 switch (codec->preset->vendor_id) { 3705 case 0x10de0002: 3706 case 0x10de0003: 3707 case 0x10de0005: 3708 case 0x10de0006: 3709 chmap->channel_mask = (1U << 2) | (1U << 8); 3710 break; 3711 case 0x10de0007: 3712 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); 3713 } 3714 return 0; 3715 } 3716 3717 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) 3718 { 3719 struct hdmi_spec *spec; 3720 int err = patch_nvhdmi_2ch(codec); 3721 if (err < 0) 3722 return err; 3723 spec = codec->spec; 3724 spec->multiout.max_channels = 8; 3725 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; 3726 codec->patch_ops.init = nvhdmi_7x_init_8ch; 3727 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; 3728 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; 3729 3730 /* Initialize the audio infoframe channel mask and checksum to something 3731 * valid */ 3732 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3733 3734 return 0; 3735 } 3736 3737 /* 3738 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: 3739 * - 0x10de0015 3740 * - 0x10de0040 3741 */ 3742 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, 3743 struct hdac_cea_channel_speaker_allocation *cap, int channels) 3744 { 3745 if (cap->ca_index == 0x00 && channels == 2) 3746 return SNDRV_CTL_TLVT_CHMAP_FIXED; 3747 3748 /* If the speaker allocation matches the channel count, it is OK. */ 3749 if (cap->channels != channels) 3750 return -1; 3751 3752 /* all channels are remappable freely */ 3753 return SNDRV_CTL_TLVT_CHMAP_VAR; 3754 } 3755 3756 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, 3757 int ca, int chs, unsigned char *map) 3758 { 3759 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) 3760 return -EINVAL; 3761 3762 return 0; 3763 } 3764 3765 /* map from pin NID to port; port is 0-based */ 3766 /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */ 3767 static int nvhdmi_pin2port(void *audio_ptr, int pin_nid) 3768 { 3769 return pin_nid - 4; 3770 } 3771 3772 /* reverse-map from port to pin NID: see above */ 3773 static int nvhdmi_port2pin(struct hda_codec *codec, int port) 3774 { 3775 return port + 4; 3776 } 3777 3778 static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = { 3779 .pin2port = nvhdmi_pin2port, 3780 .pin_eld_notify = generic_acomp_pin_eld_notify, 3781 .master_bind = generic_acomp_master_bind, 3782 .master_unbind = generic_acomp_master_unbind, 3783 }; 3784 3785 static int patch_nvhdmi(struct hda_codec *codec) 3786 { 3787 struct hdmi_spec *spec; 3788 int err; 3789 3790 err = alloc_generic_hdmi(codec); 3791 if (err < 0) 3792 return err; 3793 codec->dp_mst = true; 3794 3795 spec = codec->spec; 3796 3797 err = hdmi_parse_codec(codec); 3798 if (err < 0) { 3799 generic_spec_free(codec); 3800 return err; 3801 } 3802 3803 generic_hdmi_init_per_pins(codec); 3804 3805 spec->dyn_pin_out = true; 3806 3807 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3808 nvhdmi_chmap_cea_alloc_validate_get_type; 3809 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3810 spec->nv_dp_workaround = true; 3811 3812 codec->link_down_at_suspend = 1; 3813 3814 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin); 3815 3816 return 0; 3817 } 3818 3819 static int patch_nvhdmi_legacy(struct hda_codec *codec) 3820 { 3821 struct hdmi_spec *spec; 3822 int err; 3823 3824 err = patch_generic_hdmi(codec); 3825 if (err) 3826 return err; 3827 3828 spec = codec->spec; 3829 spec->dyn_pin_out = true; 3830 3831 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3832 nvhdmi_chmap_cea_alloc_validate_get_type; 3833 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3834 spec->nv_dp_workaround = true; 3835 3836 codec->link_down_at_suspend = 1; 3837 3838 return 0; 3839 } 3840 3841 /* 3842 * The HDA codec on NVIDIA Tegra contains two scratch registers that are 3843 * accessed using vendor-defined verbs. These registers can be used for 3844 * interoperability between the HDA and HDMI drivers. 3845 */ 3846 3847 /* Audio Function Group node */ 3848 #define NVIDIA_AFG_NID 0x01 3849 3850 /* 3851 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio 3852 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to 3853 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This 3854 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an 3855 * additional bit (at position 30) to signal the validity of the format. 3856 * 3857 * | 31 | 30 | 29 16 | 15 0 | 3858 * +---------+-------+--------+--------+ 3859 * | TRIGGER | VALID | UNUSED | FORMAT | 3860 * +-----------------------------------| 3861 * 3862 * Note that for the trigger bit to take effect it needs to change value 3863 * (i.e. it needs to be toggled). The trigger bit is not applicable from 3864 * TEGRA234 chip onwards, as new verb id 0xf80 will be used for interrupt 3865 * trigger to hdmi. 3866 */ 3867 #define NVIDIA_SET_HOST_INTR 0xf80 3868 #define NVIDIA_GET_SCRATCH0 0xfa6 3869 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 3870 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 3871 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 3872 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa 3873 #define NVIDIA_SCRATCH_TRIGGER (1 << 7) 3874 #define NVIDIA_SCRATCH_VALID (1 << 6) 3875 3876 #define NVIDIA_GET_SCRATCH1 0xfab 3877 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac 3878 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad 3879 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae 3880 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf 3881 3882 /* 3883 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, 3884 * the format is invalidated so that the HDMI codec can be disabled. 3885 */ 3886 static void tegra_hdmi_set_format(struct hda_codec *codec, 3887 hda_nid_t cvt_nid, 3888 unsigned int format) 3889 { 3890 unsigned int value; 3891 unsigned int nid = NVIDIA_AFG_NID; 3892 struct hdmi_spec *spec = codec->spec; 3893 3894 /* 3895 * Tegra HDA codec design from TEGRA234 chip onwards support DP MST. 3896 * This resulted in moving scratch registers from audio function 3897 * group to converter widget context. So CVT NID should be used for 3898 * scratch register read/write for DP MST supported Tegra HDA codec. 3899 */ 3900 if (codec->dp_mst) 3901 nid = cvt_nid; 3902 3903 /* bits [31:30] contain the trigger and valid bits */ 3904 value = snd_hda_codec_read(codec, nid, 0, 3905 NVIDIA_GET_SCRATCH0, 0); 3906 value = (value >> 24) & 0xff; 3907 3908 /* bits [15:0] are used to store the HDA format */ 3909 snd_hda_codec_write(codec, nid, 0, 3910 NVIDIA_SET_SCRATCH0_BYTE0, 3911 (format >> 0) & 0xff); 3912 snd_hda_codec_write(codec, nid, 0, 3913 NVIDIA_SET_SCRATCH0_BYTE1, 3914 (format >> 8) & 0xff); 3915 3916 /* bits [16:24] are unused */ 3917 snd_hda_codec_write(codec, nid, 0, 3918 NVIDIA_SET_SCRATCH0_BYTE2, 0); 3919 3920 /* 3921 * Bit 30 signals that the data is valid and hence that HDMI audio can 3922 * be enabled. 3923 */ 3924 if (format == 0) 3925 value &= ~NVIDIA_SCRATCH_VALID; 3926 else 3927 value |= NVIDIA_SCRATCH_VALID; 3928 3929 if (spec->hdmi_intr_trig_ctrl) { 3930 /* 3931 * For Tegra HDA Codec design from TEGRA234 onwards, the 3932 * Interrupt to hdmi driver is triggered by writing 3933 * non-zero values to verb 0xF80 instead of 31st bit of 3934 * scratch register. 3935 */ 3936 snd_hda_codec_write(codec, nid, 0, 3937 NVIDIA_SET_SCRATCH0_BYTE3, value); 3938 snd_hda_codec_write(codec, nid, 0, 3939 NVIDIA_SET_HOST_INTR, 0x1); 3940 } else { 3941 /* 3942 * Whenever the 31st trigger bit is toggled, an interrupt is raised 3943 * in the HDMI codec. The HDMI driver will use that as trigger 3944 * to update its configuration. 3945 */ 3946 value ^= NVIDIA_SCRATCH_TRIGGER; 3947 3948 snd_hda_codec_write(codec, nid, 0, 3949 NVIDIA_SET_SCRATCH0_BYTE3, value); 3950 } 3951 } 3952 3953 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, 3954 struct hda_codec *codec, 3955 unsigned int stream_tag, 3956 unsigned int format, 3957 struct snd_pcm_substream *substream) 3958 { 3959 int err; 3960 3961 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, 3962 format, substream); 3963 if (err < 0) 3964 return err; 3965 3966 /* notify the HDMI codec of the format change */ 3967 tegra_hdmi_set_format(codec, hinfo->nid, format); 3968 3969 return 0; 3970 } 3971 3972 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, 3973 struct hda_codec *codec, 3974 struct snd_pcm_substream *substream) 3975 { 3976 /* invalidate the format in the HDMI codec */ 3977 tegra_hdmi_set_format(codec, hinfo->nid, 0); 3978 3979 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); 3980 } 3981 3982 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) 3983 { 3984 struct hdmi_spec *spec = codec->spec; 3985 unsigned int i; 3986 3987 for (i = 0; i < spec->num_pins; i++) { 3988 struct hda_pcm *pcm = get_pcm_rec(spec, i); 3989 3990 if (pcm->pcm_type == type) 3991 return pcm; 3992 } 3993 3994 return NULL; 3995 } 3996 3997 static int tegra_hdmi_build_pcms(struct hda_codec *codec) 3998 { 3999 struct hda_pcm_stream *stream; 4000 struct hda_pcm *pcm; 4001 int err; 4002 4003 err = generic_hdmi_build_pcms(codec); 4004 if (err < 0) 4005 return err; 4006 4007 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); 4008 if (!pcm) 4009 return -ENODEV; 4010 4011 /* 4012 * Override ->prepare() and ->cleanup() operations to notify the HDMI 4013 * codec about format changes. 4014 */ 4015 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 4016 stream->ops.prepare = tegra_hdmi_pcm_prepare; 4017 stream->ops.cleanup = tegra_hdmi_pcm_cleanup; 4018 4019 return 0; 4020 } 4021 4022 static int tegra_hdmi_init(struct hda_codec *codec) 4023 { 4024 struct hdmi_spec *spec = codec->spec; 4025 int i, err; 4026 4027 err = hdmi_parse_codec(codec); 4028 if (err < 0) { 4029 generic_spec_free(codec); 4030 return err; 4031 } 4032 4033 for (i = 0; i < spec->num_cvts; i++) 4034 snd_hda_codec_write(codec, spec->cvt_nids[i], 0, 4035 AC_VERB_SET_DIGI_CONVERT_1, 4036 AC_DIG1_ENABLE); 4037 4038 generic_hdmi_init_per_pins(codec); 4039 4040 codec->depop_delay = 10; 4041 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; 4042 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4043 nvhdmi_chmap_cea_alloc_validate_get_type; 4044 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 4045 4046 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4047 nvhdmi_chmap_cea_alloc_validate_get_type; 4048 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 4049 spec->nv_dp_workaround = true; 4050 4051 return 0; 4052 } 4053 4054 static int patch_tegra_hdmi(struct hda_codec *codec) 4055 { 4056 int err; 4057 4058 err = alloc_generic_hdmi(codec); 4059 if (err < 0) 4060 return err; 4061 4062 return tegra_hdmi_init(codec); 4063 } 4064 4065 static int patch_tegra234_hdmi(struct hda_codec *codec) 4066 { 4067 struct hdmi_spec *spec; 4068 int err; 4069 4070 err = alloc_generic_hdmi(codec); 4071 if (err < 0) 4072 return err; 4073 4074 codec->dp_mst = true; 4075 spec = codec->spec; 4076 spec->dyn_pin_out = true; 4077 spec->hdmi_intr_trig_ctrl = true; 4078 4079 return tegra_hdmi_init(codec); 4080 } 4081 4082 /* 4083 * ATI/AMD-specific implementations 4084 */ 4085 4086 #define is_amdhdmi_rev3_or_later(codec) \ 4087 ((codec)->core.vendor_id == 0x1002aa01 && \ 4088 ((codec)->core.revision_id & 0xff00) >= 0x0300) 4089 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) 4090 4091 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ 4092 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 4093 #define ATI_VERB_SET_DOWNMIX_INFO 0x772 4094 #define ATI_VERB_SET_MULTICHANNEL_01 0x777 4095 #define ATI_VERB_SET_MULTICHANNEL_23 0x778 4096 #define ATI_VERB_SET_MULTICHANNEL_45 0x779 4097 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a 4098 #define ATI_VERB_SET_HBR_CONTROL 0x77c 4099 #define ATI_VERB_SET_MULTICHANNEL_1 0x785 4100 #define ATI_VERB_SET_MULTICHANNEL_3 0x786 4101 #define ATI_VERB_SET_MULTICHANNEL_5 0x787 4102 #define ATI_VERB_SET_MULTICHANNEL_7 0x788 4103 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 4104 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 4105 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 4106 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 4107 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 4108 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 4109 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a 4110 #define ATI_VERB_GET_HBR_CONTROL 0xf7c 4111 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 4112 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 4113 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 4114 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 4115 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 4116 4117 /* AMD specific HDA cvt verbs */ 4118 #define ATI_VERB_SET_RAMP_RATE 0x770 4119 #define ATI_VERB_GET_RAMP_RATE 0xf70 4120 4121 #define ATI_OUT_ENABLE 0x1 4122 4123 #define ATI_MULTICHANNEL_MODE_PAIRED 0 4124 #define ATI_MULTICHANNEL_MODE_SINGLE 1 4125 4126 #define ATI_HBR_CAPABLE 0x01 4127 #define ATI_HBR_ENABLE 0x10 4128 4129 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 4130 int dev_id, unsigned char *buf, int *eld_size) 4131 { 4132 WARN_ON(dev_id != 0); 4133 /* call hda_eld.c ATI/AMD-specific function */ 4134 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, 4135 is_amdhdmi_rev3_or_later(codec)); 4136 } 4137 4138 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, 4139 hda_nid_t pin_nid, int dev_id, int ca, 4140 int active_channels, int conn_type) 4141 { 4142 WARN_ON(dev_id != 0); 4143 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); 4144 } 4145 4146 static int atihdmi_paired_swap_fc_lfe(int pos) 4147 { 4148 /* 4149 * ATI/AMD have automatic FC/LFE swap built-in 4150 * when in pairwise mapping mode. 4151 */ 4152 4153 switch (pos) { 4154 /* see channel_allocations[].speakers[] */ 4155 case 2: return 3; 4156 case 3: return 2; 4157 default: break; 4158 } 4159 4160 return pos; 4161 } 4162 4163 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, 4164 int ca, int chs, unsigned char *map) 4165 { 4166 struct hdac_cea_channel_speaker_allocation *cap; 4167 int i, j; 4168 4169 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ 4170 4171 cap = snd_hdac_get_ch_alloc_from_ca(ca); 4172 for (i = 0; i < chs; ++i) { 4173 int mask = snd_hdac_chmap_to_spk_mask(map[i]); 4174 bool ok = false; 4175 bool companion_ok = false; 4176 4177 if (!mask) 4178 continue; 4179 4180 for (j = 0 + i % 2; j < 8; j += 2) { 4181 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); 4182 if (cap->speakers[chan_idx] == mask) { 4183 /* channel is in a supported position */ 4184 ok = true; 4185 4186 if (i % 2 == 0 && i + 1 < chs) { 4187 /* even channel, check the odd companion */ 4188 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); 4189 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); 4190 int comp_mask_act = cap->speakers[comp_chan_idx]; 4191 4192 if (comp_mask_req == comp_mask_act) 4193 companion_ok = true; 4194 else 4195 return -EINVAL; 4196 } 4197 break; 4198 } 4199 } 4200 4201 if (!ok) 4202 return -EINVAL; 4203 4204 if (companion_ok) 4205 i++; /* companion channel already checked */ 4206 } 4207 4208 return 0; 4209 } 4210 4211 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, 4212 hda_nid_t pin_nid, int hdmi_slot, int stream_channel) 4213 { 4214 struct hda_codec *codec = hdac_to_hda_codec(hdac); 4215 int verb; 4216 int ati_channel_setup = 0; 4217 4218 if (hdmi_slot > 7) 4219 return -EINVAL; 4220 4221 if (!has_amd_full_remap_support(codec)) { 4222 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); 4223 4224 /* In case this is an odd slot but without stream channel, do not 4225 * disable the slot since the corresponding even slot could have a 4226 * channel. In case neither have a channel, the slot pair will be 4227 * disabled when this function is called for the even slot. */ 4228 if (hdmi_slot % 2 != 0 && stream_channel == 0xf) 4229 return 0; 4230 4231 hdmi_slot -= hdmi_slot % 2; 4232 4233 if (stream_channel != 0xf) 4234 stream_channel -= stream_channel % 2; 4235 } 4236 4237 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; 4238 4239 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ 4240 4241 if (stream_channel != 0xf) 4242 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; 4243 4244 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); 4245 } 4246 4247 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, 4248 hda_nid_t pin_nid, int asp_slot) 4249 { 4250 struct hda_codec *codec = hdac_to_hda_codec(hdac); 4251 bool was_odd = false; 4252 int ati_asp_slot = asp_slot; 4253 int verb; 4254 int ati_channel_setup; 4255 4256 if (asp_slot > 7) 4257 return -EINVAL; 4258 4259 if (!has_amd_full_remap_support(codec)) { 4260 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); 4261 if (ati_asp_slot % 2 != 0) { 4262 ati_asp_slot -= 1; 4263 was_odd = true; 4264 } 4265 } 4266 4267 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; 4268 4269 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); 4270 4271 if (!(ati_channel_setup & ATI_OUT_ENABLE)) 4272 return 0xf; 4273 4274 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; 4275 } 4276 4277 static int atihdmi_paired_chmap_cea_alloc_validate_get_type( 4278 struct hdac_chmap *chmap, 4279 struct hdac_cea_channel_speaker_allocation *cap, 4280 int channels) 4281 { 4282 int c; 4283 4284 /* 4285 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so 4286 * we need to take that into account (a single channel may take 2 4287 * channel slots if we need to carry a silent channel next to it). 4288 * On Rev3+ AMD codecs this function is not used. 4289 */ 4290 int chanpairs = 0; 4291 4292 /* We only produce even-numbered channel count TLVs */ 4293 if ((channels % 2) != 0) 4294 return -1; 4295 4296 for (c = 0; c < 7; c += 2) { 4297 if (cap->speakers[c] || cap->speakers[c+1]) 4298 chanpairs++; 4299 } 4300 4301 if (chanpairs * 2 != channels) 4302 return -1; 4303 4304 return SNDRV_CTL_TLVT_CHMAP_PAIRED; 4305 } 4306 4307 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, 4308 struct hdac_cea_channel_speaker_allocation *cap, 4309 unsigned int *chmap, int channels) 4310 { 4311 /* produce paired maps for pre-rev3 ATI/AMD codecs */ 4312 int count = 0; 4313 int c; 4314 4315 for (c = 7; c >= 0; c--) { 4316 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); 4317 int spk = cap->speakers[chan]; 4318 if (!spk) { 4319 /* add N/A channel if the companion channel is occupied */ 4320 if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) 4321 chmap[count++] = SNDRV_CHMAP_NA; 4322 4323 continue; 4324 } 4325 4326 chmap[count++] = snd_hdac_spk_to_chmap(spk); 4327 } 4328 4329 WARN_ON(count != channels); 4330 } 4331 4332 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 4333 int dev_id, bool hbr) 4334 { 4335 int hbr_ctl, hbr_ctl_new; 4336 4337 WARN_ON(dev_id != 0); 4338 4339 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); 4340 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { 4341 if (hbr) 4342 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; 4343 else 4344 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; 4345 4346 codec_dbg(codec, 4347 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", 4348 pin_nid, 4349 hbr_ctl == hbr_ctl_new ? "" : "new-", 4350 hbr_ctl_new); 4351 4352 if (hbr_ctl != hbr_ctl_new) 4353 snd_hda_codec_write(codec, pin_nid, 0, 4354 ATI_VERB_SET_HBR_CONTROL, 4355 hbr_ctl_new); 4356 4357 } else if (hbr) 4358 return -EINVAL; 4359 4360 return 0; 4361 } 4362 4363 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 4364 hda_nid_t pin_nid, int dev_id, 4365 u32 stream_tag, int format) 4366 { 4367 if (is_amdhdmi_rev3_or_later(codec)) { 4368 int ramp_rate = 180; /* default as per AMD spec */ 4369 /* disable ramp-up/down for non-pcm as per AMD spec */ 4370 if (format & AC_FMT_TYPE_NON_PCM) 4371 ramp_rate = 0; 4372 4373 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); 4374 } 4375 4376 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 4377 stream_tag, format); 4378 } 4379 4380 4381 static int atihdmi_init(struct hda_codec *codec) 4382 { 4383 struct hdmi_spec *spec = codec->spec; 4384 int pin_idx, err; 4385 4386 err = generic_hdmi_init(codec); 4387 4388 if (err) 4389 return err; 4390 4391 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 4392 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 4393 4394 /* make sure downmix information in infoframe is zero */ 4395 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); 4396 4397 /* enable channel-wise remap mode if supported */ 4398 if (has_amd_full_remap_support(codec)) 4399 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 4400 ATI_VERB_SET_MULTICHANNEL_MODE, 4401 ATI_MULTICHANNEL_MODE_SINGLE); 4402 } 4403 codec->auto_runtime_pm = 1; 4404 4405 return 0; 4406 } 4407 4408 /* map from pin NID to port; port is 0-based */ 4409 /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */ 4410 static int atihdmi_pin2port(void *audio_ptr, int pin_nid) 4411 { 4412 return pin_nid / 2 - 1; 4413 } 4414 4415 /* reverse-map from port to pin NID: see above */ 4416 static int atihdmi_port2pin(struct hda_codec *codec, int port) 4417 { 4418 return port * 2 + 3; 4419 } 4420 4421 static const struct drm_audio_component_audio_ops atihdmi_audio_ops = { 4422 .pin2port = atihdmi_pin2port, 4423 .pin_eld_notify = generic_acomp_pin_eld_notify, 4424 .master_bind = generic_acomp_master_bind, 4425 .master_unbind = generic_acomp_master_unbind, 4426 }; 4427 4428 static int patch_atihdmi(struct hda_codec *codec) 4429 { 4430 struct hdmi_spec *spec; 4431 struct hdmi_spec_per_cvt *per_cvt; 4432 int err, cvt_idx; 4433 4434 err = patch_generic_hdmi(codec); 4435 4436 if (err) 4437 return err; 4438 4439 codec->patch_ops.init = atihdmi_init; 4440 4441 spec = codec->spec; 4442 4443 spec->static_pcm_mapping = true; 4444 4445 spec->ops.pin_get_eld = atihdmi_pin_get_eld; 4446 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; 4447 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; 4448 spec->ops.setup_stream = atihdmi_setup_stream; 4449 4450 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; 4451 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; 4452 4453 if (!has_amd_full_remap_support(codec)) { 4454 /* override to ATI/AMD-specific versions with pairwise mapping */ 4455 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4456 atihdmi_paired_chmap_cea_alloc_validate_get_type; 4457 spec->chmap.ops.cea_alloc_to_tlv_chmap = 4458 atihdmi_paired_cea_alloc_to_tlv_chmap; 4459 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; 4460 } 4461 4462 /* ATI/AMD converters do not advertise all of their capabilities */ 4463 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 4464 per_cvt = get_cvt(spec, cvt_idx); 4465 per_cvt->channels_max = max(per_cvt->channels_max, 8u); 4466 per_cvt->rates |= SUPPORTED_RATES; 4467 per_cvt->formats |= SUPPORTED_FORMATS; 4468 per_cvt->maxbps = max(per_cvt->maxbps, 24u); 4469 } 4470 4471 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); 4472 4473 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing 4474 * the link-down as is. Tell the core to allow it. 4475 */ 4476 codec->link_down_at_suspend = 1; 4477 4478 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin); 4479 4480 return 0; 4481 } 4482 4483 /* VIA HDMI Implementation */ 4484 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ 4485 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ 4486 4487 static int patch_via_hdmi(struct hda_codec *codec) 4488 { 4489 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); 4490 } 4491 4492 /* 4493 * patch entries 4494 */ 4495 static const struct hda_device_id snd_hda_id_hdmi[] = { 4496 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), 4497 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), 4498 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), 4499 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), 4500 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), 4501 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), 4502 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), 4503 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch), 4504 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4505 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4506 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x), 4507 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4508 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4509 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), 4510 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy), 4511 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy), 4512 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy), 4513 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy), 4514 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy), 4515 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy), 4516 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy), 4517 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy), 4518 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy), 4519 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy), 4520 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy), 4521 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy), 4522 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy), 4523 /* 17 is known to be absent */ 4524 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy), 4525 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy), 4526 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy), 4527 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy), 4528 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy), 4529 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), 4530 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), 4531 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), 4532 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), 4533 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi), 4534 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi), 4535 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), 4536 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), 4537 HDA_CODEC_ENTRY(0x10de0031, "Tegra234 HDMI/DP", patch_tegra234_hdmi), 4538 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), 4539 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), 4540 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), 4541 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), 4542 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), 4543 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi), 4544 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi), 4545 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), 4546 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi), 4547 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), 4548 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi), 4549 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi), 4550 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), 4551 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), 4552 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), 4553 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), 4554 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi), 4555 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi), 4556 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi), 4557 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi), 4558 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi), 4559 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), 4560 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi), 4561 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), 4562 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi), 4563 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), 4564 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), 4565 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi), 4566 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi), 4567 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi), 4568 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi), 4569 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi), 4570 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi), 4571 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi), 4572 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi), 4573 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), 4574 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), 4575 HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi), 4576 HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi), 4577 HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi), 4578 HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi), 4579 HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi), 4580 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), 4581 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), 4582 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), 4583 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), 4584 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), 4585 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), 4586 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4587 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), 4588 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), 4589 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), 4590 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), 4591 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4592 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), 4593 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), 4594 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), 4595 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), 4596 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), 4597 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), 4598 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), 4599 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), 4600 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), 4601 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi), 4602 HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi), 4603 HDA_CODEC_ENTRY(0x80862814, "DG1 HDMI", patch_i915_tgl_hdmi), 4604 HDA_CODEC_ENTRY(0x80862815, "Alderlake HDMI", patch_i915_tgl_hdmi), 4605 HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI", patch_i915_tgl_hdmi), 4606 HDA_CODEC_ENTRY(0x80862818, "Raptorlake HDMI", patch_i915_tgl_hdmi), 4607 HDA_CODEC_ENTRY(0x80862819, "DG2 HDMI", patch_i915_tgl_hdmi), 4608 HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi), 4609 HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi), 4610 HDA_CODEC_ENTRY(0x8086281c, "Alderlake-P HDMI", patch_i915_adlp_hdmi), 4611 HDA_CODEC_ENTRY(0x8086281f, "Raptorlake-P HDMI", patch_i915_adlp_hdmi), 4612 HDA_CODEC_ENTRY(0x8086281d, "Meteorlake HDMI", patch_i915_adlp_hdmi), 4613 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), 4614 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), 4615 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), 4616 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), 4617 /* special ID for generic HDMI */ 4618 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), 4619 {} /* terminator */ 4620 }; 4621 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); 4622 4623 MODULE_LICENSE("GPL"); 4624 MODULE_DESCRIPTION("HDMI HD-audio codec"); 4625 MODULE_ALIAS("snd-hda-codec-intelhdmi"); 4626 MODULE_ALIAS("snd-hda-codec-nvhdmi"); 4627 MODULE_ALIAS("snd-hda-codec-atihdmi"); 4628 4629 static struct hda_codec_driver hdmi_driver = { 4630 .id = snd_hda_id_hdmi, 4631 }; 4632 4633 module_hda_codec_driver(hdmi_driver); 4634