1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs 5 * 6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. 7 * Copyright (c) 2006 ATI Technologies Inc. 8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved. 9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com> 10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> 11 * 12 * Authors: 13 * Wu Fengguang <wfg@linux.intel.com> 14 * 15 * Maintained by: 16 * Wu Fengguang <wfg@linux.intel.com> 17 */ 18 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/pci.h> 22 #include <linux/slab.h> 23 #include <linux/module.h> 24 #include <linux/pm_runtime.h> 25 #include <sound/core.h> 26 #include <sound/jack.h> 27 #include <sound/asoundef.h> 28 #include <sound/tlv.h> 29 #include <sound/hdaudio.h> 30 #include <sound/hda_i915.h> 31 #include <sound/hda_chmap.h> 32 #include <sound/hda_codec.h> 33 #include "hda_local.h" 34 #include "hda_jack.h" 35 #include "hda_controller.h" 36 37 static bool static_hdmi_pcm; 38 module_param(static_hdmi_pcm, bool, 0644); 39 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); 40 41 static bool enable_acomp = true; 42 module_param(enable_acomp, bool, 0444); 43 MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)"); 44 45 static bool enable_silent_stream = 46 IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM); 47 module_param(enable_silent_stream, bool, 0644); 48 MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices"); 49 50 static bool enable_all_pins; 51 module_param(enable_all_pins, bool, 0444); 52 MODULE_PARM_DESC(enable_all_pins, "Forcibly enable all pins"); 53 54 struct hdmi_spec_per_cvt { 55 hda_nid_t cvt_nid; 56 bool assigned; /* the stream has been assigned */ 57 bool silent_stream; /* silent stream activated */ 58 unsigned int channels_min; 59 unsigned int channels_max; 60 u32 rates; 61 u64 formats; 62 unsigned int maxbps; 63 }; 64 65 /* max. connections to a widget */ 66 #define HDA_MAX_CONNECTIONS 32 67 68 struct hdmi_spec_per_pin { 69 hda_nid_t pin_nid; 70 int dev_id; 71 /* pin idx, different device entries on the same pin use the same idx */ 72 int pin_nid_idx; 73 int num_mux_nids; 74 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; 75 int mux_idx; 76 hda_nid_t cvt_nid; 77 78 struct hda_codec *codec; 79 struct hdmi_eld sink_eld; 80 struct mutex lock; 81 struct delayed_work work; 82 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ 83 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ 84 int prev_pcm_idx; /* previously assigned pcm index */ 85 int repoll_count; 86 bool setup; /* the stream has been set up by prepare callback */ 87 bool silent_stream; 88 int channels; /* current number of channels */ 89 bool non_pcm; 90 bool chmap_set; /* channel-map override by ALSA API? */ 91 unsigned char chmap[8]; /* ALSA API channel-map */ 92 #ifdef CONFIG_SND_PROC_FS 93 struct snd_info_entry *proc_entry; 94 #endif 95 }; 96 97 /* operations used by generic code that can be overridden by patches */ 98 struct hdmi_ops { 99 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, 100 int dev_id, unsigned char *buf, int *eld_size); 101 102 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, 103 int dev_id, 104 int ca, int active_channels, int conn_type); 105 106 /* enable/disable HBR (HD passthrough) */ 107 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, 108 int dev_id, bool hbr); 109 110 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, 111 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 112 int format); 113 114 void (*pin_cvt_fixup)(struct hda_codec *codec, 115 struct hdmi_spec_per_pin *per_pin, 116 hda_nid_t cvt_nid); 117 }; 118 119 struct hdmi_pcm { 120 struct hda_pcm *pcm; 121 struct snd_jack *jack; 122 struct snd_kcontrol *eld_ctl; 123 }; 124 125 enum { 126 SILENT_STREAM_OFF = 0, 127 SILENT_STREAM_KAE, /* use standard HDA Keep-Alive */ 128 SILENT_STREAM_I915, /* Intel i915 extension */ 129 }; 130 131 struct hdmi_spec { 132 struct hda_codec *codec; 133 int num_cvts; 134 struct snd_array cvts; /* struct hdmi_spec_per_cvt */ 135 hda_nid_t cvt_nids[4]; /* only for haswell fix */ 136 137 /* 138 * num_pins is the number of virtual pins 139 * for example, there are 3 pins, and each pin 140 * has 4 device entries, then the num_pins is 12 141 */ 142 int num_pins; 143 /* 144 * num_nids is the number of real pins 145 * In the above example, num_nids is 3 146 */ 147 int num_nids; 148 /* 149 * dev_num is the number of device entries 150 * on each pin. 151 * In the above example, dev_num is 4 152 */ 153 int dev_num; 154 struct snd_array pins; /* struct hdmi_spec_per_pin */ 155 struct hdmi_pcm pcm_rec[8]; 156 struct mutex pcm_lock; 157 struct mutex bind_lock; /* for audio component binding */ 158 /* pcm_bitmap means which pcms have been assigned to pins*/ 159 unsigned long pcm_bitmap; 160 int pcm_used; /* counter of pcm_rec[] */ 161 /* bitmap shows whether the pcm is opened in user space 162 * bit 0 means the first playback PCM (PCM3); 163 * bit 1 means the second playback PCM, and so on. 164 */ 165 unsigned long pcm_in_use; 166 167 struct hdmi_eld temp_eld; 168 struct hdmi_ops ops; 169 170 bool dyn_pin_out; 171 bool static_pcm_mapping; 172 /* hdmi interrupt trigger control flag for Nvidia codec */ 173 bool hdmi_intr_trig_ctrl; 174 bool nv_dp_workaround; /* workaround DP audio infoframe for Nvidia */ 175 176 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */ 177 /* 178 * Non-generic VIA/NVIDIA specific 179 */ 180 struct hda_multi_out multiout; 181 struct hda_pcm_stream pcm_playback; 182 183 bool use_acomp_notifier; /* use eld_notify callback for hotplug */ 184 bool acomp_registered; /* audio component registered in this driver */ 185 bool force_connect; /* force connectivity */ 186 struct drm_audio_component_audio_ops drm_audio_ops; 187 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */ 188 189 struct hdac_chmap chmap; 190 hda_nid_t vendor_nid; 191 const int *port_map; 192 int port_num; 193 int silent_stream_type; 194 }; 195 196 #ifdef CONFIG_SND_HDA_COMPONENT 197 static inline bool codec_has_acomp(struct hda_codec *codec) 198 { 199 struct hdmi_spec *spec = codec->spec; 200 return spec->use_acomp_notifier; 201 } 202 #else 203 #define codec_has_acomp(codec) false 204 #endif 205 206 struct hdmi_audio_infoframe { 207 u8 type; /* 0x84 */ 208 u8 ver; /* 0x01 */ 209 u8 len; /* 0x0a */ 210 211 u8 checksum; 212 213 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ 214 u8 SS01_SF24; 215 u8 CXT04; 216 u8 CA; 217 u8 LFEPBL01_LSV36_DM_INH7; 218 }; 219 220 struct dp_audio_infoframe { 221 u8 type; /* 0x84 */ 222 u8 len; /* 0x1b */ 223 u8 ver; /* 0x11 << 2 */ 224 225 u8 CC02_CT47; /* match with HDMI infoframe from this on */ 226 u8 SS01_SF24; 227 u8 CXT04; 228 u8 CA; 229 u8 LFEPBL01_LSV36_DM_INH7; 230 }; 231 232 union audio_infoframe { 233 struct hdmi_audio_infoframe hdmi; 234 struct dp_audio_infoframe dp; 235 DECLARE_FLEX_ARRAY(u8, bytes); 236 }; 237 238 /* 239 * HDMI routines 240 */ 241 242 #define get_pin(spec, idx) \ 243 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) 244 #define get_cvt(spec, idx) \ 245 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) 246 /* obtain hdmi_pcm object assigned to idx */ 247 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) 248 /* obtain hda_pcm object assigned to idx */ 249 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) 250 251 static int pin_id_to_pin_index(struct hda_codec *codec, 252 hda_nid_t pin_nid, int dev_id) 253 { 254 struct hdmi_spec *spec = codec->spec; 255 int pin_idx; 256 struct hdmi_spec_per_pin *per_pin; 257 258 /* 259 * (dev_id == -1) means it is NON-MST pin 260 * return the first virtual pin on this port 261 */ 262 if (dev_id == -1) 263 dev_id = 0; 264 265 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 266 per_pin = get_pin(spec, pin_idx); 267 if ((per_pin->pin_nid == pin_nid) && 268 (per_pin->dev_id == dev_id)) 269 return pin_idx; 270 } 271 272 codec_warn(codec, "HDMI: pin NID 0x%x not registered\n", pin_nid); 273 return -EINVAL; 274 } 275 276 static int hinfo_to_pcm_index(struct hda_codec *codec, 277 struct hda_pcm_stream *hinfo) 278 { 279 struct hdmi_spec *spec = codec->spec; 280 int pcm_idx; 281 282 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) 283 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) 284 return pcm_idx; 285 286 codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo); 287 return -EINVAL; 288 } 289 290 static int hinfo_to_pin_index(struct hda_codec *codec, 291 struct hda_pcm_stream *hinfo) 292 { 293 struct hdmi_spec *spec = codec->spec; 294 struct hdmi_spec_per_pin *per_pin; 295 int pin_idx; 296 297 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 298 per_pin = get_pin(spec, pin_idx); 299 if (per_pin->pcm && 300 per_pin->pcm->pcm->stream == hinfo) 301 return pin_idx; 302 } 303 304 codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo, 305 hinfo_to_pcm_index(codec, hinfo)); 306 return -EINVAL; 307 } 308 309 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, 310 int pcm_idx) 311 { 312 int i; 313 struct hdmi_spec_per_pin *per_pin; 314 315 for (i = 0; i < spec->num_pins; i++) { 316 per_pin = get_pin(spec, i); 317 if (per_pin->pcm_idx == pcm_idx) 318 return per_pin; 319 } 320 return NULL; 321 } 322 323 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) 324 { 325 struct hdmi_spec *spec = codec->spec; 326 int cvt_idx; 327 328 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) 329 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) 330 return cvt_idx; 331 332 codec_warn(codec, "HDMI: cvt NID 0x%x not registered\n", cvt_nid); 333 return -EINVAL; 334 } 335 336 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, 337 struct snd_ctl_elem_info *uinfo) 338 { 339 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 340 struct hdmi_spec *spec = codec->spec; 341 struct hdmi_spec_per_pin *per_pin; 342 struct hdmi_eld *eld; 343 int pcm_idx; 344 345 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 346 347 pcm_idx = kcontrol->private_value; 348 mutex_lock(&spec->pcm_lock); 349 per_pin = pcm_idx_to_pin(spec, pcm_idx); 350 if (!per_pin) { 351 /* no pin is bound to the pcm */ 352 uinfo->count = 0; 353 goto unlock; 354 } 355 eld = &per_pin->sink_eld; 356 uinfo->count = eld->eld_valid ? eld->eld_size : 0; 357 358 unlock: 359 mutex_unlock(&spec->pcm_lock); 360 return 0; 361 } 362 363 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, 364 struct snd_ctl_elem_value *ucontrol) 365 { 366 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 367 struct hdmi_spec *spec = codec->spec; 368 struct hdmi_spec_per_pin *per_pin; 369 struct hdmi_eld *eld; 370 int pcm_idx; 371 int err = 0; 372 373 pcm_idx = kcontrol->private_value; 374 mutex_lock(&spec->pcm_lock); 375 per_pin = pcm_idx_to_pin(spec, pcm_idx); 376 if (!per_pin) { 377 /* no pin is bound to the pcm */ 378 memset(ucontrol->value.bytes.data, 0, 379 ARRAY_SIZE(ucontrol->value.bytes.data)); 380 goto unlock; 381 } 382 383 eld = &per_pin->sink_eld; 384 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || 385 eld->eld_size > ELD_MAX_SIZE) { 386 snd_BUG(); 387 err = -EINVAL; 388 goto unlock; 389 } 390 391 memset(ucontrol->value.bytes.data, 0, 392 ARRAY_SIZE(ucontrol->value.bytes.data)); 393 if (eld->eld_valid) 394 memcpy(ucontrol->value.bytes.data, eld->eld_buffer, 395 eld->eld_size); 396 397 unlock: 398 mutex_unlock(&spec->pcm_lock); 399 return err; 400 } 401 402 static const struct snd_kcontrol_new eld_bytes_ctl = { 403 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE | 404 SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK, 405 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 406 .name = "ELD", 407 .info = hdmi_eld_ctl_info, 408 .get = hdmi_eld_ctl_get, 409 }; 410 411 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, 412 int device) 413 { 414 struct snd_kcontrol *kctl; 415 struct hdmi_spec *spec = codec->spec; 416 int err; 417 418 kctl = snd_ctl_new1(&eld_bytes_ctl, codec); 419 if (!kctl) 420 return -ENOMEM; 421 kctl->private_value = pcm_idx; 422 kctl->id.device = device; 423 424 /* no pin nid is associated with the kctl now 425 * tbd: associate pin nid to eld ctl later 426 */ 427 err = snd_hda_ctl_add(codec, 0, kctl); 428 if (err < 0) 429 return err; 430 431 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; 432 return 0; 433 } 434 435 #ifdef BE_PARANOID 436 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 437 int *packet_index, int *byte_index) 438 { 439 int val; 440 441 val = snd_hda_codec_read(codec, pin_nid, 0, 442 AC_VERB_GET_HDMI_DIP_INDEX, 0); 443 444 *packet_index = val >> 5; 445 *byte_index = val & 0x1f; 446 } 447 #endif 448 449 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 450 int packet_index, int byte_index) 451 { 452 int val; 453 454 val = (packet_index << 5) | (byte_index & 0x1f); 455 456 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); 457 } 458 459 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, 460 unsigned char val) 461 { 462 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); 463 } 464 465 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) 466 { 467 struct hdmi_spec *spec = codec->spec; 468 int pin_out; 469 470 /* Unmute */ 471 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 472 snd_hda_codec_write(codec, pin_nid, 0, 473 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); 474 475 if (spec->dyn_pin_out) 476 /* Disable pin out until stream is active */ 477 pin_out = 0; 478 else 479 /* Enable pin out: some machines with GM965 gets broken output 480 * when the pin is disabled or changed while using with HDMI 481 */ 482 pin_out = PIN_OUT; 483 484 snd_hda_codec_write(codec, pin_nid, 0, 485 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); 486 } 487 488 /* 489 * ELD proc files 490 */ 491 492 #ifdef CONFIG_SND_PROC_FS 493 static void print_eld_info(struct snd_info_entry *entry, 494 struct snd_info_buffer *buffer) 495 { 496 struct hdmi_spec_per_pin *per_pin = entry->private_data; 497 498 mutex_lock(&per_pin->lock); 499 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer, per_pin->pin_nid, 500 per_pin->dev_id, per_pin->cvt_nid); 501 mutex_unlock(&per_pin->lock); 502 } 503 504 static void write_eld_info(struct snd_info_entry *entry, 505 struct snd_info_buffer *buffer) 506 { 507 struct hdmi_spec_per_pin *per_pin = entry->private_data; 508 509 mutex_lock(&per_pin->lock); 510 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); 511 mutex_unlock(&per_pin->lock); 512 } 513 514 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) 515 { 516 char name[32]; 517 struct hda_codec *codec = per_pin->codec; 518 struct snd_info_entry *entry; 519 int err; 520 521 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); 522 err = snd_card_proc_new(codec->card, name, &entry); 523 if (err < 0) 524 return err; 525 526 snd_info_set_text_ops(entry, per_pin, print_eld_info); 527 entry->c.text.write = write_eld_info; 528 entry->mode |= 0200; 529 per_pin->proc_entry = entry; 530 531 return 0; 532 } 533 534 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 535 { 536 if (!per_pin->codec->bus->shutdown) { 537 snd_info_free_entry(per_pin->proc_entry); 538 per_pin->proc_entry = NULL; 539 } 540 } 541 #else 542 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, 543 int index) 544 { 545 return 0; 546 } 547 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 548 { 549 } 550 #endif 551 552 /* 553 * Audio InfoFrame routines 554 */ 555 556 /* 557 * Enable Audio InfoFrame Transmission 558 */ 559 static void hdmi_start_infoframe_trans(struct hda_codec *codec, 560 hda_nid_t pin_nid) 561 { 562 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 563 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 564 AC_DIPXMIT_BEST); 565 } 566 567 /* 568 * Disable Audio InfoFrame Transmission 569 */ 570 static void hdmi_stop_infoframe_trans(struct hda_codec *codec, 571 hda_nid_t pin_nid) 572 { 573 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 574 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 575 AC_DIPXMIT_DISABLE); 576 } 577 578 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) 579 { 580 #ifdef CONFIG_SND_DEBUG_VERBOSE 581 int i; 582 int size; 583 584 size = snd_hdmi_get_eld_size(codec, pin_nid); 585 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); 586 587 for (i = 0; i < 8; i++) { 588 size = snd_hda_codec_read(codec, pin_nid, 0, 589 AC_VERB_GET_HDMI_DIP_SIZE, i); 590 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); 591 } 592 #endif 593 } 594 595 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) 596 { 597 #ifdef BE_PARANOID 598 int i, j; 599 int size; 600 int pi, bi; 601 for (i = 0; i < 8; i++) { 602 size = snd_hda_codec_read(codec, pin_nid, 0, 603 AC_VERB_GET_HDMI_DIP_SIZE, i); 604 if (size == 0) 605 continue; 606 607 hdmi_set_dip_index(codec, pin_nid, i, 0x0); 608 for (j = 1; j < 1000; j++) { 609 hdmi_write_dip_byte(codec, pin_nid, 0x0); 610 hdmi_get_dip_index(codec, pin_nid, &pi, &bi); 611 if (pi != i) 612 codec_dbg(codec, "dip index %d: %d != %d\n", 613 bi, pi, i); 614 if (bi == 0) /* byte index wrapped around */ 615 break; 616 } 617 codec_dbg(codec, 618 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", 619 i, size, j); 620 } 621 #endif 622 } 623 624 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) 625 { 626 u8 *bytes = (u8 *)hdmi_ai; 627 u8 sum = 0; 628 int i; 629 630 hdmi_ai->checksum = 0; 631 632 for (i = 0; i < sizeof(*hdmi_ai); i++) 633 sum += bytes[i]; 634 635 hdmi_ai->checksum = -sum; 636 } 637 638 static void hdmi_fill_audio_infoframe(struct hda_codec *codec, 639 hda_nid_t pin_nid, 640 u8 *dip, int size) 641 { 642 int i; 643 644 hdmi_debug_dip_size(codec, pin_nid); 645 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ 646 647 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 648 for (i = 0; i < size; i++) 649 hdmi_write_dip_byte(codec, pin_nid, dip[i]); 650 } 651 652 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, 653 u8 *dip, int size) 654 { 655 u8 val; 656 int i; 657 658 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 659 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) 660 != AC_DIPXMIT_BEST) 661 return false; 662 663 for (i = 0; i < size; i++) { 664 val = snd_hda_codec_read(codec, pin_nid, 0, 665 AC_VERB_GET_HDMI_DIP_DATA, 0); 666 if (val != dip[i]) 667 return false; 668 } 669 670 return true; 671 } 672 673 static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 674 int dev_id, unsigned char *buf, int *eld_size) 675 { 676 snd_hda_set_dev_select(codec, nid, dev_id); 677 678 return snd_hdmi_get_eld(codec, nid, buf, eld_size); 679 } 680 681 static void hdmi_pin_setup_infoframe(struct hda_codec *codec, 682 hda_nid_t pin_nid, int dev_id, 683 int ca, int active_channels, 684 int conn_type) 685 { 686 struct hdmi_spec *spec = codec->spec; 687 union audio_infoframe ai; 688 689 memset(&ai, 0, sizeof(ai)); 690 if ((conn_type == 0) || /* HDMI */ 691 /* Nvidia DisplayPort: Nvidia HW expects same layout as HDMI */ 692 (conn_type == 1 && spec->nv_dp_workaround)) { 693 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; 694 695 if (conn_type == 0) { /* HDMI */ 696 hdmi_ai->type = 0x84; 697 hdmi_ai->ver = 0x01; 698 hdmi_ai->len = 0x0a; 699 } else {/* Nvidia DP */ 700 hdmi_ai->type = 0x84; 701 hdmi_ai->ver = 0x1b; 702 hdmi_ai->len = 0x11 << 2; 703 } 704 hdmi_ai->CC02_CT47 = active_channels - 1; 705 hdmi_ai->CA = ca; 706 hdmi_checksum_audio_infoframe(hdmi_ai); 707 } else if (conn_type == 1) { /* DisplayPort */ 708 struct dp_audio_infoframe *dp_ai = &ai.dp; 709 710 dp_ai->type = 0x84; 711 dp_ai->len = 0x1b; 712 dp_ai->ver = 0x11 << 2; 713 dp_ai->CC02_CT47 = active_channels - 1; 714 dp_ai->CA = ca; 715 } else { 716 codec_dbg(codec, "HDMI: unknown connection type at pin NID 0x%x\n", pin_nid); 717 return; 718 } 719 720 snd_hda_set_dev_select(codec, pin_nid, dev_id); 721 722 /* 723 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or 724 * sizeof(*dp_ai) to avoid partial match/update problems when 725 * the user switches between HDMI/DP monitors. 726 */ 727 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, 728 sizeof(ai))) { 729 codec_dbg(codec, "%s: pin NID=0x%x channels=%d ca=0x%02x\n", 730 __func__, pin_nid, active_channels, ca); 731 hdmi_stop_infoframe_trans(codec, pin_nid); 732 hdmi_fill_audio_infoframe(codec, pin_nid, 733 ai.bytes, sizeof(ai)); 734 hdmi_start_infoframe_trans(codec, pin_nid); 735 } 736 } 737 738 static void hdmi_setup_audio_infoframe(struct hda_codec *codec, 739 struct hdmi_spec_per_pin *per_pin, 740 bool non_pcm) 741 { 742 struct hdmi_spec *spec = codec->spec; 743 struct hdac_chmap *chmap = &spec->chmap; 744 hda_nid_t pin_nid = per_pin->pin_nid; 745 int dev_id = per_pin->dev_id; 746 int channels = per_pin->channels; 747 int active_channels; 748 struct hdmi_eld *eld; 749 int ca; 750 751 if (!channels) 752 return; 753 754 snd_hda_set_dev_select(codec, pin_nid, dev_id); 755 756 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ 757 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 758 snd_hda_codec_write(codec, pin_nid, 0, 759 AC_VERB_SET_AMP_GAIN_MUTE, 760 AMP_OUT_UNMUTE); 761 762 eld = &per_pin->sink_eld; 763 764 ca = snd_hdac_channel_allocation(&codec->core, 765 eld->info.spk_alloc, channels, 766 per_pin->chmap_set, non_pcm, per_pin->chmap); 767 768 active_channels = snd_hdac_get_active_channels(ca); 769 770 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, 771 active_channels); 772 773 /* 774 * always configure channel mapping, it may have been changed by the 775 * user in the meantime 776 */ 777 snd_hdac_setup_channel_mapping(&spec->chmap, 778 pin_nid, non_pcm, ca, channels, 779 per_pin->chmap, per_pin->chmap_set); 780 781 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id, 782 ca, active_channels, eld->info.conn_type); 783 784 per_pin->non_pcm = non_pcm; 785 } 786 787 /* 788 * Unsolicited events 789 */ 790 791 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); 792 793 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, 794 int dev_id) 795 { 796 struct hdmi_spec *spec = codec->spec; 797 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); 798 799 if (pin_idx < 0) 800 return; 801 mutex_lock(&spec->pcm_lock); 802 hdmi_present_sense(get_pin(spec, pin_idx), 1); 803 mutex_unlock(&spec->pcm_lock); 804 } 805 806 static void jack_callback(struct hda_codec *codec, 807 struct hda_jack_callback *jack) 808 { 809 /* stop polling when notification is enabled */ 810 if (codec_has_acomp(codec)) 811 return; 812 813 check_presence_and_report(codec, jack->nid, jack->dev_id); 814 } 815 816 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res, 817 struct hda_jack_tbl *jack) 818 { 819 jack->jack_dirty = 1; 820 821 codec_dbg(codec, 822 "HDMI hot plug event: Codec=%d NID=0x%x Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", 823 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA), 824 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); 825 826 check_presence_and_report(codec, jack->nid, jack->dev_id); 827 } 828 829 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) 830 { 831 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 832 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 833 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); 834 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); 835 836 codec_info(codec, 837 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", 838 codec->addr, 839 tag, 840 subtag, 841 cp_state, 842 cp_ready); 843 844 /* TODO */ 845 if (cp_state) { 846 ; 847 } 848 if (cp_ready) { 849 ; 850 } 851 } 852 853 854 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) 855 { 856 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 857 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 858 struct hda_jack_tbl *jack; 859 860 if (codec_has_acomp(codec)) 861 return; 862 863 if (codec->dp_mst) { 864 int dev_entry = 865 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 866 867 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry); 868 } else { 869 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0); 870 } 871 872 if (!jack) { 873 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); 874 return; 875 } 876 877 if (subtag == 0) 878 hdmi_intrinsic_event(codec, res, jack); 879 else 880 hdmi_non_intrinsic_event(codec, res); 881 } 882 883 static void haswell_verify_D0(struct hda_codec *codec, 884 hda_nid_t cvt_nid, hda_nid_t nid) 885 { 886 int pwr; 887 888 /* For Haswell, the converter 1/2 may keep in D3 state after bootup, 889 * thus pins could only choose converter 0 for use. Make sure the 890 * converters are in correct power state */ 891 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) 892 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); 893 894 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { 895 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, 896 AC_PWRST_D0); 897 msleep(40); 898 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); 899 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; 900 codec_dbg(codec, "Haswell HDMI audio: Power for NID 0x%x is now D%d\n", nid, pwr); 901 } 902 } 903 904 /* 905 * Callbacks 906 */ 907 908 /* HBR should be Non-PCM, 8 channels */ 909 #define is_hbr_format(format) \ 910 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) 911 912 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 913 int dev_id, bool hbr) 914 { 915 int pinctl, new_pinctl; 916 917 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { 918 snd_hda_set_dev_select(codec, pin_nid, dev_id); 919 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 920 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 921 922 if (pinctl < 0) 923 return hbr ? -EINVAL : 0; 924 925 new_pinctl = pinctl & ~AC_PINCTL_EPT; 926 if (hbr) 927 new_pinctl |= AC_PINCTL_EPT_HBR; 928 else 929 new_pinctl |= AC_PINCTL_EPT_NATIVE; 930 931 codec_dbg(codec, 932 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", 933 pin_nid, 934 pinctl == new_pinctl ? "" : "new-", 935 new_pinctl); 936 937 if (pinctl != new_pinctl) 938 snd_hda_codec_write(codec, pin_nid, 0, 939 AC_VERB_SET_PIN_WIDGET_CONTROL, 940 new_pinctl); 941 } else if (hbr) 942 return -EINVAL; 943 944 return 0; 945 } 946 947 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 948 hda_nid_t pin_nid, int dev_id, 949 u32 stream_tag, int format) 950 { 951 struct hdmi_spec *spec = codec->spec; 952 unsigned int param; 953 int err; 954 955 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id, 956 is_hbr_format(format)); 957 958 if (err) { 959 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); 960 return err; 961 } 962 963 if (spec->intel_hsw_fixup) { 964 965 /* 966 * on recent platforms IEC Coding Type is required for HBR 967 * support, read current Digital Converter settings and set 968 * ICT bitfield if needed. 969 */ 970 param = snd_hda_codec_read(codec, cvt_nid, 0, 971 AC_VERB_GET_DIGI_CONVERT_1, 0); 972 973 param = (param >> 16) & ~(AC_DIG3_ICT); 974 975 /* on recent platforms ICT mode is required for HBR support */ 976 if (is_hbr_format(format)) 977 param |= 0x1; 978 979 snd_hda_codec_write(codec, cvt_nid, 0, 980 AC_VERB_SET_DIGI_CONVERT_3, param); 981 } 982 983 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); 984 return 0; 985 } 986 987 /* Try to find an available converter 988 * If pin_idx is less then zero, just try to find an available converter. 989 * Otherwise, try to find an available converter and get the cvt mux index 990 * of the pin. 991 */ 992 static int hdmi_choose_cvt(struct hda_codec *codec, 993 int pin_idx, int *cvt_id, 994 bool silent) 995 { 996 struct hdmi_spec *spec = codec->spec; 997 struct hdmi_spec_per_pin *per_pin; 998 struct hdmi_spec_per_cvt *per_cvt = NULL; 999 int cvt_idx, mux_idx = 0; 1000 1001 /* pin_idx < 0 means no pin will be bound to the converter */ 1002 if (pin_idx < 0) 1003 per_pin = NULL; 1004 else 1005 per_pin = get_pin(spec, pin_idx); 1006 1007 if (per_pin && per_pin->silent_stream) { 1008 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid); 1009 per_cvt = get_cvt(spec, cvt_idx); 1010 if (per_cvt->assigned && !silent) 1011 return -EBUSY; 1012 if (cvt_id) 1013 *cvt_id = cvt_idx; 1014 return 0; 1015 } 1016 1017 /* Dynamically assign converter to stream */ 1018 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1019 per_cvt = get_cvt(spec, cvt_idx); 1020 1021 /* Must not already be assigned */ 1022 if (per_cvt->assigned || per_cvt->silent_stream) 1023 continue; 1024 if (per_pin == NULL) 1025 break; 1026 /* Must be in pin's mux's list of converters */ 1027 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1028 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) 1029 break; 1030 /* Not in mux list */ 1031 if (mux_idx == per_pin->num_mux_nids) 1032 continue; 1033 break; 1034 } 1035 1036 /* No free converters */ 1037 if (cvt_idx == spec->num_cvts) 1038 return -EBUSY; 1039 1040 if (per_pin != NULL) 1041 per_pin->mux_idx = mux_idx; 1042 1043 if (cvt_id) 1044 *cvt_id = cvt_idx; 1045 1046 return 0; 1047 } 1048 1049 /* Assure the pin select the right convetor */ 1050 static void intel_verify_pin_cvt_connect(struct hda_codec *codec, 1051 struct hdmi_spec_per_pin *per_pin) 1052 { 1053 hda_nid_t pin_nid = per_pin->pin_nid; 1054 int mux_idx, curr; 1055 1056 mux_idx = per_pin->mux_idx; 1057 curr = snd_hda_codec_read(codec, pin_nid, 0, 1058 AC_VERB_GET_CONNECT_SEL, 0); 1059 if (curr != mux_idx) 1060 snd_hda_codec_write_cache(codec, pin_nid, 0, 1061 AC_VERB_SET_CONNECT_SEL, 1062 mux_idx); 1063 } 1064 1065 /* get the mux index for the converter of the pins 1066 * converter's mux index is the same for all pins on Intel platform 1067 */ 1068 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, 1069 hda_nid_t cvt_nid) 1070 { 1071 int i; 1072 1073 for (i = 0; i < spec->num_cvts; i++) 1074 if (spec->cvt_nids[i] == cvt_nid) 1075 return i; 1076 return -EINVAL; 1077 } 1078 1079 /* Intel HDMI workaround to fix audio routing issue: 1080 * For some Intel display codecs, pins share the same connection list. 1081 * So a conveter can be selected by multiple pins and playback on any of these 1082 * pins will generate sound on the external display, because audio flows from 1083 * the same converter to the display pipeline. Also muting one pin may make 1084 * other pins have no sound output. 1085 * So this function assures that an assigned converter for a pin is not selected 1086 * by any other pins. 1087 */ 1088 static void intel_not_share_assigned_cvt(struct hda_codec *codec, 1089 hda_nid_t pin_nid, 1090 int dev_id, int mux_idx) 1091 { 1092 struct hdmi_spec *spec = codec->spec; 1093 hda_nid_t nid; 1094 int cvt_idx, curr; 1095 struct hdmi_spec_per_cvt *per_cvt; 1096 struct hdmi_spec_per_pin *per_pin; 1097 int pin_idx; 1098 1099 /* configure the pins connections */ 1100 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 1101 int dev_id_saved; 1102 int dev_num; 1103 1104 per_pin = get_pin(spec, pin_idx); 1105 /* 1106 * pin not connected to monitor 1107 * no need to operate on it 1108 */ 1109 if (!per_pin->pcm) 1110 continue; 1111 1112 if ((per_pin->pin_nid == pin_nid) && 1113 (per_pin->dev_id == dev_id)) 1114 continue; 1115 1116 /* 1117 * if per_pin->dev_id >= dev_num, 1118 * snd_hda_get_dev_select() will fail, 1119 * and the following operation is unpredictable. 1120 * So skip this situation. 1121 */ 1122 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; 1123 if (per_pin->dev_id >= dev_num) 1124 continue; 1125 1126 nid = per_pin->pin_nid; 1127 1128 /* 1129 * Calling this function should not impact 1130 * on the device entry selection 1131 * So let's save the dev id for each pin, 1132 * and restore it when return 1133 */ 1134 dev_id_saved = snd_hda_get_dev_select(codec, nid); 1135 snd_hda_set_dev_select(codec, nid, per_pin->dev_id); 1136 curr = snd_hda_codec_read(codec, nid, 0, 1137 AC_VERB_GET_CONNECT_SEL, 0); 1138 if (curr != mux_idx) { 1139 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1140 continue; 1141 } 1142 1143 1144 /* choose an unassigned converter. The conveters in the 1145 * connection list are in the same order as in the codec. 1146 */ 1147 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1148 per_cvt = get_cvt(spec, cvt_idx); 1149 if (!per_cvt->assigned) { 1150 codec_dbg(codec, 1151 "choose cvt %d for pin NID 0x%x\n", 1152 cvt_idx, nid); 1153 snd_hda_codec_write_cache(codec, nid, 0, 1154 AC_VERB_SET_CONNECT_SEL, 1155 cvt_idx); 1156 break; 1157 } 1158 } 1159 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1160 } 1161 } 1162 1163 /* A wrapper of intel_not_share_asigned_cvt() */ 1164 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, 1165 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) 1166 { 1167 int mux_idx; 1168 struct hdmi_spec *spec = codec->spec; 1169 1170 /* On Intel platform, the mapping of converter nid to 1171 * mux index of the pins are always the same. 1172 * The pin nid may be 0, this means all pins will not 1173 * share the converter. 1174 */ 1175 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); 1176 if (mux_idx >= 0) 1177 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); 1178 } 1179 1180 /* skeleton caller of pin_cvt_fixup ops */ 1181 static void pin_cvt_fixup(struct hda_codec *codec, 1182 struct hdmi_spec_per_pin *per_pin, 1183 hda_nid_t cvt_nid) 1184 { 1185 struct hdmi_spec *spec = codec->spec; 1186 1187 if (spec->ops.pin_cvt_fixup) 1188 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); 1189 } 1190 1191 /* called in hdmi_pcm_open when no pin is assigned to the PCM */ 1192 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, 1193 struct hda_codec *codec, 1194 struct snd_pcm_substream *substream) 1195 { 1196 struct hdmi_spec *spec = codec->spec; 1197 struct snd_pcm_runtime *runtime = substream->runtime; 1198 int cvt_idx, pcm_idx; 1199 struct hdmi_spec_per_cvt *per_cvt = NULL; 1200 int err; 1201 1202 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1203 if (pcm_idx < 0) 1204 return -EINVAL; 1205 1206 err = hdmi_choose_cvt(codec, -1, &cvt_idx, false); 1207 if (err) 1208 return err; 1209 1210 per_cvt = get_cvt(spec, cvt_idx); 1211 per_cvt->assigned = true; 1212 hinfo->nid = per_cvt->cvt_nid; 1213 1214 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); 1215 1216 set_bit(pcm_idx, &spec->pcm_in_use); 1217 /* todo: setup spdif ctls assign */ 1218 1219 /* Initially set the converter's capabilities */ 1220 hinfo->channels_min = per_cvt->channels_min; 1221 hinfo->channels_max = per_cvt->channels_max; 1222 hinfo->rates = per_cvt->rates; 1223 hinfo->formats = per_cvt->formats; 1224 hinfo->maxbps = per_cvt->maxbps; 1225 1226 /* Store the updated parameters */ 1227 runtime->hw.channels_min = hinfo->channels_min; 1228 runtime->hw.channels_max = hinfo->channels_max; 1229 runtime->hw.formats = hinfo->formats; 1230 runtime->hw.rates = hinfo->rates; 1231 1232 snd_pcm_hw_constraint_step(substream->runtime, 0, 1233 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1234 return 0; 1235 } 1236 1237 /* 1238 * HDA PCM callbacks 1239 */ 1240 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, 1241 struct hda_codec *codec, 1242 struct snd_pcm_substream *substream) 1243 { 1244 struct hdmi_spec *spec = codec->spec; 1245 struct snd_pcm_runtime *runtime = substream->runtime; 1246 int pin_idx, cvt_idx, pcm_idx; 1247 struct hdmi_spec_per_pin *per_pin; 1248 struct hdmi_eld *eld; 1249 struct hdmi_spec_per_cvt *per_cvt = NULL; 1250 int err; 1251 1252 /* Validate hinfo */ 1253 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1254 if (pcm_idx < 0) 1255 return -EINVAL; 1256 1257 mutex_lock(&spec->pcm_lock); 1258 pin_idx = hinfo_to_pin_index(codec, hinfo); 1259 /* no pin is assigned to the PCM 1260 * PA need pcm open successfully when probe 1261 */ 1262 if (pin_idx < 0) { 1263 err = hdmi_pcm_open_no_pin(hinfo, codec, substream); 1264 goto unlock; 1265 } 1266 1267 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, false); 1268 if (err < 0) 1269 goto unlock; 1270 1271 per_cvt = get_cvt(spec, cvt_idx); 1272 /* Claim converter */ 1273 per_cvt->assigned = true; 1274 1275 set_bit(pcm_idx, &spec->pcm_in_use); 1276 per_pin = get_pin(spec, pin_idx); 1277 per_pin->cvt_nid = per_cvt->cvt_nid; 1278 hinfo->nid = per_cvt->cvt_nid; 1279 1280 /* flip stripe flag for the assigned stream if supported */ 1281 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE) 1282 azx_stream(get_azx_dev(substream))->stripe = 1; 1283 1284 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1285 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1286 AC_VERB_SET_CONNECT_SEL, 1287 per_pin->mux_idx); 1288 1289 /* configure unused pins to choose other converters */ 1290 pin_cvt_fixup(codec, per_pin, 0); 1291 1292 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); 1293 1294 /* Initially set the converter's capabilities */ 1295 hinfo->channels_min = per_cvt->channels_min; 1296 hinfo->channels_max = per_cvt->channels_max; 1297 hinfo->rates = per_cvt->rates; 1298 hinfo->formats = per_cvt->formats; 1299 hinfo->maxbps = per_cvt->maxbps; 1300 1301 eld = &per_pin->sink_eld; 1302 /* Restrict capabilities by ELD if this isn't disabled */ 1303 if (!static_hdmi_pcm && eld->eld_valid) { 1304 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); 1305 if (hinfo->channels_min > hinfo->channels_max || 1306 !hinfo->rates || !hinfo->formats) { 1307 per_cvt->assigned = false; 1308 hinfo->nid = 0; 1309 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1310 err = -ENODEV; 1311 goto unlock; 1312 } 1313 } 1314 1315 /* Store the updated parameters */ 1316 runtime->hw.channels_min = hinfo->channels_min; 1317 runtime->hw.channels_max = hinfo->channels_max; 1318 runtime->hw.formats = hinfo->formats; 1319 runtime->hw.rates = hinfo->rates; 1320 1321 snd_pcm_hw_constraint_step(substream->runtime, 0, 1322 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1323 unlock: 1324 mutex_unlock(&spec->pcm_lock); 1325 return err; 1326 } 1327 1328 /* 1329 * HDA/HDMI auto parsing 1330 */ 1331 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) 1332 { 1333 struct hdmi_spec *spec = codec->spec; 1334 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1335 hda_nid_t pin_nid = per_pin->pin_nid; 1336 int dev_id = per_pin->dev_id; 1337 int conns; 1338 1339 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { 1340 codec_warn(codec, 1341 "HDMI: pin NID 0x%x wcaps %#x does not support connection list\n", 1342 pin_nid, get_wcaps(codec, pin_nid)); 1343 return -EINVAL; 1344 } 1345 1346 snd_hda_set_dev_select(codec, pin_nid, dev_id); 1347 1348 if (spec->intel_hsw_fixup) { 1349 conns = spec->num_cvts; 1350 memcpy(per_pin->mux_nids, spec->cvt_nids, 1351 sizeof(hda_nid_t) * conns); 1352 } else { 1353 conns = snd_hda_get_raw_connections(codec, pin_nid, 1354 per_pin->mux_nids, 1355 HDA_MAX_CONNECTIONS); 1356 } 1357 1358 /* all the device entries on the same pin have the same conn list */ 1359 per_pin->num_mux_nids = conns; 1360 1361 return 0; 1362 } 1363 1364 static int hdmi_find_pcm_slot(struct hdmi_spec *spec, 1365 struct hdmi_spec_per_pin *per_pin) 1366 { 1367 int i; 1368 1369 for (i = 0; i < spec->pcm_used; i++) { 1370 if (!test_bit(i, &spec->pcm_bitmap)) 1371 return i; 1372 } 1373 return -EBUSY; 1374 } 1375 1376 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, 1377 struct hdmi_spec_per_pin *per_pin) 1378 { 1379 int idx; 1380 1381 /* pcm already be attached to the pin */ 1382 if (per_pin->pcm) 1383 return; 1384 /* try the previously used slot at first */ 1385 idx = per_pin->prev_pcm_idx; 1386 if (idx >= 0) { 1387 if (!test_bit(idx, &spec->pcm_bitmap)) 1388 goto found; 1389 per_pin->prev_pcm_idx = -1; /* no longer valid, clear it */ 1390 } 1391 idx = hdmi_find_pcm_slot(spec, per_pin); 1392 if (idx == -EBUSY) 1393 return; 1394 found: 1395 per_pin->pcm_idx = idx; 1396 per_pin->pcm = get_hdmi_pcm(spec, idx); 1397 set_bit(idx, &spec->pcm_bitmap); 1398 } 1399 1400 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, 1401 struct hdmi_spec_per_pin *per_pin) 1402 { 1403 int idx; 1404 1405 /* pcm already be detached from the pin */ 1406 if (!per_pin->pcm) 1407 return; 1408 idx = per_pin->pcm_idx; 1409 per_pin->pcm_idx = -1; 1410 per_pin->prev_pcm_idx = idx; /* remember the previous index */ 1411 per_pin->pcm = NULL; 1412 if (idx >= 0 && idx < spec->pcm_used) 1413 clear_bit(idx, &spec->pcm_bitmap); 1414 } 1415 1416 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, 1417 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) 1418 { 1419 int mux_idx; 1420 1421 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1422 if (per_pin->mux_nids[mux_idx] == cvt_nid) 1423 break; 1424 return mux_idx; 1425 } 1426 1427 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); 1428 1429 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, 1430 struct hdmi_spec_per_pin *per_pin) 1431 { 1432 struct hda_codec *codec = per_pin->codec; 1433 struct hda_pcm *pcm; 1434 struct hda_pcm_stream *hinfo; 1435 struct snd_pcm_substream *substream; 1436 int mux_idx; 1437 bool non_pcm; 1438 1439 if (per_pin->pcm_idx < 0 || per_pin->pcm_idx >= spec->pcm_used) 1440 return; 1441 pcm = get_pcm_rec(spec, per_pin->pcm_idx); 1442 if (!pcm->pcm) 1443 return; 1444 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) 1445 return; 1446 1447 /* hdmi audio only uses playback and one substream */ 1448 hinfo = pcm->stream; 1449 substream = pcm->pcm->streams[0].substream; 1450 1451 per_pin->cvt_nid = hinfo->nid; 1452 1453 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); 1454 if (mux_idx < per_pin->num_mux_nids) { 1455 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1456 per_pin->dev_id); 1457 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1458 AC_VERB_SET_CONNECT_SEL, 1459 mux_idx); 1460 } 1461 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); 1462 1463 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); 1464 if (substream->runtime) 1465 per_pin->channels = substream->runtime->channels; 1466 per_pin->setup = true; 1467 per_pin->mux_idx = mux_idx; 1468 1469 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1470 } 1471 1472 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, 1473 struct hdmi_spec_per_pin *per_pin) 1474 { 1475 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1476 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); 1477 1478 per_pin->chmap_set = false; 1479 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1480 1481 per_pin->setup = false; 1482 per_pin->channels = 0; 1483 } 1484 1485 static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec, 1486 struct hdmi_spec_per_pin *per_pin) 1487 { 1488 struct hdmi_spec *spec = codec->spec; 1489 1490 if (per_pin->pcm_idx >= 0) 1491 return spec->pcm_rec[per_pin->pcm_idx].jack; 1492 else 1493 return NULL; 1494 } 1495 1496 /* update per_pin ELD from the given new ELD; 1497 * setup info frame and notification accordingly 1498 * also notify ELD kctl and report jack status changes 1499 */ 1500 static void update_eld(struct hda_codec *codec, 1501 struct hdmi_spec_per_pin *per_pin, 1502 struct hdmi_eld *eld, 1503 int repoll) 1504 { 1505 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 1506 struct hdmi_spec *spec = codec->spec; 1507 struct snd_jack *pcm_jack; 1508 bool old_eld_valid = pin_eld->eld_valid; 1509 bool eld_changed; 1510 int pcm_idx; 1511 1512 if (eld->eld_valid) { 1513 if (eld->eld_size <= 0 || 1514 snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, 1515 eld->eld_size) < 0) { 1516 eld->eld_valid = false; 1517 if (repoll) { 1518 schedule_delayed_work(&per_pin->work, 1519 msecs_to_jiffies(300)); 1520 return; 1521 } 1522 } 1523 } 1524 1525 if (!eld->eld_valid || eld->eld_size <= 0 || eld->info.sad_count <= 0) { 1526 eld->eld_valid = false; 1527 eld->eld_size = 0; 1528 } 1529 1530 /* for monitor disconnection, save pcm_idx firstly */ 1531 pcm_idx = per_pin->pcm_idx; 1532 1533 /* 1534 * pcm_idx >=0 before update_eld() means it is in monitor 1535 * disconnected event. Jack must be fetched before update_eld(). 1536 */ 1537 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); 1538 1539 if (!spec->static_pcm_mapping) { 1540 if (eld->eld_valid) { 1541 hdmi_attach_hda_pcm(spec, per_pin); 1542 hdmi_pcm_setup_pin(spec, per_pin); 1543 } else { 1544 hdmi_pcm_reset_pin(spec, per_pin); 1545 hdmi_detach_hda_pcm(spec, per_pin); 1546 } 1547 } 1548 1549 /* if pcm_idx == -1, it means this is in monitor connection event 1550 * we can get the correct pcm_idx now. 1551 */ 1552 if (pcm_idx == -1) 1553 pcm_idx = per_pin->pcm_idx; 1554 if (!pcm_jack) 1555 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); 1556 1557 if (eld->eld_valid) 1558 snd_hdmi_show_eld(codec, &eld->info); 1559 1560 eld_changed = (pin_eld->eld_valid != eld->eld_valid); 1561 eld_changed |= (pin_eld->monitor_present != eld->monitor_present); 1562 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid) 1563 if (pin_eld->eld_size != eld->eld_size || 1564 memcmp(pin_eld->eld_buffer, eld->eld_buffer, 1565 eld->eld_size) != 0) 1566 eld_changed = true; 1567 1568 if (eld_changed) { 1569 pin_eld->monitor_present = eld->monitor_present; 1570 pin_eld->eld_valid = eld->eld_valid; 1571 pin_eld->eld_size = eld->eld_size; 1572 if (eld->eld_valid) 1573 memcpy(pin_eld->eld_buffer, eld->eld_buffer, 1574 eld->eld_size); 1575 pin_eld->info = eld->info; 1576 } 1577 1578 /* 1579 * Re-setup pin and infoframe. This is needed e.g. when 1580 * - sink is first plugged-in 1581 * - transcoder can change during stream playback on Haswell 1582 * and this can make HW reset converter selection on a pin. 1583 */ 1584 if (eld->eld_valid && !old_eld_valid && per_pin->setup) { 1585 pin_cvt_fixup(codec, per_pin, 0); 1586 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1587 } 1588 1589 if (eld_changed && pcm_idx >= 0) 1590 snd_ctl_notify(codec->card, 1591 SNDRV_CTL_EVENT_MASK_VALUE | 1592 SNDRV_CTL_EVENT_MASK_INFO, 1593 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); 1594 1595 if (eld_changed && pcm_jack) 1596 snd_jack_report(pcm_jack, 1597 (eld->monitor_present && eld->eld_valid) ? 1598 SND_JACK_AVOUT : 0); 1599 } 1600 1601 /* update ELD and jack state via HD-audio verbs */ 1602 static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, 1603 int repoll) 1604 { 1605 struct hda_codec *codec = per_pin->codec; 1606 struct hdmi_spec *spec = codec->spec; 1607 struct hdmi_eld *eld = &spec->temp_eld; 1608 struct device *dev = hda_codec_dev(codec); 1609 hda_nid_t pin_nid = per_pin->pin_nid; 1610 int dev_id = per_pin->dev_id; 1611 /* 1612 * Always execute a GetPinSense verb here, even when called from 1613 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited 1614 * response's PD bit is not the real PD value, but indicates that 1615 * the real PD value changed. An older version of the HD-audio 1616 * specification worked this way. Hence, we just ignore the data in 1617 * the unsolicited response to avoid custom WARs. 1618 */ 1619 int present; 1620 int ret; 1621 1622 #ifdef CONFIG_PM 1623 if (dev->power.runtime_status == RPM_SUSPENDING) 1624 return; 1625 #endif 1626 1627 ret = snd_hda_power_up_pm(codec); 1628 if (ret < 0 && pm_runtime_suspended(dev)) 1629 goto out; 1630 1631 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id); 1632 1633 mutex_lock(&per_pin->lock); 1634 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); 1635 if (eld->monitor_present) 1636 eld->eld_valid = !!(present & AC_PINSENSE_ELDV); 1637 else 1638 eld->eld_valid = false; 1639 1640 codec_dbg(codec, 1641 "HDMI status: Codec=%d NID=0x%x Presence_Detect=%d ELD_Valid=%d\n", 1642 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); 1643 1644 if (eld->eld_valid) { 1645 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id, 1646 eld->eld_buffer, &eld->eld_size) < 0) 1647 eld->eld_valid = false; 1648 } 1649 1650 update_eld(codec, per_pin, eld, repoll); 1651 mutex_unlock(&per_pin->lock); 1652 out: 1653 snd_hda_power_down_pm(codec); 1654 } 1655 1656 #define I915_SILENT_RATE 48000 1657 #define I915_SILENT_CHANNELS 2 1658 #define I915_SILENT_FORMAT SNDRV_PCM_FORMAT_S16_LE 1659 #define I915_SILENT_FORMAT_BITS 16 1660 #define I915_SILENT_FMT_MASK 0xf 1661 1662 static void silent_stream_enable_i915(struct hda_codec *codec, 1663 struct hdmi_spec_per_pin *per_pin) 1664 { 1665 unsigned int format; 1666 1667 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, 1668 per_pin->dev_id, I915_SILENT_RATE); 1669 1670 /* trigger silent stream generation in hw */ 1671 format = snd_hdac_calc_stream_format(I915_SILENT_RATE, I915_SILENT_CHANNELS, 1672 I915_SILENT_FORMAT, I915_SILENT_FORMAT_BITS, 0); 1673 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, 1674 I915_SILENT_FMT_MASK, I915_SILENT_FMT_MASK, format); 1675 usleep_range(100, 200); 1676 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, I915_SILENT_FMT_MASK, 0, format); 1677 1678 per_pin->channels = I915_SILENT_CHANNELS; 1679 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1680 } 1681 1682 static void silent_stream_set_kae(struct hda_codec *codec, 1683 struct hdmi_spec_per_pin *per_pin, 1684 bool enable) 1685 { 1686 unsigned int param; 1687 1688 codec_dbg(codec, "HDMI: KAE %d cvt-NID=0x%x\n", enable, per_pin->cvt_nid); 1689 1690 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, AC_VERB_GET_DIGI_CONVERT_1, 0); 1691 param = (param >> 16) & 0xff; 1692 1693 if (enable) 1694 param |= AC_DIG3_KAE; 1695 else 1696 param &= ~AC_DIG3_KAE; 1697 1698 snd_hda_codec_write(codec, per_pin->cvt_nid, 0, AC_VERB_SET_DIGI_CONVERT_3, param); 1699 } 1700 1701 static void silent_stream_enable(struct hda_codec *codec, 1702 struct hdmi_spec_per_pin *per_pin) 1703 { 1704 struct hdmi_spec *spec = codec->spec; 1705 struct hdmi_spec_per_cvt *per_cvt; 1706 int cvt_idx, pin_idx, err; 1707 int keep_power = 0; 1708 1709 /* 1710 * Power-up will call hdmi_present_sense, so the PM calls 1711 * have to be done without mutex held. 1712 */ 1713 1714 err = snd_hda_power_up_pm(codec); 1715 if (err < 0 && err != -EACCES) { 1716 codec_err(codec, 1717 "Failed to power up codec for silent stream enable ret=[%d]\n", err); 1718 snd_hda_power_down_pm(codec); 1719 return; 1720 } 1721 1722 mutex_lock(&per_pin->lock); 1723 1724 if (per_pin->setup) { 1725 codec_dbg(codec, "hdmi: PCM already open, no silent stream\n"); 1726 err = -EBUSY; 1727 goto unlock_out; 1728 } 1729 1730 pin_idx = pin_id_to_pin_index(codec, per_pin->pin_nid, per_pin->dev_id); 1731 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, true); 1732 if (err) { 1733 codec_err(codec, "hdmi: no free converter to enable silent mode\n"); 1734 goto unlock_out; 1735 } 1736 1737 per_cvt = get_cvt(spec, cvt_idx); 1738 per_cvt->silent_stream = true; 1739 per_pin->cvt_nid = per_cvt->cvt_nid; 1740 per_pin->silent_stream = true; 1741 1742 codec_dbg(codec, "hdmi: enabling silent stream pin-NID=0x%x cvt-NID=0x%x\n", 1743 per_pin->pin_nid, per_cvt->cvt_nid); 1744 1745 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1746 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1747 AC_VERB_SET_CONNECT_SEL, 1748 per_pin->mux_idx); 1749 1750 /* configure unused pins to choose other converters */ 1751 pin_cvt_fixup(codec, per_pin, 0); 1752 1753 switch (spec->silent_stream_type) { 1754 case SILENT_STREAM_KAE: 1755 silent_stream_enable_i915(codec, per_pin); 1756 silent_stream_set_kae(codec, per_pin, true); 1757 break; 1758 case SILENT_STREAM_I915: 1759 silent_stream_enable_i915(codec, per_pin); 1760 keep_power = 1; 1761 break; 1762 default: 1763 break; 1764 } 1765 1766 unlock_out: 1767 mutex_unlock(&per_pin->lock); 1768 1769 if (err || !keep_power) 1770 snd_hda_power_down_pm(codec); 1771 } 1772 1773 static void silent_stream_disable(struct hda_codec *codec, 1774 struct hdmi_spec_per_pin *per_pin) 1775 { 1776 struct hdmi_spec *spec = codec->spec; 1777 struct hdmi_spec_per_cvt *per_cvt; 1778 int cvt_idx, err; 1779 1780 err = snd_hda_power_up_pm(codec); 1781 if (err < 0 && err != -EACCES) { 1782 codec_err(codec, 1783 "Failed to power up codec for silent stream disable ret=[%d]\n", 1784 err); 1785 snd_hda_power_down_pm(codec); 1786 return; 1787 } 1788 1789 mutex_lock(&per_pin->lock); 1790 if (!per_pin->silent_stream) 1791 goto unlock_out; 1792 1793 codec_dbg(codec, "HDMI: disable silent stream on pin-NID=0x%x cvt-NID=0x%x\n", 1794 per_pin->pin_nid, per_pin->cvt_nid); 1795 1796 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid); 1797 if (cvt_idx >= 0 && cvt_idx < spec->num_cvts) { 1798 per_cvt = get_cvt(spec, cvt_idx); 1799 per_cvt->silent_stream = false; 1800 } 1801 1802 if (spec->silent_stream_type == SILENT_STREAM_I915) { 1803 /* release ref taken in silent_stream_enable() */ 1804 snd_hda_power_down_pm(codec); 1805 } else if (spec->silent_stream_type == SILENT_STREAM_KAE) { 1806 silent_stream_set_kae(codec, per_pin, false); 1807 } 1808 1809 per_pin->cvt_nid = 0; 1810 per_pin->silent_stream = false; 1811 1812 unlock_out: 1813 mutex_unlock(&per_pin->lock); 1814 1815 snd_hda_power_down_pm(codec); 1816 } 1817 1818 /* update ELD and jack state via audio component */ 1819 static void sync_eld_via_acomp(struct hda_codec *codec, 1820 struct hdmi_spec_per_pin *per_pin) 1821 { 1822 struct hdmi_spec *spec = codec->spec; 1823 struct hdmi_eld *eld = &spec->temp_eld; 1824 bool monitor_prev, monitor_next; 1825 1826 mutex_lock(&per_pin->lock); 1827 eld->monitor_present = false; 1828 monitor_prev = per_pin->sink_eld.monitor_present; 1829 eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, 1830 per_pin->dev_id, &eld->monitor_present, 1831 eld->eld_buffer, ELD_MAX_SIZE); 1832 eld->eld_valid = (eld->eld_size > 0); 1833 update_eld(codec, per_pin, eld, 0); 1834 monitor_next = per_pin->sink_eld.monitor_present; 1835 mutex_unlock(&per_pin->lock); 1836 1837 if (spec->silent_stream_type) { 1838 if (!monitor_prev && monitor_next) 1839 silent_stream_enable(codec, per_pin); 1840 else if (monitor_prev && !monitor_next) 1841 silent_stream_disable(codec, per_pin); 1842 } 1843 } 1844 1845 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) 1846 { 1847 struct hda_codec *codec = per_pin->codec; 1848 1849 if (!codec_has_acomp(codec)) 1850 hdmi_present_sense_via_verbs(per_pin, repoll); 1851 else 1852 sync_eld_via_acomp(codec, per_pin); 1853 } 1854 1855 static void hdmi_repoll_eld(struct work_struct *work) 1856 { 1857 struct hdmi_spec_per_pin *per_pin = 1858 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); 1859 struct hda_codec *codec = per_pin->codec; 1860 struct hdmi_spec *spec = codec->spec; 1861 struct hda_jack_tbl *jack; 1862 1863 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid, 1864 per_pin->dev_id); 1865 if (jack) 1866 jack->jack_dirty = 1; 1867 1868 if (per_pin->repoll_count++ > 6) 1869 per_pin->repoll_count = 0; 1870 1871 mutex_lock(&spec->pcm_lock); 1872 hdmi_present_sense(per_pin, per_pin->repoll_count); 1873 mutex_unlock(&spec->pcm_lock); 1874 } 1875 1876 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) 1877 { 1878 struct hdmi_spec *spec = codec->spec; 1879 unsigned int caps, config; 1880 int pin_idx; 1881 struct hdmi_spec_per_pin *per_pin; 1882 int err; 1883 int dev_num, i; 1884 1885 caps = snd_hda_query_pin_caps(codec, pin_nid); 1886 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) 1887 return 0; 1888 1889 /* 1890 * For DP MST audio, Configuration Default is the same for 1891 * all device entries on the same pin 1892 */ 1893 config = snd_hda_codec_get_pincfg(codec, pin_nid); 1894 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE && 1895 !spec->force_connect) 1896 return 0; 1897 1898 /* 1899 * To simplify the implementation, malloc all 1900 * the virtual pins in the initialization statically 1901 */ 1902 if (spec->intel_hsw_fixup) { 1903 /* 1904 * On Intel platforms, device entries count returned 1905 * by AC_PAR_DEVLIST_LEN is dynamic, and depends on 1906 * the type of receiver that is connected. Allocate pin 1907 * structures based on worst case. 1908 */ 1909 dev_num = spec->dev_num; 1910 } else if (codec->dp_mst) { 1911 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; 1912 /* 1913 * spec->dev_num is the maxinum number of device entries 1914 * among all the pins 1915 */ 1916 spec->dev_num = (spec->dev_num > dev_num) ? 1917 spec->dev_num : dev_num; 1918 } else { 1919 /* 1920 * If the platform doesn't support DP MST, 1921 * manually set dev_num to 1. This means 1922 * the pin has only one device entry. 1923 */ 1924 dev_num = 1; 1925 spec->dev_num = 1; 1926 } 1927 1928 for (i = 0; i < dev_num; i++) { 1929 pin_idx = spec->num_pins; 1930 per_pin = snd_array_new(&spec->pins); 1931 1932 if (!per_pin) 1933 return -ENOMEM; 1934 1935 per_pin->pcm = NULL; 1936 per_pin->pcm_idx = -1; 1937 per_pin->prev_pcm_idx = -1; 1938 per_pin->pin_nid = pin_nid; 1939 per_pin->pin_nid_idx = spec->num_nids; 1940 per_pin->dev_id = i; 1941 per_pin->non_pcm = false; 1942 snd_hda_set_dev_select(codec, pin_nid, i); 1943 err = hdmi_read_pin_conn(codec, pin_idx); 1944 if (err < 0) 1945 return err; 1946 if (!is_jack_detectable(codec, pin_nid)) 1947 codec_warn(codec, "HDMI: pin NID 0x%x - jack not detectable\n", pin_nid); 1948 spec->num_pins++; 1949 } 1950 spec->num_nids++; 1951 1952 return 0; 1953 } 1954 1955 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1956 { 1957 struct hdmi_spec *spec = codec->spec; 1958 struct hdmi_spec_per_cvt *per_cvt; 1959 unsigned int chans; 1960 int err; 1961 1962 chans = get_wcaps(codec, cvt_nid); 1963 chans = get_wcaps_channels(chans); 1964 1965 per_cvt = snd_array_new(&spec->cvts); 1966 if (!per_cvt) 1967 return -ENOMEM; 1968 1969 per_cvt->cvt_nid = cvt_nid; 1970 per_cvt->channels_min = 2; 1971 if (chans <= 16) { 1972 per_cvt->channels_max = chans; 1973 if (chans > spec->chmap.channels_max) 1974 spec->chmap.channels_max = chans; 1975 } 1976 1977 err = snd_hda_query_supported_pcm(codec, cvt_nid, 1978 &per_cvt->rates, 1979 &per_cvt->formats, 1980 &per_cvt->maxbps); 1981 if (err < 0) 1982 return err; 1983 1984 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) 1985 spec->cvt_nids[spec->num_cvts] = cvt_nid; 1986 spec->num_cvts++; 1987 1988 return 0; 1989 } 1990 1991 static const struct snd_pci_quirk force_connect_list[] = { 1992 SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1), 1993 SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1), 1994 SND_PCI_QUIRK(0x103c, 0x8711, "HP", 1), 1995 SND_PCI_QUIRK(0x103c, 0x8715, "HP", 1), 1996 SND_PCI_QUIRK(0x1462, 0xec94, "MS-7C94", 1), 1997 SND_PCI_QUIRK(0x8086, 0x2081, "Intel NUC 10", 1), 1998 {} 1999 }; 2000 2001 static int hdmi_parse_codec(struct hda_codec *codec) 2002 { 2003 struct hdmi_spec *spec = codec->spec; 2004 hda_nid_t start_nid; 2005 unsigned int caps; 2006 int i, nodes; 2007 const struct snd_pci_quirk *q; 2008 2009 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid); 2010 if (!start_nid || nodes < 0) { 2011 codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); 2012 return -EINVAL; 2013 } 2014 2015 if (enable_all_pins) 2016 spec->force_connect = true; 2017 2018 q = snd_pci_quirk_lookup(codec->bus->pci, force_connect_list); 2019 2020 if (q && q->value) 2021 spec->force_connect = true; 2022 2023 /* 2024 * hdmi_add_pin() assumes total amount of converters to 2025 * be known, so first discover all converters 2026 */ 2027 for (i = 0; i < nodes; i++) { 2028 hda_nid_t nid = start_nid + i; 2029 2030 caps = get_wcaps(codec, nid); 2031 2032 if (!(caps & AC_WCAP_DIGITAL)) 2033 continue; 2034 2035 if (get_wcaps_type(caps) == AC_WID_AUD_OUT) 2036 hdmi_add_cvt(codec, nid); 2037 } 2038 2039 /* discover audio pins */ 2040 for (i = 0; i < nodes; i++) { 2041 hda_nid_t nid = start_nid + i; 2042 2043 caps = get_wcaps(codec, nid); 2044 2045 if (!(caps & AC_WCAP_DIGITAL)) 2046 continue; 2047 2048 if (get_wcaps_type(caps) == AC_WID_PIN) 2049 hdmi_add_pin(codec, nid); 2050 } 2051 2052 return 0; 2053 } 2054 2055 /* 2056 */ 2057 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 2058 { 2059 struct hda_spdif_out *spdif; 2060 bool non_pcm; 2061 2062 mutex_lock(&codec->spdif_mutex); 2063 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); 2064 /* Add sanity check to pass klockwork check. 2065 * This should never happen. 2066 */ 2067 if (WARN_ON(spdif == NULL)) { 2068 mutex_unlock(&codec->spdif_mutex); 2069 return true; 2070 } 2071 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); 2072 mutex_unlock(&codec->spdif_mutex); 2073 return non_pcm; 2074 } 2075 2076 /* 2077 * HDMI callbacks 2078 */ 2079 2080 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 2081 struct hda_codec *codec, 2082 unsigned int stream_tag, 2083 unsigned int format, 2084 struct snd_pcm_substream *substream) 2085 { 2086 hda_nid_t cvt_nid = hinfo->nid; 2087 struct hdmi_spec *spec = codec->spec; 2088 int pin_idx; 2089 struct hdmi_spec_per_pin *per_pin; 2090 struct snd_pcm_runtime *runtime = substream->runtime; 2091 bool non_pcm; 2092 int pinctl, stripe; 2093 int err = 0; 2094 2095 mutex_lock(&spec->pcm_lock); 2096 pin_idx = hinfo_to_pin_index(codec, hinfo); 2097 if (pin_idx < 0) { 2098 /* when pcm is not bound to a pin skip pin setup and return 0 2099 * to make audio playback be ongoing 2100 */ 2101 pin_cvt_fixup(codec, NULL, cvt_nid); 2102 snd_hda_codec_setup_stream(codec, cvt_nid, 2103 stream_tag, 0, format); 2104 goto unlock; 2105 } 2106 2107 per_pin = get_pin(spec, pin_idx); 2108 2109 /* Verify pin:cvt selections to avoid silent audio after S3. 2110 * After S3, the audio driver restores pin:cvt selections 2111 * but this can happen before gfx is ready and such selection 2112 * is overlooked by HW. Thus multiple pins can share a same 2113 * default convertor and mute control will affect each other, 2114 * which can cause a resumed audio playback become silent 2115 * after S3. 2116 */ 2117 pin_cvt_fixup(codec, per_pin, 0); 2118 2119 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ 2120 /* Todo: add DP1.2 MST audio support later */ 2121 if (codec_has_acomp(codec)) 2122 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, 2123 per_pin->dev_id, runtime->rate); 2124 2125 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); 2126 mutex_lock(&per_pin->lock); 2127 per_pin->channels = substream->runtime->channels; 2128 per_pin->setup = true; 2129 2130 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) { 2131 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core, 2132 substream); 2133 snd_hda_codec_write(codec, cvt_nid, 0, 2134 AC_VERB_SET_STRIPE_CONTROL, 2135 stripe); 2136 } 2137 2138 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 2139 mutex_unlock(&per_pin->lock); 2140 if (spec->dyn_pin_out) { 2141 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2142 per_pin->dev_id); 2143 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2144 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2145 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2146 AC_VERB_SET_PIN_WIDGET_CONTROL, 2147 pinctl | PIN_OUT); 2148 } 2149 2150 /* snd_hda_set_dev_select() has been called before */ 2151 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid, 2152 per_pin->dev_id, stream_tag, format); 2153 unlock: 2154 mutex_unlock(&spec->pcm_lock); 2155 return err; 2156 } 2157 2158 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 2159 struct hda_codec *codec, 2160 struct snd_pcm_substream *substream) 2161 { 2162 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 2163 return 0; 2164 } 2165 2166 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, 2167 struct hda_codec *codec, 2168 struct snd_pcm_substream *substream) 2169 { 2170 struct hdmi_spec *spec = codec->spec; 2171 int cvt_idx, pin_idx, pcm_idx; 2172 struct hdmi_spec_per_cvt *per_cvt; 2173 struct hdmi_spec_per_pin *per_pin; 2174 int pinctl; 2175 int err = 0; 2176 2177 mutex_lock(&spec->pcm_lock); 2178 if (hinfo->nid) { 2179 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 2180 if (snd_BUG_ON(pcm_idx < 0)) { 2181 err = -EINVAL; 2182 goto unlock; 2183 } 2184 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); 2185 if (snd_BUG_ON(cvt_idx < 0)) { 2186 err = -EINVAL; 2187 goto unlock; 2188 } 2189 per_cvt = get_cvt(spec, cvt_idx); 2190 per_cvt->assigned = false; 2191 hinfo->nid = 0; 2192 2193 azx_stream(get_azx_dev(substream))->stripe = 0; 2194 2195 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2196 clear_bit(pcm_idx, &spec->pcm_in_use); 2197 pin_idx = hinfo_to_pin_index(codec, hinfo); 2198 /* 2199 * In such a case, return 0 to match the behavior in 2200 * hdmi_pcm_open() 2201 */ 2202 if (pin_idx < 0) 2203 goto unlock; 2204 2205 per_pin = get_pin(spec, pin_idx); 2206 2207 if (spec->dyn_pin_out) { 2208 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2209 per_pin->dev_id); 2210 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2211 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2212 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2213 AC_VERB_SET_PIN_WIDGET_CONTROL, 2214 pinctl & ~PIN_OUT); 2215 } 2216 2217 mutex_lock(&per_pin->lock); 2218 per_pin->chmap_set = false; 2219 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 2220 2221 per_pin->setup = false; 2222 per_pin->channels = 0; 2223 mutex_unlock(&per_pin->lock); 2224 } 2225 2226 unlock: 2227 mutex_unlock(&spec->pcm_lock); 2228 2229 return err; 2230 } 2231 2232 static const struct hda_pcm_ops generic_ops = { 2233 .open = hdmi_pcm_open, 2234 .close = hdmi_pcm_close, 2235 .prepare = generic_hdmi_playback_pcm_prepare, 2236 .cleanup = generic_hdmi_playback_pcm_cleanup, 2237 }; 2238 2239 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) 2240 { 2241 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2242 struct hdmi_spec *spec = codec->spec; 2243 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2244 2245 if (!per_pin) 2246 return 0; 2247 2248 return per_pin->sink_eld.info.spk_alloc; 2249 } 2250 2251 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, 2252 unsigned char *chmap) 2253 { 2254 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2255 struct hdmi_spec *spec = codec->spec; 2256 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2257 2258 /* chmap is already set to 0 in caller */ 2259 if (!per_pin) 2260 return; 2261 2262 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); 2263 } 2264 2265 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, 2266 unsigned char *chmap, int prepared) 2267 { 2268 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2269 struct hdmi_spec *spec = codec->spec; 2270 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2271 2272 if (!per_pin) 2273 return; 2274 mutex_lock(&per_pin->lock); 2275 per_pin->chmap_set = true; 2276 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); 2277 if (prepared) 2278 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 2279 mutex_unlock(&per_pin->lock); 2280 } 2281 2282 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) 2283 { 2284 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2285 struct hdmi_spec *spec = codec->spec; 2286 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2287 2288 return per_pin ? true:false; 2289 } 2290 2291 static int generic_hdmi_build_pcms(struct hda_codec *codec) 2292 { 2293 struct hdmi_spec *spec = codec->spec; 2294 int idx, pcm_num; 2295 2296 /* limit the PCM devices to the codec converters or available PINs */ 2297 pcm_num = min(spec->num_cvts, spec->num_pins); 2298 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num); 2299 2300 for (idx = 0; idx < pcm_num; idx++) { 2301 struct hda_pcm *info; 2302 struct hda_pcm_stream *pstr; 2303 2304 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); 2305 if (!info) 2306 return -ENOMEM; 2307 2308 spec->pcm_rec[idx].pcm = info; 2309 spec->pcm_used++; 2310 info->pcm_type = HDA_PCM_TYPE_HDMI; 2311 info->own_chmap = true; 2312 2313 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2314 pstr->substreams = 1; 2315 pstr->ops = generic_ops; 2316 /* pcm number is less than pcm_rec array size */ 2317 if (spec->pcm_used >= ARRAY_SIZE(spec->pcm_rec)) 2318 break; 2319 /* other pstr fields are set in open */ 2320 } 2321 2322 return 0; 2323 } 2324 2325 static void free_hdmi_jack_priv(struct snd_jack *jack) 2326 { 2327 struct hdmi_pcm *pcm = jack->private_data; 2328 2329 pcm->jack = NULL; 2330 } 2331 2332 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) 2333 { 2334 char hdmi_str[32] = "HDMI/DP"; 2335 struct hdmi_spec *spec = codec->spec; 2336 struct snd_jack *jack; 2337 int pcmdev = get_pcm_rec(spec, pcm_idx)->device; 2338 int err; 2339 2340 if (pcmdev > 0) 2341 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); 2342 2343 err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack, 2344 true, false); 2345 if (err < 0) 2346 return err; 2347 2348 spec->pcm_rec[pcm_idx].jack = jack; 2349 jack->private_data = &spec->pcm_rec[pcm_idx]; 2350 jack->private_free = free_hdmi_jack_priv; 2351 return 0; 2352 } 2353 2354 static int generic_hdmi_build_controls(struct hda_codec *codec) 2355 { 2356 struct hdmi_spec *spec = codec->spec; 2357 int dev, err; 2358 int pin_idx, pcm_idx; 2359 2360 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2361 if (!get_pcm_rec(spec, pcm_idx)->pcm) { 2362 /* no PCM: mark this for skipping permanently */ 2363 set_bit(pcm_idx, &spec->pcm_bitmap); 2364 continue; 2365 } 2366 2367 err = generic_hdmi_build_jack(codec, pcm_idx); 2368 if (err < 0) 2369 return err; 2370 2371 /* create the spdif for each pcm 2372 * pin will be bound when monitor is connected 2373 */ 2374 err = snd_hda_create_dig_out_ctls(codec, 2375 0, spec->cvt_nids[0], 2376 HDA_PCM_TYPE_HDMI); 2377 if (err < 0) 2378 return err; 2379 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2380 2381 dev = get_pcm_rec(spec, pcm_idx)->device; 2382 if (dev != SNDRV_PCM_INVALID_DEVICE) { 2383 /* add control for ELD Bytes */ 2384 err = hdmi_create_eld_ctl(codec, pcm_idx, dev); 2385 if (err < 0) 2386 return err; 2387 } 2388 } 2389 2390 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2391 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2392 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 2393 2394 if (spec->static_pcm_mapping) { 2395 hdmi_attach_hda_pcm(spec, per_pin); 2396 hdmi_pcm_setup_pin(spec, per_pin); 2397 } 2398 2399 pin_eld->eld_valid = false; 2400 hdmi_present_sense(per_pin, 0); 2401 } 2402 2403 /* add channel maps */ 2404 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2405 struct hda_pcm *pcm; 2406 2407 pcm = get_pcm_rec(spec, pcm_idx); 2408 if (!pcm || !pcm->pcm) 2409 break; 2410 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); 2411 if (err < 0) 2412 return err; 2413 } 2414 2415 return 0; 2416 } 2417 2418 static int generic_hdmi_init_per_pins(struct hda_codec *codec) 2419 { 2420 struct hdmi_spec *spec = codec->spec; 2421 int pin_idx; 2422 2423 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2424 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2425 2426 per_pin->codec = codec; 2427 mutex_init(&per_pin->lock); 2428 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); 2429 eld_proc_new(per_pin, pin_idx); 2430 } 2431 return 0; 2432 } 2433 2434 static int generic_hdmi_init(struct hda_codec *codec) 2435 { 2436 struct hdmi_spec *spec = codec->spec; 2437 int pin_idx; 2438 2439 mutex_lock(&spec->bind_lock); 2440 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2441 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2442 hda_nid_t pin_nid = per_pin->pin_nid; 2443 int dev_id = per_pin->dev_id; 2444 2445 snd_hda_set_dev_select(codec, pin_nid, dev_id); 2446 hdmi_init_pin(codec, pin_nid); 2447 if (codec_has_acomp(codec)) 2448 continue; 2449 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id, 2450 jack_callback); 2451 } 2452 mutex_unlock(&spec->bind_lock); 2453 return 0; 2454 } 2455 2456 static void hdmi_array_init(struct hdmi_spec *spec, int nums) 2457 { 2458 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); 2459 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); 2460 } 2461 2462 static void hdmi_array_free(struct hdmi_spec *spec) 2463 { 2464 snd_array_free(&spec->pins); 2465 snd_array_free(&spec->cvts); 2466 } 2467 2468 static void generic_spec_free(struct hda_codec *codec) 2469 { 2470 struct hdmi_spec *spec = codec->spec; 2471 2472 if (spec) { 2473 hdmi_array_free(spec); 2474 kfree(spec); 2475 codec->spec = NULL; 2476 } 2477 codec->dp_mst = false; 2478 } 2479 2480 static void generic_hdmi_free(struct hda_codec *codec) 2481 { 2482 struct hdmi_spec *spec = codec->spec; 2483 int pin_idx, pcm_idx; 2484 2485 if (spec->acomp_registered) { 2486 snd_hdac_acomp_exit(&codec->bus->core); 2487 } else if (codec_has_acomp(codec)) { 2488 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL); 2489 } 2490 codec->relaxed_resume = 0; 2491 2492 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2493 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2494 cancel_delayed_work_sync(&per_pin->work); 2495 eld_proc_free(per_pin); 2496 } 2497 2498 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2499 if (spec->pcm_rec[pcm_idx].jack == NULL) 2500 continue; 2501 snd_device_free(codec->card, spec->pcm_rec[pcm_idx].jack); 2502 } 2503 2504 generic_spec_free(codec); 2505 } 2506 2507 #ifdef CONFIG_PM 2508 static int generic_hdmi_suspend(struct hda_codec *codec) 2509 { 2510 struct hdmi_spec *spec = codec->spec; 2511 int pin_idx; 2512 2513 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2514 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2515 cancel_delayed_work_sync(&per_pin->work); 2516 } 2517 return 0; 2518 } 2519 2520 static int generic_hdmi_resume(struct hda_codec *codec) 2521 { 2522 struct hdmi_spec *spec = codec->spec; 2523 int pin_idx; 2524 2525 codec->patch_ops.init(codec); 2526 snd_hda_regmap_sync(codec); 2527 2528 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2529 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2530 hdmi_present_sense(per_pin, 1); 2531 } 2532 return 0; 2533 } 2534 #endif 2535 2536 static const struct hda_codec_ops generic_hdmi_patch_ops = { 2537 .init = generic_hdmi_init, 2538 .free = generic_hdmi_free, 2539 .build_pcms = generic_hdmi_build_pcms, 2540 .build_controls = generic_hdmi_build_controls, 2541 .unsol_event = hdmi_unsol_event, 2542 #ifdef CONFIG_PM 2543 .suspend = generic_hdmi_suspend, 2544 .resume = generic_hdmi_resume, 2545 #endif 2546 }; 2547 2548 static const struct hdmi_ops generic_standard_hdmi_ops = { 2549 .pin_get_eld = hdmi_pin_get_eld, 2550 .pin_setup_infoframe = hdmi_pin_setup_infoframe, 2551 .pin_hbr_setup = hdmi_pin_hbr_setup, 2552 .setup_stream = hdmi_setup_stream, 2553 }; 2554 2555 /* allocate codec->spec and assign/initialize generic parser ops */ 2556 static int alloc_generic_hdmi(struct hda_codec *codec) 2557 { 2558 struct hdmi_spec *spec; 2559 2560 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2561 if (!spec) 2562 return -ENOMEM; 2563 2564 spec->codec = codec; 2565 spec->ops = generic_standard_hdmi_ops; 2566 spec->dev_num = 1; /* initialize to 1 */ 2567 mutex_init(&spec->pcm_lock); 2568 mutex_init(&spec->bind_lock); 2569 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); 2570 2571 spec->chmap.ops.get_chmap = hdmi_get_chmap; 2572 spec->chmap.ops.set_chmap = hdmi_set_chmap; 2573 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; 2574 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc; 2575 2576 codec->spec = spec; 2577 hdmi_array_init(spec, 4); 2578 2579 codec->patch_ops = generic_hdmi_patch_ops; 2580 2581 return 0; 2582 } 2583 2584 /* generic HDMI parser */ 2585 static int patch_generic_hdmi(struct hda_codec *codec) 2586 { 2587 int err; 2588 2589 err = alloc_generic_hdmi(codec); 2590 if (err < 0) 2591 return err; 2592 2593 err = hdmi_parse_codec(codec); 2594 if (err < 0) { 2595 generic_spec_free(codec); 2596 return err; 2597 } 2598 2599 generic_hdmi_init_per_pins(codec); 2600 return 0; 2601 } 2602 2603 /* 2604 * generic audio component binding 2605 */ 2606 2607 /* turn on / off the unsol event jack detection dynamically */ 2608 static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid, 2609 int dev_id, bool use_acomp) 2610 { 2611 struct hda_jack_tbl *tbl; 2612 2613 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id); 2614 if (tbl) { 2615 /* clear unsol even if component notifier is used, or re-enable 2616 * if notifier is cleared 2617 */ 2618 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag); 2619 snd_hda_codec_write_cache(codec, nid, 0, 2620 AC_VERB_SET_UNSOLICITED_ENABLE, val); 2621 } 2622 } 2623 2624 /* set up / clear component notifier dynamically */ 2625 static void generic_acomp_notifier_set(struct drm_audio_component *acomp, 2626 bool use_acomp) 2627 { 2628 struct hdmi_spec *spec; 2629 int i; 2630 2631 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops); 2632 mutex_lock(&spec->bind_lock); 2633 spec->use_acomp_notifier = use_acomp; 2634 spec->codec->relaxed_resume = use_acomp; 2635 spec->codec->bus->keep_power = 0; 2636 /* reprogram each jack detection logic depending on the notifier */ 2637 for (i = 0; i < spec->num_pins; i++) 2638 reprogram_jack_detect(spec->codec, 2639 get_pin(spec, i)->pin_nid, 2640 get_pin(spec, i)->dev_id, 2641 use_acomp); 2642 mutex_unlock(&spec->bind_lock); 2643 } 2644 2645 /* enable / disable the notifier via master bind / unbind */ 2646 static int generic_acomp_master_bind(struct device *dev, 2647 struct drm_audio_component *acomp) 2648 { 2649 generic_acomp_notifier_set(acomp, true); 2650 return 0; 2651 } 2652 2653 static void generic_acomp_master_unbind(struct device *dev, 2654 struct drm_audio_component *acomp) 2655 { 2656 generic_acomp_notifier_set(acomp, false); 2657 } 2658 2659 /* check whether both HD-audio and DRM PCI devices belong to the same bus */ 2660 static int match_bound_vga(struct device *dev, int subtype, void *data) 2661 { 2662 struct hdac_bus *bus = data; 2663 struct pci_dev *pci, *master; 2664 2665 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev)) 2666 return 0; 2667 master = to_pci_dev(bus->dev); 2668 pci = to_pci_dev(dev); 2669 return master->bus == pci->bus; 2670 } 2671 2672 /* audio component notifier for AMD/Nvidia HDMI codecs */ 2673 static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id) 2674 { 2675 struct hda_codec *codec = audio_ptr; 2676 struct hdmi_spec *spec = codec->spec; 2677 hda_nid_t pin_nid = spec->port2pin(codec, port); 2678 2679 if (!pin_nid) 2680 return; 2681 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN) 2682 return; 2683 /* skip notification during system suspend (but not in runtime PM); 2684 * the state will be updated at resume 2685 */ 2686 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND) 2687 return; 2688 2689 check_presence_and_report(codec, pin_nid, dev_id); 2690 } 2691 2692 /* set up the private drm_audio_ops from the template */ 2693 static void setup_drm_audio_ops(struct hda_codec *codec, 2694 const struct drm_audio_component_audio_ops *ops) 2695 { 2696 struct hdmi_spec *spec = codec->spec; 2697 2698 spec->drm_audio_ops.audio_ptr = codec; 2699 /* intel_audio_codec_enable() or intel_audio_codec_disable() 2700 * will call pin_eld_notify with using audio_ptr pointer 2701 * We need make sure audio_ptr is really setup 2702 */ 2703 wmb(); 2704 spec->drm_audio_ops.pin2port = ops->pin2port; 2705 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify; 2706 spec->drm_audio_ops.master_bind = ops->master_bind; 2707 spec->drm_audio_ops.master_unbind = ops->master_unbind; 2708 } 2709 2710 /* initialize the generic HDMI audio component */ 2711 static void generic_acomp_init(struct hda_codec *codec, 2712 const struct drm_audio_component_audio_ops *ops, 2713 int (*port2pin)(struct hda_codec *, int)) 2714 { 2715 struct hdmi_spec *spec = codec->spec; 2716 2717 if (!enable_acomp) { 2718 codec_info(codec, "audio component disabled by module option\n"); 2719 return; 2720 } 2721 2722 spec->port2pin = port2pin; 2723 setup_drm_audio_ops(codec, ops); 2724 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops, 2725 match_bound_vga, 0)) { 2726 spec->acomp_registered = true; 2727 } 2728 } 2729 2730 /* 2731 * Intel codec parsers and helpers 2732 */ 2733 2734 #define INTEL_GET_VENDOR_VERB 0xf81 2735 #define INTEL_SET_VENDOR_VERB 0x781 2736 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ 2737 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ 2738 2739 static void intel_haswell_enable_all_pins(struct hda_codec *codec, 2740 bool update_tree) 2741 { 2742 unsigned int vendor_param; 2743 struct hdmi_spec *spec = codec->spec; 2744 2745 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2746 INTEL_GET_VENDOR_VERB, 0); 2747 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) 2748 return; 2749 2750 vendor_param |= INTEL_EN_ALL_PIN_CVTS; 2751 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2752 INTEL_SET_VENDOR_VERB, vendor_param); 2753 if (vendor_param == -1) 2754 return; 2755 2756 if (update_tree) 2757 snd_hda_codec_update_widgets(codec); 2758 } 2759 2760 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) 2761 { 2762 unsigned int vendor_param; 2763 struct hdmi_spec *spec = codec->spec; 2764 2765 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2766 INTEL_GET_VENDOR_VERB, 0); 2767 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) 2768 return; 2769 2770 /* enable DP1.2 mode */ 2771 vendor_param |= INTEL_EN_DP12; 2772 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); 2773 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, 2774 INTEL_SET_VENDOR_VERB, vendor_param); 2775 } 2776 2777 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. 2778 * Otherwise you may get severe h/w communication errors. 2779 */ 2780 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, 2781 unsigned int power_state) 2782 { 2783 if (power_state == AC_PWRST_D0) { 2784 intel_haswell_enable_all_pins(codec, false); 2785 intel_haswell_fixup_enable_dp12(codec); 2786 } 2787 2788 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); 2789 snd_hda_codec_set_power_to_all(codec, fg, power_state); 2790 } 2791 2792 /* There is a fixed mapping between audio pin node and display port. 2793 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL: 2794 * Pin Widget 5 - PORT B (port = 1 in i915 driver) 2795 * Pin Widget 6 - PORT C (port = 2 in i915 driver) 2796 * Pin Widget 7 - PORT D (port = 3 in i915 driver) 2797 * 2798 * on VLV, ILK: 2799 * Pin Widget 4 - PORT B (port = 1 in i915 driver) 2800 * Pin Widget 5 - PORT C (port = 2 in i915 driver) 2801 * Pin Widget 6 - PORT D (port = 3 in i915 driver) 2802 */ 2803 static int intel_base_nid(struct hda_codec *codec) 2804 { 2805 switch (codec->core.vendor_id) { 2806 case 0x80860054: /* ILK */ 2807 case 0x80862804: /* ILK */ 2808 case 0x80862882: /* VLV */ 2809 return 4; 2810 default: 2811 return 5; 2812 } 2813 } 2814 2815 static int intel_pin2port(void *audio_ptr, int pin_nid) 2816 { 2817 struct hda_codec *codec = audio_ptr; 2818 struct hdmi_spec *spec = codec->spec; 2819 int base_nid, i; 2820 2821 if (!spec->port_num) { 2822 base_nid = intel_base_nid(codec); 2823 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3)) 2824 return -1; 2825 return pin_nid - base_nid + 1; 2826 } 2827 2828 /* 2829 * looking for the pin number in the mapping table and return 2830 * the index which indicate the port number 2831 */ 2832 for (i = 0; i < spec->port_num; i++) { 2833 if (pin_nid == spec->port_map[i]) 2834 return i; 2835 } 2836 2837 codec_info(codec, "Can't find the HDMI/DP port for pin NID 0x%x\n", pin_nid); 2838 return -1; 2839 } 2840 2841 static int intel_port2pin(struct hda_codec *codec, int port) 2842 { 2843 struct hdmi_spec *spec = codec->spec; 2844 2845 if (!spec->port_num) { 2846 /* we assume only from port-B to port-D */ 2847 if (port < 1 || port > 3) 2848 return 0; 2849 return port + intel_base_nid(codec) - 1; 2850 } 2851 2852 if (port < 0 || port >= spec->port_num) 2853 return 0; 2854 return spec->port_map[port]; 2855 } 2856 2857 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) 2858 { 2859 struct hda_codec *codec = audio_ptr; 2860 int pin_nid; 2861 int dev_id = pipe; 2862 2863 pin_nid = intel_port2pin(codec, port); 2864 if (!pin_nid) 2865 return; 2866 /* skip notification during system suspend (but not in runtime PM); 2867 * the state will be updated at resume 2868 */ 2869 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND) 2870 return; 2871 2872 snd_hdac_i915_set_bclk(&codec->bus->core); 2873 check_presence_and_report(codec, pin_nid, dev_id); 2874 } 2875 2876 static const struct drm_audio_component_audio_ops intel_audio_ops = { 2877 .pin2port = intel_pin2port, 2878 .pin_eld_notify = intel_pin_eld_notify, 2879 }; 2880 2881 /* register i915 component pin_eld_notify callback */ 2882 static void register_i915_notifier(struct hda_codec *codec) 2883 { 2884 struct hdmi_spec *spec = codec->spec; 2885 2886 spec->use_acomp_notifier = true; 2887 spec->port2pin = intel_port2pin; 2888 setup_drm_audio_ops(codec, &intel_audio_ops); 2889 snd_hdac_acomp_register_notifier(&codec->bus->core, 2890 &spec->drm_audio_ops); 2891 /* no need for forcible resume for jack check thanks to notifier */ 2892 codec->relaxed_resume = 1; 2893 } 2894 2895 /* setup_stream ops override for HSW+ */ 2896 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 2897 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 2898 int format) 2899 { 2900 struct hdmi_spec *spec = codec->spec; 2901 int pin_idx = pin_id_to_pin_index(codec, pin_nid, dev_id); 2902 struct hdmi_spec_per_pin *per_pin; 2903 int res; 2904 2905 if (pin_idx < 0) 2906 per_pin = NULL; 2907 else 2908 per_pin = get_pin(spec, pin_idx); 2909 2910 haswell_verify_D0(codec, cvt_nid, pin_nid); 2911 2912 if (spec->silent_stream_type == SILENT_STREAM_KAE && per_pin && per_pin->silent_stream) { 2913 silent_stream_set_kae(codec, per_pin, false); 2914 /* wait for pending transfers in codec to clear */ 2915 usleep_range(100, 200); 2916 } 2917 2918 res = hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 2919 stream_tag, format); 2920 2921 if (spec->silent_stream_type == SILENT_STREAM_KAE && per_pin && per_pin->silent_stream) { 2922 usleep_range(100, 200); 2923 silent_stream_set_kae(codec, per_pin, true); 2924 } 2925 2926 return res; 2927 } 2928 2929 /* pin_cvt_fixup ops override for HSW+ and VLV+ */ 2930 static void i915_pin_cvt_fixup(struct hda_codec *codec, 2931 struct hdmi_spec_per_pin *per_pin, 2932 hda_nid_t cvt_nid) 2933 { 2934 if (per_pin) { 2935 haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid); 2936 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2937 per_pin->dev_id); 2938 intel_verify_pin_cvt_connect(codec, per_pin); 2939 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, 2940 per_pin->dev_id, per_pin->mux_idx); 2941 } else { 2942 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); 2943 } 2944 } 2945 2946 #ifdef CONFIG_PM 2947 static int i915_adlp_hdmi_suspend(struct hda_codec *codec) 2948 { 2949 struct hdmi_spec *spec = codec->spec; 2950 bool silent_streams = false; 2951 int pin_idx, res; 2952 2953 res = generic_hdmi_suspend(codec); 2954 2955 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2956 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2957 2958 if (per_pin->silent_stream) { 2959 silent_streams = true; 2960 break; 2961 } 2962 } 2963 2964 if (silent_streams && spec->silent_stream_type == SILENT_STREAM_KAE) { 2965 /* 2966 * stream-id should remain programmed when codec goes 2967 * to runtime suspend 2968 */ 2969 codec->no_stream_clean_at_suspend = 1; 2970 2971 /* 2972 * the system might go to S3, in which case keep-alive 2973 * must be reprogrammed upon resume 2974 */ 2975 codec->forced_resume = 1; 2976 2977 codec_dbg(codec, "HDMI: KAE active at suspend\n"); 2978 } else { 2979 codec->no_stream_clean_at_suspend = 0; 2980 codec->forced_resume = 0; 2981 } 2982 2983 return res; 2984 } 2985 2986 static int i915_adlp_hdmi_resume(struct hda_codec *codec) 2987 { 2988 struct hdmi_spec *spec = codec->spec; 2989 int pin_idx, res; 2990 2991 res = generic_hdmi_resume(codec); 2992 2993 /* KAE not programmed at suspend, nothing to do here */ 2994 if (!codec->no_stream_clean_at_suspend) 2995 return res; 2996 2997 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2998 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2999 3000 /* 3001 * If system was in suspend with monitor connected, 3002 * the codec setting may have been lost. Re-enable 3003 * keep-alive. 3004 */ 3005 if (per_pin->silent_stream) { 3006 unsigned int param; 3007 3008 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, 3009 AC_VERB_GET_CONV, 0); 3010 if (!param) { 3011 codec_dbg(codec, "HDMI: KAE: restore stream id\n"); 3012 silent_stream_enable_i915(codec, per_pin); 3013 } 3014 3015 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, 3016 AC_VERB_GET_DIGI_CONVERT_1, 0); 3017 if (!(param & (AC_DIG3_KAE << 16))) { 3018 codec_dbg(codec, "HDMI: KAE: restore DIG3_KAE\n"); 3019 silent_stream_set_kae(codec, per_pin, true); 3020 } 3021 } 3022 } 3023 3024 return res; 3025 } 3026 #endif 3027 3028 /* precondition and allocation for Intel codecs */ 3029 static int alloc_intel_hdmi(struct hda_codec *codec) 3030 { 3031 int err; 3032 3033 /* requires i915 binding */ 3034 if (!codec->bus->core.audio_component) { 3035 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); 3036 /* set probe_id here to prevent generic fallback binding */ 3037 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE; 3038 return -ENODEV; 3039 } 3040 3041 err = alloc_generic_hdmi(codec); 3042 if (err < 0) 3043 return err; 3044 /* no need to handle unsol events */ 3045 codec->patch_ops.unsol_event = NULL; 3046 return 0; 3047 } 3048 3049 /* parse and post-process for Intel codecs */ 3050 static int parse_intel_hdmi(struct hda_codec *codec) 3051 { 3052 int err, retries = 3; 3053 3054 do { 3055 err = hdmi_parse_codec(codec); 3056 } while (err < 0 && retries--); 3057 3058 if (err < 0) { 3059 generic_spec_free(codec); 3060 return err; 3061 } 3062 3063 generic_hdmi_init_per_pins(codec); 3064 register_i915_notifier(codec); 3065 return 0; 3066 } 3067 3068 /* Intel Haswell and onwards; audio component with eld notifier */ 3069 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid, 3070 const int *port_map, int port_num, int dev_num, 3071 bool send_silent_stream) 3072 { 3073 struct hdmi_spec *spec; 3074 int err; 3075 3076 err = alloc_intel_hdmi(codec); 3077 if (err < 0) 3078 return err; 3079 spec = codec->spec; 3080 codec->dp_mst = true; 3081 spec->vendor_nid = vendor_nid; 3082 spec->port_map = port_map; 3083 spec->port_num = port_num; 3084 spec->intel_hsw_fixup = true; 3085 spec->dev_num = dev_num; 3086 3087 intel_haswell_enable_all_pins(codec, true); 3088 intel_haswell_fixup_enable_dp12(codec); 3089 3090 codec->display_power_control = 1; 3091 3092 codec->patch_ops.set_power_state = haswell_set_power_state; 3093 codec->depop_delay = 0; 3094 codec->auto_runtime_pm = 1; 3095 3096 spec->ops.setup_stream = i915_hsw_setup_stream; 3097 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 3098 3099 /* 3100 * Enable silent stream feature, if it is enabled via 3101 * module param or Kconfig option 3102 */ 3103 if (send_silent_stream) 3104 spec->silent_stream_type = SILENT_STREAM_I915; 3105 3106 return parse_intel_hdmi(codec); 3107 } 3108 3109 static int patch_i915_hsw_hdmi(struct hda_codec *codec) 3110 { 3111 return intel_hsw_common_init(codec, 0x08, NULL, 0, 3, 3112 enable_silent_stream); 3113 } 3114 3115 static int patch_i915_glk_hdmi(struct hda_codec *codec) 3116 { 3117 /* 3118 * Silent stream calls audio component .get_power() from 3119 * .pin_eld_notify(). On GLK this will deadlock in i915 due 3120 * to the audio vs. CDCLK workaround. 3121 */ 3122 return intel_hsw_common_init(codec, 0x0b, NULL, 0, 3, false); 3123 } 3124 3125 static int patch_i915_icl_hdmi(struct hda_codec *codec) 3126 { 3127 /* 3128 * pin to port mapping table where the value indicate the pin number and 3129 * the index indicate the port number. 3130 */ 3131 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb}; 3132 3133 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 3, 3134 enable_silent_stream); 3135 } 3136 3137 static int patch_i915_tgl_hdmi(struct hda_codec *codec) 3138 { 3139 /* 3140 * pin to port mapping table where the value indicate the pin number and 3141 * the index indicate the port number. 3142 */ 3143 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf}; 3144 3145 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 4, 3146 enable_silent_stream); 3147 } 3148 3149 static int patch_i915_adlp_hdmi(struct hda_codec *codec) 3150 { 3151 struct hdmi_spec *spec; 3152 int res; 3153 3154 res = patch_i915_tgl_hdmi(codec); 3155 if (!res) { 3156 spec = codec->spec; 3157 3158 if (spec->silent_stream_type) { 3159 spec->silent_stream_type = SILENT_STREAM_KAE; 3160 3161 #ifdef CONFIG_PM 3162 codec->patch_ops.resume = i915_adlp_hdmi_resume; 3163 codec->patch_ops.suspend = i915_adlp_hdmi_suspend; 3164 #endif 3165 } 3166 } 3167 3168 return res; 3169 } 3170 3171 /* Intel Baytrail and Braswell; with eld notifier */ 3172 static int patch_i915_byt_hdmi(struct hda_codec *codec) 3173 { 3174 struct hdmi_spec *spec; 3175 int err; 3176 3177 err = alloc_intel_hdmi(codec); 3178 if (err < 0) 3179 return err; 3180 spec = codec->spec; 3181 3182 /* For Valleyview/Cherryview, only the display codec is in the display 3183 * power well and can use link_power ops to request/release the power. 3184 */ 3185 codec->display_power_control = 1; 3186 3187 codec->depop_delay = 0; 3188 codec->auto_runtime_pm = 1; 3189 3190 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 3191 3192 return parse_intel_hdmi(codec); 3193 } 3194 3195 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ 3196 static int patch_i915_cpt_hdmi(struct hda_codec *codec) 3197 { 3198 int err; 3199 3200 err = alloc_intel_hdmi(codec); 3201 if (err < 0) 3202 return err; 3203 return parse_intel_hdmi(codec); 3204 } 3205 3206 /* 3207 * Shared non-generic implementations 3208 */ 3209 3210 static int simple_playback_build_pcms(struct hda_codec *codec) 3211 { 3212 struct hdmi_spec *spec = codec->spec; 3213 struct hda_pcm *info; 3214 unsigned int chans; 3215 struct hda_pcm_stream *pstr; 3216 struct hdmi_spec_per_cvt *per_cvt; 3217 3218 per_cvt = get_cvt(spec, 0); 3219 chans = get_wcaps(codec, per_cvt->cvt_nid); 3220 chans = get_wcaps_channels(chans); 3221 3222 info = snd_hda_codec_pcm_new(codec, "HDMI 0"); 3223 if (!info) 3224 return -ENOMEM; 3225 spec->pcm_rec[0].pcm = info; 3226 info->pcm_type = HDA_PCM_TYPE_HDMI; 3227 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3228 *pstr = spec->pcm_playback; 3229 pstr->nid = per_cvt->cvt_nid; 3230 if (pstr->channels_max <= 2 && chans && chans <= 16) 3231 pstr->channels_max = chans; 3232 3233 return 0; 3234 } 3235 3236 /* unsolicited event for jack sensing */ 3237 static void simple_hdmi_unsol_event(struct hda_codec *codec, 3238 unsigned int res) 3239 { 3240 snd_hda_jack_set_dirty_all(codec); 3241 snd_hda_jack_report_sync(codec); 3242 } 3243 3244 /* generic_hdmi_build_jack can be used for simple_hdmi, too, 3245 * as long as spec->pins[] is set correctly 3246 */ 3247 #define simple_hdmi_build_jack generic_hdmi_build_jack 3248 3249 static int simple_playback_build_controls(struct hda_codec *codec) 3250 { 3251 struct hdmi_spec *spec = codec->spec; 3252 struct hdmi_spec_per_cvt *per_cvt; 3253 int err; 3254 3255 per_cvt = get_cvt(spec, 0); 3256 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, 3257 per_cvt->cvt_nid, 3258 HDA_PCM_TYPE_HDMI); 3259 if (err < 0) 3260 return err; 3261 return simple_hdmi_build_jack(codec, 0); 3262 } 3263 3264 static int simple_playback_init(struct hda_codec *codec) 3265 { 3266 struct hdmi_spec *spec = codec->spec; 3267 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); 3268 hda_nid_t pin = per_pin->pin_nid; 3269 3270 snd_hda_codec_write(codec, pin, 0, 3271 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); 3272 /* some codecs require to unmute the pin */ 3273 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 3274 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, 3275 AMP_OUT_UNMUTE); 3276 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id); 3277 return 0; 3278 } 3279 3280 static void simple_playback_free(struct hda_codec *codec) 3281 { 3282 struct hdmi_spec *spec = codec->spec; 3283 3284 hdmi_array_free(spec); 3285 kfree(spec); 3286 } 3287 3288 /* 3289 * Nvidia specific implementations 3290 */ 3291 3292 #define Nv_VERB_SET_Channel_Allocation 0xF79 3293 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A 3294 #define Nv_VERB_SET_Audio_Protection_On 0xF98 3295 #define Nv_VERB_SET_Audio_Protection_Off 0xF99 3296 3297 #define nvhdmi_master_con_nid_7x 0x04 3298 #define nvhdmi_master_pin_nid_7x 0x05 3299 3300 static const hda_nid_t nvhdmi_con_nids_7x[4] = { 3301 /*front, rear, clfe, rear_surr */ 3302 0x6, 0x8, 0xa, 0xc, 3303 }; 3304 3305 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { 3306 /* set audio protect on */ 3307 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3308 /* enable digital output on pin widget */ 3309 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3310 {} /* terminator */ 3311 }; 3312 3313 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { 3314 /* set audio protect on */ 3315 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3316 /* enable digital output on pin widget */ 3317 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3318 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3319 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3320 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3321 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3322 {} /* terminator */ 3323 }; 3324 3325 #ifdef LIMITED_RATE_FMT_SUPPORT 3326 /* support only the safe format and rate */ 3327 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 3328 #define SUPPORTED_MAXBPS 16 3329 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE 3330 #else 3331 /* support all rates and formats */ 3332 #define SUPPORTED_RATES \ 3333 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ 3334 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ 3335 SNDRV_PCM_RATE_192000) 3336 #define SUPPORTED_MAXBPS 24 3337 #define SUPPORTED_FORMATS \ 3338 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 3339 #endif 3340 3341 static int nvhdmi_7x_init_2ch(struct hda_codec *codec) 3342 { 3343 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); 3344 return 0; 3345 } 3346 3347 static int nvhdmi_7x_init_8ch(struct hda_codec *codec) 3348 { 3349 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); 3350 return 0; 3351 } 3352 3353 static const unsigned int channels_2_6_8[] = { 3354 2, 6, 8 3355 }; 3356 3357 static const unsigned int channels_2_8[] = { 3358 2, 8 3359 }; 3360 3361 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { 3362 .count = ARRAY_SIZE(channels_2_6_8), 3363 .list = channels_2_6_8, 3364 .mask = 0, 3365 }; 3366 3367 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { 3368 .count = ARRAY_SIZE(channels_2_8), 3369 .list = channels_2_8, 3370 .mask = 0, 3371 }; 3372 3373 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, 3374 struct hda_codec *codec, 3375 struct snd_pcm_substream *substream) 3376 { 3377 struct hdmi_spec *spec = codec->spec; 3378 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; 3379 3380 switch (codec->preset->vendor_id) { 3381 case 0x10de0002: 3382 case 0x10de0003: 3383 case 0x10de0005: 3384 case 0x10de0006: 3385 hw_constraints_channels = &hw_constraints_2_8_channels; 3386 break; 3387 case 0x10de0007: 3388 hw_constraints_channels = &hw_constraints_2_6_8_channels; 3389 break; 3390 default: 3391 break; 3392 } 3393 3394 if (hw_constraints_channels != NULL) { 3395 snd_pcm_hw_constraint_list(substream->runtime, 0, 3396 SNDRV_PCM_HW_PARAM_CHANNELS, 3397 hw_constraints_channels); 3398 } else { 3399 snd_pcm_hw_constraint_step(substream->runtime, 0, 3400 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 3401 } 3402 3403 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3404 } 3405 3406 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, 3407 struct hda_codec *codec, 3408 struct snd_pcm_substream *substream) 3409 { 3410 struct hdmi_spec *spec = codec->spec; 3411 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3412 } 3413 3414 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3415 struct hda_codec *codec, 3416 unsigned int stream_tag, 3417 unsigned int format, 3418 struct snd_pcm_substream *substream) 3419 { 3420 struct hdmi_spec *spec = codec->spec; 3421 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3422 stream_tag, format, substream); 3423 } 3424 3425 static const struct hda_pcm_stream simple_pcm_playback = { 3426 .substreams = 1, 3427 .channels_min = 2, 3428 .channels_max = 2, 3429 .ops = { 3430 .open = simple_playback_pcm_open, 3431 .close = simple_playback_pcm_close, 3432 .prepare = simple_playback_pcm_prepare 3433 }, 3434 }; 3435 3436 static const struct hda_codec_ops simple_hdmi_patch_ops = { 3437 .build_controls = simple_playback_build_controls, 3438 .build_pcms = simple_playback_build_pcms, 3439 .init = simple_playback_init, 3440 .free = simple_playback_free, 3441 .unsol_event = simple_hdmi_unsol_event, 3442 }; 3443 3444 static int patch_simple_hdmi(struct hda_codec *codec, 3445 hda_nid_t cvt_nid, hda_nid_t pin_nid) 3446 { 3447 struct hdmi_spec *spec; 3448 struct hdmi_spec_per_cvt *per_cvt; 3449 struct hdmi_spec_per_pin *per_pin; 3450 3451 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 3452 if (!spec) 3453 return -ENOMEM; 3454 3455 spec->codec = codec; 3456 codec->spec = spec; 3457 hdmi_array_init(spec, 1); 3458 3459 spec->multiout.num_dacs = 0; /* no analog */ 3460 spec->multiout.max_channels = 2; 3461 spec->multiout.dig_out_nid = cvt_nid; 3462 spec->num_cvts = 1; 3463 spec->num_pins = 1; 3464 per_pin = snd_array_new(&spec->pins); 3465 per_cvt = snd_array_new(&spec->cvts); 3466 if (!per_pin || !per_cvt) { 3467 simple_playback_free(codec); 3468 return -ENOMEM; 3469 } 3470 per_cvt->cvt_nid = cvt_nid; 3471 per_pin->pin_nid = pin_nid; 3472 spec->pcm_playback = simple_pcm_playback; 3473 3474 codec->patch_ops = simple_hdmi_patch_ops; 3475 3476 return 0; 3477 } 3478 3479 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, 3480 int channels) 3481 { 3482 unsigned int chanmask; 3483 int chan = channels ? (channels - 1) : 1; 3484 3485 switch (channels) { 3486 default: 3487 case 0: 3488 case 2: 3489 chanmask = 0x00; 3490 break; 3491 case 4: 3492 chanmask = 0x08; 3493 break; 3494 case 6: 3495 chanmask = 0x0b; 3496 break; 3497 case 8: 3498 chanmask = 0x13; 3499 break; 3500 } 3501 3502 /* Set the audio infoframe channel allocation and checksum fields. The 3503 * channel count is computed implicitly by the hardware. */ 3504 snd_hda_codec_write(codec, 0x1, 0, 3505 Nv_VERB_SET_Channel_Allocation, chanmask); 3506 3507 snd_hda_codec_write(codec, 0x1, 0, 3508 Nv_VERB_SET_Info_Frame_Checksum, 3509 (0x71 - chan - chanmask)); 3510 } 3511 3512 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, 3513 struct hda_codec *codec, 3514 struct snd_pcm_substream *substream) 3515 { 3516 struct hdmi_spec *spec = codec->spec; 3517 int i; 3518 3519 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 3520 0, AC_VERB_SET_CHANNEL_STREAMID, 0); 3521 for (i = 0; i < 4; i++) { 3522 /* set the stream id */ 3523 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3524 AC_VERB_SET_CHANNEL_STREAMID, 0); 3525 /* set the stream format */ 3526 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3527 AC_VERB_SET_STREAM_FORMAT, 0); 3528 } 3529 3530 /* The audio hardware sends a channel count of 0x7 (8ch) when all the 3531 * streams are disabled. */ 3532 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3533 3534 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3535 } 3536 3537 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, 3538 struct hda_codec *codec, 3539 unsigned int stream_tag, 3540 unsigned int format, 3541 struct snd_pcm_substream *substream) 3542 { 3543 int chs; 3544 unsigned int dataDCC2, channel_id; 3545 int i; 3546 struct hdmi_spec *spec = codec->spec; 3547 struct hda_spdif_out *spdif; 3548 struct hdmi_spec_per_cvt *per_cvt; 3549 3550 mutex_lock(&codec->spdif_mutex); 3551 per_cvt = get_cvt(spec, 0); 3552 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); 3553 3554 chs = substream->runtime->channels; 3555 3556 dataDCC2 = 0x2; 3557 3558 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ 3559 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) 3560 snd_hda_codec_write(codec, 3561 nvhdmi_master_con_nid_7x, 3562 0, 3563 AC_VERB_SET_DIGI_CONVERT_1, 3564 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3565 3566 /* set the stream id */ 3567 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3568 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); 3569 3570 /* set the stream format */ 3571 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3572 AC_VERB_SET_STREAM_FORMAT, format); 3573 3574 /* turn on again (if needed) */ 3575 /* enable and set the channel status audio/data flag */ 3576 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { 3577 snd_hda_codec_write(codec, 3578 nvhdmi_master_con_nid_7x, 3579 0, 3580 AC_VERB_SET_DIGI_CONVERT_1, 3581 spdif->ctls & 0xff); 3582 snd_hda_codec_write(codec, 3583 nvhdmi_master_con_nid_7x, 3584 0, 3585 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3586 } 3587 3588 for (i = 0; i < 4; i++) { 3589 if (chs == 2) 3590 channel_id = 0; 3591 else 3592 channel_id = i * 2; 3593 3594 /* turn off SPDIF once; 3595 *otherwise the IEC958 bits won't be updated 3596 */ 3597 if (codec->spdif_status_reset && 3598 (spdif->ctls & AC_DIG1_ENABLE)) 3599 snd_hda_codec_write(codec, 3600 nvhdmi_con_nids_7x[i], 3601 0, 3602 AC_VERB_SET_DIGI_CONVERT_1, 3603 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3604 /* set the stream id */ 3605 snd_hda_codec_write(codec, 3606 nvhdmi_con_nids_7x[i], 3607 0, 3608 AC_VERB_SET_CHANNEL_STREAMID, 3609 (stream_tag << 4) | channel_id); 3610 /* set the stream format */ 3611 snd_hda_codec_write(codec, 3612 nvhdmi_con_nids_7x[i], 3613 0, 3614 AC_VERB_SET_STREAM_FORMAT, 3615 format); 3616 /* turn on again (if needed) */ 3617 /* enable and set the channel status audio/data flag */ 3618 if (codec->spdif_status_reset && 3619 (spdif->ctls & AC_DIG1_ENABLE)) { 3620 snd_hda_codec_write(codec, 3621 nvhdmi_con_nids_7x[i], 3622 0, 3623 AC_VERB_SET_DIGI_CONVERT_1, 3624 spdif->ctls & 0xff); 3625 snd_hda_codec_write(codec, 3626 nvhdmi_con_nids_7x[i], 3627 0, 3628 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3629 } 3630 } 3631 3632 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); 3633 3634 mutex_unlock(&codec->spdif_mutex); 3635 return 0; 3636 } 3637 3638 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { 3639 .substreams = 1, 3640 .channels_min = 2, 3641 .channels_max = 8, 3642 .nid = nvhdmi_master_con_nid_7x, 3643 .rates = SUPPORTED_RATES, 3644 .maxbps = SUPPORTED_MAXBPS, 3645 .formats = SUPPORTED_FORMATS, 3646 .ops = { 3647 .open = simple_playback_pcm_open, 3648 .close = nvhdmi_8ch_7x_pcm_close, 3649 .prepare = nvhdmi_8ch_7x_pcm_prepare 3650 }, 3651 }; 3652 3653 static int patch_nvhdmi_2ch(struct hda_codec *codec) 3654 { 3655 struct hdmi_spec *spec; 3656 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, 3657 nvhdmi_master_pin_nid_7x); 3658 if (err < 0) 3659 return err; 3660 3661 codec->patch_ops.init = nvhdmi_7x_init_2ch; 3662 /* override the PCM rates, etc, as the codec doesn't give full list */ 3663 spec = codec->spec; 3664 spec->pcm_playback.rates = SUPPORTED_RATES; 3665 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; 3666 spec->pcm_playback.formats = SUPPORTED_FORMATS; 3667 spec->nv_dp_workaround = true; 3668 return 0; 3669 } 3670 3671 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) 3672 { 3673 struct hdmi_spec *spec = codec->spec; 3674 int err = simple_playback_build_pcms(codec); 3675 if (!err) { 3676 struct hda_pcm *info = get_pcm_rec(spec, 0); 3677 info->own_chmap = true; 3678 } 3679 return err; 3680 } 3681 3682 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) 3683 { 3684 struct hdmi_spec *spec = codec->spec; 3685 struct hda_pcm *info; 3686 struct snd_pcm_chmap *chmap; 3687 int err; 3688 3689 err = simple_playback_build_controls(codec); 3690 if (err < 0) 3691 return err; 3692 3693 /* add channel maps */ 3694 info = get_pcm_rec(spec, 0); 3695 err = snd_pcm_add_chmap_ctls(info->pcm, 3696 SNDRV_PCM_STREAM_PLAYBACK, 3697 snd_pcm_alt_chmaps, 8, 0, &chmap); 3698 if (err < 0) 3699 return err; 3700 switch (codec->preset->vendor_id) { 3701 case 0x10de0002: 3702 case 0x10de0003: 3703 case 0x10de0005: 3704 case 0x10de0006: 3705 chmap->channel_mask = (1U << 2) | (1U << 8); 3706 break; 3707 case 0x10de0007: 3708 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); 3709 } 3710 return 0; 3711 } 3712 3713 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) 3714 { 3715 struct hdmi_spec *spec; 3716 int err = patch_nvhdmi_2ch(codec); 3717 if (err < 0) 3718 return err; 3719 spec = codec->spec; 3720 spec->multiout.max_channels = 8; 3721 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; 3722 codec->patch_ops.init = nvhdmi_7x_init_8ch; 3723 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; 3724 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; 3725 3726 /* Initialize the audio infoframe channel mask and checksum to something 3727 * valid */ 3728 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3729 3730 return 0; 3731 } 3732 3733 /* 3734 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: 3735 * - 0x10de0015 3736 * - 0x10de0040 3737 */ 3738 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, 3739 struct hdac_cea_channel_speaker_allocation *cap, int channels) 3740 { 3741 if (cap->ca_index == 0x00 && channels == 2) 3742 return SNDRV_CTL_TLVT_CHMAP_FIXED; 3743 3744 /* If the speaker allocation matches the channel count, it is OK. */ 3745 if (cap->channels != channels) 3746 return -1; 3747 3748 /* all channels are remappable freely */ 3749 return SNDRV_CTL_TLVT_CHMAP_VAR; 3750 } 3751 3752 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, 3753 int ca, int chs, unsigned char *map) 3754 { 3755 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) 3756 return -EINVAL; 3757 3758 return 0; 3759 } 3760 3761 /* map from pin NID to port; port is 0-based */ 3762 /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */ 3763 static int nvhdmi_pin2port(void *audio_ptr, int pin_nid) 3764 { 3765 return pin_nid - 4; 3766 } 3767 3768 /* reverse-map from port to pin NID: see above */ 3769 static int nvhdmi_port2pin(struct hda_codec *codec, int port) 3770 { 3771 return port + 4; 3772 } 3773 3774 static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = { 3775 .pin2port = nvhdmi_pin2port, 3776 .pin_eld_notify = generic_acomp_pin_eld_notify, 3777 .master_bind = generic_acomp_master_bind, 3778 .master_unbind = generic_acomp_master_unbind, 3779 }; 3780 3781 static int patch_nvhdmi(struct hda_codec *codec) 3782 { 3783 struct hdmi_spec *spec; 3784 int err; 3785 3786 err = alloc_generic_hdmi(codec); 3787 if (err < 0) 3788 return err; 3789 codec->dp_mst = true; 3790 3791 spec = codec->spec; 3792 3793 err = hdmi_parse_codec(codec); 3794 if (err < 0) { 3795 generic_spec_free(codec); 3796 return err; 3797 } 3798 3799 generic_hdmi_init_per_pins(codec); 3800 3801 spec->dyn_pin_out = true; 3802 3803 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3804 nvhdmi_chmap_cea_alloc_validate_get_type; 3805 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3806 spec->nv_dp_workaround = true; 3807 3808 codec->link_down_at_suspend = 1; 3809 3810 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin); 3811 3812 return 0; 3813 } 3814 3815 static int patch_nvhdmi_legacy(struct hda_codec *codec) 3816 { 3817 struct hdmi_spec *spec; 3818 int err; 3819 3820 err = patch_generic_hdmi(codec); 3821 if (err) 3822 return err; 3823 3824 spec = codec->spec; 3825 spec->dyn_pin_out = true; 3826 3827 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3828 nvhdmi_chmap_cea_alloc_validate_get_type; 3829 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3830 spec->nv_dp_workaround = true; 3831 3832 codec->link_down_at_suspend = 1; 3833 3834 return 0; 3835 } 3836 3837 /* 3838 * The HDA codec on NVIDIA Tegra contains two scratch registers that are 3839 * accessed using vendor-defined verbs. These registers can be used for 3840 * interoperability between the HDA and HDMI drivers. 3841 */ 3842 3843 /* Audio Function Group node */ 3844 #define NVIDIA_AFG_NID 0x01 3845 3846 /* 3847 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio 3848 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to 3849 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This 3850 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an 3851 * additional bit (at position 30) to signal the validity of the format. 3852 * 3853 * | 31 | 30 | 29 16 | 15 0 | 3854 * +---------+-------+--------+--------+ 3855 * | TRIGGER | VALID | UNUSED | FORMAT | 3856 * +-----------------------------------| 3857 * 3858 * Note that for the trigger bit to take effect it needs to change value 3859 * (i.e. it needs to be toggled). The trigger bit is not applicable from 3860 * TEGRA234 chip onwards, as new verb id 0xf80 will be used for interrupt 3861 * trigger to hdmi. 3862 */ 3863 #define NVIDIA_SET_HOST_INTR 0xf80 3864 #define NVIDIA_GET_SCRATCH0 0xfa6 3865 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 3866 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 3867 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 3868 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa 3869 #define NVIDIA_SCRATCH_TRIGGER (1 << 7) 3870 #define NVIDIA_SCRATCH_VALID (1 << 6) 3871 3872 #define NVIDIA_GET_SCRATCH1 0xfab 3873 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac 3874 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad 3875 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae 3876 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf 3877 3878 /* 3879 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, 3880 * the format is invalidated so that the HDMI codec can be disabled. 3881 */ 3882 static void tegra_hdmi_set_format(struct hda_codec *codec, 3883 hda_nid_t cvt_nid, 3884 unsigned int format) 3885 { 3886 unsigned int value; 3887 unsigned int nid = NVIDIA_AFG_NID; 3888 struct hdmi_spec *spec = codec->spec; 3889 3890 /* 3891 * Tegra HDA codec design from TEGRA234 chip onwards support DP MST. 3892 * This resulted in moving scratch registers from audio function 3893 * group to converter widget context. So CVT NID should be used for 3894 * scratch register read/write for DP MST supported Tegra HDA codec. 3895 */ 3896 if (codec->dp_mst) 3897 nid = cvt_nid; 3898 3899 /* bits [31:30] contain the trigger and valid bits */ 3900 value = snd_hda_codec_read(codec, nid, 0, 3901 NVIDIA_GET_SCRATCH0, 0); 3902 value = (value >> 24) & 0xff; 3903 3904 /* bits [15:0] are used to store the HDA format */ 3905 snd_hda_codec_write(codec, nid, 0, 3906 NVIDIA_SET_SCRATCH0_BYTE0, 3907 (format >> 0) & 0xff); 3908 snd_hda_codec_write(codec, nid, 0, 3909 NVIDIA_SET_SCRATCH0_BYTE1, 3910 (format >> 8) & 0xff); 3911 3912 /* bits [16:24] are unused */ 3913 snd_hda_codec_write(codec, nid, 0, 3914 NVIDIA_SET_SCRATCH0_BYTE2, 0); 3915 3916 /* 3917 * Bit 30 signals that the data is valid and hence that HDMI audio can 3918 * be enabled. 3919 */ 3920 if (format == 0) 3921 value &= ~NVIDIA_SCRATCH_VALID; 3922 else 3923 value |= NVIDIA_SCRATCH_VALID; 3924 3925 if (spec->hdmi_intr_trig_ctrl) { 3926 /* 3927 * For Tegra HDA Codec design from TEGRA234 onwards, the 3928 * Interrupt to hdmi driver is triggered by writing 3929 * non-zero values to verb 0xF80 instead of 31st bit of 3930 * scratch register. 3931 */ 3932 snd_hda_codec_write(codec, nid, 0, 3933 NVIDIA_SET_SCRATCH0_BYTE3, value); 3934 snd_hda_codec_write(codec, nid, 0, 3935 NVIDIA_SET_HOST_INTR, 0x1); 3936 } else { 3937 /* 3938 * Whenever the 31st trigger bit is toggled, an interrupt is raised 3939 * in the HDMI codec. The HDMI driver will use that as trigger 3940 * to update its configuration. 3941 */ 3942 value ^= NVIDIA_SCRATCH_TRIGGER; 3943 3944 snd_hda_codec_write(codec, nid, 0, 3945 NVIDIA_SET_SCRATCH0_BYTE3, value); 3946 } 3947 } 3948 3949 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, 3950 struct hda_codec *codec, 3951 unsigned int stream_tag, 3952 unsigned int format, 3953 struct snd_pcm_substream *substream) 3954 { 3955 int err; 3956 3957 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, 3958 format, substream); 3959 if (err < 0) 3960 return err; 3961 3962 /* notify the HDMI codec of the format change */ 3963 tegra_hdmi_set_format(codec, hinfo->nid, format); 3964 3965 return 0; 3966 } 3967 3968 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, 3969 struct hda_codec *codec, 3970 struct snd_pcm_substream *substream) 3971 { 3972 /* invalidate the format in the HDMI codec */ 3973 tegra_hdmi_set_format(codec, hinfo->nid, 0); 3974 3975 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); 3976 } 3977 3978 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) 3979 { 3980 struct hdmi_spec *spec = codec->spec; 3981 unsigned int i; 3982 3983 for (i = 0; i < spec->num_pins; i++) { 3984 struct hda_pcm *pcm = get_pcm_rec(spec, i); 3985 3986 if (pcm->pcm_type == type) 3987 return pcm; 3988 } 3989 3990 return NULL; 3991 } 3992 3993 static int tegra_hdmi_build_pcms(struct hda_codec *codec) 3994 { 3995 struct hda_pcm_stream *stream; 3996 struct hda_pcm *pcm; 3997 int err; 3998 3999 err = generic_hdmi_build_pcms(codec); 4000 if (err < 0) 4001 return err; 4002 4003 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); 4004 if (!pcm) 4005 return -ENODEV; 4006 4007 /* 4008 * Override ->prepare() and ->cleanup() operations to notify the HDMI 4009 * codec about format changes. 4010 */ 4011 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 4012 stream->ops.prepare = tegra_hdmi_pcm_prepare; 4013 stream->ops.cleanup = tegra_hdmi_pcm_cleanup; 4014 4015 return 0; 4016 } 4017 4018 static int tegra_hdmi_init(struct hda_codec *codec) 4019 { 4020 struct hdmi_spec *spec = codec->spec; 4021 int i, err; 4022 4023 err = hdmi_parse_codec(codec); 4024 if (err < 0) { 4025 generic_spec_free(codec); 4026 return err; 4027 } 4028 4029 for (i = 0; i < spec->num_cvts; i++) 4030 snd_hda_codec_write(codec, spec->cvt_nids[i], 0, 4031 AC_VERB_SET_DIGI_CONVERT_1, 4032 AC_DIG1_ENABLE); 4033 4034 generic_hdmi_init_per_pins(codec); 4035 4036 codec->depop_delay = 10; 4037 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; 4038 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4039 nvhdmi_chmap_cea_alloc_validate_get_type; 4040 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 4041 4042 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4043 nvhdmi_chmap_cea_alloc_validate_get_type; 4044 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 4045 spec->nv_dp_workaround = true; 4046 4047 return 0; 4048 } 4049 4050 static int patch_tegra_hdmi(struct hda_codec *codec) 4051 { 4052 int err; 4053 4054 err = alloc_generic_hdmi(codec); 4055 if (err < 0) 4056 return err; 4057 4058 return tegra_hdmi_init(codec); 4059 } 4060 4061 static int patch_tegra234_hdmi(struct hda_codec *codec) 4062 { 4063 struct hdmi_spec *spec; 4064 int err; 4065 4066 err = alloc_generic_hdmi(codec); 4067 if (err < 0) 4068 return err; 4069 4070 codec->dp_mst = true; 4071 spec = codec->spec; 4072 spec->dyn_pin_out = true; 4073 spec->hdmi_intr_trig_ctrl = true; 4074 4075 return tegra_hdmi_init(codec); 4076 } 4077 4078 /* 4079 * ATI/AMD-specific implementations 4080 */ 4081 4082 #define is_amdhdmi_rev3_or_later(codec) \ 4083 ((codec)->core.vendor_id == 0x1002aa01 && \ 4084 ((codec)->core.revision_id & 0xff00) >= 0x0300) 4085 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) 4086 4087 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ 4088 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 4089 #define ATI_VERB_SET_DOWNMIX_INFO 0x772 4090 #define ATI_VERB_SET_MULTICHANNEL_01 0x777 4091 #define ATI_VERB_SET_MULTICHANNEL_23 0x778 4092 #define ATI_VERB_SET_MULTICHANNEL_45 0x779 4093 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a 4094 #define ATI_VERB_SET_HBR_CONTROL 0x77c 4095 #define ATI_VERB_SET_MULTICHANNEL_1 0x785 4096 #define ATI_VERB_SET_MULTICHANNEL_3 0x786 4097 #define ATI_VERB_SET_MULTICHANNEL_5 0x787 4098 #define ATI_VERB_SET_MULTICHANNEL_7 0x788 4099 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 4100 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 4101 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 4102 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 4103 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 4104 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 4105 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a 4106 #define ATI_VERB_GET_HBR_CONTROL 0xf7c 4107 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 4108 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 4109 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 4110 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 4111 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 4112 4113 /* AMD specific HDA cvt verbs */ 4114 #define ATI_VERB_SET_RAMP_RATE 0x770 4115 #define ATI_VERB_GET_RAMP_RATE 0xf70 4116 4117 #define ATI_OUT_ENABLE 0x1 4118 4119 #define ATI_MULTICHANNEL_MODE_PAIRED 0 4120 #define ATI_MULTICHANNEL_MODE_SINGLE 1 4121 4122 #define ATI_HBR_CAPABLE 0x01 4123 #define ATI_HBR_ENABLE 0x10 4124 4125 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 4126 int dev_id, unsigned char *buf, int *eld_size) 4127 { 4128 WARN_ON(dev_id != 0); 4129 /* call hda_eld.c ATI/AMD-specific function */ 4130 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, 4131 is_amdhdmi_rev3_or_later(codec)); 4132 } 4133 4134 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, 4135 hda_nid_t pin_nid, int dev_id, int ca, 4136 int active_channels, int conn_type) 4137 { 4138 WARN_ON(dev_id != 0); 4139 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); 4140 } 4141 4142 static int atihdmi_paired_swap_fc_lfe(int pos) 4143 { 4144 /* 4145 * ATI/AMD have automatic FC/LFE swap built-in 4146 * when in pairwise mapping mode. 4147 */ 4148 4149 switch (pos) { 4150 /* see channel_allocations[].speakers[] */ 4151 case 2: return 3; 4152 case 3: return 2; 4153 default: break; 4154 } 4155 4156 return pos; 4157 } 4158 4159 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, 4160 int ca, int chs, unsigned char *map) 4161 { 4162 struct hdac_cea_channel_speaker_allocation *cap; 4163 int i, j; 4164 4165 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ 4166 4167 cap = snd_hdac_get_ch_alloc_from_ca(ca); 4168 for (i = 0; i < chs; ++i) { 4169 int mask = snd_hdac_chmap_to_spk_mask(map[i]); 4170 bool ok = false; 4171 bool companion_ok = false; 4172 4173 if (!mask) 4174 continue; 4175 4176 for (j = 0 + i % 2; j < 8; j += 2) { 4177 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); 4178 if (cap->speakers[chan_idx] == mask) { 4179 /* channel is in a supported position */ 4180 ok = true; 4181 4182 if (i % 2 == 0 && i + 1 < chs) { 4183 /* even channel, check the odd companion */ 4184 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); 4185 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); 4186 int comp_mask_act = cap->speakers[comp_chan_idx]; 4187 4188 if (comp_mask_req == comp_mask_act) 4189 companion_ok = true; 4190 else 4191 return -EINVAL; 4192 } 4193 break; 4194 } 4195 } 4196 4197 if (!ok) 4198 return -EINVAL; 4199 4200 if (companion_ok) 4201 i++; /* companion channel already checked */ 4202 } 4203 4204 return 0; 4205 } 4206 4207 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, 4208 hda_nid_t pin_nid, int hdmi_slot, int stream_channel) 4209 { 4210 struct hda_codec *codec = hdac_to_hda_codec(hdac); 4211 int verb; 4212 int ati_channel_setup = 0; 4213 4214 if (hdmi_slot > 7) 4215 return -EINVAL; 4216 4217 if (!has_amd_full_remap_support(codec)) { 4218 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); 4219 4220 /* In case this is an odd slot but without stream channel, do not 4221 * disable the slot since the corresponding even slot could have a 4222 * channel. In case neither have a channel, the slot pair will be 4223 * disabled when this function is called for the even slot. */ 4224 if (hdmi_slot % 2 != 0 && stream_channel == 0xf) 4225 return 0; 4226 4227 hdmi_slot -= hdmi_slot % 2; 4228 4229 if (stream_channel != 0xf) 4230 stream_channel -= stream_channel % 2; 4231 } 4232 4233 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; 4234 4235 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ 4236 4237 if (stream_channel != 0xf) 4238 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; 4239 4240 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); 4241 } 4242 4243 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, 4244 hda_nid_t pin_nid, int asp_slot) 4245 { 4246 struct hda_codec *codec = hdac_to_hda_codec(hdac); 4247 bool was_odd = false; 4248 int ati_asp_slot = asp_slot; 4249 int verb; 4250 int ati_channel_setup; 4251 4252 if (asp_slot > 7) 4253 return -EINVAL; 4254 4255 if (!has_amd_full_remap_support(codec)) { 4256 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); 4257 if (ati_asp_slot % 2 != 0) { 4258 ati_asp_slot -= 1; 4259 was_odd = true; 4260 } 4261 } 4262 4263 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; 4264 4265 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); 4266 4267 if (!(ati_channel_setup & ATI_OUT_ENABLE)) 4268 return 0xf; 4269 4270 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; 4271 } 4272 4273 static int atihdmi_paired_chmap_cea_alloc_validate_get_type( 4274 struct hdac_chmap *chmap, 4275 struct hdac_cea_channel_speaker_allocation *cap, 4276 int channels) 4277 { 4278 int c; 4279 4280 /* 4281 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so 4282 * we need to take that into account (a single channel may take 2 4283 * channel slots if we need to carry a silent channel next to it). 4284 * On Rev3+ AMD codecs this function is not used. 4285 */ 4286 int chanpairs = 0; 4287 4288 /* We only produce even-numbered channel count TLVs */ 4289 if ((channels % 2) != 0) 4290 return -1; 4291 4292 for (c = 0; c < 7; c += 2) { 4293 if (cap->speakers[c] || cap->speakers[c+1]) 4294 chanpairs++; 4295 } 4296 4297 if (chanpairs * 2 != channels) 4298 return -1; 4299 4300 return SNDRV_CTL_TLVT_CHMAP_PAIRED; 4301 } 4302 4303 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, 4304 struct hdac_cea_channel_speaker_allocation *cap, 4305 unsigned int *chmap, int channels) 4306 { 4307 /* produce paired maps for pre-rev3 ATI/AMD codecs */ 4308 int count = 0; 4309 int c; 4310 4311 for (c = 7; c >= 0; c--) { 4312 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); 4313 int spk = cap->speakers[chan]; 4314 if (!spk) { 4315 /* add N/A channel if the companion channel is occupied */ 4316 if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) 4317 chmap[count++] = SNDRV_CHMAP_NA; 4318 4319 continue; 4320 } 4321 4322 chmap[count++] = snd_hdac_spk_to_chmap(spk); 4323 } 4324 4325 WARN_ON(count != channels); 4326 } 4327 4328 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 4329 int dev_id, bool hbr) 4330 { 4331 int hbr_ctl, hbr_ctl_new; 4332 4333 WARN_ON(dev_id != 0); 4334 4335 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); 4336 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { 4337 if (hbr) 4338 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; 4339 else 4340 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; 4341 4342 codec_dbg(codec, 4343 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", 4344 pin_nid, 4345 hbr_ctl == hbr_ctl_new ? "" : "new-", 4346 hbr_ctl_new); 4347 4348 if (hbr_ctl != hbr_ctl_new) 4349 snd_hda_codec_write(codec, pin_nid, 0, 4350 ATI_VERB_SET_HBR_CONTROL, 4351 hbr_ctl_new); 4352 4353 } else if (hbr) 4354 return -EINVAL; 4355 4356 return 0; 4357 } 4358 4359 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 4360 hda_nid_t pin_nid, int dev_id, 4361 u32 stream_tag, int format) 4362 { 4363 if (is_amdhdmi_rev3_or_later(codec)) { 4364 int ramp_rate = 180; /* default as per AMD spec */ 4365 /* disable ramp-up/down for non-pcm as per AMD spec */ 4366 if (format & AC_FMT_TYPE_NON_PCM) 4367 ramp_rate = 0; 4368 4369 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); 4370 } 4371 4372 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 4373 stream_tag, format); 4374 } 4375 4376 4377 static int atihdmi_init(struct hda_codec *codec) 4378 { 4379 struct hdmi_spec *spec = codec->spec; 4380 int pin_idx, err; 4381 4382 err = generic_hdmi_init(codec); 4383 4384 if (err) 4385 return err; 4386 4387 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 4388 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 4389 4390 /* make sure downmix information in infoframe is zero */ 4391 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); 4392 4393 /* enable channel-wise remap mode if supported */ 4394 if (has_amd_full_remap_support(codec)) 4395 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 4396 ATI_VERB_SET_MULTICHANNEL_MODE, 4397 ATI_MULTICHANNEL_MODE_SINGLE); 4398 } 4399 codec->auto_runtime_pm = 1; 4400 4401 return 0; 4402 } 4403 4404 /* map from pin NID to port; port is 0-based */ 4405 /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */ 4406 static int atihdmi_pin2port(void *audio_ptr, int pin_nid) 4407 { 4408 return pin_nid / 2 - 1; 4409 } 4410 4411 /* reverse-map from port to pin NID: see above */ 4412 static int atihdmi_port2pin(struct hda_codec *codec, int port) 4413 { 4414 return port * 2 + 3; 4415 } 4416 4417 static const struct drm_audio_component_audio_ops atihdmi_audio_ops = { 4418 .pin2port = atihdmi_pin2port, 4419 .pin_eld_notify = generic_acomp_pin_eld_notify, 4420 .master_bind = generic_acomp_master_bind, 4421 .master_unbind = generic_acomp_master_unbind, 4422 }; 4423 4424 static int patch_atihdmi(struct hda_codec *codec) 4425 { 4426 struct hdmi_spec *spec; 4427 struct hdmi_spec_per_cvt *per_cvt; 4428 int err, cvt_idx; 4429 4430 err = patch_generic_hdmi(codec); 4431 4432 if (err) 4433 return err; 4434 4435 codec->patch_ops.init = atihdmi_init; 4436 4437 spec = codec->spec; 4438 4439 spec->static_pcm_mapping = true; 4440 4441 spec->ops.pin_get_eld = atihdmi_pin_get_eld; 4442 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; 4443 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; 4444 spec->ops.setup_stream = atihdmi_setup_stream; 4445 4446 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; 4447 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; 4448 4449 if (!has_amd_full_remap_support(codec)) { 4450 /* override to ATI/AMD-specific versions with pairwise mapping */ 4451 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4452 atihdmi_paired_chmap_cea_alloc_validate_get_type; 4453 spec->chmap.ops.cea_alloc_to_tlv_chmap = 4454 atihdmi_paired_cea_alloc_to_tlv_chmap; 4455 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; 4456 } 4457 4458 /* ATI/AMD converters do not advertise all of their capabilities */ 4459 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 4460 per_cvt = get_cvt(spec, cvt_idx); 4461 per_cvt->channels_max = max(per_cvt->channels_max, 8u); 4462 per_cvt->rates |= SUPPORTED_RATES; 4463 per_cvt->formats |= SUPPORTED_FORMATS; 4464 per_cvt->maxbps = max(per_cvt->maxbps, 24u); 4465 } 4466 4467 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); 4468 4469 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing 4470 * the link-down as is. Tell the core to allow it. 4471 */ 4472 codec->link_down_at_suspend = 1; 4473 4474 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin); 4475 4476 return 0; 4477 } 4478 4479 /* VIA HDMI Implementation */ 4480 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ 4481 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ 4482 4483 static int patch_via_hdmi(struct hda_codec *codec) 4484 { 4485 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); 4486 } 4487 4488 static int patch_gf_hdmi(struct hda_codec *codec) 4489 { 4490 int err; 4491 4492 err = patch_generic_hdmi(codec); 4493 if (err) 4494 return err; 4495 4496 /* 4497 * Glenfly GPUs have two codecs, stream switches from one codec to 4498 * another, need to do actual clean-ups in codec_cleanup_stream 4499 */ 4500 codec->no_sticky_stream = 1; 4501 return 0; 4502 } 4503 4504 /* 4505 * patch entries 4506 */ 4507 static const struct hda_device_id snd_hda_id_hdmi[] = { 4508 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), 4509 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), 4510 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), 4511 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), 4512 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), 4513 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), 4514 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), 4515 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch), 4516 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4517 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4518 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x), 4519 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4520 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4521 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), 4522 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy), 4523 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy), 4524 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy), 4525 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy), 4526 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy), 4527 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy), 4528 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy), 4529 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy), 4530 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy), 4531 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy), 4532 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy), 4533 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy), 4534 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy), 4535 /* 17 is known to be absent */ 4536 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy), 4537 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy), 4538 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy), 4539 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy), 4540 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy), 4541 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), 4542 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), 4543 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), 4544 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), 4545 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi), 4546 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi), 4547 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), 4548 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), 4549 HDA_CODEC_ENTRY(0x10de0031, "Tegra234 HDMI/DP", patch_tegra234_hdmi), 4550 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), 4551 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), 4552 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), 4553 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), 4554 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), 4555 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi), 4556 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi), 4557 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), 4558 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi), 4559 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), 4560 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi), 4561 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi), 4562 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), 4563 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), 4564 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), 4565 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), 4566 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi), 4567 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi), 4568 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi), 4569 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi), 4570 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi), 4571 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), 4572 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi), 4573 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), 4574 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi), 4575 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), 4576 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), 4577 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi), 4578 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi), 4579 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi), 4580 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi), 4581 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi), 4582 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi), 4583 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi), 4584 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi), 4585 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), 4586 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), 4587 HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi), 4588 HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi), 4589 HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi), 4590 HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi), 4591 HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi), 4592 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), 4593 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), 4594 HDA_CODEC_ENTRY(0x67663d82, "Arise 82 HDMI/DP", patch_gf_hdmi), 4595 HDA_CODEC_ENTRY(0x67663d83, "Arise 83 HDMI/DP", patch_gf_hdmi), 4596 HDA_CODEC_ENTRY(0x67663d84, "Arise 84 HDMI/DP", patch_gf_hdmi), 4597 HDA_CODEC_ENTRY(0x67663d85, "Arise 85 HDMI/DP", patch_gf_hdmi), 4598 HDA_CODEC_ENTRY(0x67663d86, "Arise 86 HDMI/DP", patch_gf_hdmi), 4599 HDA_CODEC_ENTRY(0x67663d87, "Arise 87 HDMI/DP", patch_gf_hdmi), 4600 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), 4601 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), 4602 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), 4603 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), 4604 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4605 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), 4606 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), 4607 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), 4608 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), 4609 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4610 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), 4611 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), 4612 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), 4613 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), 4614 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), 4615 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), 4616 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), 4617 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), 4618 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), 4619 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi), 4620 HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi), 4621 HDA_CODEC_ENTRY(0x80862814, "DG1 HDMI", patch_i915_tgl_hdmi), 4622 HDA_CODEC_ENTRY(0x80862815, "Alderlake HDMI", patch_i915_tgl_hdmi), 4623 HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI", patch_i915_tgl_hdmi), 4624 HDA_CODEC_ENTRY(0x80862818, "Raptorlake HDMI", patch_i915_tgl_hdmi), 4625 HDA_CODEC_ENTRY(0x80862819, "DG2 HDMI", patch_i915_tgl_hdmi), 4626 HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi), 4627 HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi), 4628 HDA_CODEC_ENTRY(0x8086281c, "Alderlake-P HDMI", patch_i915_adlp_hdmi), 4629 HDA_CODEC_ENTRY(0x8086281f, "Raptorlake-P HDMI", patch_i915_adlp_hdmi), 4630 HDA_CODEC_ENTRY(0x8086281d, "Meteorlake HDMI", patch_i915_adlp_hdmi), 4631 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), 4632 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), 4633 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), 4634 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), 4635 /* special ID for generic HDMI */ 4636 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), 4637 {} /* terminator */ 4638 }; 4639 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); 4640 4641 MODULE_LICENSE("GPL"); 4642 MODULE_DESCRIPTION("HDMI HD-audio codec"); 4643 MODULE_ALIAS("snd-hda-codec-intelhdmi"); 4644 MODULE_ALIAS("snd-hda-codec-nvhdmi"); 4645 MODULE_ALIAS("snd-hda-codec-atihdmi"); 4646 4647 static struct hda_codec_driver hdmi_driver = { 4648 .id = snd_hda_id_hdmi, 4649 }; 4650 4651 module_hda_codec_driver(hdmi_driver); 4652