1 /* 2 * 3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs 4 * 5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. 6 * Copyright (c) 2006 ATI Technologies Inc. 7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved. 8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com> 9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> 10 * 11 * Authors: 12 * Wu Fengguang <wfg@linux.intel.com> 13 * 14 * Maintained by: 15 * Wu Fengguang <wfg@linux.intel.com> 16 * 17 * This program is free software; you can redistribute it and/or modify it 18 * under the terms of the GNU General Public License as published by the Free 19 * Software Foundation; either version 2 of the License, or (at your option) 20 * any later version. 21 * 22 * This program is distributed in the hope that it will be useful, but 23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 25 * for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software Foundation, 29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 30 */ 31 32 #include <linux/init.h> 33 #include <linux/delay.h> 34 #include <linux/slab.h> 35 #include <linux/module.h> 36 #include <sound/core.h> 37 #include <sound/jack.h> 38 #include <sound/asoundef.h> 39 #include <sound/tlv.h> 40 #include <sound/hdaudio.h> 41 #include <sound/hda_i915.h> 42 #include <sound/hda_chmap.h> 43 #include "hda_codec.h" 44 #include "hda_local.h" 45 #include "hda_jack.h" 46 47 static bool static_hdmi_pcm; 48 module_param(static_hdmi_pcm, bool, 0644); 49 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); 50 51 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807) 52 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808) 53 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809) 54 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a) 55 #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b) 56 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \ 57 || is_skylake(codec) || is_broxton(codec) \ 58 || is_kabylake(codec)) 59 60 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882) 61 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883) 62 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec)) 63 64 struct hdmi_spec_per_cvt { 65 hda_nid_t cvt_nid; 66 int assigned; 67 unsigned int channels_min; 68 unsigned int channels_max; 69 u32 rates; 70 u64 formats; 71 unsigned int maxbps; 72 }; 73 74 /* max. connections to a widget */ 75 #define HDA_MAX_CONNECTIONS 32 76 77 struct hdmi_spec_per_pin { 78 hda_nid_t pin_nid; 79 int dev_id; 80 /* pin idx, different device entries on the same pin use the same idx */ 81 int pin_nid_idx; 82 int num_mux_nids; 83 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; 84 int mux_idx; 85 hda_nid_t cvt_nid; 86 87 struct hda_codec *codec; 88 struct hdmi_eld sink_eld; 89 struct mutex lock; 90 struct delayed_work work; 91 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ 92 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ 93 int repoll_count; 94 bool setup; /* the stream has been set up by prepare callback */ 95 int channels; /* current number of channels */ 96 bool non_pcm; 97 bool chmap_set; /* channel-map override by ALSA API? */ 98 unsigned char chmap[8]; /* ALSA API channel-map */ 99 #ifdef CONFIG_SND_PROC_FS 100 struct snd_info_entry *proc_entry; 101 #endif 102 }; 103 104 /* operations used by generic code that can be overridden by patches */ 105 struct hdmi_ops { 106 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, 107 unsigned char *buf, int *eld_size); 108 109 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, 110 int ca, int active_channels, int conn_type); 111 112 /* enable/disable HBR (HD passthrough) */ 113 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr); 114 115 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, 116 hda_nid_t pin_nid, u32 stream_tag, int format); 117 118 void (*pin_cvt_fixup)(struct hda_codec *codec, 119 struct hdmi_spec_per_pin *per_pin, 120 hda_nid_t cvt_nid); 121 }; 122 123 struct hdmi_pcm { 124 struct hda_pcm *pcm; 125 struct snd_jack *jack; 126 struct snd_kcontrol *eld_ctl; 127 }; 128 129 struct hdmi_spec { 130 int num_cvts; 131 struct snd_array cvts; /* struct hdmi_spec_per_cvt */ 132 hda_nid_t cvt_nids[4]; /* only for haswell fix */ 133 134 /* 135 * num_pins is the number of virtual pins 136 * for example, there are 3 pins, and each pin 137 * has 4 device entries, then the num_pins is 12 138 */ 139 int num_pins; 140 /* 141 * num_nids is the number of real pins 142 * In the above example, num_nids is 3 143 */ 144 int num_nids; 145 /* 146 * dev_num is the number of device entries 147 * on each pin. 148 * In the above example, dev_num is 4 149 */ 150 int dev_num; 151 struct snd_array pins; /* struct hdmi_spec_per_pin */ 152 struct hdmi_pcm pcm_rec[16]; 153 struct mutex pcm_lock; 154 /* pcm_bitmap means which pcms have been assigned to pins*/ 155 unsigned long pcm_bitmap; 156 int pcm_used; /* counter of pcm_rec[] */ 157 /* bitmap shows whether the pcm is opened in user space 158 * bit 0 means the first playback PCM (PCM3); 159 * bit 1 means the second playback PCM, and so on. 160 */ 161 unsigned long pcm_in_use; 162 163 struct hdmi_eld temp_eld; 164 struct hdmi_ops ops; 165 166 bool dyn_pin_out; 167 bool dyn_pcm_assign; 168 /* 169 * Non-generic VIA/NVIDIA specific 170 */ 171 struct hda_multi_out multiout; 172 struct hda_pcm_stream pcm_playback; 173 174 /* i915/powerwell (Haswell+/Valleyview+) specific */ 175 bool use_acomp_notifier; /* use i915 eld_notify callback for hotplug */ 176 struct i915_audio_component_audio_ops i915_audio_ops; 177 bool i915_bound; /* was i915 bound in this driver? */ 178 179 struct hdac_chmap chmap; 180 }; 181 182 #ifdef CONFIG_SND_HDA_I915 183 static inline bool codec_has_acomp(struct hda_codec *codec) 184 { 185 struct hdmi_spec *spec = codec->spec; 186 return spec->use_acomp_notifier; 187 } 188 #else 189 #define codec_has_acomp(codec) false 190 #endif 191 192 struct hdmi_audio_infoframe { 193 u8 type; /* 0x84 */ 194 u8 ver; /* 0x01 */ 195 u8 len; /* 0x0a */ 196 197 u8 checksum; 198 199 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ 200 u8 SS01_SF24; 201 u8 CXT04; 202 u8 CA; 203 u8 LFEPBL01_LSV36_DM_INH7; 204 }; 205 206 struct dp_audio_infoframe { 207 u8 type; /* 0x84 */ 208 u8 len; /* 0x1b */ 209 u8 ver; /* 0x11 << 2 */ 210 211 u8 CC02_CT47; /* match with HDMI infoframe from this on */ 212 u8 SS01_SF24; 213 u8 CXT04; 214 u8 CA; 215 u8 LFEPBL01_LSV36_DM_INH7; 216 }; 217 218 union audio_infoframe { 219 struct hdmi_audio_infoframe hdmi; 220 struct dp_audio_infoframe dp; 221 u8 bytes[0]; 222 }; 223 224 /* 225 * HDMI routines 226 */ 227 228 #define get_pin(spec, idx) \ 229 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) 230 #define get_cvt(spec, idx) \ 231 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) 232 /* obtain hdmi_pcm object assigned to idx */ 233 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) 234 /* obtain hda_pcm object assigned to idx */ 235 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) 236 237 static int pin_id_to_pin_index(struct hda_codec *codec, 238 hda_nid_t pin_nid, int dev_id) 239 { 240 struct hdmi_spec *spec = codec->spec; 241 int pin_idx; 242 struct hdmi_spec_per_pin *per_pin; 243 244 /* 245 * (dev_id == -1) means it is NON-MST pin 246 * return the first virtual pin on this port 247 */ 248 if (dev_id == -1) 249 dev_id = 0; 250 251 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 252 per_pin = get_pin(spec, pin_idx); 253 if ((per_pin->pin_nid == pin_nid) && 254 (per_pin->dev_id == dev_id)) 255 return pin_idx; 256 } 257 258 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid); 259 return -EINVAL; 260 } 261 262 static int hinfo_to_pcm_index(struct hda_codec *codec, 263 struct hda_pcm_stream *hinfo) 264 { 265 struct hdmi_spec *spec = codec->spec; 266 int pcm_idx; 267 268 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) 269 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) 270 return pcm_idx; 271 272 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo); 273 return -EINVAL; 274 } 275 276 static int hinfo_to_pin_index(struct hda_codec *codec, 277 struct hda_pcm_stream *hinfo) 278 { 279 struct hdmi_spec *spec = codec->spec; 280 struct hdmi_spec_per_pin *per_pin; 281 int pin_idx; 282 283 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 284 per_pin = get_pin(spec, pin_idx); 285 if (per_pin->pcm && 286 per_pin->pcm->pcm->stream == hinfo) 287 return pin_idx; 288 } 289 290 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo); 291 return -EINVAL; 292 } 293 294 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, 295 int pcm_idx) 296 { 297 int i; 298 struct hdmi_spec_per_pin *per_pin; 299 300 for (i = 0; i < spec->num_pins; i++) { 301 per_pin = get_pin(spec, i); 302 if (per_pin->pcm_idx == pcm_idx) 303 return per_pin; 304 } 305 return NULL; 306 } 307 308 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) 309 { 310 struct hdmi_spec *spec = codec->spec; 311 int cvt_idx; 312 313 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) 314 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) 315 return cvt_idx; 316 317 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid); 318 return -EINVAL; 319 } 320 321 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, 322 struct snd_ctl_elem_info *uinfo) 323 { 324 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 325 struct hdmi_spec *spec = codec->spec; 326 struct hdmi_spec_per_pin *per_pin; 327 struct hdmi_eld *eld; 328 int pcm_idx; 329 330 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 331 332 pcm_idx = kcontrol->private_value; 333 mutex_lock(&spec->pcm_lock); 334 per_pin = pcm_idx_to_pin(spec, pcm_idx); 335 if (!per_pin) { 336 /* no pin is bound to the pcm */ 337 uinfo->count = 0; 338 mutex_unlock(&spec->pcm_lock); 339 return 0; 340 } 341 eld = &per_pin->sink_eld; 342 uinfo->count = eld->eld_valid ? eld->eld_size : 0; 343 mutex_unlock(&spec->pcm_lock); 344 345 return 0; 346 } 347 348 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, 349 struct snd_ctl_elem_value *ucontrol) 350 { 351 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 352 struct hdmi_spec *spec = codec->spec; 353 struct hdmi_spec_per_pin *per_pin; 354 struct hdmi_eld *eld; 355 int pcm_idx; 356 357 pcm_idx = kcontrol->private_value; 358 mutex_lock(&spec->pcm_lock); 359 per_pin = pcm_idx_to_pin(spec, pcm_idx); 360 if (!per_pin) { 361 /* no pin is bound to the pcm */ 362 memset(ucontrol->value.bytes.data, 0, 363 ARRAY_SIZE(ucontrol->value.bytes.data)); 364 mutex_unlock(&spec->pcm_lock); 365 return 0; 366 } 367 eld = &per_pin->sink_eld; 368 369 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || 370 eld->eld_size > ELD_MAX_SIZE) { 371 mutex_unlock(&spec->pcm_lock); 372 snd_BUG(); 373 return -EINVAL; 374 } 375 376 memset(ucontrol->value.bytes.data, 0, 377 ARRAY_SIZE(ucontrol->value.bytes.data)); 378 if (eld->eld_valid) 379 memcpy(ucontrol->value.bytes.data, eld->eld_buffer, 380 eld->eld_size); 381 mutex_unlock(&spec->pcm_lock); 382 383 return 0; 384 } 385 386 static struct snd_kcontrol_new eld_bytes_ctl = { 387 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, 388 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 389 .name = "ELD", 390 .info = hdmi_eld_ctl_info, 391 .get = hdmi_eld_ctl_get, 392 }; 393 394 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, 395 int device) 396 { 397 struct snd_kcontrol *kctl; 398 struct hdmi_spec *spec = codec->spec; 399 int err; 400 401 kctl = snd_ctl_new1(&eld_bytes_ctl, codec); 402 if (!kctl) 403 return -ENOMEM; 404 kctl->private_value = pcm_idx; 405 kctl->id.device = device; 406 407 /* no pin nid is associated with the kctl now 408 * tbd: associate pin nid to eld ctl later 409 */ 410 err = snd_hda_ctl_add(codec, 0, kctl); 411 if (err < 0) 412 return err; 413 414 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; 415 return 0; 416 } 417 418 #ifdef BE_PARANOID 419 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 420 int *packet_index, int *byte_index) 421 { 422 int val; 423 424 val = snd_hda_codec_read(codec, pin_nid, 0, 425 AC_VERB_GET_HDMI_DIP_INDEX, 0); 426 427 *packet_index = val >> 5; 428 *byte_index = val & 0x1f; 429 } 430 #endif 431 432 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 433 int packet_index, int byte_index) 434 { 435 int val; 436 437 val = (packet_index << 5) | (byte_index & 0x1f); 438 439 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); 440 } 441 442 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, 443 unsigned char val) 444 { 445 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); 446 } 447 448 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) 449 { 450 struct hdmi_spec *spec = codec->spec; 451 int pin_out; 452 453 /* Unmute */ 454 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 455 snd_hda_codec_write(codec, pin_nid, 0, 456 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); 457 458 if (spec->dyn_pin_out) 459 /* Disable pin out until stream is active */ 460 pin_out = 0; 461 else 462 /* Enable pin out: some machines with GM965 gets broken output 463 * when the pin is disabled or changed while using with HDMI 464 */ 465 pin_out = PIN_OUT; 466 467 snd_hda_codec_write(codec, pin_nid, 0, 468 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); 469 } 470 471 /* 472 * ELD proc files 473 */ 474 475 #ifdef CONFIG_SND_PROC_FS 476 static void print_eld_info(struct snd_info_entry *entry, 477 struct snd_info_buffer *buffer) 478 { 479 struct hdmi_spec_per_pin *per_pin = entry->private_data; 480 481 mutex_lock(&per_pin->lock); 482 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer); 483 mutex_unlock(&per_pin->lock); 484 } 485 486 static void write_eld_info(struct snd_info_entry *entry, 487 struct snd_info_buffer *buffer) 488 { 489 struct hdmi_spec_per_pin *per_pin = entry->private_data; 490 491 mutex_lock(&per_pin->lock); 492 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); 493 mutex_unlock(&per_pin->lock); 494 } 495 496 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) 497 { 498 char name[32]; 499 struct hda_codec *codec = per_pin->codec; 500 struct snd_info_entry *entry; 501 int err; 502 503 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); 504 err = snd_card_proc_new(codec->card, name, &entry); 505 if (err < 0) 506 return err; 507 508 snd_info_set_text_ops(entry, per_pin, print_eld_info); 509 entry->c.text.write = write_eld_info; 510 entry->mode |= S_IWUSR; 511 per_pin->proc_entry = entry; 512 513 return 0; 514 } 515 516 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 517 { 518 if (!per_pin->codec->bus->shutdown) { 519 snd_info_free_entry(per_pin->proc_entry); 520 per_pin->proc_entry = NULL; 521 } 522 } 523 #else 524 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, 525 int index) 526 { 527 return 0; 528 } 529 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 530 { 531 } 532 #endif 533 534 /* 535 * Audio InfoFrame routines 536 */ 537 538 /* 539 * Enable Audio InfoFrame Transmission 540 */ 541 static void hdmi_start_infoframe_trans(struct hda_codec *codec, 542 hda_nid_t pin_nid) 543 { 544 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 545 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 546 AC_DIPXMIT_BEST); 547 } 548 549 /* 550 * Disable Audio InfoFrame Transmission 551 */ 552 static void hdmi_stop_infoframe_trans(struct hda_codec *codec, 553 hda_nid_t pin_nid) 554 { 555 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 556 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 557 AC_DIPXMIT_DISABLE); 558 } 559 560 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) 561 { 562 #ifdef CONFIG_SND_DEBUG_VERBOSE 563 int i; 564 int size; 565 566 size = snd_hdmi_get_eld_size(codec, pin_nid); 567 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); 568 569 for (i = 0; i < 8; i++) { 570 size = snd_hda_codec_read(codec, pin_nid, 0, 571 AC_VERB_GET_HDMI_DIP_SIZE, i); 572 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); 573 } 574 #endif 575 } 576 577 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) 578 { 579 #ifdef BE_PARANOID 580 int i, j; 581 int size; 582 int pi, bi; 583 for (i = 0; i < 8; i++) { 584 size = snd_hda_codec_read(codec, pin_nid, 0, 585 AC_VERB_GET_HDMI_DIP_SIZE, i); 586 if (size == 0) 587 continue; 588 589 hdmi_set_dip_index(codec, pin_nid, i, 0x0); 590 for (j = 1; j < 1000; j++) { 591 hdmi_write_dip_byte(codec, pin_nid, 0x0); 592 hdmi_get_dip_index(codec, pin_nid, &pi, &bi); 593 if (pi != i) 594 codec_dbg(codec, "dip index %d: %d != %d\n", 595 bi, pi, i); 596 if (bi == 0) /* byte index wrapped around */ 597 break; 598 } 599 codec_dbg(codec, 600 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", 601 i, size, j); 602 } 603 #endif 604 } 605 606 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) 607 { 608 u8 *bytes = (u8 *)hdmi_ai; 609 u8 sum = 0; 610 int i; 611 612 hdmi_ai->checksum = 0; 613 614 for (i = 0; i < sizeof(*hdmi_ai); i++) 615 sum += bytes[i]; 616 617 hdmi_ai->checksum = -sum; 618 } 619 620 static void hdmi_fill_audio_infoframe(struct hda_codec *codec, 621 hda_nid_t pin_nid, 622 u8 *dip, int size) 623 { 624 int i; 625 626 hdmi_debug_dip_size(codec, pin_nid); 627 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ 628 629 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 630 for (i = 0; i < size; i++) 631 hdmi_write_dip_byte(codec, pin_nid, dip[i]); 632 } 633 634 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, 635 u8 *dip, int size) 636 { 637 u8 val; 638 int i; 639 640 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) 641 != AC_DIPXMIT_BEST) 642 return false; 643 644 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 645 for (i = 0; i < size; i++) { 646 val = snd_hda_codec_read(codec, pin_nid, 0, 647 AC_VERB_GET_HDMI_DIP_DATA, 0); 648 if (val != dip[i]) 649 return false; 650 } 651 652 return true; 653 } 654 655 static void hdmi_pin_setup_infoframe(struct hda_codec *codec, 656 hda_nid_t pin_nid, 657 int ca, int active_channels, 658 int conn_type) 659 { 660 union audio_infoframe ai; 661 662 memset(&ai, 0, sizeof(ai)); 663 if (conn_type == 0) { /* HDMI */ 664 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; 665 666 hdmi_ai->type = 0x84; 667 hdmi_ai->ver = 0x01; 668 hdmi_ai->len = 0x0a; 669 hdmi_ai->CC02_CT47 = active_channels - 1; 670 hdmi_ai->CA = ca; 671 hdmi_checksum_audio_infoframe(hdmi_ai); 672 } else if (conn_type == 1) { /* DisplayPort */ 673 struct dp_audio_infoframe *dp_ai = &ai.dp; 674 675 dp_ai->type = 0x84; 676 dp_ai->len = 0x1b; 677 dp_ai->ver = 0x11 << 2; 678 dp_ai->CC02_CT47 = active_channels - 1; 679 dp_ai->CA = ca; 680 } else { 681 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n", 682 pin_nid); 683 return; 684 } 685 686 /* 687 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or 688 * sizeof(*dp_ai) to avoid partial match/update problems when 689 * the user switches between HDMI/DP monitors. 690 */ 691 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, 692 sizeof(ai))) { 693 codec_dbg(codec, 694 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n", 695 pin_nid, 696 active_channels, ca); 697 hdmi_stop_infoframe_trans(codec, pin_nid); 698 hdmi_fill_audio_infoframe(codec, pin_nid, 699 ai.bytes, sizeof(ai)); 700 hdmi_start_infoframe_trans(codec, pin_nid); 701 } 702 } 703 704 static void hdmi_setup_audio_infoframe(struct hda_codec *codec, 705 struct hdmi_spec_per_pin *per_pin, 706 bool non_pcm) 707 { 708 struct hdmi_spec *spec = codec->spec; 709 struct hdac_chmap *chmap = &spec->chmap; 710 hda_nid_t pin_nid = per_pin->pin_nid; 711 int channels = per_pin->channels; 712 int active_channels; 713 struct hdmi_eld *eld; 714 int ca; 715 716 if (!channels) 717 return; 718 719 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ 720 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 721 snd_hda_codec_write(codec, pin_nid, 0, 722 AC_VERB_SET_AMP_GAIN_MUTE, 723 AMP_OUT_UNMUTE); 724 725 eld = &per_pin->sink_eld; 726 727 ca = snd_hdac_channel_allocation(&codec->core, 728 eld->info.spk_alloc, channels, 729 per_pin->chmap_set, non_pcm, per_pin->chmap); 730 731 active_channels = snd_hdac_get_active_channels(ca); 732 733 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, 734 active_channels); 735 736 /* 737 * always configure channel mapping, it may have been changed by the 738 * user in the meantime 739 */ 740 snd_hdac_setup_channel_mapping(&spec->chmap, 741 pin_nid, non_pcm, ca, channels, 742 per_pin->chmap, per_pin->chmap_set); 743 744 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels, 745 eld->info.conn_type); 746 747 per_pin->non_pcm = non_pcm; 748 } 749 750 /* 751 * Unsolicited events 752 */ 753 754 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); 755 756 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, 757 int dev_id) 758 { 759 struct hdmi_spec *spec = codec->spec; 760 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); 761 762 if (pin_idx < 0) 763 return; 764 if (hdmi_present_sense(get_pin(spec, pin_idx), 1)) 765 snd_hda_jack_report_sync(codec); 766 } 767 768 static void jack_callback(struct hda_codec *codec, 769 struct hda_jack_callback *jack) 770 { 771 /* hda_jack don't support DP MST */ 772 check_presence_and_report(codec, jack->nid, 0); 773 } 774 775 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res) 776 { 777 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 778 struct hda_jack_tbl *jack; 779 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 780 781 /* 782 * assume DP MST uses dyn_pcm_assign and acomp and 783 * never comes here 784 * if DP MST supports unsol event, below code need 785 * consider dev_entry 786 */ 787 jack = snd_hda_jack_tbl_get_from_tag(codec, tag); 788 if (!jack) 789 return; 790 jack->jack_dirty = 1; 791 792 codec_dbg(codec, 793 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", 794 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA), 795 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); 796 797 /* hda_jack don't support DP MST */ 798 check_presence_and_report(codec, jack->nid, 0); 799 } 800 801 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) 802 { 803 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 804 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 805 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); 806 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); 807 808 codec_info(codec, 809 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", 810 codec->addr, 811 tag, 812 subtag, 813 cp_state, 814 cp_ready); 815 816 /* TODO */ 817 if (cp_state) 818 ; 819 if (cp_ready) 820 ; 821 } 822 823 824 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) 825 { 826 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 827 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 828 829 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) { 830 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); 831 return; 832 } 833 834 if (subtag == 0) 835 hdmi_intrinsic_event(codec, res); 836 else 837 hdmi_non_intrinsic_event(codec, res); 838 } 839 840 static void haswell_verify_D0(struct hda_codec *codec, 841 hda_nid_t cvt_nid, hda_nid_t nid) 842 { 843 int pwr; 844 845 /* For Haswell, the converter 1/2 may keep in D3 state after bootup, 846 * thus pins could only choose converter 0 for use. Make sure the 847 * converters are in correct power state */ 848 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) 849 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); 850 851 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { 852 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, 853 AC_PWRST_D0); 854 msleep(40); 855 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); 856 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; 857 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr); 858 } 859 } 860 861 /* 862 * Callbacks 863 */ 864 865 /* HBR should be Non-PCM, 8 channels */ 866 #define is_hbr_format(format) \ 867 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) 868 869 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 870 bool hbr) 871 { 872 int pinctl, new_pinctl; 873 874 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { 875 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 876 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 877 878 if (pinctl < 0) 879 return hbr ? -EINVAL : 0; 880 881 new_pinctl = pinctl & ~AC_PINCTL_EPT; 882 if (hbr) 883 new_pinctl |= AC_PINCTL_EPT_HBR; 884 else 885 new_pinctl |= AC_PINCTL_EPT_NATIVE; 886 887 codec_dbg(codec, 888 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", 889 pin_nid, 890 pinctl == new_pinctl ? "" : "new-", 891 new_pinctl); 892 893 if (pinctl != new_pinctl) 894 snd_hda_codec_write(codec, pin_nid, 0, 895 AC_VERB_SET_PIN_WIDGET_CONTROL, 896 new_pinctl); 897 } else if (hbr) 898 return -EINVAL; 899 900 return 0; 901 } 902 903 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 904 hda_nid_t pin_nid, u32 stream_tag, int format) 905 { 906 struct hdmi_spec *spec = codec->spec; 907 int err; 908 909 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format)); 910 911 if (err) { 912 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); 913 return err; 914 } 915 916 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); 917 return 0; 918 } 919 920 /* Try to find an available converter 921 * If pin_idx is less then zero, just try to find an available converter. 922 * Otherwise, try to find an available converter and get the cvt mux index 923 * of the pin. 924 */ 925 static int hdmi_choose_cvt(struct hda_codec *codec, 926 int pin_idx, int *cvt_id) 927 { 928 struct hdmi_spec *spec = codec->spec; 929 struct hdmi_spec_per_pin *per_pin; 930 struct hdmi_spec_per_cvt *per_cvt = NULL; 931 int cvt_idx, mux_idx = 0; 932 933 /* pin_idx < 0 means no pin will be bound to the converter */ 934 if (pin_idx < 0) 935 per_pin = NULL; 936 else 937 per_pin = get_pin(spec, pin_idx); 938 939 /* Dynamically assign converter to stream */ 940 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 941 per_cvt = get_cvt(spec, cvt_idx); 942 943 /* Must not already be assigned */ 944 if (per_cvt->assigned) 945 continue; 946 if (per_pin == NULL) 947 break; 948 /* Must be in pin's mux's list of converters */ 949 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 950 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) 951 break; 952 /* Not in mux list */ 953 if (mux_idx == per_pin->num_mux_nids) 954 continue; 955 break; 956 } 957 958 /* No free converters */ 959 if (cvt_idx == spec->num_cvts) 960 return -EBUSY; 961 962 if (per_pin != NULL) 963 per_pin->mux_idx = mux_idx; 964 965 if (cvt_id) 966 *cvt_id = cvt_idx; 967 968 return 0; 969 } 970 971 /* Assure the pin select the right convetor */ 972 static void intel_verify_pin_cvt_connect(struct hda_codec *codec, 973 struct hdmi_spec_per_pin *per_pin) 974 { 975 hda_nid_t pin_nid = per_pin->pin_nid; 976 int mux_idx, curr; 977 978 mux_idx = per_pin->mux_idx; 979 curr = snd_hda_codec_read(codec, pin_nid, 0, 980 AC_VERB_GET_CONNECT_SEL, 0); 981 if (curr != mux_idx) 982 snd_hda_codec_write_cache(codec, pin_nid, 0, 983 AC_VERB_SET_CONNECT_SEL, 984 mux_idx); 985 } 986 987 /* get the mux index for the converter of the pins 988 * converter's mux index is the same for all pins on Intel platform 989 */ 990 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, 991 hda_nid_t cvt_nid) 992 { 993 int i; 994 995 for (i = 0; i < spec->num_cvts; i++) 996 if (spec->cvt_nids[i] == cvt_nid) 997 return i; 998 return -EINVAL; 999 } 1000 1001 /* Intel HDMI workaround to fix audio routing issue: 1002 * For some Intel display codecs, pins share the same connection list. 1003 * So a conveter can be selected by multiple pins and playback on any of these 1004 * pins will generate sound on the external display, because audio flows from 1005 * the same converter to the display pipeline. Also muting one pin may make 1006 * other pins have no sound output. 1007 * So this function assures that an assigned converter for a pin is not selected 1008 * by any other pins. 1009 */ 1010 static void intel_not_share_assigned_cvt(struct hda_codec *codec, 1011 hda_nid_t pin_nid, 1012 int dev_id, int mux_idx) 1013 { 1014 struct hdmi_spec *spec = codec->spec; 1015 hda_nid_t nid; 1016 int cvt_idx, curr; 1017 struct hdmi_spec_per_cvt *per_cvt; 1018 struct hdmi_spec_per_pin *per_pin; 1019 int pin_idx; 1020 1021 /* configure the pins connections */ 1022 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 1023 int dev_id_saved; 1024 int dev_num; 1025 1026 per_pin = get_pin(spec, pin_idx); 1027 /* 1028 * pin not connected to monitor 1029 * no need to operate on it 1030 */ 1031 if (!per_pin->pcm) 1032 continue; 1033 1034 if ((per_pin->pin_nid == pin_nid) && 1035 (per_pin->dev_id == dev_id)) 1036 continue; 1037 1038 /* 1039 * if per_pin->dev_id >= dev_num, 1040 * snd_hda_get_dev_select() will fail, 1041 * and the following operation is unpredictable. 1042 * So skip this situation. 1043 */ 1044 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; 1045 if (per_pin->dev_id >= dev_num) 1046 continue; 1047 1048 nid = per_pin->pin_nid; 1049 1050 /* 1051 * Calling this function should not impact 1052 * on the device entry selection 1053 * So let's save the dev id for each pin, 1054 * and restore it when return 1055 */ 1056 dev_id_saved = snd_hda_get_dev_select(codec, nid); 1057 snd_hda_set_dev_select(codec, nid, per_pin->dev_id); 1058 curr = snd_hda_codec_read(codec, nid, 0, 1059 AC_VERB_GET_CONNECT_SEL, 0); 1060 if (curr != mux_idx) { 1061 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1062 continue; 1063 } 1064 1065 1066 /* choose an unassigned converter. The conveters in the 1067 * connection list are in the same order as in the codec. 1068 */ 1069 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1070 per_cvt = get_cvt(spec, cvt_idx); 1071 if (!per_cvt->assigned) { 1072 codec_dbg(codec, 1073 "choose cvt %d for pin nid %d\n", 1074 cvt_idx, nid); 1075 snd_hda_codec_write_cache(codec, nid, 0, 1076 AC_VERB_SET_CONNECT_SEL, 1077 cvt_idx); 1078 break; 1079 } 1080 } 1081 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1082 } 1083 } 1084 1085 /* A wrapper of intel_not_share_asigned_cvt() */ 1086 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, 1087 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) 1088 { 1089 int mux_idx; 1090 struct hdmi_spec *spec = codec->spec; 1091 1092 /* On Intel platform, the mapping of converter nid to 1093 * mux index of the pins are always the same. 1094 * The pin nid may be 0, this means all pins will not 1095 * share the converter. 1096 */ 1097 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); 1098 if (mux_idx >= 0) 1099 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); 1100 } 1101 1102 /* skeleton caller of pin_cvt_fixup ops */ 1103 static void pin_cvt_fixup(struct hda_codec *codec, 1104 struct hdmi_spec_per_pin *per_pin, 1105 hda_nid_t cvt_nid) 1106 { 1107 struct hdmi_spec *spec = codec->spec; 1108 1109 if (spec->ops.pin_cvt_fixup) 1110 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); 1111 } 1112 1113 /* called in hdmi_pcm_open when no pin is assigned to the PCM 1114 * in dyn_pcm_assign mode. 1115 */ 1116 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, 1117 struct hda_codec *codec, 1118 struct snd_pcm_substream *substream) 1119 { 1120 struct hdmi_spec *spec = codec->spec; 1121 struct snd_pcm_runtime *runtime = substream->runtime; 1122 int cvt_idx, pcm_idx; 1123 struct hdmi_spec_per_cvt *per_cvt = NULL; 1124 int err; 1125 1126 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1127 if (pcm_idx < 0) 1128 return -EINVAL; 1129 1130 err = hdmi_choose_cvt(codec, -1, &cvt_idx); 1131 if (err) 1132 return err; 1133 1134 per_cvt = get_cvt(spec, cvt_idx); 1135 per_cvt->assigned = 1; 1136 hinfo->nid = per_cvt->cvt_nid; 1137 1138 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); 1139 1140 set_bit(pcm_idx, &spec->pcm_in_use); 1141 /* todo: setup spdif ctls assign */ 1142 1143 /* Initially set the converter's capabilities */ 1144 hinfo->channels_min = per_cvt->channels_min; 1145 hinfo->channels_max = per_cvt->channels_max; 1146 hinfo->rates = per_cvt->rates; 1147 hinfo->formats = per_cvt->formats; 1148 hinfo->maxbps = per_cvt->maxbps; 1149 1150 /* Store the updated parameters */ 1151 runtime->hw.channels_min = hinfo->channels_min; 1152 runtime->hw.channels_max = hinfo->channels_max; 1153 runtime->hw.formats = hinfo->formats; 1154 runtime->hw.rates = hinfo->rates; 1155 1156 snd_pcm_hw_constraint_step(substream->runtime, 0, 1157 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1158 return 0; 1159 } 1160 1161 /* 1162 * HDA PCM callbacks 1163 */ 1164 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, 1165 struct hda_codec *codec, 1166 struct snd_pcm_substream *substream) 1167 { 1168 struct hdmi_spec *spec = codec->spec; 1169 struct snd_pcm_runtime *runtime = substream->runtime; 1170 int pin_idx, cvt_idx, pcm_idx; 1171 struct hdmi_spec_per_pin *per_pin; 1172 struct hdmi_eld *eld; 1173 struct hdmi_spec_per_cvt *per_cvt = NULL; 1174 int err; 1175 1176 /* Validate hinfo */ 1177 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1178 if (pcm_idx < 0) 1179 return -EINVAL; 1180 1181 mutex_lock(&spec->pcm_lock); 1182 pin_idx = hinfo_to_pin_index(codec, hinfo); 1183 if (!spec->dyn_pcm_assign) { 1184 if (snd_BUG_ON(pin_idx < 0)) { 1185 mutex_unlock(&spec->pcm_lock); 1186 return -EINVAL; 1187 } 1188 } else { 1189 /* no pin is assigned to the PCM 1190 * PA need pcm open successfully when probe 1191 */ 1192 if (pin_idx < 0) { 1193 err = hdmi_pcm_open_no_pin(hinfo, codec, substream); 1194 mutex_unlock(&spec->pcm_lock); 1195 return err; 1196 } 1197 } 1198 1199 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx); 1200 if (err < 0) { 1201 mutex_unlock(&spec->pcm_lock); 1202 return err; 1203 } 1204 1205 per_cvt = get_cvt(spec, cvt_idx); 1206 /* Claim converter */ 1207 per_cvt->assigned = 1; 1208 1209 set_bit(pcm_idx, &spec->pcm_in_use); 1210 per_pin = get_pin(spec, pin_idx); 1211 per_pin->cvt_nid = per_cvt->cvt_nid; 1212 hinfo->nid = per_cvt->cvt_nid; 1213 1214 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1215 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1216 AC_VERB_SET_CONNECT_SEL, 1217 per_pin->mux_idx); 1218 1219 /* configure unused pins to choose other converters */ 1220 pin_cvt_fixup(codec, per_pin, 0); 1221 1222 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); 1223 1224 /* Initially set the converter's capabilities */ 1225 hinfo->channels_min = per_cvt->channels_min; 1226 hinfo->channels_max = per_cvt->channels_max; 1227 hinfo->rates = per_cvt->rates; 1228 hinfo->formats = per_cvt->formats; 1229 hinfo->maxbps = per_cvt->maxbps; 1230 1231 eld = &per_pin->sink_eld; 1232 /* Restrict capabilities by ELD if this isn't disabled */ 1233 if (!static_hdmi_pcm && eld->eld_valid) { 1234 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); 1235 if (hinfo->channels_min > hinfo->channels_max || 1236 !hinfo->rates || !hinfo->formats) { 1237 per_cvt->assigned = 0; 1238 hinfo->nid = 0; 1239 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1240 mutex_unlock(&spec->pcm_lock); 1241 return -ENODEV; 1242 } 1243 } 1244 1245 mutex_unlock(&spec->pcm_lock); 1246 /* Store the updated parameters */ 1247 runtime->hw.channels_min = hinfo->channels_min; 1248 runtime->hw.channels_max = hinfo->channels_max; 1249 runtime->hw.formats = hinfo->formats; 1250 runtime->hw.rates = hinfo->rates; 1251 1252 snd_pcm_hw_constraint_step(substream->runtime, 0, 1253 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1254 return 0; 1255 } 1256 1257 /* 1258 * HDA/HDMI auto parsing 1259 */ 1260 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) 1261 { 1262 struct hdmi_spec *spec = codec->spec; 1263 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1264 hda_nid_t pin_nid = per_pin->pin_nid; 1265 1266 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { 1267 codec_warn(codec, 1268 "HDMI: pin %d wcaps %#x does not support connection list\n", 1269 pin_nid, get_wcaps(codec, pin_nid)); 1270 return -EINVAL; 1271 } 1272 1273 /* all the device entries on the same pin have the same conn list */ 1274 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid, 1275 per_pin->mux_nids, 1276 HDA_MAX_CONNECTIONS); 1277 1278 return 0; 1279 } 1280 1281 static int hdmi_find_pcm_slot(struct hdmi_spec *spec, 1282 struct hdmi_spec_per_pin *per_pin) 1283 { 1284 int i; 1285 1286 /* try the prefer PCM */ 1287 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap)) 1288 return per_pin->pin_nid_idx; 1289 1290 /* have a second try; check the "reserved area" over num_pins */ 1291 for (i = spec->num_nids; i < spec->pcm_used; i++) { 1292 if (!test_bit(i, &spec->pcm_bitmap)) 1293 return i; 1294 } 1295 1296 /* the last try; check the empty slots in pins */ 1297 for (i = 0; i < spec->num_nids; i++) { 1298 if (!test_bit(i, &spec->pcm_bitmap)) 1299 return i; 1300 } 1301 return -EBUSY; 1302 } 1303 1304 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, 1305 struct hdmi_spec_per_pin *per_pin) 1306 { 1307 int idx; 1308 1309 /* pcm already be attached to the pin */ 1310 if (per_pin->pcm) 1311 return; 1312 idx = hdmi_find_pcm_slot(spec, per_pin); 1313 if (idx == -EBUSY) 1314 return; 1315 per_pin->pcm_idx = idx; 1316 per_pin->pcm = get_hdmi_pcm(spec, idx); 1317 set_bit(idx, &spec->pcm_bitmap); 1318 } 1319 1320 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, 1321 struct hdmi_spec_per_pin *per_pin) 1322 { 1323 int idx; 1324 1325 /* pcm already be detached from the pin */ 1326 if (!per_pin->pcm) 1327 return; 1328 idx = per_pin->pcm_idx; 1329 per_pin->pcm_idx = -1; 1330 per_pin->pcm = NULL; 1331 if (idx >= 0 && idx < spec->pcm_used) 1332 clear_bit(idx, &spec->pcm_bitmap); 1333 } 1334 1335 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, 1336 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) 1337 { 1338 int mux_idx; 1339 1340 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1341 if (per_pin->mux_nids[mux_idx] == cvt_nid) 1342 break; 1343 return mux_idx; 1344 } 1345 1346 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); 1347 1348 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, 1349 struct hdmi_spec_per_pin *per_pin) 1350 { 1351 struct hda_codec *codec = per_pin->codec; 1352 struct hda_pcm *pcm; 1353 struct hda_pcm_stream *hinfo; 1354 struct snd_pcm_substream *substream; 1355 int mux_idx; 1356 bool non_pcm; 1357 1358 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1359 pcm = get_pcm_rec(spec, per_pin->pcm_idx); 1360 else 1361 return; 1362 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) 1363 return; 1364 1365 /* hdmi audio only uses playback and one substream */ 1366 hinfo = pcm->stream; 1367 substream = pcm->pcm->streams[0].substream; 1368 1369 per_pin->cvt_nid = hinfo->nid; 1370 1371 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); 1372 if (mux_idx < per_pin->num_mux_nids) { 1373 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1374 per_pin->dev_id); 1375 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1376 AC_VERB_SET_CONNECT_SEL, 1377 mux_idx); 1378 } 1379 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); 1380 1381 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); 1382 if (substream->runtime) 1383 per_pin->channels = substream->runtime->channels; 1384 per_pin->setup = true; 1385 per_pin->mux_idx = mux_idx; 1386 1387 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1388 } 1389 1390 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, 1391 struct hdmi_spec_per_pin *per_pin) 1392 { 1393 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1394 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); 1395 1396 per_pin->chmap_set = false; 1397 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1398 1399 per_pin->setup = false; 1400 per_pin->channels = 0; 1401 } 1402 1403 /* update per_pin ELD from the given new ELD; 1404 * setup info frame and notification accordingly 1405 */ 1406 static void update_eld(struct hda_codec *codec, 1407 struct hdmi_spec_per_pin *per_pin, 1408 struct hdmi_eld *eld) 1409 { 1410 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 1411 struct hdmi_spec *spec = codec->spec; 1412 bool old_eld_valid = pin_eld->eld_valid; 1413 bool eld_changed; 1414 int pcm_idx = -1; 1415 1416 /* for monitor disconnection, save pcm_idx firstly */ 1417 pcm_idx = per_pin->pcm_idx; 1418 if (spec->dyn_pcm_assign) { 1419 if (eld->eld_valid) { 1420 hdmi_attach_hda_pcm(spec, per_pin); 1421 hdmi_pcm_setup_pin(spec, per_pin); 1422 } else { 1423 hdmi_pcm_reset_pin(spec, per_pin); 1424 hdmi_detach_hda_pcm(spec, per_pin); 1425 } 1426 } 1427 /* if pcm_idx == -1, it means this is in monitor connection event 1428 * we can get the correct pcm_idx now. 1429 */ 1430 if (pcm_idx == -1) 1431 pcm_idx = per_pin->pcm_idx; 1432 1433 if (eld->eld_valid) 1434 snd_hdmi_show_eld(codec, &eld->info); 1435 1436 eld_changed = (pin_eld->eld_valid != eld->eld_valid); 1437 if (eld->eld_valid && pin_eld->eld_valid) 1438 if (pin_eld->eld_size != eld->eld_size || 1439 memcmp(pin_eld->eld_buffer, eld->eld_buffer, 1440 eld->eld_size) != 0) 1441 eld_changed = true; 1442 1443 pin_eld->monitor_present = eld->monitor_present; 1444 pin_eld->eld_valid = eld->eld_valid; 1445 pin_eld->eld_size = eld->eld_size; 1446 if (eld->eld_valid) 1447 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size); 1448 pin_eld->info = eld->info; 1449 1450 /* 1451 * Re-setup pin and infoframe. This is needed e.g. when 1452 * - sink is first plugged-in 1453 * - transcoder can change during stream playback on Haswell 1454 * and this can make HW reset converter selection on a pin. 1455 */ 1456 if (eld->eld_valid && !old_eld_valid && per_pin->setup) { 1457 pin_cvt_fixup(codec, per_pin, 0); 1458 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1459 } 1460 1461 if (eld_changed && pcm_idx >= 0) 1462 snd_ctl_notify(codec->card, 1463 SNDRV_CTL_EVENT_MASK_VALUE | 1464 SNDRV_CTL_EVENT_MASK_INFO, 1465 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); 1466 } 1467 1468 /* update ELD and jack state via HD-audio verbs */ 1469 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, 1470 int repoll) 1471 { 1472 struct hda_jack_tbl *jack; 1473 struct hda_codec *codec = per_pin->codec; 1474 struct hdmi_spec *spec = codec->spec; 1475 struct hdmi_eld *eld = &spec->temp_eld; 1476 hda_nid_t pin_nid = per_pin->pin_nid; 1477 /* 1478 * Always execute a GetPinSense verb here, even when called from 1479 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited 1480 * response's PD bit is not the real PD value, but indicates that 1481 * the real PD value changed. An older version of the HD-audio 1482 * specification worked this way. Hence, we just ignore the data in 1483 * the unsolicited response to avoid custom WARs. 1484 */ 1485 int present; 1486 bool ret; 1487 bool do_repoll = false; 1488 1489 present = snd_hda_pin_sense(codec, pin_nid); 1490 1491 mutex_lock(&per_pin->lock); 1492 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); 1493 if (eld->monitor_present) 1494 eld->eld_valid = !!(present & AC_PINSENSE_ELDV); 1495 else 1496 eld->eld_valid = false; 1497 1498 codec_dbg(codec, 1499 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n", 1500 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); 1501 1502 if (eld->eld_valid) { 1503 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer, 1504 &eld->eld_size) < 0) 1505 eld->eld_valid = false; 1506 else { 1507 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, 1508 eld->eld_size) < 0) 1509 eld->eld_valid = false; 1510 } 1511 if (!eld->eld_valid && repoll) 1512 do_repoll = true; 1513 } 1514 1515 if (do_repoll) 1516 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300)); 1517 else 1518 update_eld(codec, per_pin, eld); 1519 1520 ret = !repoll || !eld->monitor_present || eld->eld_valid; 1521 1522 jack = snd_hda_jack_tbl_get(codec, pin_nid); 1523 if (jack) 1524 jack->block_report = !ret; 1525 1526 mutex_unlock(&per_pin->lock); 1527 return ret; 1528 } 1529 1530 static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec, 1531 struct hdmi_spec_per_pin *per_pin) 1532 { 1533 struct hdmi_spec *spec = codec->spec; 1534 struct snd_jack *jack = NULL; 1535 struct hda_jack_tbl *jack_tbl; 1536 1537 /* if !dyn_pcm_assign, get jack from hda_jack_tbl 1538 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not 1539 * NULL even after snd_hda_jack_tbl_clear() is called to 1540 * free snd_jack. This may cause access invalid memory 1541 * when calling snd_jack_report 1542 */ 1543 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign) 1544 jack = spec->pcm_rec[per_pin->pcm_idx].jack; 1545 else if (!spec->dyn_pcm_assign) { 1546 /* 1547 * jack tbl doesn't support DP MST 1548 * DP MST will use dyn_pcm_assign, 1549 * so DP MST will never come here 1550 */ 1551 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid); 1552 if (jack_tbl) 1553 jack = jack_tbl->jack; 1554 } 1555 return jack; 1556 } 1557 1558 /* update ELD and jack state via audio component */ 1559 static void sync_eld_via_acomp(struct hda_codec *codec, 1560 struct hdmi_spec_per_pin *per_pin) 1561 { 1562 struct hdmi_spec *spec = codec->spec; 1563 struct hdmi_eld *eld = &spec->temp_eld; 1564 struct snd_jack *jack = NULL; 1565 int size; 1566 1567 mutex_lock(&per_pin->lock); 1568 eld->monitor_present = false; 1569 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, 1570 per_pin->dev_id, &eld->monitor_present, 1571 eld->eld_buffer, ELD_MAX_SIZE); 1572 if (size > 0) { 1573 size = min(size, ELD_MAX_SIZE); 1574 if (snd_hdmi_parse_eld(codec, &eld->info, 1575 eld->eld_buffer, size) < 0) 1576 size = -EINVAL; 1577 } 1578 1579 if (size > 0) { 1580 eld->eld_valid = true; 1581 eld->eld_size = size; 1582 } else { 1583 eld->eld_valid = false; 1584 eld->eld_size = 0; 1585 } 1586 1587 /* pcm_idx >=0 before update_eld() means it is in monitor 1588 * disconnected event. Jack must be fetched before update_eld() 1589 */ 1590 jack = pin_idx_to_jack(codec, per_pin); 1591 update_eld(codec, per_pin, eld); 1592 if (jack == NULL) 1593 jack = pin_idx_to_jack(codec, per_pin); 1594 if (jack == NULL) 1595 goto unlock; 1596 snd_jack_report(jack, 1597 eld->monitor_present ? SND_JACK_AVOUT : 0); 1598 unlock: 1599 mutex_unlock(&per_pin->lock); 1600 } 1601 1602 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) 1603 { 1604 struct hda_codec *codec = per_pin->codec; 1605 struct hdmi_spec *spec = codec->spec; 1606 int ret; 1607 1608 /* no temporary power up/down needed for component notifier */ 1609 if (!codec_has_acomp(codec)) 1610 snd_hda_power_up_pm(codec); 1611 1612 mutex_lock(&spec->pcm_lock); 1613 if (codec_has_acomp(codec)) { 1614 sync_eld_via_acomp(codec, per_pin); 1615 ret = false; /* don't call snd_hda_jack_report_sync() */ 1616 } else { 1617 ret = hdmi_present_sense_via_verbs(per_pin, repoll); 1618 } 1619 mutex_unlock(&spec->pcm_lock); 1620 1621 if (!codec_has_acomp(codec)) 1622 snd_hda_power_down_pm(codec); 1623 1624 return ret; 1625 } 1626 1627 static void hdmi_repoll_eld(struct work_struct *work) 1628 { 1629 struct hdmi_spec_per_pin *per_pin = 1630 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); 1631 1632 if (per_pin->repoll_count++ > 6) 1633 per_pin->repoll_count = 0; 1634 1635 if (hdmi_present_sense(per_pin, per_pin->repoll_count)) 1636 snd_hda_jack_report_sync(per_pin->codec); 1637 } 1638 1639 static void intel_haswell_fixup_connect_list(struct hda_codec *codec, 1640 hda_nid_t nid); 1641 1642 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) 1643 { 1644 struct hdmi_spec *spec = codec->spec; 1645 unsigned int caps, config; 1646 int pin_idx; 1647 struct hdmi_spec_per_pin *per_pin; 1648 int err; 1649 int dev_num, i; 1650 1651 caps = snd_hda_query_pin_caps(codec, pin_nid); 1652 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) 1653 return 0; 1654 1655 /* 1656 * For DP MST audio, Configuration Default is the same for 1657 * all device entries on the same pin 1658 */ 1659 config = snd_hda_codec_get_pincfg(codec, pin_nid); 1660 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE) 1661 return 0; 1662 1663 /* 1664 * To simplify the implementation, malloc all 1665 * the virtual pins in the initialization statically 1666 */ 1667 if (is_haswell_plus(codec)) { 1668 /* 1669 * On Intel platforms, device entries number is 1670 * changed dynamically. If there is a DP MST 1671 * hub connected, the device entries number is 3. 1672 * Otherwise, it is 1. 1673 * Here we manually set dev_num to 3, so that 1674 * we can initialize all the device entries when 1675 * bootup statically. 1676 */ 1677 dev_num = 3; 1678 spec->dev_num = 3; 1679 } else if (spec->dyn_pcm_assign && codec->dp_mst) { 1680 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; 1681 /* 1682 * spec->dev_num is the maxinum number of device entries 1683 * among all the pins 1684 */ 1685 spec->dev_num = (spec->dev_num > dev_num) ? 1686 spec->dev_num : dev_num; 1687 } else { 1688 /* 1689 * If the platform doesn't support DP MST, 1690 * manually set dev_num to 1. This means 1691 * the pin has only one device entry. 1692 */ 1693 dev_num = 1; 1694 spec->dev_num = 1; 1695 } 1696 1697 for (i = 0; i < dev_num; i++) { 1698 pin_idx = spec->num_pins; 1699 per_pin = snd_array_new(&spec->pins); 1700 1701 if (!per_pin) 1702 return -ENOMEM; 1703 1704 if (spec->dyn_pcm_assign) { 1705 per_pin->pcm = NULL; 1706 per_pin->pcm_idx = -1; 1707 } else { 1708 per_pin->pcm = get_hdmi_pcm(spec, pin_idx); 1709 per_pin->pcm_idx = pin_idx; 1710 } 1711 per_pin->pin_nid = pin_nid; 1712 per_pin->pin_nid_idx = spec->num_nids; 1713 per_pin->dev_id = i; 1714 per_pin->non_pcm = false; 1715 snd_hda_set_dev_select(codec, pin_nid, i); 1716 if (is_haswell_plus(codec)) 1717 intel_haswell_fixup_connect_list(codec, pin_nid); 1718 err = hdmi_read_pin_conn(codec, pin_idx); 1719 if (err < 0) 1720 return err; 1721 spec->num_pins++; 1722 } 1723 spec->num_nids++; 1724 1725 return 0; 1726 } 1727 1728 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1729 { 1730 struct hdmi_spec *spec = codec->spec; 1731 struct hdmi_spec_per_cvt *per_cvt; 1732 unsigned int chans; 1733 int err; 1734 1735 chans = get_wcaps(codec, cvt_nid); 1736 chans = get_wcaps_channels(chans); 1737 1738 per_cvt = snd_array_new(&spec->cvts); 1739 if (!per_cvt) 1740 return -ENOMEM; 1741 1742 per_cvt->cvt_nid = cvt_nid; 1743 per_cvt->channels_min = 2; 1744 if (chans <= 16) { 1745 per_cvt->channels_max = chans; 1746 if (chans > spec->chmap.channels_max) 1747 spec->chmap.channels_max = chans; 1748 } 1749 1750 err = snd_hda_query_supported_pcm(codec, cvt_nid, 1751 &per_cvt->rates, 1752 &per_cvt->formats, 1753 &per_cvt->maxbps); 1754 if (err < 0) 1755 return err; 1756 1757 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) 1758 spec->cvt_nids[spec->num_cvts] = cvt_nid; 1759 spec->num_cvts++; 1760 1761 return 0; 1762 } 1763 1764 static int hdmi_parse_codec(struct hda_codec *codec) 1765 { 1766 hda_nid_t nid; 1767 int i, nodes; 1768 1769 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid); 1770 if (!nid || nodes < 0) { 1771 codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); 1772 return -EINVAL; 1773 } 1774 1775 for (i = 0; i < nodes; i++, nid++) { 1776 unsigned int caps; 1777 unsigned int type; 1778 1779 caps = get_wcaps(codec, nid); 1780 type = get_wcaps_type(caps); 1781 1782 if (!(caps & AC_WCAP_DIGITAL)) 1783 continue; 1784 1785 switch (type) { 1786 case AC_WID_AUD_OUT: 1787 hdmi_add_cvt(codec, nid); 1788 break; 1789 case AC_WID_PIN: 1790 hdmi_add_pin(codec, nid); 1791 break; 1792 } 1793 } 1794 1795 return 0; 1796 } 1797 1798 /* 1799 */ 1800 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1801 { 1802 struct hda_spdif_out *spdif; 1803 bool non_pcm; 1804 1805 mutex_lock(&codec->spdif_mutex); 1806 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); 1807 /* Add sanity check to pass klockwork check. 1808 * This should never happen. 1809 */ 1810 if (WARN_ON(spdif == NULL)) 1811 return true; 1812 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); 1813 mutex_unlock(&codec->spdif_mutex); 1814 return non_pcm; 1815 } 1816 1817 /* 1818 * HDMI callbacks 1819 */ 1820 1821 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 1822 struct hda_codec *codec, 1823 unsigned int stream_tag, 1824 unsigned int format, 1825 struct snd_pcm_substream *substream) 1826 { 1827 hda_nid_t cvt_nid = hinfo->nid; 1828 struct hdmi_spec *spec = codec->spec; 1829 int pin_idx; 1830 struct hdmi_spec_per_pin *per_pin; 1831 hda_nid_t pin_nid; 1832 struct snd_pcm_runtime *runtime = substream->runtime; 1833 bool non_pcm; 1834 int pinctl; 1835 int err; 1836 1837 mutex_lock(&spec->pcm_lock); 1838 pin_idx = hinfo_to_pin_index(codec, hinfo); 1839 if (spec->dyn_pcm_assign && pin_idx < 0) { 1840 /* when dyn_pcm_assign and pcm is not bound to a pin 1841 * skip pin setup and return 0 to make audio playback 1842 * be ongoing 1843 */ 1844 pin_cvt_fixup(codec, NULL, cvt_nid); 1845 snd_hda_codec_setup_stream(codec, cvt_nid, 1846 stream_tag, 0, format); 1847 mutex_unlock(&spec->pcm_lock); 1848 return 0; 1849 } 1850 1851 if (snd_BUG_ON(pin_idx < 0)) { 1852 mutex_unlock(&spec->pcm_lock); 1853 return -EINVAL; 1854 } 1855 per_pin = get_pin(spec, pin_idx); 1856 pin_nid = per_pin->pin_nid; 1857 1858 /* Verify pin:cvt selections to avoid silent audio after S3. 1859 * After S3, the audio driver restores pin:cvt selections 1860 * but this can happen before gfx is ready and such selection 1861 * is overlooked by HW. Thus multiple pins can share a same 1862 * default convertor and mute control will affect each other, 1863 * which can cause a resumed audio playback become silent 1864 * after S3. 1865 */ 1866 pin_cvt_fixup(codec, per_pin, 0); 1867 1868 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ 1869 /* Todo: add DP1.2 MST audio support later */ 1870 if (codec_has_acomp(codec)) 1871 snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id, 1872 runtime->rate); 1873 1874 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); 1875 mutex_lock(&per_pin->lock); 1876 per_pin->channels = substream->runtime->channels; 1877 per_pin->setup = true; 1878 1879 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1880 mutex_unlock(&per_pin->lock); 1881 if (spec->dyn_pin_out) { 1882 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 1883 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 1884 snd_hda_codec_write(codec, pin_nid, 0, 1885 AC_VERB_SET_PIN_WIDGET_CONTROL, 1886 pinctl | PIN_OUT); 1887 } 1888 1889 /* snd_hda_set_dev_select() has been called before */ 1890 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid, 1891 stream_tag, format); 1892 mutex_unlock(&spec->pcm_lock); 1893 return err; 1894 } 1895 1896 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 1897 struct hda_codec *codec, 1898 struct snd_pcm_substream *substream) 1899 { 1900 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 1901 return 0; 1902 } 1903 1904 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, 1905 struct hda_codec *codec, 1906 struct snd_pcm_substream *substream) 1907 { 1908 struct hdmi_spec *spec = codec->spec; 1909 int cvt_idx, pin_idx, pcm_idx; 1910 struct hdmi_spec_per_cvt *per_cvt; 1911 struct hdmi_spec_per_pin *per_pin; 1912 int pinctl; 1913 1914 if (hinfo->nid) { 1915 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1916 if (snd_BUG_ON(pcm_idx < 0)) 1917 return -EINVAL; 1918 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); 1919 if (snd_BUG_ON(cvt_idx < 0)) 1920 return -EINVAL; 1921 per_cvt = get_cvt(spec, cvt_idx); 1922 1923 snd_BUG_ON(!per_cvt->assigned); 1924 per_cvt->assigned = 0; 1925 hinfo->nid = 0; 1926 1927 mutex_lock(&spec->pcm_lock); 1928 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1929 clear_bit(pcm_idx, &spec->pcm_in_use); 1930 pin_idx = hinfo_to_pin_index(codec, hinfo); 1931 if (spec->dyn_pcm_assign && pin_idx < 0) { 1932 mutex_unlock(&spec->pcm_lock); 1933 return 0; 1934 } 1935 1936 if (snd_BUG_ON(pin_idx < 0)) { 1937 mutex_unlock(&spec->pcm_lock); 1938 return -EINVAL; 1939 } 1940 per_pin = get_pin(spec, pin_idx); 1941 1942 if (spec->dyn_pin_out) { 1943 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 1944 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 1945 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 1946 AC_VERB_SET_PIN_WIDGET_CONTROL, 1947 pinctl & ~PIN_OUT); 1948 } 1949 1950 mutex_lock(&per_pin->lock); 1951 per_pin->chmap_set = false; 1952 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1953 1954 per_pin->setup = false; 1955 per_pin->channels = 0; 1956 mutex_unlock(&per_pin->lock); 1957 mutex_unlock(&spec->pcm_lock); 1958 } 1959 1960 return 0; 1961 } 1962 1963 static const struct hda_pcm_ops generic_ops = { 1964 .open = hdmi_pcm_open, 1965 .close = hdmi_pcm_close, 1966 .prepare = generic_hdmi_playback_pcm_prepare, 1967 .cleanup = generic_hdmi_playback_pcm_cleanup, 1968 }; 1969 1970 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) 1971 { 1972 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 1973 struct hdmi_spec *spec = codec->spec; 1974 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 1975 1976 if (!per_pin) 1977 return 0; 1978 1979 return per_pin->sink_eld.info.spk_alloc; 1980 } 1981 1982 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, 1983 unsigned char *chmap) 1984 { 1985 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 1986 struct hdmi_spec *spec = codec->spec; 1987 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 1988 1989 /* chmap is already set to 0 in caller */ 1990 if (!per_pin) 1991 return; 1992 1993 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); 1994 } 1995 1996 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, 1997 unsigned char *chmap, int prepared) 1998 { 1999 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2000 struct hdmi_spec *spec = codec->spec; 2001 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2002 2003 if (!per_pin) 2004 return; 2005 mutex_lock(&per_pin->lock); 2006 per_pin->chmap_set = true; 2007 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); 2008 if (prepared) 2009 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 2010 mutex_unlock(&per_pin->lock); 2011 } 2012 2013 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) 2014 { 2015 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2016 struct hdmi_spec *spec = codec->spec; 2017 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2018 2019 return per_pin ? true:false; 2020 } 2021 2022 static int generic_hdmi_build_pcms(struct hda_codec *codec) 2023 { 2024 struct hdmi_spec *spec = codec->spec; 2025 int idx; 2026 2027 /* 2028 * for non-mst mode, pcm number is the same as before 2029 * for DP MST mode, pcm number is (nid number + dev_num - 1) 2030 * dev_num is the device entry number in a pin 2031 * 2032 */ 2033 for (idx = 0; idx < spec->num_nids + spec->dev_num - 1; idx++) { 2034 struct hda_pcm *info; 2035 struct hda_pcm_stream *pstr; 2036 2037 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); 2038 if (!info) 2039 return -ENOMEM; 2040 2041 spec->pcm_rec[idx].pcm = info; 2042 spec->pcm_used++; 2043 info->pcm_type = HDA_PCM_TYPE_HDMI; 2044 info->own_chmap = true; 2045 2046 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2047 pstr->substreams = 1; 2048 pstr->ops = generic_ops; 2049 /* pcm number is less than 16 */ 2050 if (spec->pcm_used >= 16) 2051 break; 2052 /* other pstr fields are set in open */ 2053 } 2054 2055 return 0; 2056 } 2057 2058 static void free_hdmi_jack_priv(struct snd_jack *jack) 2059 { 2060 struct hdmi_pcm *pcm = jack->private_data; 2061 2062 pcm->jack = NULL; 2063 } 2064 2065 static int add_hdmi_jack_kctl(struct hda_codec *codec, 2066 struct hdmi_spec *spec, 2067 int pcm_idx, 2068 const char *name) 2069 { 2070 struct snd_jack *jack; 2071 int err; 2072 2073 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack, 2074 true, false); 2075 if (err < 0) 2076 return err; 2077 2078 spec->pcm_rec[pcm_idx].jack = jack; 2079 jack->private_data = &spec->pcm_rec[pcm_idx]; 2080 jack->private_free = free_hdmi_jack_priv; 2081 return 0; 2082 } 2083 2084 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) 2085 { 2086 char hdmi_str[32] = "HDMI/DP"; 2087 struct hdmi_spec *spec = codec->spec; 2088 struct hdmi_spec_per_pin *per_pin; 2089 struct hda_jack_tbl *jack; 2090 int pcmdev = get_pcm_rec(spec, pcm_idx)->device; 2091 bool phantom_jack; 2092 int ret; 2093 2094 if (pcmdev > 0) 2095 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); 2096 2097 if (spec->dyn_pcm_assign) 2098 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str); 2099 2100 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */ 2101 /* if !dyn_pcm_assign, it must be non-MST mode. 2102 * This means pcms and pins are statically mapped. 2103 * And pcm_idx is pin_idx. 2104 */ 2105 per_pin = get_pin(spec, pcm_idx); 2106 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid); 2107 if (phantom_jack) 2108 strncat(hdmi_str, " Phantom", 2109 sizeof(hdmi_str) - strlen(hdmi_str) - 1); 2110 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 2111 phantom_jack); 2112 if (ret < 0) 2113 return ret; 2114 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid); 2115 if (jack == NULL) 2116 return 0; 2117 /* assign jack->jack to pcm_rec[].jack to 2118 * align with dyn_pcm_assign mode 2119 */ 2120 spec->pcm_rec[pcm_idx].jack = jack->jack; 2121 return 0; 2122 } 2123 2124 static int generic_hdmi_build_controls(struct hda_codec *codec) 2125 { 2126 struct hdmi_spec *spec = codec->spec; 2127 int err; 2128 int pin_idx, pcm_idx; 2129 2130 2131 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2132 err = generic_hdmi_build_jack(codec, pcm_idx); 2133 if (err < 0) 2134 return err; 2135 2136 /* create the spdif for each pcm 2137 * pin will be bound when monitor is connected 2138 */ 2139 if (spec->dyn_pcm_assign) 2140 err = snd_hda_create_dig_out_ctls(codec, 2141 0, spec->cvt_nids[0], 2142 HDA_PCM_TYPE_HDMI); 2143 else { 2144 struct hdmi_spec_per_pin *per_pin = 2145 get_pin(spec, pcm_idx); 2146 err = snd_hda_create_dig_out_ctls(codec, 2147 per_pin->pin_nid, 2148 per_pin->mux_nids[0], 2149 HDA_PCM_TYPE_HDMI); 2150 } 2151 if (err < 0) 2152 return err; 2153 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2154 2155 /* add control for ELD Bytes */ 2156 err = hdmi_create_eld_ctl(codec, pcm_idx, 2157 get_pcm_rec(spec, pcm_idx)->device); 2158 if (err < 0) 2159 return err; 2160 } 2161 2162 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2163 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2164 2165 hdmi_present_sense(per_pin, 0); 2166 } 2167 2168 /* add channel maps */ 2169 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2170 struct hda_pcm *pcm; 2171 2172 pcm = get_pcm_rec(spec, pcm_idx); 2173 if (!pcm || !pcm->pcm) 2174 break; 2175 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); 2176 if (err < 0) 2177 return err; 2178 } 2179 2180 return 0; 2181 } 2182 2183 static int generic_hdmi_init_per_pins(struct hda_codec *codec) 2184 { 2185 struct hdmi_spec *spec = codec->spec; 2186 int pin_idx; 2187 2188 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2189 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2190 2191 per_pin->codec = codec; 2192 mutex_init(&per_pin->lock); 2193 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); 2194 eld_proc_new(per_pin, pin_idx); 2195 } 2196 return 0; 2197 } 2198 2199 static int generic_hdmi_init(struct hda_codec *codec) 2200 { 2201 struct hdmi_spec *spec = codec->spec; 2202 int pin_idx; 2203 2204 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2205 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2206 hda_nid_t pin_nid = per_pin->pin_nid; 2207 int dev_id = per_pin->dev_id; 2208 2209 snd_hda_set_dev_select(codec, pin_nid, dev_id); 2210 hdmi_init_pin(codec, pin_nid); 2211 if (!codec_has_acomp(codec)) 2212 snd_hda_jack_detect_enable_callback(codec, pin_nid, 2213 codec->jackpoll_interval > 0 ? 2214 jack_callback : NULL); 2215 } 2216 return 0; 2217 } 2218 2219 static void hdmi_array_init(struct hdmi_spec *spec, int nums) 2220 { 2221 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); 2222 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); 2223 } 2224 2225 static void hdmi_array_free(struct hdmi_spec *spec) 2226 { 2227 snd_array_free(&spec->pins); 2228 snd_array_free(&spec->cvts); 2229 } 2230 2231 static void generic_spec_free(struct hda_codec *codec) 2232 { 2233 struct hdmi_spec *spec = codec->spec; 2234 2235 if (spec) { 2236 if (spec->i915_bound) 2237 snd_hdac_i915_exit(&codec->bus->core); 2238 hdmi_array_free(spec); 2239 kfree(spec); 2240 codec->spec = NULL; 2241 } 2242 codec->dp_mst = false; 2243 } 2244 2245 static void generic_hdmi_free(struct hda_codec *codec) 2246 { 2247 struct hdmi_spec *spec = codec->spec; 2248 int pin_idx, pcm_idx; 2249 2250 if (codec_has_acomp(codec)) 2251 snd_hdac_i915_register_notifier(NULL); 2252 2253 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2254 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2255 cancel_delayed_work_sync(&per_pin->work); 2256 eld_proc_free(per_pin); 2257 } 2258 2259 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2260 if (spec->pcm_rec[pcm_idx].jack == NULL) 2261 continue; 2262 if (spec->dyn_pcm_assign) 2263 snd_device_free(codec->card, 2264 spec->pcm_rec[pcm_idx].jack); 2265 else 2266 spec->pcm_rec[pcm_idx].jack = NULL; 2267 } 2268 2269 generic_spec_free(codec); 2270 } 2271 2272 #ifdef CONFIG_PM 2273 static int generic_hdmi_resume(struct hda_codec *codec) 2274 { 2275 struct hdmi_spec *spec = codec->spec; 2276 int pin_idx; 2277 2278 codec->patch_ops.init(codec); 2279 regcache_sync(codec->core.regmap); 2280 2281 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2282 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2283 hdmi_present_sense(per_pin, 1); 2284 } 2285 return 0; 2286 } 2287 #endif 2288 2289 static const struct hda_codec_ops generic_hdmi_patch_ops = { 2290 .init = generic_hdmi_init, 2291 .free = generic_hdmi_free, 2292 .build_pcms = generic_hdmi_build_pcms, 2293 .build_controls = generic_hdmi_build_controls, 2294 .unsol_event = hdmi_unsol_event, 2295 #ifdef CONFIG_PM 2296 .resume = generic_hdmi_resume, 2297 #endif 2298 }; 2299 2300 static const struct hdmi_ops generic_standard_hdmi_ops = { 2301 .pin_get_eld = snd_hdmi_get_eld, 2302 .pin_setup_infoframe = hdmi_pin_setup_infoframe, 2303 .pin_hbr_setup = hdmi_pin_hbr_setup, 2304 .setup_stream = hdmi_setup_stream, 2305 }; 2306 2307 /* allocate codec->spec and assign/initialize generic parser ops */ 2308 static int alloc_generic_hdmi(struct hda_codec *codec) 2309 { 2310 struct hdmi_spec *spec; 2311 2312 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2313 if (!spec) 2314 return -ENOMEM; 2315 2316 spec->ops = generic_standard_hdmi_ops; 2317 spec->dev_num = 1; /* initialize to 1 */ 2318 mutex_init(&spec->pcm_lock); 2319 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); 2320 2321 spec->chmap.ops.get_chmap = hdmi_get_chmap; 2322 spec->chmap.ops.set_chmap = hdmi_set_chmap; 2323 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; 2324 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc, 2325 2326 codec->spec = spec; 2327 hdmi_array_init(spec, 4); 2328 2329 codec->patch_ops = generic_hdmi_patch_ops; 2330 2331 return 0; 2332 } 2333 2334 /* generic HDMI parser */ 2335 static int patch_generic_hdmi(struct hda_codec *codec) 2336 { 2337 int err; 2338 2339 err = alloc_generic_hdmi(codec); 2340 if (err < 0) 2341 return err; 2342 2343 err = hdmi_parse_codec(codec); 2344 if (err < 0) { 2345 generic_spec_free(codec); 2346 return err; 2347 } 2348 2349 generic_hdmi_init_per_pins(codec); 2350 return 0; 2351 } 2352 2353 /* 2354 * Intel codec parsers and helpers 2355 */ 2356 2357 static void intel_haswell_fixup_connect_list(struct hda_codec *codec, 2358 hda_nid_t nid) 2359 { 2360 struct hdmi_spec *spec = codec->spec; 2361 hda_nid_t conns[4]; 2362 int nconns; 2363 2364 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns)); 2365 if (nconns == spec->num_cvts && 2366 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t))) 2367 return; 2368 2369 /* override pins connection list */ 2370 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid); 2371 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids); 2372 } 2373 2374 #define INTEL_VENDOR_NID 0x08 2375 #define INTEL_GET_VENDOR_VERB 0xf81 2376 #define INTEL_SET_VENDOR_VERB 0x781 2377 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ 2378 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ 2379 2380 static void intel_haswell_enable_all_pins(struct hda_codec *codec, 2381 bool update_tree) 2382 { 2383 unsigned int vendor_param; 2384 2385 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0, 2386 INTEL_GET_VENDOR_VERB, 0); 2387 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) 2388 return; 2389 2390 vendor_param |= INTEL_EN_ALL_PIN_CVTS; 2391 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0, 2392 INTEL_SET_VENDOR_VERB, vendor_param); 2393 if (vendor_param == -1) 2394 return; 2395 2396 if (update_tree) 2397 snd_hda_codec_update_widgets(codec); 2398 } 2399 2400 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) 2401 { 2402 unsigned int vendor_param; 2403 2404 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0, 2405 INTEL_GET_VENDOR_VERB, 0); 2406 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) 2407 return; 2408 2409 /* enable DP1.2 mode */ 2410 vendor_param |= INTEL_EN_DP12; 2411 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); 2412 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0, 2413 INTEL_SET_VENDOR_VERB, vendor_param); 2414 } 2415 2416 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. 2417 * Otherwise you may get severe h/w communication errors. 2418 */ 2419 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, 2420 unsigned int power_state) 2421 { 2422 if (power_state == AC_PWRST_D0) { 2423 intel_haswell_enable_all_pins(codec, false); 2424 intel_haswell_fixup_enable_dp12(codec); 2425 } 2426 2427 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); 2428 snd_hda_codec_set_power_to_all(codec, fg, power_state); 2429 } 2430 2431 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) 2432 { 2433 struct hda_codec *codec = audio_ptr; 2434 int pin_nid; 2435 int dev_id = pipe; 2436 2437 /* we assume only from port-B to port-D */ 2438 if (port < 1 || port > 3) 2439 return; 2440 2441 switch (codec->core.vendor_id) { 2442 case 0x80860054: /* ILK */ 2443 case 0x80862804: /* ILK */ 2444 case 0x80862882: /* VLV */ 2445 pin_nid = port + 0x03; 2446 break; 2447 default: 2448 pin_nid = port + 0x04; 2449 break; 2450 } 2451 2452 /* skip notification during system suspend (but not in runtime PM); 2453 * the state will be updated at resume 2454 */ 2455 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) 2456 return; 2457 /* ditto during suspend/resume process itself */ 2458 if (atomic_read(&(codec)->core.in_pm)) 2459 return; 2460 2461 snd_hdac_i915_set_bclk(&codec->bus->core); 2462 check_presence_and_report(codec, pin_nid, dev_id); 2463 } 2464 2465 /* register i915 component pin_eld_notify callback */ 2466 static void register_i915_notifier(struct hda_codec *codec) 2467 { 2468 struct hdmi_spec *spec = codec->spec; 2469 2470 spec->use_acomp_notifier = true; 2471 spec->i915_audio_ops.audio_ptr = codec; 2472 /* intel_audio_codec_enable() or intel_audio_codec_disable() 2473 * will call pin_eld_notify with using audio_ptr pointer 2474 * We need make sure audio_ptr is really setup 2475 */ 2476 wmb(); 2477 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify; 2478 snd_hdac_i915_register_notifier(&spec->i915_audio_ops); 2479 } 2480 2481 /* setup_stream ops override for HSW+ */ 2482 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 2483 hda_nid_t pin_nid, u32 stream_tag, int format) 2484 { 2485 haswell_verify_D0(codec, cvt_nid, pin_nid); 2486 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format); 2487 } 2488 2489 /* pin_cvt_fixup ops override for HSW+ and VLV+ */ 2490 static void i915_pin_cvt_fixup(struct hda_codec *codec, 2491 struct hdmi_spec_per_pin *per_pin, 2492 hda_nid_t cvt_nid) 2493 { 2494 if (per_pin) { 2495 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2496 per_pin->dev_id); 2497 intel_verify_pin_cvt_connect(codec, per_pin); 2498 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, 2499 per_pin->dev_id, per_pin->mux_idx); 2500 } else { 2501 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); 2502 } 2503 } 2504 2505 /* Intel Haswell and onwards; audio component with eld notifier */ 2506 static int patch_i915_hsw_hdmi(struct hda_codec *codec) 2507 { 2508 struct hdmi_spec *spec; 2509 int err; 2510 2511 /* HSW+ requires i915 binding */ 2512 if (!codec->bus->core.audio_component) { 2513 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); 2514 return -ENODEV; 2515 } 2516 2517 err = alloc_generic_hdmi(codec); 2518 if (err < 0) 2519 return err; 2520 spec = codec->spec; 2521 codec->dp_mst = true; 2522 spec->dyn_pcm_assign = true; 2523 2524 intel_haswell_enable_all_pins(codec, true); 2525 intel_haswell_fixup_enable_dp12(codec); 2526 2527 /* For Haswell/Broadwell, the controller is also in the power well and 2528 * can cover the codec power request, and so need not set this flag. 2529 */ 2530 if (!is_haswell(codec) && !is_broadwell(codec)) 2531 codec->core.link_power_control = 1; 2532 2533 codec->patch_ops.set_power_state = haswell_set_power_state; 2534 codec->depop_delay = 0; 2535 codec->auto_runtime_pm = 1; 2536 2537 spec->ops.setup_stream = i915_hsw_setup_stream; 2538 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2539 2540 err = hdmi_parse_codec(codec); 2541 if (err < 0) { 2542 generic_spec_free(codec); 2543 return err; 2544 } 2545 2546 generic_hdmi_init_per_pins(codec); 2547 register_i915_notifier(codec); 2548 return 0; 2549 } 2550 2551 /* Intel Baytrail and Braswell; with eld notifier */ 2552 static int patch_i915_byt_hdmi(struct hda_codec *codec) 2553 { 2554 struct hdmi_spec *spec; 2555 int err; 2556 2557 /* requires i915 binding */ 2558 if (!codec->bus->core.audio_component) { 2559 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); 2560 return -ENODEV; 2561 } 2562 2563 err = alloc_generic_hdmi(codec); 2564 if (err < 0) 2565 return err; 2566 spec = codec->spec; 2567 2568 /* For Valleyview/Cherryview, only the display codec is in the display 2569 * power well and can use link_power ops to request/release the power. 2570 */ 2571 codec->core.link_power_control = 1; 2572 2573 codec->depop_delay = 0; 2574 codec->auto_runtime_pm = 1; 2575 2576 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2577 2578 err = hdmi_parse_codec(codec); 2579 if (err < 0) { 2580 generic_spec_free(codec); 2581 return err; 2582 } 2583 2584 generic_hdmi_init_per_pins(codec); 2585 register_i915_notifier(codec); 2586 return 0; 2587 } 2588 2589 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ 2590 static int patch_i915_cpt_hdmi(struct hda_codec *codec) 2591 { 2592 struct hdmi_spec *spec; 2593 int err; 2594 2595 /* no i915 component should have been bound before this */ 2596 if (WARN_ON(codec->bus->core.audio_component)) 2597 return -EBUSY; 2598 2599 err = alloc_generic_hdmi(codec); 2600 if (err < 0) 2601 return err; 2602 spec = codec->spec; 2603 2604 /* Try to bind with i915 now */ 2605 err = snd_hdac_i915_init(&codec->bus->core); 2606 if (err < 0) 2607 goto error; 2608 spec->i915_bound = true; 2609 2610 err = hdmi_parse_codec(codec); 2611 if (err < 0) 2612 goto error; 2613 2614 generic_hdmi_init_per_pins(codec); 2615 register_i915_notifier(codec); 2616 return 0; 2617 2618 error: 2619 generic_spec_free(codec); 2620 return err; 2621 } 2622 2623 /* 2624 * Shared non-generic implementations 2625 */ 2626 2627 static int simple_playback_build_pcms(struct hda_codec *codec) 2628 { 2629 struct hdmi_spec *spec = codec->spec; 2630 struct hda_pcm *info; 2631 unsigned int chans; 2632 struct hda_pcm_stream *pstr; 2633 struct hdmi_spec_per_cvt *per_cvt; 2634 2635 per_cvt = get_cvt(spec, 0); 2636 chans = get_wcaps(codec, per_cvt->cvt_nid); 2637 chans = get_wcaps_channels(chans); 2638 2639 info = snd_hda_codec_pcm_new(codec, "HDMI 0"); 2640 if (!info) 2641 return -ENOMEM; 2642 spec->pcm_rec[0].pcm = info; 2643 info->pcm_type = HDA_PCM_TYPE_HDMI; 2644 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2645 *pstr = spec->pcm_playback; 2646 pstr->nid = per_cvt->cvt_nid; 2647 if (pstr->channels_max <= 2 && chans && chans <= 16) 2648 pstr->channels_max = chans; 2649 2650 return 0; 2651 } 2652 2653 /* unsolicited event for jack sensing */ 2654 static void simple_hdmi_unsol_event(struct hda_codec *codec, 2655 unsigned int res) 2656 { 2657 snd_hda_jack_set_dirty_all(codec); 2658 snd_hda_jack_report_sync(codec); 2659 } 2660 2661 /* generic_hdmi_build_jack can be used for simple_hdmi, too, 2662 * as long as spec->pins[] is set correctly 2663 */ 2664 #define simple_hdmi_build_jack generic_hdmi_build_jack 2665 2666 static int simple_playback_build_controls(struct hda_codec *codec) 2667 { 2668 struct hdmi_spec *spec = codec->spec; 2669 struct hdmi_spec_per_cvt *per_cvt; 2670 int err; 2671 2672 per_cvt = get_cvt(spec, 0); 2673 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, 2674 per_cvt->cvt_nid, 2675 HDA_PCM_TYPE_HDMI); 2676 if (err < 0) 2677 return err; 2678 return simple_hdmi_build_jack(codec, 0); 2679 } 2680 2681 static int simple_playback_init(struct hda_codec *codec) 2682 { 2683 struct hdmi_spec *spec = codec->spec; 2684 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); 2685 hda_nid_t pin = per_pin->pin_nid; 2686 2687 snd_hda_codec_write(codec, pin, 0, 2688 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); 2689 /* some codecs require to unmute the pin */ 2690 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 2691 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, 2692 AMP_OUT_UNMUTE); 2693 snd_hda_jack_detect_enable(codec, pin); 2694 return 0; 2695 } 2696 2697 static void simple_playback_free(struct hda_codec *codec) 2698 { 2699 struct hdmi_spec *spec = codec->spec; 2700 2701 hdmi_array_free(spec); 2702 kfree(spec); 2703 } 2704 2705 /* 2706 * Nvidia specific implementations 2707 */ 2708 2709 #define Nv_VERB_SET_Channel_Allocation 0xF79 2710 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A 2711 #define Nv_VERB_SET_Audio_Protection_On 0xF98 2712 #define Nv_VERB_SET_Audio_Protection_Off 0xF99 2713 2714 #define nvhdmi_master_con_nid_7x 0x04 2715 #define nvhdmi_master_pin_nid_7x 0x05 2716 2717 static const hda_nid_t nvhdmi_con_nids_7x[4] = { 2718 /*front, rear, clfe, rear_surr */ 2719 0x6, 0x8, 0xa, 0xc, 2720 }; 2721 2722 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { 2723 /* set audio protect on */ 2724 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 2725 /* enable digital output on pin widget */ 2726 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2727 {} /* terminator */ 2728 }; 2729 2730 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { 2731 /* set audio protect on */ 2732 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 2733 /* enable digital output on pin widget */ 2734 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2735 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2736 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2737 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2738 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2739 {} /* terminator */ 2740 }; 2741 2742 #ifdef LIMITED_RATE_FMT_SUPPORT 2743 /* support only the safe format and rate */ 2744 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 2745 #define SUPPORTED_MAXBPS 16 2746 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE 2747 #else 2748 /* support all rates and formats */ 2749 #define SUPPORTED_RATES \ 2750 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ 2751 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ 2752 SNDRV_PCM_RATE_192000) 2753 #define SUPPORTED_MAXBPS 24 2754 #define SUPPORTED_FORMATS \ 2755 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 2756 #endif 2757 2758 static int nvhdmi_7x_init_2ch(struct hda_codec *codec) 2759 { 2760 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); 2761 return 0; 2762 } 2763 2764 static int nvhdmi_7x_init_8ch(struct hda_codec *codec) 2765 { 2766 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); 2767 return 0; 2768 } 2769 2770 static unsigned int channels_2_6_8[] = { 2771 2, 6, 8 2772 }; 2773 2774 static unsigned int channels_2_8[] = { 2775 2, 8 2776 }; 2777 2778 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { 2779 .count = ARRAY_SIZE(channels_2_6_8), 2780 .list = channels_2_6_8, 2781 .mask = 0, 2782 }; 2783 2784 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { 2785 .count = ARRAY_SIZE(channels_2_8), 2786 .list = channels_2_8, 2787 .mask = 0, 2788 }; 2789 2790 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, 2791 struct hda_codec *codec, 2792 struct snd_pcm_substream *substream) 2793 { 2794 struct hdmi_spec *spec = codec->spec; 2795 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; 2796 2797 switch (codec->preset->vendor_id) { 2798 case 0x10de0002: 2799 case 0x10de0003: 2800 case 0x10de0005: 2801 case 0x10de0006: 2802 hw_constraints_channels = &hw_constraints_2_8_channels; 2803 break; 2804 case 0x10de0007: 2805 hw_constraints_channels = &hw_constraints_2_6_8_channels; 2806 break; 2807 default: 2808 break; 2809 } 2810 2811 if (hw_constraints_channels != NULL) { 2812 snd_pcm_hw_constraint_list(substream->runtime, 0, 2813 SNDRV_PCM_HW_PARAM_CHANNELS, 2814 hw_constraints_channels); 2815 } else { 2816 snd_pcm_hw_constraint_step(substream->runtime, 0, 2817 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 2818 } 2819 2820 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 2821 } 2822 2823 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, 2824 struct hda_codec *codec, 2825 struct snd_pcm_substream *substream) 2826 { 2827 struct hdmi_spec *spec = codec->spec; 2828 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 2829 } 2830 2831 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 2832 struct hda_codec *codec, 2833 unsigned int stream_tag, 2834 unsigned int format, 2835 struct snd_pcm_substream *substream) 2836 { 2837 struct hdmi_spec *spec = codec->spec; 2838 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 2839 stream_tag, format, substream); 2840 } 2841 2842 static const struct hda_pcm_stream simple_pcm_playback = { 2843 .substreams = 1, 2844 .channels_min = 2, 2845 .channels_max = 2, 2846 .ops = { 2847 .open = simple_playback_pcm_open, 2848 .close = simple_playback_pcm_close, 2849 .prepare = simple_playback_pcm_prepare 2850 }, 2851 }; 2852 2853 static const struct hda_codec_ops simple_hdmi_patch_ops = { 2854 .build_controls = simple_playback_build_controls, 2855 .build_pcms = simple_playback_build_pcms, 2856 .init = simple_playback_init, 2857 .free = simple_playback_free, 2858 .unsol_event = simple_hdmi_unsol_event, 2859 }; 2860 2861 static int patch_simple_hdmi(struct hda_codec *codec, 2862 hda_nid_t cvt_nid, hda_nid_t pin_nid) 2863 { 2864 struct hdmi_spec *spec; 2865 struct hdmi_spec_per_cvt *per_cvt; 2866 struct hdmi_spec_per_pin *per_pin; 2867 2868 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2869 if (!spec) 2870 return -ENOMEM; 2871 2872 codec->spec = spec; 2873 hdmi_array_init(spec, 1); 2874 2875 spec->multiout.num_dacs = 0; /* no analog */ 2876 spec->multiout.max_channels = 2; 2877 spec->multiout.dig_out_nid = cvt_nid; 2878 spec->num_cvts = 1; 2879 spec->num_pins = 1; 2880 per_pin = snd_array_new(&spec->pins); 2881 per_cvt = snd_array_new(&spec->cvts); 2882 if (!per_pin || !per_cvt) { 2883 simple_playback_free(codec); 2884 return -ENOMEM; 2885 } 2886 per_cvt->cvt_nid = cvt_nid; 2887 per_pin->pin_nid = pin_nid; 2888 spec->pcm_playback = simple_pcm_playback; 2889 2890 codec->patch_ops = simple_hdmi_patch_ops; 2891 2892 return 0; 2893 } 2894 2895 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, 2896 int channels) 2897 { 2898 unsigned int chanmask; 2899 int chan = channels ? (channels - 1) : 1; 2900 2901 switch (channels) { 2902 default: 2903 case 0: 2904 case 2: 2905 chanmask = 0x00; 2906 break; 2907 case 4: 2908 chanmask = 0x08; 2909 break; 2910 case 6: 2911 chanmask = 0x0b; 2912 break; 2913 case 8: 2914 chanmask = 0x13; 2915 break; 2916 } 2917 2918 /* Set the audio infoframe channel allocation and checksum fields. The 2919 * channel count is computed implicitly by the hardware. */ 2920 snd_hda_codec_write(codec, 0x1, 0, 2921 Nv_VERB_SET_Channel_Allocation, chanmask); 2922 2923 snd_hda_codec_write(codec, 0x1, 0, 2924 Nv_VERB_SET_Info_Frame_Checksum, 2925 (0x71 - chan - chanmask)); 2926 } 2927 2928 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, 2929 struct hda_codec *codec, 2930 struct snd_pcm_substream *substream) 2931 { 2932 struct hdmi_spec *spec = codec->spec; 2933 int i; 2934 2935 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 2936 0, AC_VERB_SET_CHANNEL_STREAMID, 0); 2937 for (i = 0; i < 4; i++) { 2938 /* set the stream id */ 2939 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 2940 AC_VERB_SET_CHANNEL_STREAMID, 0); 2941 /* set the stream format */ 2942 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 2943 AC_VERB_SET_STREAM_FORMAT, 0); 2944 } 2945 2946 /* The audio hardware sends a channel count of 0x7 (8ch) when all the 2947 * streams are disabled. */ 2948 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 2949 2950 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 2951 } 2952 2953 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, 2954 struct hda_codec *codec, 2955 unsigned int stream_tag, 2956 unsigned int format, 2957 struct snd_pcm_substream *substream) 2958 { 2959 int chs; 2960 unsigned int dataDCC2, channel_id; 2961 int i; 2962 struct hdmi_spec *spec = codec->spec; 2963 struct hda_spdif_out *spdif; 2964 struct hdmi_spec_per_cvt *per_cvt; 2965 2966 mutex_lock(&codec->spdif_mutex); 2967 per_cvt = get_cvt(spec, 0); 2968 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); 2969 2970 chs = substream->runtime->channels; 2971 2972 dataDCC2 = 0x2; 2973 2974 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ 2975 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) 2976 snd_hda_codec_write(codec, 2977 nvhdmi_master_con_nid_7x, 2978 0, 2979 AC_VERB_SET_DIGI_CONVERT_1, 2980 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 2981 2982 /* set the stream id */ 2983 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 2984 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); 2985 2986 /* set the stream format */ 2987 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 2988 AC_VERB_SET_STREAM_FORMAT, format); 2989 2990 /* turn on again (if needed) */ 2991 /* enable and set the channel status audio/data flag */ 2992 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { 2993 snd_hda_codec_write(codec, 2994 nvhdmi_master_con_nid_7x, 2995 0, 2996 AC_VERB_SET_DIGI_CONVERT_1, 2997 spdif->ctls & 0xff); 2998 snd_hda_codec_write(codec, 2999 nvhdmi_master_con_nid_7x, 3000 0, 3001 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3002 } 3003 3004 for (i = 0; i < 4; i++) { 3005 if (chs == 2) 3006 channel_id = 0; 3007 else 3008 channel_id = i * 2; 3009 3010 /* turn off SPDIF once; 3011 *otherwise the IEC958 bits won't be updated 3012 */ 3013 if (codec->spdif_status_reset && 3014 (spdif->ctls & AC_DIG1_ENABLE)) 3015 snd_hda_codec_write(codec, 3016 nvhdmi_con_nids_7x[i], 3017 0, 3018 AC_VERB_SET_DIGI_CONVERT_1, 3019 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3020 /* set the stream id */ 3021 snd_hda_codec_write(codec, 3022 nvhdmi_con_nids_7x[i], 3023 0, 3024 AC_VERB_SET_CHANNEL_STREAMID, 3025 (stream_tag << 4) | channel_id); 3026 /* set the stream format */ 3027 snd_hda_codec_write(codec, 3028 nvhdmi_con_nids_7x[i], 3029 0, 3030 AC_VERB_SET_STREAM_FORMAT, 3031 format); 3032 /* turn on again (if needed) */ 3033 /* enable and set the channel status audio/data flag */ 3034 if (codec->spdif_status_reset && 3035 (spdif->ctls & AC_DIG1_ENABLE)) { 3036 snd_hda_codec_write(codec, 3037 nvhdmi_con_nids_7x[i], 3038 0, 3039 AC_VERB_SET_DIGI_CONVERT_1, 3040 spdif->ctls & 0xff); 3041 snd_hda_codec_write(codec, 3042 nvhdmi_con_nids_7x[i], 3043 0, 3044 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3045 } 3046 } 3047 3048 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); 3049 3050 mutex_unlock(&codec->spdif_mutex); 3051 return 0; 3052 } 3053 3054 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { 3055 .substreams = 1, 3056 .channels_min = 2, 3057 .channels_max = 8, 3058 .nid = nvhdmi_master_con_nid_7x, 3059 .rates = SUPPORTED_RATES, 3060 .maxbps = SUPPORTED_MAXBPS, 3061 .formats = SUPPORTED_FORMATS, 3062 .ops = { 3063 .open = simple_playback_pcm_open, 3064 .close = nvhdmi_8ch_7x_pcm_close, 3065 .prepare = nvhdmi_8ch_7x_pcm_prepare 3066 }, 3067 }; 3068 3069 static int patch_nvhdmi_2ch(struct hda_codec *codec) 3070 { 3071 struct hdmi_spec *spec; 3072 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, 3073 nvhdmi_master_pin_nid_7x); 3074 if (err < 0) 3075 return err; 3076 3077 codec->patch_ops.init = nvhdmi_7x_init_2ch; 3078 /* override the PCM rates, etc, as the codec doesn't give full list */ 3079 spec = codec->spec; 3080 spec->pcm_playback.rates = SUPPORTED_RATES; 3081 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; 3082 spec->pcm_playback.formats = SUPPORTED_FORMATS; 3083 return 0; 3084 } 3085 3086 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) 3087 { 3088 struct hdmi_spec *spec = codec->spec; 3089 int err = simple_playback_build_pcms(codec); 3090 if (!err) { 3091 struct hda_pcm *info = get_pcm_rec(spec, 0); 3092 info->own_chmap = true; 3093 } 3094 return err; 3095 } 3096 3097 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) 3098 { 3099 struct hdmi_spec *spec = codec->spec; 3100 struct hda_pcm *info; 3101 struct snd_pcm_chmap *chmap; 3102 int err; 3103 3104 err = simple_playback_build_controls(codec); 3105 if (err < 0) 3106 return err; 3107 3108 /* add channel maps */ 3109 info = get_pcm_rec(spec, 0); 3110 err = snd_pcm_add_chmap_ctls(info->pcm, 3111 SNDRV_PCM_STREAM_PLAYBACK, 3112 snd_pcm_alt_chmaps, 8, 0, &chmap); 3113 if (err < 0) 3114 return err; 3115 switch (codec->preset->vendor_id) { 3116 case 0x10de0002: 3117 case 0x10de0003: 3118 case 0x10de0005: 3119 case 0x10de0006: 3120 chmap->channel_mask = (1U << 2) | (1U << 8); 3121 break; 3122 case 0x10de0007: 3123 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); 3124 } 3125 return 0; 3126 } 3127 3128 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) 3129 { 3130 struct hdmi_spec *spec; 3131 int err = patch_nvhdmi_2ch(codec); 3132 if (err < 0) 3133 return err; 3134 spec = codec->spec; 3135 spec->multiout.max_channels = 8; 3136 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; 3137 codec->patch_ops.init = nvhdmi_7x_init_8ch; 3138 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; 3139 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; 3140 3141 /* Initialize the audio infoframe channel mask and checksum to something 3142 * valid */ 3143 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3144 3145 return 0; 3146 } 3147 3148 /* 3149 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: 3150 * - 0x10de0015 3151 * - 0x10de0040 3152 */ 3153 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, 3154 struct hdac_cea_channel_speaker_allocation *cap, int channels) 3155 { 3156 if (cap->ca_index == 0x00 && channels == 2) 3157 return SNDRV_CTL_TLVT_CHMAP_FIXED; 3158 3159 /* If the speaker allocation matches the channel count, it is OK. */ 3160 if (cap->channels != channels) 3161 return -1; 3162 3163 /* all channels are remappable freely */ 3164 return SNDRV_CTL_TLVT_CHMAP_VAR; 3165 } 3166 3167 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, 3168 int ca, int chs, unsigned char *map) 3169 { 3170 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) 3171 return -EINVAL; 3172 3173 return 0; 3174 } 3175 3176 static int patch_nvhdmi(struct hda_codec *codec) 3177 { 3178 struct hdmi_spec *spec; 3179 int err; 3180 3181 err = patch_generic_hdmi(codec); 3182 if (err) 3183 return err; 3184 3185 spec = codec->spec; 3186 spec->dyn_pin_out = true; 3187 3188 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3189 nvhdmi_chmap_cea_alloc_validate_get_type; 3190 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3191 3192 return 0; 3193 } 3194 3195 /* 3196 * The HDA codec on NVIDIA Tegra contains two scratch registers that are 3197 * accessed using vendor-defined verbs. These registers can be used for 3198 * interoperability between the HDA and HDMI drivers. 3199 */ 3200 3201 /* Audio Function Group node */ 3202 #define NVIDIA_AFG_NID 0x01 3203 3204 /* 3205 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio 3206 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to 3207 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This 3208 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an 3209 * additional bit (at position 30) to signal the validity of the format. 3210 * 3211 * | 31 | 30 | 29 16 | 15 0 | 3212 * +---------+-------+--------+--------+ 3213 * | TRIGGER | VALID | UNUSED | FORMAT | 3214 * +-----------------------------------| 3215 * 3216 * Note that for the trigger bit to take effect it needs to change value 3217 * (i.e. it needs to be toggled). 3218 */ 3219 #define NVIDIA_GET_SCRATCH0 0xfa6 3220 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 3221 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 3222 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 3223 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa 3224 #define NVIDIA_SCRATCH_TRIGGER (1 << 7) 3225 #define NVIDIA_SCRATCH_VALID (1 << 6) 3226 3227 #define NVIDIA_GET_SCRATCH1 0xfab 3228 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac 3229 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad 3230 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae 3231 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf 3232 3233 /* 3234 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, 3235 * the format is invalidated so that the HDMI codec can be disabled. 3236 */ 3237 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format) 3238 { 3239 unsigned int value; 3240 3241 /* bits [31:30] contain the trigger and valid bits */ 3242 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0, 3243 NVIDIA_GET_SCRATCH0, 0); 3244 value = (value >> 24) & 0xff; 3245 3246 /* bits [15:0] are used to store the HDA format */ 3247 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3248 NVIDIA_SET_SCRATCH0_BYTE0, 3249 (format >> 0) & 0xff); 3250 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3251 NVIDIA_SET_SCRATCH0_BYTE1, 3252 (format >> 8) & 0xff); 3253 3254 /* bits [16:24] are unused */ 3255 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3256 NVIDIA_SET_SCRATCH0_BYTE2, 0); 3257 3258 /* 3259 * Bit 30 signals that the data is valid and hence that HDMI audio can 3260 * be enabled. 3261 */ 3262 if (format == 0) 3263 value &= ~NVIDIA_SCRATCH_VALID; 3264 else 3265 value |= NVIDIA_SCRATCH_VALID; 3266 3267 /* 3268 * Whenever the trigger bit is toggled, an interrupt is raised in the 3269 * HDMI codec. The HDMI driver will use that as trigger to update its 3270 * configuration. 3271 */ 3272 value ^= NVIDIA_SCRATCH_TRIGGER; 3273 3274 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3275 NVIDIA_SET_SCRATCH0_BYTE3, value); 3276 } 3277 3278 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, 3279 struct hda_codec *codec, 3280 unsigned int stream_tag, 3281 unsigned int format, 3282 struct snd_pcm_substream *substream) 3283 { 3284 int err; 3285 3286 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, 3287 format, substream); 3288 if (err < 0) 3289 return err; 3290 3291 /* notify the HDMI codec of the format change */ 3292 tegra_hdmi_set_format(codec, format); 3293 3294 return 0; 3295 } 3296 3297 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, 3298 struct hda_codec *codec, 3299 struct snd_pcm_substream *substream) 3300 { 3301 /* invalidate the format in the HDMI codec */ 3302 tegra_hdmi_set_format(codec, 0); 3303 3304 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); 3305 } 3306 3307 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) 3308 { 3309 struct hdmi_spec *spec = codec->spec; 3310 unsigned int i; 3311 3312 for (i = 0; i < spec->num_pins; i++) { 3313 struct hda_pcm *pcm = get_pcm_rec(spec, i); 3314 3315 if (pcm->pcm_type == type) 3316 return pcm; 3317 } 3318 3319 return NULL; 3320 } 3321 3322 static int tegra_hdmi_build_pcms(struct hda_codec *codec) 3323 { 3324 struct hda_pcm_stream *stream; 3325 struct hda_pcm *pcm; 3326 int err; 3327 3328 err = generic_hdmi_build_pcms(codec); 3329 if (err < 0) 3330 return err; 3331 3332 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); 3333 if (!pcm) 3334 return -ENODEV; 3335 3336 /* 3337 * Override ->prepare() and ->cleanup() operations to notify the HDMI 3338 * codec about format changes. 3339 */ 3340 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3341 stream->ops.prepare = tegra_hdmi_pcm_prepare; 3342 stream->ops.cleanup = tegra_hdmi_pcm_cleanup; 3343 3344 return 0; 3345 } 3346 3347 static int patch_tegra_hdmi(struct hda_codec *codec) 3348 { 3349 int err; 3350 3351 err = patch_generic_hdmi(codec); 3352 if (err) 3353 return err; 3354 3355 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; 3356 3357 return 0; 3358 } 3359 3360 /* 3361 * ATI/AMD-specific implementations 3362 */ 3363 3364 #define is_amdhdmi_rev3_or_later(codec) \ 3365 ((codec)->core.vendor_id == 0x1002aa01 && \ 3366 ((codec)->core.revision_id & 0xff00) >= 0x0300) 3367 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) 3368 3369 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ 3370 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 3371 #define ATI_VERB_SET_DOWNMIX_INFO 0x772 3372 #define ATI_VERB_SET_MULTICHANNEL_01 0x777 3373 #define ATI_VERB_SET_MULTICHANNEL_23 0x778 3374 #define ATI_VERB_SET_MULTICHANNEL_45 0x779 3375 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a 3376 #define ATI_VERB_SET_HBR_CONTROL 0x77c 3377 #define ATI_VERB_SET_MULTICHANNEL_1 0x785 3378 #define ATI_VERB_SET_MULTICHANNEL_3 0x786 3379 #define ATI_VERB_SET_MULTICHANNEL_5 0x787 3380 #define ATI_VERB_SET_MULTICHANNEL_7 0x788 3381 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 3382 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 3383 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 3384 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 3385 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 3386 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 3387 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a 3388 #define ATI_VERB_GET_HBR_CONTROL 0xf7c 3389 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 3390 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 3391 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 3392 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 3393 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 3394 3395 /* AMD specific HDA cvt verbs */ 3396 #define ATI_VERB_SET_RAMP_RATE 0x770 3397 #define ATI_VERB_GET_RAMP_RATE 0xf70 3398 3399 #define ATI_OUT_ENABLE 0x1 3400 3401 #define ATI_MULTICHANNEL_MODE_PAIRED 0 3402 #define ATI_MULTICHANNEL_MODE_SINGLE 1 3403 3404 #define ATI_HBR_CAPABLE 0x01 3405 #define ATI_HBR_ENABLE 0x10 3406 3407 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 3408 unsigned char *buf, int *eld_size) 3409 { 3410 /* call hda_eld.c ATI/AMD-specific function */ 3411 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, 3412 is_amdhdmi_rev3_or_later(codec)); 3413 } 3414 3415 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca, 3416 int active_channels, int conn_type) 3417 { 3418 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); 3419 } 3420 3421 static int atihdmi_paired_swap_fc_lfe(int pos) 3422 { 3423 /* 3424 * ATI/AMD have automatic FC/LFE swap built-in 3425 * when in pairwise mapping mode. 3426 */ 3427 3428 switch (pos) { 3429 /* see channel_allocations[].speakers[] */ 3430 case 2: return 3; 3431 case 3: return 2; 3432 default: break; 3433 } 3434 3435 return pos; 3436 } 3437 3438 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, 3439 int ca, int chs, unsigned char *map) 3440 { 3441 struct hdac_cea_channel_speaker_allocation *cap; 3442 int i, j; 3443 3444 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ 3445 3446 cap = snd_hdac_get_ch_alloc_from_ca(ca); 3447 for (i = 0; i < chs; ++i) { 3448 int mask = snd_hdac_chmap_to_spk_mask(map[i]); 3449 bool ok = false; 3450 bool companion_ok = false; 3451 3452 if (!mask) 3453 continue; 3454 3455 for (j = 0 + i % 2; j < 8; j += 2) { 3456 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); 3457 if (cap->speakers[chan_idx] == mask) { 3458 /* channel is in a supported position */ 3459 ok = true; 3460 3461 if (i % 2 == 0 && i + 1 < chs) { 3462 /* even channel, check the odd companion */ 3463 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); 3464 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); 3465 int comp_mask_act = cap->speakers[comp_chan_idx]; 3466 3467 if (comp_mask_req == comp_mask_act) 3468 companion_ok = true; 3469 else 3470 return -EINVAL; 3471 } 3472 break; 3473 } 3474 } 3475 3476 if (!ok) 3477 return -EINVAL; 3478 3479 if (companion_ok) 3480 i++; /* companion channel already checked */ 3481 } 3482 3483 return 0; 3484 } 3485 3486 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, 3487 hda_nid_t pin_nid, int hdmi_slot, int stream_channel) 3488 { 3489 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 3490 int verb; 3491 int ati_channel_setup = 0; 3492 3493 if (hdmi_slot > 7) 3494 return -EINVAL; 3495 3496 if (!has_amd_full_remap_support(codec)) { 3497 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); 3498 3499 /* In case this is an odd slot but without stream channel, do not 3500 * disable the slot since the corresponding even slot could have a 3501 * channel. In case neither have a channel, the slot pair will be 3502 * disabled when this function is called for the even slot. */ 3503 if (hdmi_slot % 2 != 0 && stream_channel == 0xf) 3504 return 0; 3505 3506 hdmi_slot -= hdmi_slot % 2; 3507 3508 if (stream_channel != 0xf) 3509 stream_channel -= stream_channel % 2; 3510 } 3511 3512 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; 3513 3514 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ 3515 3516 if (stream_channel != 0xf) 3517 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; 3518 3519 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); 3520 } 3521 3522 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, 3523 hda_nid_t pin_nid, int asp_slot) 3524 { 3525 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 3526 bool was_odd = false; 3527 int ati_asp_slot = asp_slot; 3528 int verb; 3529 int ati_channel_setup; 3530 3531 if (asp_slot > 7) 3532 return -EINVAL; 3533 3534 if (!has_amd_full_remap_support(codec)) { 3535 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); 3536 if (ati_asp_slot % 2 != 0) { 3537 ati_asp_slot -= 1; 3538 was_odd = true; 3539 } 3540 } 3541 3542 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; 3543 3544 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); 3545 3546 if (!(ati_channel_setup & ATI_OUT_ENABLE)) 3547 return 0xf; 3548 3549 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; 3550 } 3551 3552 static int atihdmi_paired_chmap_cea_alloc_validate_get_type( 3553 struct hdac_chmap *chmap, 3554 struct hdac_cea_channel_speaker_allocation *cap, 3555 int channels) 3556 { 3557 int c; 3558 3559 /* 3560 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so 3561 * we need to take that into account (a single channel may take 2 3562 * channel slots if we need to carry a silent channel next to it). 3563 * On Rev3+ AMD codecs this function is not used. 3564 */ 3565 int chanpairs = 0; 3566 3567 /* We only produce even-numbered channel count TLVs */ 3568 if ((channels % 2) != 0) 3569 return -1; 3570 3571 for (c = 0; c < 7; c += 2) { 3572 if (cap->speakers[c] || cap->speakers[c+1]) 3573 chanpairs++; 3574 } 3575 3576 if (chanpairs * 2 != channels) 3577 return -1; 3578 3579 return SNDRV_CTL_TLVT_CHMAP_PAIRED; 3580 } 3581 3582 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, 3583 struct hdac_cea_channel_speaker_allocation *cap, 3584 unsigned int *chmap, int channels) 3585 { 3586 /* produce paired maps for pre-rev3 ATI/AMD codecs */ 3587 int count = 0; 3588 int c; 3589 3590 for (c = 7; c >= 0; c--) { 3591 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); 3592 int spk = cap->speakers[chan]; 3593 if (!spk) { 3594 /* add N/A channel if the companion channel is occupied */ 3595 if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) 3596 chmap[count++] = SNDRV_CHMAP_NA; 3597 3598 continue; 3599 } 3600 3601 chmap[count++] = snd_hdac_spk_to_chmap(spk); 3602 } 3603 3604 WARN_ON(count != channels); 3605 } 3606 3607 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 3608 bool hbr) 3609 { 3610 int hbr_ctl, hbr_ctl_new; 3611 3612 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); 3613 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { 3614 if (hbr) 3615 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; 3616 else 3617 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; 3618 3619 codec_dbg(codec, 3620 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", 3621 pin_nid, 3622 hbr_ctl == hbr_ctl_new ? "" : "new-", 3623 hbr_ctl_new); 3624 3625 if (hbr_ctl != hbr_ctl_new) 3626 snd_hda_codec_write(codec, pin_nid, 0, 3627 ATI_VERB_SET_HBR_CONTROL, 3628 hbr_ctl_new); 3629 3630 } else if (hbr) 3631 return -EINVAL; 3632 3633 return 0; 3634 } 3635 3636 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 3637 hda_nid_t pin_nid, u32 stream_tag, int format) 3638 { 3639 3640 if (is_amdhdmi_rev3_or_later(codec)) { 3641 int ramp_rate = 180; /* default as per AMD spec */ 3642 /* disable ramp-up/down for non-pcm as per AMD spec */ 3643 if (format & AC_FMT_TYPE_NON_PCM) 3644 ramp_rate = 0; 3645 3646 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); 3647 } 3648 3649 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format); 3650 } 3651 3652 3653 static int atihdmi_init(struct hda_codec *codec) 3654 { 3655 struct hdmi_spec *spec = codec->spec; 3656 int pin_idx, err; 3657 3658 err = generic_hdmi_init(codec); 3659 3660 if (err) 3661 return err; 3662 3663 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 3664 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 3665 3666 /* make sure downmix information in infoframe is zero */ 3667 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); 3668 3669 /* enable channel-wise remap mode if supported */ 3670 if (has_amd_full_remap_support(codec)) 3671 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 3672 ATI_VERB_SET_MULTICHANNEL_MODE, 3673 ATI_MULTICHANNEL_MODE_SINGLE); 3674 } 3675 3676 return 0; 3677 } 3678 3679 static int patch_atihdmi(struct hda_codec *codec) 3680 { 3681 struct hdmi_spec *spec; 3682 struct hdmi_spec_per_cvt *per_cvt; 3683 int err, cvt_idx; 3684 3685 err = patch_generic_hdmi(codec); 3686 3687 if (err) 3688 return err; 3689 3690 codec->patch_ops.init = atihdmi_init; 3691 3692 spec = codec->spec; 3693 3694 spec->ops.pin_get_eld = atihdmi_pin_get_eld; 3695 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; 3696 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; 3697 spec->ops.setup_stream = atihdmi_setup_stream; 3698 3699 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; 3700 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; 3701 3702 if (!has_amd_full_remap_support(codec)) { 3703 /* override to ATI/AMD-specific versions with pairwise mapping */ 3704 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3705 atihdmi_paired_chmap_cea_alloc_validate_get_type; 3706 spec->chmap.ops.cea_alloc_to_tlv_chmap = 3707 atihdmi_paired_cea_alloc_to_tlv_chmap; 3708 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; 3709 } 3710 3711 /* ATI/AMD converters do not advertise all of their capabilities */ 3712 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 3713 per_cvt = get_cvt(spec, cvt_idx); 3714 per_cvt->channels_max = max(per_cvt->channels_max, 8u); 3715 per_cvt->rates |= SUPPORTED_RATES; 3716 per_cvt->formats |= SUPPORTED_FORMATS; 3717 per_cvt->maxbps = max(per_cvt->maxbps, 24u); 3718 } 3719 3720 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); 3721 3722 return 0; 3723 } 3724 3725 /* VIA HDMI Implementation */ 3726 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ 3727 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ 3728 3729 static int patch_via_hdmi(struct hda_codec *codec) 3730 { 3731 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); 3732 } 3733 3734 /* 3735 * patch entries 3736 */ 3737 static const struct hda_device_id snd_hda_id_hdmi[] = { 3738 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), 3739 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), 3740 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), 3741 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), 3742 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), 3743 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), 3744 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), 3745 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 3746 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 3747 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 3748 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 3749 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), 3750 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi), 3751 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi), 3752 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi), 3753 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi), 3754 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi), 3755 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi), 3756 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi), 3757 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi), 3758 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi), 3759 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi), 3760 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi), 3761 /* 17 is known to be absent */ 3762 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi), 3763 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi), 3764 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi), 3765 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi), 3766 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi), 3767 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), 3768 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), 3769 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), 3770 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), 3771 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), 3772 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), 3773 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), 3774 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), 3775 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), 3776 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), 3777 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), 3778 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), 3779 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), 3780 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), 3781 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), 3782 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), 3783 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), 3784 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), 3785 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), 3786 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), 3787 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), 3788 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), 3789 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), 3790 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), 3791 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), 3792 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), 3793 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), 3794 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), 3795 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), 3796 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), 3797 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), 3798 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), 3799 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), 3800 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), 3801 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), 3802 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), 3803 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), 3804 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), 3805 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), 3806 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), 3807 /* special ID for generic HDMI */ 3808 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), 3809 {} /* terminator */ 3810 }; 3811 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); 3812 3813 MODULE_LICENSE("GPL"); 3814 MODULE_DESCRIPTION("HDMI HD-audio codec"); 3815 MODULE_ALIAS("snd-hda-codec-intelhdmi"); 3816 MODULE_ALIAS("snd-hda-codec-nvhdmi"); 3817 MODULE_ALIAS("snd-hda-codec-atihdmi"); 3818 3819 static struct hda_codec_driver hdmi_driver = { 3820 .id = snd_hda_id_hdmi, 3821 }; 3822 3823 module_hda_codec_driver(hdmi_driver); 3824