1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs 5 * 6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. 7 * Copyright (c) 2006 ATI Technologies Inc. 8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved. 9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com> 10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> 11 * 12 * Authors: 13 * Wu Fengguang <wfg@linux.intel.com> 14 * 15 * Maintained by: 16 * Wu Fengguang <wfg@linux.intel.com> 17 */ 18 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/pci.h> 22 #include <linux/slab.h> 23 #include <linux/module.h> 24 #include <linux/pm_runtime.h> 25 #include <sound/core.h> 26 #include <sound/jack.h> 27 #include <sound/asoundef.h> 28 #include <sound/tlv.h> 29 #include <sound/hdaudio.h> 30 #include <sound/hda_i915.h> 31 #include <sound/hda_chmap.h> 32 #include <sound/hda_codec.h> 33 #include "hda_local.h" 34 #include "hda_jack.h" 35 #include "hda_controller.h" 36 37 static bool static_hdmi_pcm; 38 module_param(static_hdmi_pcm, bool, 0644); 39 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); 40 41 struct hdmi_spec_per_cvt { 42 hda_nid_t cvt_nid; 43 int assigned; 44 unsigned int channels_min; 45 unsigned int channels_max; 46 u32 rates; 47 u64 formats; 48 unsigned int maxbps; 49 }; 50 51 /* max. connections to a widget */ 52 #define HDA_MAX_CONNECTIONS 32 53 54 struct hdmi_spec_per_pin { 55 hda_nid_t pin_nid; 56 int dev_id; 57 /* pin idx, different device entries on the same pin use the same idx */ 58 int pin_nid_idx; 59 int num_mux_nids; 60 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; 61 int mux_idx; 62 hda_nid_t cvt_nid; 63 64 struct hda_codec *codec; 65 struct hdmi_eld sink_eld; 66 struct mutex lock; 67 struct delayed_work work; 68 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ 69 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ 70 int repoll_count; 71 bool setup; /* the stream has been set up by prepare callback */ 72 int channels; /* current number of channels */ 73 bool non_pcm; 74 bool chmap_set; /* channel-map override by ALSA API? */ 75 unsigned char chmap[8]; /* ALSA API channel-map */ 76 #ifdef CONFIG_SND_PROC_FS 77 struct snd_info_entry *proc_entry; 78 #endif 79 }; 80 81 /* operations used by generic code that can be overridden by patches */ 82 struct hdmi_ops { 83 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, 84 int dev_id, unsigned char *buf, int *eld_size); 85 86 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, 87 int dev_id, 88 int ca, int active_channels, int conn_type); 89 90 /* enable/disable HBR (HD passthrough) */ 91 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, 92 int dev_id, bool hbr); 93 94 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, 95 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 96 int format); 97 98 void (*pin_cvt_fixup)(struct hda_codec *codec, 99 struct hdmi_spec_per_pin *per_pin, 100 hda_nid_t cvt_nid); 101 }; 102 103 struct hdmi_pcm { 104 struct hda_pcm *pcm; 105 struct snd_jack *jack; 106 struct snd_kcontrol *eld_ctl; 107 }; 108 109 struct hdmi_spec { 110 struct hda_codec *codec; 111 int num_cvts; 112 struct snd_array cvts; /* struct hdmi_spec_per_cvt */ 113 hda_nid_t cvt_nids[4]; /* only for haswell fix */ 114 115 /* 116 * num_pins is the number of virtual pins 117 * for example, there are 3 pins, and each pin 118 * has 4 device entries, then the num_pins is 12 119 */ 120 int num_pins; 121 /* 122 * num_nids is the number of real pins 123 * In the above example, num_nids is 3 124 */ 125 int num_nids; 126 /* 127 * dev_num is the number of device entries 128 * on each pin. 129 * In the above example, dev_num is 4 130 */ 131 int dev_num; 132 struct snd_array pins; /* struct hdmi_spec_per_pin */ 133 struct hdmi_pcm pcm_rec[16]; 134 struct mutex pcm_lock; 135 struct mutex bind_lock; /* for audio component binding */ 136 /* pcm_bitmap means which pcms have been assigned to pins*/ 137 unsigned long pcm_bitmap; 138 int pcm_used; /* counter of pcm_rec[] */ 139 /* bitmap shows whether the pcm is opened in user space 140 * bit 0 means the first playback PCM (PCM3); 141 * bit 1 means the second playback PCM, and so on. 142 */ 143 unsigned long pcm_in_use; 144 145 struct hdmi_eld temp_eld; 146 struct hdmi_ops ops; 147 148 bool dyn_pin_out; 149 bool dyn_pcm_assign; 150 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */ 151 /* 152 * Non-generic VIA/NVIDIA specific 153 */ 154 struct hda_multi_out multiout; 155 struct hda_pcm_stream pcm_playback; 156 157 bool use_jack_detect; /* jack detection enabled */ 158 bool use_acomp_notifier; /* use eld_notify callback for hotplug */ 159 bool acomp_registered; /* audio component registered in this driver */ 160 struct drm_audio_component_audio_ops drm_audio_ops; 161 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */ 162 163 struct hdac_chmap chmap; 164 hda_nid_t vendor_nid; 165 const int *port_map; 166 int port_num; 167 }; 168 169 #ifdef CONFIG_SND_HDA_COMPONENT 170 static inline bool codec_has_acomp(struct hda_codec *codec) 171 { 172 struct hdmi_spec *spec = codec->spec; 173 return spec->use_acomp_notifier; 174 } 175 #else 176 #define codec_has_acomp(codec) false 177 #endif 178 179 struct hdmi_audio_infoframe { 180 u8 type; /* 0x84 */ 181 u8 ver; /* 0x01 */ 182 u8 len; /* 0x0a */ 183 184 u8 checksum; 185 186 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ 187 u8 SS01_SF24; 188 u8 CXT04; 189 u8 CA; 190 u8 LFEPBL01_LSV36_DM_INH7; 191 }; 192 193 struct dp_audio_infoframe { 194 u8 type; /* 0x84 */ 195 u8 len; /* 0x1b */ 196 u8 ver; /* 0x11 << 2 */ 197 198 u8 CC02_CT47; /* match with HDMI infoframe from this on */ 199 u8 SS01_SF24; 200 u8 CXT04; 201 u8 CA; 202 u8 LFEPBL01_LSV36_DM_INH7; 203 }; 204 205 union audio_infoframe { 206 struct hdmi_audio_infoframe hdmi; 207 struct dp_audio_infoframe dp; 208 u8 bytes[0]; 209 }; 210 211 /* 212 * HDMI routines 213 */ 214 215 #define get_pin(spec, idx) \ 216 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) 217 #define get_cvt(spec, idx) \ 218 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) 219 /* obtain hdmi_pcm object assigned to idx */ 220 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) 221 /* obtain hda_pcm object assigned to idx */ 222 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) 223 224 static int pin_id_to_pin_index(struct hda_codec *codec, 225 hda_nid_t pin_nid, int dev_id) 226 { 227 struct hdmi_spec *spec = codec->spec; 228 int pin_idx; 229 struct hdmi_spec_per_pin *per_pin; 230 231 /* 232 * (dev_id == -1) means it is NON-MST pin 233 * return the first virtual pin on this port 234 */ 235 if (dev_id == -1) 236 dev_id = 0; 237 238 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 239 per_pin = get_pin(spec, pin_idx); 240 if ((per_pin->pin_nid == pin_nid) && 241 (per_pin->dev_id == dev_id)) 242 return pin_idx; 243 } 244 245 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid); 246 return -EINVAL; 247 } 248 249 static int hinfo_to_pcm_index(struct hda_codec *codec, 250 struct hda_pcm_stream *hinfo) 251 { 252 struct hdmi_spec *spec = codec->spec; 253 int pcm_idx; 254 255 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) 256 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) 257 return pcm_idx; 258 259 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo); 260 return -EINVAL; 261 } 262 263 static int hinfo_to_pin_index(struct hda_codec *codec, 264 struct hda_pcm_stream *hinfo) 265 { 266 struct hdmi_spec *spec = codec->spec; 267 struct hdmi_spec_per_pin *per_pin; 268 int pin_idx; 269 270 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 271 per_pin = get_pin(spec, pin_idx); 272 if (per_pin->pcm && 273 per_pin->pcm->pcm->stream == hinfo) 274 return pin_idx; 275 } 276 277 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo); 278 return -EINVAL; 279 } 280 281 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, 282 int pcm_idx) 283 { 284 int i; 285 struct hdmi_spec_per_pin *per_pin; 286 287 for (i = 0; i < spec->num_pins; i++) { 288 per_pin = get_pin(spec, i); 289 if (per_pin->pcm_idx == pcm_idx) 290 return per_pin; 291 } 292 return NULL; 293 } 294 295 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) 296 { 297 struct hdmi_spec *spec = codec->spec; 298 int cvt_idx; 299 300 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) 301 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) 302 return cvt_idx; 303 304 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid); 305 return -EINVAL; 306 } 307 308 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, 309 struct snd_ctl_elem_info *uinfo) 310 { 311 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 312 struct hdmi_spec *spec = codec->spec; 313 struct hdmi_spec_per_pin *per_pin; 314 struct hdmi_eld *eld; 315 int pcm_idx; 316 317 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 318 319 pcm_idx = kcontrol->private_value; 320 mutex_lock(&spec->pcm_lock); 321 per_pin = pcm_idx_to_pin(spec, pcm_idx); 322 if (!per_pin) { 323 /* no pin is bound to the pcm */ 324 uinfo->count = 0; 325 goto unlock; 326 } 327 eld = &per_pin->sink_eld; 328 uinfo->count = eld->eld_valid ? eld->eld_size : 0; 329 330 unlock: 331 mutex_unlock(&spec->pcm_lock); 332 return 0; 333 } 334 335 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, 336 struct snd_ctl_elem_value *ucontrol) 337 { 338 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 339 struct hdmi_spec *spec = codec->spec; 340 struct hdmi_spec_per_pin *per_pin; 341 struct hdmi_eld *eld; 342 int pcm_idx; 343 int err = 0; 344 345 pcm_idx = kcontrol->private_value; 346 mutex_lock(&spec->pcm_lock); 347 per_pin = pcm_idx_to_pin(spec, pcm_idx); 348 if (!per_pin) { 349 /* no pin is bound to the pcm */ 350 memset(ucontrol->value.bytes.data, 0, 351 ARRAY_SIZE(ucontrol->value.bytes.data)); 352 goto unlock; 353 } 354 355 eld = &per_pin->sink_eld; 356 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || 357 eld->eld_size > ELD_MAX_SIZE) { 358 snd_BUG(); 359 err = -EINVAL; 360 goto unlock; 361 } 362 363 memset(ucontrol->value.bytes.data, 0, 364 ARRAY_SIZE(ucontrol->value.bytes.data)); 365 if (eld->eld_valid) 366 memcpy(ucontrol->value.bytes.data, eld->eld_buffer, 367 eld->eld_size); 368 369 unlock: 370 mutex_unlock(&spec->pcm_lock); 371 return err; 372 } 373 374 static const struct snd_kcontrol_new eld_bytes_ctl = { 375 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, 376 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 377 .name = "ELD", 378 .info = hdmi_eld_ctl_info, 379 .get = hdmi_eld_ctl_get, 380 }; 381 382 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, 383 int device) 384 { 385 struct snd_kcontrol *kctl; 386 struct hdmi_spec *spec = codec->spec; 387 int err; 388 389 kctl = snd_ctl_new1(&eld_bytes_ctl, codec); 390 if (!kctl) 391 return -ENOMEM; 392 kctl->private_value = pcm_idx; 393 kctl->id.device = device; 394 395 /* no pin nid is associated with the kctl now 396 * tbd: associate pin nid to eld ctl later 397 */ 398 err = snd_hda_ctl_add(codec, 0, kctl); 399 if (err < 0) 400 return err; 401 402 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; 403 return 0; 404 } 405 406 #ifdef BE_PARANOID 407 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 408 int *packet_index, int *byte_index) 409 { 410 int val; 411 412 val = snd_hda_codec_read(codec, pin_nid, 0, 413 AC_VERB_GET_HDMI_DIP_INDEX, 0); 414 415 *packet_index = val >> 5; 416 *byte_index = val & 0x1f; 417 } 418 #endif 419 420 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 421 int packet_index, int byte_index) 422 { 423 int val; 424 425 val = (packet_index << 5) | (byte_index & 0x1f); 426 427 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); 428 } 429 430 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, 431 unsigned char val) 432 { 433 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); 434 } 435 436 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) 437 { 438 struct hdmi_spec *spec = codec->spec; 439 int pin_out; 440 441 /* Unmute */ 442 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 443 snd_hda_codec_write(codec, pin_nid, 0, 444 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); 445 446 if (spec->dyn_pin_out) 447 /* Disable pin out until stream is active */ 448 pin_out = 0; 449 else 450 /* Enable pin out: some machines with GM965 gets broken output 451 * when the pin is disabled or changed while using with HDMI 452 */ 453 pin_out = PIN_OUT; 454 455 snd_hda_codec_write(codec, pin_nid, 0, 456 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); 457 } 458 459 /* 460 * ELD proc files 461 */ 462 463 #ifdef CONFIG_SND_PROC_FS 464 static void print_eld_info(struct snd_info_entry *entry, 465 struct snd_info_buffer *buffer) 466 { 467 struct hdmi_spec_per_pin *per_pin = entry->private_data; 468 469 mutex_lock(&per_pin->lock); 470 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer); 471 mutex_unlock(&per_pin->lock); 472 } 473 474 static void write_eld_info(struct snd_info_entry *entry, 475 struct snd_info_buffer *buffer) 476 { 477 struct hdmi_spec_per_pin *per_pin = entry->private_data; 478 479 mutex_lock(&per_pin->lock); 480 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); 481 mutex_unlock(&per_pin->lock); 482 } 483 484 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) 485 { 486 char name[32]; 487 struct hda_codec *codec = per_pin->codec; 488 struct snd_info_entry *entry; 489 int err; 490 491 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); 492 err = snd_card_proc_new(codec->card, name, &entry); 493 if (err < 0) 494 return err; 495 496 snd_info_set_text_ops(entry, per_pin, print_eld_info); 497 entry->c.text.write = write_eld_info; 498 entry->mode |= 0200; 499 per_pin->proc_entry = entry; 500 501 return 0; 502 } 503 504 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 505 { 506 if (!per_pin->codec->bus->shutdown) { 507 snd_info_free_entry(per_pin->proc_entry); 508 per_pin->proc_entry = NULL; 509 } 510 } 511 #else 512 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, 513 int index) 514 { 515 return 0; 516 } 517 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 518 { 519 } 520 #endif 521 522 /* 523 * Audio InfoFrame routines 524 */ 525 526 /* 527 * Enable Audio InfoFrame Transmission 528 */ 529 static void hdmi_start_infoframe_trans(struct hda_codec *codec, 530 hda_nid_t pin_nid) 531 { 532 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 533 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 534 AC_DIPXMIT_BEST); 535 } 536 537 /* 538 * Disable Audio InfoFrame Transmission 539 */ 540 static void hdmi_stop_infoframe_trans(struct hda_codec *codec, 541 hda_nid_t pin_nid) 542 { 543 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 544 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 545 AC_DIPXMIT_DISABLE); 546 } 547 548 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) 549 { 550 #ifdef CONFIG_SND_DEBUG_VERBOSE 551 int i; 552 int size; 553 554 size = snd_hdmi_get_eld_size(codec, pin_nid); 555 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); 556 557 for (i = 0; i < 8; i++) { 558 size = snd_hda_codec_read(codec, pin_nid, 0, 559 AC_VERB_GET_HDMI_DIP_SIZE, i); 560 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); 561 } 562 #endif 563 } 564 565 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) 566 { 567 #ifdef BE_PARANOID 568 int i, j; 569 int size; 570 int pi, bi; 571 for (i = 0; i < 8; i++) { 572 size = snd_hda_codec_read(codec, pin_nid, 0, 573 AC_VERB_GET_HDMI_DIP_SIZE, i); 574 if (size == 0) 575 continue; 576 577 hdmi_set_dip_index(codec, pin_nid, i, 0x0); 578 for (j = 1; j < 1000; j++) { 579 hdmi_write_dip_byte(codec, pin_nid, 0x0); 580 hdmi_get_dip_index(codec, pin_nid, &pi, &bi); 581 if (pi != i) 582 codec_dbg(codec, "dip index %d: %d != %d\n", 583 bi, pi, i); 584 if (bi == 0) /* byte index wrapped around */ 585 break; 586 } 587 codec_dbg(codec, 588 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", 589 i, size, j); 590 } 591 #endif 592 } 593 594 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) 595 { 596 u8 *bytes = (u8 *)hdmi_ai; 597 u8 sum = 0; 598 int i; 599 600 hdmi_ai->checksum = 0; 601 602 for (i = 0; i < sizeof(*hdmi_ai); i++) 603 sum += bytes[i]; 604 605 hdmi_ai->checksum = -sum; 606 } 607 608 static void hdmi_fill_audio_infoframe(struct hda_codec *codec, 609 hda_nid_t pin_nid, 610 u8 *dip, int size) 611 { 612 int i; 613 614 hdmi_debug_dip_size(codec, pin_nid); 615 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ 616 617 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 618 for (i = 0; i < size; i++) 619 hdmi_write_dip_byte(codec, pin_nid, dip[i]); 620 } 621 622 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, 623 u8 *dip, int size) 624 { 625 u8 val; 626 int i; 627 628 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) 629 != AC_DIPXMIT_BEST) 630 return false; 631 632 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 633 for (i = 0; i < size; i++) { 634 val = snd_hda_codec_read(codec, pin_nid, 0, 635 AC_VERB_GET_HDMI_DIP_DATA, 0); 636 if (val != dip[i]) 637 return false; 638 } 639 640 return true; 641 } 642 643 static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 644 int dev_id, unsigned char *buf, int *eld_size) 645 { 646 snd_hda_set_dev_select(codec, nid, dev_id); 647 648 return snd_hdmi_get_eld(codec, nid, buf, eld_size); 649 } 650 651 static void hdmi_pin_setup_infoframe(struct hda_codec *codec, 652 hda_nid_t pin_nid, int dev_id, 653 int ca, int active_channels, 654 int conn_type) 655 { 656 union audio_infoframe ai; 657 658 memset(&ai, 0, sizeof(ai)); 659 if (conn_type == 0) { /* HDMI */ 660 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; 661 662 hdmi_ai->type = 0x84; 663 hdmi_ai->ver = 0x01; 664 hdmi_ai->len = 0x0a; 665 hdmi_ai->CC02_CT47 = active_channels - 1; 666 hdmi_ai->CA = ca; 667 hdmi_checksum_audio_infoframe(hdmi_ai); 668 } else if (conn_type == 1) { /* DisplayPort */ 669 struct dp_audio_infoframe *dp_ai = &ai.dp; 670 671 dp_ai->type = 0x84; 672 dp_ai->len = 0x1b; 673 dp_ai->ver = 0x11 << 2; 674 dp_ai->CC02_CT47 = active_channels - 1; 675 dp_ai->CA = ca; 676 } else { 677 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n", 678 pin_nid); 679 return; 680 } 681 682 snd_hda_set_dev_select(codec, pin_nid, dev_id); 683 684 /* 685 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or 686 * sizeof(*dp_ai) to avoid partial match/update problems when 687 * the user switches between HDMI/DP monitors. 688 */ 689 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, 690 sizeof(ai))) { 691 codec_dbg(codec, 692 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n", 693 pin_nid, 694 active_channels, ca); 695 hdmi_stop_infoframe_trans(codec, pin_nid); 696 hdmi_fill_audio_infoframe(codec, pin_nid, 697 ai.bytes, sizeof(ai)); 698 hdmi_start_infoframe_trans(codec, pin_nid); 699 } 700 } 701 702 static void hdmi_setup_audio_infoframe(struct hda_codec *codec, 703 struct hdmi_spec_per_pin *per_pin, 704 bool non_pcm) 705 { 706 struct hdmi_spec *spec = codec->spec; 707 struct hdac_chmap *chmap = &spec->chmap; 708 hda_nid_t pin_nid = per_pin->pin_nid; 709 int dev_id = per_pin->dev_id; 710 int channels = per_pin->channels; 711 int active_channels; 712 struct hdmi_eld *eld; 713 int ca; 714 715 if (!channels) 716 return; 717 718 snd_hda_set_dev_select(codec, pin_nid, dev_id); 719 720 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ 721 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 722 snd_hda_codec_write(codec, pin_nid, 0, 723 AC_VERB_SET_AMP_GAIN_MUTE, 724 AMP_OUT_UNMUTE); 725 726 eld = &per_pin->sink_eld; 727 728 ca = snd_hdac_channel_allocation(&codec->core, 729 eld->info.spk_alloc, channels, 730 per_pin->chmap_set, non_pcm, per_pin->chmap); 731 732 active_channels = snd_hdac_get_active_channels(ca); 733 734 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, 735 active_channels); 736 737 /* 738 * always configure channel mapping, it may have been changed by the 739 * user in the meantime 740 */ 741 snd_hdac_setup_channel_mapping(&spec->chmap, 742 pin_nid, non_pcm, ca, channels, 743 per_pin->chmap, per_pin->chmap_set); 744 745 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id, 746 ca, active_channels, eld->info.conn_type); 747 748 per_pin->non_pcm = non_pcm; 749 } 750 751 /* 752 * Unsolicited events 753 */ 754 755 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); 756 757 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, 758 int dev_id) 759 { 760 struct hdmi_spec *spec = codec->spec; 761 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); 762 763 if (pin_idx < 0) 764 return; 765 mutex_lock(&spec->pcm_lock); 766 if (hdmi_present_sense(get_pin(spec, pin_idx), 1)) 767 snd_hda_jack_report_sync(codec); 768 mutex_unlock(&spec->pcm_lock); 769 } 770 771 static void jack_callback(struct hda_codec *codec, 772 struct hda_jack_callback *jack) 773 { 774 /* stop polling when notification is enabled */ 775 if (codec_has_acomp(codec)) 776 return; 777 778 check_presence_and_report(codec, jack->nid, jack->dev_id); 779 } 780 781 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res) 782 { 783 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 784 struct hda_jack_tbl *jack; 785 786 if (codec->dp_mst) { 787 int dev_entry = 788 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 789 790 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry); 791 } else { 792 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0); 793 } 794 if (!jack) 795 return; 796 jack->jack_dirty = 1; 797 798 codec_dbg(codec, 799 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", 800 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA), 801 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); 802 803 check_presence_and_report(codec, jack->nid, jack->dev_id); 804 } 805 806 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) 807 { 808 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 809 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 810 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); 811 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); 812 813 codec_info(codec, 814 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", 815 codec->addr, 816 tag, 817 subtag, 818 cp_state, 819 cp_ready); 820 821 /* TODO */ 822 if (cp_state) 823 ; 824 if (cp_ready) 825 ; 826 } 827 828 829 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) 830 { 831 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 832 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 833 struct hda_jack_tbl *jack; 834 835 if (codec_has_acomp(codec)) 836 return; 837 838 if (codec->dp_mst) { 839 int dev_entry = 840 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 841 842 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry); 843 } else { 844 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0); 845 } 846 847 if (!jack) { 848 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); 849 return; 850 } 851 852 if (subtag == 0) 853 hdmi_intrinsic_event(codec, res); 854 else 855 hdmi_non_intrinsic_event(codec, res); 856 } 857 858 static void haswell_verify_D0(struct hda_codec *codec, 859 hda_nid_t cvt_nid, hda_nid_t nid) 860 { 861 int pwr; 862 863 /* For Haswell, the converter 1/2 may keep in D3 state after bootup, 864 * thus pins could only choose converter 0 for use. Make sure the 865 * converters are in correct power state */ 866 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) 867 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); 868 869 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { 870 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, 871 AC_PWRST_D0); 872 msleep(40); 873 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); 874 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; 875 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr); 876 } 877 } 878 879 /* 880 * Callbacks 881 */ 882 883 /* HBR should be Non-PCM, 8 channels */ 884 #define is_hbr_format(format) \ 885 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) 886 887 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 888 int dev_id, bool hbr) 889 { 890 int pinctl, new_pinctl; 891 892 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { 893 snd_hda_set_dev_select(codec, pin_nid, dev_id); 894 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 895 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 896 897 if (pinctl < 0) 898 return hbr ? -EINVAL : 0; 899 900 new_pinctl = pinctl & ~AC_PINCTL_EPT; 901 if (hbr) 902 new_pinctl |= AC_PINCTL_EPT_HBR; 903 else 904 new_pinctl |= AC_PINCTL_EPT_NATIVE; 905 906 codec_dbg(codec, 907 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", 908 pin_nid, 909 pinctl == new_pinctl ? "" : "new-", 910 new_pinctl); 911 912 if (pinctl != new_pinctl) 913 snd_hda_codec_write(codec, pin_nid, 0, 914 AC_VERB_SET_PIN_WIDGET_CONTROL, 915 new_pinctl); 916 } else if (hbr) 917 return -EINVAL; 918 919 return 0; 920 } 921 922 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 923 hda_nid_t pin_nid, int dev_id, 924 u32 stream_tag, int format) 925 { 926 struct hdmi_spec *spec = codec->spec; 927 unsigned int param; 928 int err; 929 930 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id, 931 is_hbr_format(format)); 932 933 if (err) { 934 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); 935 return err; 936 } 937 938 if (spec->intel_hsw_fixup) { 939 940 /* 941 * on recent platforms IEC Coding Type is required for HBR 942 * support, read current Digital Converter settings and set 943 * ICT bitfield if needed. 944 */ 945 param = snd_hda_codec_read(codec, cvt_nid, 0, 946 AC_VERB_GET_DIGI_CONVERT_1, 0); 947 948 param = (param >> 16) & ~(AC_DIG3_ICT); 949 950 /* on recent platforms ICT mode is required for HBR support */ 951 if (is_hbr_format(format)) 952 param |= 0x1; 953 954 snd_hda_codec_write(codec, cvt_nid, 0, 955 AC_VERB_SET_DIGI_CONVERT_3, param); 956 } 957 958 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); 959 return 0; 960 } 961 962 /* Try to find an available converter 963 * If pin_idx is less then zero, just try to find an available converter. 964 * Otherwise, try to find an available converter and get the cvt mux index 965 * of the pin. 966 */ 967 static int hdmi_choose_cvt(struct hda_codec *codec, 968 int pin_idx, int *cvt_id) 969 { 970 struct hdmi_spec *spec = codec->spec; 971 struct hdmi_spec_per_pin *per_pin; 972 struct hdmi_spec_per_cvt *per_cvt = NULL; 973 int cvt_idx, mux_idx = 0; 974 975 /* pin_idx < 0 means no pin will be bound to the converter */ 976 if (pin_idx < 0) 977 per_pin = NULL; 978 else 979 per_pin = get_pin(spec, pin_idx); 980 981 /* Dynamically assign converter to stream */ 982 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 983 per_cvt = get_cvt(spec, cvt_idx); 984 985 /* Must not already be assigned */ 986 if (per_cvt->assigned) 987 continue; 988 if (per_pin == NULL) 989 break; 990 /* Must be in pin's mux's list of converters */ 991 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 992 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) 993 break; 994 /* Not in mux list */ 995 if (mux_idx == per_pin->num_mux_nids) 996 continue; 997 break; 998 } 999 1000 /* No free converters */ 1001 if (cvt_idx == spec->num_cvts) 1002 return -EBUSY; 1003 1004 if (per_pin != NULL) 1005 per_pin->mux_idx = mux_idx; 1006 1007 if (cvt_id) 1008 *cvt_id = cvt_idx; 1009 1010 return 0; 1011 } 1012 1013 /* Assure the pin select the right convetor */ 1014 static void intel_verify_pin_cvt_connect(struct hda_codec *codec, 1015 struct hdmi_spec_per_pin *per_pin) 1016 { 1017 hda_nid_t pin_nid = per_pin->pin_nid; 1018 int mux_idx, curr; 1019 1020 mux_idx = per_pin->mux_idx; 1021 curr = snd_hda_codec_read(codec, pin_nid, 0, 1022 AC_VERB_GET_CONNECT_SEL, 0); 1023 if (curr != mux_idx) 1024 snd_hda_codec_write_cache(codec, pin_nid, 0, 1025 AC_VERB_SET_CONNECT_SEL, 1026 mux_idx); 1027 } 1028 1029 /* get the mux index for the converter of the pins 1030 * converter's mux index is the same for all pins on Intel platform 1031 */ 1032 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, 1033 hda_nid_t cvt_nid) 1034 { 1035 int i; 1036 1037 for (i = 0; i < spec->num_cvts; i++) 1038 if (spec->cvt_nids[i] == cvt_nid) 1039 return i; 1040 return -EINVAL; 1041 } 1042 1043 /* Intel HDMI workaround to fix audio routing issue: 1044 * For some Intel display codecs, pins share the same connection list. 1045 * So a conveter can be selected by multiple pins and playback on any of these 1046 * pins will generate sound on the external display, because audio flows from 1047 * the same converter to the display pipeline. Also muting one pin may make 1048 * other pins have no sound output. 1049 * So this function assures that an assigned converter for a pin is not selected 1050 * by any other pins. 1051 */ 1052 static void intel_not_share_assigned_cvt(struct hda_codec *codec, 1053 hda_nid_t pin_nid, 1054 int dev_id, int mux_idx) 1055 { 1056 struct hdmi_spec *spec = codec->spec; 1057 hda_nid_t nid; 1058 int cvt_idx, curr; 1059 struct hdmi_spec_per_cvt *per_cvt; 1060 struct hdmi_spec_per_pin *per_pin; 1061 int pin_idx; 1062 1063 /* configure the pins connections */ 1064 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 1065 int dev_id_saved; 1066 int dev_num; 1067 1068 per_pin = get_pin(spec, pin_idx); 1069 /* 1070 * pin not connected to monitor 1071 * no need to operate on it 1072 */ 1073 if (!per_pin->pcm) 1074 continue; 1075 1076 if ((per_pin->pin_nid == pin_nid) && 1077 (per_pin->dev_id == dev_id)) 1078 continue; 1079 1080 /* 1081 * if per_pin->dev_id >= dev_num, 1082 * snd_hda_get_dev_select() will fail, 1083 * and the following operation is unpredictable. 1084 * So skip this situation. 1085 */ 1086 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; 1087 if (per_pin->dev_id >= dev_num) 1088 continue; 1089 1090 nid = per_pin->pin_nid; 1091 1092 /* 1093 * Calling this function should not impact 1094 * on the device entry selection 1095 * So let's save the dev id for each pin, 1096 * and restore it when return 1097 */ 1098 dev_id_saved = snd_hda_get_dev_select(codec, nid); 1099 snd_hda_set_dev_select(codec, nid, per_pin->dev_id); 1100 curr = snd_hda_codec_read(codec, nid, 0, 1101 AC_VERB_GET_CONNECT_SEL, 0); 1102 if (curr != mux_idx) { 1103 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1104 continue; 1105 } 1106 1107 1108 /* choose an unassigned converter. The conveters in the 1109 * connection list are in the same order as in the codec. 1110 */ 1111 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1112 per_cvt = get_cvt(spec, cvt_idx); 1113 if (!per_cvt->assigned) { 1114 codec_dbg(codec, 1115 "choose cvt %d for pin nid %d\n", 1116 cvt_idx, nid); 1117 snd_hda_codec_write_cache(codec, nid, 0, 1118 AC_VERB_SET_CONNECT_SEL, 1119 cvt_idx); 1120 break; 1121 } 1122 } 1123 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1124 } 1125 } 1126 1127 /* A wrapper of intel_not_share_asigned_cvt() */ 1128 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, 1129 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) 1130 { 1131 int mux_idx; 1132 struct hdmi_spec *spec = codec->spec; 1133 1134 /* On Intel platform, the mapping of converter nid to 1135 * mux index of the pins are always the same. 1136 * The pin nid may be 0, this means all pins will not 1137 * share the converter. 1138 */ 1139 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); 1140 if (mux_idx >= 0) 1141 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); 1142 } 1143 1144 /* skeleton caller of pin_cvt_fixup ops */ 1145 static void pin_cvt_fixup(struct hda_codec *codec, 1146 struct hdmi_spec_per_pin *per_pin, 1147 hda_nid_t cvt_nid) 1148 { 1149 struct hdmi_spec *spec = codec->spec; 1150 1151 if (spec->ops.pin_cvt_fixup) 1152 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); 1153 } 1154 1155 /* called in hdmi_pcm_open when no pin is assigned to the PCM 1156 * in dyn_pcm_assign mode. 1157 */ 1158 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, 1159 struct hda_codec *codec, 1160 struct snd_pcm_substream *substream) 1161 { 1162 struct hdmi_spec *spec = codec->spec; 1163 struct snd_pcm_runtime *runtime = substream->runtime; 1164 int cvt_idx, pcm_idx; 1165 struct hdmi_spec_per_cvt *per_cvt = NULL; 1166 int err; 1167 1168 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1169 if (pcm_idx < 0) 1170 return -EINVAL; 1171 1172 err = hdmi_choose_cvt(codec, -1, &cvt_idx); 1173 if (err) 1174 return err; 1175 1176 per_cvt = get_cvt(spec, cvt_idx); 1177 per_cvt->assigned = 1; 1178 hinfo->nid = per_cvt->cvt_nid; 1179 1180 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); 1181 1182 set_bit(pcm_idx, &spec->pcm_in_use); 1183 /* todo: setup spdif ctls assign */ 1184 1185 /* Initially set the converter's capabilities */ 1186 hinfo->channels_min = per_cvt->channels_min; 1187 hinfo->channels_max = per_cvt->channels_max; 1188 hinfo->rates = per_cvt->rates; 1189 hinfo->formats = per_cvt->formats; 1190 hinfo->maxbps = per_cvt->maxbps; 1191 1192 /* Store the updated parameters */ 1193 runtime->hw.channels_min = hinfo->channels_min; 1194 runtime->hw.channels_max = hinfo->channels_max; 1195 runtime->hw.formats = hinfo->formats; 1196 runtime->hw.rates = hinfo->rates; 1197 1198 snd_pcm_hw_constraint_step(substream->runtime, 0, 1199 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1200 return 0; 1201 } 1202 1203 /* 1204 * HDA PCM callbacks 1205 */ 1206 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, 1207 struct hda_codec *codec, 1208 struct snd_pcm_substream *substream) 1209 { 1210 struct hdmi_spec *spec = codec->spec; 1211 struct snd_pcm_runtime *runtime = substream->runtime; 1212 int pin_idx, cvt_idx, pcm_idx; 1213 struct hdmi_spec_per_pin *per_pin; 1214 struct hdmi_eld *eld; 1215 struct hdmi_spec_per_cvt *per_cvt = NULL; 1216 int err; 1217 1218 /* Validate hinfo */ 1219 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1220 if (pcm_idx < 0) 1221 return -EINVAL; 1222 1223 mutex_lock(&spec->pcm_lock); 1224 pin_idx = hinfo_to_pin_index(codec, hinfo); 1225 if (!spec->dyn_pcm_assign) { 1226 if (snd_BUG_ON(pin_idx < 0)) { 1227 err = -EINVAL; 1228 goto unlock; 1229 } 1230 } else { 1231 /* no pin is assigned to the PCM 1232 * PA need pcm open successfully when probe 1233 */ 1234 if (pin_idx < 0) { 1235 err = hdmi_pcm_open_no_pin(hinfo, codec, substream); 1236 goto unlock; 1237 } 1238 } 1239 1240 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx); 1241 if (err < 0) 1242 goto unlock; 1243 1244 per_cvt = get_cvt(spec, cvt_idx); 1245 /* Claim converter */ 1246 per_cvt->assigned = 1; 1247 1248 set_bit(pcm_idx, &spec->pcm_in_use); 1249 per_pin = get_pin(spec, pin_idx); 1250 per_pin->cvt_nid = per_cvt->cvt_nid; 1251 hinfo->nid = per_cvt->cvt_nid; 1252 1253 /* flip stripe flag for the assigned stream if supported */ 1254 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE) 1255 azx_stream(get_azx_dev(substream))->stripe = 1; 1256 1257 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1258 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1259 AC_VERB_SET_CONNECT_SEL, 1260 per_pin->mux_idx); 1261 1262 /* configure unused pins to choose other converters */ 1263 pin_cvt_fixup(codec, per_pin, 0); 1264 1265 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); 1266 1267 /* Initially set the converter's capabilities */ 1268 hinfo->channels_min = per_cvt->channels_min; 1269 hinfo->channels_max = per_cvt->channels_max; 1270 hinfo->rates = per_cvt->rates; 1271 hinfo->formats = per_cvt->formats; 1272 hinfo->maxbps = per_cvt->maxbps; 1273 1274 eld = &per_pin->sink_eld; 1275 /* Restrict capabilities by ELD if this isn't disabled */ 1276 if (!static_hdmi_pcm && eld->eld_valid) { 1277 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); 1278 if (hinfo->channels_min > hinfo->channels_max || 1279 !hinfo->rates || !hinfo->formats) { 1280 per_cvt->assigned = 0; 1281 hinfo->nid = 0; 1282 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1283 err = -ENODEV; 1284 goto unlock; 1285 } 1286 } 1287 1288 /* Store the updated parameters */ 1289 runtime->hw.channels_min = hinfo->channels_min; 1290 runtime->hw.channels_max = hinfo->channels_max; 1291 runtime->hw.formats = hinfo->formats; 1292 runtime->hw.rates = hinfo->rates; 1293 1294 snd_pcm_hw_constraint_step(substream->runtime, 0, 1295 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1296 unlock: 1297 mutex_unlock(&spec->pcm_lock); 1298 return err; 1299 } 1300 1301 /* 1302 * HDA/HDMI auto parsing 1303 */ 1304 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) 1305 { 1306 struct hdmi_spec *spec = codec->spec; 1307 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1308 hda_nid_t pin_nid = per_pin->pin_nid; 1309 int dev_id = per_pin->dev_id; 1310 int conns; 1311 1312 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { 1313 codec_warn(codec, 1314 "HDMI: pin %d wcaps %#x does not support connection list\n", 1315 pin_nid, get_wcaps(codec, pin_nid)); 1316 return -EINVAL; 1317 } 1318 1319 snd_hda_set_dev_select(codec, pin_nid, dev_id); 1320 1321 if (spec->intel_hsw_fixup) { 1322 conns = spec->num_cvts; 1323 memcpy(per_pin->mux_nids, spec->cvt_nids, 1324 sizeof(hda_nid_t) * conns); 1325 } else { 1326 conns = snd_hda_get_raw_connections(codec, pin_nid, 1327 per_pin->mux_nids, 1328 HDA_MAX_CONNECTIONS); 1329 } 1330 1331 /* all the device entries on the same pin have the same conn list */ 1332 per_pin->num_mux_nids = conns; 1333 1334 return 0; 1335 } 1336 1337 static int hdmi_find_pcm_slot(struct hdmi_spec *spec, 1338 struct hdmi_spec_per_pin *per_pin) 1339 { 1340 int i; 1341 1342 /* 1343 * generic_hdmi_build_pcms() may allocate extra PCMs on some 1344 * platforms (with maximum of 'num_nids + dev_num - 1') 1345 * 1346 * The per_pin of pin_nid_idx=n and dev_id=m prefers to get pcm-n 1347 * if m==0. This guarantees that dynamic pcm assignments are compatible 1348 * with the legacy static per_pin-pcm assignment that existed in the 1349 * days before DP-MST. 1350 * 1351 * Intel DP-MST prefers this legacy behavior for compatibility, too. 1352 * 1353 * per_pin of m!=0 prefers to get pcm=(num_nids + (m - 1)). 1354 */ 1355 1356 if (per_pin->dev_id == 0 || spec->intel_hsw_fixup) { 1357 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap)) 1358 return per_pin->pin_nid_idx; 1359 } else { 1360 i = spec->num_nids + (per_pin->dev_id - 1); 1361 if (i < spec->pcm_used && !(test_bit(i, &spec->pcm_bitmap))) 1362 return i; 1363 } 1364 1365 /* have a second try; check the area over num_nids */ 1366 for (i = spec->num_nids; i < spec->pcm_used; i++) { 1367 if (!test_bit(i, &spec->pcm_bitmap)) 1368 return i; 1369 } 1370 1371 /* the last try; check the empty slots in pins */ 1372 for (i = 0; i < spec->num_nids; i++) { 1373 if (!test_bit(i, &spec->pcm_bitmap)) 1374 return i; 1375 } 1376 return -EBUSY; 1377 } 1378 1379 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, 1380 struct hdmi_spec_per_pin *per_pin) 1381 { 1382 int idx; 1383 1384 /* pcm already be attached to the pin */ 1385 if (per_pin->pcm) 1386 return; 1387 idx = hdmi_find_pcm_slot(spec, per_pin); 1388 if (idx == -EBUSY) 1389 return; 1390 per_pin->pcm_idx = idx; 1391 per_pin->pcm = get_hdmi_pcm(spec, idx); 1392 set_bit(idx, &spec->pcm_bitmap); 1393 } 1394 1395 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, 1396 struct hdmi_spec_per_pin *per_pin) 1397 { 1398 int idx; 1399 1400 /* pcm already be detached from the pin */ 1401 if (!per_pin->pcm) 1402 return; 1403 idx = per_pin->pcm_idx; 1404 per_pin->pcm_idx = -1; 1405 per_pin->pcm = NULL; 1406 if (idx >= 0 && idx < spec->pcm_used) 1407 clear_bit(idx, &spec->pcm_bitmap); 1408 } 1409 1410 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, 1411 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) 1412 { 1413 int mux_idx; 1414 1415 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1416 if (per_pin->mux_nids[mux_idx] == cvt_nid) 1417 break; 1418 return mux_idx; 1419 } 1420 1421 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); 1422 1423 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, 1424 struct hdmi_spec_per_pin *per_pin) 1425 { 1426 struct hda_codec *codec = per_pin->codec; 1427 struct hda_pcm *pcm; 1428 struct hda_pcm_stream *hinfo; 1429 struct snd_pcm_substream *substream; 1430 int mux_idx; 1431 bool non_pcm; 1432 1433 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1434 pcm = get_pcm_rec(spec, per_pin->pcm_idx); 1435 else 1436 return; 1437 if (!pcm->pcm) 1438 return; 1439 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) 1440 return; 1441 1442 /* hdmi audio only uses playback and one substream */ 1443 hinfo = pcm->stream; 1444 substream = pcm->pcm->streams[0].substream; 1445 1446 per_pin->cvt_nid = hinfo->nid; 1447 1448 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); 1449 if (mux_idx < per_pin->num_mux_nids) { 1450 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1451 per_pin->dev_id); 1452 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1453 AC_VERB_SET_CONNECT_SEL, 1454 mux_idx); 1455 } 1456 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); 1457 1458 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); 1459 if (substream->runtime) 1460 per_pin->channels = substream->runtime->channels; 1461 per_pin->setup = true; 1462 per_pin->mux_idx = mux_idx; 1463 1464 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1465 } 1466 1467 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, 1468 struct hdmi_spec_per_pin *per_pin) 1469 { 1470 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1471 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); 1472 1473 per_pin->chmap_set = false; 1474 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1475 1476 per_pin->setup = false; 1477 per_pin->channels = 0; 1478 } 1479 1480 /* update per_pin ELD from the given new ELD; 1481 * setup info frame and notification accordingly 1482 */ 1483 static bool update_eld(struct hda_codec *codec, 1484 struct hdmi_spec_per_pin *per_pin, 1485 struct hdmi_eld *eld) 1486 { 1487 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 1488 struct hdmi_spec *spec = codec->spec; 1489 bool old_eld_valid = pin_eld->eld_valid; 1490 bool eld_changed; 1491 int pcm_idx; 1492 1493 /* for monitor disconnection, save pcm_idx firstly */ 1494 pcm_idx = per_pin->pcm_idx; 1495 if (spec->dyn_pcm_assign) { 1496 if (eld->eld_valid) { 1497 hdmi_attach_hda_pcm(spec, per_pin); 1498 hdmi_pcm_setup_pin(spec, per_pin); 1499 } else { 1500 hdmi_pcm_reset_pin(spec, per_pin); 1501 hdmi_detach_hda_pcm(spec, per_pin); 1502 } 1503 } 1504 /* if pcm_idx == -1, it means this is in monitor connection event 1505 * we can get the correct pcm_idx now. 1506 */ 1507 if (pcm_idx == -1) 1508 pcm_idx = per_pin->pcm_idx; 1509 1510 if (eld->eld_valid) 1511 snd_hdmi_show_eld(codec, &eld->info); 1512 1513 eld_changed = (pin_eld->eld_valid != eld->eld_valid); 1514 eld_changed |= (pin_eld->monitor_present != eld->monitor_present); 1515 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid) 1516 if (pin_eld->eld_size != eld->eld_size || 1517 memcmp(pin_eld->eld_buffer, eld->eld_buffer, 1518 eld->eld_size) != 0) 1519 eld_changed = true; 1520 1521 if (eld_changed) { 1522 pin_eld->monitor_present = eld->monitor_present; 1523 pin_eld->eld_valid = eld->eld_valid; 1524 pin_eld->eld_size = eld->eld_size; 1525 if (eld->eld_valid) 1526 memcpy(pin_eld->eld_buffer, eld->eld_buffer, 1527 eld->eld_size); 1528 pin_eld->info = eld->info; 1529 } 1530 1531 /* 1532 * Re-setup pin and infoframe. This is needed e.g. when 1533 * - sink is first plugged-in 1534 * - transcoder can change during stream playback on Haswell 1535 * and this can make HW reset converter selection on a pin. 1536 */ 1537 if (eld->eld_valid && !old_eld_valid && per_pin->setup) { 1538 pin_cvt_fixup(codec, per_pin, 0); 1539 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1540 } 1541 1542 if (eld_changed && pcm_idx >= 0) 1543 snd_ctl_notify(codec->card, 1544 SNDRV_CTL_EVENT_MASK_VALUE | 1545 SNDRV_CTL_EVENT_MASK_INFO, 1546 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); 1547 return eld_changed; 1548 } 1549 1550 /* update ELD and jack state via HD-audio verbs */ 1551 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, 1552 int repoll) 1553 { 1554 struct hda_jack_tbl *jack; 1555 struct hda_codec *codec = per_pin->codec; 1556 struct hdmi_spec *spec = codec->spec; 1557 struct hdmi_eld *eld = &spec->temp_eld; 1558 hda_nid_t pin_nid = per_pin->pin_nid; 1559 int dev_id = per_pin->dev_id; 1560 /* 1561 * Always execute a GetPinSense verb here, even when called from 1562 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited 1563 * response's PD bit is not the real PD value, but indicates that 1564 * the real PD value changed. An older version of the HD-audio 1565 * specification worked this way. Hence, we just ignore the data in 1566 * the unsolicited response to avoid custom WARs. 1567 */ 1568 int present; 1569 bool ret; 1570 bool do_repoll = false; 1571 1572 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id); 1573 1574 mutex_lock(&per_pin->lock); 1575 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); 1576 if (eld->monitor_present) 1577 eld->eld_valid = !!(present & AC_PINSENSE_ELDV); 1578 else 1579 eld->eld_valid = false; 1580 1581 codec_dbg(codec, 1582 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n", 1583 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); 1584 1585 if (eld->eld_valid) { 1586 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id, 1587 eld->eld_buffer, &eld->eld_size) < 0) 1588 eld->eld_valid = false; 1589 else { 1590 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, 1591 eld->eld_size) < 0) 1592 eld->eld_valid = false; 1593 } 1594 if (!eld->eld_valid && repoll) 1595 do_repoll = true; 1596 } 1597 1598 if (do_repoll) 1599 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300)); 1600 else 1601 update_eld(codec, per_pin, eld); 1602 1603 ret = !repoll || !eld->monitor_present || eld->eld_valid; 1604 1605 jack = snd_hda_jack_tbl_get_mst(codec, pin_nid, per_pin->dev_id); 1606 if (jack) { 1607 jack->block_report = !ret; 1608 jack->pin_sense = (eld->monitor_present && eld->eld_valid) ? 1609 AC_PINSENSE_PRESENCE : 0; 1610 } 1611 mutex_unlock(&per_pin->lock); 1612 return ret; 1613 } 1614 1615 static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec, 1616 struct hdmi_spec_per_pin *per_pin) 1617 { 1618 struct hdmi_spec *spec = codec->spec; 1619 struct snd_jack *jack = NULL; 1620 struct hda_jack_tbl *jack_tbl; 1621 1622 /* if !dyn_pcm_assign, get jack from hda_jack_tbl 1623 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not 1624 * NULL even after snd_hda_jack_tbl_clear() is called to 1625 * free snd_jack. This may cause access invalid memory 1626 * when calling snd_jack_report 1627 */ 1628 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign) 1629 jack = spec->pcm_rec[per_pin->pcm_idx].jack; 1630 else if (!spec->dyn_pcm_assign) { 1631 /* 1632 * jack tbl doesn't support DP MST 1633 * DP MST will use dyn_pcm_assign, 1634 * so DP MST will never come here 1635 */ 1636 jack_tbl = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid, 1637 per_pin->dev_id); 1638 if (jack_tbl) 1639 jack = jack_tbl->jack; 1640 } 1641 return jack; 1642 } 1643 1644 /* update ELD and jack state via audio component */ 1645 static void sync_eld_via_acomp(struct hda_codec *codec, 1646 struct hdmi_spec_per_pin *per_pin) 1647 { 1648 struct hdmi_spec *spec = codec->spec; 1649 struct hdmi_eld *eld = &spec->temp_eld; 1650 struct snd_jack *jack = NULL; 1651 bool changed; 1652 int size; 1653 1654 mutex_lock(&per_pin->lock); 1655 eld->monitor_present = false; 1656 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, 1657 per_pin->dev_id, &eld->monitor_present, 1658 eld->eld_buffer, ELD_MAX_SIZE); 1659 if (size > 0) { 1660 size = min(size, ELD_MAX_SIZE); 1661 if (snd_hdmi_parse_eld(codec, &eld->info, 1662 eld->eld_buffer, size) < 0) 1663 size = -EINVAL; 1664 } 1665 1666 if (size > 0) { 1667 eld->eld_valid = true; 1668 eld->eld_size = size; 1669 } else { 1670 eld->eld_valid = false; 1671 eld->eld_size = 0; 1672 } 1673 1674 /* pcm_idx >=0 before update_eld() means it is in monitor 1675 * disconnected event. Jack must be fetched before update_eld() 1676 */ 1677 jack = pin_idx_to_jack(codec, per_pin); 1678 changed = update_eld(codec, per_pin, eld); 1679 if (jack == NULL) 1680 jack = pin_idx_to_jack(codec, per_pin); 1681 if (changed && jack) 1682 snd_jack_report(jack, 1683 (eld->monitor_present && eld->eld_valid) ? 1684 SND_JACK_AVOUT : 0); 1685 mutex_unlock(&per_pin->lock); 1686 } 1687 1688 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) 1689 { 1690 struct hda_codec *codec = per_pin->codec; 1691 int ret; 1692 1693 /* no temporary power up/down needed for component notifier */ 1694 if (!codec_has_acomp(codec)) { 1695 ret = snd_hda_power_up_pm(codec); 1696 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) { 1697 snd_hda_power_down_pm(codec); 1698 return false; 1699 } 1700 ret = hdmi_present_sense_via_verbs(per_pin, repoll); 1701 snd_hda_power_down_pm(codec); 1702 } else { 1703 sync_eld_via_acomp(codec, per_pin); 1704 ret = false; /* don't call snd_hda_jack_report_sync() */ 1705 } 1706 1707 return ret; 1708 } 1709 1710 static void hdmi_repoll_eld(struct work_struct *work) 1711 { 1712 struct hdmi_spec_per_pin *per_pin = 1713 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); 1714 struct hda_codec *codec = per_pin->codec; 1715 struct hdmi_spec *spec = codec->spec; 1716 struct hda_jack_tbl *jack; 1717 1718 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid, 1719 per_pin->dev_id); 1720 if (jack) 1721 jack->jack_dirty = 1; 1722 1723 if (per_pin->repoll_count++ > 6) 1724 per_pin->repoll_count = 0; 1725 1726 mutex_lock(&spec->pcm_lock); 1727 if (hdmi_present_sense(per_pin, per_pin->repoll_count)) 1728 snd_hda_jack_report_sync(per_pin->codec); 1729 mutex_unlock(&spec->pcm_lock); 1730 } 1731 1732 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) 1733 { 1734 struct hdmi_spec *spec = codec->spec; 1735 unsigned int caps, config; 1736 int pin_idx; 1737 struct hdmi_spec_per_pin *per_pin; 1738 int err; 1739 int dev_num, i; 1740 1741 caps = snd_hda_query_pin_caps(codec, pin_nid); 1742 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) 1743 return 0; 1744 1745 /* 1746 * For DP MST audio, Configuration Default is the same for 1747 * all device entries on the same pin 1748 */ 1749 config = snd_hda_codec_get_pincfg(codec, pin_nid); 1750 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE) 1751 return 0; 1752 1753 /* 1754 * To simplify the implementation, malloc all 1755 * the virtual pins in the initialization statically 1756 */ 1757 if (spec->intel_hsw_fixup) { 1758 /* 1759 * On Intel platforms, device entries number is 1760 * changed dynamically. If there is a DP MST 1761 * hub connected, the device entries number is 3. 1762 * Otherwise, it is 1. 1763 * Here we manually set dev_num to 3, so that 1764 * we can initialize all the device entries when 1765 * bootup statically. 1766 */ 1767 dev_num = 3; 1768 spec->dev_num = 3; 1769 } else if (spec->dyn_pcm_assign && codec->dp_mst) { 1770 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; 1771 /* 1772 * spec->dev_num is the maxinum number of device entries 1773 * among all the pins 1774 */ 1775 spec->dev_num = (spec->dev_num > dev_num) ? 1776 spec->dev_num : dev_num; 1777 } else { 1778 /* 1779 * If the platform doesn't support DP MST, 1780 * manually set dev_num to 1. This means 1781 * the pin has only one device entry. 1782 */ 1783 dev_num = 1; 1784 spec->dev_num = 1; 1785 } 1786 1787 for (i = 0; i < dev_num; i++) { 1788 pin_idx = spec->num_pins; 1789 per_pin = snd_array_new(&spec->pins); 1790 1791 if (!per_pin) 1792 return -ENOMEM; 1793 1794 if (spec->dyn_pcm_assign) { 1795 per_pin->pcm = NULL; 1796 per_pin->pcm_idx = -1; 1797 } else { 1798 per_pin->pcm = get_hdmi_pcm(spec, pin_idx); 1799 per_pin->pcm_idx = pin_idx; 1800 } 1801 per_pin->pin_nid = pin_nid; 1802 per_pin->pin_nid_idx = spec->num_nids; 1803 per_pin->dev_id = i; 1804 per_pin->non_pcm = false; 1805 snd_hda_set_dev_select(codec, pin_nid, i); 1806 err = hdmi_read_pin_conn(codec, pin_idx); 1807 if (err < 0) 1808 return err; 1809 spec->num_pins++; 1810 } 1811 spec->num_nids++; 1812 1813 return 0; 1814 } 1815 1816 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1817 { 1818 struct hdmi_spec *spec = codec->spec; 1819 struct hdmi_spec_per_cvt *per_cvt; 1820 unsigned int chans; 1821 int err; 1822 1823 chans = get_wcaps(codec, cvt_nid); 1824 chans = get_wcaps_channels(chans); 1825 1826 per_cvt = snd_array_new(&spec->cvts); 1827 if (!per_cvt) 1828 return -ENOMEM; 1829 1830 per_cvt->cvt_nid = cvt_nid; 1831 per_cvt->channels_min = 2; 1832 if (chans <= 16) { 1833 per_cvt->channels_max = chans; 1834 if (chans > spec->chmap.channels_max) 1835 spec->chmap.channels_max = chans; 1836 } 1837 1838 err = snd_hda_query_supported_pcm(codec, cvt_nid, 1839 &per_cvt->rates, 1840 &per_cvt->formats, 1841 &per_cvt->maxbps); 1842 if (err < 0) 1843 return err; 1844 1845 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) 1846 spec->cvt_nids[spec->num_cvts] = cvt_nid; 1847 spec->num_cvts++; 1848 1849 return 0; 1850 } 1851 1852 static int hdmi_parse_codec(struct hda_codec *codec) 1853 { 1854 hda_nid_t nid; 1855 int i, nodes; 1856 1857 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid); 1858 if (!nid || nodes < 0) { 1859 codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); 1860 return -EINVAL; 1861 } 1862 1863 for (i = 0; i < nodes; i++, nid++) { 1864 unsigned int caps; 1865 unsigned int type; 1866 1867 caps = get_wcaps(codec, nid); 1868 type = get_wcaps_type(caps); 1869 1870 if (!(caps & AC_WCAP_DIGITAL)) 1871 continue; 1872 1873 switch (type) { 1874 case AC_WID_AUD_OUT: 1875 hdmi_add_cvt(codec, nid); 1876 break; 1877 case AC_WID_PIN: 1878 hdmi_add_pin(codec, nid); 1879 break; 1880 } 1881 } 1882 1883 return 0; 1884 } 1885 1886 /* 1887 */ 1888 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1889 { 1890 struct hda_spdif_out *spdif; 1891 bool non_pcm; 1892 1893 mutex_lock(&codec->spdif_mutex); 1894 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); 1895 /* Add sanity check to pass klockwork check. 1896 * This should never happen. 1897 */ 1898 if (WARN_ON(spdif == NULL)) 1899 return true; 1900 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); 1901 mutex_unlock(&codec->spdif_mutex); 1902 return non_pcm; 1903 } 1904 1905 /* 1906 * HDMI callbacks 1907 */ 1908 1909 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 1910 struct hda_codec *codec, 1911 unsigned int stream_tag, 1912 unsigned int format, 1913 struct snd_pcm_substream *substream) 1914 { 1915 hda_nid_t cvt_nid = hinfo->nid; 1916 struct hdmi_spec *spec = codec->spec; 1917 int pin_idx; 1918 struct hdmi_spec_per_pin *per_pin; 1919 struct snd_pcm_runtime *runtime = substream->runtime; 1920 bool non_pcm; 1921 int pinctl, stripe; 1922 int err = 0; 1923 1924 mutex_lock(&spec->pcm_lock); 1925 pin_idx = hinfo_to_pin_index(codec, hinfo); 1926 if (spec->dyn_pcm_assign && pin_idx < 0) { 1927 /* when dyn_pcm_assign and pcm is not bound to a pin 1928 * skip pin setup and return 0 to make audio playback 1929 * be ongoing 1930 */ 1931 pin_cvt_fixup(codec, NULL, cvt_nid); 1932 snd_hda_codec_setup_stream(codec, cvt_nid, 1933 stream_tag, 0, format); 1934 goto unlock; 1935 } 1936 1937 if (snd_BUG_ON(pin_idx < 0)) { 1938 err = -EINVAL; 1939 goto unlock; 1940 } 1941 per_pin = get_pin(spec, pin_idx); 1942 1943 /* Verify pin:cvt selections to avoid silent audio after S3. 1944 * After S3, the audio driver restores pin:cvt selections 1945 * but this can happen before gfx is ready and such selection 1946 * is overlooked by HW. Thus multiple pins can share a same 1947 * default convertor and mute control will affect each other, 1948 * which can cause a resumed audio playback become silent 1949 * after S3. 1950 */ 1951 pin_cvt_fixup(codec, per_pin, 0); 1952 1953 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ 1954 /* Todo: add DP1.2 MST audio support later */ 1955 if (codec_has_acomp(codec)) 1956 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, 1957 per_pin->dev_id, runtime->rate); 1958 1959 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); 1960 mutex_lock(&per_pin->lock); 1961 per_pin->channels = substream->runtime->channels; 1962 per_pin->setup = true; 1963 1964 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) { 1965 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core, 1966 substream); 1967 snd_hda_codec_write(codec, cvt_nid, 0, 1968 AC_VERB_SET_STRIPE_CONTROL, 1969 stripe); 1970 } 1971 1972 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1973 mutex_unlock(&per_pin->lock); 1974 if (spec->dyn_pin_out) { 1975 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1976 per_pin->dev_id); 1977 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 1978 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 1979 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 1980 AC_VERB_SET_PIN_WIDGET_CONTROL, 1981 pinctl | PIN_OUT); 1982 } 1983 1984 /* snd_hda_set_dev_select() has been called before */ 1985 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid, 1986 per_pin->dev_id, stream_tag, format); 1987 unlock: 1988 mutex_unlock(&spec->pcm_lock); 1989 return err; 1990 } 1991 1992 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 1993 struct hda_codec *codec, 1994 struct snd_pcm_substream *substream) 1995 { 1996 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 1997 return 0; 1998 } 1999 2000 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, 2001 struct hda_codec *codec, 2002 struct snd_pcm_substream *substream) 2003 { 2004 struct hdmi_spec *spec = codec->spec; 2005 int cvt_idx, pin_idx, pcm_idx; 2006 struct hdmi_spec_per_cvt *per_cvt; 2007 struct hdmi_spec_per_pin *per_pin; 2008 int pinctl; 2009 int err = 0; 2010 2011 if (hinfo->nid) { 2012 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 2013 if (snd_BUG_ON(pcm_idx < 0)) 2014 return -EINVAL; 2015 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); 2016 if (snd_BUG_ON(cvt_idx < 0)) 2017 return -EINVAL; 2018 per_cvt = get_cvt(spec, cvt_idx); 2019 2020 snd_BUG_ON(!per_cvt->assigned); 2021 per_cvt->assigned = 0; 2022 hinfo->nid = 0; 2023 2024 azx_stream(get_azx_dev(substream))->stripe = 0; 2025 2026 mutex_lock(&spec->pcm_lock); 2027 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2028 clear_bit(pcm_idx, &spec->pcm_in_use); 2029 pin_idx = hinfo_to_pin_index(codec, hinfo); 2030 if (spec->dyn_pcm_assign && pin_idx < 0) 2031 goto unlock; 2032 2033 if (snd_BUG_ON(pin_idx < 0)) { 2034 err = -EINVAL; 2035 goto unlock; 2036 } 2037 per_pin = get_pin(spec, pin_idx); 2038 2039 if (spec->dyn_pin_out) { 2040 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2041 per_pin->dev_id); 2042 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2043 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2044 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2045 AC_VERB_SET_PIN_WIDGET_CONTROL, 2046 pinctl & ~PIN_OUT); 2047 } 2048 2049 mutex_lock(&per_pin->lock); 2050 per_pin->chmap_set = false; 2051 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 2052 2053 per_pin->setup = false; 2054 per_pin->channels = 0; 2055 mutex_unlock(&per_pin->lock); 2056 unlock: 2057 mutex_unlock(&spec->pcm_lock); 2058 } 2059 2060 return err; 2061 } 2062 2063 static const struct hda_pcm_ops generic_ops = { 2064 .open = hdmi_pcm_open, 2065 .close = hdmi_pcm_close, 2066 .prepare = generic_hdmi_playback_pcm_prepare, 2067 .cleanup = generic_hdmi_playback_pcm_cleanup, 2068 }; 2069 2070 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) 2071 { 2072 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2073 struct hdmi_spec *spec = codec->spec; 2074 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2075 2076 if (!per_pin) 2077 return 0; 2078 2079 return per_pin->sink_eld.info.spk_alloc; 2080 } 2081 2082 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, 2083 unsigned char *chmap) 2084 { 2085 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2086 struct hdmi_spec *spec = codec->spec; 2087 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2088 2089 /* chmap is already set to 0 in caller */ 2090 if (!per_pin) 2091 return; 2092 2093 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); 2094 } 2095 2096 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, 2097 unsigned char *chmap, int prepared) 2098 { 2099 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2100 struct hdmi_spec *spec = codec->spec; 2101 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2102 2103 if (!per_pin) 2104 return; 2105 mutex_lock(&per_pin->lock); 2106 per_pin->chmap_set = true; 2107 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); 2108 if (prepared) 2109 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 2110 mutex_unlock(&per_pin->lock); 2111 } 2112 2113 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) 2114 { 2115 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2116 struct hdmi_spec *spec = codec->spec; 2117 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2118 2119 return per_pin ? true:false; 2120 } 2121 2122 static int generic_hdmi_build_pcms(struct hda_codec *codec) 2123 { 2124 struct hdmi_spec *spec = codec->spec; 2125 int idx, pcm_num; 2126 2127 /* 2128 * for non-mst mode, pcm number is the same as before 2129 * for DP MST mode without extra PCM, pcm number is same 2130 * for DP MST mode with extra PCMs, pcm number is 2131 * (nid number + dev_num - 1) 2132 * dev_num is the device entry number in a pin 2133 */ 2134 2135 if (codec->mst_no_extra_pcms) 2136 pcm_num = spec->num_nids; 2137 else 2138 pcm_num = spec->num_nids + spec->dev_num - 1; 2139 2140 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num); 2141 2142 for (idx = 0; idx < pcm_num; idx++) { 2143 struct hda_pcm *info; 2144 struct hda_pcm_stream *pstr; 2145 2146 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); 2147 if (!info) 2148 return -ENOMEM; 2149 2150 spec->pcm_rec[idx].pcm = info; 2151 spec->pcm_used++; 2152 info->pcm_type = HDA_PCM_TYPE_HDMI; 2153 info->own_chmap = true; 2154 2155 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2156 pstr->substreams = 1; 2157 pstr->ops = generic_ops; 2158 /* pcm number is less than 16 */ 2159 if (spec->pcm_used >= 16) 2160 break; 2161 /* other pstr fields are set in open */ 2162 } 2163 2164 return 0; 2165 } 2166 2167 static void free_hdmi_jack_priv(struct snd_jack *jack) 2168 { 2169 struct hdmi_pcm *pcm = jack->private_data; 2170 2171 pcm->jack = NULL; 2172 } 2173 2174 static int add_hdmi_jack_kctl(struct hda_codec *codec, 2175 struct hdmi_spec *spec, 2176 int pcm_idx, 2177 const char *name) 2178 { 2179 struct snd_jack *jack; 2180 int err; 2181 2182 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack, 2183 true, false); 2184 if (err < 0) 2185 return err; 2186 2187 spec->pcm_rec[pcm_idx].jack = jack; 2188 jack->private_data = &spec->pcm_rec[pcm_idx]; 2189 jack->private_free = free_hdmi_jack_priv; 2190 return 0; 2191 } 2192 2193 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) 2194 { 2195 char hdmi_str[32] = "HDMI/DP"; 2196 struct hdmi_spec *spec = codec->spec; 2197 struct hdmi_spec_per_pin *per_pin; 2198 struct hda_jack_tbl *jack; 2199 int pcmdev = get_pcm_rec(spec, pcm_idx)->device; 2200 bool phantom_jack; 2201 int ret; 2202 2203 if (pcmdev > 0) 2204 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); 2205 2206 if (spec->dyn_pcm_assign) 2207 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str); 2208 2209 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */ 2210 /* if !dyn_pcm_assign, it must be non-MST mode. 2211 * This means pcms and pins are statically mapped. 2212 * And pcm_idx is pin_idx. 2213 */ 2214 per_pin = get_pin(spec, pcm_idx); 2215 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid); 2216 if (phantom_jack) 2217 strncat(hdmi_str, " Phantom", 2218 sizeof(hdmi_str) - strlen(hdmi_str) - 1); 2219 ret = snd_hda_jack_add_kctl_mst(codec, per_pin->pin_nid, 2220 per_pin->dev_id, hdmi_str, phantom_jack, 2221 0, NULL); 2222 if (ret < 0) 2223 return ret; 2224 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid, 2225 per_pin->dev_id); 2226 if (jack == NULL) 2227 return 0; 2228 /* assign jack->jack to pcm_rec[].jack to 2229 * align with dyn_pcm_assign mode 2230 */ 2231 spec->pcm_rec[pcm_idx].jack = jack->jack; 2232 return 0; 2233 } 2234 2235 static int generic_hdmi_build_controls(struct hda_codec *codec) 2236 { 2237 struct hdmi_spec *spec = codec->spec; 2238 int dev, err; 2239 int pin_idx, pcm_idx; 2240 2241 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2242 if (!get_pcm_rec(spec, pcm_idx)->pcm) { 2243 /* no PCM: mark this for skipping permanently */ 2244 set_bit(pcm_idx, &spec->pcm_bitmap); 2245 continue; 2246 } 2247 2248 err = generic_hdmi_build_jack(codec, pcm_idx); 2249 if (err < 0) 2250 return err; 2251 2252 /* create the spdif for each pcm 2253 * pin will be bound when monitor is connected 2254 */ 2255 if (spec->dyn_pcm_assign) 2256 err = snd_hda_create_dig_out_ctls(codec, 2257 0, spec->cvt_nids[0], 2258 HDA_PCM_TYPE_HDMI); 2259 else { 2260 struct hdmi_spec_per_pin *per_pin = 2261 get_pin(spec, pcm_idx); 2262 err = snd_hda_create_dig_out_ctls(codec, 2263 per_pin->pin_nid, 2264 per_pin->mux_nids[0], 2265 HDA_PCM_TYPE_HDMI); 2266 } 2267 if (err < 0) 2268 return err; 2269 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2270 2271 dev = get_pcm_rec(spec, pcm_idx)->device; 2272 if (dev != SNDRV_PCM_INVALID_DEVICE) { 2273 /* add control for ELD Bytes */ 2274 err = hdmi_create_eld_ctl(codec, pcm_idx, dev); 2275 if (err < 0) 2276 return err; 2277 } 2278 } 2279 2280 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2281 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2282 2283 hdmi_present_sense(per_pin, 0); 2284 } 2285 2286 /* add channel maps */ 2287 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2288 struct hda_pcm *pcm; 2289 2290 pcm = get_pcm_rec(spec, pcm_idx); 2291 if (!pcm || !pcm->pcm) 2292 break; 2293 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); 2294 if (err < 0) 2295 return err; 2296 } 2297 2298 return 0; 2299 } 2300 2301 static int generic_hdmi_init_per_pins(struct hda_codec *codec) 2302 { 2303 struct hdmi_spec *spec = codec->spec; 2304 int pin_idx; 2305 2306 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2307 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2308 2309 per_pin->codec = codec; 2310 mutex_init(&per_pin->lock); 2311 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); 2312 eld_proc_new(per_pin, pin_idx); 2313 } 2314 return 0; 2315 } 2316 2317 static int generic_hdmi_init(struct hda_codec *codec) 2318 { 2319 struct hdmi_spec *spec = codec->spec; 2320 int pin_idx; 2321 2322 mutex_lock(&spec->bind_lock); 2323 spec->use_jack_detect = !codec->jackpoll_interval; 2324 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2325 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2326 hda_nid_t pin_nid = per_pin->pin_nid; 2327 int dev_id = per_pin->dev_id; 2328 2329 snd_hda_set_dev_select(codec, pin_nid, dev_id); 2330 hdmi_init_pin(codec, pin_nid); 2331 if (codec_has_acomp(codec)) 2332 continue; 2333 if (spec->use_jack_detect) 2334 snd_hda_jack_detect_enable(codec, pin_nid, dev_id); 2335 else 2336 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, 2337 dev_id, 2338 jack_callback); 2339 } 2340 mutex_unlock(&spec->bind_lock); 2341 return 0; 2342 } 2343 2344 static void hdmi_array_init(struct hdmi_spec *spec, int nums) 2345 { 2346 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); 2347 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); 2348 } 2349 2350 static void hdmi_array_free(struct hdmi_spec *spec) 2351 { 2352 snd_array_free(&spec->pins); 2353 snd_array_free(&spec->cvts); 2354 } 2355 2356 static void generic_spec_free(struct hda_codec *codec) 2357 { 2358 struct hdmi_spec *spec = codec->spec; 2359 2360 if (spec) { 2361 hdmi_array_free(spec); 2362 kfree(spec); 2363 codec->spec = NULL; 2364 } 2365 codec->dp_mst = false; 2366 } 2367 2368 static void generic_hdmi_free(struct hda_codec *codec) 2369 { 2370 struct hdmi_spec *spec = codec->spec; 2371 int pin_idx, pcm_idx; 2372 2373 if (spec->acomp_registered) { 2374 snd_hdac_acomp_exit(&codec->bus->core); 2375 } else if (codec_has_acomp(codec)) { 2376 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL); 2377 } 2378 codec->relaxed_resume = 0; 2379 2380 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2381 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2382 cancel_delayed_work_sync(&per_pin->work); 2383 eld_proc_free(per_pin); 2384 } 2385 2386 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2387 if (spec->pcm_rec[pcm_idx].jack == NULL) 2388 continue; 2389 if (spec->dyn_pcm_assign) 2390 snd_device_free(codec->card, 2391 spec->pcm_rec[pcm_idx].jack); 2392 else 2393 spec->pcm_rec[pcm_idx].jack = NULL; 2394 } 2395 2396 generic_spec_free(codec); 2397 } 2398 2399 #ifdef CONFIG_PM 2400 static int generic_hdmi_resume(struct hda_codec *codec) 2401 { 2402 struct hdmi_spec *spec = codec->spec; 2403 int pin_idx; 2404 2405 codec->patch_ops.init(codec); 2406 regcache_sync(codec->core.regmap); 2407 2408 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2409 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2410 hdmi_present_sense(per_pin, 1); 2411 } 2412 return 0; 2413 } 2414 #endif 2415 2416 static const struct hda_codec_ops generic_hdmi_patch_ops = { 2417 .init = generic_hdmi_init, 2418 .free = generic_hdmi_free, 2419 .build_pcms = generic_hdmi_build_pcms, 2420 .build_controls = generic_hdmi_build_controls, 2421 .unsol_event = hdmi_unsol_event, 2422 #ifdef CONFIG_PM 2423 .resume = generic_hdmi_resume, 2424 #endif 2425 }; 2426 2427 static const struct hdmi_ops generic_standard_hdmi_ops = { 2428 .pin_get_eld = hdmi_pin_get_eld, 2429 .pin_setup_infoframe = hdmi_pin_setup_infoframe, 2430 .pin_hbr_setup = hdmi_pin_hbr_setup, 2431 .setup_stream = hdmi_setup_stream, 2432 }; 2433 2434 /* allocate codec->spec and assign/initialize generic parser ops */ 2435 static int alloc_generic_hdmi(struct hda_codec *codec) 2436 { 2437 struct hdmi_spec *spec; 2438 2439 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2440 if (!spec) 2441 return -ENOMEM; 2442 2443 spec->codec = codec; 2444 spec->ops = generic_standard_hdmi_ops; 2445 spec->dev_num = 1; /* initialize to 1 */ 2446 mutex_init(&spec->pcm_lock); 2447 mutex_init(&spec->bind_lock); 2448 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); 2449 2450 spec->chmap.ops.get_chmap = hdmi_get_chmap; 2451 spec->chmap.ops.set_chmap = hdmi_set_chmap; 2452 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; 2453 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc, 2454 2455 codec->spec = spec; 2456 hdmi_array_init(spec, 4); 2457 2458 codec->patch_ops = generic_hdmi_patch_ops; 2459 2460 return 0; 2461 } 2462 2463 /* generic HDMI parser */ 2464 static int patch_generic_hdmi(struct hda_codec *codec) 2465 { 2466 int err; 2467 2468 err = alloc_generic_hdmi(codec); 2469 if (err < 0) 2470 return err; 2471 2472 err = hdmi_parse_codec(codec); 2473 if (err < 0) { 2474 generic_spec_free(codec); 2475 return err; 2476 } 2477 2478 generic_hdmi_init_per_pins(codec); 2479 return 0; 2480 } 2481 2482 /* 2483 * generic audio component binding 2484 */ 2485 2486 /* turn on / off the unsol event jack detection dynamically */ 2487 static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid, 2488 int dev_id, bool use_acomp) 2489 { 2490 struct hda_jack_tbl *tbl; 2491 2492 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id); 2493 if (tbl) { 2494 /* clear unsol even if component notifier is used, or re-enable 2495 * if notifier is cleared 2496 */ 2497 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag); 2498 snd_hda_codec_write_cache(codec, nid, 0, 2499 AC_VERB_SET_UNSOLICITED_ENABLE, val); 2500 } else { 2501 /* if no jack entry was defined beforehand, create a new one 2502 * at need (i.e. only when notifier is cleared) 2503 */ 2504 if (!use_acomp) 2505 snd_hda_jack_detect_enable(codec, nid, dev_id); 2506 } 2507 } 2508 2509 /* set up / clear component notifier dynamically */ 2510 static void generic_acomp_notifier_set(struct drm_audio_component *acomp, 2511 bool use_acomp) 2512 { 2513 struct hdmi_spec *spec; 2514 int i; 2515 2516 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops); 2517 mutex_lock(&spec->bind_lock); 2518 spec->use_acomp_notifier = use_acomp; 2519 spec->codec->relaxed_resume = use_acomp; 2520 /* reprogram each jack detection logic depending on the notifier */ 2521 if (spec->use_jack_detect) { 2522 for (i = 0; i < spec->num_pins; i++) 2523 reprogram_jack_detect(spec->codec, 2524 get_pin(spec, i)->pin_nid, 2525 get_pin(spec, i)->dev_id, 2526 use_acomp); 2527 } 2528 mutex_unlock(&spec->bind_lock); 2529 } 2530 2531 /* enable / disable the notifier via master bind / unbind */ 2532 static int generic_acomp_master_bind(struct device *dev, 2533 struct drm_audio_component *acomp) 2534 { 2535 generic_acomp_notifier_set(acomp, true); 2536 return 0; 2537 } 2538 2539 static void generic_acomp_master_unbind(struct device *dev, 2540 struct drm_audio_component *acomp) 2541 { 2542 generic_acomp_notifier_set(acomp, false); 2543 } 2544 2545 /* check whether both HD-audio and DRM PCI devices belong to the same bus */ 2546 static int match_bound_vga(struct device *dev, int subtype, void *data) 2547 { 2548 struct hdac_bus *bus = data; 2549 struct pci_dev *pci, *master; 2550 2551 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev)) 2552 return 0; 2553 master = to_pci_dev(bus->dev); 2554 pci = to_pci_dev(dev); 2555 return master->bus == pci->bus; 2556 } 2557 2558 /* audio component notifier for AMD/Nvidia HDMI codecs */ 2559 static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id) 2560 { 2561 struct hda_codec *codec = audio_ptr; 2562 struct hdmi_spec *spec = codec->spec; 2563 hda_nid_t pin_nid = spec->port2pin(codec, port); 2564 2565 if (!pin_nid) 2566 return; 2567 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN) 2568 return; 2569 /* skip notification during system suspend (but not in runtime PM); 2570 * the state will be updated at resume 2571 */ 2572 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) 2573 return; 2574 /* ditto during suspend/resume process itself */ 2575 if (snd_hdac_is_in_pm(&codec->core)) 2576 return; 2577 2578 check_presence_and_report(codec, pin_nid, dev_id); 2579 } 2580 2581 /* set up the private drm_audio_ops from the template */ 2582 static void setup_drm_audio_ops(struct hda_codec *codec, 2583 const struct drm_audio_component_audio_ops *ops) 2584 { 2585 struct hdmi_spec *spec = codec->spec; 2586 2587 spec->drm_audio_ops.audio_ptr = codec; 2588 /* intel_audio_codec_enable() or intel_audio_codec_disable() 2589 * will call pin_eld_notify with using audio_ptr pointer 2590 * We need make sure audio_ptr is really setup 2591 */ 2592 wmb(); 2593 spec->drm_audio_ops.pin2port = ops->pin2port; 2594 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify; 2595 spec->drm_audio_ops.master_bind = ops->master_bind; 2596 spec->drm_audio_ops.master_unbind = ops->master_unbind; 2597 } 2598 2599 /* initialize the generic HDMI audio component */ 2600 static void generic_acomp_init(struct hda_codec *codec, 2601 const struct drm_audio_component_audio_ops *ops, 2602 int (*port2pin)(struct hda_codec *, int)) 2603 { 2604 struct hdmi_spec *spec = codec->spec; 2605 2606 spec->port2pin = port2pin; 2607 setup_drm_audio_ops(codec, ops); 2608 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops, 2609 match_bound_vga, 0)) { 2610 spec->acomp_registered = true; 2611 codec->bus->keep_power = 0; 2612 } 2613 } 2614 2615 /* 2616 * Intel codec parsers and helpers 2617 */ 2618 2619 #define INTEL_GET_VENDOR_VERB 0xf81 2620 #define INTEL_SET_VENDOR_VERB 0x781 2621 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ 2622 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ 2623 2624 static void intel_haswell_enable_all_pins(struct hda_codec *codec, 2625 bool update_tree) 2626 { 2627 unsigned int vendor_param; 2628 struct hdmi_spec *spec = codec->spec; 2629 2630 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2631 INTEL_GET_VENDOR_VERB, 0); 2632 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) 2633 return; 2634 2635 vendor_param |= INTEL_EN_ALL_PIN_CVTS; 2636 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2637 INTEL_SET_VENDOR_VERB, vendor_param); 2638 if (vendor_param == -1) 2639 return; 2640 2641 if (update_tree) 2642 snd_hda_codec_update_widgets(codec); 2643 } 2644 2645 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) 2646 { 2647 unsigned int vendor_param; 2648 struct hdmi_spec *spec = codec->spec; 2649 2650 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2651 INTEL_GET_VENDOR_VERB, 0); 2652 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) 2653 return; 2654 2655 /* enable DP1.2 mode */ 2656 vendor_param |= INTEL_EN_DP12; 2657 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); 2658 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, 2659 INTEL_SET_VENDOR_VERB, vendor_param); 2660 } 2661 2662 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. 2663 * Otherwise you may get severe h/w communication errors. 2664 */ 2665 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, 2666 unsigned int power_state) 2667 { 2668 if (power_state == AC_PWRST_D0) { 2669 intel_haswell_enable_all_pins(codec, false); 2670 intel_haswell_fixup_enable_dp12(codec); 2671 } 2672 2673 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); 2674 snd_hda_codec_set_power_to_all(codec, fg, power_state); 2675 } 2676 2677 /* There is a fixed mapping between audio pin node and display port. 2678 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL: 2679 * Pin Widget 5 - PORT B (port = 1 in i915 driver) 2680 * Pin Widget 6 - PORT C (port = 2 in i915 driver) 2681 * Pin Widget 7 - PORT D (port = 3 in i915 driver) 2682 * 2683 * on VLV, ILK: 2684 * Pin Widget 4 - PORT B (port = 1 in i915 driver) 2685 * Pin Widget 5 - PORT C (port = 2 in i915 driver) 2686 * Pin Widget 6 - PORT D (port = 3 in i915 driver) 2687 */ 2688 static int intel_base_nid(struct hda_codec *codec) 2689 { 2690 switch (codec->core.vendor_id) { 2691 case 0x80860054: /* ILK */ 2692 case 0x80862804: /* ILK */ 2693 case 0x80862882: /* VLV */ 2694 return 4; 2695 default: 2696 return 5; 2697 } 2698 } 2699 2700 static int intel_pin2port(void *audio_ptr, int pin_nid) 2701 { 2702 struct hda_codec *codec = audio_ptr; 2703 struct hdmi_spec *spec = codec->spec; 2704 int base_nid, i; 2705 2706 if (!spec->port_num) { 2707 base_nid = intel_base_nid(codec); 2708 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3)) 2709 return -1; 2710 return pin_nid - base_nid + 1; 2711 } 2712 2713 /* 2714 * looking for the pin number in the mapping table and return 2715 * the index which indicate the port number 2716 */ 2717 for (i = 0; i < spec->port_num; i++) { 2718 if (pin_nid == spec->port_map[i]) 2719 return i; 2720 } 2721 2722 codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid); 2723 return -1; 2724 } 2725 2726 static int intel_port2pin(struct hda_codec *codec, int port) 2727 { 2728 struct hdmi_spec *spec = codec->spec; 2729 2730 if (!spec->port_num) { 2731 /* we assume only from port-B to port-D */ 2732 if (port < 1 || port > 3) 2733 return 0; 2734 return port + intel_base_nid(codec) - 1; 2735 } 2736 2737 if (port < 0 || port >= spec->port_num) 2738 return 0; 2739 return spec->port_map[port]; 2740 } 2741 2742 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) 2743 { 2744 struct hda_codec *codec = audio_ptr; 2745 int pin_nid; 2746 int dev_id = pipe; 2747 2748 pin_nid = intel_port2pin(codec, port); 2749 if (!pin_nid) 2750 return; 2751 /* skip notification during system suspend (but not in runtime PM); 2752 * the state will be updated at resume 2753 */ 2754 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) 2755 return; 2756 /* ditto during suspend/resume process itself */ 2757 if (snd_hdac_is_in_pm(&codec->core)) 2758 return; 2759 2760 snd_hdac_i915_set_bclk(&codec->bus->core); 2761 check_presence_and_report(codec, pin_nid, dev_id); 2762 } 2763 2764 static const struct drm_audio_component_audio_ops intel_audio_ops = { 2765 .pin2port = intel_pin2port, 2766 .pin_eld_notify = intel_pin_eld_notify, 2767 }; 2768 2769 /* register i915 component pin_eld_notify callback */ 2770 static void register_i915_notifier(struct hda_codec *codec) 2771 { 2772 struct hdmi_spec *spec = codec->spec; 2773 2774 spec->use_acomp_notifier = true; 2775 spec->port2pin = intel_port2pin; 2776 setup_drm_audio_ops(codec, &intel_audio_ops); 2777 snd_hdac_acomp_register_notifier(&codec->bus->core, 2778 &spec->drm_audio_ops); 2779 /* no need for forcible resume for jack check thanks to notifier */ 2780 codec->relaxed_resume = 1; 2781 } 2782 2783 /* setup_stream ops override for HSW+ */ 2784 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 2785 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 2786 int format) 2787 { 2788 haswell_verify_D0(codec, cvt_nid, pin_nid); 2789 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 2790 stream_tag, format); 2791 } 2792 2793 /* pin_cvt_fixup ops override for HSW+ and VLV+ */ 2794 static void i915_pin_cvt_fixup(struct hda_codec *codec, 2795 struct hdmi_spec_per_pin *per_pin, 2796 hda_nid_t cvt_nid) 2797 { 2798 if (per_pin) { 2799 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2800 per_pin->dev_id); 2801 intel_verify_pin_cvt_connect(codec, per_pin); 2802 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, 2803 per_pin->dev_id, per_pin->mux_idx); 2804 } else { 2805 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); 2806 } 2807 } 2808 2809 /* precondition and allocation for Intel codecs */ 2810 static int alloc_intel_hdmi(struct hda_codec *codec) 2811 { 2812 int err; 2813 2814 /* requires i915 binding */ 2815 if (!codec->bus->core.audio_component) { 2816 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); 2817 /* set probe_id here to prevent generic fallback binding */ 2818 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE; 2819 return -ENODEV; 2820 } 2821 2822 err = alloc_generic_hdmi(codec); 2823 if (err < 0) 2824 return err; 2825 /* no need to handle unsol events */ 2826 codec->patch_ops.unsol_event = NULL; 2827 return 0; 2828 } 2829 2830 /* parse and post-process for Intel codecs */ 2831 static int parse_intel_hdmi(struct hda_codec *codec) 2832 { 2833 int err; 2834 2835 err = hdmi_parse_codec(codec); 2836 if (err < 0) { 2837 generic_spec_free(codec); 2838 return err; 2839 } 2840 2841 generic_hdmi_init_per_pins(codec); 2842 register_i915_notifier(codec); 2843 return 0; 2844 } 2845 2846 /* Intel Haswell and onwards; audio component with eld notifier */ 2847 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid, 2848 const int *port_map, int port_num) 2849 { 2850 struct hdmi_spec *spec; 2851 int err; 2852 2853 err = alloc_intel_hdmi(codec); 2854 if (err < 0) 2855 return err; 2856 spec = codec->spec; 2857 codec->dp_mst = true; 2858 spec->dyn_pcm_assign = true; 2859 spec->vendor_nid = vendor_nid; 2860 spec->port_map = port_map; 2861 spec->port_num = port_num; 2862 spec->intel_hsw_fixup = true; 2863 2864 intel_haswell_enable_all_pins(codec, true); 2865 intel_haswell_fixup_enable_dp12(codec); 2866 2867 codec->display_power_control = 1; 2868 2869 codec->patch_ops.set_power_state = haswell_set_power_state; 2870 codec->depop_delay = 0; 2871 codec->auto_runtime_pm = 1; 2872 2873 spec->ops.setup_stream = i915_hsw_setup_stream; 2874 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2875 2876 return parse_intel_hdmi(codec); 2877 } 2878 2879 static int patch_i915_hsw_hdmi(struct hda_codec *codec) 2880 { 2881 return intel_hsw_common_init(codec, 0x08, NULL, 0); 2882 } 2883 2884 static int patch_i915_glk_hdmi(struct hda_codec *codec) 2885 { 2886 return intel_hsw_common_init(codec, 0x0b, NULL, 0); 2887 } 2888 2889 static int patch_i915_icl_hdmi(struct hda_codec *codec) 2890 { 2891 /* 2892 * pin to port mapping table where the value indicate the pin number and 2893 * the index indicate the port number. 2894 */ 2895 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb}; 2896 2897 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map)); 2898 } 2899 2900 static int patch_i915_tgl_hdmi(struct hda_codec *codec) 2901 { 2902 /* 2903 * pin to port mapping table where the value indicate the pin number and 2904 * the index indicate the port number. 2905 */ 2906 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf}; 2907 2908 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map)); 2909 } 2910 2911 /* Intel Baytrail and Braswell; with eld notifier */ 2912 static int patch_i915_byt_hdmi(struct hda_codec *codec) 2913 { 2914 struct hdmi_spec *spec; 2915 int err; 2916 2917 err = alloc_intel_hdmi(codec); 2918 if (err < 0) 2919 return err; 2920 spec = codec->spec; 2921 2922 /* For Valleyview/Cherryview, only the display codec is in the display 2923 * power well and can use link_power ops to request/release the power. 2924 */ 2925 codec->display_power_control = 1; 2926 2927 codec->depop_delay = 0; 2928 codec->auto_runtime_pm = 1; 2929 2930 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2931 2932 return parse_intel_hdmi(codec); 2933 } 2934 2935 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ 2936 static int patch_i915_cpt_hdmi(struct hda_codec *codec) 2937 { 2938 int err; 2939 2940 err = alloc_intel_hdmi(codec); 2941 if (err < 0) 2942 return err; 2943 return parse_intel_hdmi(codec); 2944 } 2945 2946 /* 2947 * Shared non-generic implementations 2948 */ 2949 2950 static int simple_playback_build_pcms(struct hda_codec *codec) 2951 { 2952 struct hdmi_spec *spec = codec->spec; 2953 struct hda_pcm *info; 2954 unsigned int chans; 2955 struct hda_pcm_stream *pstr; 2956 struct hdmi_spec_per_cvt *per_cvt; 2957 2958 per_cvt = get_cvt(spec, 0); 2959 chans = get_wcaps(codec, per_cvt->cvt_nid); 2960 chans = get_wcaps_channels(chans); 2961 2962 info = snd_hda_codec_pcm_new(codec, "HDMI 0"); 2963 if (!info) 2964 return -ENOMEM; 2965 spec->pcm_rec[0].pcm = info; 2966 info->pcm_type = HDA_PCM_TYPE_HDMI; 2967 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2968 *pstr = spec->pcm_playback; 2969 pstr->nid = per_cvt->cvt_nid; 2970 if (pstr->channels_max <= 2 && chans && chans <= 16) 2971 pstr->channels_max = chans; 2972 2973 return 0; 2974 } 2975 2976 /* unsolicited event for jack sensing */ 2977 static void simple_hdmi_unsol_event(struct hda_codec *codec, 2978 unsigned int res) 2979 { 2980 snd_hda_jack_set_dirty_all(codec); 2981 snd_hda_jack_report_sync(codec); 2982 } 2983 2984 /* generic_hdmi_build_jack can be used for simple_hdmi, too, 2985 * as long as spec->pins[] is set correctly 2986 */ 2987 #define simple_hdmi_build_jack generic_hdmi_build_jack 2988 2989 static int simple_playback_build_controls(struct hda_codec *codec) 2990 { 2991 struct hdmi_spec *spec = codec->spec; 2992 struct hdmi_spec_per_cvt *per_cvt; 2993 int err; 2994 2995 per_cvt = get_cvt(spec, 0); 2996 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, 2997 per_cvt->cvt_nid, 2998 HDA_PCM_TYPE_HDMI); 2999 if (err < 0) 3000 return err; 3001 return simple_hdmi_build_jack(codec, 0); 3002 } 3003 3004 static int simple_playback_init(struct hda_codec *codec) 3005 { 3006 struct hdmi_spec *spec = codec->spec; 3007 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); 3008 hda_nid_t pin = per_pin->pin_nid; 3009 3010 snd_hda_codec_write(codec, pin, 0, 3011 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); 3012 /* some codecs require to unmute the pin */ 3013 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 3014 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, 3015 AMP_OUT_UNMUTE); 3016 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id); 3017 return 0; 3018 } 3019 3020 static void simple_playback_free(struct hda_codec *codec) 3021 { 3022 struct hdmi_spec *spec = codec->spec; 3023 3024 hdmi_array_free(spec); 3025 kfree(spec); 3026 } 3027 3028 /* 3029 * Nvidia specific implementations 3030 */ 3031 3032 #define Nv_VERB_SET_Channel_Allocation 0xF79 3033 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A 3034 #define Nv_VERB_SET_Audio_Protection_On 0xF98 3035 #define Nv_VERB_SET_Audio_Protection_Off 0xF99 3036 3037 #define nvhdmi_master_con_nid_7x 0x04 3038 #define nvhdmi_master_pin_nid_7x 0x05 3039 3040 static const hda_nid_t nvhdmi_con_nids_7x[4] = { 3041 /*front, rear, clfe, rear_surr */ 3042 0x6, 0x8, 0xa, 0xc, 3043 }; 3044 3045 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { 3046 /* set audio protect on */ 3047 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3048 /* enable digital output on pin widget */ 3049 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3050 {} /* terminator */ 3051 }; 3052 3053 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { 3054 /* set audio protect on */ 3055 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3056 /* enable digital output on pin widget */ 3057 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3058 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3059 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3060 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3061 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3062 {} /* terminator */ 3063 }; 3064 3065 #ifdef LIMITED_RATE_FMT_SUPPORT 3066 /* support only the safe format and rate */ 3067 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 3068 #define SUPPORTED_MAXBPS 16 3069 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE 3070 #else 3071 /* support all rates and formats */ 3072 #define SUPPORTED_RATES \ 3073 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ 3074 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ 3075 SNDRV_PCM_RATE_192000) 3076 #define SUPPORTED_MAXBPS 24 3077 #define SUPPORTED_FORMATS \ 3078 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 3079 #endif 3080 3081 static int nvhdmi_7x_init_2ch(struct hda_codec *codec) 3082 { 3083 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); 3084 return 0; 3085 } 3086 3087 static int nvhdmi_7x_init_8ch(struct hda_codec *codec) 3088 { 3089 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); 3090 return 0; 3091 } 3092 3093 static const unsigned int channels_2_6_8[] = { 3094 2, 6, 8 3095 }; 3096 3097 static const unsigned int channels_2_8[] = { 3098 2, 8 3099 }; 3100 3101 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { 3102 .count = ARRAY_SIZE(channels_2_6_8), 3103 .list = channels_2_6_8, 3104 .mask = 0, 3105 }; 3106 3107 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { 3108 .count = ARRAY_SIZE(channels_2_8), 3109 .list = channels_2_8, 3110 .mask = 0, 3111 }; 3112 3113 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, 3114 struct hda_codec *codec, 3115 struct snd_pcm_substream *substream) 3116 { 3117 struct hdmi_spec *spec = codec->spec; 3118 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; 3119 3120 switch (codec->preset->vendor_id) { 3121 case 0x10de0002: 3122 case 0x10de0003: 3123 case 0x10de0005: 3124 case 0x10de0006: 3125 hw_constraints_channels = &hw_constraints_2_8_channels; 3126 break; 3127 case 0x10de0007: 3128 hw_constraints_channels = &hw_constraints_2_6_8_channels; 3129 break; 3130 default: 3131 break; 3132 } 3133 3134 if (hw_constraints_channels != NULL) { 3135 snd_pcm_hw_constraint_list(substream->runtime, 0, 3136 SNDRV_PCM_HW_PARAM_CHANNELS, 3137 hw_constraints_channels); 3138 } else { 3139 snd_pcm_hw_constraint_step(substream->runtime, 0, 3140 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 3141 } 3142 3143 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3144 } 3145 3146 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, 3147 struct hda_codec *codec, 3148 struct snd_pcm_substream *substream) 3149 { 3150 struct hdmi_spec *spec = codec->spec; 3151 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3152 } 3153 3154 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3155 struct hda_codec *codec, 3156 unsigned int stream_tag, 3157 unsigned int format, 3158 struct snd_pcm_substream *substream) 3159 { 3160 struct hdmi_spec *spec = codec->spec; 3161 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3162 stream_tag, format, substream); 3163 } 3164 3165 static const struct hda_pcm_stream simple_pcm_playback = { 3166 .substreams = 1, 3167 .channels_min = 2, 3168 .channels_max = 2, 3169 .ops = { 3170 .open = simple_playback_pcm_open, 3171 .close = simple_playback_pcm_close, 3172 .prepare = simple_playback_pcm_prepare 3173 }, 3174 }; 3175 3176 static const struct hda_codec_ops simple_hdmi_patch_ops = { 3177 .build_controls = simple_playback_build_controls, 3178 .build_pcms = simple_playback_build_pcms, 3179 .init = simple_playback_init, 3180 .free = simple_playback_free, 3181 .unsol_event = simple_hdmi_unsol_event, 3182 }; 3183 3184 static int patch_simple_hdmi(struct hda_codec *codec, 3185 hda_nid_t cvt_nid, hda_nid_t pin_nid) 3186 { 3187 struct hdmi_spec *spec; 3188 struct hdmi_spec_per_cvt *per_cvt; 3189 struct hdmi_spec_per_pin *per_pin; 3190 3191 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 3192 if (!spec) 3193 return -ENOMEM; 3194 3195 spec->codec = codec; 3196 codec->spec = spec; 3197 hdmi_array_init(spec, 1); 3198 3199 spec->multiout.num_dacs = 0; /* no analog */ 3200 spec->multiout.max_channels = 2; 3201 spec->multiout.dig_out_nid = cvt_nid; 3202 spec->num_cvts = 1; 3203 spec->num_pins = 1; 3204 per_pin = snd_array_new(&spec->pins); 3205 per_cvt = snd_array_new(&spec->cvts); 3206 if (!per_pin || !per_cvt) { 3207 simple_playback_free(codec); 3208 return -ENOMEM; 3209 } 3210 per_cvt->cvt_nid = cvt_nid; 3211 per_pin->pin_nid = pin_nid; 3212 spec->pcm_playback = simple_pcm_playback; 3213 3214 codec->patch_ops = simple_hdmi_patch_ops; 3215 3216 return 0; 3217 } 3218 3219 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, 3220 int channels) 3221 { 3222 unsigned int chanmask; 3223 int chan = channels ? (channels - 1) : 1; 3224 3225 switch (channels) { 3226 default: 3227 case 0: 3228 case 2: 3229 chanmask = 0x00; 3230 break; 3231 case 4: 3232 chanmask = 0x08; 3233 break; 3234 case 6: 3235 chanmask = 0x0b; 3236 break; 3237 case 8: 3238 chanmask = 0x13; 3239 break; 3240 } 3241 3242 /* Set the audio infoframe channel allocation and checksum fields. The 3243 * channel count is computed implicitly by the hardware. */ 3244 snd_hda_codec_write(codec, 0x1, 0, 3245 Nv_VERB_SET_Channel_Allocation, chanmask); 3246 3247 snd_hda_codec_write(codec, 0x1, 0, 3248 Nv_VERB_SET_Info_Frame_Checksum, 3249 (0x71 - chan - chanmask)); 3250 } 3251 3252 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, 3253 struct hda_codec *codec, 3254 struct snd_pcm_substream *substream) 3255 { 3256 struct hdmi_spec *spec = codec->spec; 3257 int i; 3258 3259 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 3260 0, AC_VERB_SET_CHANNEL_STREAMID, 0); 3261 for (i = 0; i < 4; i++) { 3262 /* set the stream id */ 3263 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3264 AC_VERB_SET_CHANNEL_STREAMID, 0); 3265 /* set the stream format */ 3266 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3267 AC_VERB_SET_STREAM_FORMAT, 0); 3268 } 3269 3270 /* The audio hardware sends a channel count of 0x7 (8ch) when all the 3271 * streams are disabled. */ 3272 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3273 3274 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3275 } 3276 3277 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, 3278 struct hda_codec *codec, 3279 unsigned int stream_tag, 3280 unsigned int format, 3281 struct snd_pcm_substream *substream) 3282 { 3283 int chs; 3284 unsigned int dataDCC2, channel_id; 3285 int i; 3286 struct hdmi_spec *spec = codec->spec; 3287 struct hda_spdif_out *spdif; 3288 struct hdmi_spec_per_cvt *per_cvt; 3289 3290 mutex_lock(&codec->spdif_mutex); 3291 per_cvt = get_cvt(spec, 0); 3292 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); 3293 3294 chs = substream->runtime->channels; 3295 3296 dataDCC2 = 0x2; 3297 3298 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ 3299 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) 3300 snd_hda_codec_write(codec, 3301 nvhdmi_master_con_nid_7x, 3302 0, 3303 AC_VERB_SET_DIGI_CONVERT_1, 3304 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3305 3306 /* set the stream id */ 3307 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3308 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); 3309 3310 /* set the stream format */ 3311 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3312 AC_VERB_SET_STREAM_FORMAT, format); 3313 3314 /* turn on again (if needed) */ 3315 /* enable and set the channel status audio/data flag */ 3316 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { 3317 snd_hda_codec_write(codec, 3318 nvhdmi_master_con_nid_7x, 3319 0, 3320 AC_VERB_SET_DIGI_CONVERT_1, 3321 spdif->ctls & 0xff); 3322 snd_hda_codec_write(codec, 3323 nvhdmi_master_con_nid_7x, 3324 0, 3325 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3326 } 3327 3328 for (i = 0; i < 4; i++) { 3329 if (chs == 2) 3330 channel_id = 0; 3331 else 3332 channel_id = i * 2; 3333 3334 /* turn off SPDIF once; 3335 *otherwise the IEC958 bits won't be updated 3336 */ 3337 if (codec->spdif_status_reset && 3338 (spdif->ctls & AC_DIG1_ENABLE)) 3339 snd_hda_codec_write(codec, 3340 nvhdmi_con_nids_7x[i], 3341 0, 3342 AC_VERB_SET_DIGI_CONVERT_1, 3343 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3344 /* set the stream id */ 3345 snd_hda_codec_write(codec, 3346 nvhdmi_con_nids_7x[i], 3347 0, 3348 AC_VERB_SET_CHANNEL_STREAMID, 3349 (stream_tag << 4) | channel_id); 3350 /* set the stream format */ 3351 snd_hda_codec_write(codec, 3352 nvhdmi_con_nids_7x[i], 3353 0, 3354 AC_VERB_SET_STREAM_FORMAT, 3355 format); 3356 /* turn on again (if needed) */ 3357 /* enable and set the channel status audio/data flag */ 3358 if (codec->spdif_status_reset && 3359 (spdif->ctls & AC_DIG1_ENABLE)) { 3360 snd_hda_codec_write(codec, 3361 nvhdmi_con_nids_7x[i], 3362 0, 3363 AC_VERB_SET_DIGI_CONVERT_1, 3364 spdif->ctls & 0xff); 3365 snd_hda_codec_write(codec, 3366 nvhdmi_con_nids_7x[i], 3367 0, 3368 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3369 } 3370 } 3371 3372 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); 3373 3374 mutex_unlock(&codec->spdif_mutex); 3375 return 0; 3376 } 3377 3378 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { 3379 .substreams = 1, 3380 .channels_min = 2, 3381 .channels_max = 8, 3382 .nid = nvhdmi_master_con_nid_7x, 3383 .rates = SUPPORTED_RATES, 3384 .maxbps = SUPPORTED_MAXBPS, 3385 .formats = SUPPORTED_FORMATS, 3386 .ops = { 3387 .open = simple_playback_pcm_open, 3388 .close = nvhdmi_8ch_7x_pcm_close, 3389 .prepare = nvhdmi_8ch_7x_pcm_prepare 3390 }, 3391 }; 3392 3393 static int patch_nvhdmi_2ch(struct hda_codec *codec) 3394 { 3395 struct hdmi_spec *spec; 3396 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, 3397 nvhdmi_master_pin_nid_7x); 3398 if (err < 0) 3399 return err; 3400 3401 codec->patch_ops.init = nvhdmi_7x_init_2ch; 3402 /* override the PCM rates, etc, as the codec doesn't give full list */ 3403 spec = codec->spec; 3404 spec->pcm_playback.rates = SUPPORTED_RATES; 3405 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; 3406 spec->pcm_playback.formats = SUPPORTED_FORMATS; 3407 return 0; 3408 } 3409 3410 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) 3411 { 3412 struct hdmi_spec *spec = codec->spec; 3413 int err = simple_playback_build_pcms(codec); 3414 if (!err) { 3415 struct hda_pcm *info = get_pcm_rec(spec, 0); 3416 info->own_chmap = true; 3417 } 3418 return err; 3419 } 3420 3421 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) 3422 { 3423 struct hdmi_spec *spec = codec->spec; 3424 struct hda_pcm *info; 3425 struct snd_pcm_chmap *chmap; 3426 int err; 3427 3428 err = simple_playback_build_controls(codec); 3429 if (err < 0) 3430 return err; 3431 3432 /* add channel maps */ 3433 info = get_pcm_rec(spec, 0); 3434 err = snd_pcm_add_chmap_ctls(info->pcm, 3435 SNDRV_PCM_STREAM_PLAYBACK, 3436 snd_pcm_alt_chmaps, 8, 0, &chmap); 3437 if (err < 0) 3438 return err; 3439 switch (codec->preset->vendor_id) { 3440 case 0x10de0002: 3441 case 0x10de0003: 3442 case 0x10de0005: 3443 case 0x10de0006: 3444 chmap->channel_mask = (1U << 2) | (1U << 8); 3445 break; 3446 case 0x10de0007: 3447 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); 3448 } 3449 return 0; 3450 } 3451 3452 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) 3453 { 3454 struct hdmi_spec *spec; 3455 int err = patch_nvhdmi_2ch(codec); 3456 if (err < 0) 3457 return err; 3458 spec = codec->spec; 3459 spec->multiout.max_channels = 8; 3460 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; 3461 codec->patch_ops.init = nvhdmi_7x_init_8ch; 3462 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; 3463 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; 3464 3465 /* Initialize the audio infoframe channel mask and checksum to something 3466 * valid */ 3467 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3468 3469 return 0; 3470 } 3471 3472 /* 3473 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: 3474 * - 0x10de0015 3475 * - 0x10de0040 3476 */ 3477 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, 3478 struct hdac_cea_channel_speaker_allocation *cap, int channels) 3479 { 3480 if (cap->ca_index == 0x00 && channels == 2) 3481 return SNDRV_CTL_TLVT_CHMAP_FIXED; 3482 3483 /* If the speaker allocation matches the channel count, it is OK. */ 3484 if (cap->channels != channels) 3485 return -1; 3486 3487 /* all channels are remappable freely */ 3488 return SNDRV_CTL_TLVT_CHMAP_VAR; 3489 } 3490 3491 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, 3492 int ca, int chs, unsigned char *map) 3493 { 3494 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) 3495 return -EINVAL; 3496 3497 return 0; 3498 } 3499 3500 /* map from pin NID to port; port is 0-based */ 3501 /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */ 3502 static int nvhdmi_pin2port(void *audio_ptr, int pin_nid) 3503 { 3504 return pin_nid - 4; 3505 } 3506 3507 /* reverse-map from port to pin NID: see above */ 3508 static int nvhdmi_port2pin(struct hda_codec *codec, int port) 3509 { 3510 return port + 4; 3511 } 3512 3513 static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = { 3514 .pin2port = nvhdmi_pin2port, 3515 .pin_eld_notify = generic_acomp_pin_eld_notify, 3516 .master_bind = generic_acomp_master_bind, 3517 .master_unbind = generic_acomp_master_unbind, 3518 }; 3519 3520 static int patch_nvhdmi(struct hda_codec *codec) 3521 { 3522 struct hdmi_spec *spec; 3523 int err; 3524 3525 err = alloc_generic_hdmi(codec); 3526 if (err < 0) 3527 return err; 3528 codec->dp_mst = true; 3529 3530 spec = codec->spec; 3531 spec->dyn_pcm_assign = true; 3532 3533 err = hdmi_parse_codec(codec); 3534 if (err < 0) { 3535 generic_spec_free(codec); 3536 return err; 3537 } 3538 3539 generic_hdmi_init_per_pins(codec); 3540 3541 spec->dyn_pin_out = true; 3542 3543 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3544 nvhdmi_chmap_cea_alloc_validate_get_type; 3545 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3546 3547 codec->link_down_at_suspend = 1; 3548 3549 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin); 3550 3551 return 0; 3552 } 3553 3554 static int patch_nvhdmi_legacy(struct hda_codec *codec) 3555 { 3556 struct hdmi_spec *spec; 3557 int err; 3558 3559 err = patch_generic_hdmi(codec); 3560 if (err) 3561 return err; 3562 3563 spec = codec->spec; 3564 spec->dyn_pin_out = true; 3565 3566 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3567 nvhdmi_chmap_cea_alloc_validate_get_type; 3568 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3569 3570 codec->link_down_at_suspend = 1; 3571 3572 return 0; 3573 } 3574 3575 /* 3576 * The HDA codec on NVIDIA Tegra contains two scratch registers that are 3577 * accessed using vendor-defined verbs. These registers can be used for 3578 * interoperability between the HDA and HDMI drivers. 3579 */ 3580 3581 /* Audio Function Group node */ 3582 #define NVIDIA_AFG_NID 0x01 3583 3584 /* 3585 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio 3586 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to 3587 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This 3588 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an 3589 * additional bit (at position 30) to signal the validity of the format. 3590 * 3591 * | 31 | 30 | 29 16 | 15 0 | 3592 * +---------+-------+--------+--------+ 3593 * | TRIGGER | VALID | UNUSED | FORMAT | 3594 * +-----------------------------------| 3595 * 3596 * Note that for the trigger bit to take effect it needs to change value 3597 * (i.e. it needs to be toggled). 3598 */ 3599 #define NVIDIA_GET_SCRATCH0 0xfa6 3600 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 3601 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 3602 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 3603 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa 3604 #define NVIDIA_SCRATCH_TRIGGER (1 << 7) 3605 #define NVIDIA_SCRATCH_VALID (1 << 6) 3606 3607 #define NVIDIA_GET_SCRATCH1 0xfab 3608 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac 3609 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad 3610 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae 3611 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf 3612 3613 /* 3614 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, 3615 * the format is invalidated so that the HDMI codec can be disabled. 3616 */ 3617 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format) 3618 { 3619 unsigned int value; 3620 3621 /* bits [31:30] contain the trigger and valid bits */ 3622 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0, 3623 NVIDIA_GET_SCRATCH0, 0); 3624 value = (value >> 24) & 0xff; 3625 3626 /* bits [15:0] are used to store the HDA format */ 3627 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3628 NVIDIA_SET_SCRATCH0_BYTE0, 3629 (format >> 0) & 0xff); 3630 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3631 NVIDIA_SET_SCRATCH0_BYTE1, 3632 (format >> 8) & 0xff); 3633 3634 /* bits [16:24] are unused */ 3635 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3636 NVIDIA_SET_SCRATCH0_BYTE2, 0); 3637 3638 /* 3639 * Bit 30 signals that the data is valid and hence that HDMI audio can 3640 * be enabled. 3641 */ 3642 if (format == 0) 3643 value &= ~NVIDIA_SCRATCH_VALID; 3644 else 3645 value |= NVIDIA_SCRATCH_VALID; 3646 3647 /* 3648 * Whenever the trigger bit is toggled, an interrupt is raised in the 3649 * HDMI codec. The HDMI driver will use that as trigger to update its 3650 * configuration. 3651 */ 3652 value ^= NVIDIA_SCRATCH_TRIGGER; 3653 3654 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3655 NVIDIA_SET_SCRATCH0_BYTE3, value); 3656 } 3657 3658 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, 3659 struct hda_codec *codec, 3660 unsigned int stream_tag, 3661 unsigned int format, 3662 struct snd_pcm_substream *substream) 3663 { 3664 int err; 3665 3666 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, 3667 format, substream); 3668 if (err < 0) 3669 return err; 3670 3671 /* notify the HDMI codec of the format change */ 3672 tegra_hdmi_set_format(codec, format); 3673 3674 return 0; 3675 } 3676 3677 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, 3678 struct hda_codec *codec, 3679 struct snd_pcm_substream *substream) 3680 { 3681 /* invalidate the format in the HDMI codec */ 3682 tegra_hdmi_set_format(codec, 0); 3683 3684 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); 3685 } 3686 3687 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) 3688 { 3689 struct hdmi_spec *spec = codec->spec; 3690 unsigned int i; 3691 3692 for (i = 0; i < spec->num_pins; i++) { 3693 struct hda_pcm *pcm = get_pcm_rec(spec, i); 3694 3695 if (pcm->pcm_type == type) 3696 return pcm; 3697 } 3698 3699 return NULL; 3700 } 3701 3702 static int tegra_hdmi_build_pcms(struct hda_codec *codec) 3703 { 3704 struct hda_pcm_stream *stream; 3705 struct hda_pcm *pcm; 3706 int err; 3707 3708 err = generic_hdmi_build_pcms(codec); 3709 if (err < 0) 3710 return err; 3711 3712 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); 3713 if (!pcm) 3714 return -ENODEV; 3715 3716 /* 3717 * Override ->prepare() and ->cleanup() operations to notify the HDMI 3718 * codec about format changes. 3719 */ 3720 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3721 stream->ops.prepare = tegra_hdmi_pcm_prepare; 3722 stream->ops.cleanup = tegra_hdmi_pcm_cleanup; 3723 3724 return 0; 3725 } 3726 3727 static int patch_tegra_hdmi(struct hda_codec *codec) 3728 { 3729 int err; 3730 3731 err = patch_generic_hdmi(codec); 3732 if (err) 3733 return err; 3734 3735 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; 3736 3737 return 0; 3738 } 3739 3740 /* 3741 * ATI/AMD-specific implementations 3742 */ 3743 3744 #define is_amdhdmi_rev3_or_later(codec) \ 3745 ((codec)->core.vendor_id == 0x1002aa01 && \ 3746 ((codec)->core.revision_id & 0xff00) >= 0x0300) 3747 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) 3748 3749 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ 3750 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 3751 #define ATI_VERB_SET_DOWNMIX_INFO 0x772 3752 #define ATI_VERB_SET_MULTICHANNEL_01 0x777 3753 #define ATI_VERB_SET_MULTICHANNEL_23 0x778 3754 #define ATI_VERB_SET_MULTICHANNEL_45 0x779 3755 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a 3756 #define ATI_VERB_SET_HBR_CONTROL 0x77c 3757 #define ATI_VERB_SET_MULTICHANNEL_1 0x785 3758 #define ATI_VERB_SET_MULTICHANNEL_3 0x786 3759 #define ATI_VERB_SET_MULTICHANNEL_5 0x787 3760 #define ATI_VERB_SET_MULTICHANNEL_7 0x788 3761 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 3762 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 3763 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 3764 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 3765 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 3766 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 3767 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a 3768 #define ATI_VERB_GET_HBR_CONTROL 0xf7c 3769 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 3770 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 3771 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 3772 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 3773 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 3774 3775 /* AMD specific HDA cvt verbs */ 3776 #define ATI_VERB_SET_RAMP_RATE 0x770 3777 #define ATI_VERB_GET_RAMP_RATE 0xf70 3778 3779 #define ATI_OUT_ENABLE 0x1 3780 3781 #define ATI_MULTICHANNEL_MODE_PAIRED 0 3782 #define ATI_MULTICHANNEL_MODE_SINGLE 1 3783 3784 #define ATI_HBR_CAPABLE 0x01 3785 #define ATI_HBR_ENABLE 0x10 3786 3787 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 3788 int dev_id, unsigned char *buf, int *eld_size) 3789 { 3790 WARN_ON(dev_id != 0); 3791 /* call hda_eld.c ATI/AMD-specific function */ 3792 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, 3793 is_amdhdmi_rev3_or_later(codec)); 3794 } 3795 3796 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, 3797 hda_nid_t pin_nid, int dev_id, int ca, 3798 int active_channels, int conn_type) 3799 { 3800 WARN_ON(dev_id != 0); 3801 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); 3802 } 3803 3804 static int atihdmi_paired_swap_fc_lfe(int pos) 3805 { 3806 /* 3807 * ATI/AMD have automatic FC/LFE swap built-in 3808 * when in pairwise mapping mode. 3809 */ 3810 3811 switch (pos) { 3812 /* see channel_allocations[].speakers[] */ 3813 case 2: return 3; 3814 case 3: return 2; 3815 default: break; 3816 } 3817 3818 return pos; 3819 } 3820 3821 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, 3822 int ca, int chs, unsigned char *map) 3823 { 3824 struct hdac_cea_channel_speaker_allocation *cap; 3825 int i, j; 3826 3827 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ 3828 3829 cap = snd_hdac_get_ch_alloc_from_ca(ca); 3830 for (i = 0; i < chs; ++i) { 3831 int mask = snd_hdac_chmap_to_spk_mask(map[i]); 3832 bool ok = false; 3833 bool companion_ok = false; 3834 3835 if (!mask) 3836 continue; 3837 3838 for (j = 0 + i % 2; j < 8; j += 2) { 3839 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); 3840 if (cap->speakers[chan_idx] == mask) { 3841 /* channel is in a supported position */ 3842 ok = true; 3843 3844 if (i % 2 == 0 && i + 1 < chs) { 3845 /* even channel, check the odd companion */ 3846 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); 3847 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); 3848 int comp_mask_act = cap->speakers[comp_chan_idx]; 3849 3850 if (comp_mask_req == comp_mask_act) 3851 companion_ok = true; 3852 else 3853 return -EINVAL; 3854 } 3855 break; 3856 } 3857 } 3858 3859 if (!ok) 3860 return -EINVAL; 3861 3862 if (companion_ok) 3863 i++; /* companion channel already checked */ 3864 } 3865 3866 return 0; 3867 } 3868 3869 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, 3870 hda_nid_t pin_nid, int hdmi_slot, int stream_channel) 3871 { 3872 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 3873 int verb; 3874 int ati_channel_setup = 0; 3875 3876 if (hdmi_slot > 7) 3877 return -EINVAL; 3878 3879 if (!has_amd_full_remap_support(codec)) { 3880 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); 3881 3882 /* In case this is an odd slot but without stream channel, do not 3883 * disable the slot since the corresponding even slot could have a 3884 * channel. In case neither have a channel, the slot pair will be 3885 * disabled when this function is called for the even slot. */ 3886 if (hdmi_slot % 2 != 0 && stream_channel == 0xf) 3887 return 0; 3888 3889 hdmi_slot -= hdmi_slot % 2; 3890 3891 if (stream_channel != 0xf) 3892 stream_channel -= stream_channel % 2; 3893 } 3894 3895 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; 3896 3897 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ 3898 3899 if (stream_channel != 0xf) 3900 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; 3901 3902 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); 3903 } 3904 3905 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, 3906 hda_nid_t pin_nid, int asp_slot) 3907 { 3908 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 3909 bool was_odd = false; 3910 int ati_asp_slot = asp_slot; 3911 int verb; 3912 int ati_channel_setup; 3913 3914 if (asp_slot > 7) 3915 return -EINVAL; 3916 3917 if (!has_amd_full_remap_support(codec)) { 3918 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); 3919 if (ati_asp_slot % 2 != 0) { 3920 ati_asp_slot -= 1; 3921 was_odd = true; 3922 } 3923 } 3924 3925 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; 3926 3927 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); 3928 3929 if (!(ati_channel_setup & ATI_OUT_ENABLE)) 3930 return 0xf; 3931 3932 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; 3933 } 3934 3935 static int atihdmi_paired_chmap_cea_alloc_validate_get_type( 3936 struct hdac_chmap *chmap, 3937 struct hdac_cea_channel_speaker_allocation *cap, 3938 int channels) 3939 { 3940 int c; 3941 3942 /* 3943 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so 3944 * we need to take that into account (a single channel may take 2 3945 * channel slots if we need to carry a silent channel next to it). 3946 * On Rev3+ AMD codecs this function is not used. 3947 */ 3948 int chanpairs = 0; 3949 3950 /* We only produce even-numbered channel count TLVs */ 3951 if ((channels % 2) != 0) 3952 return -1; 3953 3954 for (c = 0; c < 7; c += 2) { 3955 if (cap->speakers[c] || cap->speakers[c+1]) 3956 chanpairs++; 3957 } 3958 3959 if (chanpairs * 2 != channels) 3960 return -1; 3961 3962 return SNDRV_CTL_TLVT_CHMAP_PAIRED; 3963 } 3964 3965 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, 3966 struct hdac_cea_channel_speaker_allocation *cap, 3967 unsigned int *chmap, int channels) 3968 { 3969 /* produce paired maps for pre-rev3 ATI/AMD codecs */ 3970 int count = 0; 3971 int c; 3972 3973 for (c = 7; c >= 0; c--) { 3974 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); 3975 int spk = cap->speakers[chan]; 3976 if (!spk) { 3977 /* add N/A channel if the companion channel is occupied */ 3978 if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) 3979 chmap[count++] = SNDRV_CHMAP_NA; 3980 3981 continue; 3982 } 3983 3984 chmap[count++] = snd_hdac_spk_to_chmap(spk); 3985 } 3986 3987 WARN_ON(count != channels); 3988 } 3989 3990 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 3991 int dev_id, bool hbr) 3992 { 3993 int hbr_ctl, hbr_ctl_new; 3994 3995 WARN_ON(dev_id != 0); 3996 3997 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); 3998 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { 3999 if (hbr) 4000 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; 4001 else 4002 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; 4003 4004 codec_dbg(codec, 4005 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", 4006 pin_nid, 4007 hbr_ctl == hbr_ctl_new ? "" : "new-", 4008 hbr_ctl_new); 4009 4010 if (hbr_ctl != hbr_ctl_new) 4011 snd_hda_codec_write(codec, pin_nid, 0, 4012 ATI_VERB_SET_HBR_CONTROL, 4013 hbr_ctl_new); 4014 4015 } else if (hbr) 4016 return -EINVAL; 4017 4018 return 0; 4019 } 4020 4021 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 4022 hda_nid_t pin_nid, int dev_id, 4023 u32 stream_tag, int format) 4024 { 4025 if (is_amdhdmi_rev3_or_later(codec)) { 4026 int ramp_rate = 180; /* default as per AMD spec */ 4027 /* disable ramp-up/down for non-pcm as per AMD spec */ 4028 if (format & AC_FMT_TYPE_NON_PCM) 4029 ramp_rate = 0; 4030 4031 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); 4032 } 4033 4034 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 4035 stream_tag, format); 4036 } 4037 4038 4039 static int atihdmi_init(struct hda_codec *codec) 4040 { 4041 struct hdmi_spec *spec = codec->spec; 4042 int pin_idx, err; 4043 4044 err = generic_hdmi_init(codec); 4045 4046 if (err) 4047 return err; 4048 4049 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 4050 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 4051 4052 /* make sure downmix information in infoframe is zero */ 4053 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); 4054 4055 /* enable channel-wise remap mode if supported */ 4056 if (has_amd_full_remap_support(codec)) 4057 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 4058 ATI_VERB_SET_MULTICHANNEL_MODE, 4059 ATI_MULTICHANNEL_MODE_SINGLE); 4060 } 4061 codec->auto_runtime_pm = 1; 4062 4063 return 0; 4064 } 4065 4066 /* map from pin NID to port; port is 0-based */ 4067 /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */ 4068 static int atihdmi_pin2port(void *audio_ptr, int pin_nid) 4069 { 4070 return pin_nid / 2 - 1; 4071 } 4072 4073 /* reverse-map from port to pin NID: see above */ 4074 static int atihdmi_port2pin(struct hda_codec *codec, int port) 4075 { 4076 return port * 2 + 3; 4077 } 4078 4079 static const struct drm_audio_component_audio_ops atihdmi_audio_ops = { 4080 .pin2port = atihdmi_pin2port, 4081 .pin_eld_notify = generic_acomp_pin_eld_notify, 4082 .master_bind = generic_acomp_master_bind, 4083 .master_unbind = generic_acomp_master_unbind, 4084 }; 4085 4086 static int patch_atihdmi(struct hda_codec *codec) 4087 { 4088 struct hdmi_spec *spec; 4089 struct hdmi_spec_per_cvt *per_cvt; 4090 int err, cvt_idx; 4091 4092 err = patch_generic_hdmi(codec); 4093 4094 if (err) 4095 return err; 4096 4097 codec->patch_ops.init = atihdmi_init; 4098 4099 spec = codec->spec; 4100 4101 spec->ops.pin_get_eld = atihdmi_pin_get_eld; 4102 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; 4103 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; 4104 spec->ops.setup_stream = atihdmi_setup_stream; 4105 4106 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; 4107 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; 4108 4109 if (!has_amd_full_remap_support(codec)) { 4110 /* override to ATI/AMD-specific versions with pairwise mapping */ 4111 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4112 atihdmi_paired_chmap_cea_alloc_validate_get_type; 4113 spec->chmap.ops.cea_alloc_to_tlv_chmap = 4114 atihdmi_paired_cea_alloc_to_tlv_chmap; 4115 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; 4116 } 4117 4118 /* ATI/AMD converters do not advertise all of their capabilities */ 4119 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 4120 per_cvt = get_cvt(spec, cvt_idx); 4121 per_cvt->channels_max = max(per_cvt->channels_max, 8u); 4122 per_cvt->rates |= SUPPORTED_RATES; 4123 per_cvt->formats |= SUPPORTED_FORMATS; 4124 per_cvt->maxbps = max(per_cvt->maxbps, 24u); 4125 } 4126 4127 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); 4128 4129 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing 4130 * the link-down as is. Tell the core to allow it. 4131 */ 4132 codec->link_down_at_suspend = 1; 4133 4134 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin); 4135 4136 return 0; 4137 } 4138 4139 /* VIA HDMI Implementation */ 4140 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ 4141 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ 4142 4143 static int patch_via_hdmi(struct hda_codec *codec) 4144 { 4145 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); 4146 } 4147 4148 /* 4149 * patch entries 4150 */ 4151 static const struct hda_device_id snd_hda_id_hdmi[] = { 4152 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), 4153 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), 4154 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), 4155 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), 4156 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), 4157 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), 4158 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), 4159 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch), 4160 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4161 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4162 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x), 4163 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4164 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4165 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), 4166 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy), 4167 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy), 4168 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy), 4169 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy), 4170 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy), 4171 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy), 4172 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy), 4173 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy), 4174 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy), 4175 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy), 4176 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy), 4177 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy), 4178 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy), 4179 /* 17 is known to be absent */ 4180 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy), 4181 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy), 4182 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy), 4183 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy), 4184 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy), 4185 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), 4186 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), 4187 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), 4188 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), 4189 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi), 4190 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi), 4191 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), 4192 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), 4193 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), 4194 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), 4195 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), 4196 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), 4197 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), 4198 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi), 4199 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi), 4200 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), 4201 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi), 4202 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), 4203 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi), 4204 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi), 4205 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), 4206 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), 4207 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), 4208 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), 4209 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi), 4210 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi), 4211 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi), 4212 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi), 4213 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi), 4214 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), 4215 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi), 4216 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), 4217 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi), 4218 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), 4219 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), 4220 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi), 4221 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi), 4222 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi), 4223 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi), 4224 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi), 4225 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi), 4226 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi), 4227 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi), 4228 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), 4229 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), 4230 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), 4231 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), 4232 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), 4233 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), 4234 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), 4235 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), 4236 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4237 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), 4238 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), 4239 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), 4240 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), 4241 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4242 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), 4243 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), 4244 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), 4245 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), 4246 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), 4247 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), 4248 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), 4249 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), 4250 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), 4251 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi), 4252 HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi), 4253 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), 4254 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), 4255 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), 4256 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), 4257 /* special ID for generic HDMI */ 4258 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), 4259 {} /* terminator */ 4260 }; 4261 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); 4262 4263 MODULE_LICENSE("GPL"); 4264 MODULE_DESCRIPTION("HDMI HD-audio codec"); 4265 MODULE_ALIAS("snd-hda-codec-intelhdmi"); 4266 MODULE_ALIAS("snd-hda-codec-nvhdmi"); 4267 MODULE_ALIAS("snd-hda-codec-atihdmi"); 4268 4269 static struct hda_codec_driver hdmi_driver = { 4270 .id = snd_hda_id_hdmi, 4271 }; 4272 4273 module_hda_codec_driver(hdmi_driver); 4274