1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs 5 * 6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. 7 * Copyright (c) 2006 ATI Technologies Inc. 8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved. 9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com> 10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> 11 * 12 * Authors: 13 * Wu Fengguang <wfg@linux.intel.com> 14 * 15 * Maintained by: 16 * Wu Fengguang <wfg@linux.intel.com> 17 */ 18 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/pci.h> 22 #include <linux/slab.h> 23 #include <linux/module.h> 24 #include <linux/pm_runtime.h> 25 #include <sound/core.h> 26 #include <sound/jack.h> 27 #include <sound/asoundef.h> 28 #include <sound/tlv.h> 29 #include <sound/hdaudio.h> 30 #include <sound/hda_i915.h> 31 #include <sound/hda_chmap.h> 32 #include <sound/hda_codec.h> 33 #include "hda_local.h" 34 #include "hda_jack.h" 35 #include "hda_controller.h" 36 37 static bool static_hdmi_pcm; 38 module_param(static_hdmi_pcm, bool, 0644); 39 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); 40 41 struct hdmi_spec_per_cvt { 42 hda_nid_t cvt_nid; 43 int assigned; 44 unsigned int channels_min; 45 unsigned int channels_max; 46 u32 rates; 47 u64 formats; 48 unsigned int maxbps; 49 }; 50 51 /* max. connections to a widget */ 52 #define HDA_MAX_CONNECTIONS 32 53 54 struct hdmi_spec_per_pin { 55 hda_nid_t pin_nid; 56 int dev_id; 57 /* pin idx, different device entries on the same pin use the same idx */ 58 int pin_nid_idx; 59 int num_mux_nids; 60 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; 61 int mux_idx; 62 hda_nid_t cvt_nid; 63 64 struct hda_codec *codec; 65 struct hdmi_eld sink_eld; 66 struct mutex lock; 67 struct delayed_work work; 68 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ 69 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ 70 int repoll_count; 71 bool setup; /* the stream has been set up by prepare callback */ 72 int channels; /* current number of channels */ 73 bool non_pcm; 74 bool chmap_set; /* channel-map override by ALSA API? */ 75 unsigned char chmap[8]; /* ALSA API channel-map */ 76 #ifdef CONFIG_SND_PROC_FS 77 struct snd_info_entry *proc_entry; 78 #endif 79 }; 80 81 /* operations used by generic code that can be overridden by patches */ 82 struct hdmi_ops { 83 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, 84 int dev_id, unsigned char *buf, int *eld_size); 85 86 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, 87 int dev_id, 88 int ca, int active_channels, int conn_type); 89 90 /* enable/disable HBR (HD passthrough) */ 91 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, 92 int dev_id, bool hbr); 93 94 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, 95 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 96 int format); 97 98 void (*pin_cvt_fixup)(struct hda_codec *codec, 99 struct hdmi_spec_per_pin *per_pin, 100 hda_nid_t cvt_nid); 101 }; 102 103 struct hdmi_pcm { 104 struct hda_pcm *pcm; 105 struct snd_jack *jack; 106 struct snd_kcontrol *eld_ctl; 107 }; 108 109 struct hdmi_spec { 110 struct hda_codec *codec; 111 int num_cvts; 112 struct snd_array cvts; /* struct hdmi_spec_per_cvt */ 113 hda_nid_t cvt_nids[4]; /* only for haswell fix */ 114 115 /* 116 * num_pins is the number of virtual pins 117 * for example, there are 3 pins, and each pin 118 * has 4 device entries, then the num_pins is 12 119 */ 120 int num_pins; 121 /* 122 * num_nids is the number of real pins 123 * In the above example, num_nids is 3 124 */ 125 int num_nids; 126 /* 127 * dev_num is the number of device entries 128 * on each pin. 129 * In the above example, dev_num is 4 130 */ 131 int dev_num; 132 struct snd_array pins; /* struct hdmi_spec_per_pin */ 133 struct hdmi_pcm pcm_rec[16]; 134 struct mutex pcm_lock; 135 struct mutex bind_lock; /* for audio component binding */ 136 /* pcm_bitmap means which pcms have been assigned to pins*/ 137 unsigned long pcm_bitmap; 138 int pcm_used; /* counter of pcm_rec[] */ 139 /* bitmap shows whether the pcm is opened in user space 140 * bit 0 means the first playback PCM (PCM3); 141 * bit 1 means the second playback PCM, and so on. 142 */ 143 unsigned long pcm_in_use; 144 145 struct hdmi_eld temp_eld; 146 struct hdmi_ops ops; 147 148 bool dyn_pin_out; 149 bool dyn_pcm_assign; 150 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */ 151 /* 152 * Non-generic VIA/NVIDIA specific 153 */ 154 struct hda_multi_out multiout; 155 struct hda_pcm_stream pcm_playback; 156 157 bool use_jack_detect; /* jack detection enabled */ 158 bool use_acomp_notifier; /* use eld_notify callback for hotplug */ 159 bool acomp_registered; /* audio component registered in this driver */ 160 struct drm_audio_component_audio_ops drm_audio_ops; 161 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */ 162 163 struct hdac_chmap chmap; 164 hda_nid_t vendor_nid; 165 const int *port_map; 166 int port_num; 167 }; 168 169 #ifdef CONFIG_SND_HDA_COMPONENT 170 static inline bool codec_has_acomp(struct hda_codec *codec) 171 { 172 struct hdmi_spec *spec = codec->spec; 173 return spec->use_acomp_notifier; 174 } 175 #else 176 #define codec_has_acomp(codec) false 177 #endif 178 179 struct hdmi_audio_infoframe { 180 u8 type; /* 0x84 */ 181 u8 ver; /* 0x01 */ 182 u8 len; /* 0x0a */ 183 184 u8 checksum; 185 186 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ 187 u8 SS01_SF24; 188 u8 CXT04; 189 u8 CA; 190 u8 LFEPBL01_LSV36_DM_INH7; 191 }; 192 193 struct dp_audio_infoframe { 194 u8 type; /* 0x84 */ 195 u8 len; /* 0x1b */ 196 u8 ver; /* 0x11 << 2 */ 197 198 u8 CC02_CT47; /* match with HDMI infoframe from this on */ 199 u8 SS01_SF24; 200 u8 CXT04; 201 u8 CA; 202 u8 LFEPBL01_LSV36_DM_INH7; 203 }; 204 205 union audio_infoframe { 206 struct hdmi_audio_infoframe hdmi; 207 struct dp_audio_infoframe dp; 208 u8 bytes[0]; 209 }; 210 211 /* 212 * HDMI routines 213 */ 214 215 #define get_pin(spec, idx) \ 216 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) 217 #define get_cvt(spec, idx) \ 218 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) 219 /* obtain hdmi_pcm object assigned to idx */ 220 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) 221 /* obtain hda_pcm object assigned to idx */ 222 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) 223 224 static int pin_id_to_pin_index(struct hda_codec *codec, 225 hda_nid_t pin_nid, int dev_id) 226 { 227 struct hdmi_spec *spec = codec->spec; 228 int pin_idx; 229 struct hdmi_spec_per_pin *per_pin; 230 231 /* 232 * (dev_id == -1) means it is NON-MST pin 233 * return the first virtual pin on this port 234 */ 235 if (dev_id == -1) 236 dev_id = 0; 237 238 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 239 per_pin = get_pin(spec, pin_idx); 240 if ((per_pin->pin_nid == pin_nid) && 241 (per_pin->dev_id == dev_id)) 242 return pin_idx; 243 } 244 245 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid); 246 return -EINVAL; 247 } 248 249 static int hinfo_to_pcm_index(struct hda_codec *codec, 250 struct hda_pcm_stream *hinfo) 251 { 252 struct hdmi_spec *spec = codec->spec; 253 int pcm_idx; 254 255 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) 256 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) 257 return pcm_idx; 258 259 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo); 260 return -EINVAL; 261 } 262 263 static int hinfo_to_pin_index(struct hda_codec *codec, 264 struct hda_pcm_stream *hinfo) 265 { 266 struct hdmi_spec *spec = codec->spec; 267 struct hdmi_spec_per_pin *per_pin; 268 int pin_idx; 269 270 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 271 per_pin = get_pin(spec, pin_idx); 272 if (per_pin->pcm && 273 per_pin->pcm->pcm->stream == hinfo) 274 return pin_idx; 275 } 276 277 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo); 278 return -EINVAL; 279 } 280 281 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, 282 int pcm_idx) 283 { 284 int i; 285 struct hdmi_spec_per_pin *per_pin; 286 287 for (i = 0; i < spec->num_pins; i++) { 288 per_pin = get_pin(spec, i); 289 if (per_pin->pcm_idx == pcm_idx) 290 return per_pin; 291 } 292 return NULL; 293 } 294 295 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) 296 { 297 struct hdmi_spec *spec = codec->spec; 298 int cvt_idx; 299 300 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) 301 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) 302 return cvt_idx; 303 304 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid); 305 return -EINVAL; 306 } 307 308 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, 309 struct snd_ctl_elem_info *uinfo) 310 { 311 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 312 struct hdmi_spec *spec = codec->spec; 313 struct hdmi_spec_per_pin *per_pin; 314 struct hdmi_eld *eld; 315 int pcm_idx; 316 317 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 318 319 pcm_idx = kcontrol->private_value; 320 mutex_lock(&spec->pcm_lock); 321 per_pin = pcm_idx_to_pin(spec, pcm_idx); 322 if (!per_pin) { 323 /* no pin is bound to the pcm */ 324 uinfo->count = 0; 325 goto unlock; 326 } 327 eld = &per_pin->sink_eld; 328 uinfo->count = eld->eld_valid ? eld->eld_size : 0; 329 330 unlock: 331 mutex_unlock(&spec->pcm_lock); 332 return 0; 333 } 334 335 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, 336 struct snd_ctl_elem_value *ucontrol) 337 { 338 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 339 struct hdmi_spec *spec = codec->spec; 340 struct hdmi_spec_per_pin *per_pin; 341 struct hdmi_eld *eld; 342 int pcm_idx; 343 int err = 0; 344 345 pcm_idx = kcontrol->private_value; 346 mutex_lock(&spec->pcm_lock); 347 per_pin = pcm_idx_to_pin(spec, pcm_idx); 348 if (!per_pin) { 349 /* no pin is bound to the pcm */ 350 memset(ucontrol->value.bytes.data, 0, 351 ARRAY_SIZE(ucontrol->value.bytes.data)); 352 goto unlock; 353 } 354 355 eld = &per_pin->sink_eld; 356 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || 357 eld->eld_size > ELD_MAX_SIZE) { 358 snd_BUG(); 359 err = -EINVAL; 360 goto unlock; 361 } 362 363 memset(ucontrol->value.bytes.data, 0, 364 ARRAY_SIZE(ucontrol->value.bytes.data)); 365 if (eld->eld_valid) 366 memcpy(ucontrol->value.bytes.data, eld->eld_buffer, 367 eld->eld_size); 368 369 unlock: 370 mutex_unlock(&spec->pcm_lock); 371 return err; 372 } 373 374 static const struct snd_kcontrol_new eld_bytes_ctl = { 375 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE | 376 SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK, 377 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 378 .name = "ELD", 379 .info = hdmi_eld_ctl_info, 380 .get = hdmi_eld_ctl_get, 381 }; 382 383 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, 384 int device) 385 { 386 struct snd_kcontrol *kctl; 387 struct hdmi_spec *spec = codec->spec; 388 int err; 389 390 kctl = snd_ctl_new1(&eld_bytes_ctl, codec); 391 if (!kctl) 392 return -ENOMEM; 393 kctl->private_value = pcm_idx; 394 kctl->id.device = device; 395 396 /* no pin nid is associated with the kctl now 397 * tbd: associate pin nid to eld ctl later 398 */ 399 err = snd_hda_ctl_add(codec, 0, kctl); 400 if (err < 0) 401 return err; 402 403 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; 404 return 0; 405 } 406 407 #ifdef BE_PARANOID 408 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 409 int *packet_index, int *byte_index) 410 { 411 int val; 412 413 val = snd_hda_codec_read(codec, pin_nid, 0, 414 AC_VERB_GET_HDMI_DIP_INDEX, 0); 415 416 *packet_index = val >> 5; 417 *byte_index = val & 0x1f; 418 } 419 #endif 420 421 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 422 int packet_index, int byte_index) 423 { 424 int val; 425 426 val = (packet_index << 5) | (byte_index & 0x1f); 427 428 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); 429 } 430 431 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, 432 unsigned char val) 433 { 434 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); 435 } 436 437 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) 438 { 439 struct hdmi_spec *spec = codec->spec; 440 int pin_out; 441 442 /* Unmute */ 443 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 444 snd_hda_codec_write(codec, pin_nid, 0, 445 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); 446 447 if (spec->dyn_pin_out) 448 /* Disable pin out until stream is active */ 449 pin_out = 0; 450 else 451 /* Enable pin out: some machines with GM965 gets broken output 452 * when the pin is disabled or changed while using with HDMI 453 */ 454 pin_out = PIN_OUT; 455 456 snd_hda_codec_write(codec, pin_nid, 0, 457 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); 458 } 459 460 /* 461 * ELD proc files 462 */ 463 464 #ifdef CONFIG_SND_PROC_FS 465 static void print_eld_info(struct snd_info_entry *entry, 466 struct snd_info_buffer *buffer) 467 { 468 struct hdmi_spec_per_pin *per_pin = entry->private_data; 469 470 mutex_lock(&per_pin->lock); 471 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer); 472 mutex_unlock(&per_pin->lock); 473 } 474 475 static void write_eld_info(struct snd_info_entry *entry, 476 struct snd_info_buffer *buffer) 477 { 478 struct hdmi_spec_per_pin *per_pin = entry->private_data; 479 480 mutex_lock(&per_pin->lock); 481 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); 482 mutex_unlock(&per_pin->lock); 483 } 484 485 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) 486 { 487 char name[32]; 488 struct hda_codec *codec = per_pin->codec; 489 struct snd_info_entry *entry; 490 int err; 491 492 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); 493 err = snd_card_proc_new(codec->card, name, &entry); 494 if (err < 0) 495 return err; 496 497 snd_info_set_text_ops(entry, per_pin, print_eld_info); 498 entry->c.text.write = write_eld_info; 499 entry->mode |= 0200; 500 per_pin->proc_entry = entry; 501 502 return 0; 503 } 504 505 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 506 { 507 if (!per_pin->codec->bus->shutdown) { 508 snd_info_free_entry(per_pin->proc_entry); 509 per_pin->proc_entry = NULL; 510 } 511 } 512 #else 513 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, 514 int index) 515 { 516 return 0; 517 } 518 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 519 { 520 } 521 #endif 522 523 /* 524 * Audio InfoFrame routines 525 */ 526 527 /* 528 * Enable Audio InfoFrame Transmission 529 */ 530 static void hdmi_start_infoframe_trans(struct hda_codec *codec, 531 hda_nid_t pin_nid) 532 { 533 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 534 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 535 AC_DIPXMIT_BEST); 536 } 537 538 /* 539 * Disable Audio InfoFrame Transmission 540 */ 541 static void hdmi_stop_infoframe_trans(struct hda_codec *codec, 542 hda_nid_t pin_nid) 543 { 544 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 545 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 546 AC_DIPXMIT_DISABLE); 547 } 548 549 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) 550 { 551 #ifdef CONFIG_SND_DEBUG_VERBOSE 552 int i; 553 int size; 554 555 size = snd_hdmi_get_eld_size(codec, pin_nid); 556 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); 557 558 for (i = 0; i < 8; i++) { 559 size = snd_hda_codec_read(codec, pin_nid, 0, 560 AC_VERB_GET_HDMI_DIP_SIZE, i); 561 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); 562 } 563 #endif 564 } 565 566 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) 567 { 568 #ifdef BE_PARANOID 569 int i, j; 570 int size; 571 int pi, bi; 572 for (i = 0; i < 8; i++) { 573 size = snd_hda_codec_read(codec, pin_nid, 0, 574 AC_VERB_GET_HDMI_DIP_SIZE, i); 575 if (size == 0) 576 continue; 577 578 hdmi_set_dip_index(codec, pin_nid, i, 0x0); 579 for (j = 1; j < 1000; j++) { 580 hdmi_write_dip_byte(codec, pin_nid, 0x0); 581 hdmi_get_dip_index(codec, pin_nid, &pi, &bi); 582 if (pi != i) 583 codec_dbg(codec, "dip index %d: %d != %d\n", 584 bi, pi, i); 585 if (bi == 0) /* byte index wrapped around */ 586 break; 587 } 588 codec_dbg(codec, 589 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", 590 i, size, j); 591 } 592 #endif 593 } 594 595 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) 596 { 597 u8 *bytes = (u8 *)hdmi_ai; 598 u8 sum = 0; 599 int i; 600 601 hdmi_ai->checksum = 0; 602 603 for (i = 0; i < sizeof(*hdmi_ai); i++) 604 sum += bytes[i]; 605 606 hdmi_ai->checksum = -sum; 607 } 608 609 static void hdmi_fill_audio_infoframe(struct hda_codec *codec, 610 hda_nid_t pin_nid, 611 u8 *dip, int size) 612 { 613 int i; 614 615 hdmi_debug_dip_size(codec, pin_nid); 616 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ 617 618 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 619 for (i = 0; i < size; i++) 620 hdmi_write_dip_byte(codec, pin_nid, dip[i]); 621 } 622 623 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, 624 u8 *dip, int size) 625 { 626 u8 val; 627 int i; 628 629 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) 630 != AC_DIPXMIT_BEST) 631 return false; 632 633 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 634 for (i = 0; i < size; i++) { 635 val = snd_hda_codec_read(codec, pin_nid, 0, 636 AC_VERB_GET_HDMI_DIP_DATA, 0); 637 if (val != dip[i]) 638 return false; 639 } 640 641 return true; 642 } 643 644 static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 645 int dev_id, unsigned char *buf, int *eld_size) 646 { 647 snd_hda_set_dev_select(codec, nid, dev_id); 648 649 return snd_hdmi_get_eld(codec, nid, buf, eld_size); 650 } 651 652 static void hdmi_pin_setup_infoframe(struct hda_codec *codec, 653 hda_nid_t pin_nid, int dev_id, 654 int ca, int active_channels, 655 int conn_type) 656 { 657 union audio_infoframe ai; 658 659 memset(&ai, 0, sizeof(ai)); 660 if (conn_type == 0) { /* HDMI */ 661 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; 662 663 hdmi_ai->type = 0x84; 664 hdmi_ai->ver = 0x01; 665 hdmi_ai->len = 0x0a; 666 hdmi_ai->CC02_CT47 = active_channels - 1; 667 hdmi_ai->CA = ca; 668 hdmi_checksum_audio_infoframe(hdmi_ai); 669 } else if (conn_type == 1) { /* DisplayPort */ 670 struct dp_audio_infoframe *dp_ai = &ai.dp; 671 672 dp_ai->type = 0x84; 673 dp_ai->len = 0x1b; 674 dp_ai->ver = 0x11 << 2; 675 dp_ai->CC02_CT47 = active_channels - 1; 676 dp_ai->CA = ca; 677 } else { 678 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n", 679 pin_nid); 680 return; 681 } 682 683 snd_hda_set_dev_select(codec, pin_nid, dev_id); 684 685 /* 686 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or 687 * sizeof(*dp_ai) to avoid partial match/update problems when 688 * the user switches between HDMI/DP monitors. 689 */ 690 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, 691 sizeof(ai))) { 692 codec_dbg(codec, 693 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n", 694 pin_nid, 695 active_channels, ca); 696 hdmi_stop_infoframe_trans(codec, pin_nid); 697 hdmi_fill_audio_infoframe(codec, pin_nid, 698 ai.bytes, sizeof(ai)); 699 hdmi_start_infoframe_trans(codec, pin_nid); 700 } 701 } 702 703 static void hdmi_setup_audio_infoframe(struct hda_codec *codec, 704 struct hdmi_spec_per_pin *per_pin, 705 bool non_pcm) 706 { 707 struct hdmi_spec *spec = codec->spec; 708 struct hdac_chmap *chmap = &spec->chmap; 709 hda_nid_t pin_nid = per_pin->pin_nid; 710 int dev_id = per_pin->dev_id; 711 int channels = per_pin->channels; 712 int active_channels; 713 struct hdmi_eld *eld; 714 int ca; 715 716 if (!channels) 717 return; 718 719 snd_hda_set_dev_select(codec, pin_nid, dev_id); 720 721 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ 722 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 723 snd_hda_codec_write(codec, pin_nid, 0, 724 AC_VERB_SET_AMP_GAIN_MUTE, 725 AMP_OUT_UNMUTE); 726 727 eld = &per_pin->sink_eld; 728 729 ca = snd_hdac_channel_allocation(&codec->core, 730 eld->info.spk_alloc, channels, 731 per_pin->chmap_set, non_pcm, per_pin->chmap); 732 733 active_channels = snd_hdac_get_active_channels(ca); 734 735 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, 736 active_channels); 737 738 /* 739 * always configure channel mapping, it may have been changed by the 740 * user in the meantime 741 */ 742 snd_hdac_setup_channel_mapping(&spec->chmap, 743 pin_nid, non_pcm, ca, channels, 744 per_pin->chmap, per_pin->chmap_set); 745 746 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id, 747 ca, active_channels, eld->info.conn_type); 748 749 per_pin->non_pcm = non_pcm; 750 } 751 752 /* 753 * Unsolicited events 754 */ 755 756 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); 757 758 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, 759 int dev_id) 760 { 761 struct hdmi_spec *spec = codec->spec; 762 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); 763 764 if (pin_idx < 0) 765 return; 766 mutex_lock(&spec->pcm_lock); 767 if (hdmi_present_sense(get_pin(spec, pin_idx), 1)) 768 snd_hda_jack_report_sync(codec); 769 mutex_unlock(&spec->pcm_lock); 770 } 771 772 static void jack_callback(struct hda_codec *codec, 773 struct hda_jack_callback *jack) 774 { 775 /* stop polling when notification is enabled */ 776 if (codec_has_acomp(codec)) 777 return; 778 779 check_presence_and_report(codec, jack->nid, jack->dev_id); 780 } 781 782 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res) 783 { 784 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 785 struct hda_jack_tbl *jack; 786 787 if (codec->dp_mst) { 788 int dev_entry = 789 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 790 791 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry); 792 } else { 793 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0); 794 } 795 if (!jack) 796 return; 797 jack->jack_dirty = 1; 798 799 codec_dbg(codec, 800 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", 801 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA), 802 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); 803 804 check_presence_and_report(codec, jack->nid, jack->dev_id); 805 } 806 807 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) 808 { 809 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 810 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 811 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); 812 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); 813 814 codec_info(codec, 815 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", 816 codec->addr, 817 tag, 818 subtag, 819 cp_state, 820 cp_ready); 821 822 /* TODO */ 823 if (cp_state) 824 ; 825 if (cp_ready) 826 ; 827 } 828 829 830 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) 831 { 832 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 833 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 834 struct hda_jack_tbl *jack; 835 836 if (codec_has_acomp(codec)) 837 return; 838 839 if (codec->dp_mst) { 840 int dev_entry = 841 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 842 843 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry); 844 } else { 845 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0); 846 } 847 848 if (!jack) { 849 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); 850 return; 851 } 852 853 if (subtag == 0) 854 hdmi_intrinsic_event(codec, res); 855 else 856 hdmi_non_intrinsic_event(codec, res); 857 } 858 859 static void haswell_verify_D0(struct hda_codec *codec, 860 hda_nid_t cvt_nid, hda_nid_t nid) 861 { 862 int pwr; 863 864 /* For Haswell, the converter 1/2 may keep in D3 state after bootup, 865 * thus pins could only choose converter 0 for use. Make sure the 866 * converters are in correct power state */ 867 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) 868 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); 869 870 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { 871 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, 872 AC_PWRST_D0); 873 msleep(40); 874 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); 875 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; 876 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr); 877 } 878 } 879 880 /* 881 * Callbacks 882 */ 883 884 /* HBR should be Non-PCM, 8 channels */ 885 #define is_hbr_format(format) \ 886 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) 887 888 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 889 int dev_id, bool hbr) 890 { 891 int pinctl, new_pinctl; 892 893 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { 894 snd_hda_set_dev_select(codec, pin_nid, dev_id); 895 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 896 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 897 898 if (pinctl < 0) 899 return hbr ? -EINVAL : 0; 900 901 new_pinctl = pinctl & ~AC_PINCTL_EPT; 902 if (hbr) 903 new_pinctl |= AC_PINCTL_EPT_HBR; 904 else 905 new_pinctl |= AC_PINCTL_EPT_NATIVE; 906 907 codec_dbg(codec, 908 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", 909 pin_nid, 910 pinctl == new_pinctl ? "" : "new-", 911 new_pinctl); 912 913 if (pinctl != new_pinctl) 914 snd_hda_codec_write(codec, pin_nid, 0, 915 AC_VERB_SET_PIN_WIDGET_CONTROL, 916 new_pinctl); 917 } else if (hbr) 918 return -EINVAL; 919 920 return 0; 921 } 922 923 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 924 hda_nid_t pin_nid, int dev_id, 925 u32 stream_tag, int format) 926 { 927 struct hdmi_spec *spec = codec->spec; 928 unsigned int param; 929 int err; 930 931 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id, 932 is_hbr_format(format)); 933 934 if (err) { 935 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); 936 return err; 937 } 938 939 if (spec->intel_hsw_fixup) { 940 941 /* 942 * on recent platforms IEC Coding Type is required for HBR 943 * support, read current Digital Converter settings and set 944 * ICT bitfield if needed. 945 */ 946 param = snd_hda_codec_read(codec, cvt_nid, 0, 947 AC_VERB_GET_DIGI_CONVERT_1, 0); 948 949 param = (param >> 16) & ~(AC_DIG3_ICT); 950 951 /* on recent platforms ICT mode is required for HBR support */ 952 if (is_hbr_format(format)) 953 param |= 0x1; 954 955 snd_hda_codec_write(codec, cvt_nid, 0, 956 AC_VERB_SET_DIGI_CONVERT_3, param); 957 } 958 959 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); 960 return 0; 961 } 962 963 /* Try to find an available converter 964 * If pin_idx is less then zero, just try to find an available converter. 965 * Otherwise, try to find an available converter and get the cvt mux index 966 * of the pin. 967 */ 968 static int hdmi_choose_cvt(struct hda_codec *codec, 969 int pin_idx, int *cvt_id) 970 { 971 struct hdmi_spec *spec = codec->spec; 972 struct hdmi_spec_per_pin *per_pin; 973 struct hdmi_spec_per_cvt *per_cvt = NULL; 974 int cvt_idx, mux_idx = 0; 975 976 /* pin_idx < 0 means no pin will be bound to the converter */ 977 if (pin_idx < 0) 978 per_pin = NULL; 979 else 980 per_pin = get_pin(spec, pin_idx); 981 982 /* Dynamically assign converter to stream */ 983 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 984 per_cvt = get_cvt(spec, cvt_idx); 985 986 /* Must not already be assigned */ 987 if (per_cvt->assigned) 988 continue; 989 if (per_pin == NULL) 990 break; 991 /* Must be in pin's mux's list of converters */ 992 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 993 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) 994 break; 995 /* Not in mux list */ 996 if (mux_idx == per_pin->num_mux_nids) 997 continue; 998 break; 999 } 1000 1001 /* No free converters */ 1002 if (cvt_idx == spec->num_cvts) 1003 return -EBUSY; 1004 1005 if (per_pin != NULL) 1006 per_pin->mux_idx = mux_idx; 1007 1008 if (cvt_id) 1009 *cvt_id = cvt_idx; 1010 1011 return 0; 1012 } 1013 1014 /* Assure the pin select the right convetor */ 1015 static void intel_verify_pin_cvt_connect(struct hda_codec *codec, 1016 struct hdmi_spec_per_pin *per_pin) 1017 { 1018 hda_nid_t pin_nid = per_pin->pin_nid; 1019 int mux_idx, curr; 1020 1021 mux_idx = per_pin->mux_idx; 1022 curr = snd_hda_codec_read(codec, pin_nid, 0, 1023 AC_VERB_GET_CONNECT_SEL, 0); 1024 if (curr != mux_idx) 1025 snd_hda_codec_write_cache(codec, pin_nid, 0, 1026 AC_VERB_SET_CONNECT_SEL, 1027 mux_idx); 1028 } 1029 1030 /* get the mux index for the converter of the pins 1031 * converter's mux index is the same for all pins on Intel platform 1032 */ 1033 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, 1034 hda_nid_t cvt_nid) 1035 { 1036 int i; 1037 1038 for (i = 0; i < spec->num_cvts; i++) 1039 if (spec->cvt_nids[i] == cvt_nid) 1040 return i; 1041 return -EINVAL; 1042 } 1043 1044 /* Intel HDMI workaround to fix audio routing issue: 1045 * For some Intel display codecs, pins share the same connection list. 1046 * So a conveter can be selected by multiple pins and playback on any of these 1047 * pins will generate sound on the external display, because audio flows from 1048 * the same converter to the display pipeline. Also muting one pin may make 1049 * other pins have no sound output. 1050 * So this function assures that an assigned converter for a pin is not selected 1051 * by any other pins. 1052 */ 1053 static void intel_not_share_assigned_cvt(struct hda_codec *codec, 1054 hda_nid_t pin_nid, 1055 int dev_id, int mux_idx) 1056 { 1057 struct hdmi_spec *spec = codec->spec; 1058 hda_nid_t nid; 1059 int cvt_idx, curr; 1060 struct hdmi_spec_per_cvt *per_cvt; 1061 struct hdmi_spec_per_pin *per_pin; 1062 int pin_idx; 1063 1064 /* configure the pins connections */ 1065 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 1066 int dev_id_saved; 1067 int dev_num; 1068 1069 per_pin = get_pin(spec, pin_idx); 1070 /* 1071 * pin not connected to monitor 1072 * no need to operate on it 1073 */ 1074 if (!per_pin->pcm) 1075 continue; 1076 1077 if ((per_pin->pin_nid == pin_nid) && 1078 (per_pin->dev_id == dev_id)) 1079 continue; 1080 1081 /* 1082 * if per_pin->dev_id >= dev_num, 1083 * snd_hda_get_dev_select() will fail, 1084 * and the following operation is unpredictable. 1085 * So skip this situation. 1086 */ 1087 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; 1088 if (per_pin->dev_id >= dev_num) 1089 continue; 1090 1091 nid = per_pin->pin_nid; 1092 1093 /* 1094 * Calling this function should not impact 1095 * on the device entry selection 1096 * So let's save the dev id for each pin, 1097 * and restore it when return 1098 */ 1099 dev_id_saved = snd_hda_get_dev_select(codec, nid); 1100 snd_hda_set_dev_select(codec, nid, per_pin->dev_id); 1101 curr = snd_hda_codec_read(codec, nid, 0, 1102 AC_VERB_GET_CONNECT_SEL, 0); 1103 if (curr != mux_idx) { 1104 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1105 continue; 1106 } 1107 1108 1109 /* choose an unassigned converter. The conveters in the 1110 * connection list are in the same order as in the codec. 1111 */ 1112 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1113 per_cvt = get_cvt(spec, cvt_idx); 1114 if (!per_cvt->assigned) { 1115 codec_dbg(codec, 1116 "choose cvt %d for pin nid %d\n", 1117 cvt_idx, nid); 1118 snd_hda_codec_write_cache(codec, nid, 0, 1119 AC_VERB_SET_CONNECT_SEL, 1120 cvt_idx); 1121 break; 1122 } 1123 } 1124 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1125 } 1126 } 1127 1128 /* A wrapper of intel_not_share_asigned_cvt() */ 1129 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, 1130 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) 1131 { 1132 int mux_idx; 1133 struct hdmi_spec *spec = codec->spec; 1134 1135 /* On Intel platform, the mapping of converter nid to 1136 * mux index of the pins are always the same. 1137 * The pin nid may be 0, this means all pins will not 1138 * share the converter. 1139 */ 1140 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); 1141 if (mux_idx >= 0) 1142 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); 1143 } 1144 1145 /* skeleton caller of pin_cvt_fixup ops */ 1146 static void pin_cvt_fixup(struct hda_codec *codec, 1147 struct hdmi_spec_per_pin *per_pin, 1148 hda_nid_t cvt_nid) 1149 { 1150 struct hdmi_spec *spec = codec->spec; 1151 1152 if (spec->ops.pin_cvt_fixup) 1153 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); 1154 } 1155 1156 /* called in hdmi_pcm_open when no pin is assigned to the PCM 1157 * in dyn_pcm_assign mode. 1158 */ 1159 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, 1160 struct hda_codec *codec, 1161 struct snd_pcm_substream *substream) 1162 { 1163 struct hdmi_spec *spec = codec->spec; 1164 struct snd_pcm_runtime *runtime = substream->runtime; 1165 int cvt_idx, pcm_idx; 1166 struct hdmi_spec_per_cvt *per_cvt = NULL; 1167 int err; 1168 1169 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1170 if (pcm_idx < 0) 1171 return -EINVAL; 1172 1173 err = hdmi_choose_cvt(codec, -1, &cvt_idx); 1174 if (err) 1175 return err; 1176 1177 per_cvt = get_cvt(spec, cvt_idx); 1178 per_cvt->assigned = 1; 1179 hinfo->nid = per_cvt->cvt_nid; 1180 1181 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); 1182 1183 set_bit(pcm_idx, &spec->pcm_in_use); 1184 /* todo: setup spdif ctls assign */ 1185 1186 /* Initially set the converter's capabilities */ 1187 hinfo->channels_min = per_cvt->channels_min; 1188 hinfo->channels_max = per_cvt->channels_max; 1189 hinfo->rates = per_cvt->rates; 1190 hinfo->formats = per_cvt->formats; 1191 hinfo->maxbps = per_cvt->maxbps; 1192 1193 /* Store the updated parameters */ 1194 runtime->hw.channels_min = hinfo->channels_min; 1195 runtime->hw.channels_max = hinfo->channels_max; 1196 runtime->hw.formats = hinfo->formats; 1197 runtime->hw.rates = hinfo->rates; 1198 1199 snd_pcm_hw_constraint_step(substream->runtime, 0, 1200 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1201 return 0; 1202 } 1203 1204 /* 1205 * HDA PCM callbacks 1206 */ 1207 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, 1208 struct hda_codec *codec, 1209 struct snd_pcm_substream *substream) 1210 { 1211 struct hdmi_spec *spec = codec->spec; 1212 struct snd_pcm_runtime *runtime = substream->runtime; 1213 int pin_idx, cvt_idx, pcm_idx; 1214 struct hdmi_spec_per_pin *per_pin; 1215 struct hdmi_eld *eld; 1216 struct hdmi_spec_per_cvt *per_cvt = NULL; 1217 int err; 1218 1219 /* Validate hinfo */ 1220 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1221 if (pcm_idx < 0) 1222 return -EINVAL; 1223 1224 mutex_lock(&spec->pcm_lock); 1225 pin_idx = hinfo_to_pin_index(codec, hinfo); 1226 if (!spec->dyn_pcm_assign) { 1227 if (snd_BUG_ON(pin_idx < 0)) { 1228 err = -EINVAL; 1229 goto unlock; 1230 } 1231 } else { 1232 /* no pin is assigned to the PCM 1233 * PA need pcm open successfully when probe 1234 */ 1235 if (pin_idx < 0) { 1236 err = hdmi_pcm_open_no_pin(hinfo, codec, substream); 1237 goto unlock; 1238 } 1239 } 1240 1241 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx); 1242 if (err < 0) 1243 goto unlock; 1244 1245 per_cvt = get_cvt(spec, cvt_idx); 1246 /* Claim converter */ 1247 per_cvt->assigned = 1; 1248 1249 set_bit(pcm_idx, &spec->pcm_in_use); 1250 per_pin = get_pin(spec, pin_idx); 1251 per_pin->cvt_nid = per_cvt->cvt_nid; 1252 hinfo->nid = per_cvt->cvt_nid; 1253 1254 /* flip stripe flag for the assigned stream if supported */ 1255 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE) 1256 azx_stream(get_azx_dev(substream))->stripe = 1; 1257 1258 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1259 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1260 AC_VERB_SET_CONNECT_SEL, 1261 per_pin->mux_idx); 1262 1263 /* configure unused pins to choose other converters */ 1264 pin_cvt_fixup(codec, per_pin, 0); 1265 1266 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); 1267 1268 /* Initially set the converter's capabilities */ 1269 hinfo->channels_min = per_cvt->channels_min; 1270 hinfo->channels_max = per_cvt->channels_max; 1271 hinfo->rates = per_cvt->rates; 1272 hinfo->formats = per_cvt->formats; 1273 hinfo->maxbps = per_cvt->maxbps; 1274 1275 eld = &per_pin->sink_eld; 1276 /* Restrict capabilities by ELD if this isn't disabled */ 1277 if (!static_hdmi_pcm && eld->eld_valid) { 1278 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); 1279 if (hinfo->channels_min > hinfo->channels_max || 1280 !hinfo->rates || !hinfo->formats) { 1281 per_cvt->assigned = 0; 1282 hinfo->nid = 0; 1283 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1284 err = -ENODEV; 1285 goto unlock; 1286 } 1287 } 1288 1289 /* Store the updated parameters */ 1290 runtime->hw.channels_min = hinfo->channels_min; 1291 runtime->hw.channels_max = hinfo->channels_max; 1292 runtime->hw.formats = hinfo->formats; 1293 runtime->hw.rates = hinfo->rates; 1294 1295 snd_pcm_hw_constraint_step(substream->runtime, 0, 1296 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1297 unlock: 1298 mutex_unlock(&spec->pcm_lock); 1299 return err; 1300 } 1301 1302 /* 1303 * HDA/HDMI auto parsing 1304 */ 1305 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) 1306 { 1307 struct hdmi_spec *spec = codec->spec; 1308 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1309 hda_nid_t pin_nid = per_pin->pin_nid; 1310 int dev_id = per_pin->dev_id; 1311 int conns; 1312 1313 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { 1314 codec_warn(codec, 1315 "HDMI: pin %d wcaps %#x does not support connection list\n", 1316 pin_nid, get_wcaps(codec, pin_nid)); 1317 return -EINVAL; 1318 } 1319 1320 snd_hda_set_dev_select(codec, pin_nid, dev_id); 1321 1322 if (spec->intel_hsw_fixup) { 1323 conns = spec->num_cvts; 1324 memcpy(per_pin->mux_nids, spec->cvt_nids, 1325 sizeof(hda_nid_t) * conns); 1326 } else { 1327 conns = snd_hda_get_raw_connections(codec, pin_nid, 1328 per_pin->mux_nids, 1329 HDA_MAX_CONNECTIONS); 1330 } 1331 1332 /* all the device entries on the same pin have the same conn list */ 1333 per_pin->num_mux_nids = conns; 1334 1335 return 0; 1336 } 1337 1338 static int hdmi_find_pcm_slot(struct hdmi_spec *spec, 1339 struct hdmi_spec_per_pin *per_pin) 1340 { 1341 int i; 1342 1343 /* 1344 * generic_hdmi_build_pcms() may allocate extra PCMs on some 1345 * platforms (with maximum of 'num_nids + dev_num - 1') 1346 * 1347 * The per_pin of pin_nid_idx=n and dev_id=m prefers to get pcm-n 1348 * if m==0. This guarantees that dynamic pcm assignments are compatible 1349 * with the legacy static per_pin-pcm assignment that existed in the 1350 * days before DP-MST. 1351 * 1352 * Intel DP-MST prefers this legacy behavior for compatibility, too. 1353 * 1354 * per_pin of m!=0 prefers to get pcm=(num_nids + (m - 1)). 1355 */ 1356 1357 if (per_pin->dev_id == 0 || spec->intel_hsw_fixup) { 1358 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap)) 1359 return per_pin->pin_nid_idx; 1360 } else { 1361 i = spec->num_nids + (per_pin->dev_id - 1); 1362 if (i < spec->pcm_used && !(test_bit(i, &spec->pcm_bitmap))) 1363 return i; 1364 } 1365 1366 /* have a second try; check the area over num_nids */ 1367 for (i = spec->num_nids; i < spec->pcm_used; i++) { 1368 if (!test_bit(i, &spec->pcm_bitmap)) 1369 return i; 1370 } 1371 1372 /* the last try; check the empty slots in pins */ 1373 for (i = 0; i < spec->num_nids; i++) { 1374 if (!test_bit(i, &spec->pcm_bitmap)) 1375 return i; 1376 } 1377 return -EBUSY; 1378 } 1379 1380 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, 1381 struct hdmi_spec_per_pin *per_pin) 1382 { 1383 int idx; 1384 1385 /* pcm already be attached to the pin */ 1386 if (per_pin->pcm) 1387 return; 1388 idx = hdmi_find_pcm_slot(spec, per_pin); 1389 if (idx == -EBUSY) 1390 return; 1391 per_pin->pcm_idx = idx; 1392 per_pin->pcm = get_hdmi_pcm(spec, idx); 1393 set_bit(idx, &spec->pcm_bitmap); 1394 } 1395 1396 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, 1397 struct hdmi_spec_per_pin *per_pin) 1398 { 1399 int idx; 1400 1401 /* pcm already be detached from the pin */ 1402 if (!per_pin->pcm) 1403 return; 1404 idx = per_pin->pcm_idx; 1405 per_pin->pcm_idx = -1; 1406 per_pin->pcm = NULL; 1407 if (idx >= 0 && idx < spec->pcm_used) 1408 clear_bit(idx, &spec->pcm_bitmap); 1409 } 1410 1411 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, 1412 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) 1413 { 1414 int mux_idx; 1415 1416 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1417 if (per_pin->mux_nids[mux_idx] == cvt_nid) 1418 break; 1419 return mux_idx; 1420 } 1421 1422 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); 1423 1424 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, 1425 struct hdmi_spec_per_pin *per_pin) 1426 { 1427 struct hda_codec *codec = per_pin->codec; 1428 struct hda_pcm *pcm; 1429 struct hda_pcm_stream *hinfo; 1430 struct snd_pcm_substream *substream; 1431 int mux_idx; 1432 bool non_pcm; 1433 1434 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1435 pcm = get_pcm_rec(spec, per_pin->pcm_idx); 1436 else 1437 return; 1438 if (!pcm->pcm) 1439 return; 1440 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) 1441 return; 1442 1443 /* hdmi audio only uses playback and one substream */ 1444 hinfo = pcm->stream; 1445 substream = pcm->pcm->streams[0].substream; 1446 1447 per_pin->cvt_nid = hinfo->nid; 1448 1449 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); 1450 if (mux_idx < per_pin->num_mux_nids) { 1451 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1452 per_pin->dev_id); 1453 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1454 AC_VERB_SET_CONNECT_SEL, 1455 mux_idx); 1456 } 1457 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); 1458 1459 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); 1460 if (substream->runtime) 1461 per_pin->channels = substream->runtime->channels; 1462 per_pin->setup = true; 1463 per_pin->mux_idx = mux_idx; 1464 1465 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1466 } 1467 1468 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, 1469 struct hdmi_spec_per_pin *per_pin) 1470 { 1471 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1472 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); 1473 1474 per_pin->chmap_set = false; 1475 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1476 1477 per_pin->setup = false; 1478 per_pin->channels = 0; 1479 } 1480 1481 /* update per_pin ELD from the given new ELD; 1482 * setup info frame and notification accordingly 1483 */ 1484 static bool update_eld(struct hda_codec *codec, 1485 struct hdmi_spec_per_pin *per_pin, 1486 struct hdmi_eld *eld) 1487 { 1488 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 1489 struct hdmi_spec *spec = codec->spec; 1490 bool old_eld_valid = pin_eld->eld_valid; 1491 bool eld_changed; 1492 int pcm_idx; 1493 1494 /* for monitor disconnection, save pcm_idx firstly */ 1495 pcm_idx = per_pin->pcm_idx; 1496 if (spec->dyn_pcm_assign) { 1497 if (eld->eld_valid) { 1498 hdmi_attach_hda_pcm(spec, per_pin); 1499 hdmi_pcm_setup_pin(spec, per_pin); 1500 } else { 1501 hdmi_pcm_reset_pin(spec, per_pin); 1502 hdmi_detach_hda_pcm(spec, per_pin); 1503 } 1504 } 1505 /* if pcm_idx == -1, it means this is in monitor connection event 1506 * we can get the correct pcm_idx now. 1507 */ 1508 if (pcm_idx == -1) 1509 pcm_idx = per_pin->pcm_idx; 1510 1511 if (eld->eld_valid) 1512 snd_hdmi_show_eld(codec, &eld->info); 1513 1514 eld_changed = (pin_eld->eld_valid != eld->eld_valid); 1515 eld_changed |= (pin_eld->monitor_present != eld->monitor_present); 1516 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid) 1517 if (pin_eld->eld_size != eld->eld_size || 1518 memcmp(pin_eld->eld_buffer, eld->eld_buffer, 1519 eld->eld_size) != 0) 1520 eld_changed = true; 1521 1522 if (eld_changed) { 1523 pin_eld->monitor_present = eld->monitor_present; 1524 pin_eld->eld_valid = eld->eld_valid; 1525 pin_eld->eld_size = eld->eld_size; 1526 if (eld->eld_valid) 1527 memcpy(pin_eld->eld_buffer, eld->eld_buffer, 1528 eld->eld_size); 1529 pin_eld->info = eld->info; 1530 } 1531 1532 /* 1533 * Re-setup pin and infoframe. This is needed e.g. when 1534 * - sink is first plugged-in 1535 * - transcoder can change during stream playback on Haswell 1536 * and this can make HW reset converter selection on a pin. 1537 */ 1538 if (eld->eld_valid && !old_eld_valid && per_pin->setup) { 1539 pin_cvt_fixup(codec, per_pin, 0); 1540 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1541 } 1542 1543 if (eld_changed && pcm_idx >= 0) 1544 snd_ctl_notify(codec->card, 1545 SNDRV_CTL_EVENT_MASK_VALUE | 1546 SNDRV_CTL_EVENT_MASK_INFO, 1547 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); 1548 return eld_changed; 1549 } 1550 1551 /* update ELD and jack state via HD-audio verbs */ 1552 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, 1553 int repoll) 1554 { 1555 struct hda_jack_tbl *jack; 1556 struct hda_codec *codec = per_pin->codec; 1557 struct hdmi_spec *spec = codec->spec; 1558 struct hdmi_eld *eld = &spec->temp_eld; 1559 hda_nid_t pin_nid = per_pin->pin_nid; 1560 int dev_id = per_pin->dev_id; 1561 /* 1562 * Always execute a GetPinSense verb here, even when called from 1563 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited 1564 * response's PD bit is not the real PD value, but indicates that 1565 * the real PD value changed. An older version of the HD-audio 1566 * specification worked this way. Hence, we just ignore the data in 1567 * the unsolicited response to avoid custom WARs. 1568 */ 1569 int present; 1570 bool ret; 1571 bool do_repoll = false; 1572 1573 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id); 1574 1575 mutex_lock(&per_pin->lock); 1576 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); 1577 if (eld->monitor_present) 1578 eld->eld_valid = !!(present & AC_PINSENSE_ELDV); 1579 else 1580 eld->eld_valid = false; 1581 1582 codec_dbg(codec, 1583 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n", 1584 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); 1585 1586 if (eld->eld_valid) { 1587 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id, 1588 eld->eld_buffer, &eld->eld_size) < 0) 1589 eld->eld_valid = false; 1590 else { 1591 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, 1592 eld->eld_size) < 0) 1593 eld->eld_valid = false; 1594 } 1595 if (!eld->eld_valid && repoll) 1596 do_repoll = true; 1597 } 1598 1599 if (do_repoll) 1600 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300)); 1601 else 1602 update_eld(codec, per_pin, eld); 1603 1604 ret = !repoll || !eld->monitor_present || eld->eld_valid; 1605 1606 jack = snd_hda_jack_tbl_get_mst(codec, pin_nid, per_pin->dev_id); 1607 if (jack) { 1608 jack->block_report = !ret; 1609 jack->pin_sense = (eld->monitor_present && eld->eld_valid) ? 1610 AC_PINSENSE_PRESENCE : 0; 1611 } 1612 mutex_unlock(&per_pin->lock); 1613 return ret; 1614 } 1615 1616 static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec, 1617 struct hdmi_spec_per_pin *per_pin) 1618 { 1619 struct hdmi_spec *spec = codec->spec; 1620 struct snd_jack *jack = NULL; 1621 struct hda_jack_tbl *jack_tbl; 1622 1623 /* if !dyn_pcm_assign, get jack from hda_jack_tbl 1624 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not 1625 * NULL even after snd_hda_jack_tbl_clear() is called to 1626 * free snd_jack. This may cause access invalid memory 1627 * when calling snd_jack_report 1628 */ 1629 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign) 1630 jack = spec->pcm_rec[per_pin->pcm_idx].jack; 1631 else if (!spec->dyn_pcm_assign) { 1632 /* 1633 * jack tbl doesn't support DP MST 1634 * DP MST will use dyn_pcm_assign, 1635 * so DP MST will never come here 1636 */ 1637 jack_tbl = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid, 1638 per_pin->dev_id); 1639 if (jack_tbl) 1640 jack = jack_tbl->jack; 1641 } 1642 return jack; 1643 } 1644 1645 /* update ELD and jack state via audio component */ 1646 static void sync_eld_via_acomp(struct hda_codec *codec, 1647 struct hdmi_spec_per_pin *per_pin) 1648 { 1649 struct hdmi_spec *spec = codec->spec; 1650 struct hdmi_eld *eld = &spec->temp_eld; 1651 struct snd_jack *jack = NULL; 1652 bool changed; 1653 int size; 1654 1655 mutex_lock(&per_pin->lock); 1656 eld->monitor_present = false; 1657 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, 1658 per_pin->dev_id, &eld->monitor_present, 1659 eld->eld_buffer, ELD_MAX_SIZE); 1660 if (size > 0) { 1661 size = min(size, ELD_MAX_SIZE); 1662 if (snd_hdmi_parse_eld(codec, &eld->info, 1663 eld->eld_buffer, size) < 0) 1664 size = -EINVAL; 1665 } 1666 1667 if (size > 0) { 1668 eld->eld_valid = true; 1669 eld->eld_size = size; 1670 } else { 1671 eld->eld_valid = false; 1672 eld->eld_size = 0; 1673 } 1674 1675 /* pcm_idx >=0 before update_eld() means it is in monitor 1676 * disconnected event. Jack must be fetched before update_eld() 1677 */ 1678 jack = pin_idx_to_jack(codec, per_pin); 1679 changed = update_eld(codec, per_pin, eld); 1680 if (jack == NULL) 1681 jack = pin_idx_to_jack(codec, per_pin); 1682 if (changed && jack) 1683 snd_jack_report(jack, 1684 (eld->monitor_present && eld->eld_valid) ? 1685 SND_JACK_AVOUT : 0); 1686 mutex_unlock(&per_pin->lock); 1687 } 1688 1689 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) 1690 { 1691 struct hda_codec *codec = per_pin->codec; 1692 int ret; 1693 1694 /* no temporary power up/down needed for component notifier */ 1695 if (!codec_has_acomp(codec)) { 1696 ret = snd_hda_power_up_pm(codec); 1697 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) { 1698 snd_hda_power_down_pm(codec); 1699 return false; 1700 } 1701 ret = hdmi_present_sense_via_verbs(per_pin, repoll); 1702 snd_hda_power_down_pm(codec); 1703 } else { 1704 sync_eld_via_acomp(codec, per_pin); 1705 ret = false; /* don't call snd_hda_jack_report_sync() */ 1706 } 1707 1708 return ret; 1709 } 1710 1711 static void hdmi_repoll_eld(struct work_struct *work) 1712 { 1713 struct hdmi_spec_per_pin *per_pin = 1714 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); 1715 struct hda_codec *codec = per_pin->codec; 1716 struct hdmi_spec *spec = codec->spec; 1717 struct hda_jack_tbl *jack; 1718 1719 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid, 1720 per_pin->dev_id); 1721 if (jack) 1722 jack->jack_dirty = 1; 1723 1724 if (per_pin->repoll_count++ > 6) 1725 per_pin->repoll_count = 0; 1726 1727 mutex_lock(&spec->pcm_lock); 1728 if (hdmi_present_sense(per_pin, per_pin->repoll_count)) 1729 snd_hda_jack_report_sync(per_pin->codec); 1730 mutex_unlock(&spec->pcm_lock); 1731 } 1732 1733 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) 1734 { 1735 struct hdmi_spec *spec = codec->spec; 1736 unsigned int caps, config; 1737 int pin_idx; 1738 struct hdmi_spec_per_pin *per_pin; 1739 int err; 1740 int dev_num, i; 1741 1742 caps = snd_hda_query_pin_caps(codec, pin_nid); 1743 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) 1744 return 0; 1745 1746 /* 1747 * For DP MST audio, Configuration Default is the same for 1748 * all device entries on the same pin 1749 */ 1750 config = snd_hda_codec_get_pincfg(codec, pin_nid); 1751 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE) 1752 return 0; 1753 1754 /* 1755 * To simplify the implementation, malloc all 1756 * the virtual pins in the initialization statically 1757 */ 1758 if (spec->intel_hsw_fixup) { 1759 /* 1760 * On Intel platforms, device entries number is 1761 * changed dynamically. If there is a DP MST 1762 * hub connected, the device entries number is 3. 1763 * Otherwise, it is 1. 1764 * Here we manually set dev_num to 3, so that 1765 * we can initialize all the device entries when 1766 * bootup statically. 1767 */ 1768 dev_num = 3; 1769 spec->dev_num = 3; 1770 } else if (spec->dyn_pcm_assign && codec->dp_mst) { 1771 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; 1772 /* 1773 * spec->dev_num is the maxinum number of device entries 1774 * among all the pins 1775 */ 1776 spec->dev_num = (spec->dev_num > dev_num) ? 1777 spec->dev_num : dev_num; 1778 } else { 1779 /* 1780 * If the platform doesn't support DP MST, 1781 * manually set dev_num to 1. This means 1782 * the pin has only one device entry. 1783 */ 1784 dev_num = 1; 1785 spec->dev_num = 1; 1786 } 1787 1788 for (i = 0; i < dev_num; i++) { 1789 pin_idx = spec->num_pins; 1790 per_pin = snd_array_new(&spec->pins); 1791 1792 if (!per_pin) 1793 return -ENOMEM; 1794 1795 if (spec->dyn_pcm_assign) { 1796 per_pin->pcm = NULL; 1797 per_pin->pcm_idx = -1; 1798 } else { 1799 per_pin->pcm = get_hdmi_pcm(spec, pin_idx); 1800 per_pin->pcm_idx = pin_idx; 1801 } 1802 per_pin->pin_nid = pin_nid; 1803 per_pin->pin_nid_idx = spec->num_nids; 1804 per_pin->dev_id = i; 1805 per_pin->non_pcm = false; 1806 snd_hda_set_dev_select(codec, pin_nid, i); 1807 err = hdmi_read_pin_conn(codec, pin_idx); 1808 if (err < 0) 1809 return err; 1810 spec->num_pins++; 1811 } 1812 spec->num_nids++; 1813 1814 return 0; 1815 } 1816 1817 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1818 { 1819 struct hdmi_spec *spec = codec->spec; 1820 struct hdmi_spec_per_cvt *per_cvt; 1821 unsigned int chans; 1822 int err; 1823 1824 chans = get_wcaps(codec, cvt_nid); 1825 chans = get_wcaps_channels(chans); 1826 1827 per_cvt = snd_array_new(&spec->cvts); 1828 if (!per_cvt) 1829 return -ENOMEM; 1830 1831 per_cvt->cvt_nid = cvt_nid; 1832 per_cvt->channels_min = 2; 1833 if (chans <= 16) { 1834 per_cvt->channels_max = chans; 1835 if (chans > spec->chmap.channels_max) 1836 spec->chmap.channels_max = chans; 1837 } 1838 1839 err = snd_hda_query_supported_pcm(codec, cvt_nid, 1840 &per_cvt->rates, 1841 &per_cvt->formats, 1842 &per_cvt->maxbps); 1843 if (err < 0) 1844 return err; 1845 1846 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) 1847 spec->cvt_nids[spec->num_cvts] = cvt_nid; 1848 spec->num_cvts++; 1849 1850 return 0; 1851 } 1852 1853 static int hdmi_parse_codec(struct hda_codec *codec) 1854 { 1855 hda_nid_t nid; 1856 int i, nodes; 1857 1858 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid); 1859 if (!nid || nodes < 0) { 1860 codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); 1861 return -EINVAL; 1862 } 1863 1864 for (i = 0; i < nodes; i++, nid++) { 1865 unsigned int caps; 1866 unsigned int type; 1867 1868 caps = get_wcaps(codec, nid); 1869 type = get_wcaps_type(caps); 1870 1871 if (!(caps & AC_WCAP_DIGITAL)) 1872 continue; 1873 1874 switch (type) { 1875 case AC_WID_AUD_OUT: 1876 hdmi_add_cvt(codec, nid); 1877 break; 1878 case AC_WID_PIN: 1879 hdmi_add_pin(codec, nid); 1880 break; 1881 } 1882 } 1883 1884 return 0; 1885 } 1886 1887 /* 1888 */ 1889 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1890 { 1891 struct hda_spdif_out *spdif; 1892 bool non_pcm; 1893 1894 mutex_lock(&codec->spdif_mutex); 1895 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); 1896 /* Add sanity check to pass klockwork check. 1897 * This should never happen. 1898 */ 1899 if (WARN_ON(spdif == NULL)) 1900 return true; 1901 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); 1902 mutex_unlock(&codec->spdif_mutex); 1903 return non_pcm; 1904 } 1905 1906 /* 1907 * HDMI callbacks 1908 */ 1909 1910 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 1911 struct hda_codec *codec, 1912 unsigned int stream_tag, 1913 unsigned int format, 1914 struct snd_pcm_substream *substream) 1915 { 1916 hda_nid_t cvt_nid = hinfo->nid; 1917 struct hdmi_spec *spec = codec->spec; 1918 int pin_idx; 1919 struct hdmi_spec_per_pin *per_pin; 1920 struct snd_pcm_runtime *runtime = substream->runtime; 1921 bool non_pcm; 1922 int pinctl, stripe; 1923 int err = 0; 1924 1925 mutex_lock(&spec->pcm_lock); 1926 pin_idx = hinfo_to_pin_index(codec, hinfo); 1927 if (spec->dyn_pcm_assign && pin_idx < 0) { 1928 /* when dyn_pcm_assign and pcm is not bound to a pin 1929 * skip pin setup and return 0 to make audio playback 1930 * be ongoing 1931 */ 1932 pin_cvt_fixup(codec, NULL, cvt_nid); 1933 snd_hda_codec_setup_stream(codec, cvt_nid, 1934 stream_tag, 0, format); 1935 goto unlock; 1936 } 1937 1938 if (snd_BUG_ON(pin_idx < 0)) { 1939 err = -EINVAL; 1940 goto unlock; 1941 } 1942 per_pin = get_pin(spec, pin_idx); 1943 1944 /* Verify pin:cvt selections to avoid silent audio after S3. 1945 * After S3, the audio driver restores pin:cvt selections 1946 * but this can happen before gfx is ready and such selection 1947 * is overlooked by HW. Thus multiple pins can share a same 1948 * default convertor and mute control will affect each other, 1949 * which can cause a resumed audio playback become silent 1950 * after S3. 1951 */ 1952 pin_cvt_fixup(codec, per_pin, 0); 1953 1954 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ 1955 /* Todo: add DP1.2 MST audio support later */ 1956 if (codec_has_acomp(codec)) 1957 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, 1958 per_pin->dev_id, runtime->rate); 1959 1960 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); 1961 mutex_lock(&per_pin->lock); 1962 per_pin->channels = substream->runtime->channels; 1963 per_pin->setup = true; 1964 1965 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) { 1966 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core, 1967 substream); 1968 snd_hda_codec_write(codec, cvt_nid, 0, 1969 AC_VERB_SET_STRIPE_CONTROL, 1970 stripe); 1971 } 1972 1973 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1974 mutex_unlock(&per_pin->lock); 1975 if (spec->dyn_pin_out) { 1976 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1977 per_pin->dev_id); 1978 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 1979 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 1980 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 1981 AC_VERB_SET_PIN_WIDGET_CONTROL, 1982 pinctl | PIN_OUT); 1983 } 1984 1985 /* snd_hda_set_dev_select() has been called before */ 1986 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid, 1987 per_pin->dev_id, stream_tag, format); 1988 unlock: 1989 mutex_unlock(&spec->pcm_lock); 1990 return err; 1991 } 1992 1993 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 1994 struct hda_codec *codec, 1995 struct snd_pcm_substream *substream) 1996 { 1997 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 1998 return 0; 1999 } 2000 2001 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, 2002 struct hda_codec *codec, 2003 struct snd_pcm_substream *substream) 2004 { 2005 struct hdmi_spec *spec = codec->spec; 2006 int cvt_idx, pin_idx, pcm_idx; 2007 struct hdmi_spec_per_cvt *per_cvt; 2008 struct hdmi_spec_per_pin *per_pin; 2009 int pinctl; 2010 int err = 0; 2011 2012 if (hinfo->nid) { 2013 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 2014 if (snd_BUG_ON(pcm_idx < 0)) 2015 return -EINVAL; 2016 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); 2017 if (snd_BUG_ON(cvt_idx < 0)) 2018 return -EINVAL; 2019 per_cvt = get_cvt(spec, cvt_idx); 2020 2021 snd_BUG_ON(!per_cvt->assigned); 2022 per_cvt->assigned = 0; 2023 hinfo->nid = 0; 2024 2025 azx_stream(get_azx_dev(substream))->stripe = 0; 2026 2027 mutex_lock(&spec->pcm_lock); 2028 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2029 clear_bit(pcm_idx, &spec->pcm_in_use); 2030 pin_idx = hinfo_to_pin_index(codec, hinfo); 2031 if (spec->dyn_pcm_assign && pin_idx < 0) 2032 goto unlock; 2033 2034 if (snd_BUG_ON(pin_idx < 0)) { 2035 err = -EINVAL; 2036 goto unlock; 2037 } 2038 per_pin = get_pin(spec, pin_idx); 2039 2040 if (spec->dyn_pin_out) { 2041 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2042 per_pin->dev_id); 2043 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2044 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2045 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2046 AC_VERB_SET_PIN_WIDGET_CONTROL, 2047 pinctl & ~PIN_OUT); 2048 } 2049 2050 mutex_lock(&per_pin->lock); 2051 per_pin->chmap_set = false; 2052 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 2053 2054 per_pin->setup = false; 2055 per_pin->channels = 0; 2056 mutex_unlock(&per_pin->lock); 2057 unlock: 2058 mutex_unlock(&spec->pcm_lock); 2059 } 2060 2061 return err; 2062 } 2063 2064 static const struct hda_pcm_ops generic_ops = { 2065 .open = hdmi_pcm_open, 2066 .close = hdmi_pcm_close, 2067 .prepare = generic_hdmi_playback_pcm_prepare, 2068 .cleanup = generic_hdmi_playback_pcm_cleanup, 2069 }; 2070 2071 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) 2072 { 2073 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2074 struct hdmi_spec *spec = codec->spec; 2075 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2076 2077 if (!per_pin) 2078 return 0; 2079 2080 return per_pin->sink_eld.info.spk_alloc; 2081 } 2082 2083 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, 2084 unsigned char *chmap) 2085 { 2086 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2087 struct hdmi_spec *spec = codec->spec; 2088 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2089 2090 /* chmap is already set to 0 in caller */ 2091 if (!per_pin) 2092 return; 2093 2094 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); 2095 } 2096 2097 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, 2098 unsigned char *chmap, int prepared) 2099 { 2100 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2101 struct hdmi_spec *spec = codec->spec; 2102 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2103 2104 if (!per_pin) 2105 return; 2106 mutex_lock(&per_pin->lock); 2107 per_pin->chmap_set = true; 2108 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); 2109 if (prepared) 2110 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 2111 mutex_unlock(&per_pin->lock); 2112 } 2113 2114 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) 2115 { 2116 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2117 struct hdmi_spec *spec = codec->spec; 2118 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2119 2120 return per_pin ? true:false; 2121 } 2122 2123 static int generic_hdmi_build_pcms(struct hda_codec *codec) 2124 { 2125 struct hdmi_spec *spec = codec->spec; 2126 int idx, pcm_num; 2127 2128 /* 2129 * for non-mst mode, pcm number is the same as before 2130 * for DP MST mode without extra PCM, pcm number is same 2131 * for DP MST mode with extra PCMs, pcm number is 2132 * (nid number + dev_num - 1) 2133 * dev_num is the device entry number in a pin 2134 */ 2135 2136 if (codec->mst_no_extra_pcms) 2137 pcm_num = spec->num_nids; 2138 else 2139 pcm_num = spec->num_nids + spec->dev_num - 1; 2140 2141 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num); 2142 2143 for (idx = 0; idx < pcm_num; idx++) { 2144 struct hda_pcm *info; 2145 struct hda_pcm_stream *pstr; 2146 2147 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); 2148 if (!info) 2149 return -ENOMEM; 2150 2151 spec->pcm_rec[idx].pcm = info; 2152 spec->pcm_used++; 2153 info->pcm_type = HDA_PCM_TYPE_HDMI; 2154 info->own_chmap = true; 2155 2156 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2157 pstr->substreams = 1; 2158 pstr->ops = generic_ops; 2159 /* pcm number is less than 16 */ 2160 if (spec->pcm_used >= 16) 2161 break; 2162 /* other pstr fields are set in open */ 2163 } 2164 2165 return 0; 2166 } 2167 2168 static void free_hdmi_jack_priv(struct snd_jack *jack) 2169 { 2170 struct hdmi_pcm *pcm = jack->private_data; 2171 2172 pcm->jack = NULL; 2173 } 2174 2175 static int add_hdmi_jack_kctl(struct hda_codec *codec, 2176 struct hdmi_spec *spec, 2177 int pcm_idx, 2178 const char *name) 2179 { 2180 struct snd_jack *jack; 2181 int err; 2182 2183 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack, 2184 true, false); 2185 if (err < 0) 2186 return err; 2187 2188 spec->pcm_rec[pcm_idx].jack = jack; 2189 jack->private_data = &spec->pcm_rec[pcm_idx]; 2190 jack->private_free = free_hdmi_jack_priv; 2191 return 0; 2192 } 2193 2194 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) 2195 { 2196 char hdmi_str[32] = "HDMI/DP"; 2197 struct hdmi_spec *spec = codec->spec; 2198 struct hdmi_spec_per_pin *per_pin; 2199 struct hda_jack_tbl *jack; 2200 int pcmdev = get_pcm_rec(spec, pcm_idx)->device; 2201 bool phantom_jack; 2202 int ret; 2203 2204 if (pcmdev > 0) 2205 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); 2206 2207 if (spec->dyn_pcm_assign) 2208 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str); 2209 2210 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */ 2211 /* if !dyn_pcm_assign, it must be non-MST mode. 2212 * This means pcms and pins are statically mapped. 2213 * And pcm_idx is pin_idx. 2214 */ 2215 per_pin = get_pin(spec, pcm_idx); 2216 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid); 2217 if (phantom_jack) 2218 strncat(hdmi_str, " Phantom", 2219 sizeof(hdmi_str) - strlen(hdmi_str) - 1); 2220 ret = snd_hda_jack_add_kctl_mst(codec, per_pin->pin_nid, 2221 per_pin->dev_id, hdmi_str, phantom_jack, 2222 0, NULL); 2223 if (ret < 0) 2224 return ret; 2225 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid, 2226 per_pin->dev_id); 2227 if (jack == NULL) 2228 return 0; 2229 /* assign jack->jack to pcm_rec[].jack to 2230 * align with dyn_pcm_assign mode 2231 */ 2232 spec->pcm_rec[pcm_idx].jack = jack->jack; 2233 return 0; 2234 } 2235 2236 static int generic_hdmi_build_controls(struct hda_codec *codec) 2237 { 2238 struct hdmi_spec *spec = codec->spec; 2239 int dev, err; 2240 int pin_idx, pcm_idx; 2241 2242 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2243 if (!get_pcm_rec(spec, pcm_idx)->pcm) { 2244 /* no PCM: mark this for skipping permanently */ 2245 set_bit(pcm_idx, &spec->pcm_bitmap); 2246 continue; 2247 } 2248 2249 err = generic_hdmi_build_jack(codec, pcm_idx); 2250 if (err < 0) 2251 return err; 2252 2253 /* create the spdif for each pcm 2254 * pin will be bound when monitor is connected 2255 */ 2256 if (spec->dyn_pcm_assign) 2257 err = snd_hda_create_dig_out_ctls(codec, 2258 0, spec->cvt_nids[0], 2259 HDA_PCM_TYPE_HDMI); 2260 else { 2261 struct hdmi_spec_per_pin *per_pin = 2262 get_pin(spec, pcm_idx); 2263 err = snd_hda_create_dig_out_ctls(codec, 2264 per_pin->pin_nid, 2265 per_pin->mux_nids[0], 2266 HDA_PCM_TYPE_HDMI); 2267 } 2268 if (err < 0) 2269 return err; 2270 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2271 2272 dev = get_pcm_rec(spec, pcm_idx)->device; 2273 if (dev != SNDRV_PCM_INVALID_DEVICE) { 2274 /* add control for ELD Bytes */ 2275 err = hdmi_create_eld_ctl(codec, pcm_idx, dev); 2276 if (err < 0) 2277 return err; 2278 } 2279 } 2280 2281 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2282 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2283 2284 hdmi_present_sense(per_pin, 0); 2285 } 2286 2287 /* add channel maps */ 2288 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2289 struct hda_pcm *pcm; 2290 2291 pcm = get_pcm_rec(spec, pcm_idx); 2292 if (!pcm || !pcm->pcm) 2293 break; 2294 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); 2295 if (err < 0) 2296 return err; 2297 } 2298 2299 return 0; 2300 } 2301 2302 static int generic_hdmi_init_per_pins(struct hda_codec *codec) 2303 { 2304 struct hdmi_spec *spec = codec->spec; 2305 int pin_idx; 2306 2307 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2308 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2309 2310 per_pin->codec = codec; 2311 mutex_init(&per_pin->lock); 2312 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); 2313 eld_proc_new(per_pin, pin_idx); 2314 } 2315 return 0; 2316 } 2317 2318 static int generic_hdmi_init(struct hda_codec *codec) 2319 { 2320 struct hdmi_spec *spec = codec->spec; 2321 int pin_idx; 2322 2323 mutex_lock(&spec->bind_lock); 2324 spec->use_jack_detect = !codec->jackpoll_interval; 2325 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2326 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2327 hda_nid_t pin_nid = per_pin->pin_nid; 2328 int dev_id = per_pin->dev_id; 2329 2330 snd_hda_set_dev_select(codec, pin_nid, dev_id); 2331 hdmi_init_pin(codec, pin_nid); 2332 if (codec_has_acomp(codec)) 2333 continue; 2334 if (spec->use_jack_detect) 2335 snd_hda_jack_detect_enable(codec, pin_nid, dev_id); 2336 else 2337 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, 2338 dev_id, 2339 jack_callback); 2340 } 2341 mutex_unlock(&spec->bind_lock); 2342 return 0; 2343 } 2344 2345 static void hdmi_array_init(struct hdmi_spec *spec, int nums) 2346 { 2347 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); 2348 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); 2349 } 2350 2351 static void hdmi_array_free(struct hdmi_spec *spec) 2352 { 2353 snd_array_free(&spec->pins); 2354 snd_array_free(&spec->cvts); 2355 } 2356 2357 static void generic_spec_free(struct hda_codec *codec) 2358 { 2359 struct hdmi_spec *spec = codec->spec; 2360 2361 if (spec) { 2362 hdmi_array_free(spec); 2363 kfree(spec); 2364 codec->spec = NULL; 2365 } 2366 codec->dp_mst = false; 2367 } 2368 2369 static void generic_hdmi_free(struct hda_codec *codec) 2370 { 2371 struct hdmi_spec *spec = codec->spec; 2372 int pin_idx, pcm_idx; 2373 2374 if (spec->acomp_registered) { 2375 snd_hdac_acomp_exit(&codec->bus->core); 2376 } else if (codec_has_acomp(codec)) { 2377 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL); 2378 } 2379 codec->relaxed_resume = 0; 2380 2381 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2382 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2383 cancel_delayed_work_sync(&per_pin->work); 2384 eld_proc_free(per_pin); 2385 } 2386 2387 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2388 if (spec->pcm_rec[pcm_idx].jack == NULL) 2389 continue; 2390 if (spec->dyn_pcm_assign) 2391 snd_device_free(codec->card, 2392 spec->pcm_rec[pcm_idx].jack); 2393 else 2394 spec->pcm_rec[pcm_idx].jack = NULL; 2395 } 2396 2397 generic_spec_free(codec); 2398 } 2399 2400 #ifdef CONFIG_PM 2401 static int generic_hdmi_resume(struct hda_codec *codec) 2402 { 2403 struct hdmi_spec *spec = codec->spec; 2404 int pin_idx; 2405 2406 codec->patch_ops.init(codec); 2407 regcache_sync(codec->core.regmap); 2408 2409 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2410 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2411 hdmi_present_sense(per_pin, 1); 2412 } 2413 return 0; 2414 } 2415 #endif 2416 2417 static const struct hda_codec_ops generic_hdmi_patch_ops = { 2418 .init = generic_hdmi_init, 2419 .free = generic_hdmi_free, 2420 .build_pcms = generic_hdmi_build_pcms, 2421 .build_controls = generic_hdmi_build_controls, 2422 .unsol_event = hdmi_unsol_event, 2423 #ifdef CONFIG_PM 2424 .resume = generic_hdmi_resume, 2425 #endif 2426 }; 2427 2428 static const struct hdmi_ops generic_standard_hdmi_ops = { 2429 .pin_get_eld = hdmi_pin_get_eld, 2430 .pin_setup_infoframe = hdmi_pin_setup_infoframe, 2431 .pin_hbr_setup = hdmi_pin_hbr_setup, 2432 .setup_stream = hdmi_setup_stream, 2433 }; 2434 2435 /* allocate codec->spec and assign/initialize generic parser ops */ 2436 static int alloc_generic_hdmi(struct hda_codec *codec) 2437 { 2438 struct hdmi_spec *spec; 2439 2440 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2441 if (!spec) 2442 return -ENOMEM; 2443 2444 spec->codec = codec; 2445 spec->ops = generic_standard_hdmi_ops; 2446 spec->dev_num = 1; /* initialize to 1 */ 2447 mutex_init(&spec->pcm_lock); 2448 mutex_init(&spec->bind_lock); 2449 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); 2450 2451 spec->chmap.ops.get_chmap = hdmi_get_chmap; 2452 spec->chmap.ops.set_chmap = hdmi_set_chmap; 2453 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; 2454 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc, 2455 2456 codec->spec = spec; 2457 hdmi_array_init(spec, 4); 2458 2459 codec->patch_ops = generic_hdmi_patch_ops; 2460 2461 return 0; 2462 } 2463 2464 /* generic HDMI parser */ 2465 static int patch_generic_hdmi(struct hda_codec *codec) 2466 { 2467 int err; 2468 2469 err = alloc_generic_hdmi(codec); 2470 if (err < 0) 2471 return err; 2472 2473 err = hdmi_parse_codec(codec); 2474 if (err < 0) { 2475 generic_spec_free(codec); 2476 return err; 2477 } 2478 2479 generic_hdmi_init_per_pins(codec); 2480 return 0; 2481 } 2482 2483 /* 2484 * generic audio component binding 2485 */ 2486 2487 /* turn on / off the unsol event jack detection dynamically */ 2488 static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid, 2489 int dev_id, bool use_acomp) 2490 { 2491 struct hda_jack_tbl *tbl; 2492 2493 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id); 2494 if (tbl) { 2495 /* clear unsol even if component notifier is used, or re-enable 2496 * if notifier is cleared 2497 */ 2498 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag); 2499 snd_hda_codec_write_cache(codec, nid, 0, 2500 AC_VERB_SET_UNSOLICITED_ENABLE, val); 2501 } else { 2502 /* if no jack entry was defined beforehand, create a new one 2503 * at need (i.e. only when notifier is cleared) 2504 */ 2505 if (!use_acomp) 2506 snd_hda_jack_detect_enable(codec, nid, dev_id); 2507 } 2508 } 2509 2510 /* set up / clear component notifier dynamically */ 2511 static void generic_acomp_notifier_set(struct drm_audio_component *acomp, 2512 bool use_acomp) 2513 { 2514 struct hdmi_spec *spec; 2515 int i; 2516 2517 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops); 2518 mutex_lock(&spec->bind_lock); 2519 spec->use_acomp_notifier = use_acomp; 2520 spec->codec->relaxed_resume = use_acomp; 2521 /* reprogram each jack detection logic depending on the notifier */ 2522 if (spec->use_jack_detect) { 2523 for (i = 0; i < spec->num_pins; i++) 2524 reprogram_jack_detect(spec->codec, 2525 get_pin(spec, i)->pin_nid, 2526 get_pin(spec, i)->dev_id, 2527 use_acomp); 2528 } 2529 mutex_unlock(&spec->bind_lock); 2530 } 2531 2532 /* enable / disable the notifier via master bind / unbind */ 2533 static int generic_acomp_master_bind(struct device *dev, 2534 struct drm_audio_component *acomp) 2535 { 2536 generic_acomp_notifier_set(acomp, true); 2537 return 0; 2538 } 2539 2540 static void generic_acomp_master_unbind(struct device *dev, 2541 struct drm_audio_component *acomp) 2542 { 2543 generic_acomp_notifier_set(acomp, false); 2544 } 2545 2546 /* check whether both HD-audio and DRM PCI devices belong to the same bus */ 2547 static int match_bound_vga(struct device *dev, int subtype, void *data) 2548 { 2549 struct hdac_bus *bus = data; 2550 struct pci_dev *pci, *master; 2551 2552 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev)) 2553 return 0; 2554 master = to_pci_dev(bus->dev); 2555 pci = to_pci_dev(dev); 2556 return master->bus == pci->bus; 2557 } 2558 2559 /* audio component notifier for AMD/Nvidia HDMI codecs */ 2560 static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id) 2561 { 2562 struct hda_codec *codec = audio_ptr; 2563 struct hdmi_spec *spec = codec->spec; 2564 hda_nid_t pin_nid = spec->port2pin(codec, port); 2565 2566 if (!pin_nid) 2567 return; 2568 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN) 2569 return; 2570 /* skip notification during system suspend (but not in runtime PM); 2571 * the state will be updated at resume 2572 */ 2573 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) 2574 return; 2575 /* ditto during suspend/resume process itself */ 2576 if (snd_hdac_is_in_pm(&codec->core)) 2577 return; 2578 2579 check_presence_and_report(codec, pin_nid, dev_id); 2580 } 2581 2582 /* set up the private drm_audio_ops from the template */ 2583 static void setup_drm_audio_ops(struct hda_codec *codec, 2584 const struct drm_audio_component_audio_ops *ops) 2585 { 2586 struct hdmi_spec *spec = codec->spec; 2587 2588 spec->drm_audio_ops.audio_ptr = codec; 2589 /* intel_audio_codec_enable() or intel_audio_codec_disable() 2590 * will call pin_eld_notify with using audio_ptr pointer 2591 * We need make sure audio_ptr is really setup 2592 */ 2593 wmb(); 2594 spec->drm_audio_ops.pin2port = ops->pin2port; 2595 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify; 2596 spec->drm_audio_ops.master_bind = ops->master_bind; 2597 spec->drm_audio_ops.master_unbind = ops->master_unbind; 2598 } 2599 2600 /* initialize the generic HDMI audio component */ 2601 static void generic_acomp_init(struct hda_codec *codec, 2602 const struct drm_audio_component_audio_ops *ops, 2603 int (*port2pin)(struct hda_codec *, int)) 2604 { 2605 struct hdmi_spec *spec = codec->spec; 2606 2607 spec->port2pin = port2pin; 2608 setup_drm_audio_ops(codec, ops); 2609 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops, 2610 match_bound_vga, 0)) { 2611 spec->acomp_registered = true; 2612 codec->bus->keep_power = 0; 2613 } 2614 } 2615 2616 /* 2617 * Intel codec parsers and helpers 2618 */ 2619 2620 #define INTEL_GET_VENDOR_VERB 0xf81 2621 #define INTEL_SET_VENDOR_VERB 0x781 2622 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ 2623 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ 2624 2625 static void intel_haswell_enable_all_pins(struct hda_codec *codec, 2626 bool update_tree) 2627 { 2628 unsigned int vendor_param; 2629 struct hdmi_spec *spec = codec->spec; 2630 2631 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2632 INTEL_GET_VENDOR_VERB, 0); 2633 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) 2634 return; 2635 2636 vendor_param |= INTEL_EN_ALL_PIN_CVTS; 2637 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2638 INTEL_SET_VENDOR_VERB, vendor_param); 2639 if (vendor_param == -1) 2640 return; 2641 2642 if (update_tree) 2643 snd_hda_codec_update_widgets(codec); 2644 } 2645 2646 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) 2647 { 2648 unsigned int vendor_param; 2649 struct hdmi_spec *spec = codec->spec; 2650 2651 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2652 INTEL_GET_VENDOR_VERB, 0); 2653 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) 2654 return; 2655 2656 /* enable DP1.2 mode */ 2657 vendor_param |= INTEL_EN_DP12; 2658 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); 2659 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, 2660 INTEL_SET_VENDOR_VERB, vendor_param); 2661 } 2662 2663 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. 2664 * Otherwise you may get severe h/w communication errors. 2665 */ 2666 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, 2667 unsigned int power_state) 2668 { 2669 if (power_state == AC_PWRST_D0) { 2670 intel_haswell_enable_all_pins(codec, false); 2671 intel_haswell_fixup_enable_dp12(codec); 2672 } 2673 2674 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); 2675 snd_hda_codec_set_power_to_all(codec, fg, power_state); 2676 } 2677 2678 /* There is a fixed mapping between audio pin node and display port. 2679 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL: 2680 * Pin Widget 5 - PORT B (port = 1 in i915 driver) 2681 * Pin Widget 6 - PORT C (port = 2 in i915 driver) 2682 * Pin Widget 7 - PORT D (port = 3 in i915 driver) 2683 * 2684 * on VLV, ILK: 2685 * Pin Widget 4 - PORT B (port = 1 in i915 driver) 2686 * Pin Widget 5 - PORT C (port = 2 in i915 driver) 2687 * Pin Widget 6 - PORT D (port = 3 in i915 driver) 2688 */ 2689 static int intel_base_nid(struct hda_codec *codec) 2690 { 2691 switch (codec->core.vendor_id) { 2692 case 0x80860054: /* ILK */ 2693 case 0x80862804: /* ILK */ 2694 case 0x80862882: /* VLV */ 2695 return 4; 2696 default: 2697 return 5; 2698 } 2699 } 2700 2701 static int intel_pin2port(void *audio_ptr, int pin_nid) 2702 { 2703 struct hda_codec *codec = audio_ptr; 2704 struct hdmi_spec *spec = codec->spec; 2705 int base_nid, i; 2706 2707 if (!spec->port_num) { 2708 base_nid = intel_base_nid(codec); 2709 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3)) 2710 return -1; 2711 return pin_nid - base_nid + 1; 2712 } 2713 2714 /* 2715 * looking for the pin number in the mapping table and return 2716 * the index which indicate the port number 2717 */ 2718 for (i = 0; i < spec->port_num; i++) { 2719 if (pin_nid == spec->port_map[i]) 2720 return i; 2721 } 2722 2723 codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid); 2724 return -1; 2725 } 2726 2727 static int intel_port2pin(struct hda_codec *codec, int port) 2728 { 2729 struct hdmi_spec *spec = codec->spec; 2730 2731 if (!spec->port_num) { 2732 /* we assume only from port-B to port-D */ 2733 if (port < 1 || port > 3) 2734 return 0; 2735 return port + intel_base_nid(codec) - 1; 2736 } 2737 2738 if (port < 0 || port >= spec->port_num) 2739 return 0; 2740 return spec->port_map[port]; 2741 } 2742 2743 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) 2744 { 2745 struct hda_codec *codec = audio_ptr; 2746 int pin_nid; 2747 int dev_id = pipe; 2748 2749 pin_nid = intel_port2pin(codec, port); 2750 if (!pin_nid) 2751 return; 2752 /* skip notification during system suspend (but not in runtime PM); 2753 * the state will be updated at resume 2754 */ 2755 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) 2756 return; 2757 /* ditto during suspend/resume process itself */ 2758 if (snd_hdac_is_in_pm(&codec->core)) 2759 return; 2760 2761 snd_hdac_i915_set_bclk(&codec->bus->core); 2762 check_presence_and_report(codec, pin_nid, dev_id); 2763 } 2764 2765 static const struct drm_audio_component_audio_ops intel_audio_ops = { 2766 .pin2port = intel_pin2port, 2767 .pin_eld_notify = intel_pin_eld_notify, 2768 }; 2769 2770 /* register i915 component pin_eld_notify callback */ 2771 static void register_i915_notifier(struct hda_codec *codec) 2772 { 2773 struct hdmi_spec *spec = codec->spec; 2774 2775 spec->use_acomp_notifier = true; 2776 spec->port2pin = intel_port2pin; 2777 setup_drm_audio_ops(codec, &intel_audio_ops); 2778 snd_hdac_acomp_register_notifier(&codec->bus->core, 2779 &spec->drm_audio_ops); 2780 /* no need for forcible resume for jack check thanks to notifier */ 2781 codec->relaxed_resume = 1; 2782 } 2783 2784 /* setup_stream ops override for HSW+ */ 2785 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 2786 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 2787 int format) 2788 { 2789 haswell_verify_D0(codec, cvt_nid, pin_nid); 2790 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 2791 stream_tag, format); 2792 } 2793 2794 /* pin_cvt_fixup ops override for HSW+ and VLV+ */ 2795 static void i915_pin_cvt_fixup(struct hda_codec *codec, 2796 struct hdmi_spec_per_pin *per_pin, 2797 hda_nid_t cvt_nid) 2798 { 2799 if (per_pin) { 2800 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2801 per_pin->dev_id); 2802 intel_verify_pin_cvt_connect(codec, per_pin); 2803 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, 2804 per_pin->dev_id, per_pin->mux_idx); 2805 } else { 2806 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); 2807 } 2808 } 2809 2810 /* precondition and allocation for Intel codecs */ 2811 static int alloc_intel_hdmi(struct hda_codec *codec) 2812 { 2813 int err; 2814 2815 /* requires i915 binding */ 2816 if (!codec->bus->core.audio_component) { 2817 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); 2818 /* set probe_id here to prevent generic fallback binding */ 2819 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE; 2820 return -ENODEV; 2821 } 2822 2823 err = alloc_generic_hdmi(codec); 2824 if (err < 0) 2825 return err; 2826 /* no need to handle unsol events */ 2827 codec->patch_ops.unsol_event = NULL; 2828 return 0; 2829 } 2830 2831 /* parse and post-process for Intel codecs */ 2832 static int parse_intel_hdmi(struct hda_codec *codec) 2833 { 2834 int err; 2835 2836 err = hdmi_parse_codec(codec); 2837 if (err < 0) { 2838 generic_spec_free(codec); 2839 return err; 2840 } 2841 2842 generic_hdmi_init_per_pins(codec); 2843 register_i915_notifier(codec); 2844 return 0; 2845 } 2846 2847 /* Intel Haswell and onwards; audio component with eld notifier */ 2848 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid, 2849 const int *port_map, int port_num) 2850 { 2851 struct hdmi_spec *spec; 2852 int err; 2853 2854 err = alloc_intel_hdmi(codec); 2855 if (err < 0) 2856 return err; 2857 spec = codec->spec; 2858 codec->dp_mst = true; 2859 spec->dyn_pcm_assign = true; 2860 spec->vendor_nid = vendor_nid; 2861 spec->port_map = port_map; 2862 spec->port_num = port_num; 2863 spec->intel_hsw_fixup = true; 2864 2865 intel_haswell_enable_all_pins(codec, true); 2866 intel_haswell_fixup_enable_dp12(codec); 2867 2868 codec->display_power_control = 1; 2869 2870 codec->patch_ops.set_power_state = haswell_set_power_state; 2871 codec->depop_delay = 0; 2872 codec->auto_runtime_pm = 1; 2873 2874 spec->ops.setup_stream = i915_hsw_setup_stream; 2875 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2876 2877 return parse_intel_hdmi(codec); 2878 } 2879 2880 static int patch_i915_hsw_hdmi(struct hda_codec *codec) 2881 { 2882 return intel_hsw_common_init(codec, 0x08, NULL, 0); 2883 } 2884 2885 static int patch_i915_glk_hdmi(struct hda_codec *codec) 2886 { 2887 return intel_hsw_common_init(codec, 0x0b, NULL, 0); 2888 } 2889 2890 static int patch_i915_icl_hdmi(struct hda_codec *codec) 2891 { 2892 /* 2893 * pin to port mapping table where the value indicate the pin number and 2894 * the index indicate the port number. 2895 */ 2896 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb}; 2897 2898 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map)); 2899 } 2900 2901 static int patch_i915_tgl_hdmi(struct hda_codec *codec) 2902 { 2903 /* 2904 * pin to port mapping table where the value indicate the pin number and 2905 * the index indicate the port number. 2906 */ 2907 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf}; 2908 2909 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map)); 2910 } 2911 2912 /* Intel Baytrail and Braswell; with eld notifier */ 2913 static int patch_i915_byt_hdmi(struct hda_codec *codec) 2914 { 2915 struct hdmi_spec *spec; 2916 int err; 2917 2918 err = alloc_intel_hdmi(codec); 2919 if (err < 0) 2920 return err; 2921 spec = codec->spec; 2922 2923 /* For Valleyview/Cherryview, only the display codec is in the display 2924 * power well and can use link_power ops to request/release the power. 2925 */ 2926 codec->display_power_control = 1; 2927 2928 codec->depop_delay = 0; 2929 codec->auto_runtime_pm = 1; 2930 2931 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2932 2933 return parse_intel_hdmi(codec); 2934 } 2935 2936 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ 2937 static int patch_i915_cpt_hdmi(struct hda_codec *codec) 2938 { 2939 int err; 2940 2941 err = alloc_intel_hdmi(codec); 2942 if (err < 0) 2943 return err; 2944 return parse_intel_hdmi(codec); 2945 } 2946 2947 /* 2948 * Shared non-generic implementations 2949 */ 2950 2951 static int simple_playback_build_pcms(struct hda_codec *codec) 2952 { 2953 struct hdmi_spec *spec = codec->spec; 2954 struct hda_pcm *info; 2955 unsigned int chans; 2956 struct hda_pcm_stream *pstr; 2957 struct hdmi_spec_per_cvt *per_cvt; 2958 2959 per_cvt = get_cvt(spec, 0); 2960 chans = get_wcaps(codec, per_cvt->cvt_nid); 2961 chans = get_wcaps_channels(chans); 2962 2963 info = snd_hda_codec_pcm_new(codec, "HDMI 0"); 2964 if (!info) 2965 return -ENOMEM; 2966 spec->pcm_rec[0].pcm = info; 2967 info->pcm_type = HDA_PCM_TYPE_HDMI; 2968 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2969 *pstr = spec->pcm_playback; 2970 pstr->nid = per_cvt->cvt_nid; 2971 if (pstr->channels_max <= 2 && chans && chans <= 16) 2972 pstr->channels_max = chans; 2973 2974 return 0; 2975 } 2976 2977 /* unsolicited event for jack sensing */ 2978 static void simple_hdmi_unsol_event(struct hda_codec *codec, 2979 unsigned int res) 2980 { 2981 snd_hda_jack_set_dirty_all(codec); 2982 snd_hda_jack_report_sync(codec); 2983 } 2984 2985 /* generic_hdmi_build_jack can be used for simple_hdmi, too, 2986 * as long as spec->pins[] is set correctly 2987 */ 2988 #define simple_hdmi_build_jack generic_hdmi_build_jack 2989 2990 static int simple_playback_build_controls(struct hda_codec *codec) 2991 { 2992 struct hdmi_spec *spec = codec->spec; 2993 struct hdmi_spec_per_cvt *per_cvt; 2994 int err; 2995 2996 per_cvt = get_cvt(spec, 0); 2997 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, 2998 per_cvt->cvt_nid, 2999 HDA_PCM_TYPE_HDMI); 3000 if (err < 0) 3001 return err; 3002 return simple_hdmi_build_jack(codec, 0); 3003 } 3004 3005 static int simple_playback_init(struct hda_codec *codec) 3006 { 3007 struct hdmi_spec *spec = codec->spec; 3008 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); 3009 hda_nid_t pin = per_pin->pin_nid; 3010 3011 snd_hda_codec_write(codec, pin, 0, 3012 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); 3013 /* some codecs require to unmute the pin */ 3014 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 3015 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, 3016 AMP_OUT_UNMUTE); 3017 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id); 3018 return 0; 3019 } 3020 3021 static void simple_playback_free(struct hda_codec *codec) 3022 { 3023 struct hdmi_spec *spec = codec->spec; 3024 3025 hdmi_array_free(spec); 3026 kfree(spec); 3027 } 3028 3029 /* 3030 * Nvidia specific implementations 3031 */ 3032 3033 #define Nv_VERB_SET_Channel_Allocation 0xF79 3034 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A 3035 #define Nv_VERB_SET_Audio_Protection_On 0xF98 3036 #define Nv_VERB_SET_Audio_Protection_Off 0xF99 3037 3038 #define nvhdmi_master_con_nid_7x 0x04 3039 #define nvhdmi_master_pin_nid_7x 0x05 3040 3041 static const hda_nid_t nvhdmi_con_nids_7x[4] = { 3042 /*front, rear, clfe, rear_surr */ 3043 0x6, 0x8, 0xa, 0xc, 3044 }; 3045 3046 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { 3047 /* set audio protect on */ 3048 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3049 /* enable digital output on pin widget */ 3050 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3051 {} /* terminator */ 3052 }; 3053 3054 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { 3055 /* set audio protect on */ 3056 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3057 /* enable digital output on pin widget */ 3058 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3059 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3060 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3061 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3062 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3063 {} /* terminator */ 3064 }; 3065 3066 #ifdef LIMITED_RATE_FMT_SUPPORT 3067 /* support only the safe format and rate */ 3068 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 3069 #define SUPPORTED_MAXBPS 16 3070 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE 3071 #else 3072 /* support all rates and formats */ 3073 #define SUPPORTED_RATES \ 3074 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ 3075 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ 3076 SNDRV_PCM_RATE_192000) 3077 #define SUPPORTED_MAXBPS 24 3078 #define SUPPORTED_FORMATS \ 3079 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 3080 #endif 3081 3082 static int nvhdmi_7x_init_2ch(struct hda_codec *codec) 3083 { 3084 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); 3085 return 0; 3086 } 3087 3088 static int nvhdmi_7x_init_8ch(struct hda_codec *codec) 3089 { 3090 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); 3091 return 0; 3092 } 3093 3094 static const unsigned int channels_2_6_8[] = { 3095 2, 6, 8 3096 }; 3097 3098 static const unsigned int channels_2_8[] = { 3099 2, 8 3100 }; 3101 3102 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { 3103 .count = ARRAY_SIZE(channels_2_6_8), 3104 .list = channels_2_6_8, 3105 .mask = 0, 3106 }; 3107 3108 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { 3109 .count = ARRAY_SIZE(channels_2_8), 3110 .list = channels_2_8, 3111 .mask = 0, 3112 }; 3113 3114 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, 3115 struct hda_codec *codec, 3116 struct snd_pcm_substream *substream) 3117 { 3118 struct hdmi_spec *spec = codec->spec; 3119 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; 3120 3121 switch (codec->preset->vendor_id) { 3122 case 0x10de0002: 3123 case 0x10de0003: 3124 case 0x10de0005: 3125 case 0x10de0006: 3126 hw_constraints_channels = &hw_constraints_2_8_channels; 3127 break; 3128 case 0x10de0007: 3129 hw_constraints_channels = &hw_constraints_2_6_8_channels; 3130 break; 3131 default: 3132 break; 3133 } 3134 3135 if (hw_constraints_channels != NULL) { 3136 snd_pcm_hw_constraint_list(substream->runtime, 0, 3137 SNDRV_PCM_HW_PARAM_CHANNELS, 3138 hw_constraints_channels); 3139 } else { 3140 snd_pcm_hw_constraint_step(substream->runtime, 0, 3141 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 3142 } 3143 3144 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3145 } 3146 3147 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, 3148 struct hda_codec *codec, 3149 struct snd_pcm_substream *substream) 3150 { 3151 struct hdmi_spec *spec = codec->spec; 3152 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3153 } 3154 3155 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3156 struct hda_codec *codec, 3157 unsigned int stream_tag, 3158 unsigned int format, 3159 struct snd_pcm_substream *substream) 3160 { 3161 struct hdmi_spec *spec = codec->spec; 3162 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3163 stream_tag, format, substream); 3164 } 3165 3166 static const struct hda_pcm_stream simple_pcm_playback = { 3167 .substreams = 1, 3168 .channels_min = 2, 3169 .channels_max = 2, 3170 .ops = { 3171 .open = simple_playback_pcm_open, 3172 .close = simple_playback_pcm_close, 3173 .prepare = simple_playback_pcm_prepare 3174 }, 3175 }; 3176 3177 static const struct hda_codec_ops simple_hdmi_patch_ops = { 3178 .build_controls = simple_playback_build_controls, 3179 .build_pcms = simple_playback_build_pcms, 3180 .init = simple_playback_init, 3181 .free = simple_playback_free, 3182 .unsol_event = simple_hdmi_unsol_event, 3183 }; 3184 3185 static int patch_simple_hdmi(struct hda_codec *codec, 3186 hda_nid_t cvt_nid, hda_nid_t pin_nid) 3187 { 3188 struct hdmi_spec *spec; 3189 struct hdmi_spec_per_cvt *per_cvt; 3190 struct hdmi_spec_per_pin *per_pin; 3191 3192 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 3193 if (!spec) 3194 return -ENOMEM; 3195 3196 spec->codec = codec; 3197 codec->spec = spec; 3198 hdmi_array_init(spec, 1); 3199 3200 spec->multiout.num_dacs = 0; /* no analog */ 3201 spec->multiout.max_channels = 2; 3202 spec->multiout.dig_out_nid = cvt_nid; 3203 spec->num_cvts = 1; 3204 spec->num_pins = 1; 3205 per_pin = snd_array_new(&spec->pins); 3206 per_cvt = snd_array_new(&spec->cvts); 3207 if (!per_pin || !per_cvt) { 3208 simple_playback_free(codec); 3209 return -ENOMEM; 3210 } 3211 per_cvt->cvt_nid = cvt_nid; 3212 per_pin->pin_nid = pin_nid; 3213 spec->pcm_playback = simple_pcm_playback; 3214 3215 codec->patch_ops = simple_hdmi_patch_ops; 3216 3217 return 0; 3218 } 3219 3220 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, 3221 int channels) 3222 { 3223 unsigned int chanmask; 3224 int chan = channels ? (channels - 1) : 1; 3225 3226 switch (channels) { 3227 default: 3228 case 0: 3229 case 2: 3230 chanmask = 0x00; 3231 break; 3232 case 4: 3233 chanmask = 0x08; 3234 break; 3235 case 6: 3236 chanmask = 0x0b; 3237 break; 3238 case 8: 3239 chanmask = 0x13; 3240 break; 3241 } 3242 3243 /* Set the audio infoframe channel allocation and checksum fields. The 3244 * channel count is computed implicitly by the hardware. */ 3245 snd_hda_codec_write(codec, 0x1, 0, 3246 Nv_VERB_SET_Channel_Allocation, chanmask); 3247 3248 snd_hda_codec_write(codec, 0x1, 0, 3249 Nv_VERB_SET_Info_Frame_Checksum, 3250 (0x71 - chan - chanmask)); 3251 } 3252 3253 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, 3254 struct hda_codec *codec, 3255 struct snd_pcm_substream *substream) 3256 { 3257 struct hdmi_spec *spec = codec->spec; 3258 int i; 3259 3260 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 3261 0, AC_VERB_SET_CHANNEL_STREAMID, 0); 3262 for (i = 0; i < 4; i++) { 3263 /* set the stream id */ 3264 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3265 AC_VERB_SET_CHANNEL_STREAMID, 0); 3266 /* set the stream format */ 3267 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3268 AC_VERB_SET_STREAM_FORMAT, 0); 3269 } 3270 3271 /* The audio hardware sends a channel count of 0x7 (8ch) when all the 3272 * streams are disabled. */ 3273 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3274 3275 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3276 } 3277 3278 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, 3279 struct hda_codec *codec, 3280 unsigned int stream_tag, 3281 unsigned int format, 3282 struct snd_pcm_substream *substream) 3283 { 3284 int chs; 3285 unsigned int dataDCC2, channel_id; 3286 int i; 3287 struct hdmi_spec *spec = codec->spec; 3288 struct hda_spdif_out *spdif; 3289 struct hdmi_spec_per_cvt *per_cvt; 3290 3291 mutex_lock(&codec->spdif_mutex); 3292 per_cvt = get_cvt(spec, 0); 3293 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); 3294 3295 chs = substream->runtime->channels; 3296 3297 dataDCC2 = 0x2; 3298 3299 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ 3300 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) 3301 snd_hda_codec_write(codec, 3302 nvhdmi_master_con_nid_7x, 3303 0, 3304 AC_VERB_SET_DIGI_CONVERT_1, 3305 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3306 3307 /* set the stream id */ 3308 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3309 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); 3310 3311 /* set the stream format */ 3312 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3313 AC_VERB_SET_STREAM_FORMAT, format); 3314 3315 /* turn on again (if needed) */ 3316 /* enable and set the channel status audio/data flag */ 3317 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { 3318 snd_hda_codec_write(codec, 3319 nvhdmi_master_con_nid_7x, 3320 0, 3321 AC_VERB_SET_DIGI_CONVERT_1, 3322 spdif->ctls & 0xff); 3323 snd_hda_codec_write(codec, 3324 nvhdmi_master_con_nid_7x, 3325 0, 3326 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3327 } 3328 3329 for (i = 0; i < 4; i++) { 3330 if (chs == 2) 3331 channel_id = 0; 3332 else 3333 channel_id = i * 2; 3334 3335 /* turn off SPDIF once; 3336 *otherwise the IEC958 bits won't be updated 3337 */ 3338 if (codec->spdif_status_reset && 3339 (spdif->ctls & AC_DIG1_ENABLE)) 3340 snd_hda_codec_write(codec, 3341 nvhdmi_con_nids_7x[i], 3342 0, 3343 AC_VERB_SET_DIGI_CONVERT_1, 3344 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3345 /* set the stream id */ 3346 snd_hda_codec_write(codec, 3347 nvhdmi_con_nids_7x[i], 3348 0, 3349 AC_VERB_SET_CHANNEL_STREAMID, 3350 (stream_tag << 4) | channel_id); 3351 /* set the stream format */ 3352 snd_hda_codec_write(codec, 3353 nvhdmi_con_nids_7x[i], 3354 0, 3355 AC_VERB_SET_STREAM_FORMAT, 3356 format); 3357 /* turn on again (if needed) */ 3358 /* enable and set the channel status audio/data flag */ 3359 if (codec->spdif_status_reset && 3360 (spdif->ctls & AC_DIG1_ENABLE)) { 3361 snd_hda_codec_write(codec, 3362 nvhdmi_con_nids_7x[i], 3363 0, 3364 AC_VERB_SET_DIGI_CONVERT_1, 3365 spdif->ctls & 0xff); 3366 snd_hda_codec_write(codec, 3367 nvhdmi_con_nids_7x[i], 3368 0, 3369 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3370 } 3371 } 3372 3373 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); 3374 3375 mutex_unlock(&codec->spdif_mutex); 3376 return 0; 3377 } 3378 3379 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { 3380 .substreams = 1, 3381 .channels_min = 2, 3382 .channels_max = 8, 3383 .nid = nvhdmi_master_con_nid_7x, 3384 .rates = SUPPORTED_RATES, 3385 .maxbps = SUPPORTED_MAXBPS, 3386 .formats = SUPPORTED_FORMATS, 3387 .ops = { 3388 .open = simple_playback_pcm_open, 3389 .close = nvhdmi_8ch_7x_pcm_close, 3390 .prepare = nvhdmi_8ch_7x_pcm_prepare 3391 }, 3392 }; 3393 3394 static int patch_nvhdmi_2ch(struct hda_codec *codec) 3395 { 3396 struct hdmi_spec *spec; 3397 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, 3398 nvhdmi_master_pin_nid_7x); 3399 if (err < 0) 3400 return err; 3401 3402 codec->patch_ops.init = nvhdmi_7x_init_2ch; 3403 /* override the PCM rates, etc, as the codec doesn't give full list */ 3404 spec = codec->spec; 3405 spec->pcm_playback.rates = SUPPORTED_RATES; 3406 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; 3407 spec->pcm_playback.formats = SUPPORTED_FORMATS; 3408 return 0; 3409 } 3410 3411 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) 3412 { 3413 struct hdmi_spec *spec = codec->spec; 3414 int err = simple_playback_build_pcms(codec); 3415 if (!err) { 3416 struct hda_pcm *info = get_pcm_rec(spec, 0); 3417 info->own_chmap = true; 3418 } 3419 return err; 3420 } 3421 3422 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) 3423 { 3424 struct hdmi_spec *spec = codec->spec; 3425 struct hda_pcm *info; 3426 struct snd_pcm_chmap *chmap; 3427 int err; 3428 3429 err = simple_playback_build_controls(codec); 3430 if (err < 0) 3431 return err; 3432 3433 /* add channel maps */ 3434 info = get_pcm_rec(spec, 0); 3435 err = snd_pcm_add_chmap_ctls(info->pcm, 3436 SNDRV_PCM_STREAM_PLAYBACK, 3437 snd_pcm_alt_chmaps, 8, 0, &chmap); 3438 if (err < 0) 3439 return err; 3440 switch (codec->preset->vendor_id) { 3441 case 0x10de0002: 3442 case 0x10de0003: 3443 case 0x10de0005: 3444 case 0x10de0006: 3445 chmap->channel_mask = (1U << 2) | (1U << 8); 3446 break; 3447 case 0x10de0007: 3448 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); 3449 } 3450 return 0; 3451 } 3452 3453 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) 3454 { 3455 struct hdmi_spec *spec; 3456 int err = patch_nvhdmi_2ch(codec); 3457 if (err < 0) 3458 return err; 3459 spec = codec->spec; 3460 spec->multiout.max_channels = 8; 3461 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; 3462 codec->patch_ops.init = nvhdmi_7x_init_8ch; 3463 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; 3464 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; 3465 3466 /* Initialize the audio infoframe channel mask and checksum to something 3467 * valid */ 3468 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3469 3470 return 0; 3471 } 3472 3473 /* 3474 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: 3475 * - 0x10de0015 3476 * - 0x10de0040 3477 */ 3478 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, 3479 struct hdac_cea_channel_speaker_allocation *cap, int channels) 3480 { 3481 if (cap->ca_index == 0x00 && channels == 2) 3482 return SNDRV_CTL_TLVT_CHMAP_FIXED; 3483 3484 /* If the speaker allocation matches the channel count, it is OK. */ 3485 if (cap->channels != channels) 3486 return -1; 3487 3488 /* all channels are remappable freely */ 3489 return SNDRV_CTL_TLVT_CHMAP_VAR; 3490 } 3491 3492 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, 3493 int ca, int chs, unsigned char *map) 3494 { 3495 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) 3496 return -EINVAL; 3497 3498 return 0; 3499 } 3500 3501 /* map from pin NID to port; port is 0-based */ 3502 /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */ 3503 static int nvhdmi_pin2port(void *audio_ptr, int pin_nid) 3504 { 3505 return pin_nid - 4; 3506 } 3507 3508 /* reverse-map from port to pin NID: see above */ 3509 static int nvhdmi_port2pin(struct hda_codec *codec, int port) 3510 { 3511 return port + 4; 3512 } 3513 3514 static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = { 3515 .pin2port = nvhdmi_pin2port, 3516 .pin_eld_notify = generic_acomp_pin_eld_notify, 3517 .master_bind = generic_acomp_master_bind, 3518 .master_unbind = generic_acomp_master_unbind, 3519 }; 3520 3521 static int patch_nvhdmi(struct hda_codec *codec) 3522 { 3523 struct hdmi_spec *spec; 3524 int err; 3525 3526 err = alloc_generic_hdmi(codec); 3527 if (err < 0) 3528 return err; 3529 codec->dp_mst = true; 3530 3531 spec = codec->spec; 3532 spec->dyn_pcm_assign = true; 3533 3534 err = hdmi_parse_codec(codec); 3535 if (err < 0) { 3536 generic_spec_free(codec); 3537 return err; 3538 } 3539 3540 generic_hdmi_init_per_pins(codec); 3541 3542 spec->dyn_pin_out = true; 3543 3544 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3545 nvhdmi_chmap_cea_alloc_validate_get_type; 3546 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3547 3548 codec->link_down_at_suspend = 1; 3549 3550 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin); 3551 3552 return 0; 3553 } 3554 3555 static int patch_nvhdmi_legacy(struct hda_codec *codec) 3556 { 3557 struct hdmi_spec *spec; 3558 int err; 3559 3560 err = patch_generic_hdmi(codec); 3561 if (err) 3562 return err; 3563 3564 spec = codec->spec; 3565 spec->dyn_pin_out = true; 3566 3567 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3568 nvhdmi_chmap_cea_alloc_validate_get_type; 3569 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3570 3571 codec->link_down_at_suspend = 1; 3572 3573 return 0; 3574 } 3575 3576 /* 3577 * The HDA codec on NVIDIA Tegra contains two scratch registers that are 3578 * accessed using vendor-defined verbs. These registers can be used for 3579 * interoperability between the HDA and HDMI drivers. 3580 */ 3581 3582 /* Audio Function Group node */ 3583 #define NVIDIA_AFG_NID 0x01 3584 3585 /* 3586 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio 3587 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to 3588 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This 3589 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an 3590 * additional bit (at position 30) to signal the validity of the format. 3591 * 3592 * | 31 | 30 | 29 16 | 15 0 | 3593 * +---------+-------+--------+--------+ 3594 * | TRIGGER | VALID | UNUSED | FORMAT | 3595 * +-----------------------------------| 3596 * 3597 * Note that for the trigger bit to take effect it needs to change value 3598 * (i.e. it needs to be toggled). 3599 */ 3600 #define NVIDIA_GET_SCRATCH0 0xfa6 3601 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 3602 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 3603 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 3604 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa 3605 #define NVIDIA_SCRATCH_TRIGGER (1 << 7) 3606 #define NVIDIA_SCRATCH_VALID (1 << 6) 3607 3608 #define NVIDIA_GET_SCRATCH1 0xfab 3609 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac 3610 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad 3611 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae 3612 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf 3613 3614 /* 3615 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, 3616 * the format is invalidated so that the HDMI codec can be disabled. 3617 */ 3618 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format) 3619 { 3620 unsigned int value; 3621 3622 /* bits [31:30] contain the trigger and valid bits */ 3623 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0, 3624 NVIDIA_GET_SCRATCH0, 0); 3625 value = (value >> 24) & 0xff; 3626 3627 /* bits [15:0] are used to store the HDA format */ 3628 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3629 NVIDIA_SET_SCRATCH0_BYTE0, 3630 (format >> 0) & 0xff); 3631 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3632 NVIDIA_SET_SCRATCH0_BYTE1, 3633 (format >> 8) & 0xff); 3634 3635 /* bits [16:24] are unused */ 3636 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3637 NVIDIA_SET_SCRATCH0_BYTE2, 0); 3638 3639 /* 3640 * Bit 30 signals that the data is valid and hence that HDMI audio can 3641 * be enabled. 3642 */ 3643 if (format == 0) 3644 value &= ~NVIDIA_SCRATCH_VALID; 3645 else 3646 value |= NVIDIA_SCRATCH_VALID; 3647 3648 /* 3649 * Whenever the trigger bit is toggled, an interrupt is raised in the 3650 * HDMI codec. The HDMI driver will use that as trigger to update its 3651 * configuration. 3652 */ 3653 value ^= NVIDIA_SCRATCH_TRIGGER; 3654 3655 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3656 NVIDIA_SET_SCRATCH0_BYTE3, value); 3657 } 3658 3659 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, 3660 struct hda_codec *codec, 3661 unsigned int stream_tag, 3662 unsigned int format, 3663 struct snd_pcm_substream *substream) 3664 { 3665 int err; 3666 3667 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, 3668 format, substream); 3669 if (err < 0) 3670 return err; 3671 3672 /* notify the HDMI codec of the format change */ 3673 tegra_hdmi_set_format(codec, format); 3674 3675 return 0; 3676 } 3677 3678 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, 3679 struct hda_codec *codec, 3680 struct snd_pcm_substream *substream) 3681 { 3682 /* invalidate the format in the HDMI codec */ 3683 tegra_hdmi_set_format(codec, 0); 3684 3685 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); 3686 } 3687 3688 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) 3689 { 3690 struct hdmi_spec *spec = codec->spec; 3691 unsigned int i; 3692 3693 for (i = 0; i < spec->num_pins; i++) { 3694 struct hda_pcm *pcm = get_pcm_rec(spec, i); 3695 3696 if (pcm->pcm_type == type) 3697 return pcm; 3698 } 3699 3700 return NULL; 3701 } 3702 3703 static int tegra_hdmi_build_pcms(struct hda_codec *codec) 3704 { 3705 struct hda_pcm_stream *stream; 3706 struct hda_pcm *pcm; 3707 int err; 3708 3709 err = generic_hdmi_build_pcms(codec); 3710 if (err < 0) 3711 return err; 3712 3713 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); 3714 if (!pcm) 3715 return -ENODEV; 3716 3717 /* 3718 * Override ->prepare() and ->cleanup() operations to notify the HDMI 3719 * codec about format changes. 3720 */ 3721 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3722 stream->ops.prepare = tegra_hdmi_pcm_prepare; 3723 stream->ops.cleanup = tegra_hdmi_pcm_cleanup; 3724 3725 return 0; 3726 } 3727 3728 static int patch_tegra_hdmi(struct hda_codec *codec) 3729 { 3730 int err; 3731 3732 err = patch_generic_hdmi(codec); 3733 if (err) 3734 return err; 3735 3736 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; 3737 3738 return 0; 3739 } 3740 3741 /* 3742 * ATI/AMD-specific implementations 3743 */ 3744 3745 #define is_amdhdmi_rev3_or_later(codec) \ 3746 ((codec)->core.vendor_id == 0x1002aa01 && \ 3747 ((codec)->core.revision_id & 0xff00) >= 0x0300) 3748 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) 3749 3750 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ 3751 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 3752 #define ATI_VERB_SET_DOWNMIX_INFO 0x772 3753 #define ATI_VERB_SET_MULTICHANNEL_01 0x777 3754 #define ATI_VERB_SET_MULTICHANNEL_23 0x778 3755 #define ATI_VERB_SET_MULTICHANNEL_45 0x779 3756 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a 3757 #define ATI_VERB_SET_HBR_CONTROL 0x77c 3758 #define ATI_VERB_SET_MULTICHANNEL_1 0x785 3759 #define ATI_VERB_SET_MULTICHANNEL_3 0x786 3760 #define ATI_VERB_SET_MULTICHANNEL_5 0x787 3761 #define ATI_VERB_SET_MULTICHANNEL_7 0x788 3762 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 3763 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 3764 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 3765 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 3766 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 3767 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 3768 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a 3769 #define ATI_VERB_GET_HBR_CONTROL 0xf7c 3770 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 3771 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 3772 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 3773 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 3774 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 3775 3776 /* AMD specific HDA cvt verbs */ 3777 #define ATI_VERB_SET_RAMP_RATE 0x770 3778 #define ATI_VERB_GET_RAMP_RATE 0xf70 3779 3780 #define ATI_OUT_ENABLE 0x1 3781 3782 #define ATI_MULTICHANNEL_MODE_PAIRED 0 3783 #define ATI_MULTICHANNEL_MODE_SINGLE 1 3784 3785 #define ATI_HBR_CAPABLE 0x01 3786 #define ATI_HBR_ENABLE 0x10 3787 3788 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 3789 int dev_id, unsigned char *buf, int *eld_size) 3790 { 3791 WARN_ON(dev_id != 0); 3792 /* call hda_eld.c ATI/AMD-specific function */ 3793 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, 3794 is_amdhdmi_rev3_or_later(codec)); 3795 } 3796 3797 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, 3798 hda_nid_t pin_nid, int dev_id, int ca, 3799 int active_channels, int conn_type) 3800 { 3801 WARN_ON(dev_id != 0); 3802 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); 3803 } 3804 3805 static int atihdmi_paired_swap_fc_lfe(int pos) 3806 { 3807 /* 3808 * ATI/AMD have automatic FC/LFE swap built-in 3809 * when in pairwise mapping mode. 3810 */ 3811 3812 switch (pos) { 3813 /* see channel_allocations[].speakers[] */ 3814 case 2: return 3; 3815 case 3: return 2; 3816 default: break; 3817 } 3818 3819 return pos; 3820 } 3821 3822 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, 3823 int ca, int chs, unsigned char *map) 3824 { 3825 struct hdac_cea_channel_speaker_allocation *cap; 3826 int i, j; 3827 3828 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ 3829 3830 cap = snd_hdac_get_ch_alloc_from_ca(ca); 3831 for (i = 0; i < chs; ++i) { 3832 int mask = snd_hdac_chmap_to_spk_mask(map[i]); 3833 bool ok = false; 3834 bool companion_ok = false; 3835 3836 if (!mask) 3837 continue; 3838 3839 for (j = 0 + i % 2; j < 8; j += 2) { 3840 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); 3841 if (cap->speakers[chan_idx] == mask) { 3842 /* channel is in a supported position */ 3843 ok = true; 3844 3845 if (i % 2 == 0 && i + 1 < chs) { 3846 /* even channel, check the odd companion */ 3847 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); 3848 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); 3849 int comp_mask_act = cap->speakers[comp_chan_idx]; 3850 3851 if (comp_mask_req == comp_mask_act) 3852 companion_ok = true; 3853 else 3854 return -EINVAL; 3855 } 3856 break; 3857 } 3858 } 3859 3860 if (!ok) 3861 return -EINVAL; 3862 3863 if (companion_ok) 3864 i++; /* companion channel already checked */ 3865 } 3866 3867 return 0; 3868 } 3869 3870 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, 3871 hda_nid_t pin_nid, int hdmi_slot, int stream_channel) 3872 { 3873 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 3874 int verb; 3875 int ati_channel_setup = 0; 3876 3877 if (hdmi_slot > 7) 3878 return -EINVAL; 3879 3880 if (!has_amd_full_remap_support(codec)) { 3881 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); 3882 3883 /* In case this is an odd slot but without stream channel, do not 3884 * disable the slot since the corresponding even slot could have a 3885 * channel. In case neither have a channel, the slot pair will be 3886 * disabled when this function is called for the even slot. */ 3887 if (hdmi_slot % 2 != 0 && stream_channel == 0xf) 3888 return 0; 3889 3890 hdmi_slot -= hdmi_slot % 2; 3891 3892 if (stream_channel != 0xf) 3893 stream_channel -= stream_channel % 2; 3894 } 3895 3896 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; 3897 3898 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ 3899 3900 if (stream_channel != 0xf) 3901 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; 3902 3903 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); 3904 } 3905 3906 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, 3907 hda_nid_t pin_nid, int asp_slot) 3908 { 3909 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 3910 bool was_odd = false; 3911 int ati_asp_slot = asp_slot; 3912 int verb; 3913 int ati_channel_setup; 3914 3915 if (asp_slot > 7) 3916 return -EINVAL; 3917 3918 if (!has_amd_full_remap_support(codec)) { 3919 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); 3920 if (ati_asp_slot % 2 != 0) { 3921 ati_asp_slot -= 1; 3922 was_odd = true; 3923 } 3924 } 3925 3926 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; 3927 3928 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); 3929 3930 if (!(ati_channel_setup & ATI_OUT_ENABLE)) 3931 return 0xf; 3932 3933 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; 3934 } 3935 3936 static int atihdmi_paired_chmap_cea_alloc_validate_get_type( 3937 struct hdac_chmap *chmap, 3938 struct hdac_cea_channel_speaker_allocation *cap, 3939 int channels) 3940 { 3941 int c; 3942 3943 /* 3944 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so 3945 * we need to take that into account (a single channel may take 2 3946 * channel slots if we need to carry a silent channel next to it). 3947 * On Rev3+ AMD codecs this function is not used. 3948 */ 3949 int chanpairs = 0; 3950 3951 /* We only produce even-numbered channel count TLVs */ 3952 if ((channels % 2) != 0) 3953 return -1; 3954 3955 for (c = 0; c < 7; c += 2) { 3956 if (cap->speakers[c] || cap->speakers[c+1]) 3957 chanpairs++; 3958 } 3959 3960 if (chanpairs * 2 != channels) 3961 return -1; 3962 3963 return SNDRV_CTL_TLVT_CHMAP_PAIRED; 3964 } 3965 3966 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, 3967 struct hdac_cea_channel_speaker_allocation *cap, 3968 unsigned int *chmap, int channels) 3969 { 3970 /* produce paired maps for pre-rev3 ATI/AMD codecs */ 3971 int count = 0; 3972 int c; 3973 3974 for (c = 7; c >= 0; c--) { 3975 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); 3976 int spk = cap->speakers[chan]; 3977 if (!spk) { 3978 /* add N/A channel if the companion channel is occupied */ 3979 if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) 3980 chmap[count++] = SNDRV_CHMAP_NA; 3981 3982 continue; 3983 } 3984 3985 chmap[count++] = snd_hdac_spk_to_chmap(spk); 3986 } 3987 3988 WARN_ON(count != channels); 3989 } 3990 3991 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 3992 int dev_id, bool hbr) 3993 { 3994 int hbr_ctl, hbr_ctl_new; 3995 3996 WARN_ON(dev_id != 0); 3997 3998 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); 3999 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { 4000 if (hbr) 4001 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; 4002 else 4003 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; 4004 4005 codec_dbg(codec, 4006 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", 4007 pin_nid, 4008 hbr_ctl == hbr_ctl_new ? "" : "new-", 4009 hbr_ctl_new); 4010 4011 if (hbr_ctl != hbr_ctl_new) 4012 snd_hda_codec_write(codec, pin_nid, 0, 4013 ATI_VERB_SET_HBR_CONTROL, 4014 hbr_ctl_new); 4015 4016 } else if (hbr) 4017 return -EINVAL; 4018 4019 return 0; 4020 } 4021 4022 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 4023 hda_nid_t pin_nid, int dev_id, 4024 u32 stream_tag, int format) 4025 { 4026 if (is_amdhdmi_rev3_or_later(codec)) { 4027 int ramp_rate = 180; /* default as per AMD spec */ 4028 /* disable ramp-up/down for non-pcm as per AMD spec */ 4029 if (format & AC_FMT_TYPE_NON_PCM) 4030 ramp_rate = 0; 4031 4032 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); 4033 } 4034 4035 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 4036 stream_tag, format); 4037 } 4038 4039 4040 static int atihdmi_init(struct hda_codec *codec) 4041 { 4042 struct hdmi_spec *spec = codec->spec; 4043 int pin_idx, err; 4044 4045 err = generic_hdmi_init(codec); 4046 4047 if (err) 4048 return err; 4049 4050 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 4051 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 4052 4053 /* make sure downmix information in infoframe is zero */ 4054 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); 4055 4056 /* enable channel-wise remap mode if supported */ 4057 if (has_amd_full_remap_support(codec)) 4058 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 4059 ATI_VERB_SET_MULTICHANNEL_MODE, 4060 ATI_MULTICHANNEL_MODE_SINGLE); 4061 } 4062 codec->auto_runtime_pm = 1; 4063 4064 return 0; 4065 } 4066 4067 /* map from pin NID to port; port is 0-based */ 4068 /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */ 4069 static int atihdmi_pin2port(void *audio_ptr, int pin_nid) 4070 { 4071 return pin_nid / 2 - 1; 4072 } 4073 4074 /* reverse-map from port to pin NID: see above */ 4075 static int atihdmi_port2pin(struct hda_codec *codec, int port) 4076 { 4077 return port * 2 + 3; 4078 } 4079 4080 static const struct drm_audio_component_audio_ops atihdmi_audio_ops = { 4081 .pin2port = atihdmi_pin2port, 4082 .pin_eld_notify = generic_acomp_pin_eld_notify, 4083 .master_bind = generic_acomp_master_bind, 4084 .master_unbind = generic_acomp_master_unbind, 4085 }; 4086 4087 static int patch_atihdmi(struct hda_codec *codec) 4088 { 4089 struct hdmi_spec *spec; 4090 struct hdmi_spec_per_cvt *per_cvt; 4091 int err, cvt_idx; 4092 4093 err = patch_generic_hdmi(codec); 4094 4095 if (err) 4096 return err; 4097 4098 codec->patch_ops.init = atihdmi_init; 4099 4100 spec = codec->spec; 4101 4102 spec->ops.pin_get_eld = atihdmi_pin_get_eld; 4103 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; 4104 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; 4105 spec->ops.setup_stream = atihdmi_setup_stream; 4106 4107 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; 4108 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; 4109 4110 if (!has_amd_full_remap_support(codec)) { 4111 /* override to ATI/AMD-specific versions with pairwise mapping */ 4112 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4113 atihdmi_paired_chmap_cea_alloc_validate_get_type; 4114 spec->chmap.ops.cea_alloc_to_tlv_chmap = 4115 atihdmi_paired_cea_alloc_to_tlv_chmap; 4116 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; 4117 } 4118 4119 /* ATI/AMD converters do not advertise all of their capabilities */ 4120 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 4121 per_cvt = get_cvt(spec, cvt_idx); 4122 per_cvt->channels_max = max(per_cvt->channels_max, 8u); 4123 per_cvt->rates |= SUPPORTED_RATES; 4124 per_cvt->formats |= SUPPORTED_FORMATS; 4125 per_cvt->maxbps = max(per_cvt->maxbps, 24u); 4126 } 4127 4128 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); 4129 4130 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing 4131 * the link-down as is. Tell the core to allow it. 4132 */ 4133 codec->link_down_at_suspend = 1; 4134 4135 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin); 4136 4137 return 0; 4138 } 4139 4140 /* VIA HDMI Implementation */ 4141 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ 4142 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ 4143 4144 static int patch_via_hdmi(struct hda_codec *codec) 4145 { 4146 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); 4147 } 4148 4149 /* 4150 * patch entries 4151 */ 4152 static const struct hda_device_id snd_hda_id_hdmi[] = { 4153 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), 4154 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), 4155 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), 4156 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), 4157 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), 4158 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), 4159 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), 4160 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch), 4161 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4162 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4163 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x), 4164 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4165 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4166 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), 4167 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy), 4168 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy), 4169 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy), 4170 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy), 4171 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy), 4172 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy), 4173 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy), 4174 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy), 4175 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy), 4176 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy), 4177 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy), 4178 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy), 4179 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy), 4180 /* 17 is known to be absent */ 4181 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy), 4182 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy), 4183 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy), 4184 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy), 4185 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy), 4186 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), 4187 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), 4188 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), 4189 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), 4190 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi), 4191 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi), 4192 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), 4193 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), 4194 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), 4195 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), 4196 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), 4197 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), 4198 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), 4199 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi), 4200 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi), 4201 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), 4202 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi), 4203 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), 4204 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi), 4205 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi), 4206 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), 4207 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), 4208 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), 4209 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), 4210 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi), 4211 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi), 4212 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi), 4213 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi), 4214 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi), 4215 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), 4216 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi), 4217 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), 4218 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi), 4219 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), 4220 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), 4221 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi), 4222 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi), 4223 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi), 4224 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi), 4225 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi), 4226 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi), 4227 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi), 4228 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi), 4229 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), 4230 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), 4231 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), 4232 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), 4233 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), 4234 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), 4235 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), 4236 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), 4237 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4238 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), 4239 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), 4240 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), 4241 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), 4242 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4243 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), 4244 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), 4245 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), 4246 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), 4247 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), 4248 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), 4249 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), 4250 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), 4251 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), 4252 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi), 4253 HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi), 4254 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), 4255 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), 4256 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), 4257 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), 4258 /* special ID for generic HDMI */ 4259 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), 4260 {} /* terminator */ 4261 }; 4262 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); 4263 4264 MODULE_LICENSE("GPL"); 4265 MODULE_DESCRIPTION("HDMI HD-audio codec"); 4266 MODULE_ALIAS("snd-hda-codec-intelhdmi"); 4267 MODULE_ALIAS("snd-hda-codec-nvhdmi"); 4268 MODULE_ALIAS("snd-hda-codec-atihdmi"); 4269 4270 static struct hda_codec_driver hdmi_driver = { 4271 .id = snd_hda_id_hdmi, 4272 }; 4273 4274 module_hda_codec_driver(hdmi_driver); 4275