1 /* 2 * 3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs 4 * 5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. 6 * Copyright (c) 2006 ATI Technologies Inc. 7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved. 8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com> 9 * 10 * Authors: 11 * Wu Fengguang <wfg@linux.intel.com> 12 * 13 * Maintained by: 14 * Wu Fengguang <wfg@linux.intel.com> 15 * 16 * This program is free software; you can redistribute it and/or modify it 17 * under the terms of the GNU General Public License as published by the Free 18 * Software Foundation; either version 2 of the License, or (at your option) 19 * any later version. 20 * 21 * This program is distributed in the hope that it will be useful, but 22 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 23 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 24 * for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software Foundation, 28 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 29 */ 30 31 #include <linux/init.h> 32 #include <linux/delay.h> 33 #include <linux/slab.h> 34 #include <linux/moduleparam.h> 35 #include <sound/core.h> 36 #include <sound/jack.h> 37 #include "hda_codec.h" 38 #include "hda_local.h" 39 40 static bool static_hdmi_pcm; 41 module_param(static_hdmi_pcm, bool, 0644); 42 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); 43 44 /* 45 * The HDMI/DisplayPort configuration can be highly dynamic. A graphics device 46 * could support two independent pipes, each of them can be connected to one or 47 * more ports (DVI, HDMI or DisplayPort). 48 * 49 * The HDA correspondence of pipes/ports are converter/pin nodes. 50 */ 51 #define MAX_HDMI_CVTS 3 52 #define MAX_HDMI_PINS 3 53 54 struct hdmi_spec { 55 int num_cvts; 56 int num_pins; 57 hda_nid_t cvt[MAX_HDMI_CVTS+1]; /* audio sources */ 58 hda_nid_t pin[MAX_HDMI_PINS+1]; /* audio sinks */ 59 60 /* 61 * source connection for each pin 62 */ 63 hda_nid_t pin_cvt[MAX_HDMI_PINS+1]; 64 65 /* 66 * HDMI sink attached to each pin 67 */ 68 struct hdmi_eld sink_eld[MAX_HDMI_PINS]; 69 70 /* 71 * export one pcm per pipe 72 */ 73 struct hda_pcm pcm_rec[MAX_HDMI_CVTS]; 74 struct hda_pcm_stream codec_pcm_pars[MAX_HDMI_CVTS]; 75 76 /* 77 * ati/nvhdmi specific 78 */ 79 struct hda_multi_out multiout; 80 const struct hda_pcm_stream *pcm_playback; 81 82 /* misc flags */ 83 /* PD bit indicates only the update, not the current state */ 84 unsigned int old_pin_detect:1; 85 }; 86 87 88 struct hdmi_audio_infoframe { 89 u8 type; /* 0x84 */ 90 u8 ver; /* 0x01 */ 91 u8 len; /* 0x0a */ 92 93 u8 checksum; 94 95 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ 96 u8 SS01_SF24; 97 u8 CXT04; 98 u8 CA; 99 u8 LFEPBL01_LSV36_DM_INH7; 100 }; 101 102 struct dp_audio_infoframe { 103 u8 type; /* 0x84 */ 104 u8 len; /* 0x1b */ 105 u8 ver; /* 0x11 << 2 */ 106 107 u8 CC02_CT47; /* match with HDMI infoframe from this on */ 108 u8 SS01_SF24; 109 u8 CXT04; 110 u8 CA; 111 u8 LFEPBL01_LSV36_DM_INH7; 112 }; 113 114 union audio_infoframe { 115 struct hdmi_audio_infoframe hdmi; 116 struct dp_audio_infoframe dp; 117 u8 bytes[0]; 118 }; 119 120 /* 121 * CEA speaker placement: 122 * 123 * FLH FCH FRH 124 * FLW FL FLC FC FRC FR FRW 125 * 126 * LFE 127 * TC 128 * 129 * RL RLC RC RRC RR 130 * 131 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to 132 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC. 133 */ 134 enum cea_speaker_placement { 135 FL = (1 << 0), /* Front Left */ 136 FC = (1 << 1), /* Front Center */ 137 FR = (1 << 2), /* Front Right */ 138 FLC = (1 << 3), /* Front Left Center */ 139 FRC = (1 << 4), /* Front Right Center */ 140 RL = (1 << 5), /* Rear Left */ 141 RC = (1 << 6), /* Rear Center */ 142 RR = (1 << 7), /* Rear Right */ 143 RLC = (1 << 8), /* Rear Left Center */ 144 RRC = (1 << 9), /* Rear Right Center */ 145 LFE = (1 << 10), /* Low Frequency Effect */ 146 FLW = (1 << 11), /* Front Left Wide */ 147 FRW = (1 << 12), /* Front Right Wide */ 148 FLH = (1 << 13), /* Front Left High */ 149 FCH = (1 << 14), /* Front Center High */ 150 FRH = (1 << 15), /* Front Right High */ 151 TC = (1 << 16), /* Top Center */ 152 }; 153 154 /* 155 * ELD SA bits in the CEA Speaker Allocation data block 156 */ 157 static int eld_speaker_allocation_bits[] = { 158 [0] = FL | FR, 159 [1] = LFE, 160 [2] = FC, 161 [3] = RL | RR, 162 [4] = RC, 163 [5] = FLC | FRC, 164 [6] = RLC | RRC, 165 /* the following are not defined in ELD yet */ 166 [7] = FLW | FRW, 167 [8] = FLH | FRH, 168 [9] = TC, 169 [10] = FCH, 170 }; 171 172 struct cea_channel_speaker_allocation { 173 int ca_index; 174 int speakers[8]; 175 176 /* derived values, just for convenience */ 177 int channels; 178 int spk_mask; 179 }; 180 181 /* 182 * ALSA sequence is: 183 * 184 * surround40 surround41 surround50 surround51 surround71 185 * ch0 front left = = = = 186 * ch1 front right = = = = 187 * ch2 rear left = = = = 188 * ch3 rear right = = = = 189 * ch4 LFE center center center 190 * ch5 LFE LFE 191 * ch6 side left 192 * ch7 side right 193 * 194 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR} 195 */ 196 static int hdmi_channel_mapping[0x32][8] = { 197 /* stereo */ 198 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }, 199 /* 2.1 */ 200 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }, 201 /* Dolby Surround */ 202 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 }, 203 /* surround40 */ 204 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 }, 205 /* 4ch */ 206 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 }, 207 /* surround41 */ 208 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 }, 209 /* surround50 */ 210 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 }, 211 /* surround51 */ 212 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 }, 213 /* 7.1 */ 214 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 }, 215 }; 216 217 /* 218 * This is an ordered list! 219 * 220 * The preceding ones have better chances to be selected by 221 * hdmi_channel_allocation(). 222 */ 223 static struct cea_channel_speaker_allocation channel_allocations[] = { 224 /* channel: 7 6 5 4 3 2 1 0 */ 225 { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } }, 226 /* 2.1 */ 227 { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } }, 228 /* Dolby Surround */ 229 { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } }, 230 /* surround40 */ 231 { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } }, 232 /* surround41 */ 233 { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } }, 234 /* surround50 */ 235 { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } }, 236 /* surround51 */ 237 { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } }, 238 /* 6.1 */ 239 { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } }, 240 /* surround71 */ 241 { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } }, 242 243 { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } }, 244 { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } }, 245 { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } }, 246 { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } }, 247 { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } }, 248 { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } }, 249 { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } }, 250 { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } }, 251 { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } }, 252 { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } }, 253 { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } }, 254 { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } }, 255 { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } }, 256 { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } }, 257 { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } }, 258 { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } }, 259 { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } }, 260 { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } }, 261 { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } }, 262 { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } }, 263 { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } }, 264 { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } }, 265 { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } }, 266 { .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } }, 267 { .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } }, 268 { .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } }, 269 { .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } }, 270 { .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } }, 271 { .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } }, 272 { .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } }, 273 { .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } }, 274 { .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } }, 275 { .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } }, 276 { .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } }, 277 { .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } }, 278 { .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } }, 279 { .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } }, 280 { .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } }, 281 { .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } }, 282 { .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } }, 283 { .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } }, 284 }; 285 286 287 /* 288 * HDMI routines 289 */ 290 291 static int hda_node_index(hda_nid_t *nids, hda_nid_t nid) 292 { 293 int i; 294 295 for (i = 0; nids[i]; i++) 296 if (nids[i] == nid) 297 return i; 298 299 snd_printk(KERN_WARNING "HDMI: nid %d not registered\n", nid); 300 return -EINVAL; 301 } 302 303 static void hdmi_get_show_eld(struct hda_codec *codec, hda_nid_t pin_nid, 304 struct hdmi_eld *eld) 305 { 306 if (!snd_hdmi_get_eld(eld, codec, pin_nid)) 307 snd_hdmi_show_eld(eld); 308 } 309 310 #ifdef BE_PARANOID 311 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 312 int *packet_index, int *byte_index) 313 { 314 int val; 315 316 val = snd_hda_codec_read(codec, pin_nid, 0, 317 AC_VERB_GET_HDMI_DIP_INDEX, 0); 318 319 *packet_index = val >> 5; 320 *byte_index = val & 0x1f; 321 } 322 #endif 323 324 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 325 int packet_index, int byte_index) 326 { 327 int val; 328 329 val = (packet_index << 5) | (byte_index & 0x1f); 330 331 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); 332 } 333 334 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, 335 unsigned char val) 336 { 337 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); 338 } 339 340 static void hdmi_enable_output(struct hda_codec *codec, hda_nid_t pin_nid) 341 { 342 /* Unmute */ 343 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 344 snd_hda_codec_write(codec, pin_nid, 0, 345 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); 346 /* Enable pin out */ 347 snd_hda_codec_write(codec, pin_nid, 0, 348 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); 349 } 350 351 static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t nid) 352 { 353 return 1 + snd_hda_codec_read(codec, nid, 0, 354 AC_VERB_GET_CVT_CHAN_COUNT, 0); 355 } 356 357 static void hdmi_set_channel_count(struct hda_codec *codec, 358 hda_nid_t nid, int chs) 359 { 360 if (chs != hdmi_get_channel_count(codec, nid)) 361 snd_hda_codec_write(codec, nid, 0, 362 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1); 363 } 364 365 366 /* 367 * Channel mapping routines 368 */ 369 370 /* 371 * Compute derived values in channel_allocations[]. 372 */ 373 static void init_channel_allocations(void) 374 { 375 int i, j; 376 struct cea_channel_speaker_allocation *p; 377 378 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 379 p = channel_allocations + i; 380 p->channels = 0; 381 p->spk_mask = 0; 382 for (j = 0; j < ARRAY_SIZE(p->speakers); j++) 383 if (p->speakers[j]) { 384 p->channels++; 385 p->spk_mask |= p->speakers[j]; 386 } 387 } 388 } 389 390 /* 391 * The transformation takes two steps: 392 * 393 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask 394 * spk_mask => (channel_allocations[]) => ai->CA 395 * 396 * TODO: it could select the wrong CA from multiple candidates. 397 */ 398 static int hdmi_channel_allocation(struct hda_codec *codec, hda_nid_t nid, 399 int channels) 400 { 401 struct hdmi_spec *spec = codec->spec; 402 struct hdmi_eld *eld; 403 int i; 404 int ca = 0; 405 int spk_mask = 0; 406 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE]; 407 408 /* 409 * CA defaults to 0 for basic stereo audio 410 */ 411 if (channels <= 2) 412 return 0; 413 414 i = hda_node_index(spec->pin_cvt, nid); 415 if (i < 0) 416 return 0; 417 eld = &spec->sink_eld[i]; 418 419 /* 420 * HDMI sink's ELD info cannot always be retrieved for now, e.g. 421 * in console or for audio devices. Assume the highest speakers 422 * configuration, to _not_ prohibit multi-channel audio playback. 423 */ 424 if (!eld->spk_alloc) 425 eld->spk_alloc = 0xffff; 426 427 /* 428 * expand ELD's speaker allocation mask 429 * 430 * ELD tells the speaker mask in a compact(paired) form, 431 * expand ELD's notions to match the ones used by Audio InfoFrame. 432 */ 433 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) { 434 if (eld->spk_alloc & (1 << i)) 435 spk_mask |= eld_speaker_allocation_bits[i]; 436 } 437 438 /* search for the first working match in the CA table */ 439 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 440 if (channels == channel_allocations[i].channels && 441 (spk_mask & channel_allocations[i].spk_mask) == 442 channel_allocations[i].spk_mask) { 443 ca = channel_allocations[i].ca_index; 444 break; 445 } 446 } 447 448 snd_print_channel_allocation(eld->spk_alloc, buf, sizeof(buf)); 449 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n", 450 ca, channels, buf); 451 452 return ca; 453 } 454 455 static void hdmi_debug_channel_mapping(struct hda_codec *codec, 456 hda_nid_t pin_nid) 457 { 458 #ifdef CONFIG_SND_DEBUG_VERBOSE 459 int i; 460 int slot; 461 462 for (i = 0; i < 8; i++) { 463 slot = snd_hda_codec_read(codec, pin_nid, 0, 464 AC_VERB_GET_HDMI_CHAN_SLOT, i); 465 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n", 466 slot >> 4, slot & 0xf); 467 } 468 #endif 469 } 470 471 472 static void hdmi_setup_channel_mapping(struct hda_codec *codec, 473 hda_nid_t pin_nid, 474 int ca) 475 { 476 int i; 477 int err; 478 479 if (hdmi_channel_mapping[ca][1] == 0) { 480 for (i = 0; i < channel_allocations[ca].channels; i++) 481 hdmi_channel_mapping[ca][i] = i | (i << 4); 482 for (; i < 8; i++) 483 hdmi_channel_mapping[ca][i] = 0xf | (i << 4); 484 } 485 486 for (i = 0; i < 8; i++) { 487 err = snd_hda_codec_write(codec, pin_nid, 0, 488 AC_VERB_SET_HDMI_CHAN_SLOT, 489 hdmi_channel_mapping[ca][i]); 490 if (err) { 491 snd_printdd(KERN_NOTICE 492 "HDMI: channel mapping failed\n"); 493 break; 494 } 495 } 496 497 hdmi_debug_channel_mapping(codec, pin_nid); 498 } 499 500 501 /* 502 * Audio InfoFrame routines 503 */ 504 505 /* 506 * Enable Audio InfoFrame Transmission 507 */ 508 static void hdmi_start_infoframe_trans(struct hda_codec *codec, 509 hda_nid_t pin_nid) 510 { 511 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 512 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 513 AC_DIPXMIT_BEST); 514 } 515 516 /* 517 * Disable Audio InfoFrame Transmission 518 */ 519 static void hdmi_stop_infoframe_trans(struct hda_codec *codec, 520 hda_nid_t pin_nid) 521 { 522 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 523 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 524 AC_DIPXMIT_DISABLE); 525 } 526 527 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) 528 { 529 #ifdef CONFIG_SND_DEBUG_VERBOSE 530 int i; 531 int size; 532 533 size = snd_hdmi_get_eld_size(codec, pin_nid); 534 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size); 535 536 for (i = 0; i < 8; i++) { 537 size = snd_hda_codec_read(codec, pin_nid, 0, 538 AC_VERB_GET_HDMI_DIP_SIZE, i); 539 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size); 540 } 541 #endif 542 } 543 544 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) 545 { 546 #ifdef BE_PARANOID 547 int i, j; 548 int size; 549 int pi, bi; 550 for (i = 0; i < 8; i++) { 551 size = snd_hda_codec_read(codec, pin_nid, 0, 552 AC_VERB_GET_HDMI_DIP_SIZE, i); 553 if (size == 0) 554 continue; 555 556 hdmi_set_dip_index(codec, pin_nid, i, 0x0); 557 for (j = 1; j < 1000; j++) { 558 hdmi_write_dip_byte(codec, pin_nid, 0x0); 559 hdmi_get_dip_index(codec, pin_nid, &pi, &bi); 560 if (pi != i) 561 snd_printd(KERN_INFO "dip index %d: %d != %d\n", 562 bi, pi, i); 563 if (bi == 0) /* byte index wrapped around */ 564 break; 565 } 566 snd_printd(KERN_INFO 567 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", 568 i, size, j); 569 } 570 #endif 571 } 572 573 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) 574 { 575 u8 *bytes = (u8 *)hdmi_ai; 576 u8 sum = 0; 577 int i; 578 579 hdmi_ai->checksum = 0; 580 581 for (i = 0; i < sizeof(*hdmi_ai); i++) 582 sum += bytes[i]; 583 584 hdmi_ai->checksum = -sum; 585 } 586 587 static void hdmi_fill_audio_infoframe(struct hda_codec *codec, 588 hda_nid_t pin_nid, 589 u8 *dip, int size) 590 { 591 int i; 592 593 hdmi_debug_dip_size(codec, pin_nid); 594 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ 595 596 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 597 for (i = 0; i < size; i++) 598 hdmi_write_dip_byte(codec, pin_nid, dip[i]); 599 } 600 601 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, 602 u8 *dip, int size) 603 { 604 u8 val; 605 int i; 606 607 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) 608 != AC_DIPXMIT_BEST) 609 return false; 610 611 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 612 for (i = 0; i < size; i++) { 613 val = snd_hda_codec_read(codec, pin_nid, 0, 614 AC_VERB_GET_HDMI_DIP_DATA, 0); 615 if (val != dip[i]) 616 return false; 617 } 618 619 return true; 620 } 621 622 static void hdmi_setup_audio_infoframe(struct hda_codec *codec, hda_nid_t nid, 623 struct snd_pcm_substream *substream) 624 { 625 struct hdmi_spec *spec = codec->spec; 626 hda_nid_t pin_nid; 627 int channels = substream->runtime->channels; 628 int ca; 629 int i; 630 union audio_infoframe ai; 631 632 ca = hdmi_channel_allocation(codec, nid, channels); 633 634 for (i = 0; i < spec->num_pins; i++) { 635 if (spec->pin_cvt[i] != nid) 636 continue; 637 if (!spec->sink_eld[i].monitor_present) 638 continue; 639 640 pin_nid = spec->pin[i]; 641 642 memset(&ai, 0, sizeof(ai)); 643 if (spec->sink_eld[i].conn_type == 0) { /* HDMI */ 644 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; 645 646 hdmi_ai->type = 0x84; 647 hdmi_ai->ver = 0x01; 648 hdmi_ai->len = 0x0a; 649 hdmi_ai->CC02_CT47 = channels - 1; 650 hdmi_ai->CA = ca; 651 hdmi_checksum_audio_infoframe(hdmi_ai); 652 } else if (spec->sink_eld[i].conn_type == 1) { /* DisplayPort */ 653 struct dp_audio_infoframe *dp_ai = &ai.dp; 654 655 dp_ai->type = 0x84; 656 dp_ai->len = 0x1b; 657 dp_ai->ver = 0x11 << 2; 658 dp_ai->CC02_CT47 = channels - 1; 659 dp_ai->CA = ca; 660 } else { 661 snd_printd("HDMI: unknown connection type at pin %d\n", 662 pin_nid); 663 continue; 664 } 665 666 /* 667 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or 668 * sizeof(*dp_ai) to avoid partial match/update problems when 669 * the user switches between HDMI/DP monitors. 670 */ 671 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, 672 sizeof(ai))) { 673 snd_printdd("hdmi_setup_audio_infoframe: " 674 "cvt=%d pin=%d channels=%d\n", 675 nid, pin_nid, 676 channels); 677 hdmi_setup_channel_mapping(codec, pin_nid, ca); 678 hdmi_stop_infoframe_trans(codec, pin_nid); 679 hdmi_fill_audio_infoframe(codec, pin_nid, 680 ai.bytes, sizeof(ai)); 681 hdmi_start_infoframe_trans(codec, pin_nid); 682 } 683 } 684 } 685 686 687 /* 688 * Unsolicited events 689 */ 690 691 static void hdmi_present_sense(struct hda_codec *codec, hda_nid_t pin_nid, 692 struct hdmi_eld *eld); 693 694 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res) 695 { 696 struct hdmi_spec *spec = codec->spec; 697 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 698 int pind = !!(res & AC_UNSOL_RES_PD); 699 int eldv = !!(res & AC_UNSOL_RES_ELDV); 700 int index; 701 702 printk(KERN_INFO 703 "HDMI hot plug event: Pin=%d Presence_Detect=%d ELD_Valid=%d\n", 704 tag, pind, eldv); 705 706 index = hda_node_index(spec->pin, tag); 707 if (index < 0) 708 return; 709 710 if (spec->old_pin_detect) { 711 if (pind) 712 hdmi_present_sense(codec, tag, &spec->sink_eld[index]); 713 pind = spec->sink_eld[index].monitor_present; 714 } 715 716 spec->sink_eld[index].monitor_present = pind; 717 spec->sink_eld[index].eld_valid = eldv; 718 719 if (pind && eldv) { 720 hdmi_get_show_eld(codec, spec->pin[index], 721 &spec->sink_eld[index]); 722 /* TODO: do real things about ELD */ 723 } 724 725 snd_hda_input_jack_report(codec, tag); 726 } 727 728 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) 729 { 730 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 731 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 732 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); 733 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); 734 735 printk(KERN_INFO 736 "HDMI CP event: PIN=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", 737 tag, 738 subtag, 739 cp_state, 740 cp_ready); 741 742 /* TODO */ 743 if (cp_state) 744 ; 745 if (cp_ready) 746 ; 747 } 748 749 750 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) 751 { 752 struct hdmi_spec *spec = codec->spec; 753 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 754 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 755 756 if (hda_node_index(spec->pin, tag) < 0) { 757 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag); 758 return; 759 } 760 761 if (subtag == 0) 762 hdmi_intrinsic_event(codec, res); 763 else 764 hdmi_non_intrinsic_event(codec, res); 765 } 766 767 /* 768 * Callbacks 769 */ 770 771 /* HBR should be Non-PCM, 8 channels */ 772 #define is_hbr_format(format) \ 773 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) 774 775 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t nid, 776 u32 stream_tag, int format) 777 { 778 struct hdmi_spec *spec = codec->spec; 779 int pinctl; 780 int new_pinctl = 0; 781 int i; 782 783 for (i = 0; i < spec->num_pins; i++) { 784 if (spec->pin_cvt[i] != nid) 785 continue; 786 if (!(snd_hda_query_pin_caps(codec, spec->pin[i]) & AC_PINCAP_HBR)) 787 continue; 788 789 pinctl = snd_hda_codec_read(codec, spec->pin[i], 0, 790 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 791 792 new_pinctl = pinctl & ~AC_PINCTL_EPT; 793 if (is_hbr_format(format)) 794 new_pinctl |= AC_PINCTL_EPT_HBR; 795 else 796 new_pinctl |= AC_PINCTL_EPT_NATIVE; 797 798 snd_printdd("hdmi_setup_stream: " 799 "NID=0x%x, %spinctl=0x%x\n", 800 spec->pin[i], 801 pinctl == new_pinctl ? "" : "new-", 802 new_pinctl); 803 804 if (pinctl != new_pinctl) 805 snd_hda_codec_write(codec, spec->pin[i], 0, 806 AC_VERB_SET_PIN_WIDGET_CONTROL, 807 new_pinctl); 808 } 809 810 if (is_hbr_format(format) && !new_pinctl) { 811 snd_printdd("hdmi_setup_stream: HBR is not supported\n"); 812 return -EINVAL; 813 } 814 815 snd_hda_codec_setup_stream(codec, nid, stream_tag, 0, format); 816 return 0; 817 } 818 819 /* 820 * HDA PCM callbacks 821 */ 822 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, 823 struct hda_codec *codec, 824 struct snd_pcm_substream *substream) 825 { 826 struct hdmi_spec *spec = codec->spec; 827 struct hdmi_eld *eld; 828 struct hda_pcm_stream *codec_pars; 829 struct snd_pcm_runtime *runtime = substream->runtime; 830 unsigned int idx; 831 832 for (idx = 0; idx < spec->num_cvts; idx++) 833 if (hinfo->nid == spec->cvt[idx]) 834 break; 835 if (snd_BUG_ON(idx >= spec->num_cvts) || 836 snd_BUG_ON(idx >= spec->num_pins)) 837 return -EINVAL; 838 839 /* save the PCM info the codec provides */ 840 codec_pars = &spec->codec_pcm_pars[idx]; 841 if (!codec_pars->rates) 842 *codec_pars = *hinfo; 843 844 eld = &spec->sink_eld[idx]; 845 if (!static_hdmi_pcm && eld->eld_valid && eld->sad_count > 0) { 846 hdmi_eld_update_pcm_info(eld, hinfo, codec_pars); 847 if (hinfo->channels_min > hinfo->channels_max || 848 !hinfo->rates || !hinfo->formats) 849 return -ENODEV; 850 } else { 851 /* fallback to the codec default */ 852 hinfo->channels_max = codec_pars->channels_max; 853 hinfo->rates = codec_pars->rates; 854 hinfo->formats = codec_pars->formats; 855 hinfo->maxbps = codec_pars->maxbps; 856 } 857 /* store the updated parameters */ 858 runtime->hw.channels_min = hinfo->channels_min; 859 runtime->hw.channels_max = hinfo->channels_max; 860 runtime->hw.formats = hinfo->formats; 861 runtime->hw.rates = hinfo->rates; 862 863 snd_pcm_hw_constraint_step(substream->runtime, 0, 864 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 865 return 0; 866 } 867 868 /* 869 * HDA/HDMI auto parsing 870 */ 871 static int hdmi_read_pin_conn(struct hda_codec *codec, hda_nid_t pin_nid) 872 { 873 struct hdmi_spec *spec = codec->spec; 874 hda_nid_t conn_list[HDA_MAX_CONNECTIONS]; 875 int conn_len, curr; 876 int index; 877 878 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { 879 snd_printk(KERN_WARNING 880 "HDMI: pin %d wcaps %#x " 881 "does not support connection list\n", 882 pin_nid, get_wcaps(codec, pin_nid)); 883 return -EINVAL; 884 } 885 886 conn_len = snd_hda_get_connections(codec, pin_nid, conn_list, 887 HDA_MAX_CONNECTIONS); 888 if (conn_len > 1) 889 curr = snd_hda_codec_read(codec, pin_nid, 0, 890 AC_VERB_GET_CONNECT_SEL, 0); 891 else 892 curr = 0; 893 894 index = hda_node_index(spec->pin, pin_nid); 895 if (index < 0) 896 return -EINVAL; 897 898 spec->pin_cvt[index] = conn_list[curr]; 899 900 return 0; 901 } 902 903 static void hdmi_present_sense(struct hda_codec *codec, hda_nid_t pin_nid, 904 struct hdmi_eld *eld) 905 { 906 int present = snd_hda_pin_sense(codec, pin_nid); 907 908 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); 909 eld->eld_valid = !!(present & AC_PINSENSE_ELDV); 910 911 if (present & AC_PINSENSE_ELDV) 912 hdmi_get_show_eld(codec, pin_nid, eld); 913 } 914 915 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) 916 { 917 struct hdmi_spec *spec = codec->spec; 918 int err; 919 920 if (spec->num_pins >= MAX_HDMI_PINS) { 921 snd_printk(KERN_WARNING 922 "HDMI: no space for pin %d\n", pin_nid); 923 return -E2BIG; 924 } 925 926 err = snd_hda_input_jack_add(codec, pin_nid, 927 SND_JACK_VIDEOOUT, NULL); 928 if (err < 0) 929 return err; 930 snd_hda_input_jack_report(codec, pin_nid); 931 932 hdmi_present_sense(codec, pin_nid, &spec->sink_eld[spec->num_pins]); 933 934 spec->pin[spec->num_pins] = pin_nid; 935 spec->num_pins++; 936 937 return hdmi_read_pin_conn(codec, pin_nid); 938 } 939 940 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t nid) 941 { 942 int i, found_pin = 0; 943 struct hdmi_spec *spec = codec->spec; 944 945 for (i = 0; i < spec->num_pins; i++) 946 if (nid == spec->pin_cvt[i]) { 947 found_pin = 1; 948 break; 949 } 950 951 if (!found_pin) { 952 snd_printdd("HDMI: Skipping node %d (no connection)\n", nid); 953 return -EINVAL; 954 } 955 956 if (snd_BUG_ON(spec->num_cvts >= MAX_HDMI_CVTS)) 957 return -E2BIG; 958 959 spec->cvt[spec->num_cvts] = nid; 960 spec->num_cvts++; 961 962 return 0; 963 } 964 965 static int hdmi_parse_codec(struct hda_codec *codec) 966 { 967 hda_nid_t nid; 968 int i, nodes; 969 int num_tmp_cvts = 0; 970 hda_nid_t tmp_cvt[MAX_HDMI_CVTS]; 971 972 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid); 973 if (!nid || nodes < 0) { 974 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n"); 975 return -EINVAL; 976 } 977 978 for (i = 0; i < nodes; i++, nid++) { 979 unsigned int caps; 980 unsigned int type; 981 unsigned int config; 982 983 caps = snd_hda_param_read(codec, nid, AC_PAR_AUDIO_WIDGET_CAP); 984 type = get_wcaps_type(caps); 985 986 if (!(caps & AC_WCAP_DIGITAL)) 987 continue; 988 989 switch (type) { 990 case AC_WID_AUD_OUT: 991 if (num_tmp_cvts >= MAX_HDMI_CVTS) { 992 snd_printk(KERN_WARNING 993 "HDMI: no space for converter %d\n", nid); 994 continue; 995 } 996 tmp_cvt[num_tmp_cvts] = nid; 997 num_tmp_cvts++; 998 break; 999 case AC_WID_PIN: 1000 caps = snd_hda_param_read(codec, nid, AC_PAR_PIN_CAP); 1001 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) 1002 continue; 1003 1004 config = snd_hda_codec_read(codec, nid, 0, 1005 AC_VERB_GET_CONFIG_DEFAULT, 0); 1006 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE) 1007 continue; 1008 1009 hdmi_add_pin(codec, nid); 1010 break; 1011 } 1012 } 1013 1014 for (i = 0; i < num_tmp_cvts; i++) 1015 hdmi_add_cvt(codec, tmp_cvt[i]); 1016 1017 /* 1018 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event 1019 * can be lost and presence sense verb will become inaccurate if the 1020 * HDA link is powered off at hot plug or hw initialization time. 1021 */ 1022 #ifdef CONFIG_SND_HDA_POWER_SAVE 1023 if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) & 1024 AC_PWRST_EPSS)) 1025 codec->bus->power_keep_link_on = 1; 1026 #endif 1027 1028 return 0; 1029 } 1030 1031 /* 1032 */ 1033 static char *generic_hdmi_pcm_names[MAX_HDMI_CVTS] = { 1034 "HDMI 0", 1035 "HDMI 1", 1036 "HDMI 2", 1037 }; 1038 1039 /* 1040 * HDMI callbacks 1041 */ 1042 1043 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 1044 struct hda_codec *codec, 1045 unsigned int stream_tag, 1046 unsigned int format, 1047 struct snd_pcm_substream *substream) 1048 { 1049 hdmi_set_channel_count(codec, hinfo->nid, 1050 substream->runtime->channels); 1051 1052 hdmi_setup_audio_infoframe(codec, hinfo->nid, substream); 1053 1054 return hdmi_setup_stream(codec, hinfo->nid, stream_tag, format); 1055 } 1056 1057 static const struct hda_pcm_stream generic_hdmi_pcm_playback = { 1058 .substreams = 1, 1059 .channels_min = 2, 1060 .ops = { 1061 .open = hdmi_pcm_open, 1062 .prepare = generic_hdmi_playback_pcm_prepare, 1063 }, 1064 }; 1065 1066 static int generic_hdmi_build_pcms(struct hda_codec *codec) 1067 { 1068 struct hdmi_spec *spec = codec->spec; 1069 struct hda_pcm *info = spec->pcm_rec; 1070 int i; 1071 1072 codec->num_pcms = spec->num_cvts; 1073 codec->pcm_info = info; 1074 1075 for (i = 0; i < codec->num_pcms; i++, info++) { 1076 unsigned int chans; 1077 struct hda_pcm_stream *pstr; 1078 1079 chans = get_wcaps(codec, spec->cvt[i]); 1080 chans = get_wcaps_channels(chans); 1081 1082 info->name = generic_hdmi_pcm_names[i]; 1083 info->pcm_type = HDA_PCM_TYPE_HDMI; 1084 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 1085 if (spec->pcm_playback) 1086 *pstr = *spec->pcm_playback; 1087 else 1088 *pstr = generic_hdmi_pcm_playback; 1089 pstr->nid = spec->cvt[i]; 1090 if (pstr->channels_max <= 2 && chans && chans <= 16) 1091 pstr->channels_max = chans; 1092 } 1093 1094 return 0; 1095 } 1096 1097 static int generic_hdmi_build_controls(struct hda_codec *codec) 1098 { 1099 struct hdmi_spec *spec = codec->spec; 1100 int err; 1101 int i; 1102 1103 for (i = 0; i < codec->num_pcms; i++) { 1104 err = snd_hda_create_spdif_out_ctls(codec, spec->cvt[i]); 1105 if (err < 0) 1106 return err; 1107 } 1108 1109 return 0; 1110 } 1111 1112 static int generic_hdmi_init(struct hda_codec *codec) 1113 { 1114 struct hdmi_spec *spec = codec->spec; 1115 int i; 1116 1117 for (i = 0; spec->pin[i]; i++) { 1118 hdmi_enable_output(codec, spec->pin[i]); 1119 snd_hda_codec_write(codec, spec->pin[i], 0, 1120 AC_VERB_SET_UNSOLICITED_ENABLE, 1121 AC_USRSP_EN | spec->pin[i]); 1122 } 1123 return 0; 1124 } 1125 1126 static void generic_hdmi_free(struct hda_codec *codec) 1127 { 1128 struct hdmi_spec *spec = codec->spec; 1129 int i; 1130 1131 for (i = 0; i < spec->num_pins; i++) 1132 snd_hda_eld_proc_free(codec, &spec->sink_eld[i]); 1133 snd_hda_input_jack_free(codec); 1134 1135 kfree(spec); 1136 } 1137 1138 static const struct hda_codec_ops generic_hdmi_patch_ops = { 1139 .init = generic_hdmi_init, 1140 .free = generic_hdmi_free, 1141 .build_pcms = generic_hdmi_build_pcms, 1142 .build_controls = generic_hdmi_build_controls, 1143 .unsol_event = hdmi_unsol_event, 1144 }; 1145 1146 static int patch_generic_hdmi(struct hda_codec *codec) 1147 { 1148 struct hdmi_spec *spec; 1149 int i; 1150 1151 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 1152 if (spec == NULL) 1153 return -ENOMEM; 1154 1155 codec->spec = spec; 1156 if (hdmi_parse_codec(codec) < 0) { 1157 codec->spec = NULL; 1158 kfree(spec); 1159 return -EINVAL; 1160 } 1161 codec->patch_ops = generic_hdmi_patch_ops; 1162 1163 for (i = 0; i < spec->num_pins; i++) 1164 snd_hda_eld_proc_new(codec, &spec->sink_eld[i], i); 1165 1166 init_channel_allocations(); 1167 1168 return 0; 1169 } 1170 1171 /* 1172 * Nvidia specific implementations 1173 */ 1174 1175 #define Nv_VERB_SET_Channel_Allocation 0xF79 1176 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A 1177 #define Nv_VERB_SET_Audio_Protection_On 0xF98 1178 #define Nv_VERB_SET_Audio_Protection_Off 0xF99 1179 1180 #define nvhdmi_master_con_nid_7x 0x04 1181 #define nvhdmi_master_pin_nid_7x 0x05 1182 1183 static const hda_nid_t nvhdmi_con_nids_7x[4] = { 1184 /*front, rear, clfe, rear_surr */ 1185 0x6, 0x8, 0xa, 0xc, 1186 }; 1187 1188 static const struct hda_verb nvhdmi_basic_init_7x[] = { 1189 /* set audio protect on */ 1190 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 1191 /* enable digital output on pin widget */ 1192 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 1193 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 1194 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 1195 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 1196 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 1197 {} /* terminator */ 1198 }; 1199 1200 #ifdef LIMITED_RATE_FMT_SUPPORT 1201 /* support only the safe format and rate */ 1202 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 1203 #define SUPPORTED_MAXBPS 16 1204 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE 1205 #else 1206 /* support all rates and formats */ 1207 #define SUPPORTED_RATES \ 1208 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ 1209 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ 1210 SNDRV_PCM_RATE_192000) 1211 #define SUPPORTED_MAXBPS 24 1212 #define SUPPORTED_FORMATS \ 1213 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 1214 #endif 1215 1216 static int nvhdmi_7x_init(struct hda_codec *codec) 1217 { 1218 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x); 1219 return 0; 1220 } 1221 1222 static unsigned int channels_2_6_8[] = { 1223 2, 6, 8 1224 }; 1225 1226 static unsigned int channels_2_8[] = { 1227 2, 8 1228 }; 1229 1230 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { 1231 .count = ARRAY_SIZE(channels_2_6_8), 1232 .list = channels_2_6_8, 1233 .mask = 0, 1234 }; 1235 1236 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { 1237 .count = ARRAY_SIZE(channels_2_8), 1238 .list = channels_2_8, 1239 .mask = 0, 1240 }; 1241 1242 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, 1243 struct hda_codec *codec, 1244 struct snd_pcm_substream *substream) 1245 { 1246 struct hdmi_spec *spec = codec->spec; 1247 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; 1248 1249 switch (codec->preset->id) { 1250 case 0x10de0002: 1251 case 0x10de0003: 1252 case 0x10de0005: 1253 case 0x10de0006: 1254 hw_constraints_channels = &hw_constraints_2_8_channels; 1255 break; 1256 case 0x10de0007: 1257 hw_constraints_channels = &hw_constraints_2_6_8_channels; 1258 break; 1259 default: 1260 break; 1261 } 1262 1263 if (hw_constraints_channels != NULL) { 1264 snd_pcm_hw_constraint_list(substream->runtime, 0, 1265 SNDRV_PCM_HW_PARAM_CHANNELS, 1266 hw_constraints_channels); 1267 } else { 1268 snd_pcm_hw_constraint_step(substream->runtime, 0, 1269 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1270 } 1271 1272 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 1273 } 1274 1275 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, 1276 struct hda_codec *codec, 1277 struct snd_pcm_substream *substream) 1278 { 1279 struct hdmi_spec *spec = codec->spec; 1280 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 1281 } 1282 1283 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 1284 struct hda_codec *codec, 1285 unsigned int stream_tag, 1286 unsigned int format, 1287 struct snd_pcm_substream *substream) 1288 { 1289 struct hdmi_spec *spec = codec->spec; 1290 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 1291 stream_tag, format, substream); 1292 } 1293 1294 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, 1295 int channels) 1296 { 1297 unsigned int chanmask; 1298 int chan = channels ? (channels - 1) : 1; 1299 1300 switch (channels) { 1301 default: 1302 case 0: 1303 case 2: 1304 chanmask = 0x00; 1305 break; 1306 case 4: 1307 chanmask = 0x08; 1308 break; 1309 case 6: 1310 chanmask = 0x0b; 1311 break; 1312 case 8: 1313 chanmask = 0x13; 1314 break; 1315 } 1316 1317 /* Set the audio infoframe channel allocation and checksum fields. The 1318 * channel count is computed implicitly by the hardware. */ 1319 snd_hda_codec_write(codec, 0x1, 0, 1320 Nv_VERB_SET_Channel_Allocation, chanmask); 1321 1322 snd_hda_codec_write(codec, 0x1, 0, 1323 Nv_VERB_SET_Info_Frame_Checksum, 1324 (0x71 - chan - chanmask)); 1325 } 1326 1327 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, 1328 struct hda_codec *codec, 1329 struct snd_pcm_substream *substream) 1330 { 1331 struct hdmi_spec *spec = codec->spec; 1332 int i; 1333 1334 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 1335 0, AC_VERB_SET_CHANNEL_STREAMID, 0); 1336 for (i = 0; i < 4; i++) { 1337 /* set the stream id */ 1338 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 1339 AC_VERB_SET_CHANNEL_STREAMID, 0); 1340 /* set the stream format */ 1341 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 1342 AC_VERB_SET_STREAM_FORMAT, 0); 1343 } 1344 1345 /* The audio hardware sends a channel count of 0x7 (8ch) when all the 1346 * streams are disabled. */ 1347 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 1348 1349 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 1350 } 1351 1352 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, 1353 struct hda_codec *codec, 1354 unsigned int stream_tag, 1355 unsigned int format, 1356 struct snd_pcm_substream *substream) 1357 { 1358 int chs; 1359 unsigned int dataDCC1, dataDCC2, channel_id; 1360 int i; 1361 1362 mutex_lock(&codec->spdif_mutex); 1363 1364 chs = substream->runtime->channels; 1365 1366 dataDCC1 = AC_DIG1_ENABLE | AC_DIG1_COPYRIGHT; 1367 dataDCC2 = 0x2; 1368 1369 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ 1370 if (codec->spdif_status_reset && (codec->spdif_ctls & AC_DIG1_ENABLE)) 1371 snd_hda_codec_write(codec, 1372 nvhdmi_master_con_nid_7x, 1373 0, 1374 AC_VERB_SET_DIGI_CONVERT_1, 1375 codec->spdif_ctls & ~AC_DIG1_ENABLE & 0xff); 1376 1377 /* set the stream id */ 1378 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 1379 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); 1380 1381 /* set the stream format */ 1382 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 1383 AC_VERB_SET_STREAM_FORMAT, format); 1384 1385 /* turn on again (if needed) */ 1386 /* enable and set the channel status audio/data flag */ 1387 if (codec->spdif_status_reset && (codec->spdif_ctls & AC_DIG1_ENABLE)) { 1388 snd_hda_codec_write(codec, 1389 nvhdmi_master_con_nid_7x, 1390 0, 1391 AC_VERB_SET_DIGI_CONVERT_1, 1392 codec->spdif_ctls & 0xff); 1393 snd_hda_codec_write(codec, 1394 nvhdmi_master_con_nid_7x, 1395 0, 1396 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 1397 } 1398 1399 for (i = 0; i < 4; i++) { 1400 if (chs == 2) 1401 channel_id = 0; 1402 else 1403 channel_id = i * 2; 1404 1405 /* turn off SPDIF once; 1406 *otherwise the IEC958 bits won't be updated 1407 */ 1408 if (codec->spdif_status_reset && 1409 (codec->spdif_ctls & AC_DIG1_ENABLE)) 1410 snd_hda_codec_write(codec, 1411 nvhdmi_con_nids_7x[i], 1412 0, 1413 AC_VERB_SET_DIGI_CONVERT_1, 1414 codec->spdif_ctls & ~AC_DIG1_ENABLE & 0xff); 1415 /* set the stream id */ 1416 snd_hda_codec_write(codec, 1417 nvhdmi_con_nids_7x[i], 1418 0, 1419 AC_VERB_SET_CHANNEL_STREAMID, 1420 (stream_tag << 4) | channel_id); 1421 /* set the stream format */ 1422 snd_hda_codec_write(codec, 1423 nvhdmi_con_nids_7x[i], 1424 0, 1425 AC_VERB_SET_STREAM_FORMAT, 1426 format); 1427 /* turn on again (if needed) */ 1428 /* enable and set the channel status audio/data flag */ 1429 if (codec->spdif_status_reset && 1430 (codec->spdif_ctls & AC_DIG1_ENABLE)) { 1431 snd_hda_codec_write(codec, 1432 nvhdmi_con_nids_7x[i], 1433 0, 1434 AC_VERB_SET_DIGI_CONVERT_1, 1435 codec->spdif_ctls & 0xff); 1436 snd_hda_codec_write(codec, 1437 nvhdmi_con_nids_7x[i], 1438 0, 1439 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 1440 } 1441 } 1442 1443 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); 1444 1445 mutex_unlock(&codec->spdif_mutex); 1446 return 0; 1447 } 1448 1449 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { 1450 .substreams = 1, 1451 .channels_min = 2, 1452 .channels_max = 8, 1453 .nid = nvhdmi_master_con_nid_7x, 1454 .rates = SUPPORTED_RATES, 1455 .maxbps = SUPPORTED_MAXBPS, 1456 .formats = SUPPORTED_FORMATS, 1457 .ops = { 1458 .open = simple_playback_pcm_open, 1459 .close = nvhdmi_8ch_7x_pcm_close, 1460 .prepare = nvhdmi_8ch_7x_pcm_prepare 1461 }, 1462 }; 1463 1464 static const struct hda_pcm_stream nvhdmi_pcm_playback_2ch = { 1465 .substreams = 1, 1466 .channels_min = 2, 1467 .channels_max = 2, 1468 .nid = nvhdmi_master_con_nid_7x, 1469 .rates = SUPPORTED_RATES, 1470 .maxbps = SUPPORTED_MAXBPS, 1471 .formats = SUPPORTED_FORMATS, 1472 .ops = { 1473 .open = simple_playback_pcm_open, 1474 .close = simple_playback_pcm_close, 1475 .prepare = simple_playback_pcm_prepare 1476 }, 1477 }; 1478 1479 static const struct hda_codec_ops nvhdmi_patch_ops_8ch_7x = { 1480 .build_controls = generic_hdmi_build_controls, 1481 .build_pcms = generic_hdmi_build_pcms, 1482 .init = nvhdmi_7x_init, 1483 .free = generic_hdmi_free, 1484 }; 1485 1486 static const struct hda_codec_ops nvhdmi_patch_ops_2ch = { 1487 .build_controls = generic_hdmi_build_controls, 1488 .build_pcms = generic_hdmi_build_pcms, 1489 .init = nvhdmi_7x_init, 1490 .free = generic_hdmi_free, 1491 }; 1492 1493 static int patch_nvhdmi_8ch_89(struct hda_codec *codec) 1494 { 1495 struct hdmi_spec *spec; 1496 int err = patch_generic_hdmi(codec); 1497 1498 if (err < 0) 1499 return err; 1500 spec = codec->spec; 1501 spec->old_pin_detect = 1; 1502 return 0; 1503 } 1504 1505 static int patch_nvhdmi_2ch(struct hda_codec *codec) 1506 { 1507 struct hdmi_spec *spec; 1508 1509 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 1510 if (spec == NULL) 1511 return -ENOMEM; 1512 1513 codec->spec = spec; 1514 1515 spec->multiout.num_dacs = 0; /* no analog */ 1516 spec->multiout.max_channels = 2; 1517 spec->multiout.dig_out_nid = nvhdmi_master_con_nid_7x; 1518 spec->old_pin_detect = 1; 1519 spec->num_cvts = 1; 1520 spec->cvt[0] = nvhdmi_master_con_nid_7x; 1521 spec->pcm_playback = &nvhdmi_pcm_playback_2ch; 1522 1523 codec->patch_ops = nvhdmi_patch_ops_2ch; 1524 1525 return 0; 1526 } 1527 1528 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) 1529 { 1530 struct hdmi_spec *spec; 1531 int err = patch_nvhdmi_2ch(codec); 1532 1533 if (err < 0) 1534 return err; 1535 spec = codec->spec; 1536 spec->multiout.max_channels = 8; 1537 spec->pcm_playback = &nvhdmi_pcm_playback_8ch_7x; 1538 codec->patch_ops = nvhdmi_patch_ops_8ch_7x; 1539 1540 /* Initialize the audio infoframe channel mask and checksum to something 1541 * valid */ 1542 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 1543 1544 return 0; 1545 } 1546 1547 /* 1548 * ATI-specific implementations 1549 * 1550 * FIXME: we may omit the whole this and use the generic code once after 1551 * it's confirmed to work. 1552 */ 1553 1554 #define ATIHDMI_CVT_NID 0x02 /* audio converter */ 1555 #define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */ 1556 1557 static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 1558 struct hda_codec *codec, 1559 unsigned int stream_tag, 1560 unsigned int format, 1561 struct snd_pcm_substream *substream) 1562 { 1563 struct hdmi_spec *spec = codec->spec; 1564 int chans = substream->runtime->channels; 1565 int i, err; 1566 1567 err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format, 1568 substream); 1569 if (err < 0) 1570 return err; 1571 snd_hda_codec_write(codec, spec->cvt[0], 0, AC_VERB_SET_CVT_CHAN_COUNT, 1572 chans - 1); 1573 /* FIXME: XXX */ 1574 for (i = 0; i < chans; i++) { 1575 snd_hda_codec_write(codec, spec->cvt[0], 0, 1576 AC_VERB_SET_HDMI_CHAN_SLOT, 1577 (i << 4) | i); 1578 } 1579 return 0; 1580 } 1581 1582 static const struct hda_pcm_stream atihdmi_pcm_digital_playback = { 1583 .substreams = 1, 1584 .channels_min = 2, 1585 .channels_max = 2, 1586 .nid = ATIHDMI_CVT_NID, 1587 .ops = { 1588 .open = simple_playback_pcm_open, 1589 .close = simple_playback_pcm_close, 1590 .prepare = atihdmi_playback_pcm_prepare 1591 }, 1592 }; 1593 1594 static const struct hda_verb atihdmi_basic_init[] = { 1595 /* enable digital output on pin widget */ 1596 { 0x03, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT }, 1597 {} /* terminator */ 1598 }; 1599 1600 static int atihdmi_init(struct hda_codec *codec) 1601 { 1602 struct hdmi_spec *spec = codec->spec; 1603 1604 snd_hda_sequence_write(codec, atihdmi_basic_init); 1605 /* SI codec requires to unmute the pin */ 1606 if (get_wcaps(codec, spec->pin[0]) & AC_WCAP_OUT_AMP) 1607 snd_hda_codec_write(codec, spec->pin[0], 0, 1608 AC_VERB_SET_AMP_GAIN_MUTE, 1609 AMP_OUT_UNMUTE); 1610 return 0; 1611 } 1612 1613 static const struct hda_codec_ops atihdmi_patch_ops = { 1614 .build_controls = generic_hdmi_build_controls, 1615 .build_pcms = generic_hdmi_build_pcms, 1616 .init = atihdmi_init, 1617 .free = generic_hdmi_free, 1618 }; 1619 1620 1621 static int patch_atihdmi(struct hda_codec *codec) 1622 { 1623 struct hdmi_spec *spec; 1624 1625 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 1626 if (spec == NULL) 1627 return -ENOMEM; 1628 1629 codec->spec = spec; 1630 1631 spec->multiout.num_dacs = 0; /* no analog */ 1632 spec->multiout.max_channels = 2; 1633 spec->multiout.dig_out_nid = ATIHDMI_CVT_NID; 1634 spec->num_cvts = 1; 1635 spec->cvt[0] = ATIHDMI_CVT_NID; 1636 spec->pin[0] = ATIHDMI_PIN_NID; 1637 spec->pcm_playback = &atihdmi_pcm_digital_playback; 1638 1639 codec->patch_ops = atihdmi_patch_ops; 1640 1641 return 0; 1642 } 1643 1644 1645 /* 1646 * patch entries 1647 */ 1648 static const struct hda_codec_preset snd_hda_preset_hdmi[] = { 1649 { .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi }, 1650 { .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi }, 1651 { .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi }, 1652 { .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi }, 1653 { .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi }, 1654 { .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi }, 1655 { .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi }, 1656 { .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x }, 1657 { .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x }, 1658 { .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x }, 1659 { .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x }, 1660 { .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x }, 1661 { .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, 1662 { .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, 1663 { .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_nvhdmi_8ch_89 }, 1664 { .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, 1665 { .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, 1666 { .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, 1667 { .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, 1668 { .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, 1669 { .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, 1670 { .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, 1671 { .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, 1672 /* 17 is known to be absent */ 1673 { .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, 1674 { .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, 1675 { .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, 1676 { .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, 1677 { .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, 1678 { .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, 1679 { .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, 1680 { .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, 1681 { .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, 1682 { .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, 1683 { .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch }, 1684 { .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch }, 1685 { .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi }, 1686 { .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi }, 1687 { .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi }, 1688 { .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi }, 1689 { .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi }, 1690 { .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi }, 1691 { .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi }, 1692 { .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi }, 1693 {} /* terminator */ 1694 }; 1695 1696 MODULE_ALIAS("snd-hda-codec-id:1002793c"); 1697 MODULE_ALIAS("snd-hda-codec-id:10027919"); 1698 MODULE_ALIAS("snd-hda-codec-id:1002791a"); 1699 MODULE_ALIAS("snd-hda-codec-id:1002aa01"); 1700 MODULE_ALIAS("snd-hda-codec-id:10951390"); 1701 MODULE_ALIAS("snd-hda-codec-id:10951392"); 1702 MODULE_ALIAS("snd-hda-codec-id:10de0002"); 1703 MODULE_ALIAS("snd-hda-codec-id:10de0003"); 1704 MODULE_ALIAS("snd-hda-codec-id:10de0005"); 1705 MODULE_ALIAS("snd-hda-codec-id:10de0006"); 1706 MODULE_ALIAS("snd-hda-codec-id:10de0007"); 1707 MODULE_ALIAS("snd-hda-codec-id:10de000a"); 1708 MODULE_ALIAS("snd-hda-codec-id:10de000b"); 1709 MODULE_ALIAS("snd-hda-codec-id:10de000c"); 1710 MODULE_ALIAS("snd-hda-codec-id:10de000d"); 1711 MODULE_ALIAS("snd-hda-codec-id:10de0010"); 1712 MODULE_ALIAS("snd-hda-codec-id:10de0011"); 1713 MODULE_ALIAS("snd-hda-codec-id:10de0012"); 1714 MODULE_ALIAS("snd-hda-codec-id:10de0013"); 1715 MODULE_ALIAS("snd-hda-codec-id:10de0014"); 1716 MODULE_ALIAS("snd-hda-codec-id:10de0015"); 1717 MODULE_ALIAS("snd-hda-codec-id:10de0016"); 1718 MODULE_ALIAS("snd-hda-codec-id:10de0018"); 1719 MODULE_ALIAS("snd-hda-codec-id:10de0019"); 1720 MODULE_ALIAS("snd-hda-codec-id:10de001a"); 1721 MODULE_ALIAS("snd-hda-codec-id:10de001b"); 1722 MODULE_ALIAS("snd-hda-codec-id:10de001c"); 1723 MODULE_ALIAS("snd-hda-codec-id:10de0040"); 1724 MODULE_ALIAS("snd-hda-codec-id:10de0041"); 1725 MODULE_ALIAS("snd-hda-codec-id:10de0042"); 1726 MODULE_ALIAS("snd-hda-codec-id:10de0043"); 1727 MODULE_ALIAS("snd-hda-codec-id:10de0044"); 1728 MODULE_ALIAS("snd-hda-codec-id:10de0067"); 1729 MODULE_ALIAS("snd-hda-codec-id:10de8001"); 1730 MODULE_ALIAS("snd-hda-codec-id:17e80047"); 1731 MODULE_ALIAS("snd-hda-codec-id:80860054"); 1732 MODULE_ALIAS("snd-hda-codec-id:80862801"); 1733 MODULE_ALIAS("snd-hda-codec-id:80862802"); 1734 MODULE_ALIAS("snd-hda-codec-id:80862803"); 1735 MODULE_ALIAS("snd-hda-codec-id:80862804"); 1736 MODULE_ALIAS("snd-hda-codec-id:80862805"); 1737 MODULE_ALIAS("snd-hda-codec-id:80862806"); 1738 MODULE_ALIAS("snd-hda-codec-id:808629fb"); 1739 1740 MODULE_LICENSE("GPL"); 1741 MODULE_DESCRIPTION("HDMI HD-audio codec"); 1742 MODULE_ALIAS("snd-hda-codec-intelhdmi"); 1743 MODULE_ALIAS("snd-hda-codec-nvhdmi"); 1744 MODULE_ALIAS("snd-hda-codec-atihdmi"); 1745 1746 static struct hda_codec_preset_list intel_list = { 1747 .preset = snd_hda_preset_hdmi, 1748 .owner = THIS_MODULE, 1749 }; 1750 1751 static int __init patch_hdmi_init(void) 1752 { 1753 return snd_hda_add_codec_preset(&intel_list); 1754 } 1755 1756 static void __exit patch_hdmi_exit(void) 1757 { 1758 snd_hda_delete_codec_preset(&intel_list); 1759 } 1760 1761 module_init(patch_hdmi_init) 1762 module_exit(patch_hdmi_exit) 1763