1 /* 2 * 3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs 4 * 5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. 6 * Copyright (c) 2006 ATI Technologies Inc. 7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved. 8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com> 9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> 10 * 11 * Authors: 12 * Wu Fengguang <wfg@linux.intel.com> 13 * 14 * Maintained by: 15 * Wu Fengguang <wfg@linux.intel.com> 16 * 17 * This program is free software; you can redistribute it and/or modify it 18 * under the terms of the GNU General Public License as published by the Free 19 * Software Foundation; either version 2 of the License, or (at your option) 20 * any later version. 21 * 22 * This program is distributed in the hope that it will be useful, but 23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 25 * for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software Foundation, 29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 30 */ 31 32 #include <linux/init.h> 33 #include <linux/delay.h> 34 #include <linux/slab.h> 35 #include <linux/module.h> 36 #include <sound/core.h> 37 #include <sound/jack.h> 38 #include <sound/asoundef.h> 39 #include <sound/tlv.h> 40 #include <sound/hdaudio.h> 41 #include <sound/hda_i915.h> 42 #include <sound/hda_chmap.h> 43 #include "hda_codec.h" 44 #include "hda_local.h" 45 #include "hda_jack.h" 46 47 static bool static_hdmi_pcm; 48 module_param(static_hdmi_pcm, bool, 0644); 49 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); 50 51 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807) 52 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808) 53 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809) 54 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a) 55 #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b) 56 #define is_geminilake(codec) (((codec)->core.vendor_id == 0x8086280d) || \ 57 ((codec)->core.vendor_id == 0x80862800)) 58 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \ 59 || is_skylake(codec) || is_broxton(codec) \ 60 || is_kabylake(codec)) || is_geminilake(codec) 61 62 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882) 63 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883) 64 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec)) 65 66 struct hdmi_spec_per_cvt { 67 hda_nid_t cvt_nid; 68 int assigned; 69 unsigned int channels_min; 70 unsigned int channels_max; 71 u32 rates; 72 u64 formats; 73 unsigned int maxbps; 74 }; 75 76 /* max. connections to a widget */ 77 #define HDA_MAX_CONNECTIONS 32 78 79 struct hdmi_spec_per_pin { 80 hda_nid_t pin_nid; 81 int dev_id; 82 /* pin idx, different device entries on the same pin use the same idx */ 83 int pin_nid_idx; 84 int num_mux_nids; 85 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; 86 int mux_idx; 87 hda_nid_t cvt_nid; 88 89 struct hda_codec *codec; 90 struct hdmi_eld sink_eld; 91 struct mutex lock; 92 struct delayed_work work; 93 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ 94 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ 95 int repoll_count; 96 bool setup; /* the stream has been set up by prepare callback */ 97 int channels; /* current number of channels */ 98 bool non_pcm; 99 bool chmap_set; /* channel-map override by ALSA API? */ 100 unsigned char chmap[8]; /* ALSA API channel-map */ 101 #ifdef CONFIG_SND_PROC_FS 102 struct snd_info_entry *proc_entry; 103 #endif 104 }; 105 106 /* operations used by generic code that can be overridden by patches */ 107 struct hdmi_ops { 108 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, 109 unsigned char *buf, int *eld_size); 110 111 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, 112 int ca, int active_channels, int conn_type); 113 114 /* enable/disable HBR (HD passthrough) */ 115 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr); 116 117 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, 118 hda_nid_t pin_nid, u32 stream_tag, int format); 119 120 void (*pin_cvt_fixup)(struct hda_codec *codec, 121 struct hdmi_spec_per_pin *per_pin, 122 hda_nid_t cvt_nid); 123 }; 124 125 struct hdmi_pcm { 126 struct hda_pcm *pcm; 127 struct snd_jack *jack; 128 struct snd_kcontrol *eld_ctl; 129 }; 130 131 struct hdmi_spec { 132 int num_cvts; 133 struct snd_array cvts; /* struct hdmi_spec_per_cvt */ 134 hda_nid_t cvt_nids[4]; /* only for haswell fix */ 135 136 /* 137 * num_pins is the number of virtual pins 138 * for example, there are 3 pins, and each pin 139 * has 4 device entries, then the num_pins is 12 140 */ 141 int num_pins; 142 /* 143 * num_nids is the number of real pins 144 * In the above example, num_nids is 3 145 */ 146 int num_nids; 147 /* 148 * dev_num is the number of device entries 149 * on each pin. 150 * In the above example, dev_num is 4 151 */ 152 int dev_num; 153 struct snd_array pins; /* struct hdmi_spec_per_pin */ 154 struct hdmi_pcm pcm_rec[16]; 155 struct mutex pcm_lock; 156 /* pcm_bitmap means which pcms have been assigned to pins*/ 157 unsigned long pcm_bitmap; 158 int pcm_used; /* counter of pcm_rec[] */ 159 /* bitmap shows whether the pcm is opened in user space 160 * bit 0 means the first playback PCM (PCM3); 161 * bit 1 means the second playback PCM, and so on. 162 */ 163 unsigned long pcm_in_use; 164 165 struct hdmi_eld temp_eld; 166 struct hdmi_ops ops; 167 168 bool dyn_pin_out; 169 bool dyn_pcm_assign; 170 /* 171 * Non-generic VIA/NVIDIA specific 172 */ 173 struct hda_multi_out multiout; 174 struct hda_pcm_stream pcm_playback; 175 176 /* i915/powerwell (Haswell+/Valleyview+) specific */ 177 bool use_acomp_notifier; /* use i915 eld_notify callback for hotplug */ 178 struct i915_audio_component_audio_ops i915_audio_ops; 179 180 struct hdac_chmap chmap; 181 hda_nid_t vendor_nid; 182 }; 183 184 #ifdef CONFIG_SND_HDA_I915 185 static inline bool codec_has_acomp(struct hda_codec *codec) 186 { 187 struct hdmi_spec *spec = codec->spec; 188 return spec->use_acomp_notifier; 189 } 190 #else 191 #define codec_has_acomp(codec) false 192 #endif 193 194 struct hdmi_audio_infoframe { 195 u8 type; /* 0x84 */ 196 u8 ver; /* 0x01 */ 197 u8 len; /* 0x0a */ 198 199 u8 checksum; 200 201 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ 202 u8 SS01_SF24; 203 u8 CXT04; 204 u8 CA; 205 u8 LFEPBL01_LSV36_DM_INH7; 206 }; 207 208 struct dp_audio_infoframe { 209 u8 type; /* 0x84 */ 210 u8 len; /* 0x1b */ 211 u8 ver; /* 0x11 << 2 */ 212 213 u8 CC02_CT47; /* match with HDMI infoframe from this on */ 214 u8 SS01_SF24; 215 u8 CXT04; 216 u8 CA; 217 u8 LFEPBL01_LSV36_DM_INH7; 218 }; 219 220 union audio_infoframe { 221 struct hdmi_audio_infoframe hdmi; 222 struct dp_audio_infoframe dp; 223 u8 bytes[0]; 224 }; 225 226 /* 227 * HDMI routines 228 */ 229 230 #define get_pin(spec, idx) \ 231 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) 232 #define get_cvt(spec, idx) \ 233 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) 234 /* obtain hdmi_pcm object assigned to idx */ 235 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) 236 /* obtain hda_pcm object assigned to idx */ 237 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) 238 239 static int pin_id_to_pin_index(struct hda_codec *codec, 240 hda_nid_t pin_nid, int dev_id) 241 { 242 struct hdmi_spec *spec = codec->spec; 243 int pin_idx; 244 struct hdmi_spec_per_pin *per_pin; 245 246 /* 247 * (dev_id == -1) means it is NON-MST pin 248 * return the first virtual pin on this port 249 */ 250 if (dev_id == -1) 251 dev_id = 0; 252 253 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 254 per_pin = get_pin(spec, pin_idx); 255 if ((per_pin->pin_nid == pin_nid) && 256 (per_pin->dev_id == dev_id)) 257 return pin_idx; 258 } 259 260 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid); 261 return -EINVAL; 262 } 263 264 static int hinfo_to_pcm_index(struct hda_codec *codec, 265 struct hda_pcm_stream *hinfo) 266 { 267 struct hdmi_spec *spec = codec->spec; 268 int pcm_idx; 269 270 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) 271 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) 272 return pcm_idx; 273 274 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo); 275 return -EINVAL; 276 } 277 278 static int hinfo_to_pin_index(struct hda_codec *codec, 279 struct hda_pcm_stream *hinfo) 280 { 281 struct hdmi_spec *spec = codec->spec; 282 struct hdmi_spec_per_pin *per_pin; 283 int pin_idx; 284 285 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 286 per_pin = get_pin(spec, pin_idx); 287 if (per_pin->pcm && 288 per_pin->pcm->pcm->stream == hinfo) 289 return pin_idx; 290 } 291 292 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo); 293 return -EINVAL; 294 } 295 296 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, 297 int pcm_idx) 298 { 299 int i; 300 struct hdmi_spec_per_pin *per_pin; 301 302 for (i = 0; i < spec->num_pins; i++) { 303 per_pin = get_pin(spec, i); 304 if (per_pin->pcm_idx == pcm_idx) 305 return per_pin; 306 } 307 return NULL; 308 } 309 310 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) 311 { 312 struct hdmi_spec *spec = codec->spec; 313 int cvt_idx; 314 315 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) 316 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) 317 return cvt_idx; 318 319 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid); 320 return -EINVAL; 321 } 322 323 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, 324 struct snd_ctl_elem_info *uinfo) 325 { 326 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 327 struct hdmi_spec *spec = codec->spec; 328 struct hdmi_spec_per_pin *per_pin; 329 struct hdmi_eld *eld; 330 int pcm_idx; 331 332 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 333 334 pcm_idx = kcontrol->private_value; 335 mutex_lock(&spec->pcm_lock); 336 per_pin = pcm_idx_to_pin(spec, pcm_idx); 337 if (!per_pin) { 338 /* no pin is bound to the pcm */ 339 uinfo->count = 0; 340 mutex_unlock(&spec->pcm_lock); 341 return 0; 342 } 343 eld = &per_pin->sink_eld; 344 uinfo->count = eld->eld_valid ? eld->eld_size : 0; 345 mutex_unlock(&spec->pcm_lock); 346 347 return 0; 348 } 349 350 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, 351 struct snd_ctl_elem_value *ucontrol) 352 { 353 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 354 struct hdmi_spec *spec = codec->spec; 355 struct hdmi_spec_per_pin *per_pin; 356 struct hdmi_eld *eld; 357 int pcm_idx; 358 359 pcm_idx = kcontrol->private_value; 360 mutex_lock(&spec->pcm_lock); 361 per_pin = pcm_idx_to_pin(spec, pcm_idx); 362 if (!per_pin) { 363 /* no pin is bound to the pcm */ 364 memset(ucontrol->value.bytes.data, 0, 365 ARRAY_SIZE(ucontrol->value.bytes.data)); 366 mutex_unlock(&spec->pcm_lock); 367 return 0; 368 } 369 eld = &per_pin->sink_eld; 370 371 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || 372 eld->eld_size > ELD_MAX_SIZE) { 373 mutex_unlock(&spec->pcm_lock); 374 snd_BUG(); 375 return -EINVAL; 376 } 377 378 memset(ucontrol->value.bytes.data, 0, 379 ARRAY_SIZE(ucontrol->value.bytes.data)); 380 if (eld->eld_valid) 381 memcpy(ucontrol->value.bytes.data, eld->eld_buffer, 382 eld->eld_size); 383 mutex_unlock(&spec->pcm_lock); 384 385 return 0; 386 } 387 388 static const struct snd_kcontrol_new eld_bytes_ctl = { 389 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, 390 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 391 .name = "ELD", 392 .info = hdmi_eld_ctl_info, 393 .get = hdmi_eld_ctl_get, 394 }; 395 396 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, 397 int device) 398 { 399 struct snd_kcontrol *kctl; 400 struct hdmi_spec *spec = codec->spec; 401 int err; 402 403 kctl = snd_ctl_new1(&eld_bytes_ctl, codec); 404 if (!kctl) 405 return -ENOMEM; 406 kctl->private_value = pcm_idx; 407 kctl->id.device = device; 408 409 /* no pin nid is associated with the kctl now 410 * tbd: associate pin nid to eld ctl later 411 */ 412 err = snd_hda_ctl_add(codec, 0, kctl); 413 if (err < 0) 414 return err; 415 416 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; 417 return 0; 418 } 419 420 #ifdef BE_PARANOID 421 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 422 int *packet_index, int *byte_index) 423 { 424 int val; 425 426 val = snd_hda_codec_read(codec, pin_nid, 0, 427 AC_VERB_GET_HDMI_DIP_INDEX, 0); 428 429 *packet_index = val >> 5; 430 *byte_index = val & 0x1f; 431 } 432 #endif 433 434 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 435 int packet_index, int byte_index) 436 { 437 int val; 438 439 val = (packet_index << 5) | (byte_index & 0x1f); 440 441 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); 442 } 443 444 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, 445 unsigned char val) 446 { 447 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); 448 } 449 450 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) 451 { 452 struct hdmi_spec *spec = codec->spec; 453 int pin_out; 454 455 /* Unmute */ 456 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 457 snd_hda_codec_write(codec, pin_nid, 0, 458 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); 459 460 if (spec->dyn_pin_out) 461 /* Disable pin out until stream is active */ 462 pin_out = 0; 463 else 464 /* Enable pin out: some machines with GM965 gets broken output 465 * when the pin is disabled or changed while using with HDMI 466 */ 467 pin_out = PIN_OUT; 468 469 snd_hda_codec_write(codec, pin_nid, 0, 470 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); 471 } 472 473 /* 474 * ELD proc files 475 */ 476 477 #ifdef CONFIG_SND_PROC_FS 478 static void print_eld_info(struct snd_info_entry *entry, 479 struct snd_info_buffer *buffer) 480 { 481 struct hdmi_spec_per_pin *per_pin = entry->private_data; 482 483 mutex_lock(&per_pin->lock); 484 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer); 485 mutex_unlock(&per_pin->lock); 486 } 487 488 static void write_eld_info(struct snd_info_entry *entry, 489 struct snd_info_buffer *buffer) 490 { 491 struct hdmi_spec_per_pin *per_pin = entry->private_data; 492 493 mutex_lock(&per_pin->lock); 494 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); 495 mutex_unlock(&per_pin->lock); 496 } 497 498 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) 499 { 500 char name[32]; 501 struct hda_codec *codec = per_pin->codec; 502 struct snd_info_entry *entry; 503 int err; 504 505 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); 506 err = snd_card_proc_new(codec->card, name, &entry); 507 if (err < 0) 508 return err; 509 510 snd_info_set_text_ops(entry, per_pin, print_eld_info); 511 entry->c.text.write = write_eld_info; 512 entry->mode |= S_IWUSR; 513 per_pin->proc_entry = entry; 514 515 return 0; 516 } 517 518 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 519 { 520 if (!per_pin->codec->bus->shutdown) { 521 snd_info_free_entry(per_pin->proc_entry); 522 per_pin->proc_entry = NULL; 523 } 524 } 525 #else 526 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, 527 int index) 528 { 529 return 0; 530 } 531 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 532 { 533 } 534 #endif 535 536 /* 537 * Audio InfoFrame routines 538 */ 539 540 /* 541 * Enable Audio InfoFrame Transmission 542 */ 543 static void hdmi_start_infoframe_trans(struct hda_codec *codec, 544 hda_nid_t pin_nid) 545 { 546 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 547 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 548 AC_DIPXMIT_BEST); 549 } 550 551 /* 552 * Disable Audio InfoFrame Transmission 553 */ 554 static void hdmi_stop_infoframe_trans(struct hda_codec *codec, 555 hda_nid_t pin_nid) 556 { 557 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 558 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 559 AC_DIPXMIT_DISABLE); 560 } 561 562 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) 563 { 564 #ifdef CONFIG_SND_DEBUG_VERBOSE 565 int i; 566 int size; 567 568 size = snd_hdmi_get_eld_size(codec, pin_nid); 569 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); 570 571 for (i = 0; i < 8; i++) { 572 size = snd_hda_codec_read(codec, pin_nid, 0, 573 AC_VERB_GET_HDMI_DIP_SIZE, i); 574 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); 575 } 576 #endif 577 } 578 579 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) 580 { 581 #ifdef BE_PARANOID 582 int i, j; 583 int size; 584 int pi, bi; 585 for (i = 0; i < 8; i++) { 586 size = snd_hda_codec_read(codec, pin_nid, 0, 587 AC_VERB_GET_HDMI_DIP_SIZE, i); 588 if (size == 0) 589 continue; 590 591 hdmi_set_dip_index(codec, pin_nid, i, 0x0); 592 for (j = 1; j < 1000; j++) { 593 hdmi_write_dip_byte(codec, pin_nid, 0x0); 594 hdmi_get_dip_index(codec, pin_nid, &pi, &bi); 595 if (pi != i) 596 codec_dbg(codec, "dip index %d: %d != %d\n", 597 bi, pi, i); 598 if (bi == 0) /* byte index wrapped around */ 599 break; 600 } 601 codec_dbg(codec, 602 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", 603 i, size, j); 604 } 605 #endif 606 } 607 608 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) 609 { 610 u8 *bytes = (u8 *)hdmi_ai; 611 u8 sum = 0; 612 int i; 613 614 hdmi_ai->checksum = 0; 615 616 for (i = 0; i < sizeof(*hdmi_ai); i++) 617 sum += bytes[i]; 618 619 hdmi_ai->checksum = -sum; 620 } 621 622 static void hdmi_fill_audio_infoframe(struct hda_codec *codec, 623 hda_nid_t pin_nid, 624 u8 *dip, int size) 625 { 626 int i; 627 628 hdmi_debug_dip_size(codec, pin_nid); 629 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ 630 631 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 632 for (i = 0; i < size; i++) 633 hdmi_write_dip_byte(codec, pin_nid, dip[i]); 634 } 635 636 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, 637 u8 *dip, int size) 638 { 639 u8 val; 640 int i; 641 642 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) 643 != AC_DIPXMIT_BEST) 644 return false; 645 646 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 647 for (i = 0; i < size; i++) { 648 val = snd_hda_codec_read(codec, pin_nid, 0, 649 AC_VERB_GET_HDMI_DIP_DATA, 0); 650 if (val != dip[i]) 651 return false; 652 } 653 654 return true; 655 } 656 657 static void hdmi_pin_setup_infoframe(struct hda_codec *codec, 658 hda_nid_t pin_nid, 659 int ca, int active_channels, 660 int conn_type) 661 { 662 union audio_infoframe ai; 663 664 memset(&ai, 0, sizeof(ai)); 665 if (conn_type == 0) { /* HDMI */ 666 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; 667 668 hdmi_ai->type = 0x84; 669 hdmi_ai->ver = 0x01; 670 hdmi_ai->len = 0x0a; 671 hdmi_ai->CC02_CT47 = active_channels - 1; 672 hdmi_ai->CA = ca; 673 hdmi_checksum_audio_infoframe(hdmi_ai); 674 } else if (conn_type == 1) { /* DisplayPort */ 675 struct dp_audio_infoframe *dp_ai = &ai.dp; 676 677 dp_ai->type = 0x84; 678 dp_ai->len = 0x1b; 679 dp_ai->ver = 0x11 << 2; 680 dp_ai->CC02_CT47 = active_channels - 1; 681 dp_ai->CA = ca; 682 } else { 683 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n", 684 pin_nid); 685 return; 686 } 687 688 /* 689 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or 690 * sizeof(*dp_ai) to avoid partial match/update problems when 691 * the user switches between HDMI/DP monitors. 692 */ 693 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, 694 sizeof(ai))) { 695 codec_dbg(codec, 696 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n", 697 pin_nid, 698 active_channels, ca); 699 hdmi_stop_infoframe_trans(codec, pin_nid); 700 hdmi_fill_audio_infoframe(codec, pin_nid, 701 ai.bytes, sizeof(ai)); 702 hdmi_start_infoframe_trans(codec, pin_nid); 703 } 704 } 705 706 static void hdmi_setup_audio_infoframe(struct hda_codec *codec, 707 struct hdmi_spec_per_pin *per_pin, 708 bool non_pcm) 709 { 710 struct hdmi_spec *spec = codec->spec; 711 struct hdac_chmap *chmap = &spec->chmap; 712 hda_nid_t pin_nid = per_pin->pin_nid; 713 int channels = per_pin->channels; 714 int active_channels; 715 struct hdmi_eld *eld; 716 int ca; 717 718 if (!channels) 719 return; 720 721 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ 722 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 723 snd_hda_codec_write(codec, pin_nid, 0, 724 AC_VERB_SET_AMP_GAIN_MUTE, 725 AMP_OUT_UNMUTE); 726 727 eld = &per_pin->sink_eld; 728 729 ca = snd_hdac_channel_allocation(&codec->core, 730 eld->info.spk_alloc, channels, 731 per_pin->chmap_set, non_pcm, per_pin->chmap); 732 733 active_channels = snd_hdac_get_active_channels(ca); 734 735 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, 736 active_channels); 737 738 /* 739 * always configure channel mapping, it may have been changed by the 740 * user in the meantime 741 */ 742 snd_hdac_setup_channel_mapping(&spec->chmap, 743 pin_nid, non_pcm, ca, channels, 744 per_pin->chmap, per_pin->chmap_set); 745 746 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels, 747 eld->info.conn_type); 748 749 per_pin->non_pcm = non_pcm; 750 } 751 752 /* 753 * Unsolicited events 754 */ 755 756 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); 757 758 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, 759 int dev_id) 760 { 761 struct hdmi_spec *spec = codec->spec; 762 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); 763 764 if (pin_idx < 0) 765 return; 766 if (hdmi_present_sense(get_pin(spec, pin_idx), 1)) 767 snd_hda_jack_report_sync(codec); 768 } 769 770 static void jack_callback(struct hda_codec *codec, 771 struct hda_jack_callback *jack) 772 { 773 /* hda_jack don't support DP MST */ 774 check_presence_and_report(codec, jack->nid, 0); 775 } 776 777 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res) 778 { 779 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 780 struct hda_jack_tbl *jack; 781 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 782 783 /* 784 * assume DP MST uses dyn_pcm_assign and acomp and 785 * never comes here 786 * if DP MST supports unsol event, below code need 787 * consider dev_entry 788 */ 789 jack = snd_hda_jack_tbl_get_from_tag(codec, tag); 790 if (!jack) 791 return; 792 jack->jack_dirty = 1; 793 794 codec_dbg(codec, 795 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", 796 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA), 797 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); 798 799 /* hda_jack don't support DP MST */ 800 check_presence_and_report(codec, jack->nid, 0); 801 } 802 803 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) 804 { 805 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 806 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 807 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); 808 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); 809 810 codec_info(codec, 811 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", 812 codec->addr, 813 tag, 814 subtag, 815 cp_state, 816 cp_ready); 817 818 /* TODO */ 819 if (cp_state) 820 ; 821 if (cp_ready) 822 ; 823 } 824 825 826 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) 827 { 828 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 829 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 830 831 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) { 832 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); 833 return; 834 } 835 836 if (subtag == 0) 837 hdmi_intrinsic_event(codec, res); 838 else 839 hdmi_non_intrinsic_event(codec, res); 840 } 841 842 static void haswell_verify_D0(struct hda_codec *codec, 843 hda_nid_t cvt_nid, hda_nid_t nid) 844 { 845 int pwr; 846 847 /* For Haswell, the converter 1/2 may keep in D3 state after bootup, 848 * thus pins could only choose converter 0 for use. Make sure the 849 * converters are in correct power state */ 850 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) 851 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); 852 853 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { 854 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, 855 AC_PWRST_D0); 856 msleep(40); 857 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); 858 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; 859 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr); 860 } 861 } 862 863 /* 864 * Callbacks 865 */ 866 867 /* HBR should be Non-PCM, 8 channels */ 868 #define is_hbr_format(format) \ 869 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) 870 871 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 872 bool hbr) 873 { 874 int pinctl, new_pinctl; 875 876 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { 877 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 878 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 879 880 if (pinctl < 0) 881 return hbr ? -EINVAL : 0; 882 883 new_pinctl = pinctl & ~AC_PINCTL_EPT; 884 if (hbr) 885 new_pinctl |= AC_PINCTL_EPT_HBR; 886 else 887 new_pinctl |= AC_PINCTL_EPT_NATIVE; 888 889 codec_dbg(codec, 890 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", 891 pin_nid, 892 pinctl == new_pinctl ? "" : "new-", 893 new_pinctl); 894 895 if (pinctl != new_pinctl) 896 snd_hda_codec_write(codec, pin_nid, 0, 897 AC_VERB_SET_PIN_WIDGET_CONTROL, 898 new_pinctl); 899 } else if (hbr) 900 return -EINVAL; 901 902 return 0; 903 } 904 905 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 906 hda_nid_t pin_nid, u32 stream_tag, int format) 907 { 908 struct hdmi_spec *spec = codec->spec; 909 int err; 910 911 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format)); 912 913 if (err) { 914 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); 915 return err; 916 } 917 918 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); 919 return 0; 920 } 921 922 /* Try to find an available converter 923 * If pin_idx is less then zero, just try to find an available converter. 924 * Otherwise, try to find an available converter and get the cvt mux index 925 * of the pin. 926 */ 927 static int hdmi_choose_cvt(struct hda_codec *codec, 928 int pin_idx, int *cvt_id) 929 { 930 struct hdmi_spec *spec = codec->spec; 931 struct hdmi_spec_per_pin *per_pin; 932 struct hdmi_spec_per_cvt *per_cvt = NULL; 933 int cvt_idx, mux_idx = 0; 934 935 /* pin_idx < 0 means no pin will be bound to the converter */ 936 if (pin_idx < 0) 937 per_pin = NULL; 938 else 939 per_pin = get_pin(spec, pin_idx); 940 941 /* Dynamically assign converter to stream */ 942 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 943 per_cvt = get_cvt(spec, cvt_idx); 944 945 /* Must not already be assigned */ 946 if (per_cvt->assigned) 947 continue; 948 if (per_pin == NULL) 949 break; 950 /* Must be in pin's mux's list of converters */ 951 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 952 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) 953 break; 954 /* Not in mux list */ 955 if (mux_idx == per_pin->num_mux_nids) 956 continue; 957 break; 958 } 959 960 /* No free converters */ 961 if (cvt_idx == spec->num_cvts) 962 return -EBUSY; 963 964 if (per_pin != NULL) 965 per_pin->mux_idx = mux_idx; 966 967 if (cvt_id) 968 *cvt_id = cvt_idx; 969 970 return 0; 971 } 972 973 /* Assure the pin select the right convetor */ 974 static void intel_verify_pin_cvt_connect(struct hda_codec *codec, 975 struct hdmi_spec_per_pin *per_pin) 976 { 977 hda_nid_t pin_nid = per_pin->pin_nid; 978 int mux_idx, curr; 979 980 mux_idx = per_pin->mux_idx; 981 curr = snd_hda_codec_read(codec, pin_nid, 0, 982 AC_VERB_GET_CONNECT_SEL, 0); 983 if (curr != mux_idx) 984 snd_hda_codec_write_cache(codec, pin_nid, 0, 985 AC_VERB_SET_CONNECT_SEL, 986 mux_idx); 987 } 988 989 /* get the mux index for the converter of the pins 990 * converter's mux index is the same for all pins on Intel platform 991 */ 992 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, 993 hda_nid_t cvt_nid) 994 { 995 int i; 996 997 for (i = 0; i < spec->num_cvts; i++) 998 if (spec->cvt_nids[i] == cvt_nid) 999 return i; 1000 return -EINVAL; 1001 } 1002 1003 /* Intel HDMI workaround to fix audio routing issue: 1004 * For some Intel display codecs, pins share the same connection list. 1005 * So a conveter can be selected by multiple pins and playback on any of these 1006 * pins will generate sound on the external display, because audio flows from 1007 * the same converter to the display pipeline. Also muting one pin may make 1008 * other pins have no sound output. 1009 * So this function assures that an assigned converter for a pin is not selected 1010 * by any other pins. 1011 */ 1012 static void intel_not_share_assigned_cvt(struct hda_codec *codec, 1013 hda_nid_t pin_nid, 1014 int dev_id, int mux_idx) 1015 { 1016 struct hdmi_spec *spec = codec->spec; 1017 hda_nid_t nid; 1018 int cvt_idx, curr; 1019 struct hdmi_spec_per_cvt *per_cvt; 1020 struct hdmi_spec_per_pin *per_pin; 1021 int pin_idx; 1022 1023 /* configure the pins connections */ 1024 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 1025 int dev_id_saved; 1026 int dev_num; 1027 1028 per_pin = get_pin(spec, pin_idx); 1029 /* 1030 * pin not connected to monitor 1031 * no need to operate on it 1032 */ 1033 if (!per_pin->pcm) 1034 continue; 1035 1036 if ((per_pin->pin_nid == pin_nid) && 1037 (per_pin->dev_id == dev_id)) 1038 continue; 1039 1040 /* 1041 * if per_pin->dev_id >= dev_num, 1042 * snd_hda_get_dev_select() will fail, 1043 * and the following operation is unpredictable. 1044 * So skip this situation. 1045 */ 1046 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; 1047 if (per_pin->dev_id >= dev_num) 1048 continue; 1049 1050 nid = per_pin->pin_nid; 1051 1052 /* 1053 * Calling this function should not impact 1054 * on the device entry selection 1055 * So let's save the dev id for each pin, 1056 * and restore it when return 1057 */ 1058 dev_id_saved = snd_hda_get_dev_select(codec, nid); 1059 snd_hda_set_dev_select(codec, nid, per_pin->dev_id); 1060 curr = snd_hda_codec_read(codec, nid, 0, 1061 AC_VERB_GET_CONNECT_SEL, 0); 1062 if (curr != mux_idx) { 1063 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1064 continue; 1065 } 1066 1067 1068 /* choose an unassigned converter. The conveters in the 1069 * connection list are in the same order as in the codec. 1070 */ 1071 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1072 per_cvt = get_cvt(spec, cvt_idx); 1073 if (!per_cvt->assigned) { 1074 codec_dbg(codec, 1075 "choose cvt %d for pin nid %d\n", 1076 cvt_idx, nid); 1077 snd_hda_codec_write_cache(codec, nid, 0, 1078 AC_VERB_SET_CONNECT_SEL, 1079 cvt_idx); 1080 break; 1081 } 1082 } 1083 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1084 } 1085 } 1086 1087 /* A wrapper of intel_not_share_asigned_cvt() */ 1088 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, 1089 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) 1090 { 1091 int mux_idx; 1092 struct hdmi_spec *spec = codec->spec; 1093 1094 /* On Intel platform, the mapping of converter nid to 1095 * mux index of the pins are always the same. 1096 * The pin nid may be 0, this means all pins will not 1097 * share the converter. 1098 */ 1099 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); 1100 if (mux_idx >= 0) 1101 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); 1102 } 1103 1104 /* skeleton caller of pin_cvt_fixup ops */ 1105 static void pin_cvt_fixup(struct hda_codec *codec, 1106 struct hdmi_spec_per_pin *per_pin, 1107 hda_nid_t cvt_nid) 1108 { 1109 struct hdmi_spec *spec = codec->spec; 1110 1111 if (spec->ops.pin_cvt_fixup) 1112 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); 1113 } 1114 1115 /* called in hdmi_pcm_open when no pin is assigned to the PCM 1116 * in dyn_pcm_assign mode. 1117 */ 1118 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, 1119 struct hda_codec *codec, 1120 struct snd_pcm_substream *substream) 1121 { 1122 struct hdmi_spec *spec = codec->spec; 1123 struct snd_pcm_runtime *runtime = substream->runtime; 1124 int cvt_idx, pcm_idx; 1125 struct hdmi_spec_per_cvt *per_cvt = NULL; 1126 int err; 1127 1128 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1129 if (pcm_idx < 0) 1130 return -EINVAL; 1131 1132 err = hdmi_choose_cvt(codec, -1, &cvt_idx); 1133 if (err) 1134 return err; 1135 1136 per_cvt = get_cvt(spec, cvt_idx); 1137 per_cvt->assigned = 1; 1138 hinfo->nid = per_cvt->cvt_nid; 1139 1140 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); 1141 1142 set_bit(pcm_idx, &spec->pcm_in_use); 1143 /* todo: setup spdif ctls assign */ 1144 1145 /* Initially set the converter's capabilities */ 1146 hinfo->channels_min = per_cvt->channels_min; 1147 hinfo->channels_max = per_cvt->channels_max; 1148 hinfo->rates = per_cvt->rates; 1149 hinfo->formats = per_cvt->formats; 1150 hinfo->maxbps = per_cvt->maxbps; 1151 1152 /* Store the updated parameters */ 1153 runtime->hw.channels_min = hinfo->channels_min; 1154 runtime->hw.channels_max = hinfo->channels_max; 1155 runtime->hw.formats = hinfo->formats; 1156 runtime->hw.rates = hinfo->rates; 1157 1158 snd_pcm_hw_constraint_step(substream->runtime, 0, 1159 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1160 return 0; 1161 } 1162 1163 /* 1164 * HDA PCM callbacks 1165 */ 1166 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, 1167 struct hda_codec *codec, 1168 struct snd_pcm_substream *substream) 1169 { 1170 struct hdmi_spec *spec = codec->spec; 1171 struct snd_pcm_runtime *runtime = substream->runtime; 1172 int pin_idx, cvt_idx, pcm_idx; 1173 struct hdmi_spec_per_pin *per_pin; 1174 struct hdmi_eld *eld; 1175 struct hdmi_spec_per_cvt *per_cvt = NULL; 1176 int err; 1177 1178 /* Validate hinfo */ 1179 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1180 if (pcm_idx < 0) 1181 return -EINVAL; 1182 1183 mutex_lock(&spec->pcm_lock); 1184 pin_idx = hinfo_to_pin_index(codec, hinfo); 1185 if (!spec->dyn_pcm_assign) { 1186 if (snd_BUG_ON(pin_idx < 0)) { 1187 mutex_unlock(&spec->pcm_lock); 1188 return -EINVAL; 1189 } 1190 } else { 1191 /* no pin is assigned to the PCM 1192 * PA need pcm open successfully when probe 1193 */ 1194 if (pin_idx < 0) { 1195 err = hdmi_pcm_open_no_pin(hinfo, codec, substream); 1196 mutex_unlock(&spec->pcm_lock); 1197 return err; 1198 } 1199 } 1200 1201 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx); 1202 if (err < 0) { 1203 mutex_unlock(&spec->pcm_lock); 1204 return err; 1205 } 1206 1207 per_cvt = get_cvt(spec, cvt_idx); 1208 /* Claim converter */ 1209 per_cvt->assigned = 1; 1210 1211 set_bit(pcm_idx, &spec->pcm_in_use); 1212 per_pin = get_pin(spec, pin_idx); 1213 per_pin->cvt_nid = per_cvt->cvt_nid; 1214 hinfo->nid = per_cvt->cvt_nid; 1215 1216 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1217 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1218 AC_VERB_SET_CONNECT_SEL, 1219 per_pin->mux_idx); 1220 1221 /* configure unused pins to choose other converters */ 1222 pin_cvt_fixup(codec, per_pin, 0); 1223 1224 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); 1225 1226 /* Initially set the converter's capabilities */ 1227 hinfo->channels_min = per_cvt->channels_min; 1228 hinfo->channels_max = per_cvt->channels_max; 1229 hinfo->rates = per_cvt->rates; 1230 hinfo->formats = per_cvt->formats; 1231 hinfo->maxbps = per_cvt->maxbps; 1232 1233 eld = &per_pin->sink_eld; 1234 /* Restrict capabilities by ELD if this isn't disabled */ 1235 if (!static_hdmi_pcm && eld->eld_valid) { 1236 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); 1237 if (hinfo->channels_min > hinfo->channels_max || 1238 !hinfo->rates || !hinfo->formats) { 1239 per_cvt->assigned = 0; 1240 hinfo->nid = 0; 1241 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1242 mutex_unlock(&spec->pcm_lock); 1243 return -ENODEV; 1244 } 1245 } 1246 1247 mutex_unlock(&spec->pcm_lock); 1248 /* Store the updated parameters */ 1249 runtime->hw.channels_min = hinfo->channels_min; 1250 runtime->hw.channels_max = hinfo->channels_max; 1251 runtime->hw.formats = hinfo->formats; 1252 runtime->hw.rates = hinfo->rates; 1253 1254 snd_pcm_hw_constraint_step(substream->runtime, 0, 1255 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1256 return 0; 1257 } 1258 1259 /* 1260 * HDA/HDMI auto parsing 1261 */ 1262 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) 1263 { 1264 struct hdmi_spec *spec = codec->spec; 1265 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1266 hda_nid_t pin_nid = per_pin->pin_nid; 1267 1268 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { 1269 codec_warn(codec, 1270 "HDMI: pin %d wcaps %#x does not support connection list\n", 1271 pin_nid, get_wcaps(codec, pin_nid)); 1272 return -EINVAL; 1273 } 1274 1275 /* all the device entries on the same pin have the same conn list */ 1276 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid, 1277 per_pin->mux_nids, 1278 HDA_MAX_CONNECTIONS); 1279 1280 return 0; 1281 } 1282 1283 static int hdmi_find_pcm_slot(struct hdmi_spec *spec, 1284 struct hdmi_spec_per_pin *per_pin) 1285 { 1286 int i; 1287 1288 /* try the prefer PCM */ 1289 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap)) 1290 return per_pin->pin_nid_idx; 1291 1292 /* have a second try; check the "reserved area" over num_pins */ 1293 for (i = spec->num_nids; i < spec->pcm_used; i++) { 1294 if (!test_bit(i, &spec->pcm_bitmap)) 1295 return i; 1296 } 1297 1298 /* the last try; check the empty slots in pins */ 1299 for (i = 0; i < spec->num_nids; i++) { 1300 if (!test_bit(i, &spec->pcm_bitmap)) 1301 return i; 1302 } 1303 return -EBUSY; 1304 } 1305 1306 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, 1307 struct hdmi_spec_per_pin *per_pin) 1308 { 1309 int idx; 1310 1311 /* pcm already be attached to the pin */ 1312 if (per_pin->pcm) 1313 return; 1314 idx = hdmi_find_pcm_slot(spec, per_pin); 1315 if (idx == -EBUSY) 1316 return; 1317 per_pin->pcm_idx = idx; 1318 per_pin->pcm = get_hdmi_pcm(spec, idx); 1319 set_bit(idx, &spec->pcm_bitmap); 1320 } 1321 1322 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, 1323 struct hdmi_spec_per_pin *per_pin) 1324 { 1325 int idx; 1326 1327 /* pcm already be detached from the pin */ 1328 if (!per_pin->pcm) 1329 return; 1330 idx = per_pin->pcm_idx; 1331 per_pin->pcm_idx = -1; 1332 per_pin->pcm = NULL; 1333 if (idx >= 0 && idx < spec->pcm_used) 1334 clear_bit(idx, &spec->pcm_bitmap); 1335 } 1336 1337 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, 1338 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) 1339 { 1340 int mux_idx; 1341 1342 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1343 if (per_pin->mux_nids[mux_idx] == cvt_nid) 1344 break; 1345 return mux_idx; 1346 } 1347 1348 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); 1349 1350 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, 1351 struct hdmi_spec_per_pin *per_pin) 1352 { 1353 struct hda_codec *codec = per_pin->codec; 1354 struct hda_pcm *pcm; 1355 struct hda_pcm_stream *hinfo; 1356 struct snd_pcm_substream *substream; 1357 int mux_idx; 1358 bool non_pcm; 1359 1360 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1361 pcm = get_pcm_rec(spec, per_pin->pcm_idx); 1362 else 1363 return; 1364 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) 1365 return; 1366 1367 /* hdmi audio only uses playback and one substream */ 1368 hinfo = pcm->stream; 1369 substream = pcm->pcm->streams[0].substream; 1370 1371 per_pin->cvt_nid = hinfo->nid; 1372 1373 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); 1374 if (mux_idx < per_pin->num_mux_nids) { 1375 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1376 per_pin->dev_id); 1377 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1378 AC_VERB_SET_CONNECT_SEL, 1379 mux_idx); 1380 } 1381 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); 1382 1383 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); 1384 if (substream->runtime) 1385 per_pin->channels = substream->runtime->channels; 1386 per_pin->setup = true; 1387 per_pin->mux_idx = mux_idx; 1388 1389 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1390 } 1391 1392 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, 1393 struct hdmi_spec_per_pin *per_pin) 1394 { 1395 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1396 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); 1397 1398 per_pin->chmap_set = false; 1399 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1400 1401 per_pin->setup = false; 1402 per_pin->channels = 0; 1403 } 1404 1405 /* update per_pin ELD from the given new ELD; 1406 * setup info frame and notification accordingly 1407 */ 1408 static void update_eld(struct hda_codec *codec, 1409 struct hdmi_spec_per_pin *per_pin, 1410 struct hdmi_eld *eld) 1411 { 1412 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 1413 struct hdmi_spec *spec = codec->spec; 1414 bool old_eld_valid = pin_eld->eld_valid; 1415 bool eld_changed; 1416 int pcm_idx = -1; 1417 1418 /* for monitor disconnection, save pcm_idx firstly */ 1419 pcm_idx = per_pin->pcm_idx; 1420 if (spec->dyn_pcm_assign) { 1421 if (eld->eld_valid) { 1422 hdmi_attach_hda_pcm(spec, per_pin); 1423 hdmi_pcm_setup_pin(spec, per_pin); 1424 } else { 1425 hdmi_pcm_reset_pin(spec, per_pin); 1426 hdmi_detach_hda_pcm(spec, per_pin); 1427 } 1428 } 1429 /* if pcm_idx == -1, it means this is in monitor connection event 1430 * we can get the correct pcm_idx now. 1431 */ 1432 if (pcm_idx == -1) 1433 pcm_idx = per_pin->pcm_idx; 1434 1435 if (eld->eld_valid) 1436 snd_hdmi_show_eld(codec, &eld->info); 1437 1438 eld_changed = (pin_eld->eld_valid != eld->eld_valid); 1439 if (eld->eld_valid && pin_eld->eld_valid) 1440 if (pin_eld->eld_size != eld->eld_size || 1441 memcmp(pin_eld->eld_buffer, eld->eld_buffer, 1442 eld->eld_size) != 0) 1443 eld_changed = true; 1444 1445 pin_eld->monitor_present = eld->monitor_present; 1446 pin_eld->eld_valid = eld->eld_valid; 1447 pin_eld->eld_size = eld->eld_size; 1448 if (eld->eld_valid) 1449 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size); 1450 pin_eld->info = eld->info; 1451 1452 /* 1453 * Re-setup pin and infoframe. This is needed e.g. when 1454 * - sink is first plugged-in 1455 * - transcoder can change during stream playback on Haswell 1456 * and this can make HW reset converter selection on a pin. 1457 */ 1458 if (eld->eld_valid && !old_eld_valid && per_pin->setup) { 1459 pin_cvt_fixup(codec, per_pin, 0); 1460 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1461 } 1462 1463 if (eld_changed && pcm_idx >= 0) 1464 snd_ctl_notify(codec->card, 1465 SNDRV_CTL_EVENT_MASK_VALUE | 1466 SNDRV_CTL_EVENT_MASK_INFO, 1467 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); 1468 } 1469 1470 /* update ELD and jack state via HD-audio verbs */ 1471 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, 1472 int repoll) 1473 { 1474 struct hda_jack_tbl *jack; 1475 struct hda_codec *codec = per_pin->codec; 1476 struct hdmi_spec *spec = codec->spec; 1477 struct hdmi_eld *eld = &spec->temp_eld; 1478 hda_nid_t pin_nid = per_pin->pin_nid; 1479 /* 1480 * Always execute a GetPinSense verb here, even when called from 1481 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited 1482 * response's PD bit is not the real PD value, but indicates that 1483 * the real PD value changed. An older version of the HD-audio 1484 * specification worked this way. Hence, we just ignore the data in 1485 * the unsolicited response to avoid custom WARs. 1486 */ 1487 int present; 1488 bool ret; 1489 bool do_repoll = false; 1490 1491 present = snd_hda_pin_sense(codec, pin_nid); 1492 1493 mutex_lock(&per_pin->lock); 1494 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); 1495 if (eld->monitor_present) 1496 eld->eld_valid = !!(present & AC_PINSENSE_ELDV); 1497 else 1498 eld->eld_valid = false; 1499 1500 codec_dbg(codec, 1501 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n", 1502 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); 1503 1504 if (eld->eld_valid) { 1505 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer, 1506 &eld->eld_size) < 0) 1507 eld->eld_valid = false; 1508 else { 1509 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, 1510 eld->eld_size) < 0) 1511 eld->eld_valid = false; 1512 } 1513 if (!eld->eld_valid && repoll) 1514 do_repoll = true; 1515 } 1516 1517 if (do_repoll) 1518 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300)); 1519 else 1520 update_eld(codec, per_pin, eld); 1521 1522 ret = !repoll || !eld->monitor_present || eld->eld_valid; 1523 1524 jack = snd_hda_jack_tbl_get(codec, pin_nid); 1525 if (jack) 1526 jack->block_report = !ret; 1527 1528 mutex_unlock(&per_pin->lock); 1529 return ret; 1530 } 1531 1532 static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec, 1533 struct hdmi_spec_per_pin *per_pin) 1534 { 1535 struct hdmi_spec *spec = codec->spec; 1536 struct snd_jack *jack = NULL; 1537 struct hda_jack_tbl *jack_tbl; 1538 1539 /* if !dyn_pcm_assign, get jack from hda_jack_tbl 1540 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not 1541 * NULL even after snd_hda_jack_tbl_clear() is called to 1542 * free snd_jack. This may cause access invalid memory 1543 * when calling snd_jack_report 1544 */ 1545 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign) 1546 jack = spec->pcm_rec[per_pin->pcm_idx].jack; 1547 else if (!spec->dyn_pcm_assign) { 1548 /* 1549 * jack tbl doesn't support DP MST 1550 * DP MST will use dyn_pcm_assign, 1551 * so DP MST will never come here 1552 */ 1553 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid); 1554 if (jack_tbl) 1555 jack = jack_tbl->jack; 1556 } 1557 return jack; 1558 } 1559 1560 /* update ELD and jack state via audio component */ 1561 static void sync_eld_via_acomp(struct hda_codec *codec, 1562 struct hdmi_spec_per_pin *per_pin) 1563 { 1564 struct hdmi_spec *spec = codec->spec; 1565 struct hdmi_eld *eld = &spec->temp_eld; 1566 struct snd_jack *jack = NULL; 1567 int size; 1568 1569 mutex_lock(&per_pin->lock); 1570 eld->monitor_present = false; 1571 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, 1572 per_pin->dev_id, &eld->monitor_present, 1573 eld->eld_buffer, ELD_MAX_SIZE); 1574 if (size > 0) { 1575 size = min(size, ELD_MAX_SIZE); 1576 if (snd_hdmi_parse_eld(codec, &eld->info, 1577 eld->eld_buffer, size) < 0) 1578 size = -EINVAL; 1579 } 1580 1581 if (size > 0) { 1582 eld->eld_valid = true; 1583 eld->eld_size = size; 1584 } else { 1585 eld->eld_valid = false; 1586 eld->eld_size = 0; 1587 } 1588 1589 /* pcm_idx >=0 before update_eld() means it is in monitor 1590 * disconnected event. Jack must be fetched before update_eld() 1591 */ 1592 jack = pin_idx_to_jack(codec, per_pin); 1593 update_eld(codec, per_pin, eld); 1594 if (jack == NULL) 1595 jack = pin_idx_to_jack(codec, per_pin); 1596 if (jack == NULL) 1597 goto unlock; 1598 snd_jack_report(jack, 1599 eld->monitor_present ? SND_JACK_AVOUT : 0); 1600 unlock: 1601 mutex_unlock(&per_pin->lock); 1602 } 1603 1604 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) 1605 { 1606 struct hda_codec *codec = per_pin->codec; 1607 struct hdmi_spec *spec = codec->spec; 1608 int ret; 1609 1610 /* no temporary power up/down needed for component notifier */ 1611 if (!codec_has_acomp(codec)) 1612 snd_hda_power_up_pm(codec); 1613 1614 mutex_lock(&spec->pcm_lock); 1615 if (codec_has_acomp(codec)) { 1616 sync_eld_via_acomp(codec, per_pin); 1617 ret = false; /* don't call snd_hda_jack_report_sync() */ 1618 } else { 1619 ret = hdmi_present_sense_via_verbs(per_pin, repoll); 1620 } 1621 mutex_unlock(&spec->pcm_lock); 1622 1623 if (!codec_has_acomp(codec)) 1624 snd_hda_power_down_pm(codec); 1625 1626 return ret; 1627 } 1628 1629 static void hdmi_repoll_eld(struct work_struct *work) 1630 { 1631 struct hdmi_spec_per_pin *per_pin = 1632 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); 1633 1634 if (per_pin->repoll_count++ > 6) 1635 per_pin->repoll_count = 0; 1636 1637 if (hdmi_present_sense(per_pin, per_pin->repoll_count)) 1638 snd_hda_jack_report_sync(per_pin->codec); 1639 } 1640 1641 static void intel_haswell_fixup_connect_list(struct hda_codec *codec, 1642 hda_nid_t nid); 1643 1644 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) 1645 { 1646 struct hdmi_spec *spec = codec->spec; 1647 unsigned int caps, config; 1648 int pin_idx; 1649 struct hdmi_spec_per_pin *per_pin; 1650 int err; 1651 int dev_num, i; 1652 1653 caps = snd_hda_query_pin_caps(codec, pin_nid); 1654 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) 1655 return 0; 1656 1657 /* 1658 * For DP MST audio, Configuration Default is the same for 1659 * all device entries on the same pin 1660 */ 1661 config = snd_hda_codec_get_pincfg(codec, pin_nid); 1662 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE) 1663 return 0; 1664 1665 /* 1666 * To simplify the implementation, malloc all 1667 * the virtual pins in the initialization statically 1668 */ 1669 if (is_haswell_plus(codec)) { 1670 /* 1671 * On Intel platforms, device entries number is 1672 * changed dynamically. If there is a DP MST 1673 * hub connected, the device entries number is 3. 1674 * Otherwise, it is 1. 1675 * Here we manually set dev_num to 3, so that 1676 * we can initialize all the device entries when 1677 * bootup statically. 1678 */ 1679 dev_num = 3; 1680 spec->dev_num = 3; 1681 } else if (spec->dyn_pcm_assign && codec->dp_mst) { 1682 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; 1683 /* 1684 * spec->dev_num is the maxinum number of device entries 1685 * among all the pins 1686 */ 1687 spec->dev_num = (spec->dev_num > dev_num) ? 1688 spec->dev_num : dev_num; 1689 } else { 1690 /* 1691 * If the platform doesn't support DP MST, 1692 * manually set dev_num to 1. This means 1693 * the pin has only one device entry. 1694 */ 1695 dev_num = 1; 1696 spec->dev_num = 1; 1697 } 1698 1699 for (i = 0; i < dev_num; i++) { 1700 pin_idx = spec->num_pins; 1701 per_pin = snd_array_new(&spec->pins); 1702 1703 if (!per_pin) 1704 return -ENOMEM; 1705 1706 if (spec->dyn_pcm_assign) { 1707 per_pin->pcm = NULL; 1708 per_pin->pcm_idx = -1; 1709 } else { 1710 per_pin->pcm = get_hdmi_pcm(spec, pin_idx); 1711 per_pin->pcm_idx = pin_idx; 1712 } 1713 per_pin->pin_nid = pin_nid; 1714 per_pin->pin_nid_idx = spec->num_nids; 1715 per_pin->dev_id = i; 1716 per_pin->non_pcm = false; 1717 snd_hda_set_dev_select(codec, pin_nid, i); 1718 if (is_haswell_plus(codec)) 1719 intel_haswell_fixup_connect_list(codec, pin_nid); 1720 err = hdmi_read_pin_conn(codec, pin_idx); 1721 if (err < 0) 1722 return err; 1723 spec->num_pins++; 1724 } 1725 spec->num_nids++; 1726 1727 return 0; 1728 } 1729 1730 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1731 { 1732 struct hdmi_spec *spec = codec->spec; 1733 struct hdmi_spec_per_cvt *per_cvt; 1734 unsigned int chans; 1735 int err; 1736 1737 chans = get_wcaps(codec, cvt_nid); 1738 chans = get_wcaps_channels(chans); 1739 1740 per_cvt = snd_array_new(&spec->cvts); 1741 if (!per_cvt) 1742 return -ENOMEM; 1743 1744 per_cvt->cvt_nid = cvt_nid; 1745 per_cvt->channels_min = 2; 1746 if (chans <= 16) { 1747 per_cvt->channels_max = chans; 1748 if (chans > spec->chmap.channels_max) 1749 spec->chmap.channels_max = chans; 1750 } 1751 1752 err = snd_hda_query_supported_pcm(codec, cvt_nid, 1753 &per_cvt->rates, 1754 &per_cvt->formats, 1755 &per_cvt->maxbps); 1756 if (err < 0) 1757 return err; 1758 1759 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) 1760 spec->cvt_nids[spec->num_cvts] = cvt_nid; 1761 spec->num_cvts++; 1762 1763 return 0; 1764 } 1765 1766 static int hdmi_parse_codec(struct hda_codec *codec) 1767 { 1768 hda_nid_t nid; 1769 int i, nodes; 1770 1771 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid); 1772 if (!nid || nodes < 0) { 1773 codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); 1774 return -EINVAL; 1775 } 1776 1777 for (i = 0; i < nodes; i++, nid++) { 1778 unsigned int caps; 1779 unsigned int type; 1780 1781 caps = get_wcaps(codec, nid); 1782 type = get_wcaps_type(caps); 1783 1784 if (!(caps & AC_WCAP_DIGITAL)) 1785 continue; 1786 1787 switch (type) { 1788 case AC_WID_AUD_OUT: 1789 hdmi_add_cvt(codec, nid); 1790 break; 1791 case AC_WID_PIN: 1792 hdmi_add_pin(codec, nid); 1793 break; 1794 } 1795 } 1796 1797 return 0; 1798 } 1799 1800 /* 1801 */ 1802 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1803 { 1804 struct hda_spdif_out *spdif; 1805 bool non_pcm; 1806 1807 mutex_lock(&codec->spdif_mutex); 1808 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); 1809 /* Add sanity check to pass klockwork check. 1810 * This should never happen. 1811 */ 1812 if (WARN_ON(spdif == NULL)) 1813 return true; 1814 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); 1815 mutex_unlock(&codec->spdif_mutex); 1816 return non_pcm; 1817 } 1818 1819 /* 1820 * HDMI callbacks 1821 */ 1822 1823 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 1824 struct hda_codec *codec, 1825 unsigned int stream_tag, 1826 unsigned int format, 1827 struct snd_pcm_substream *substream) 1828 { 1829 hda_nid_t cvt_nid = hinfo->nid; 1830 struct hdmi_spec *spec = codec->spec; 1831 int pin_idx; 1832 struct hdmi_spec_per_pin *per_pin; 1833 hda_nid_t pin_nid; 1834 struct snd_pcm_runtime *runtime = substream->runtime; 1835 bool non_pcm; 1836 int pinctl; 1837 int err; 1838 1839 mutex_lock(&spec->pcm_lock); 1840 pin_idx = hinfo_to_pin_index(codec, hinfo); 1841 if (spec->dyn_pcm_assign && pin_idx < 0) { 1842 /* when dyn_pcm_assign and pcm is not bound to a pin 1843 * skip pin setup and return 0 to make audio playback 1844 * be ongoing 1845 */ 1846 pin_cvt_fixup(codec, NULL, cvt_nid); 1847 snd_hda_codec_setup_stream(codec, cvt_nid, 1848 stream_tag, 0, format); 1849 mutex_unlock(&spec->pcm_lock); 1850 return 0; 1851 } 1852 1853 if (snd_BUG_ON(pin_idx < 0)) { 1854 mutex_unlock(&spec->pcm_lock); 1855 return -EINVAL; 1856 } 1857 per_pin = get_pin(spec, pin_idx); 1858 pin_nid = per_pin->pin_nid; 1859 1860 /* Verify pin:cvt selections to avoid silent audio after S3. 1861 * After S3, the audio driver restores pin:cvt selections 1862 * but this can happen before gfx is ready and such selection 1863 * is overlooked by HW. Thus multiple pins can share a same 1864 * default convertor and mute control will affect each other, 1865 * which can cause a resumed audio playback become silent 1866 * after S3. 1867 */ 1868 pin_cvt_fixup(codec, per_pin, 0); 1869 1870 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ 1871 /* Todo: add DP1.2 MST audio support later */ 1872 if (codec_has_acomp(codec)) 1873 snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id, 1874 runtime->rate); 1875 1876 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); 1877 mutex_lock(&per_pin->lock); 1878 per_pin->channels = substream->runtime->channels; 1879 per_pin->setup = true; 1880 1881 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1882 mutex_unlock(&per_pin->lock); 1883 if (spec->dyn_pin_out) { 1884 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 1885 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 1886 snd_hda_codec_write(codec, pin_nid, 0, 1887 AC_VERB_SET_PIN_WIDGET_CONTROL, 1888 pinctl | PIN_OUT); 1889 } 1890 1891 /* snd_hda_set_dev_select() has been called before */ 1892 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid, 1893 stream_tag, format); 1894 mutex_unlock(&spec->pcm_lock); 1895 return err; 1896 } 1897 1898 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 1899 struct hda_codec *codec, 1900 struct snd_pcm_substream *substream) 1901 { 1902 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 1903 return 0; 1904 } 1905 1906 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, 1907 struct hda_codec *codec, 1908 struct snd_pcm_substream *substream) 1909 { 1910 struct hdmi_spec *spec = codec->spec; 1911 int cvt_idx, pin_idx, pcm_idx; 1912 struct hdmi_spec_per_cvt *per_cvt; 1913 struct hdmi_spec_per_pin *per_pin; 1914 int pinctl; 1915 1916 if (hinfo->nid) { 1917 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1918 if (snd_BUG_ON(pcm_idx < 0)) 1919 return -EINVAL; 1920 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); 1921 if (snd_BUG_ON(cvt_idx < 0)) 1922 return -EINVAL; 1923 per_cvt = get_cvt(spec, cvt_idx); 1924 1925 snd_BUG_ON(!per_cvt->assigned); 1926 per_cvt->assigned = 0; 1927 hinfo->nid = 0; 1928 1929 mutex_lock(&spec->pcm_lock); 1930 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1931 clear_bit(pcm_idx, &spec->pcm_in_use); 1932 pin_idx = hinfo_to_pin_index(codec, hinfo); 1933 if (spec->dyn_pcm_assign && pin_idx < 0) { 1934 mutex_unlock(&spec->pcm_lock); 1935 return 0; 1936 } 1937 1938 if (snd_BUG_ON(pin_idx < 0)) { 1939 mutex_unlock(&spec->pcm_lock); 1940 return -EINVAL; 1941 } 1942 per_pin = get_pin(spec, pin_idx); 1943 1944 if (spec->dyn_pin_out) { 1945 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 1946 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 1947 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 1948 AC_VERB_SET_PIN_WIDGET_CONTROL, 1949 pinctl & ~PIN_OUT); 1950 } 1951 1952 mutex_lock(&per_pin->lock); 1953 per_pin->chmap_set = false; 1954 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1955 1956 per_pin->setup = false; 1957 per_pin->channels = 0; 1958 mutex_unlock(&per_pin->lock); 1959 mutex_unlock(&spec->pcm_lock); 1960 } 1961 1962 return 0; 1963 } 1964 1965 static const struct hda_pcm_ops generic_ops = { 1966 .open = hdmi_pcm_open, 1967 .close = hdmi_pcm_close, 1968 .prepare = generic_hdmi_playback_pcm_prepare, 1969 .cleanup = generic_hdmi_playback_pcm_cleanup, 1970 }; 1971 1972 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) 1973 { 1974 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 1975 struct hdmi_spec *spec = codec->spec; 1976 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 1977 1978 if (!per_pin) 1979 return 0; 1980 1981 return per_pin->sink_eld.info.spk_alloc; 1982 } 1983 1984 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, 1985 unsigned char *chmap) 1986 { 1987 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 1988 struct hdmi_spec *spec = codec->spec; 1989 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 1990 1991 /* chmap is already set to 0 in caller */ 1992 if (!per_pin) 1993 return; 1994 1995 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); 1996 } 1997 1998 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, 1999 unsigned char *chmap, int prepared) 2000 { 2001 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2002 struct hdmi_spec *spec = codec->spec; 2003 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2004 2005 if (!per_pin) 2006 return; 2007 mutex_lock(&per_pin->lock); 2008 per_pin->chmap_set = true; 2009 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); 2010 if (prepared) 2011 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 2012 mutex_unlock(&per_pin->lock); 2013 } 2014 2015 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) 2016 { 2017 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2018 struct hdmi_spec *spec = codec->spec; 2019 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2020 2021 return per_pin ? true:false; 2022 } 2023 2024 static int generic_hdmi_build_pcms(struct hda_codec *codec) 2025 { 2026 struct hdmi_spec *spec = codec->spec; 2027 int idx; 2028 2029 /* 2030 * for non-mst mode, pcm number is the same as before 2031 * for DP MST mode, pcm number is (nid number + dev_num - 1) 2032 * dev_num is the device entry number in a pin 2033 * 2034 */ 2035 for (idx = 0; idx < spec->num_nids + spec->dev_num - 1; idx++) { 2036 struct hda_pcm *info; 2037 struct hda_pcm_stream *pstr; 2038 2039 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); 2040 if (!info) 2041 return -ENOMEM; 2042 2043 spec->pcm_rec[idx].pcm = info; 2044 spec->pcm_used++; 2045 info->pcm_type = HDA_PCM_TYPE_HDMI; 2046 info->own_chmap = true; 2047 2048 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2049 pstr->substreams = 1; 2050 pstr->ops = generic_ops; 2051 /* pcm number is less than 16 */ 2052 if (spec->pcm_used >= 16) 2053 break; 2054 /* other pstr fields are set in open */ 2055 } 2056 2057 return 0; 2058 } 2059 2060 static void free_hdmi_jack_priv(struct snd_jack *jack) 2061 { 2062 struct hdmi_pcm *pcm = jack->private_data; 2063 2064 pcm->jack = NULL; 2065 } 2066 2067 static int add_hdmi_jack_kctl(struct hda_codec *codec, 2068 struct hdmi_spec *spec, 2069 int pcm_idx, 2070 const char *name) 2071 { 2072 struct snd_jack *jack; 2073 int err; 2074 2075 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack, 2076 true, false); 2077 if (err < 0) 2078 return err; 2079 2080 spec->pcm_rec[pcm_idx].jack = jack; 2081 jack->private_data = &spec->pcm_rec[pcm_idx]; 2082 jack->private_free = free_hdmi_jack_priv; 2083 return 0; 2084 } 2085 2086 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) 2087 { 2088 char hdmi_str[32] = "HDMI/DP"; 2089 struct hdmi_spec *spec = codec->spec; 2090 struct hdmi_spec_per_pin *per_pin; 2091 struct hda_jack_tbl *jack; 2092 int pcmdev = get_pcm_rec(spec, pcm_idx)->device; 2093 bool phantom_jack; 2094 int ret; 2095 2096 if (pcmdev > 0) 2097 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); 2098 2099 if (spec->dyn_pcm_assign) 2100 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str); 2101 2102 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */ 2103 /* if !dyn_pcm_assign, it must be non-MST mode. 2104 * This means pcms and pins are statically mapped. 2105 * And pcm_idx is pin_idx. 2106 */ 2107 per_pin = get_pin(spec, pcm_idx); 2108 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid); 2109 if (phantom_jack) 2110 strncat(hdmi_str, " Phantom", 2111 sizeof(hdmi_str) - strlen(hdmi_str) - 1); 2112 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 2113 phantom_jack); 2114 if (ret < 0) 2115 return ret; 2116 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid); 2117 if (jack == NULL) 2118 return 0; 2119 /* assign jack->jack to pcm_rec[].jack to 2120 * align with dyn_pcm_assign mode 2121 */ 2122 spec->pcm_rec[pcm_idx].jack = jack->jack; 2123 return 0; 2124 } 2125 2126 static int generic_hdmi_build_controls(struct hda_codec *codec) 2127 { 2128 struct hdmi_spec *spec = codec->spec; 2129 int err; 2130 int pin_idx, pcm_idx; 2131 2132 2133 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2134 err = generic_hdmi_build_jack(codec, pcm_idx); 2135 if (err < 0) 2136 return err; 2137 2138 /* create the spdif for each pcm 2139 * pin will be bound when monitor is connected 2140 */ 2141 if (spec->dyn_pcm_assign) 2142 err = snd_hda_create_dig_out_ctls(codec, 2143 0, spec->cvt_nids[0], 2144 HDA_PCM_TYPE_HDMI); 2145 else { 2146 struct hdmi_spec_per_pin *per_pin = 2147 get_pin(spec, pcm_idx); 2148 err = snd_hda_create_dig_out_ctls(codec, 2149 per_pin->pin_nid, 2150 per_pin->mux_nids[0], 2151 HDA_PCM_TYPE_HDMI); 2152 } 2153 if (err < 0) 2154 return err; 2155 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2156 2157 /* add control for ELD Bytes */ 2158 err = hdmi_create_eld_ctl(codec, pcm_idx, 2159 get_pcm_rec(spec, pcm_idx)->device); 2160 if (err < 0) 2161 return err; 2162 } 2163 2164 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2165 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2166 2167 hdmi_present_sense(per_pin, 0); 2168 } 2169 2170 /* add channel maps */ 2171 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2172 struct hda_pcm *pcm; 2173 2174 pcm = get_pcm_rec(spec, pcm_idx); 2175 if (!pcm || !pcm->pcm) 2176 break; 2177 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); 2178 if (err < 0) 2179 return err; 2180 } 2181 2182 return 0; 2183 } 2184 2185 static int generic_hdmi_init_per_pins(struct hda_codec *codec) 2186 { 2187 struct hdmi_spec *spec = codec->spec; 2188 int pin_idx; 2189 2190 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2191 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2192 2193 per_pin->codec = codec; 2194 mutex_init(&per_pin->lock); 2195 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); 2196 eld_proc_new(per_pin, pin_idx); 2197 } 2198 return 0; 2199 } 2200 2201 static int generic_hdmi_init(struct hda_codec *codec) 2202 { 2203 struct hdmi_spec *spec = codec->spec; 2204 int pin_idx; 2205 2206 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2207 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2208 hda_nid_t pin_nid = per_pin->pin_nid; 2209 int dev_id = per_pin->dev_id; 2210 2211 snd_hda_set_dev_select(codec, pin_nid, dev_id); 2212 hdmi_init_pin(codec, pin_nid); 2213 if (!codec_has_acomp(codec)) 2214 snd_hda_jack_detect_enable_callback(codec, pin_nid, 2215 codec->jackpoll_interval > 0 ? 2216 jack_callback : NULL); 2217 } 2218 return 0; 2219 } 2220 2221 static void hdmi_array_init(struct hdmi_spec *spec, int nums) 2222 { 2223 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); 2224 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); 2225 } 2226 2227 static void hdmi_array_free(struct hdmi_spec *spec) 2228 { 2229 snd_array_free(&spec->pins); 2230 snd_array_free(&spec->cvts); 2231 } 2232 2233 static void generic_spec_free(struct hda_codec *codec) 2234 { 2235 struct hdmi_spec *spec = codec->spec; 2236 2237 if (spec) { 2238 hdmi_array_free(spec); 2239 kfree(spec); 2240 codec->spec = NULL; 2241 } 2242 codec->dp_mst = false; 2243 } 2244 2245 static void generic_hdmi_free(struct hda_codec *codec) 2246 { 2247 struct hdmi_spec *spec = codec->spec; 2248 int pin_idx, pcm_idx; 2249 2250 if (codec_has_acomp(codec)) 2251 snd_hdac_i915_register_notifier(NULL); 2252 2253 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2254 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2255 cancel_delayed_work_sync(&per_pin->work); 2256 eld_proc_free(per_pin); 2257 } 2258 2259 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2260 if (spec->pcm_rec[pcm_idx].jack == NULL) 2261 continue; 2262 if (spec->dyn_pcm_assign) 2263 snd_device_free(codec->card, 2264 spec->pcm_rec[pcm_idx].jack); 2265 else 2266 spec->pcm_rec[pcm_idx].jack = NULL; 2267 } 2268 2269 generic_spec_free(codec); 2270 } 2271 2272 #ifdef CONFIG_PM 2273 static int generic_hdmi_resume(struct hda_codec *codec) 2274 { 2275 struct hdmi_spec *spec = codec->spec; 2276 int pin_idx; 2277 2278 codec->patch_ops.init(codec); 2279 regcache_sync(codec->core.regmap); 2280 2281 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2282 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2283 hdmi_present_sense(per_pin, 1); 2284 } 2285 return 0; 2286 } 2287 #endif 2288 2289 static const struct hda_codec_ops generic_hdmi_patch_ops = { 2290 .init = generic_hdmi_init, 2291 .free = generic_hdmi_free, 2292 .build_pcms = generic_hdmi_build_pcms, 2293 .build_controls = generic_hdmi_build_controls, 2294 .unsol_event = hdmi_unsol_event, 2295 #ifdef CONFIG_PM 2296 .resume = generic_hdmi_resume, 2297 #endif 2298 }; 2299 2300 static const struct hdmi_ops generic_standard_hdmi_ops = { 2301 .pin_get_eld = snd_hdmi_get_eld, 2302 .pin_setup_infoframe = hdmi_pin_setup_infoframe, 2303 .pin_hbr_setup = hdmi_pin_hbr_setup, 2304 .setup_stream = hdmi_setup_stream, 2305 }; 2306 2307 /* allocate codec->spec and assign/initialize generic parser ops */ 2308 static int alloc_generic_hdmi(struct hda_codec *codec) 2309 { 2310 struct hdmi_spec *spec; 2311 2312 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2313 if (!spec) 2314 return -ENOMEM; 2315 2316 spec->ops = generic_standard_hdmi_ops; 2317 spec->dev_num = 1; /* initialize to 1 */ 2318 mutex_init(&spec->pcm_lock); 2319 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); 2320 2321 spec->chmap.ops.get_chmap = hdmi_get_chmap; 2322 spec->chmap.ops.set_chmap = hdmi_set_chmap; 2323 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; 2324 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc, 2325 2326 codec->spec = spec; 2327 hdmi_array_init(spec, 4); 2328 2329 codec->patch_ops = generic_hdmi_patch_ops; 2330 2331 return 0; 2332 } 2333 2334 /* generic HDMI parser */ 2335 static int patch_generic_hdmi(struct hda_codec *codec) 2336 { 2337 int err; 2338 2339 err = alloc_generic_hdmi(codec); 2340 if (err < 0) 2341 return err; 2342 2343 err = hdmi_parse_codec(codec); 2344 if (err < 0) { 2345 generic_spec_free(codec); 2346 return err; 2347 } 2348 2349 generic_hdmi_init_per_pins(codec); 2350 return 0; 2351 } 2352 2353 /* 2354 * Intel codec parsers and helpers 2355 */ 2356 2357 static void intel_haswell_fixup_connect_list(struct hda_codec *codec, 2358 hda_nid_t nid) 2359 { 2360 struct hdmi_spec *spec = codec->spec; 2361 hda_nid_t conns[4]; 2362 int nconns; 2363 2364 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns)); 2365 if (nconns == spec->num_cvts && 2366 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t))) 2367 return; 2368 2369 /* override pins connection list */ 2370 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid); 2371 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids); 2372 } 2373 2374 #define INTEL_VENDOR_NID 0x08 2375 #define INTEL_GLK_VENDOR_NID 0x0B 2376 #define INTEL_GET_VENDOR_VERB 0xf81 2377 #define INTEL_SET_VENDOR_VERB 0x781 2378 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ 2379 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ 2380 2381 static void intel_haswell_enable_all_pins(struct hda_codec *codec, 2382 bool update_tree) 2383 { 2384 unsigned int vendor_param; 2385 struct hdmi_spec *spec = codec->spec; 2386 2387 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2388 INTEL_GET_VENDOR_VERB, 0); 2389 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) 2390 return; 2391 2392 vendor_param |= INTEL_EN_ALL_PIN_CVTS; 2393 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2394 INTEL_SET_VENDOR_VERB, vendor_param); 2395 if (vendor_param == -1) 2396 return; 2397 2398 if (update_tree) 2399 snd_hda_codec_update_widgets(codec); 2400 } 2401 2402 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) 2403 { 2404 unsigned int vendor_param; 2405 struct hdmi_spec *spec = codec->spec; 2406 2407 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2408 INTEL_GET_VENDOR_VERB, 0); 2409 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) 2410 return; 2411 2412 /* enable DP1.2 mode */ 2413 vendor_param |= INTEL_EN_DP12; 2414 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); 2415 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, 2416 INTEL_SET_VENDOR_VERB, vendor_param); 2417 } 2418 2419 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. 2420 * Otherwise you may get severe h/w communication errors. 2421 */ 2422 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, 2423 unsigned int power_state) 2424 { 2425 if (power_state == AC_PWRST_D0) { 2426 intel_haswell_enable_all_pins(codec, false); 2427 intel_haswell_fixup_enable_dp12(codec); 2428 } 2429 2430 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); 2431 snd_hda_codec_set_power_to_all(codec, fg, power_state); 2432 } 2433 2434 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) 2435 { 2436 struct hda_codec *codec = audio_ptr; 2437 int pin_nid; 2438 int dev_id = pipe; 2439 2440 /* we assume only from port-B to port-D */ 2441 if (port < 1 || port > 3) 2442 return; 2443 2444 switch (codec->core.vendor_id) { 2445 case 0x80860054: /* ILK */ 2446 case 0x80862804: /* ILK */ 2447 case 0x80862882: /* VLV */ 2448 pin_nid = port + 0x03; 2449 break; 2450 default: 2451 pin_nid = port + 0x04; 2452 break; 2453 } 2454 2455 /* skip notification during system suspend (but not in runtime PM); 2456 * the state will be updated at resume 2457 */ 2458 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) 2459 return; 2460 /* ditto during suspend/resume process itself */ 2461 if (atomic_read(&(codec)->core.in_pm)) 2462 return; 2463 2464 snd_hdac_i915_set_bclk(&codec->bus->core); 2465 check_presence_and_report(codec, pin_nid, dev_id); 2466 } 2467 2468 /* register i915 component pin_eld_notify callback */ 2469 static void register_i915_notifier(struct hda_codec *codec) 2470 { 2471 struct hdmi_spec *spec = codec->spec; 2472 2473 spec->use_acomp_notifier = true; 2474 spec->i915_audio_ops.audio_ptr = codec; 2475 /* intel_audio_codec_enable() or intel_audio_codec_disable() 2476 * will call pin_eld_notify with using audio_ptr pointer 2477 * We need make sure audio_ptr is really setup 2478 */ 2479 wmb(); 2480 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify; 2481 snd_hdac_i915_register_notifier(&spec->i915_audio_ops); 2482 } 2483 2484 /* setup_stream ops override for HSW+ */ 2485 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 2486 hda_nid_t pin_nid, u32 stream_tag, int format) 2487 { 2488 haswell_verify_D0(codec, cvt_nid, pin_nid); 2489 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format); 2490 } 2491 2492 /* pin_cvt_fixup ops override for HSW+ and VLV+ */ 2493 static void i915_pin_cvt_fixup(struct hda_codec *codec, 2494 struct hdmi_spec_per_pin *per_pin, 2495 hda_nid_t cvt_nid) 2496 { 2497 if (per_pin) { 2498 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2499 per_pin->dev_id); 2500 intel_verify_pin_cvt_connect(codec, per_pin); 2501 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, 2502 per_pin->dev_id, per_pin->mux_idx); 2503 } else { 2504 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); 2505 } 2506 } 2507 2508 /* precondition and allocation for Intel codecs */ 2509 static int alloc_intel_hdmi(struct hda_codec *codec) 2510 { 2511 /* requires i915 binding */ 2512 if (!codec->bus->core.audio_component) { 2513 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); 2514 return -ENODEV; 2515 } 2516 2517 return alloc_generic_hdmi(codec); 2518 } 2519 2520 /* parse and post-process for Intel codecs */ 2521 static int parse_intel_hdmi(struct hda_codec *codec) 2522 { 2523 int err; 2524 2525 err = hdmi_parse_codec(codec); 2526 if (err < 0) { 2527 generic_spec_free(codec); 2528 return err; 2529 } 2530 2531 generic_hdmi_init_per_pins(codec); 2532 register_i915_notifier(codec); 2533 return 0; 2534 } 2535 2536 /* Intel Haswell and onwards; audio component with eld notifier */ 2537 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid) 2538 { 2539 struct hdmi_spec *spec; 2540 int err; 2541 2542 err = alloc_intel_hdmi(codec); 2543 if (err < 0) 2544 return err; 2545 spec = codec->spec; 2546 codec->dp_mst = true; 2547 spec->dyn_pcm_assign = true; 2548 spec->vendor_nid = vendor_nid; 2549 2550 intel_haswell_enable_all_pins(codec, true); 2551 intel_haswell_fixup_enable_dp12(codec); 2552 2553 /* For Haswell/Broadwell, the controller is also in the power well and 2554 * can cover the codec power request, and so need not set this flag. 2555 */ 2556 if (!is_haswell(codec) && !is_broadwell(codec)) 2557 codec->core.link_power_control = 1; 2558 2559 codec->patch_ops.set_power_state = haswell_set_power_state; 2560 codec->depop_delay = 0; 2561 codec->auto_runtime_pm = 1; 2562 2563 spec->ops.setup_stream = i915_hsw_setup_stream; 2564 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2565 2566 return parse_intel_hdmi(codec); 2567 } 2568 2569 static int patch_i915_hsw_hdmi(struct hda_codec *codec) 2570 { 2571 return intel_hsw_common_init(codec, INTEL_VENDOR_NID); 2572 } 2573 2574 static int patch_i915_glk_hdmi(struct hda_codec *codec) 2575 { 2576 return intel_hsw_common_init(codec, INTEL_GLK_VENDOR_NID); 2577 } 2578 2579 /* Intel Baytrail and Braswell; with eld notifier */ 2580 static int patch_i915_byt_hdmi(struct hda_codec *codec) 2581 { 2582 struct hdmi_spec *spec; 2583 int err; 2584 2585 err = alloc_intel_hdmi(codec); 2586 if (err < 0) 2587 return err; 2588 spec = codec->spec; 2589 2590 /* For Valleyview/Cherryview, only the display codec is in the display 2591 * power well and can use link_power ops to request/release the power. 2592 */ 2593 codec->core.link_power_control = 1; 2594 2595 codec->depop_delay = 0; 2596 codec->auto_runtime_pm = 1; 2597 2598 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2599 2600 return parse_intel_hdmi(codec); 2601 } 2602 2603 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ 2604 static int patch_i915_cpt_hdmi(struct hda_codec *codec) 2605 { 2606 int err; 2607 2608 err = alloc_intel_hdmi(codec); 2609 if (err < 0) 2610 return err; 2611 return parse_intel_hdmi(codec); 2612 } 2613 2614 /* 2615 * Shared non-generic implementations 2616 */ 2617 2618 static int simple_playback_build_pcms(struct hda_codec *codec) 2619 { 2620 struct hdmi_spec *spec = codec->spec; 2621 struct hda_pcm *info; 2622 unsigned int chans; 2623 struct hda_pcm_stream *pstr; 2624 struct hdmi_spec_per_cvt *per_cvt; 2625 2626 per_cvt = get_cvt(spec, 0); 2627 chans = get_wcaps(codec, per_cvt->cvt_nid); 2628 chans = get_wcaps_channels(chans); 2629 2630 info = snd_hda_codec_pcm_new(codec, "HDMI 0"); 2631 if (!info) 2632 return -ENOMEM; 2633 spec->pcm_rec[0].pcm = info; 2634 info->pcm_type = HDA_PCM_TYPE_HDMI; 2635 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2636 *pstr = spec->pcm_playback; 2637 pstr->nid = per_cvt->cvt_nid; 2638 if (pstr->channels_max <= 2 && chans && chans <= 16) 2639 pstr->channels_max = chans; 2640 2641 return 0; 2642 } 2643 2644 /* unsolicited event for jack sensing */ 2645 static void simple_hdmi_unsol_event(struct hda_codec *codec, 2646 unsigned int res) 2647 { 2648 snd_hda_jack_set_dirty_all(codec); 2649 snd_hda_jack_report_sync(codec); 2650 } 2651 2652 /* generic_hdmi_build_jack can be used for simple_hdmi, too, 2653 * as long as spec->pins[] is set correctly 2654 */ 2655 #define simple_hdmi_build_jack generic_hdmi_build_jack 2656 2657 static int simple_playback_build_controls(struct hda_codec *codec) 2658 { 2659 struct hdmi_spec *spec = codec->spec; 2660 struct hdmi_spec_per_cvt *per_cvt; 2661 int err; 2662 2663 per_cvt = get_cvt(spec, 0); 2664 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, 2665 per_cvt->cvt_nid, 2666 HDA_PCM_TYPE_HDMI); 2667 if (err < 0) 2668 return err; 2669 return simple_hdmi_build_jack(codec, 0); 2670 } 2671 2672 static int simple_playback_init(struct hda_codec *codec) 2673 { 2674 struct hdmi_spec *spec = codec->spec; 2675 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); 2676 hda_nid_t pin = per_pin->pin_nid; 2677 2678 snd_hda_codec_write(codec, pin, 0, 2679 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); 2680 /* some codecs require to unmute the pin */ 2681 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 2682 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, 2683 AMP_OUT_UNMUTE); 2684 snd_hda_jack_detect_enable(codec, pin); 2685 return 0; 2686 } 2687 2688 static void simple_playback_free(struct hda_codec *codec) 2689 { 2690 struct hdmi_spec *spec = codec->spec; 2691 2692 hdmi_array_free(spec); 2693 kfree(spec); 2694 } 2695 2696 /* 2697 * Nvidia specific implementations 2698 */ 2699 2700 #define Nv_VERB_SET_Channel_Allocation 0xF79 2701 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A 2702 #define Nv_VERB_SET_Audio_Protection_On 0xF98 2703 #define Nv_VERB_SET_Audio_Protection_Off 0xF99 2704 2705 #define nvhdmi_master_con_nid_7x 0x04 2706 #define nvhdmi_master_pin_nid_7x 0x05 2707 2708 static const hda_nid_t nvhdmi_con_nids_7x[4] = { 2709 /*front, rear, clfe, rear_surr */ 2710 0x6, 0x8, 0xa, 0xc, 2711 }; 2712 2713 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { 2714 /* set audio protect on */ 2715 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 2716 /* enable digital output on pin widget */ 2717 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2718 {} /* terminator */ 2719 }; 2720 2721 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { 2722 /* set audio protect on */ 2723 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 2724 /* enable digital output on pin widget */ 2725 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2726 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2727 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2728 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2729 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2730 {} /* terminator */ 2731 }; 2732 2733 #ifdef LIMITED_RATE_FMT_SUPPORT 2734 /* support only the safe format and rate */ 2735 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 2736 #define SUPPORTED_MAXBPS 16 2737 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE 2738 #else 2739 /* support all rates and formats */ 2740 #define SUPPORTED_RATES \ 2741 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ 2742 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ 2743 SNDRV_PCM_RATE_192000) 2744 #define SUPPORTED_MAXBPS 24 2745 #define SUPPORTED_FORMATS \ 2746 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 2747 #endif 2748 2749 static int nvhdmi_7x_init_2ch(struct hda_codec *codec) 2750 { 2751 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); 2752 return 0; 2753 } 2754 2755 static int nvhdmi_7x_init_8ch(struct hda_codec *codec) 2756 { 2757 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); 2758 return 0; 2759 } 2760 2761 static const unsigned int channels_2_6_8[] = { 2762 2, 6, 8 2763 }; 2764 2765 static const unsigned int channels_2_8[] = { 2766 2, 8 2767 }; 2768 2769 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { 2770 .count = ARRAY_SIZE(channels_2_6_8), 2771 .list = channels_2_6_8, 2772 .mask = 0, 2773 }; 2774 2775 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { 2776 .count = ARRAY_SIZE(channels_2_8), 2777 .list = channels_2_8, 2778 .mask = 0, 2779 }; 2780 2781 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, 2782 struct hda_codec *codec, 2783 struct snd_pcm_substream *substream) 2784 { 2785 struct hdmi_spec *spec = codec->spec; 2786 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; 2787 2788 switch (codec->preset->vendor_id) { 2789 case 0x10de0002: 2790 case 0x10de0003: 2791 case 0x10de0005: 2792 case 0x10de0006: 2793 hw_constraints_channels = &hw_constraints_2_8_channels; 2794 break; 2795 case 0x10de0007: 2796 hw_constraints_channels = &hw_constraints_2_6_8_channels; 2797 break; 2798 default: 2799 break; 2800 } 2801 2802 if (hw_constraints_channels != NULL) { 2803 snd_pcm_hw_constraint_list(substream->runtime, 0, 2804 SNDRV_PCM_HW_PARAM_CHANNELS, 2805 hw_constraints_channels); 2806 } else { 2807 snd_pcm_hw_constraint_step(substream->runtime, 0, 2808 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 2809 } 2810 2811 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 2812 } 2813 2814 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, 2815 struct hda_codec *codec, 2816 struct snd_pcm_substream *substream) 2817 { 2818 struct hdmi_spec *spec = codec->spec; 2819 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 2820 } 2821 2822 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 2823 struct hda_codec *codec, 2824 unsigned int stream_tag, 2825 unsigned int format, 2826 struct snd_pcm_substream *substream) 2827 { 2828 struct hdmi_spec *spec = codec->spec; 2829 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 2830 stream_tag, format, substream); 2831 } 2832 2833 static const struct hda_pcm_stream simple_pcm_playback = { 2834 .substreams = 1, 2835 .channels_min = 2, 2836 .channels_max = 2, 2837 .ops = { 2838 .open = simple_playback_pcm_open, 2839 .close = simple_playback_pcm_close, 2840 .prepare = simple_playback_pcm_prepare 2841 }, 2842 }; 2843 2844 static const struct hda_codec_ops simple_hdmi_patch_ops = { 2845 .build_controls = simple_playback_build_controls, 2846 .build_pcms = simple_playback_build_pcms, 2847 .init = simple_playback_init, 2848 .free = simple_playback_free, 2849 .unsol_event = simple_hdmi_unsol_event, 2850 }; 2851 2852 static int patch_simple_hdmi(struct hda_codec *codec, 2853 hda_nid_t cvt_nid, hda_nid_t pin_nid) 2854 { 2855 struct hdmi_spec *spec; 2856 struct hdmi_spec_per_cvt *per_cvt; 2857 struct hdmi_spec_per_pin *per_pin; 2858 2859 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2860 if (!spec) 2861 return -ENOMEM; 2862 2863 codec->spec = spec; 2864 hdmi_array_init(spec, 1); 2865 2866 spec->multiout.num_dacs = 0; /* no analog */ 2867 spec->multiout.max_channels = 2; 2868 spec->multiout.dig_out_nid = cvt_nid; 2869 spec->num_cvts = 1; 2870 spec->num_pins = 1; 2871 per_pin = snd_array_new(&spec->pins); 2872 per_cvt = snd_array_new(&spec->cvts); 2873 if (!per_pin || !per_cvt) { 2874 simple_playback_free(codec); 2875 return -ENOMEM; 2876 } 2877 per_cvt->cvt_nid = cvt_nid; 2878 per_pin->pin_nid = pin_nid; 2879 spec->pcm_playback = simple_pcm_playback; 2880 2881 codec->patch_ops = simple_hdmi_patch_ops; 2882 2883 return 0; 2884 } 2885 2886 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, 2887 int channels) 2888 { 2889 unsigned int chanmask; 2890 int chan = channels ? (channels - 1) : 1; 2891 2892 switch (channels) { 2893 default: 2894 case 0: 2895 case 2: 2896 chanmask = 0x00; 2897 break; 2898 case 4: 2899 chanmask = 0x08; 2900 break; 2901 case 6: 2902 chanmask = 0x0b; 2903 break; 2904 case 8: 2905 chanmask = 0x13; 2906 break; 2907 } 2908 2909 /* Set the audio infoframe channel allocation and checksum fields. The 2910 * channel count is computed implicitly by the hardware. */ 2911 snd_hda_codec_write(codec, 0x1, 0, 2912 Nv_VERB_SET_Channel_Allocation, chanmask); 2913 2914 snd_hda_codec_write(codec, 0x1, 0, 2915 Nv_VERB_SET_Info_Frame_Checksum, 2916 (0x71 - chan - chanmask)); 2917 } 2918 2919 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, 2920 struct hda_codec *codec, 2921 struct snd_pcm_substream *substream) 2922 { 2923 struct hdmi_spec *spec = codec->spec; 2924 int i; 2925 2926 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 2927 0, AC_VERB_SET_CHANNEL_STREAMID, 0); 2928 for (i = 0; i < 4; i++) { 2929 /* set the stream id */ 2930 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 2931 AC_VERB_SET_CHANNEL_STREAMID, 0); 2932 /* set the stream format */ 2933 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 2934 AC_VERB_SET_STREAM_FORMAT, 0); 2935 } 2936 2937 /* The audio hardware sends a channel count of 0x7 (8ch) when all the 2938 * streams are disabled. */ 2939 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 2940 2941 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 2942 } 2943 2944 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, 2945 struct hda_codec *codec, 2946 unsigned int stream_tag, 2947 unsigned int format, 2948 struct snd_pcm_substream *substream) 2949 { 2950 int chs; 2951 unsigned int dataDCC2, channel_id; 2952 int i; 2953 struct hdmi_spec *spec = codec->spec; 2954 struct hda_spdif_out *spdif; 2955 struct hdmi_spec_per_cvt *per_cvt; 2956 2957 mutex_lock(&codec->spdif_mutex); 2958 per_cvt = get_cvt(spec, 0); 2959 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); 2960 2961 chs = substream->runtime->channels; 2962 2963 dataDCC2 = 0x2; 2964 2965 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ 2966 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) 2967 snd_hda_codec_write(codec, 2968 nvhdmi_master_con_nid_7x, 2969 0, 2970 AC_VERB_SET_DIGI_CONVERT_1, 2971 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 2972 2973 /* set the stream id */ 2974 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 2975 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); 2976 2977 /* set the stream format */ 2978 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 2979 AC_VERB_SET_STREAM_FORMAT, format); 2980 2981 /* turn on again (if needed) */ 2982 /* enable and set the channel status audio/data flag */ 2983 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { 2984 snd_hda_codec_write(codec, 2985 nvhdmi_master_con_nid_7x, 2986 0, 2987 AC_VERB_SET_DIGI_CONVERT_1, 2988 spdif->ctls & 0xff); 2989 snd_hda_codec_write(codec, 2990 nvhdmi_master_con_nid_7x, 2991 0, 2992 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 2993 } 2994 2995 for (i = 0; i < 4; i++) { 2996 if (chs == 2) 2997 channel_id = 0; 2998 else 2999 channel_id = i * 2; 3000 3001 /* turn off SPDIF once; 3002 *otherwise the IEC958 bits won't be updated 3003 */ 3004 if (codec->spdif_status_reset && 3005 (spdif->ctls & AC_DIG1_ENABLE)) 3006 snd_hda_codec_write(codec, 3007 nvhdmi_con_nids_7x[i], 3008 0, 3009 AC_VERB_SET_DIGI_CONVERT_1, 3010 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3011 /* set the stream id */ 3012 snd_hda_codec_write(codec, 3013 nvhdmi_con_nids_7x[i], 3014 0, 3015 AC_VERB_SET_CHANNEL_STREAMID, 3016 (stream_tag << 4) | channel_id); 3017 /* set the stream format */ 3018 snd_hda_codec_write(codec, 3019 nvhdmi_con_nids_7x[i], 3020 0, 3021 AC_VERB_SET_STREAM_FORMAT, 3022 format); 3023 /* turn on again (if needed) */ 3024 /* enable and set the channel status audio/data flag */ 3025 if (codec->spdif_status_reset && 3026 (spdif->ctls & AC_DIG1_ENABLE)) { 3027 snd_hda_codec_write(codec, 3028 nvhdmi_con_nids_7x[i], 3029 0, 3030 AC_VERB_SET_DIGI_CONVERT_1, 3031 spdif->ctls & 0xff); 3032 snd_hda_codec_write(codec, 3033 nvhdmi_con_nids_7x[i], 3034 0, 3035 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3036 } 3037 } 3038 3039 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); 3040 3041 mutex_unlock(&codec->spdif_mutex); 3042 return 0; 3043 } 3044 3045 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { 3046 .substreams = 1, 3047 .channels_min = 2, 3048 .channels_max = 8, 3049 .nid = nvhdmi_master_con_nid_7x, 3050 .rates = SUPPORTED_RATES, 3051 .maxbps = SUPPORTED_MAXBPS, 3052 .formats = SUPPORTED_FORMATS, 3053 .ops = { 3054 .open = simple_playback_pcm_open, 3055 .close = nvhdmi_8ch_7x_pcm_close, 3056 .prepare = nvhdmi_8ch_7x_pcm_prepare 3057 }, 3058 }; 3059 3060 static int patch_nvhdmi_2ch(struct hda_codec *codec) 3061 { 3062 struct hdmi_spec *spec; 3063 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, 3064 nvhdmi_master_pin_nid_7x); 3065 if (err < 0) 3066 return err; 3067 3068 codec->patch_ops.init = nvhdmi_7x_init_2ch; 3069 /* override the PCM rates, etc, as the codec doesn't give full list */ 3070 spec = codec->spec; 3071 spec->pcm_playback.rates = SUPPORTED_RATES; 3072 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; 3073 spec->pcm_playback.formats = SUPPORTED_FORMATS; 3074 return 0; 3075 } 3076 3077 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) 3078 { 3079 struct hdmi_spec *spec = codec->spec; 3080 int err = simple_playback_build_pcms(codec); 3081 if (!err) { 3082 struct hda_pcm *info = get_pcm_rec(spec, 0); 3083 info->own_chmap = true; 3084 } 3085 return err; 3086 } 3087 3088 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) 3089 { 3090 struct hdmi_spec *spec = codec->spec; 3091 struct hda_pcm *info; 3092 struct snd_pcm_chmap *chmap; 3093 int err; 3094 3095 err = simple_playback_build_controls(codec); 3096 if (err < 0) 3097 return err; 3098 3099 /* add channel maps */ 3100 info = get_pcm_rec(spec, 0); 3101 err = snd_pcm_add_chmap_ctls(info->pcm, 3102 SNDRV_PCM_STREAM_PLAYBACK, 3103 snd_pcm_alt_chmaps, 8, 0, &chmap); 3104 if (err < 0) 3105 return err; 3106 switch (codec->preset->vendor_id) { 3107 case 0x10de0002: 3108 case 0x10de0003: 3109 case 0x10de0005: 3110 case 0x10de0006: 3111 chmap->channel_mask = (1U << 2) | (1U << 8); 3112 break; 3113 case 0x10de0007: 3114 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); 3115 } 3116 return 0; 3117 } 3118 3119 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) 3120 { 3121 struct hdmi_spec *spec; 3122 int err = patch_nvhdmi_2ch(codec); 3123 if (err < 0) 3124 return err; 3125 spec = codec->spec; 3126 spec->multiout.max_channels = 8; 3127 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; 3128 codec->patch_ops.init = nvhdmi_7x_init_8ch; 3129 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; 3130 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; 3131 3132 /* Initialize the audio infoframe channel mask and checksum to something 3133 * valid */ 3134 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3135 3136 return 0; 3137 } 3138 3139 /* 3140 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: 3141 * - 0x10de0015 3142 * - 0x10de0040 3143 */ 3144 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, 3145 struct hdac_cea_channel_speaker_allocation *cap, int channels) 3146 { 3147 if (cap->ca_index == 0x00 && channels == 2) 3148 return SNDRV_CTL_TLVT_CHMAP_FIXED; 3149 3150 /* If the speaker allocation matches the channel count, it is OK. */ 3151 if (cap->channels != channels) 3152 return -1; 3153 3154 /* all channels are remappable freely */ 3155 return SNDRV_CTL_TLVT_CHMAP_VAR; 3156 } 3157 3158 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, 3159 int ca, int chs, unsigned char *map) 3160 { 3161 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) 3162 return -EINVAL; 3163 3164 return 0; 3165 } 3166 3167 static int patch_nvhdmi(struct hda_codec *codec) 3168 { 3169 struct hdmi_spec *spec; 3170 int err; 3171 3172 err = patch_generic_hdmi(codec); 3173 if (err) 3174 return err; 3175 3176 spec = codec->spec; 3177 spec->dyn_pin_out = true; 3178 3179 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3180 nvhdmi_chmap_cea_alloc_validate_get_type; 3181 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3182 3183 return 0; 3184 } 3185 3186 /* 3187 * The HDA codec on NVIDIA Tegra contains two scratch registers that are 3188 * accessed using vendor-defined verbs. These registers can be used for 3189 * interoperability between the HDA and HDMI drivers. 3190 */ 3191 3192 /* Audio Function Group node */ 3193 #define NVIDIA_AFG_NID 0x01 3194 3195 /* 3196 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio 3197 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to 3198 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This 3199 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an 3200 * additional bit (at position 30) to signal the validity of the format. 3201 * 3202 * | 31 | 30 | 29 16 | 15 0 | 3203 * +---------+-------+--------+--------+ 3204 * | TRIGGER | VALID | UNUSED | FORMAT | 3205 * +-----------------------------------| 3206 * 3207 * Note that for the trigger bit to take effect it needs to change value 3208 * (i.e. it needs to be toggled). 3209 */ 3210 #define NVIDIA_GET_SCRATCH0 0xfa6 3211 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 3212 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 3213 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 3214 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa 3215 #define NVIDIA_SCRATCH_TRIGGER (1 << 7) 3216 #define NVIDIA_SCRATCH_VALID (1 << 6) 3217 3218 #define NVIDIA_GET_SCRATCH1 0xfab 3219 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac 3220 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad 3221 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae 3222 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf 3223 3224 /* 3225 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, 3226 * the format is invalidated so that the HDMI codec can be disabled. 3227 */ 3228 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format) 3229 { 3230 unsigned int value; 3231 3232 /* bits [31:30] contain the trigger and valid bits */ 3233 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0, 3234 NVIDIA_GET_SCRATCH0, 0); 3235 value = (value >> 24) & 0xff; 3236 3237 /* bits [15:0] are used to store the HDA format */ 3238 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3239 NVIDIA_SET_SCRATCH0_BYTE0, 3240 (format >> 0) & 0xff); 3241 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3242 NVIDIA_SET_SCRATCH0_BYTE1, 3243 (format >> 8) & 0xff); 3244 3245 /* bits [16:24] are unused */ 3246 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3247 NVIDIA_SET_SCRATCH0_BYTE2, 0); 3248 3249 /* 3250 * Bit 30 signals that the data is valid and hence that HDMI audio can 3251 * be enabled. 3252 */ 3253 if (format == 0) 3254 value &= ~NVIDIA_SCRATCH_VALID; 3255 else 3256 value |= NVIDIA_SCRATCH_VALID; 3257 3258 /* 3259 * Whenever the trigger bit is toggled, an interrupt is raised in the 3260 * HDMI codec. The HDMI driver will use that as trigger to update its 3261 * configuration. 3262 */ 3263 value ^= NVIDIA_SCRATCH_TRIGGER; 3264 3265 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3266 NVIDIA_SET_SCRATCH0_BYTE3, value); 3267 } 3268 3269 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, 3270 struct hda_codec *codec, 3271 unsigned int stream_tag, 3272 unsigned int format, 3273 struct snd_pcm_substream *substream) 3274 { 3275 int err; 3276 3277 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, 3278 format, substream); 3279 if (err < 0) 3280 return err; 3281 3282 /* notify the HDMI codec of the format change */ 3283 tegra_hdmi_set_format(codec, format); 3284 3285 return 0; 3286 } 3287 3288 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, 3289 struct hda_codec *codec, 3290 struct snd_pcm_substream *substream) 3291 { 3292 /* invalidate the format in the HDMI codec */ 3293 tegra_hdmi_set_format(codec, 0); 3294 3295 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); 3296 } 3297 3298 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) 3299 { 3300 struct hdmi_spec *spec = codec->spec; 3301 unsigned int i; 3302 3303 for (i = 0; i < spec->num_pins; i++) { 3304 struct hda_pcm *pcm = get_pcm_rec(spec, i); 3305 3306 if (pcm->pcm_type == type) 3307 return pcm; 3308 } 3309 3310 return NULL; 3311 } 3312 3313 static int tegra_hdmi_build_pcms(struct hda_codec *codec) 3314 { 3315 struct hda_pcm_stream *stream; 3316 struct hda_pcm *pcm; 3317 int err; 3318 3319 err = generic_hdmi_build_pcms(codec); 3320 if (err < 0) 3321 return err; 3322 3323 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); 3324 if (!pcm) 3325 return -ENODEV; 3326 3327 /* 3328 * Override ->prepare() and ->cleanup() operations to notify the HDMI 3329 * codec about format changes. 3330 */ 3331 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3332 stream->ops.prepare = tegra_hdmi_pcm_prepare; 3333 stream->ops.cleanup = tegra_hdmi_pcm_cleanup; 3334 3335 return 0; 3336 } 3337 3338 static int patch_tegra_hdmi(struct hda_codec *codec) 3339 { 3340 int err; 3341 3342 err = patch_generic_hdmi(codec); 3343 if (err) 3344 return err; 3345 3346 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; 3347 3348 return 0; 3349 } 3350 3351 /* 3352 * ATI/AMD-specific implementations 3353 */ 3354 3355 #define is_amdhdmi_rev3_or_later(codec) \ 3356 ((codec)->core.vendor_id == 0x1002aa01 && \ 3357 ((codec)->core.revision_id & 0xff00) >= 0x0300) 3358 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) 3359 3360 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ 3361 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 3362 #define ATI_VERB_SET_DOWNMIX_INFO 0x772 3363 #define ATI_VERB_SET_MULTICHANNEL_01 0x777 3364 #define ATI_VERB_SET_MULTICHANNEL_23 0x778 3365 #define ATI_VERB_SET_MULTICHANNEL_45 0x779 3366 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a 3367 #define ATI_VERB_SET_HBR_CONTROL 0x77c 3368 #define ATI_VERB_SET_MULTICHANNEL_1 0x785 3369 #define ATI_VERB_SET_MULTICHANNEL_3 0x786 3370 #define ATI_VERB_SET_MULTICHANNEL_5 0x787 3371 #define ATI_VERB_SET_MULTICHANNEL_7 0x788 3372 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 3373 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 3374 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 3375 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 3376 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 3377 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 3378 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a 3379 #define ATI_VERB_GET_HBR_CONTROL 0xf7c 3380 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 3381 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 3382 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 3383 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 3384 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 3385 3386 /* AMD specific HDA cvt verbs */ 3387 #define ATI_VERB_SET_RAMP_RATE 0x770 3388 #define ATI_VERB_GET_RAMP_RATE 0xf70 3389 3390 #define ATI_OUT_ENABLE 0x1 3391 3392 #define ATI_MULTICHANNEL_MODE_PAIRED 0 3393 #define ATI_MULTICHANNEL_MODE_SINGLE 1 3394 3395 #define ATI_HBR_CAPABLE 0x01 3396 #define ATI_HBR_ENABLE 0x10 3397 3398 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 3399 unsigned char *buf, int *eld_size) 3400 { 3401 /* call hda_eld.c ATI/AMD-specific function */ 3402 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, 3403 is_amdhdmi_rev3_or_later(codec)); 3404 } 3405 3406 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca, 3407 int active_channels, int conn_type) 3408 { 3409 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); 3410 } 3411 3412 static int atihdmi_paired_swap_fc_lfe(int pos) 3413 { 3414 /* 3415 * ATI/AMD have automatic FC/LFE swap built-in 3416 * when in pairwise mapping mode. 3417 */ 3418 3419 switch (pos) { 3420 /* see channel_allocations[].speakers[] */ 3421 case 2: return 3; 3422 case 3: return 2; 3423 default: break; 3424 } 3425 3426 return pos; 3427 } 3428 3429 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, 3430 int ca, int chs, unsigned char *map) 3431 { 3432 struct hdac_cea_channel_speaker_allocation *cap; 3433 int i, j; 3434 3435 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ 3436 3437 cap = snd_hdac_get_ch_alloc_from_ca(ca); 3438 for (i = 0; i < chs; ++i) { 3439 int mask = snd_hdac_chmap_to_spk_mask(map[i]); 3440 bool ok = false; 3441 bool companion_ok = false; 3442 3443 if (!mask) 3444 continue; 3445 3446 for (j = 0 + i % 2; j < 8; j += 2) { 3447 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); 3448 if (cap->speakers[chan_idx] == mask) { 3449 /* channel is in a supported position */ 3450 ok = true; 3451 3452 if (i % 2 == 0 && i + 1 < chs) { 3453 /* even channel, check the odd companion */ 3454 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); 3455 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); 3456 int comp_mask_act = cap->speakers[comp_chan_idx]; 3457 3458 if (comp_mask_req == comp_mask_act) 3459 companion_ok = true; 3460 else 3461 return -EINVAL; 3462 } 3463 break; 3464 } 3465 } 3466 3467 if (!ok) 3468 return -EINVAL; 3469 3470 if (companion_ok) 3471 i++; /* companion channel already checked */ 3472 } 3473 3474 return 0; 3475 } 3476 3477 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, 3478 hda_nid_t pin_nid, int hdmi_slot, int stream_channel) 3479 { 3480 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 3481 int verb; 3482 int ati_channel_setup = 0; 3483 3484 if (hdmi_slot > 7) 3485 return -EINVAL; 3486 3487 if (!has_amd_full_remap_support(codec)) { 3488 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); 3489 3490 /* In case this is an odd slot but without stream channel, do not 3491 * disable the slot since the corresponding even slot could have a 3492 * channel. In case neither have a channel, the slot pair will be 3493 * disabled when this function is called for the even slot. */ 3494 if (hdmi_slot % 2 != 0 && stream_channel == 0xf) 3495 return 0; 3496 3497 hdmi_slot -= hdmi_slot % 2; 3498 3499 if (stream_channel != 0xf) 3500 stream_channel -= stream_channel % 2; 3501 } 3502 3503 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; 3504 3505 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ 3506 3507 if (stream_channel != 0xf) 3508 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; 3509 3510 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); 3511 } 3512 3513 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, 3514 hda_nid_t pin_nid, int asp_slot) 3515 { 3516 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 3517 bool was_odd = false; 3518 int ati_asp_slot = asp_slot; 3519 int verb; 3520 int ati_channel_setup; 3521 3522 if (asp_slot > 7) 3523 return -EINVAL; 3524 3525 if (!has_amd_full_remap_support(codec)) { 3526 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); 3527 if (ati_asp_slot % 2 != 0) { 3528 ati_asp_slot -= 1; 3529 was_odd = true; 3530 } 3531 } 3532 3533 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; 3534 3535 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); 3536 3537 if (!(ati_channel_setup & ATI_OUT_ENABLE)) 3538 return 0xf; 3539 3540 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; 3541 } 3542 3543 static int atihdmi_paired_chmap_cea_alloc_validate_get_type( 3544 struct hdac_chmap *chmap, 3545 struct hdac_cea_channel_speaker_allocation *cap, 3546 int channels) 3547 { 3548 int c; 3549 3550 /* 3551 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so 3552 * we need to take that into account (a single channel may take 2 3553 * channel slots if we need to carry a silent channel next to it). 3554 * On Rev3+ AMD codecs this function is not used. 3555 */ 3556 int chanpairs = 0; 3557 3558 /* We only produce even-numbered channel count TLVs */ 3559 if ((channels % 2) != 0) 3560 return -1; 3561 3562 for (c = 0; c < 7; c += 2) { 3563 if (cap->speakers[c] || cap->speakers[c+1]) 3564 chanpairs++; 3565 } 3566 3567 if (chanpairs * 2 != channels) 3568 return -1; 3569 3570 return SNDRV_CTL_TLVT_CHMAP_PAIRED; 3571 } 3572 3573 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, 3574 struct hdac_cea_channel_speaker_allocation *cap, 3575 unsigned int *chmap, int channels) 3576 { 3577 /* produce paired maps for pre-rev3 ATI/AMD codecs */ 3578 int count = 0; 3579 int c; 3580 3581 for (c = 7; c >= 0; c--) { 3582 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); 3583 int spk = cap->speakers[chan]; 3584 if (!spk) { 3585 /* add N/A channel if the companion channel is occupied */ 3586 if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) 3587 chmap[count++] = SNDRV_CHMAP_NA; 3588 3589 continue; 3590 } 3591 3592 chmap[count++] = snd_hdac_spk_to_chmap(spk); 3593 } 3594 3595 WARN_ON(count != channels); 3596 } 3597 3598 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 3599 bool hbr) 3600 { 3601 int hbr_ctl, hbr_ctl_new; 3602 3603 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); 3604 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { 3605 if (hbr) 3606 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; 3607 else 3608 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; 3609 3610 codec_dbg(codec, 3611 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", 3612 pin_nid, 3613 hbr_ctl == hbr_ctl_new ? "" : "new-", 3614 hbr_ctl_new); 3615 3616 if (hbr_ctl != hbr_ctl_new) 3617 snd_hda_codec_write(codec, pin_nid, 0, 3618 ATI_VERB_SET_HBR_CONTROL, 3619 hbr_ctl_new); 3620 3621 } else if (hbr) 3622 return -EINVAL; 3623 3624 return 0; 3625 } 3626 3627 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 3628 hda_nid_t pin_nid, u32 stream_tag, int format) 3629 { 3630 3631 if (is_amdhdmi_rev3_or_later(codec)) { 3632 int ramp_rate = 180; /* default as per AMD spec */ 3633 /* disable ramp-up/down for non-pcm as per AMD spec */ 3634 if (format & AC_FMT_TYPE_NON_PCM) 3635 ramp_rate = 0; 3636 3637 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); 3638 } 3639 3640 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format); 3641 } 3642 3643 3644 static int atihdmi_init(struct hda_codec *codec) 3645 { 3646 struct hdmi_spec *spec = codec->spec; 3647 int pin_idx, err; 3648 3649 err = generic_hdmi_init(codec); 3650 3651 if (err) 3652 return err; 3653 3654 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 3655 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 3656 3657 /* make sure downmix information in infoframe is zero */ 3658 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); 3659 3660 /* enable channel-wise remap mode if supported */ 3661 if (has_amd_full_remap_support(codec)) 3662 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 3663 ATI_VERB_SET_MULTICHANNEL_MODE, 3664 ATI_MULTICHANNEL_MODE_SINGLE); 3665 } 3666 3667 return 0; 3668 } 3669 3670 static int patch_atihdmi(struct hda_codec *codec) 3671 { 3672 struct hdmi_spec *spec; 3673 struct hdmi_spec_per_cvt *per_cvt; 3674 int err, cvt_idx; 3675 3676 err = patch_generic_hdmi(codec); 3677 3678 if (err) 3679 return err; 3680 3681 codec->patch_ops.init = atihdmi_init; 3682 3683 spec = codec->spec; 3684 3685 spec->ops.pin_get_eld = atihdmi_pin_get_eld; 3686 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; 3687 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; 3688 spec->ops.setup_stream = atihdmi_setup_stream; 3689 3690 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; 3691 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; 3692 3693 if (!has_amd_full_remap_support(codec)) { 3694 /* override to ATI/AMD-specific versions with pairwise mapping */ 3695 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3696 atihdmi_paired_chmap_cea_alloc_validate_get_type; 3697 spec->chmap.ops.cea_alloc_to_tlv_chmap = 3698 atihdmi_paired_cea_alloc_to_tlv_chmap; 3699 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; 3700 } 3701 3702 /* ATI/AMD converters do not advertise all of their capabilities */ 3703 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 3704 per_cvt = get_cvt(spec, cvt_idx); 3705 per_cvt->channels_max = max(per_cvt->channels_max, 8u); 3706 per_cvt->rates |= SUPPORTED_RATES; 3707 per_cvt->formats |= SUPPORTED_FORMATS; 3708 per_cvt->maxbps = max(per_cvt->maxbps, 24u); 3709 } 3710 3711 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); 3712 3713 return 0; 3714 } 3715 3716 /* VIA HDMI Implementation */ 3717 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ 3718 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ 3719 3720 static int patch_via_hdmi(struct hda_codec *codec) 3721 { 3722 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); 3723 } 3724 3725 /* 3726 * patch entries 3727 */ 3728 static const struct hda_device_id snd_hda_id_hdmi[] = { 3729 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), 3730 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), 3731 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), 3732 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), 3733 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), 3734 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), 3735 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), 3736 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 3737 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 3738 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 3739 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 3740 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), 3741 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi), 3742 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi), 3743 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi), 3744 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi), 3745 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi), 3746 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi), 3747 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi), 3748 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi), 3749 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi), 3750 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi), 3751 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi), 3752 /* 17 is known to be absent */ 3753 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi), 3754 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi), 3755 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi), 3756 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi), 3757 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi), 3758 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), 3759 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), 3760 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), 3761 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), 3762 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), 3763 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), 3764 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), 3765 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), 3766 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), 3767 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), 3768 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), 3769 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), 3770 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), 3771 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), 3772 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), 3773 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), 3774 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), 3775 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), 3776 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), 3777 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), 3778 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), 3779 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), 3780 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), 3781 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), 3782 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), 3783 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), 3784 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), 3785 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), 3786 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), 3787 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), 3788 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), 3789 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), 3790 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), 3791 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), 3792 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), 3793 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), 3794 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), 3795 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), 3796 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), 3797 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), 3798 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), 3799 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), 3800 /* special ID for generic HDMI */ 3801 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), 3802 {} /* terminator */ 3803 }; 3804 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); 3805 3806 MODULE_LICENSE("GPL"); 3807 MODULE_DESCRIPTION("HDMI HD-audio codec"); 3808 MODULE_ALIAS("snd-hda-codec-intelhdmi"); 3809 MODULE_ALIAS("snd-hda-codec-nvhdmi"); 3810 MODULE_ALIAS("snd-hda-codec-atihdmi"); 3811 3812 static struct hda_codec_driver hdmi_driver = { 3813 .id = snd_hda_id_hdmi, 3814 }; 3815 3816 module_hda_codec_driver(hdmi_driver); 3817