1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs 5 * 6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. 7 * Copyright (c) 2006 ATI Technologies Inc. 8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved. 9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com> 10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> 11 * 12 * Authors: 13 * Wu Fengguang <wfg@linux.intel.com> 14 * 15 * Maintained by: 16 * Wu Fengguang <wfg@linux.intel.com> 17 */ 18 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/pci.h> 22 #include <linux/slab.h> 23 #include <linux/module.h> 24 #include <linux/pm_runtime.h> 25 #include <sound/core.h> 26 #include <sound/jack.h> 27 #include <sound/asoundef.h> 28 #include <sound/tlv.h> 29 #include <sound/hdaudio.h> 30 #include <sound/hda_i915.h> 31 #include <sound/hda_chmap.h> 32 #include <sound/hda_codec.h> 33 #include "hda_local.h" 34 #include "hda_jack.h" 35 #include "hda_controller.h" 36 37 static bool static_hdmi_pcm; 38 module_param(static_hdmi_pcm, bool, 0644); 39 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); 40 41 static bool enable_acomp = true; 42 module_param(enable_acomp, bool, 0444); 43 MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)"); 44 45 struct hdmi_spec_per_cvt { 46 hda_nid_t cvt_nid; 47 int assigned; 48 unsigned int channels_min; 49 unsigned int channels_max; 50 u32 rates; 51 u64 formats; 52 unsigned int maxbps; 53 }; 54 55 /* max. connections to a widget */ 56 #define HDA_MAX_CONNECTIONS 32 57 58 struct hdmi_spec_per_pin { 59 hda_nid_t pin_nid; 60 int dev_id; 61 /* pin idx, different device entries on the same pin use the same idx */ 62 int pin_nid_idx; 63 int num_mux_nids; 64 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; 65 int mux_idx; 66 hda_nid_t cvt_nid; 67 68 struct hda_codec *codec; 69 struct hdmi_eld sink_eld; 70 struct mutex lock; 71 struct delayed_work work; 72 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ 73 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ 74 int repoll_count; 75 bool setup; /* the stream has been set up by prepare callback */ 76 int channels; /* current number of channels */ 77 bool non_pcm; 78 bool chmap_set; /* channel-map override by ALSA API? */ 79 unsigned char chmap[8]; /* ALSA API channel-map */ 80 #ifdef CONFIG_SND_PROC_FS 81 struct snd_info_entry *proc_entry; 82 #endif 83 }; 84 85 /* operations used by generic code that can be overridden by patches */ 86 struct hdmi_ops { 87 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, 88 int dev_id, unsigned char *buf, int *eld_size); 89 90 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, 91 int dev_id, 92 int ca, int active_channels, int conn_type); 93 94 /* enable/disable HBR (HD passthrough) */ 95 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, 96 int dev_id, bool hbr); 97 98 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, 99 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 100 int format); 101 102 void (*pin_cvt_fixup)(struct hda_codec *codec, 103 struct hdmi_spec_per_pin *per_pin, 104 hda_nid_t cvt_nid); 105 }; 106 107 struct hdmi_pcm { 108 struct hda_pcm *pcm; 109 struct snd_jack *jack; 110 struct snd_kcontrol *eld_ctl; 111 }; 112 113 struct hdmi_spec { 114 struct hda_codec *codec; 115 int num_cvts; 116 struct snd_array cvts; /* struct hdmi_spec_per_cvt */ 117 hda_nid_t cvt_nids[4]; /* only for haswell fix */ 118 119 /* 120 * num_pins is the number of virtual pins 121 * for example, there are 3 pins, and each pin 122 * has 4 device entries, then the num_pins is 12 123 */ 124 int num_pins; 125 /* 126 * num_nids is the number of real pins 127 * In the above example, num_nids is 3 128 */ 129 int num_nids; 130 /* 131 * dev_num is the number of device entries 132 * on each pin. 133 * In the above example, dev_num is 4 134 */ 135 int dev_num; 136 struct snd_array pins; /* struct hdmi_spec_per_pin */ 137 struct hdmi_pcm pcm_rec[16]; 138 struct mutex pcm_lock; 139 struct mutex bind_lock; /* for audio component binding */ 140 /* pcm_bitmap means which pcms have been assigned to pins*/ 141 unsigned long pcm_bitmap; 142 int pcm_used; /* counter of pcm_rec[] */ 143 /* bitmap shows whether the pcm is opened in user space 144 * bit 0 means the first playback PCM (PCM3); 145 * bit 1 means the second playback PCM, and so on. 146 */ 147 unsigned long pcm_in_use; 148 149 struct hdmi_eld temp_eld; 150 struct hdmi_ops ops; 151 152 bool dyn_pin_out; 153 bool dyn_pcm_assign; 154 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */ 155 /* 156 * Non-generic VIA/NVIDIA specific 157 */ 158 struct hda_multi_out multiout; 159 struct hda_pcm_stream pcm_playback; 160 161 bool use_acomp_notifier; /* use eld_notify callback for hotplug */ 162 bool acomp_registered; /* audio component registered in this driver */ 163 struct drm_audio_component_audio_ops drm_audio_ops; 164 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */ 165 166 struct hdac_chmap chmap; 167 hda_nid_t vendor_nid; 168 const int *port_map; 169 int port_num; 170 }; 171 172 #ifdef CONFIG_SND_HDA_COMPONENT 173 static inline bool codec_has_acomp(struct hda_codec *codec) 174 { 175 struct hdmi_spec *spec = codec->spec; 176 return spec->use_acomp_notifier; 177 } 178 #else 179 #define codec_has_acomp(codec) false 180 #endif 181 182 struct hdmi_audio_infoframe { 183 u8 type; /* 0x84 */ 184 u8 ver; /* 0x01 */ 185 u8 len; /* 0x0a */ 186 187 u8 checksum; 188 189 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ 190 u8 SS01_SF24; 191 u8 CXT04; 192 u8 CA; 193 u8 LFEPBL01_LSV36_DM_INH7; 194 }; 195 196 struct dp_audio_infoframe { 197 u8 type; /* 0x84 */ 198 u8 len; /* 0x1b */ 199 u8 ver; /* 0x11 << 2 */ 200 201 u8 CC02_CT47; /* match with HDMI infoframe from this on */ 202 u8 SS01_SF24; 203 u8 CXT04; 204 u8 CA; 205 u8 LFEPBL01_LSV36_DM_INH7; 206 }; 207 208 union audio_infoframe { 209 struct hdmi_audio_infoframe hdmi; 210 struct dp_audio_infoframe dp; 211 u8 bytes[0]; 212 }; 213 214 /* 215 * HDMI routines 216 */ 217 218 #define get_pin(spec, idx) \ 219 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) 220 #define get_cvt(spec, idx) \ 221 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) 222 /* obtain hdmi_pcm object assigned to idx */ 223 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) 224 /* obtain hda_pcm object assigned to idx */ 225 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) 226 227 static int pin_id_to_pin_index(struct hda_codec *codec, 228 hda_nid_t pin_nid, int dev_id) 229 { 230 struct hdmi_spec *spec = codec->spec; 231 int pin_idx; 232 struct hdmi_spec_per_pin *per_pin; 233 234 /* 235 * (dev_id == -1) means it is NON-MST pin 236 * return the first virtual pin on this port 237 */ 238 if (dev_id == -1) 239 dev_id = 0; 240 241 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 242 per_pin = get_pin(spec, pin_idx); 243 if ((per_pin->pin_nid == pin_nid) && 244 (per_pin->dev_id == dev_id)) 245 return pin_idx; 246 } 247 248 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid); 249 return -EINVAL; 250 } 251 252 static int hinfo_to_pcm_index(struct hda_codec *codec, 253 struct hda_pcm_stream *hinfo) 254 { 255 struct hdmi_spec *spec = codec->spec; 256 int pcm_idx; 257 258 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) 259 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) 260 return pcm_idx; 261 262 codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo); 263 return -EINVAL; 264 } 265 266 static int hinfo_to_pin_index(struct hda_codec *codec, 267 struct hda_pcm_stream *hinfo) 268 { 269 struct hdmi_spec *spec = codec->spec; 270 struct hdmi_spec_per_pin *per_pin; 271 int pin_idx; 272 273 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 274 per_pin = get_pin(spec, pin_idx); 275 if (per_pin->pcm && 276 per_pin->pcm->pcm->stream == hinfo) 277 return pin_idx; 278 } 279 280 codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo, 281 hinfo_to_pcm_index(codec, hinfo)); 282 return -EINVAL; 283 } 284 285 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, 286 int pcm_idx) 287 { 288 int i; 289 struct hdmi_spec_per_pin *per_pin; 290 291 for (i = 0; i < spec->num_pins; i++) { 292 per_pin = get_pin(spec, i); 293 if (per_pin->pcm_idx == pcm_idx) 294 return per_pin; 295 } 296 return NULL; 297 } 298 299 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) 300 { 301 struct hdmi_spec *spec = codec->spec; 302 int cvt_idx; 303 304 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) 305 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) 306 return cvt_idx; 307 308 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid); 309 return -EINVAL; 310 } 311 312 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, 313 struct snd_ctl_elem_info *uinfo) 314 { 315 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 316 struct hdmi_spec *spec = codec->spec; 317 struct hdmi_spec_per_pin *per_pin; 318 struct hdmi_eld *eld; 319 int pcm_idx; 320 321 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 322 323 pcm_idx = kcontrol->private_value; 324 mutex_lock(&spec->pcm_lock); 325 per_pin = pcm_idx_to_pin(spec, pcm_idx); 326 if (!per_pin) { 327 /* no pin is bound to the pcm */ 328 uinfo->count = 0; 329 goto unlock; 330 } 331 eld = &per_pin->sink_eld; 332 uinfo->count = eld->eld_valid ? eld->eld_size : 0; 333 334 unlock: 335 mutex_unlock(&spec->pcm_lock); 336 return 0; 337 } 338 339 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, 340 struct snd_ctl_elem_value *ucontrol) 341 { 342 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 343 struct hdmi_spec *spec = codec->spec; 344 struct hdmi_spec_per_pin *per_pin; 345 struct hdmi_eld *eld; 346 int pcm_idx; 347 int err = 0; 348 349 pcm_idx = kcontrol->private_value; 350 mutex_lock(&spec->pcm_lock); 351 per_pin = pcm_idx_to_pin(spec, pcm_idx); 352 if (!per_pin) { 353 /* no pin is bound to the pcm */ 354 memset(ucontrol->value.bytes.data, 0, 355 ARRAY_SIZE(ucontrol->value.bytes.data)); 356 goto unlock; 357 } 358 359 eld = &per_pin->sink_eld; 360 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || 361 eld->eld_size > ELD_MAX_SIZE) { 362 snd_BUG(); 363 err = -EINVAL; 364 goto unlock; 365 } 366 367 memset(ucontrol->value.bytes.data, 0, 368 ARRAY_SIZE(ucontrol->value.bytes.data)); 369 if (eld->eld_valid) 370 memcpy(ucontrol->value.bytes.data, eld->eld_buffer, 371 eld->eld_size); 372 373 unlock: 374 mutex_unlock(&spec->pcm_lock); 375 return err; 376 } 377 378 static const struct snd_kcontrol_new eld_bytes_ctl = { 379 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE | 380 SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK, 381 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 382 .name = "ELD", 383 .info = hdmi_eld_ctl_info, 384 .get = hdmi_eld_ctl_get, 385 }; 386 387 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, 388 int device) 389 { 390 struct snd_kcontrol *kctl; 391 struct hdmi_spec *spec = codec->spec; 392 int err; 393 394 kctl = snd_ctl_new1(&eld_bytes_ctl, codec); 395 if (!kctl) 396 return -ENOMEM; 397 kctl->private_value = pcm_idx; 398 kctl->id.device = device; 399 400 /* no pin nid is associated with the kctl now 401 * tbd: associate pin nid to eld ctl later 402 */ 403 err = snd_hda_ctl_add(codec, 0, kctl); 404 if (err < 0) 405 return err; 406 407 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; 408 return 0; 409 } 410 411 #ifdef BE_PARANOID 412 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 413 int *packet_index, int *byte_index) 414 { 415 int val; 416 417 val = snd_hda_codec_read(codec, pin_nid, 0, 418 AC_VERB_GET_HDMI_DIP_INDEX, 0); 419 420 *packet_index = val >> 5; 421 *byte_index = val & 0x1f; 422 } 423 #endif 424 425 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 426 int packet_index, int byte_index) 427 { 428 int val; 429 430 val = (packet_index << 5) | (byte_index & 0x1f); 431 432 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); 433 } 434 435 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, 436 unsigned char val) 437 { 438 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); 439 } 440 441 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) 442 { 443 struct hdmi_spec *spec = codec->spec; 444 int pin_out; 445 446 /* Unmute */ 447 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 448 snd_hda_codec_write(codec, pin_nid, 0, 449 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); 450 451 if (spec->dyn_pin_out) 452 /* Disable pin out until stream is active */ 453 pin_out = 0; 454 else 455 /* Enable pin out: some machines with GM965 gets broken output 456 * when the pin is disabled or changed while using with HDMI 457 */ 458 pin_out = PIN_OUT; 459 460 snd_hda_codec_write(codec, pin_nid, 0, 461 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); 462 } 463 464 /* 465 * ELD proc files 466 */ 467 468 #ifdef CONFIG_SND_PROC_FS 469 static void print_eld_info(struct snd_info_entry *entry, 470 struct snd_info_buffer *buffer) 471 { 472 struct hdmi_spec_per_pin *per_pin = entry->private_data; 473 474 mutex_lock(&per_pin->lock); 475 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer); 476 mutex_unlock(&per_pin->lock); 477 } 478 479 static void write_eld_info(struct snd_info_entry *entry, 480 struct snd_info_buffer *buffer) 481 { 482 struct hdmi_spec_per_pin *per_pin = entry->private_data; 483 484 mutex_lock(&per_pin->lock); 485 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); 486 mutex_unlock(&per_pin->lock); 487 } 488 489 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) 490 { 491 char name[32]; 492 struct hda_codec *codec = per_pin->codec; 493 struct snd_info_entry *entry; 494 int err; 495 496 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); 497 err = snd_card_proc_new(codec->card, name, &entry); 498 if (err < 0) 499 return err; 500 501 snd_info_set_text_ops(entry, per_pin, print_eld_info); 502 entry->c.text.write = write_eld_info; 503 entry->mode |= 0200; 504 per_pin->proc_entry = entry; 505 506 return 0; 507 } 508 509 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 510 { 511 if (!per_pin->codec->bus->shutdown) { 512 snd_info_free_entry(per_pin->proc_entry); 513 per_pin->proc_entry = NULL; 514 } 515 } 516 #else 517 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, 518 int index) 519 { 520 return 0; 521 } 522 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 523 { 524 } 525 #endif 526 527 /* 528 * Audio InfoFrame routines 529 */ 530 531 /* 532 * Enable Audio InfoFrame Transmission 533 */ 534 static void hdmi_start_infoframe_trans(struct hda_codec *codec, 535 hda_nid_t pin_nid) 536 { 537 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 538 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 539 AC_DIPXMIT_BEST); 540 } 541 542 /* 543 * Disable Audio InfoFrame Transmission 544 */ 545 static void hdmi_stop_infoframe_trans(struct hda_codec *codec, 546 hda_nid_t pin_nid) 547 { 548 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 549 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 550 AC_DIPXMIT_DISABLE); 551 } 552 553 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) 554 { 555 #ifdef CONFIG_SND_DEBUG_VERBOSE 556 int i; 557 int size; 558 559 size = snd_hdmi_get_eld_size(codec, pin_nid); 560 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); 561 562 for (i = 0; i < 8; i++) { 563 size = snd_hda_codec_read(codec, pin_nid, 0, 564 AC_VERB_GET_HDMI_DIP_SIZE, i); 565 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); 566 } 567 #endif 568 } 569 570 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) 571 { 572 #ifdef BE_PARANOID 573 int i, j; 574 int size; 575 int pi, bi; 576 for (i = 0; i < 8; i++) { 577 size = snd_hda_codec_read(codec, pin_nid, 0, 578 AC_VERB_GET_HDMI_DIP_SIZE, i); 579 if (size == 0) 580 continue; 581 582 hdmi_set_dip_index(codec, pin_nid, i, 0x0); 583 for (j = 1; j < 1000; j++) { 584 hdmi_write_dip_byte(codec, pin_nid, 0x0); 585 hdmi_get_dip_index(codec, pin_nid, &pi, &bi); 586 if (pi != i) 587 codec_dbg(codec, "dip index %d: %d != %d\n", 588 bi, pi, i); 589 if (bi == 0) /* byte index wrapped around */ 590 break; 591 } 592 codec_dbg(codec, 593 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", 594 i, size, j); 595 } 596 #endif 597 } 598 599 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) 600 { 601 u8 *bytes = (u8 *)hdmi_ai; 602 u8 sum = 0; 603 int i; 604 605 hdmi_ai->checksum = 0; 606 607 for (i = 0; i < sizeof(*hdmi_ai); i++) 608 sum += bytes[i]; 609 610 hdmi_ai->checksum = -sum; 611 } 612 613 static void hdmi_fill_audio_infoframe(struct hda_codec *codec, 614 hda_nid_t pin_nid, 615 u8 *dip, int size) 616 { 617 int i; 618 619 hdmi_debug_dip_size(codec, pin_nid); 620 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ 621 622 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 623 for (i = 0; i < size; i++) 624 hdmi_write_dip_byte(codec, pin_nid, dip[i]); 625 } 626 627 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, 628 u8 *dip, int size) 629 { 630 u8 val; 631 int i; 632 633 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) 634 != AC_DIPXMIT_BEST) 635 return false; 636 637 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 638 for (i = 0; i < size; i++) { 639 val = snd_hda_codec_read(codec, pin_nid, 0, 640 AC_VERB_GET_HDMI_DIP_DATA, 0); 641 if (val != dip[i]) 642 return false; 643 } 644 645 return true; 646 } 647 648 static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 649 int dev_id, unsigned char *buf, int *eld_size) 650 { 651 snd_hda_set_dev_select(codec, nid, dev_id); 652 653 return snd_hdmi_get_eld(codec, nid, buf, eld_size); 654 } 655 656 static void hdmi_pin_setup_infoframe(struct hda_codec *codec, 657 hda_nid_t pin_nid, int dev_id, 658 int ca, int active_channels, 659 int conn_type) 660 { 661 union audio_infoframe ai; 662 663 memset(&ai, 0, sizeof(ai)); 664 if (conn_type == 0) { /* HDMI */ 665 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; 666 667 hdmi_ai->type = 0x84; 668 hdmi_ai->ver = 0x01; 669 hdmi_ai->len = 0x0a; 670 hdmi_ai->CC02_CT47 = active_channels - 1; 671 hdmi_ai->CA = ca; 672 hdmi_checksum_audio_infoframe(hdmi_ai); 673 } else if (conn_type == 1) { /* DisplayPort */ 674 struct dp_audio_infoframe *dp_ai = &ai.dp; 675 676 dp_ai->type = 0x84; 677 dp_ai->len = 0x1b; 678 dp_ai->ver = 0x11 << 2; 679 dp_ai->CC02_CT47 = active_channels - 1; 680 dp_ai->CA = ca; 681 } else { 682 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n", 683 pin_nid); 684 return; 685 } 686 687 snd_hda_set_dev_select(codec, pin_nid, dev_id); 688 689 /* 690 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or 691 * sizeof(*dp_ai) to avoid partial match/update problems when 692 * the user switches between HDMI/DP monitors. 693 */ 694 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, 695 sizeof(ai))) { 696 codec_dbg(codec, 697 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n", 698 pin_nid, 699 active_channels, ca); 700 hdmi_stop_infoframe_trans(codec, pin_nid); 701 hdmi_fill_audio_infoframe(codec, pin_nid, 702 ai.bytes, sizeof(ai)); 703 hdmi_start_infoframe_trans(codec, pin_nid); 704 } 705 } 706 707 static void hdmi_setup_audio_infoframe(struct hda_codec *codec, 708 struct hdmi_spec_per_pin *per_pin, 709 bool non_pcm) 710 { 711 struct hdmi_spec *spec = codec->spec; 712 struct hdac_chmap *chmap = &spec->chmap; 713 hda_nid_t pin_nid = per_pin->pin_nid; 714 int dev_id = per_pin->dev_id; 715 int channels = per_pin->channels; 716 int active_channels; 717 struct hdmi_eld *eld; 718 int ca; 719 720 if (!channels) 721 return; 722 723 snd_hda_set_dev_select(codec, pin_nid, dev_id); 724 725 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ 726 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 727 snd_hda_codec_write(codec, pin_nid, 0, 728 AC_VERB_SET_AMP_GAIN_MUTE, 729 AMP_OUT_UNMUTE); 730 731 eld = &per_pin->sink_eld; 732 733 ca = snd_hdac_channel_allocation(&codec->core, 734 eld->info.spk_alloc, channels, 735 per_pin->chmap_set, non_pcm, per_pin->chmap); 736 737 active_channels = snd_hdac_get_active_channels(ca); 738 739 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, 740 active_channels); 741 742 /* 743 * always configure channel mapping, it may have been changed by the 744 * user in the meantime 745 */ 746 snd_hdac_setup_channel_mapping(&spec->chmap, 747 pin_nid, non_pcm, ca, channels, 748 per_pin->chmap, per_pin->chmap_set); 749 750 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id, 751 ca, active_channels, eld->info.conn_type); 752 753 per_pin->non_pcm = non_pcm; 754 } 755 756 /* 757 * Unsolicited events 758 */ 759 760 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); 761 762 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, 763 int dev_id) 764 { 765 struct hdmi_spec *spec = codec->spec; 766 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); 767 768 if (pin_idx < 0) 769 return; 770 mutex_lock(&spec->pcm_lock); 771 hdmi_present_sense(get_pin(spec, pin_idx), 1); 772 mutex_unlock(&spec->pcm_lock); 773 } 774 775 static void jack_callback(struct hda_codec *codec, 776 struct hda_jack_callback *jack) 777 { 778 /* stop polling when notification is enabled */ 779 if (codec_has_acomp(codec)) 780 return; 781 782 check_presence_and_report(codec, jack->nid, jack->dev_id); 783 } 784 785 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res, 786 struct hda_jack_tbl *jack) 787 { 788 jack->jack_dirty = 1; 789 790 codec_dbg(codec, 791 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", 792 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA), 793 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); 794 795 check_presence_and_report(codec, jack->nid, jack->dev_id); 796 } 797 798 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) 799 { 800 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 801 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 802 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); 803 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); 804 805 codec_info(codec, 806 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", 807 codec->addr, 808 tag, 809 subtag, 810 cp_state, 811 cp_ready); 812 813 /* TODO */ 814 if (cp_state) { 815 ; 816 } 817 if (cp_ready) { 818 ; 819 } 820 } 821 822 823 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) 824 { 825 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 826 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 827 struct hda_jack_tbl *jack; 828 829 if (codec_has_acomp(codec)) 830 return; 831 832 if (codec->dp_mst) { 833 int dev_entry = 834 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 835 836 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry); 837 } else { 838 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0); 839 } 840 841 if (!jack) { 842 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); 843 return; 844 } 845 846 if (subtag == 0) 847 hdmi_intrinsic_event(codec, res, jack); 848 else 849 hdmi_non_intrinsic_event(codec, res); 850 } 851 852 static void haswell_verify_D0(struct hda_codec *codec, 853 hda_nid_t cvt_nid, hda_nid_t nid) 854 { 855 int pwr; 856 857 /* For Haswell, the converter 1/2 may keep in D3 state after bootup, 858 * thus pins could only choose converter 0 for use. Make sure the 859 * converters are in correct power state */ 860 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) 861 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); 862 863 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { 864 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, 865 AC_PWRST_D0); 866 msleep(40); 867 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); 868 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; 869 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr); 870 } 871 } 872 873 /* 874 * Callbacks 875 */ 876 877 /* HBR should be Non-PCM, 8 channels */ 878 #define is_hbr_format(format) \ 879 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) 880 881 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 882 int dev_id, bool hbr) 883 { 884 int pinctl, new_pinctl; 885 886 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { 887 snd_hda_set_dev_select(codec, pin_nid, dev_id); 888 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 889 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 890 891 if (pinctl < 0) 892 return hbr ? -EINVAL : 0; 893 894 new_pinctl = pinctl & ~AC_PINCTL_EPT; 895 if (hbr) 896 new_pinctl |= AC_PINCTL_EPT_HBR; 897 else 898 new_pinctl |= AC_PINCTL_EPT_NATIVE; 899 900 codec_dbg(codec, 901 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", 902 pin_nid, 903 pinctl == new_pinctl ? "" : "new-", 904 new_pinctl); 905 906 if (pinctl != new_pinctl) 907 snd_hda_codec_write(codec, pin_nid, 0, 908 AC_VERB_SET_PIN_WIDGET_CONTROL, 909 new_pinctl); 910 } else if (hbr) 911 return -EINVAL; 912 913 return 0; 914 } 915 916 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 917 hda_nid_t pin_nid, int dev_id, 918 u32 stream_tag, int format) 919 { 920 struct hdmi_spec *spec = codec->spec; 921 unsigned int param; 922 int err; 923 924 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id, 925 is_hbr_format(format)); 926 927 if (err) { 928 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); 929 return err; 930 } 931 932 if (spec->intel_hsw_fixup) { 933 934 /* 935 * on recent platforms IEC Coding Type is required for HBR 936 * support, read current Digital Converter settings and set 937 * ICT bitfield if needed. 938 */ 939 param = snd_hda_codec_read(codec, cvt_nid, 0, 940 AC_VERB_GET_DIGI_CONVERT_1, 0); 941 942 param = (param >> 16) & ~(AC_DIG3_ICT); 943 944 /* on recent platforms ICT mode is required for HBR support */ 945 if (is_hbr_format(format)) 946 param |= 0x1; 947 948 snd_hda_codec_write(codec, cvt_nid, 0, 949 AC_VERB_SET_DIGI_CONVERT_3, param); 950 } 951 952 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); 953 return 0; 954 } 955 956 /* Try to find an available converter 957 * If pin_idx is less then zero, just try to find an available converter. 958 * Otherwise, try to find an available converter and get the cvt mux index 959 * of the pin. 960 */ 961 static int hdmi_choose_cvt(struct hda_codec *codec, 962 int pin_idx, int *cvt_id) 963 { 964 struct hdmi_spec *spec = codec->spec; 965 struct hdmi_spec_per_pin *per_pin; 966 struct hdmi_spec_per_cvt *per_cvt = NULL; 967 int cvt_idx, mux_idx = 0; 968 969 /* pin_idx < 0 means no pin will be bound to the converter */ 970 if (pin_idx < 0) 971 per_pin = NULL; 972 else 973 per_pin = get_pin(spec, pin_idx); 974 975 /* Dynamically assign converter to stream */ 976 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 977 per_cvt = get_cvt(spec, cvt_idx); 978 979 /* Must not already be assigned */ 980 if (per_cvt->assigned) 981 continue; 982 if (per_pin == NULL) 983 break; 984 /* Must be in pin's mux's list of converters */ 985 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 986 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) 987 break; 988 /* Not in mux list */ 989 if (mux_idx == per_pin->num_mux_nids) 990 continue; 991 break; 992 } 993 994 /* No free converters */ 995 if (cvt_idx == spec->num_cvts) 996 return -EBUSY; 997 998 if (per_pin != NULL) 999 per_pin->mux_idx = mux_idx; 1000 1001 if (cvt_id) 1002 *cvt_id = cvt_idx; 1003 1004 return 0; 1005 } 1006 1007 /* Assure the pin select the right convetor */ 1008 static void intel_verify_pin_cvt_connect(struct hda_codec *codec, 1009 struct hdmi_spec_per_pin *per_pin) 1010 { 1011 hda_nid_t pin_nid = per_pin->pin_nid; 1012 int mux_idx, curr; 1013 1014 mux_idx = per_pin->mux_idx; 1015 curr = snd_hda_codec_read(codec, pin_nid, 0, 1016 AC_VERB_GET_CONNECT_SEL, 0); 1017 if (curr != mux_idx) 1018 snd_hda_codec_write_cache(codec, pin_nid, 0, 1019 AC_VERB_SET_CONNECT_SEL, 1020 mux_idx); 1021 } 1022 1023 /* get the mux index for the converter of the pins 1024 * converter's mux index is the same for all pins on Intel platform 1025 */ 1026 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, 1027 hda_nid_t cvt_nid) 1028 { 1029 int i; 1030 1031 for (i = 0; i < spec->num_cvts; i++) 1032 if (spec->cvt_nids[i] == cvt_nid) 1033 return i; 1034 return -EINVAL; 1035 } 1036 1037 /* Intel HDMI workaround to fix audio routing issue: 1038 * For some Intel display codecs, pins share the same connection list. 1039 * So a conveter can be selected by multiple pins and playback on any of these 1040 * pins will generate sound on the external display, because audio flows from 1041 * the same converter to the display pipeline. Also muting one pin may make 1042 * other pins have no sound output. 1043 * So this function assures that an assigned converter for a pin is not selected 1044 * by any other pins. 1045 */ 1046 static void intel_not_share_assigned_cvt(struct hda_codec *codec, 1047 hda_nid_t pin_nid, 1048 int dev_id, int mux_idx) 1049 { 1050 struct hdmi_spec *spec = codec->spec; 1051 hda_nid_t nid; 1052 int cvt_idx, curr; 1053 struct hdmi_spec_per_cvt *per_cvt; 1054 struct hdmi_spec_per_pin *per_pin; 1055 int pin_idx; 1056 1057 /* configure the pins connections */ 1058 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 1059 int dev_id_saved; 1060 int dev_num; 1061 1062 per_pin = get_pin(spec, pin_idx); 1063 /* 1064 * pin not connected to monitor 1065 * no need to operate on it 1066 */ 1067 if (!per_pin->pcm) 1068 continue; 1069 1070 if ((per_pin->pin_nid == pin_nid) && 1071 (per_pin->dev_id == dev_id)) 1072 continue; 1073 1074 /* 1075 * if per_pin->dev_id >= dev_num, 1076 * snd_hda_get_dev_select() will fail, 1077 * and the following operation is unpredictable. 1078 * So skip this situation. 1079 */ 1080 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; 1081 if (per_pin->dev_id >= dev_num) 1082 continue; 1083 1084 nid = per_pin->pin_nid; 1085 1086 /* 1087 * Calling this function should not impact 1088 * on the device entry selection 1089 * So let's save the dev id for each pin, 1090 * and restore it when return 1091 */ 1092 dev_id_saved = snd_hda_get_dev_select(codec, nid); 1093 snd_hda_set_dev_select(codec, nid, per_pin->dev_id); 1094 curr = snd_hda_codec_read(codec, nid, 0, 1095 AC_VERB_GET_CONNECT_SEL, 0); 1096 if (curr != mux_idx) { 1097 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1098 continue; 1099 } 1100 1101 1102 /* choose an unassigned converter. The conveters in the 1103 * connection list are in the same order as in the codec. 1104 */ 1105 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1106 per_cvt = get_cvt(spec, cvt_idx); 1107 if (!per_cvt->assigned) { 1108 codec_dbg(codec, 1109 "choose cvt %d for pin nid %d\n", 1110 cvt_idx, nid); 1111 snd_hda_codec_write_cache(codec, nid, 0, 1112 AC_VERB_SET_CONNECT_SEL, 1113 cvt_idx); 1114 break; 1115 } 1116 } 1117 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1118 } 1119 } 1120 1121 /* A wrapper of intel_not_share_asigned_cvt() */ 1122 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, 1123 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) 1124 { 1125 int mux_idx; 1126 struct hdmi_spec *spec = codec->spec; 1127 1128 /* On Intel platform, the mapping of converter nid to 1129 * mux index of the pins are always the same. 1130 * The pin nid may be 0, this means all pins will not 1131 * share the converter. 1132 */ 1133 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); 1134 if (mux_idx >= 0) 1135 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); 1136 } 1137 1138 /* skeleton caller of pin_cvt_fixup ops */ 1139 static void pin_cvt_fixup(struct hda_codec *codec, 1140 struct hdmi_spec_per_pin *per_pin, 1141 hda_nid_t cvt_nid) 1142 { 1143 struct hdmi_spec *spec = codec->spec; 1144 1145 if (spec->ops.pin_cvt_fixup) 1146 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); 1147 } 1148 1149 /* called in hdmi_pcm_open when no pin is assigned to the PCM 1150 * in dyn_pcm_assign mode. 1151 */ 1152 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, 1153 struct hda_codec *codec, 1154 struct snd_pcm_substream *substream) 1155 { 1156 struct hdmi_spec *spec = codec->spec; 1157 struct snd_pcm_runtime *runtime = substream->runtime; 1158 int cvt_idx, pcm_idx; 1159 struct hdmi_spec_per_cvt *per_cvt = NULL; 1160 int err; 1161 1162 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1163 if (pcm_idx < 0) 1164 return -EINVAL; 1165 1166 err = hdmi_choose_cvt(codec, -1, &cvt_idx); 1167 if (err) 1168 return err; 1169 1170 per_cvt = get_cvt(spec, cvt_idx); 1171 per_cvt->assigned = 1; 1172 hinfo->nid = per_cvt->cvt_nid; 1173 1174 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); 1175 1176 set_bit(pcm_idx, &spec->pcm_in_use); 1177 /* todo: setup spdif ctls assign */ 1178 1179 /* Initially set the converter's capabilities */ 1180 hinfo->channels_min = per_cvt->channels_min; 1181 hinfo->channels_max = per_cvt->channels_max; 1182 hinfo->rates = per_cvt->rates; 1183 hinfo->formats = per_cvt->formats; 1184 hinfo->maxbps = per_cvt->maxbps; 1185 1186 /* Store the updated parameters */ 1187 runtime->hw.channels_min = hinfo->channels_min; 1188 runtime->hw.channels_max = hinfo->channels_max; 1189 runtime->hw.formats = hinfo->formats; 1190 runtime->hw.rates = hinfo->rates; 1191 1192 snd_pcm_hw_constraint_step(substream->runtime, 0, 1193 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1194 return 0; 1195 } 1196 1197 /* 1198 * HDA PCM callbacks 1199 */ 1200 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, 1201 struct hda_codec *codec, 1202 struct snd_pcm_substream *substream) 1203 { 1204 struct hdmi_spec *spec = codec->spec; 1205 struct snd_pcm_runtime *runtime = substream->runtime; 1206 int pin_idx, cvt_idx, pcm_idx; 1207 struct hdmi_spec_per_pin *per_pin; 1208 struct hdmi_eld *eld; 1209 struct hdmi_spec_per_cvt *per_cvt = NULL; 1210 int err; 1211 1212 /* Validate hinfo */ 1213 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1214 if (pcm_idx < 0) 1215 return -EINVAL; 1216 1217 mutex_lock(&spec->pcm_lock); 1218 pin_idx = hinfo_to_pin_index(codec, hinfo); 1219 if (!spec->dyn_pcm_assign) { 1220 if (snd_BUG_ON(pin_idx < 0)) { 1221 err = -EINVAL; 1222 goto unlock; 1223 } 1224 } else { 1225 /* no pin is assigned to the PCM 1226 * PA need pcm open successfully when probe 1227 */ 1228 if (pin_idx < 0) { 1229 err = hdmi_pcm_open_no_pin(hinfo, codec, substream); 1230 goto unlock; 1231 } 1232 } 1233 1234 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx); 1235 if (err < 0) 1236 goto unlock; 1237 1238 per_cvt = get_cvt(spec, cvt_idx); 1239 /* Claim converter */ 1240 per_cvt->assigned = 1; 1241 1242 set_bit(pcm_idx, &spec->pcm_in_use); 1243 per_pin = get_pin(spec, pin_idx); 1244 per_pin->cvt_nid = per_cvt->cvt_nid; 1245 hinfo->nid = per_cvt->cvt_nid; 1246 1247 /* flip stripe flag for the assigned stream if supported */ 1248 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE) 1249 azx_stream(get_azx_dev(substream))->stripe = 1; 1250 1251 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1252 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1253 AC_VERB_SET_CONNECT_SEL, 1254 per_pin->mux_idx); 1255 1256 /* configure unused pins to choose other converters */ 1257 pin_cvt_fixup(codec, per_pin, 0); 1258 1259 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); 1260 1261 /* Initially set the converter's capabilities */ 1262 hinfo->channels_min = per_cvt->channels_min; 1263 hinfo->channels_max = per_cvt->channels_max; 1264 hinfo->rates = per_cvt->rates; 1265 hinfo->formats = per_cvt->formats; 1266 hinfo->maxbps = per_cvt->maxbps; 1267 1268 eld = &per_pin->sink_eld; 1269 /* Restrict capabilities by ELD if this isn't disabled */ 1270 if (!static_hdmi_pcm && eld->eld_valid) { 1271 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); 1272 if (hinfo->channels_min > hinfo->channels_max || 1273 !hinfo->rates || !hinfo->formats) { 1274 per_cvt->assigned = 0; 1275 hinfo->nid = 0; 1276 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1277 err = -ENODEV; 1278 goto unlock; 1279 } 1280 } 1281 1282 /* Store the updated parameters */ 1283 runtime->hw.channels_min = hinfo->channels_min; 1284 runtime->hw.channels_max = hinfo->channels_max; 1285 runtime->hw.formats = hinfo->formats; 1286 runtime->hw.rates = hinfo->rates; 1287 1288 snd_pcm_hw_constraint_step(substream->runtime, 0, 1289 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1290 unlock: 1291 mutex_unlock(&spec->pcm_lock); 1292 return err; 1293 } 1294 1295 /* 1296 * HDA/HDMI auto parsing 1297 */ 1298 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) 1299 { 1300 struct hdmi_spec *spec = codec->spec; 1301 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1302 hda_nid_t pin_nid = per_pin->pin_nid; 1303 int dev_id = per_pin->dev_id; 1304 int conns; 1305 1306 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { 1307 codec_warn(codec, 1308 "HDMI: pin %d wcaps %#x does not support connection list\n", 1309 pin_nid, get_wcaps(codec, pin_nid)); 1310 return -EINVAL; 1311 } 1312 1313 snd_hda_set_dev_select(codec, pin_nid, dev_id); 1314 1315 if (spec->intel_hsw_fixup) { 1316 conns = spec->num_cvts; 1317 memcpy(per_pin->mux_nids, spec->cvt_nids, 1318 sizeof(hda_nid_t) * conns); 1319 } else { 1320 conns = snd_hda_get_raw_connections(codec, pin_nid, 1321 per_pin->mux_nids, 1322 HDA_MAX_CONNECTIONS); 1323 } 1324 1325 /* all the device entries on the same pin have the same conn list */ 1326 per_pin->num_mux_nids = conns; 1327 1328 return 0; 1329 } 1330 1331 static int hdmi_find_pcm_slot(struct hdmi_spec *spec, 1332 struct hdmi_spec_per_pin *per_pin) 1333 { 1334 int i; 1335 1336 /* 1337 * generic_hdmi_build_pcms() may allocate extra PCMs on some 1338 * platforms (with maximum of 'num_nids + dev_num - 1') 1339 * 1340 * The per_pin of pin_nid_idx=n and dev_id=m prefers to get pcm-n 1341 * if m==0. This guarantees that dynamic pcm assignments are compatible 1342 * with the legacy static per_pin-pcm assignment that existed in the 1343 * days before DP-MST. 1344 * 1345 * Intel DP-MST prefers this legacy behavior for compatibility, too. 1346 * 1347 * per_pin of m!=0 prefers to get pcm=(num_nids + (m - 1)). 1348 */ 1349 1350 if (per_pin->dev_id == 0 || spec->intel_hsw_fixup) { 1351 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap)) 1352 return per_pin->pin_nid_idx; 1353 } else { 1354 i = spec->num_nids + (per_pin->dev_id - 1); 1355 if (i < spec->pcm_used && !(test_bit(i, &spec->pcm_bitmap))) 1356 return i; 1357 } 1358 1359 /* have a second try; check the area over num_nids */ 1360 for (i = spec->num_nids; i < spec->pcm_used; i++) { 1361 if (!test_bit(i, &spec->pcm_bitmap)) 1362 return i; 1363 } 1364 1365 /* the last try; check the empty slots in pins */ 1366 for (i = 0; i < spec->num_nids; i++) { 1367 if (!test_bit(i, &spec->pcm_bitmap)) 1368 return i; 1369 } 1370 return -EBUSY; 1371 } 1372 1373 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, 1374 struct hdmi_spec_per_pin *per_pin) 1375 { 1376 int idx; 1377 1378 /* pcm already be attached to the pin */ 1379 if (per_pin->pcm) 1380 return; 1381 idx = hdmi_find_pcm_slot(spec, per_pin); 1382 if (idx == -EBUSY) 1383 return; 1384 per_pin->pcm_idx = idx; 1385 per_pin->pcm = get_hdmi_pcm(spec, idx); 1386 set_bit(idx, &spec->pcm_bitmap); 1387 } 1388 1389 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, 1390 struct hdmi_spec_per_pin *per_pin) 1391 { 1392 int idx; 1393 1394 /* pcm already be detached from the pin */ 1395 if (!per_pin->pcm) 1396 return; 1397 idx = per_pin->pcm_idx; 1398 per_pin->pcm_idx = -1; 1399 per_pin->pcm = NULL; 1400 if (idx >= 0 && idx < spec->pcm_used) 1401 clear_bit(idx, &spec->pcm_bitmap); 1402 } 1403 1404 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, 1405 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) 1406 { 1407 int mux_idx; 1408 1409 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1410 if (per_pin->mux_nids[mux_idx] == cvt_nid) 1411 break; 1412 return mux_idx; 1413 } 1414 1415 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); 1416 1417 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, 1418 struct hdmi_spec_per_pin *per_pin) 1419 { 1420 struct hda_codec *codec = per_pin->codec; 1421 struct hda_pcm *pcm; 1422 struct hda_pcm_stream *hinfo; 1423 struct snd_pcm_substream *substream; 1424 int mux_idx; 1425 bool non_pcm; 1426 1427 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1428 pcm = get_pcm_rec(spec, per_pin->pcm_idx); 1429 else 1430 return; 1431 if (!pcm->pcm) 1432 return; 1433 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) 1434 return; 1435 1436 /* hdmi audio only uses playback and one substream */ 1437 hinfo = pcm->stream; 1438 substream = pcm->pcm->streams[0].substream; 1439 1440 per_pin->cvt_nid = hinfo->nid; 1441 1442 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); 1443 if (mux_idx < per_pin->num_mux_nids) { 1444 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1445 per_pin->dev_id); 1446 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1447 AC_VERB_SET_CONNECT_SEL, 1448 mux_idx); 1449 } 1450 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); 1451 1452 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); 1453 if (substream->runtime) 1454 per_pin->channels = substream->runtime->channels; 1455 per_pin->setup = true; 1456 per_pin->mux_idx = mux_idx; 1457 1458 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1459 } 1460 1461 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, 1462 struct hdmi_spec_per_pin *per_pin) 1463 { 1464 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1465 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); 1466 1467 per_pin->chmap_set = false; 1468 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1469 1470 per_pin->setup = false; 1471 per_pin->channels = 0; 1472 } 1473 1474 static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec, 1475 struct hdmi_spec_per_pin *per_pin) 1476 { 1477 struct hdmi_spec *spec = codec->spec; 1478 1479 if (per_pin->pcm_idx >= 0) 1480 return spec->pcm_rec[per_pin->pcm_idx].jack; 1481 else 1482 return NULL; 1483 } 1484 1485 /* update per_pin ELD from the given new ELD; 1486 * setup info frame and notification accordingly 1487 * also notify ELD kctl and report jack status changes 1488 */ 1489 static void update_eld(struct hda_codec *codec, 1490 struct hdmi_spec_per_pin *per_pin, 1491 struct hdmi_eld *eld, 1492 int repoll) 1493 { 1494 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 1495 struct hdmi_spec *spec = codec->spec; 1496 struct snd_jack *pcm_jack; 1497 bool old_eld_valid = pin_eld->eld_valid; 1498 bool eld_changed; 1499 int pcm_idx; 1500 1501 if (eld->eld_valid) { 1502 if (eld->eld_size <= 0 || 1503 snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, 1504 eld->eld_size) < 0) { 1505 eld->eld_valid = false; 1506 if (repoll) { 1507 schedule_delayed_work(&per_pin->work, 1508 msecs_to_jiffies(300)); 1509 return; 1510 } 1511 } 1512 } 1513 1514 if (!eld->eld_valid || eld->eld_size <= 0) { 1515 eld->eld_valid = false; 1516 eld->eld_size = 0; 1517 } 1518 1519 /* for monitor disconnection, save pcm_idx firstly */ 1520 pcm_idx = per_pin->pcm_idx; 1521 1522 /* 1523 * pcm_idx >=0 before update_eld() means it is in monitor 1524 * disconnected event. Jack must be fetched before update_eld(). 1525 */ 1526 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); 1527 1528 if (spec->dyn_pcm_assign) { 1529 if (eld->eld_valid) { 1530 hdmi_attach_hda_pcm(spec, per_pin); 1531 hdmi_pcm_setup_pin(spec, per_pin); 1532 } else { 1533 hdmi_pcm_reset_pin(spec, per_pin); 1534 hdmi_detach_hda_pcm(spec, per_pin); 1535 } 1536 } 1537 /* if pcm_idx == -1, it means this is in monitor connection event 1538 * we can get the correct pcm_idx now. 1539 */ 1540 if (pcm_idx == -1) 1541 pcm_idx = per_pin->pcm_idx; 1542 if (!pcm_jack) 1543 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); 1544 1545 if (eld->eld_valid) 1546 snd_hdmi_show_eld(codec, &eld->info); 1547 1548 eld_changed = (pin_eld->eld_valid != eld->eld_valid); 1549 eld_changed |= (pin_eld->monitor_present != eld->monitor_present); 1550 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid) 1551 if (pin_eld->eld_size != eld->eld_size || 1552 memcmp(pin_eld->eld_buffer, eld->eld_buffer, 1553 eld->eld_size) != 0) 1554 eld_changed = true; 1555 1556 if (eld_changed) { 1557 pin_eld->monitor_present = eld->monitor_present; 1558 pin_eld->eld_valid = eld->eld_valid; 1559 pin_eld->eld_size = eld->eld_size; 1560 if (eld->eld_valid) 1561 memcpy(pin_eld->eld_buffer, eld->eld_buffer, 1562 eld->eld_size); 1563 pin_eld->info = eld->info; 1564 } 1565 1566 /* 1567 * Re-setup pin and infoframe. This is needed e.g. when 1568 * - sink is first plugged-in 1569 * - transcoder can change during stream playback on Haswell 1570 * and this can make HW reset converter selection on a pin. 1571 */ 1572 if (eld->eld_valid && !old_eld_valid && per_pin->setup) { 1573 pin_cvt_fixup(codec, per_pin, 0); 1574 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1575 } 1576 1577 if (eld_changed && pcm_idx >= 0) 1578 snd_ctl_notify(codec->card, 1579 SNDRV_CTL_EVENT_MASK_VALUE | 1580 SNDRV_CTL_EVENT_MASK_INFO, 1581 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); 1582 1583 if (eld_changed && pcm_jack) 1584 snd_jack_report(pcm_jack, 1585 (eld->monitor_present && eld->eld_valid) ? 1586 SND_JACK_AVOUT : 0); 1587 } 1588 1589 /* update ELD and jack state via HD-audio verbs */ 1590 static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, 1591 int repoll) 1592 { 1593 struct hda_codec *codec = per_pin->codec; 1594 struct hdmi_spec *spec = codec->spec; 1595 struct hdmi_eld *eld = &spec->temp_eld; 1596 hda_nid_t pin_nid = per_pin->pin_nid; 1597 int dev_id = per_pin->dev_id; 1598 /* 1599 * Always execute a GetPinSense verb here, even when called from 1600 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited 1601 * response's PD bit is not the real PD value, but indicates that 1602 * the real PD value changed. An older version of the HD-audio 1603 * specification worked this way. Hence, we just ignore the data in 1604 * the unsolicited response to avoid custom WARs. 1605 */ 1606 int present; 1607 int ret; 1608 1609 ret = snd_hda_power_up_pm(codec); 1610 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) 1611 goto out; 1612 1613 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id); 1614 1615 mutex_lock(&per_pin->lock); 1616 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); 1617 if (eld->monitor_present) 1618 eld->eld_valid = !!(present & AC_PINSENSE_ELDV); 1619 else 1620 eld->eld_valid = false; 1621 1622 codec_dbg(codec, 1623 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n", 1624 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); 1625 1626 if (eld->eld_valid) { 1627 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id, 1628 eld->eld_buffer, &eld->eld_size) < 0) 1629 eld->eld_valid = false; 1630 } 1631 1632 update_eld(codec, per_pin, eld, repoll); 1633 mutex_unlock(&per_pin->lock); 1634 out: 1635 snd_hda_power_down_pm(codec); 1636 } 1637 1638 /* update ELD and jack state via audio component */ 1639 static void sync_eld_via_acomp(struct hda_codec *codec, 1640 struct hdmi_spec_per_pin *per_pin) 1641 { 1642 struct hdmi_spec *spec = codec->spec; 1643 struct hdmi_eld *eld = &spec->temp_eld; 1644 1645 mutex_lock(&per_pin->lock); 1646 eld->monitor_present = false; 1647 eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, 1648 per_pin->dev_id, &eld->monitor_present, 1649 eld->eld_buffer, ELD_MAX_SIZE); 1650 eld->eld_valid = (eld->eld_size > 0); 1651 update_eld(codec, per_pin, eld, 0); 1652 mutex_unlock(&per_pin->lock); 1653 } 1654 1655 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) 1656 { 1657 struct hda_codec *codec = per_pin->codec; 1658 1659 if (!codec_has_acomp(codec)) 1660 hdmi_present_sense_via_verbs(per_pin, repoll); 1661 else 1662 sync_eld_via_acomp(codec, per_pin); 1663 } 1664 1665 static void hdmi_repoll_eld(struct work_struct *work) 1666 { 1667 struct hdmi_spec_per_pin *per_pin = 1668 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); 1669 struct hda_codec *codec = per_pin->codec; 1670 struct hdmi_spec *spec = codec->spec; 1671 struct hda_jack_tbl *jack; 1672 1673 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid, 1674 per_pin->dev_id); 1675 if (jack) 1676 jack->jack_dirty = 1; 1677 1678 if (per_pin->repoll_count++ > 6) 1679 per_pin->repoll_count = 0; 1680 1681 mutex_lock(&spec->pcm_lock); 1682 hdmi_present_sense(per_pin, per_pin->repoll_count); 1683 mutex_unlock(&spec->pcm_lock); 1684 } 1685 1686 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) 1687 { 1688 struct hdmi_spec *spec = codec->spec; 1689 unsigned int caps, config; 1690 int pin_idx; 1691 struct hdmi_spec_per_pin *per_pin; 1692 int err; 1693 int dev_num, i; 1694 1695 caps = snd_hda_query_pin_caps(codec, pin_nid); 1696 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) 1697 return 0; 1698 1699 /* 1700 * For DP MST audio, Configuration Default is the same for 1701 * all device entries on the same pin 1702 */ 1703 config = snd_hda_codec_get_pincfg(codec, pin_nid); 1704 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE) 1705 return 0; 1706 1707 /* 1708 * To simplify the implementation, malloc all 1709 * the virtual pins in the initialization statically 1710 */ 1711 if (spec->intel_hsw_fixup) { 1712 /* 1713 * On Intel platforms, device entries number is 1714 * changed dynamically. If there is a DP MST 1715 * hub connected, the device entries number is 3. 1716 * Otherwise, it is 1. 1717 * Here we manually set dev_num to 3, so that 1718 * we can initialize all the device entries when 1719 * bootup statically. 1720 */ 1721 dev_num = 3; 1722 spec->dev_num = 3; 1723 } else if (spec->dyn_pcm_assign && codec->dp_mst) { 1724 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; 1725 /* 1726 * spec->dev_num is the maxinum number of device entries 1727 * among all the pins 1728 */ 1729 spec->dev_num = (spec->dev_num > dev_num) ? 1730 spec->dev_num : dev_num; 1731 } else { 1732 /* 1733 * If the platform doesn't support DP MST, 1734 * manually set dev_num to 1. This means 1735 * the pin has only one device entry. 1736 */ 1737 dev_num = 1; 1738 spec->dev_num = 1; 1739 } 1740 1741 for (i = 0; i < dev_num; i++) { 1742 pin_idx = spec->num_pins; 1743 per_pin = snd_array_new(&spec->pins); 1744 1745 if (!per_pin) 1746 return -ENOMEM; 1747 1748 if (spec->dyn_pcm_assign) { 1749 per_pin->pcm = NULL; 1750 per_pin->pcm_idx = -1; 1751 } else { 1752 per_pin->pcm = get_hdmi_pcm(spec, pin_idx); 1753 per_pin->pcm_idx = pin_idx; 1754 } 1755 per_pin->pin_nid = pin_nid; 1756 per_pin->pin_nid_idx = spec->num_nids; 1757 per_pin->dev_id = i; 1758 per_pin->non_pcm = false; 1759 snd_hda_set_dev_select(codec, pin_nid, i); 1760 err = hdmi_read_pin_conn(codec, pin_idx); 1761 if (err < 0) 1762 return err; 1763 spec->num_pins++; 1764 } 1765 spec->num_nids++; 1766 1767 return 0; 1768 } 1769 1770 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1771 { 1772 struct hdmi_spec *spec = codec->spec; 1773 struct hdmi_spec_per_cvt *per_cvt; 1774 unsigned int chans; 1775 int err; 1776 1777 chans = get_wcaps(codec, cvt_nid); 1778 chans = get_wcaps_channels(chans); 1779 1780 per_cvt = snd_array_new(&spec->cvts); 1781 if (!per_cvt) 1782 return -ENOMEM; 1783 1784 per_cvt->cvt_nid = cvt_nid; 1785 per_cvt->channels_min = 2; 1786 if (chans <= 16) { 1787 per_cvt->channels_max = chans; 1788 if (chans > spec->chmap.channels_max) 1789 spec->chmap.channels_max = chans; 1790 } 1791 1792 err = snd_hda_query_supported_pcm(codec, cvt_nid, 1793 &per_cvt->rates, 1794 &per_cvt->formats, 1795 &per_cvt->maxbps); 1796 if (err < 0) 1797 return err; 1798 1799 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) 1800 spec->cvt_nids[spec->num_cvts] = cvt_nid; 1801 spec->num_cvts++; 1802 1803 return 0; 1804 } 1805 1806 static int hdmi_parse_codec(struct hda_codec *codec) 1807 { 1808 hda_nid_t start_nid; 1809 unsigned int caps; 1810 int i, nodes; 1811 1812 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid); 1813 if (!start_nid || nodes < 0) { 1814 codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); 1815 return -EINVAL; 1816 } 1817 1818 /* 1819 * hdmi_add_pin() assumes total amount of converters to 1820 * be known, so first discover all converters 1821 */ 1822 for (i = 0; i < nodes; i++) { 1823 hda_nid_t nid = start_nid + i; 1824 1825 caps = get_wcaps(codec, nid); 1826 1827 if (!(caps & AC_WCAP_DIGITAL)) 1828 continue; 1829 1830 if (get_wcaps_type(caps) == AC_WID_AUD_OUT) 1831 hdmi_add_cvt(codec, nid); 1832 } 1833 1834 /* discover audio pins */ 1835 for (i = 0; i < nodes; i++) { 1836 hda_nid_t nid = start_nid + i; 1837 1838 caps = get_wcaps(codec, nid); 1839 1840 if (!(caps & AC_WCAP_DIGITAL)) 1841 continue; 1842 1843 if (get_wcaps_type(caps) == AC_WID_PIN) 1844 hdmi_add_pin(codec, nid); 1845 } 1846 1847 return 0; 1848 } 1849 1850 /* 1851 */ 1852 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1853 { 1854 struct hda_spdif_out *spdif; 1855 bool non_pcm; 1856 1857 mutex_lock(&codec->spdif_mutex); 1858 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); 1859 /* Add sanity check to pass klockwork check. 1860 * This should never happen. 1861 */ 1862 if (WARN_ON(spdif == NULL)) { 1863 mutex_unlock(&codec->spdif_mutex); 1864 return true; 1865 } 1866 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); 1867 mutex_unlock(&codec->spdif_mutex); 1868 return non_pcm; 1869 } 1870 1871 /* 1872 * HDMI callbacks 1873 */ 1874 1875 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 1876 struct hda_codec *codec, 1877 unsigned int stream_tag, 1878 unsigned int format, 1879 struct snd_pcm_substream *substream) 1880 { 1881 hda_nid_t cvt_nid = hinfo->nid; 1882 struct hdmi_spec *spec = codec->spec; 1883 int pin_idx; 1884 struct hdmi_spec_per_pin *per_pin; 1885 struct snd_pcm_runtime *runtime = substream->runtime; 1886 bool non_pcm; 1887 int pinctl, stripe; 1888 int err = 0; 1889 1890 mutex_lock(&spec->pcm_lock); 1891 pin_idx = hinfo_to_pin_index(codec, hinfo); 1892 if (spec->dyn_pcm_assign && pin_idx < 0) { 1893 /* when dyn_pcm_assign and pcm is not bound to a pin 1894 * skip pin setup and return 0 to make audio playback 1895 * be ongoing 1896 */ 1897 pin_cvt_fixup(codec, NULL, cvt_nid); 1898 snd_hda_codec_setup_stream(codec, cvt_nid, 1899 stream_tag, 0, format); 1900 goto unlock; 1901 } 1902 1903 if (snd_BUG_ON(pin_idx < 0)) { 1904 err = -EINVAL; 1905 goto unlock; 1906 } 1907 per_pin = get_pin(spec, pin_idx); 1908 1909 /* Verify pin:cvt selections to avoid silent audio after S3. 1910 * After S3, the audio driver restores pin:cvt selections 1911 * but this can happen before gfx is ready and such selection 1912 * is overlooked by HW. Thus multiple pins can share a same 1913 * default convertor and mute control will affect each other, 1914 * which can cause a resumed audio playback become silent 1915 * after S3. 1916 */ 1917 pin_cvt_fixup(codec, per_pin, 0); 1918 1919 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ 1920 /* Todo: add DP1.2 MST audio support later */ 1921 if (codec_has_acomp(codec)) 1922 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, 1923 per_pin->dev_id, runtime->rate); 1924 1925 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); 1926 mutex_lock(&per_pin->lock); 1927 per_pin->channels = substream->runtime->channels; 1928 per_pin->setup = true; 1929 1930 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) { 1931 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core, 1932 substream); 1933 snd_hda_codec_write(codec, cvt_nid, 0, 1934 AC_VERB_SET_STRIPE_CONTROL, 1935 stripe); 1936 } 1937 1938 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1939 mutex_unlock(&per_pin->lock); 1940 if (spec->dyn_pin_out) { 1941 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1942 per_pin->dev_id); 1943 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 1944 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 1945 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 1946 AC_VERB_SET_PIN_WIDGET_CONTROL, 1947 pinctl | PIN_OUT); 1948 } 1949 1950 /* snd_hda_set_dev_select() has been called before */ 1951 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid, 1952 per_pin->dev_id, stream_tag, format); 1953 unlock: 1954 mutex_unlock(&spec->pcm_lock); 1955 return err; 1956 } 1957 1958 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 1959 struct hda_codec *codec, 1960 struct snd_pcm_substream *substream) 1961 { 1962 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 1963 return 0; 1964 } 1965 1966 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, 1967 struct hda_codec *codec, 1968 struct snd_pcm_substream *substream) 1969 { 1970 struct hdmi_spec *spec = codec->spec; 1971 int cvt_idx, pin_idx, pcm_idx; 1972 struct hdmi_spec_per_cvt *per_cvt; 1973 struct hdmi_spec_per_pin *per_pin; 1974 int pinctl; 1975 int err = 0; 1976 1977 if (hinfo->nid) { 1978 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1979 if (snd_BUG_ON(pcm_idx < 0)) 1980 return -EINVAL; 1981 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); 1982 if (snd_BUG_ON(cvt_idx < 0)) 1983 return -EINVAL; 1984 per_cvt = get_cvt(spec, cvt_idx); 1985 1986 snd_BUG_ON(!per_cvt->assigned); 1987 per_cvt->assigned = 0; 1988 hinfo->nid = 0; 1989 1990 azx_stream(get_azx_dev(substream))->stripe = 0; 1991 1992 mutex_lock(&spec->pcm_lock); 1993 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1994 clear_bit(pcm_idx, &spec->pcm_in_use); 1995 pin_idx = hinfo_to_pin_index(codec, hinfo); 1996 if (spec->dyn_pcm_assign && pin_idx < 0) 1997 goto unlock; 1998 1999 if (snd_BUG_ON(pin_idx < 0)) { 2000 err = -EINVAL; 2001 goto unlock; 2002 } 2003 per_pin = get_pin(spec, pin_idx); 2004 2005 if (spec->dyn_pin_out) { 2006 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2007 per_pin->dev_id); 2008 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2009 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2010 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2011 AC_VERB_SET_PIN_WIDGET_CONTROL, 2012 pinctl & ~PIN_OUT); 2013 } 2014 2015 mutex_lock(&per_pin->lock); 2016 per_pin->chmap_set = false; 2017 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 2018 2019 per_pin->setup = false; 2020 per_pin->channels = 0; 2021 mutex_unlock(&per_pin->lock); 2022 unlock: 2023 mutex_unlock(&spec->pcm_lock); 2024 } 2025 2026 return err; 2027 } 2028 2029 static const struct hda_pcm_ops generic_ops = { 2030 .open = hdmi_pcm_open, 2031 .close = hdmi_pcm_close, 2032 .prepare = generic_hdmi_playback_pcm_prepare, 2033 .cleanup = generic_hdmi_playback_pcm_cleanup, 2034 }; 2035 2036 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) 2037 { 2038 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2039 struct hdmi_spec *spec = codec->spec; 2040 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2041 2042 if (!per_pin) 2043 return 0; 2044 2045 return per_pin->sink_eld.info.spk_alloc; 2046 } 2047 2048 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, 2049 unsigned char *chmap) 2050 { 2051 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2052 struct hdmi_spec *spec = codec->spec; 2053 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2054 2055 /* chmap is already set to 0 in caller */ 2056 if (!per_pin) 2057 return; 2058 2059 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); 2060 } 2061 2062 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, 2063 unsigned char *chmap, int prepared) 2064 { 2065 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2066 struct hdmi_spec *spec = codec->spec; 2067 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2068 2069 if (!per_pin) 2070 return; 2071 mutex_lock(&per_pin->lock); 2072 per_pin->chmap_set = true; 2073 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); 2074 if (prepared) 2075 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 2076 mutex_unlock(&per_pin->lock); 2077 } 2078 2079 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) 2080 { 2081 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2082 struct hdmi_spec *spec = codec->spec; 2083 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2084 2085 return per_pin ? true:false; 2086 } 2087 2088 static int generic_hdmi_build_pcms(struct hda_codec *codec) 2089 { 2090 struct hdmi_spec *spec = codec->spec; 2091 int idx, pcm_num; 2092 2093 /* 2094 * for non-mst mode, pcm number is the same as before 2095 * for DP MST mode without extra PCM, pcm number is same 2096 * for DP MST mode with extra PCMs, pcm number is 2097 * (nid number + dev_num - 1) 2098 * dev_num is the device entry number in a pin 2099 */ 2100 2101 if (codec->mst_no_extra_pcms) 2102 pcm_num = spec->num_nids; 2103 else 2104 pcm_num = spec->num_nids + spec->dev_num - 1; 2105 2106 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num); 2107 2108 for (idx = 0; idx < pcm_num; idx++) { 2109 struct hda_pcm *info; 2110 struct hda_pcm_stream *pstr; 2111 2112 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); 2113 if (!info) 2114 return -ENOMEM; 2115 2116 spec->pcm_rec[idx].pcm = info; 2117 spec->pcm_used++; 2118 info->pcm_type = HDA_PCM_TYPE_HDMI; 2119 info->own_chmap = true; 2120 2121 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2122 pstr->substreams = 1; 2123 pstr->ops = generic_ops; 2124 /* pcm number is less than 16 */ 2125 if (spec->pcm_used >= 16) 2126 break; 2127 /* other pstr fields are set in open */ 2128 } 2129 2130 return 0; 2131 } 2132 2133 static void free_hdmi_jack_priv(struct snd_jack *jack) 2134 { 2135 struct hdmi_pcm *pcm = jack->private_data; 2136 2137 pcm->jack = NULL; 2138 } 2139 2140 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) 2141 { 2142 char hdmi_str[32] = "HDMI/DP"; 2143 struct hdmi_spec *spec = codec->spec; 2144 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pcm_idx); 2145 struct snd_jack *jack; 2146 int pcmdev = get_pcm_rec(spec, pcm_idx)->device; 2147 int err; 2148 2149 if (pcmdev > 0) 2150 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); 2151 if (!spec->dyn_pcm_assign && 2152 !is_jack_detectable(codec, per_pin->pin_nid)) 2153 strncat(hdmi_str, " Phantom", 2154 sizeof(hdmi_str) - strlen(hdmi_str) - 1); 2155 2156 err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack, 2157 true, false); 2158 if (err < 0) 2159 return err; 2160 2161 spec->pcm_rec[pcm_idx].jack = jack; 2162 jack->private_data = &spec->pcm_rec[pcm_idx]; 2163 jack->private_free = free_hdmi_jack_priv; 2164 return 0; 2165 } 2166 2167 static int generic_hdmi_build_controls(struct hda_codec *codec) 2168 { 2169 struct hdmi_spec *spec = codec->spec; 2170 int dev, err; 2171 int pin_idx, pcm_idx; 2172 2173 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2174 if (!get_pcm_rec(spec, pcm_idx)->pcm) { 2175 /* no PCM: mark this for skipping permanently */ 2176 set_bit(pcm_idx, &spec->pcm_bitmap); 2177 continue; 2178 } 2179 2180 err = generic_hdmi_build_jack(codec, pcm_idx); 2181 if (err < 0) 2182 return err; 2183 2184 /* create the spdif for each pcm 2185 * pin will be bound when monitor is connected 2186 */ 2187 if (spec->dyn_pcm_assign) 2188 err = snd_hda_create_dig_out_ctls(codec, 2189 0, spec->cvt_nids[0], 2190 HDA_PCM_TYPE_HDMI); 2191 else { 2192 struct hdmi_spec_per_pin *per_pin = 2193 get_pin(spec, pcm_idx); 2194 err = snd_hda_create_dig_out_ctls(codec, 2195 per_pin->pin_nid, 2196 per_pin->mux_nids[0], 2197 HDA_PCM_TYPE_HDMI); 2198 } 2199 if (err < 0) 2200 return err; 2201 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2202 2203 dev = get_pcm_rec(spec, pcm_idx)->device; 2204 if (dev != SNDRV_PCM_INVALID_DEVICE) { 2205 /* add control for ELD Bytes */ 2206 err = hdmi_create_eld_ctl(codec, pcm_idx, dev); 2207 if (err < 0) 2208 return err; 2209 } 2210 } 2211 2212 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2213 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2214 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 2215 2216 pin_eld->eld_valid = false; 2217 hdmi_present_sense(per_pin, 0); 2218 } 2219 2220 /* add channel maps */ 2221 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2222 struct hda_pcm *pcm; 2223 2224 pcm = get_pcm_rec(spec, pcm_idx); 2225 if (!pcm || !pcm->pcm) 2226 break; 2227 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); 2228 if (err < 0) 2229 return err; 2230 } 2231 2232 return 0; 2233 } 2234 2235 static int generic_hdmi_init_per_pins(struct hda_codec *codec) 2236 { 2237 struct hdmi_spec *spec = codec->spec; 2238 int pin_idx; 2239 2240 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2241 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2242 2243 per_pin->codec = codec; 2244 mutex_init(&per_pin->lock); 2245 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); 2246 eld_proc_new(per_pin, pin_idx); 2247 } 2248 return 0; 2249 } 2250 2251 static int generic_hdmi_init(struct hda_codec *codec) 2252 { 2253 struct hdmi_spec *spec = codec->spec; 2254 int pin_idx; 2255 2256 mutex_lock(&spec->bind_lock); 2257 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2258 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2259 hda_nid_t pin_nid = per_pin->pin_nid; 2260 int dev_id = per_pin->dev_id; 2261 2262 snd_hda_set_dev_select(codec, pin_nid, dev_id); 2263 hdmi_init_pin(codec, pin_nid); 2264 if (codec_has_acomp(codec)) 2265 continue; 2266 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id, 2267 jack_callback); 2268 } 2269 mutex_unlock(&spec->bind_lock); 2270 return 0; 2271 } 2272 2273 static void hdmi_array_init(struct hdmi_spec *spec, int nums) 2274 { 2275 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); 2276 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); 2277 } 2278 2279 static void hdmi_array_free(struct hdmi_spec *spec) 2280 { 2281 snd_array_free(&spec->pins); 2282 snd_array_free(&spec->cvts); 2283 } 2284 2285 static void generic_spec_free(struct hda_codec *codec) 2286 { 2287 struct hdmi_spec *spec = codec->spec; 2288 2289 if (spec) { 2290 hdmi_array_free(spec); 2291 kfree(spec); 2292 codec->spec = NULL; 2293 } 2294 codec->dp_mst = false; 2295 } 2296 2297 static void generic_hdmi_free(struct hda_codec *codec) 2298 { 2299 struct hdmi_spec *spec = codec->spec; 2300 int pin_idx, pcm_idx; 2301 2302 if (spec->acomp_registered) { 2303 snd_hdac_acomp_exit(&codec->bus->core); 2304 } else if (codec_has_acomp(codec)) { 2305 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL); 2306 } 2307 codec->relaxed_resume = 0; 2308 2309 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2310 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2311 cancel_delayed_work_sync(&per_pin->work); 2312 eld_proc_free(per_pin); 2313 } 2314 2315 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2316 if (spec->pcm_rec[pcm_idx].jack == NULL) 2317 continue; 2318 if (spec->dyn_pcm_assign) 2319 snd_device_free(codec->card, 2320 spec->pcm_rec[pcm_idx].jack); 2321 else 2322 spec->pcm_rec[pcm_idx].jack = NULL; 2323 } 2324 2325 generic_spec_free(codec); 2326 } 2327 2328 #ifdef CONFIG_PM 2329 static int generic_hdmi_resume(struct hda_codec *codec) 2330 { 2331 struct hdmi_spec *spec = codec->spec; 2332 int pin_idx; 2333 2334 codec->patch_ops.init(codec); 2335 snd_hda_regmap_sync(codec); 2336 2337 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2338 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2339 hdmi_present_sense(per_pin, 1); 2340 } 2341 return 0; 2342 } 2343 #endif 2344 2345 static const struct hda_codec_ops generic_hdmi_patch_ops = { 2346 .init = generic_hdmi_init, 2347 .free = generic_hdmi_free, 2348 .build_pcms = generic_hdmi_build_pcms, 2349 .build_controls = generic_hdmi_build_controls, 2350 .unsol_event = hdmi_unsol_event, 2351 #ifdef CONFIG_PM 2352 .resume = generic_hdmi_resume, 2353 #endif 2354 }; 2355 2356 static const struct hdmi_ops generic_standard_hdmi_ops = { 2357 .pin_get_eld = hdmi_pin_get_eld, 2358 .pin_setup_infoframe = hdmi_pin_setup_infoframe, 2359 .pin_hbr_setup = hdmi_pin_hbr_setup, 2360 .setup_stream = hdmi_setup_stream, 2361 }; 2362 2363 /* allocate codec->spec and assign/initialize generic parser ops */ 2364 static int alloc_generic_hdmi(struct hda_codec *codec) 2365 { 2366 struct hdmi_spec *spec; 2367 2368 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2369 if (!spec) 2370 return -ENOMEM; 2371 2372 spec->codec = codec; 2373 spec->ops = generic_standard_hdmi_ops; 2374 spec->dev_num = 1; /* initialize to 1 */ 2375 mutex_init(&spec->pcm_lock); 2376 mutex_init(&spec->bind_lock); 2377 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); 2378 2379 spec->chmap.ops.get_chmap = hdmi_get_chmap; 2380 spec->chmap.ops.set_chmap = hdmi_set_chmap; 2381 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; 2382 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc, 2383 2384 codec->spec = spec; 2385 hdmi_array_init(spec, 4); 2386 2387 codec->patch_ops = generic_hdmi_patch_ops; 2388 2389 return 0; 2390 } 2391 2392 /* generic HDMI parser */ 2393 static int patch_generic_hdmi(struct hda_codec *codec) 2394 { 2395 int err; 2396 2397 err = alloc_generic_hdmi(codec); 2398 if (err < 0) 2399 return err; 2400 2401 err = hdmi_parse_codec(codec); 2402 if (err < 0) { 2403 generic_spec_free(codec); 2404 return err; 2405 } 2406 2407 generic_hdmi_init_per_pins(codec); 2408 return 0; 2409 } 2410 2411 /* 2412 * generic audio component binding 2413 */ 2414 2415 /* turn on / off the unsol event jack detection dynamically */ 2416 static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid, 2417 int dev_id, bool use_acomp) 2418 { 2419 struct hda_jack_tbl *tbl; 2420 2421 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id); 2422 if (tbl) { 2423 /* clear unsol even if component notifier is used, or re-enable 2424 * if notifier is cleared 2425 */ 2426 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag); 2427 snd_hda_codec_write_cache(codec, nid, 0, 2428 AC_VERB_SET_UNSOLICITED_ENABLE, val); 2429 } 2430 } 2431 2432 /* set up / clear component notifier dynamically */ 2433 static void generic_acomp_notifier_set(struct drm_audio_component *acomp, 2434 bool use_acomp) 2435 { 2436 struct hdmi_spec *spec; 2437 int i; 2438 2439 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops); 2440 mutex_lock(&spec->bind_lock); 2441 spec->use_acomp_notifier = use_acomp; 2442 spec->codec->relaxed_resume = use_acomp; 2443 spec->codec->bus->keep_power = 0; 2444 /* reprogram each jack detection logic depending on the notifier */ 2445 for (i = 0; i < spec->num_pins; i++) 2446 reprogram_jack_detect(spec->codec, 2447 get_pin(spec, i)->pin_nid, 2448 get_pin(spec, i)->dev_id, 2449 use_acomp); 2450 mutex_unlock(&spec->bind_lock); 2451 } 2452 2453 /* enable / disable the notifier via master bind / unbind */ 2454 static int generic_acomp_master_bind(struct device *dev, 2455 struct drm_audio_component *acomp) 2456 { 2457 generic_acomp_notifier_set(acomp, true); 2458 return 0; 2459 } 2460 2461 static void generic_acomp_master_unbind(struct device *dev, 2462 struct drm_audio_component *acomp) 2463 { 2464 generic_acomp_notifier_set(acomp, false); 2465 } 2466 2467 /* check whether both HD-audio and DRM PCI devices belong to the same bus */ 2468 static int match_bound_vga(struct device *dev, int subtype, void *data) 2469 { 2470 struct hdac_bus *bus = data; 2471 struct pci_dev *pci, *master; 2472 2473 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev)) 2474 return 0; 2475 master = to_pci_dev(bus->dev); 2476 pci = to_pci_dev(dev); 2477 return master->bus == pci->bus; 2478 } 2479 2480 /* audio component notifier for AMD/Nvidia HDMI codecs */ 2481 static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id) 2482 { 2483 struct hda_codec *codec = audio_ptr; 2484 struct hdmi_spec *spec = codec->spec; 2485 hda_nid_t pin_nid = spec->port2pin(codec, port); 2486 2487 if (!pin_nid) 2488 return; 2489 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN) 2490 return; 2491 /* skip notification during system suspend (but not in runtime PM); 2492 * the state will be updated at resume 2493 */ 2494 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) 2495 return; 2496 /* ditto during suspend/resume process itself */ 2497 if (snd_hdac_is_in_pm(&codec->core)) 2498 return; 2499 2500 check_presence_and_report(codec, pin_nid, dev_id); 2501 } 2502 2503 /* set up the private drm_audio_ops from the template */ 2504 static void setup_drm_audio_ops(struct hda_codec *codec, 2505 const struct drm_audio_component_audio_ops *ops) 2506 { 2507 struct hdmi_spec *spec = codec->spec; 2508 2509 spec->drm_audio_ops.audio_ptr = codec; 2510 /* intel_audio_codec_enable() or intel_audio_codec_disable() 2511 * will call pin_eld_notify with using audio_ptr pointer 2512 * We need make sure audio_ptr is really setup 2513 */ 2514 wmb(); 2515 spec->drm_audio_ops.pin2port = ops->pin2port; 2516 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify; 2517 spec->drm_audio_ops.master_bind = ops->master_bind; 2518 spec->drm_audio_ops.master_unbind = ops->master_unbind; 2519 } 2520 2521 /* initialize the generic HDMI audio component */ 2522 static void generic_acomp_init(struct hda_codec *codec, 2523 const struct drm_audio_component_audio_ops *ops, 2524 int (*port2pin)(struct hda_codec *, int)) 2525 { 2526 struct hdmi_spec *spec = codec->spec; 2527 2528 if (!enable_acomp) { 2529 codec_info(codec, "audio component disabled by module option\n"); 2530 return; 2531 } 2532 2533 spec->port2pin = port2pin; 2534 setup_drm_audio_ops(codec, ops); 2535 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops, 2536 match_bound_vga, 0)) { 2537 spec->acomp_registered = true; 2538 } 2539 } 2540 2541 /* 2542 * Intel codec parsers and helpers 2543 */ 2544 2545 #define INTEL_GET_VENDOR_VERB 0xf81 2546 #define INTEL_SET_VENDOR_VERB 0x781 2547 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ 2548 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ 2549 2550 static void intel_haswell_enable_all_pins(struct hda_codec *codec, 2551 bool update_tree) 2552 { 2553 unsigned int vendor_param; 2554 struct hdmi_spec *spec = codec->spec; 2555 2556 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2557 INTEL_GET_VENDOR_VERB, 0); 2558 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) 2559 return; 2560 2561 vendor_param |= INTEL_EN_ALL_PIN_CVTS; 2562 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2563 INTEL_SET_VENDOR_VERB, vendor_param); 2564 if (vendor_param == -1) 2565 return; 2566 2567 if (update_tree) 2568 snd_hda_codec_update_widgets(codec); 2569 } 2570 2571 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) 2572 { 2573 unsigned int vendor_param; 2574 struct hdmi_spec *spec = codec->spec; 2575 2576 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2577 INTEL_GET_VENDOR_VERB, 0); 2578 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) 2579 return; 2580 2581 /* enable DP1.2 mode */ 2582 vendor_param |= INTEL_EN_DP12; 2583 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); 2584 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, 2585 INTEL_SET_VENDOR_VERB, vendor_param); 2586 } 2587 2588 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. 2589 * Otherwise you may get severe h/w communication errors. 2590 */ 2591 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, 2592 unsigned int power_state) 2593 { 2594 if (power_state == AC_PWRST_D0) { 2595 intel_haswell_enable_all_pins(codec, false); 2596 intel_haswell_fixup_enable_dp12(codec); 2597 } 2598 2599 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); 2600 snd_hda_codec_set_power_to_all(codec, fg, power_state); 2601 } 2602 2603 /* There is a fixed mapping between audio pin node and display port. 2604 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL: 2605 * Pin Widget 5 - PORT B (port = 1 in i915 driver) 2606 * Pin Widget 6 - PORT C (port = 2 in i915 driver) 2607 * Pin Widget 7 - PORT D (port = 3 in i915 driver) 2608 * 2609 * on VLV, ILK: 2610 * Pin Widget 4 - PORT B (port = 1 in i915 driver) 2611 * Pin Widget 5 - PORT C (port = 2 in i915 driver) 2612 * Pin Widget 6 - PORT D (port = 3 in i915 driver) 2613 */ 2614 static int intel_base_nid(struct hda_codec *codec) 2615 { 2616 switch (codec->core.vendor_id) { 2617 case 0x80860054: /* ILK */ 2618 case 0x80862804: /* ILK */ 2619 case 0x80862882: /* VLV */ 2620 return 4; 2621 default: 2622 return 5; 2623 } 2624 } 2625 2626 static int intel_pin2port(void *audio_ptr, int pin_nid) 2627 { 2628 struct hda_codec *codec = audio_ptr; 2629 struct hdmi_spec *spec = codec->spec; 2630 int base_nid, i; 2631 2632 if (!spec->port_num) { 2633 base_nid = intel_base_nid(codec); 2634 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3)) 2635 return -1; 2636 return pin_nid - base_nid + 1; 2637 } 2638 2639 /* 2640 * looking for the pin number in the mapping table and return 2641 * the index which indicate the port number 2642 */ 2643 for (i = 0; i < spec->port_num; i++) { 2644 if (pin_nid == spec->port_map[i]) 2645 return i; 2646 } 2647 2648 codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid); 2649 return -1; 2650 } 2651 2652 static int intel_port2pin(struct hda_codec *codec, int port) 2653 { 2654 struct hdmi_spec *spec = codec->spec; 2655 2656 if (!spec->port_num) { 2657 /* we assume only from port-B to port-D */ 2658 if (port < 1 || port > 3) 2659 return 0; 2660 return port + intel_base_nid(codec) - 1; 2661 } 2662 2663 if (port < 0 || port >= spec->port_num) 2664 return 0; 2665 return spec->port_map[port]; 2666 } 2667 2668 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) 2669 { 2670 struct hda_codec *codec = audio_ptr; 2671 int pin_nid; 2672 int dev_id = pipe; 2673 2674 pin_nid = intel_port2pin(codec, port); 2675 if (!pin_nid) 2676 return; 2677 /* skip notification during system suspend (but not in runtime PM); 2678 * the state will be updated at resume 2679 */ 2680 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) 2681 return; 2682 /* ditto during suspend/resume process itself */ 2683 if (snd_hdac_is_in_pm(&codec->core)) 2684 return; 2685 2686 snd_hdac_i915_set_bclk(&codec->bus->core); 2687 check_presence_and_report(codec, pin_nid, dev_id); 2688 } 2689 2690 static const struct drm_audio_component_audio_ops intel_audio_ops = { 2691 .pin2port = intel_pin2port, 2692 .pin_eld_notify = intel_pin_eld_notify, 2693 }; 2694 2695 /* register i915 component pin_eld_notify callback */ 2696 static void register_i915_notifier(struct hda_codec *codec) 2697 { 2698 struct hdmi_spec *spec = codec->spec; 2699 2700 spec->use_acomp_notifier = true; 2701 spec->port2pin = intel_port2pin; 2702 setup_drm_audio_ops(codec, &intel_audio_ops); 2703 snd_hdac_acomp_register_notifier(&codec->bus->core, 2704 &spec->drm_audio_ops); 2705 /* no need for forcible resume for jack check thanks to notifier */ 2706 codec->relaxed_resume = 1; 2707 } 2708 2709 /* setup_stream ops override for HSW+ */ 2710 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 2711 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 2712 int format) 2713 { 2714 haswell_verify_D0(codec, cvt_nid, pin_nid); 2715 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 2716 stream_tag, format); 2717 } 2718 2719 /* pin_cvt_fixup ops override for HSW+ and VLV+ */ 2720 static void i915_pin_cvt_fixup(struct hda_codec *codec, 2721 struct hdmi_spec_per_pin *per_pin, 2722 hda_nid_t cvt_nid) 2723 { 2724 if (per_pin) { 2725 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2726 per_pin->dev_id); 2727 intel_verify_pin_cvt_connect(codec, per_pin); 2728 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, 2729 per_pin->dev_id, per_pin->mux_idx); 2730 } else { 2731 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); 2732 } 2733 } 2734 2735 /* precondition and allocation for Intel codecs */ 2736 static int alloc_intel_hdmi(struct hda_codec *codec) 2737 { 2738 int err; 2739 2740 /* requires i915 binding */ 2741 if (!codec->bus->core.audio_component) { 2742 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); 2743 /* set probe_id here to prevent generic fallback binding */ 2744 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE; 2745 return -ENODEV; 2746 } 2747 2748 err = alloc_generic_hdmi(codec); 2749 if (err < 0) 2750 return err; 2751 /* no need to handle unsol events */ 2752 codec->patch_ops.unsol_event = NULL; 2753 return 0; 2754 } 2755 2756 /* parse and post-process for Intel codecs */ 2757 static int parse_intel_hdmi(struct hda_codec *codec) 2758 { 2759 int err, retries = 3; 2760 2761 do { 2762 err = hdmi_parse_codec(codec); 2763 } while (err < 0 && retries--); 2764 2765 if (err < 0) { 2766 generic_spec_free(codec); 2767 return err; 2768 } 2769 2770 generic_hdmi_init_per_pins(codec); 2771 register_i915_notifier(codec); 2772 return 0; 2773 } 2774 2775 /* Intel Haswell and onwards; audio component with eld notifier */ 2776 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid, 2777 const int *port_map, int port_num) 2778 { 2779 struct hdmi_spec *spec; 2780 int err; 2781 2782 err = alloc_intel_hdmi(codec); 2783 if (err < 0) 2784 return err; 2785 spec = codec->spec; 2786 codec->dp_mst = true; 2787 spec->dyn_pcm_assign = true; 2788 spec->vendor_nid = vendor_nid; 2789 spec->port_map = port_map; 2790 spec->port_num = port_num; 2791 spec->intel_hsw_fixup = true; 2792 2793 intel_haswell_enable_all_pins(codec, true); 2794 intel_haswell_fixup_enable_dp12(codec); 2795 2796 codec->display_power_control = 1; 2797 2798 codec->patch_ops.set_power_state = haswell_set_power_state; 2799 codec->depop_delay = 0; 2800 codec->auto_runtime_pm = 1; 2801 2802 spec->ops.setup_stream = i915_hsw_setup_stream; 2803 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2804 2805 return parse_intel_hdmi(codec); 2806 } 2807 2808 static int patch_i915_hsw_hdmi(struct hda_codec *codec) 2809 { 2810 return intel_hsw_common_init(codec, 0x08, NULL, 0); 2811 } 2812 2813 static int patch_i915_glk_hdmi(struct hda_codec *codec) 2814 { 2815 return intel_hsw_common_init(codec, 0x0b, NULL, 0); 2816 } 2817 2818 static int patch_i915_icl_hdmi(struct hda_codec *codec) 2819 { 2820 /* 2821 * pin to port mapping table where the value indicate the pin number and 2822 * the index indicate the port number. 2823 */ 2824 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb}; 2825 2826 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map)); 2827 } 2828 2829 static int patch_i915_tgl_hdmi(struct hda_codec *codec) 2830 { 2831 /* 2832 * pin to port mapping table where the value indicate the pin number and 2833 * the index indicate the port number. 2834 */ 2835 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf}; 2836 2837 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map)); 2838 } 2839 2840 /* Intel Baytrail and Braswell; with eld notifier */ 2841 static int patch_i915_byt_hdmi(struct hda_codec *codec) 2842 { 2843 struct hdmi_spec *spec; 2844 int err; 2845 2846 err = alloc_intel_hdmi(codec); 2847 if (err < 0) 2848 return err; 2849 spec = codec->spec; 2850 2851 /* For Valleyview/Cherryview, only the display codec is in the display 2852 * power well and can use link_power ops to request/release the power. 2853 */ 2854 codec->display_power_control = 1; 2855 2856 codec->depop_delay = 0; 2857 codec->auto_runtime_pm = 1; 2858 2859 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2860 2861 return parse_intel_hdmi(codec); 2862 } 2863 2864 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ 2865 static int patch_i915_cpt_hdmi(struct hda_codec *codec) 2866 { 2867 int err; 2868 2869 err = alloc_intel_hdmi(codec); 2870 if (err < 0) 2871 return err; 2872 return parse_intel_hdmi(codec); 2873 } 2874 2875 /* 2876 * Shared non-generic implementations 2877 */ 2878 2879 static int simple_playback_build_pcms(struct hda_codec *codec) 2880 { 2881 struct hdmi_spec *spec = codec->spec; 2882 struct hda_pcm *info; 2883 unsigned int chans; 2884 struct hda_pcm_stream *pstr; 2885 struct hdmi_spec_per_cvt *per_cvt; 2886 2887 per_cvt = get_cvt(spec, 0); 2888 chans = get_wcaps(codec, per_cvt->cvt_nid); 2889 chans = get_wcaps_channels(chans); 2890 2891 info = snd_hda_codec_pcm_new(codec, "HDMI 0"); 2892 if (!info) 2893 return -ENOMEM; 2894 spec->pcm_rec[0].pcm = info; 2895 info->pcm_type = HDA_PCM_TYPE_HDMI; 2896 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2897 *pstr = spec->pcm_playback; 2898 pstr->nid = per_cvt->cvt_nid; 2899 if (pstr->channels_max <= 2 && chans && chans <= 16) 2900 pstr->channels_max = chans; 2901 2902 return 0; 2903 } 2904 2905 /* unsolicited event for jack sensing */ 2906 static void simple_hdmi_unsol_event(struct hda_codec *codec, 2907 unsigned int res) 2908 { 2909 snd_hda_jack_set_dirty_all(codec); 2910 snd_hda_jack_report_sync(codec); 2911 } 2912 2913 /* generic_hdmi_build_jack can be used for simple_hdmi, too, 2914 * as long as spec->pins[] is set correctly 2915 */ 2916 #define simple_hdmi_build_jack generic_hdmi_build_jack 2917 2918 static int simple_playback_build_controls(struct hda_codec *codec) 2919 { 2920 struct hdmi_spec *spec = codec->spec; 2921 struct hdmi_spec_per_cvt *per_cvt; 2922 int err; 2923 2924 per_cvt = get_cvt(spec, 0); 2925 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, 2926 per_cvt->cvt_nid, 2927 HDA_PCM_TYPE_HDMI); 2928 if (err < 0) 2929 return err; 2930 return simple_hdmi_build_jack(codec, 0); 2931 } 2932 2933 static int simple_playback_init(struct hda_codec *codec) 2934 { 2935 struct hdmi_spec *spec = codec->spec; 2936 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); 2937 hda_nid_t pin = per_pin->pin_nid; 2938 2939 snd_hda_codec_write(codec, pin, 0, 2940 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); 2941 /* some codecs require to unmute the pin */ 2942 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 2943 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, 2944 AMP_OUT_UNMUTE); 2945 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id); 2946 return 0; 2947 } 2948 2949 static void simple_playback_free(struct hda_codec *codec) 2950 { 2951 struct hdmi_spec *spec = codec->spec; 2952 2953 hdmi_array_free(spec); 2954 kfree(spec); 2955 } 2956 2957 /* 2958 * Nvidia specific implementations 2959 */ 2960 2961 #define Nv_VERB_SET_Channel_Allocation 0xF79 2962 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A 2963 #define Nv_VERB_SET_Audio_Protection_On 0xF98 2964 #define Nv_VERB_SET_Audio_Protection_Off 0xF99 2965 2966 #define nvhdmi_master_con_nid_7x 0x04 2967 #define nvhdmi_master_pin_nid_7x 0x05 2968 2969 static const hda_nid_t nvhdmi_con_nids_7x[4] = { 2970 /*front, rear, clfe, rear_surr */ 2971 0x6, 0x8, 0xa, 0xc, 2972 }; 2973 2974 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { 2975 /* set audio protect on */ 2976 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 2977 /* enable digital output on pin widget */ 2978 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2979 {} /* terminator */ 2980 }; 2981 2982 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { 2983 /* set audio protect on */ 2984 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 2985 /* enable digital output on pin widget */ 2986 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2987 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2988 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2989 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2990 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2991 {} /* terminator */ 2992 }; 2993 2994 #ifdef LIMITED_RATE_FMT_SUPPORT 2995 /* support only the safe format and rate */ 2996 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 2997 #define SUPPORTED_MAXBPS 16 2998 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE 2999 #else 3000 /* support all rates and formats */ 3001 #define SUPPORTED_RATES \ 3002 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ 3003 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ 3004 SNDRV_PCM_RATE_192000) 3005 #define SUPPORTED_MAXBPS 24 3006 #define SUPPORTED_FORMATS \ 3007 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 3008 #endif 3009 3010 static int nvhdmi_7x_init_2ch(struct hda_codec *codec) 3011 { 3012 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); 3013 return 0; 3014 } 3015 3016 static int nvhdmi_7x_init_8ch(struct hda_codec *codec) 3017 { 3018 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); 3019 return 0; 3020 } 3021 3022 static const unsigned int channels_2_6_8[] = { 3023 2, 6, 8 3024 }; 3025 3026 static const unsigned int channels_2_8[] = { 3027 2, 8 3028 }; 3029 3030 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { 3031 .count = ARRAY_SIZE(channels_2_6_8), 3032 .list = channels_2_6_8, 3033 .mask = 0, 3034 }; 3035 3036 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { 3037 .count = ARRAY_SIZE(channels_2_8), 3038 .list = channels_2_8, 3039 .mask = 0, 3040 }; 3041 3042 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, 3043 struct hda_codec *codec, 3044 struct snd_pcm_substream *substream) 3045 { 3046 struct hdmi_spec *spec = codec->spec; 3047 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; 3048 3049 switch (codec->preset->vendor_id) { 3050 case 0x10de0002: 3051 case 0x10de0003: 3052 case 0x10de0005: 3053 case 0x10de0006: 3054 hw_constraints_channels = &hw_constraints_2_8_channels; 3055 break; 3056 case 0x10de0007: 3057 hw_constraints_channels = &hw_constraints_2_6_8_channels; 3058 break; 3059 default: 3060 break; 3061 } 3062 3063 if (hw_constraints_channels != NULL) { 3064 snd_pcm_hw_constraint_list(substream->runtime, 0, 3065 SNDRV_PCM_HW_PARAM_CHANNELS, 3066 hw_constraints_channels); 3067 } else { 3068 snd_pcm_hw_constraint_step(substream->runtime, 0, 3069 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 3070 } 3071 3072 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3073 } 3074 3075 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, 3076 struct hda_codec *codec, 3077 struct snd_pcm_substream *substream) 3078 { 3079 struct hdmi_spec *spec = codec->spec; 3080 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3081 } 3082 3083 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3084 struct hda_codec *codec, 3085 unsigned int stream_tag, 3086 unsigned int format, 3087 struct snd_pcm_substream *substream) 3088 { 3089 struct hdmi_spec *spec = codec->spec; 3090 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3091 stream_tag, format, substream); 3092 } 3093 3094 static const struct hda_pcm_stream simple_pcm_playback = { 3095 .substreams = 1, 3096 .channels_min = 2, 3097 .channels_max = 2, 3098 .ops = { 3099 .open = simple_playback_pcm_open, 3100 .close = simple_playback_pcm_close, 3101 .prepare = simple_playback_pcm_prepare 3102 }, 3103 }; 3104 3105 static const struct hda_codec_ops simple_hdmi_patch_ops = { 3106 .build_controls = simple_playback_build_controls, 3107 .build_pcms = simple_playback_build_pcms, 3108 .init = simple_playback_init, 3109 .free = simple_playback_free, 3110 .unsol_event = simple_hdmi_unsol_event, 3111 }; 3112 3113 static int patch_simple_hdmi(struct hda_codec *codec, 3114 hda_nid_t cvt_nid, hda_nid_t pin_nid) 3115 { 3116 struct hdmi_spec *spec; 3117 struct hdmi_spec_per_cvt *per_cvt; 3118 struct hdmi_spec_per_pin *per_pin; 3119 3120 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 3121 if (!spec) 3122 return -ENOMEM; 3123 3124 spec->codec = codec; 3125 codec->spec = spec; 3126 hdmi_array_init(spec, 1); 3127 3128 spec->multiout.num_dacs = 0; /* no analog */ 3129 spec->multiout.max_channels = 2; 3130 spec->multiout.dig_out_nid = cvt_nid; 3131 spec->num_cvts = 1; 3132 spec->num_pins = 1; 3133 per_pin = snd_array_new(&spec->pins); 3134 per_cvt = snd_array_new(&spec->cvts); 3135 if (!per_pin || !per_cvt) { 3136 simple_playback_free(codec); 3137 return -ENOMEM; 3138 } 3139 per_cvt->cvt_nid = cvt_nid; 3140 per_pin->pin_nid = pin_nid; 3141 spec->pcm_playback = simple_pcm_playback; 3142 3143 codec->patch_ops = simple_hdmi_patch_ops; 3144 3145 return 0; 3146 } 3147 3148 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, 3149 int channels) 3150 { 3151 unsigned int chanmask; 3152 int chan = channels ? (channels - 1) : 1; 3153 3154 switch (channels) { 3155 default: 3156 case 0: 3157 case 2: 3158 chanmask = 0x00; 3159 break; 3160 case 4: 3161 chanmask = 0x08; 3162 break; 3163 case 6: 3164 chanmask = 0x0b; 3165 break; 3166 case 8: 3167 chanmask = 0x13; 3168 break; 3169 } 3170 3171 /* Set the audio infoframe channel allocation and checksum fields. The 3172 * channel count is computed implicitly by the hardware. */ 3173 snd_hda_codec_write(codec, 0x1, 0, 3174 Nv_VERB_SET_Channel_Allocation, chanmask); 3175 3176 snd_hda_codec_write(codec, 0x1, 0, 3177 Nv_VERB_SET_Info_Frame_Checksum, 3178 (0x71 - chan - chanmask)); 3179 } 3180 3181 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, 3182 struct hda_codec *codec, 3183 struct snd_pcm_substream *substream) 3184 { 3185 struct hdmi_spec *spec = codec->spec; 3186 int i; 3187 3188 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 3189 0, AC_VERB_SET_CHANNEL_STREAMID, 0); 3190 for (i = 0; i < 4; i++) { 3191 /* set the stream id */ 3192 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3193 AC_VERB_SET_CHANNEL_STREAMID, 0); 3194 /* set the stream format */ 3195 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3196 AC_VERB_SET_STREAM_FORMAT, 0); 3197 } 3198 3199 /* The audio hardware sends a channel count of 0x7 (8ch) when all the 3200 * streams are disabled. */ 3201 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3202 3203 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3204 } 3205 3206 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, 3207 struct hda_codec *codec, 3208 unsigned int stream_tag, 3209 unsigned int format, 3210 struct snd_pcm_substream *substream) 3211 { 3212 int chs; 3213 unsigned int dataDCC2, channel_id; 3214 int i; 3215 struct hdmi_spec *spec = codec->spec; 3216 struct hda_spdif_out *spdif; 3217 struct hdmi_spec_per_cvt *per_cvt; 3218 3219 mutex_lock(&codec->spdif_mutex); 3220 per_cvt = get_cvt(spec, 0); 3221 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); 3222 3223 chs = substream->runtime->channels; 3224 3225 dataDCC2 = 0x2; 3226 3227 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ 3228 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) 3229 snd_hda_codec_write(codec, 3230 nvhdmi_master_con_nid_7x, 3231 0, 3232 AC_VERB_SET_DIGI_CONVERT_1, 3233 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3234 3235 /* set the stream id */ 3236 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3237 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); 3238 3239 /* set the stream format */ 3240 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3241 AC_VERB_SET_STREAM_FORMAT, format); 3242 3243 /* turn on again (if needed) */ 3244 /* enable and set the channel status audio/data flag */ 3245 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { 3246 snd_hda_codec_write(codec, 3247 nvhdmi_master_con_nid_7x, 3248 0, 3249 AC_VERB_SET_DIGI_CONVERT_1, 3250 spdif->ctls & 0xff); 3251 snd_hda_codec_write(codec, 3252 nvhdmi_master_con_nid_7x, 3253 0, 3254 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3255 } 3256 3257 for (i = 0; i < 4; i++) { 3258 if (chs == 2) 3259 channel_id = 0; 3260 else 3261 channel_id = i * 2; 3262 3263 /* turn off SPDIF once; 3264 *otherwise the IEC958 bits won't be updated 3265 */ 3266 if (codec->spdif_status_reset && 3267 (spdif->ctls & AC_DIG1_ENABLE)) 3268 snd_hda_codec_write(codec, 3269 nvhdmi_con_nids_7x[i], 3270 0, 3271 AC_VERB_SET_DIGI_CONVERT_1, 3272 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3273 /* set the stream id */ 3274 snd_hda_codec_write(codec, 3275 nvhdmi_con_nids_7x[i], 3276 0, 3277 AC_VERB_SET_CHANNEL_STREAMID, 3278 (stream_tag << 4) | channel_id); 3279 /* set the stream format */ 3280 snd_hda_codec_write(codec, 3281 nvhdmi_con_nids_7x[i], 3282 0, 3283 AC_VERB_SET_STREAM_FORMAT, 3284 format); 3285 /* turn on again (if needed) */ 3286 /* enable and set the channel status audio/data flag */ 3287 if (codec->spdif_status_reset && 3288 (spdif->ctls & AC_DIG1_ENABLE)) { 3289 snd_hda_codec_write(codec, 3290 nvhdmi_con_nids_7x[i], 3291 0, 3292 AC_VERB_SET_DIGI_CONVERT_1, 3293 spdif->ctls & 0xff); 3294 snd_hda_codec_write(codec, 3295 nvhdmi_con_nids_7x[i], 3296 0, 3297 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3298 } 3299 } 3300 3301 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); 3302 3303 mutex_unlock(&codec->spdif_mutex); 3304 return 0; 3305 } 3306 3307 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { 3308 .substreams = 1, 3309 .channels_min = 2, 3310 .channels_max = 8, 3311 .nid = nvhdmi_master_con_nid_7x, 3312 .rates = SUPPORTED_RATES, 3313 .maxbps = SUPPORTED_MAXBPS, 3314 .formats = SUPPORTED_FORMATS, 3315 .ops = { 3316 .open = simple_playback_pcm_open, 3317 .close = nvhdmi_8ch_7x_pcm_close, 3318 .prepare = nvhdmi_8ch_7x_pcm_prepare 3319 }, 3320 }; 3321 3322 static int patch_nvhdmi_2ch(struct hda_codec *codec) 3323 { 3324 struct hdmi_spec *spec; 3325 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, 3326 nvhdmi_master_pin_nid_7x); 3327 if (err < 0) 3328 return err; 3329 3330 codec->patch_ops.init = nvhdmi_7x_init_2ch; 3331 /* override the PCM rates, etc, as the codec doesn't give full list */ 3332 spec = codec->spec; 3333 spec->pcm_playback.rates = SUPPORTED_RATES; 3334 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; 3335 spec->pcm_playback.formats = SUPPORTED_FORMATS; 3336 return 0; 3337 } 3338 3339 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) 3340 { 3341 struct hdmi_spec *spec = codec->spec; 3342 int err = simple_playback_build_pcms(codec); 3343 if (!err) { 3344 struct hda_pcm *info = get_pcm_rec(spec, 0); 3345 info->own_chmap = true; 3346 } 3347 return err; 3348 } 3349 3350 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) 3351 { 3352 struct hdmi_spec *spec = codec->spec; 3353 struct hda_pcm *info; 3354 struct snd_pcm_chmap *chmap; 3355 int err; 3356 3357 err = simple_playback_build_controls(codec); 3358 if (err < 0) 3359 return err; 3360 3361 /* add channel maps */ 3362 info = get_pcm_rec(spec, 0); 3363 err = snd_pcm_add_chmap_ctls(info->pcm, 3364 SNDRV_PCM_STREAM_PLAYBACK, 3365 snd_pcm_alt_chmaps, 8, 0, &chmap); 3366 if (err < 0) 3367 return err; 3368 switch (codec->preset->vendor_id) { 3369 case 0x10de0002: 3370 case 0x10de0003: 3371 case 0x10de0005: 3372 case 0x10de0006: 3373 chmap->channel_mask = (1U << 2) | (1U << 8); 3374 break; 3375 case 0x10de0007: 3376 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); 3377 } 3378 return 0; 3379 } 3380 3381 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) 3382 { 3383 struct hdmi_spec *spec; 3384 int err = patch_nvhdmi_2ch(codec); 3385 if (err < 0) 3386 return err; 3387 spec = codec->spec; 3388 spec->multiout.max_channels = 8; 3389 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; 3390 codec->patch_ops.init = nvhdmi_7x_init_8ch; 3391 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; 3392 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; 3393 3394 /* Initialize the audio infoframe channel mask and checksum to something 3395 * valid */ 3396 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3397 3398 return 0; 3399 } 3400 3401 /* 3402 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: 3403 * - 0x10de0015 3404 * - 0x10de0040 3405 */ 3406 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, 3407 struct hdac_cea_channel_speaker_allocation *cap, int channels) 3408 { 3409 if (cap->ca_index == 0x00 && channels == 2) 3410 return SNDRV_CTL_TLVT_CHMAP_FIXED; 3411 3412 /* If the speaker allocation matches the channel count, it is OK. */ 3413 if (cap->channels != channels) 3414 return -1; 3415 3416 /* all channels are remappable freely */ 3417 return SNDRV_CTL_TLVT_CHMAP_VAR; 3418 } 3419 3420 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, 3421 int ca, int chs, unsigned char *map) 3422 { 3423 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) 3424 return -EINVAL; 3425 3426 return 0; 3427 } 3428 3429 /* map from pin NID to port; port is 0-based */ 3430 /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */ 3431 static int nvhdmi_pin2port(void *audio_ptr, int pin_nid) 3432 { 3433 return pin_nid - 4; 3434 } 3435 3436 /* reverse-map from port to pin NID: see above */ 3437 static int nvhdmi_port2pin(struct hda_codec *codec, int port) 3438 { 3439 return port + 4; 3440 } 3441 3442 static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = { 3443 .pin2port = nvhdmi_pin2port, 3444 .pin_eld_notify = generic_acomp_pin_eld_notify, 3445 .master_bind = generic_acomp_master_bind, 3446 .master_unbind = generic_acomp_master_unbind, 3447 }; 3448 3449 static int patch_nvhdmi(struct hda_codec *codec) 3450 { 3451 struct hdmi_spec *spec; 3452 int err; 3453 3454 err = alloc_generic_hdmi(codec); 3455 if (err < 0) 3456 return err; 3457 codec->dp_mst = true; 3458 3459 spec = codec->spec; 3460 spec->dyn_pcm_assign = true; 3461 3462 err = hdmi_parse_codec(codec); 3463 if (err < 0) { 3464 generic_spec_free(codec); 3465 return err; 3466 } 3467 3468 generic_hdmi_init_per_pins(codec); 3469 3470 spec->dyn_pin_out = true; 3471 3472 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3473 nvhdmi_chmap_cea_alloc_validate_get_type; 3474 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3475 3476 codec->link_down_at_suspend = 1; 3477 3478 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin); 3479 3480 return 0; 3481 } 3482 3483 static int patch_nvhdmi_legacy(struct hda_codec *codec) 3484 { 3485 struct hdmi_spec *spec; 3486 int err; 3487 3488 err = patch_generic_hdmi(codec); 3489 if (err) 3490 return err; 3491 3492 spec = codec->spec; 3493 spec->dyn_pin_out = true; 3494 3495 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3496 nvhdmi_chmap_cea_alloc_validate_get_type; 3497 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3498 3499 codec->link_down_at_suspend = 1; 3500 3501 return 0; 3502 } 3503 3504 /* 3505 * The HDA codec on NVIDIA Tegra contains two scratch registers that are 3506 * accessed using vendor-defined verbs. These registers can be used for 3507 * interoperability between the HDA and HDMI drivers. 3508 */ 3509 3510 /* Audio Function Group node */ 3511 #define NVIDIA_AFG_NID 0x01 3512 3513 /* 3514 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio 3515 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to 3516 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This 3517 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an 3518 * additional bit (at position 30) to signal the validity of the format. 3519 * 3520 * | 31 | 30 | 29 16 | 15 0 | 3521 * +---------+-------+--------+--------+ 3522 * | TRIGGER | VALID | UNUSED | FORMAT | 3523 * +-----------------------------------| 3524 * 3525 * Note that for the trigger bit to take effect it needs to change value 3526 * (i.e. it needs to be toggled). 3527 */ 3528 #define NVIDIA_GET_SCRATCH0 0xfa6 3529 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 3530 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 3531 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 3532 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa 3533 #define NVIDIA_SCRATCH_TRIGGER (1 << 7) 3534 #define NVIDIA_SCRATCH_VALID (1 << 6) 3535 3536 #define NVIDIA_GET_SCRATCH1 0xfab 3537 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac 3538 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad 3539 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae 3540 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf 3541 3542 /* 3543 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, 3544 * the format is invalidated so that the HDMI codec can be disabled. 3545 */ 3546 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format) 3547 { 3548 unsigned int value; 3549 3550 /* bits [31:30] contain the trigger and valid bits */ 3551 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0, 3552 NVIDIA_GET_SCRATCH0, 0); 3553 value = (value >> 24) & 0xff; 3554 3555 /* bits [15:0] are used to store the HDA format */ 3556 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3557 NVIDIA_SET_SCRATCH0_BYTE0, 3558 (format >> 0) & 0xff); 3559 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3560 NVIDIA_SET_SCRATCH0_BYTE1, 3561 (format >> 8) & 0xff); 3562 3563 /* bits [16:24] are unused */ 3564 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3565 NVIDIA_SET_SCRATCH0_BYTE2, 0); 3566 3567 /* 3568 * Bit 30 signals that the data is valid and hence that HDMI audio can 3569 * be enabled. 3570 */ 3571 if (format == 0) 3572 value &= ~NVIDIA_SCRATCH_VALID; 3573 else 3574 value |= NVIDIA_SCRATCH_VALID; 3575 3576 /* 3577 * Whenever the trigger bit is toggled, an interrupt is raised in the 3578 * HDMI codec. The HDMI driver will use that as trigger to update its 3579 * configuration. 3580 */ 3581 value ^= NVIDIA_SCRATCH_TRIGGER; 3582 3583 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3584 NVIDIA_SET_SCRATCH0_BYTE3, value); 3585 } 3586 3587 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, 3588 struct hda_codec *codec, 3589 unsigned int stream_tag, 3590 unsigned int format, 3591 struct snd_pcm_substream *substream) 3592 { 3593 int err; 3594 3595 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, 3596 format, substream); 3597 if (err < 0) 3598 return err; 3599 3600 /* notify the HDMI codec of the format change */ 3601 tegra_hdmi_set_format(codec, format); 3602 3603 return 0; 3604 } 3605 3606 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, 3607 struct hda_codec *codec, 3608 struct snd_pcm_substream *substream) 3609 { 3610 /* invalidate the format in the HDMI codec */ 3611 tegra_hdmi_set_format(codec, 0); 3612 3613 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); 3614 } 3615 3616 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) 3617 { 3618 struct hdmi_spec *spec = codec->spec; 3619 unsigned int i; 3620 3621 for (i = 0; i < spec->num_pins; i++) { 3622 struct hda_pcm *pcm = get_pcm_rec(spec, i); 3623 3624 if (pcm->pcm_type == type) 3625 return pcm; 3626 } 3627 3628 return NULL; 3629 } 3630 3631 static int tegra_hdmi_build_pcms(struct hda_codec *codec) 3632 { 3633 struct hda_pcm_stream *stream; 3634 struct hda_pcm *pcm; 3635 int err; 3636 3637 err = generic_hdmi_build_pcms(codec); 3638 if (err < 0) 3639 return err; 3640 3641 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); 3642 if (!pcm) 3643 return -ENODEV; 3644 3645 /* 3646 * Override ->prepare() and ->cleanup() operations to notify the HDMI 3647 * codec about format changes. 3648 */ 3649 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3650 stream->ops.prepare = tegra_hdmi_pcm_prepare; 3651 stream->ops.cleanup = tegra_hdmi_pcm_cleanup; 3652 3653 return 0; 3654 } 3655 3656 static int patch_tegra_hdmi(struct hda_codec *codec) 3657 { 3658 int err; 3659 3660 err = patch_generic_hdmi(codec); 3661 if (err) 3662 return err; 3663 3664 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; 3665 3666 return 0; 3667 } 3668 3669 /* 3670 * ATI/AMD-specific implementations 3671 */ 3672 3673 #define is_amdhdmi_rev3_or_later(codec) \ 3674 ((codec)->core.vendor_id == 0x1002aa01 && \ 3675 ((codec)->core.revision_id & 0xff00) >= 0x0300) 3676 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) 3677 3678 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ 3679 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 3680 #define ATI_VERB_SET_DOWNMIX_INFO 0x772 3681 #define ATI_VERB_SET_MULTICHANNEL_01 0x777 3682 #define ATI_VERB_SET_MULTICHANNEL_23 0x778 3683 #define ATI_VERB_SET_MULTICHANNEL_45 0x779 3684 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a 3685 #define ATI_VERB_SET_HBR_CONTROL 0x77c 3686 #define ATI_VERB_SET_MULTICHANNEL_1 0x785 3687 #define ATI_VERB_SET_MULTICHANNEL_3 0x786 3688 #define ATI_VERB_SET_MULTICHANNEL_5 0x787 3689 #define ATI_VERB_SET_MULTICHANNEL_7 0x788 3690 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 3691 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 3692 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 3693 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 3694 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 3695 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 3696 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a 3697 #define ATI_VERB_GET_HBR_CONTROL 0xf7c 3698 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 3699 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 3700 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 3701 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 3702 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 3703 3704 /* AMD specific HDA cvt verbs */ 3705 #define ATI_VERB_SET_RAMP_RATE 0x770 3706 #define ATI_VERB_GET_RAMP_RATE 0xf70 3707 3708 #define ATI_OUT_ENABLE 0x1 3709 3710 #define ATI_MULTICHANNEL_MODE_PAIRED 0 3711 #define ATI_MULTICHANNEL_MODE_SINGLE 1 3712 3713 #define ATI_HBR_CAPABLE 0x01 3714 #define ATI_HBR_ENABLE 0x10 3715 3716 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 3717 int dev_id, unsigned char *buf, int *eld_size) 3718 { 3719 WARN_ON(dev_id != 0); 3720 /* call hda_eld.c ATI/AMD-specific function */ 3721 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, 3722 is_amdhdmi_rev3_or_later(codec)); 3723 } 3724 3725 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, 3726 hda_nid_t pin_nid, int dev_id, int ca, 3727 int active_channels, int conn_type) 3728 { 3729 WARN_ON(dev_id != 0); 3730 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); 3731 } 3732 3733 static int atihdmi_paired_swap_fc_lfe(int pos) 3734 { 3735 /* 3736 * ATI/AMD have automatic FC/LFE swap built-in 3737 * when in pairwise mapping mode. 3738 */ 3739 3740 switch (pos) { 3741 /* see channel_allocations[].speakers[] */ 3742 case 2: return 3; 3743 case 3: return 2; 3744 default: break; 3745 } 3746 3747 return pos; 3748 } 3749 3750 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, 3751 int ca, int chs, unsigned char *map) 3752 { 3753 struct hdac_cea_channel_speaker_allocation *cap; 3754 int i, j; 3755 3756 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ 3757 3758 cap = snd_hdac_get_ch_alloc_from_ca(ca); 3759 for (i = 0; i < chs; ++i) { 3760 int mask = snd_hdac_chmap_to_spk_mask(map[i]); 3761 bool ok = false; 3762 bool companion_ok = false; 3763 3764 if (!mask) 3765 continue; 3766 3767 for (j = 0 + i % 2; j < 8; j += 2) { 3768 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); 3769 if (cap->speakers[chan_idx] == mask) { 3770 /* channel is in a supported position */ 3771 ok = true; 3772 3773 if (i % 2 == 0 && i + 1 < chs) { 3774 /* even channel, check the odd companion */ 3775 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); 3776 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); 3777 int comp_mask_act = cap->speakers[comp_chan_idx]; 3778 3779 if (comp_mask_req == comp_mask_act) 3780 companion_ok = true; 3781 else 3782 return -EINVAL; 3783 } 3784 break; 3785 } 3786 } 3787 3788 if (!ok) 3789 return -EINVAL; 3790 3791 if (companion_ok) 3792 i++; /* companion channel already checked */ 3793 } 3794 3795 return 0; 3796 } 3797 3798 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, 3799 hda_nid_t pin_nid, int hdmi_slot, int stream_channel) 3800 { 3801 struct hda_codec *codec = hdac_to_hda_codec(hdac); 3802 int verb; 3803 int ati_channel_setup = 0; 3804 3805 if (hdmi_slot > 7) 3806 return -EINVAL; 3807 3808 if (!has_amd_full_remap_support(codec)) { 3809 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); 3810 3811 /* In case this is an odd slot but without stream channel, do not 3812 * disable the slot since the corresponding even slot could have a 3813 * channel. In case neither have a channel, the slot pair will be 3814 * disabled when this function is called for the even slot. */ 3815 if (hdmi_slot % 2 != 0 && stream_channel == 0xf) 3816 return 0; 3817 3818 hdmi_slot -= hdmi_slot % 2; 3819 3820 if (stream_channel != 0xf) 3821 stream_channel -= stream_channel % 2; 3822 } 3823 3824 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; 3825 3826 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ 3827 3828 if (stream_channel != 0xf) 3829 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; 3830 3831 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); 3832 } 3833 3834 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, 3835 hda_nid_t pin_nid, int asp_slot) 3836 { 3837 struct hda_codec *codec = hdac_to_hda_codec(hdac); 3838 bool was_odd = false; 3839 int ati_asp_slot = asp_slot; 3840 int verb; 3841 int ati_channel_setup; 3842 3843 if (asp_slot > 7) 3844 return -EINVAL; 3845 3846 if (!has_amd_full_remap_support(codec)) { 3847 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); 3848 if (ati_asp_slot % 2 != 0) { 3849 ati_asp_slot -= 1; 3850 was_odd = true; 3851 } 3852 } 3853 3854 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; 3855 3856 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); 3857 3858 if (!(ati_channel_setup & ATI_OUT_ENABLE)) 3859 return 0xf; 3860 3861 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; 3862 } 3863 3864 static int atihdmi_paired_chmap_cea_alloc_validate_get_type( 3865 struct hdac_chmap *chmap, 3866 struct hdac_cea_channel_speaker_allocation *cap, 3867 int channels) 3868 { 3869 int c; 3870 3871 /* 3872 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so 3873 * we need to take that into account (a single channel may take 2 3874 * channel slots if we need to carry a silent channel next to it). 3875 * On Rev3+ AMD codecs this function is not used. 3876 */ 3877 int chanpairs = 0; 3878 3879 /* We only produce even-numbered channel count TLVs */ 3880 if ((channels % 2) != 0) 3881 return -1; 3882 3883 for (c = 0; c < 7; c += 2) { 3884 if (cap->speakers[c] || cap->speakers[c+1]) 3885 chanpairs++; 3886 } 3887 3888 if (chanpairs * 2 != channels) 3889 return -1; 3890 3891 return SNDRV_CTL_TLVT_CHMAP_PAIRED; 3892 } 3893 3894 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, 3895 struct hdac_cea_channel_speaker_allocation *cap, 3896 unsigned int *chmap, int channels) 3897 { 3898 /* produce paired maps for pre-rev3 ATI/AMD codecs */ 3899 int count = 0; 3900 int c; 3901 3902 for (c = 7; c >= 0; c--) { 3903 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); 3904 int spk = cap->speakers[chan]; 3905 if (!spk) { 3906 /* add N/A channel if the companion channel is occupied */ 3907 if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) 3908 chmap[count++] = SNDRV_CHMAP_NA; 3909 3910 continue; 3911 } 3912 3913 chmap[count++] = snd_hdac_spk_to_chmap(spk); 3914 } 3915 3916 WARN_ON(count != channels); 3917 } 3918 3919 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 3920 int dev_id, bool hbr) 3921 { 3922 int hbr_ctl, hbr_ctl_new; 3923 3924 WARN_ON(dev_id != 0); 3925 3926 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); 3927 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { 3928 if (hbr) 3929 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; 3930 else 3931 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; 3932 3933 codec_dbg(codec, 3934 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", 3935 pin_nid, 3936 hbr_ctl == hbr_ctl_new ? "" : "new-", 3937 hbr_ctl_new); 3938 3939 if (hbr_ctl != hbr_ctl_new) 3940 snd_hda_codec_write(codec, pin_nid, 0, 3941 ATI_VERB_SET_HBR_CONTROL, 3942 hbr_ctl_new); 3943 3944 } else if (hbr) 3945 return -EINVAL; 3946 3947 return 0; 3948 } 3949 3950 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 3951 hda_nid_t pin_nid, int dev_id, 3952 u32 stream_tag, int format) 3953 { 3954 if (is_amdhdmi_rev3_or_later(codec)) { 3955 int ramp_rate = 180; /* default as per AMD spec */ 3956 /* disable ramp-up/down for non-pcm as per AMD spec */ 3957 if (format & AC_FMT_TYPE_NON_PCM) 3958 ramp_rate = 0; 3959 3960 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); 3961 } 3962 3963 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 3964 stream_tag, format); 3965 } 3966 3967 3968 static int atihdmi_init(struct hda_codec *codec) 3969 { 3970 struct hdmi_spec *spec = codec->spec; 3971 int pin_idx, err; 3972 3973 err = generic_hdmi_init(codec); 3974 3975 if (err) 3976 return err; 3977 3978 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 3979 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 3980 3981 /* make sure downmix information in infoframe is zero */ 3982 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); 3983 3984 /* enable channel-wise remap mode if supported */ 3985 if (has_amd_full_remap_support(codec)) 3986 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 3987 ATI_VERB_SET_MULTICHANNEL_MODE, 3988 ATI_MULTICHANNEL_MODE_SINGLE); 3989 } 3990 codec->auto_runtime_pm = 1; 3991 3992 return 0; 3993 } 3994 3995 /* map from pin NID to port; port is 0-based */ 3996 /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */ 3997 static int atihdmi_pin2port(void *audio_ptr, int pin_nid) 3998 { 3999 return pin_nid / 2 - 1; 4000 } 4001 4002 /* reverse-map from port to pin NID: see above */ 4003 static int atihdmi_port2pin(struct hda_codec *codec, int port) 4004 { 4005 return port * 2 + 3; 4006 } 4007 4008 static const struct drm_audio_component_audio_ops atihdmi_audio_ops = { 4009 .pin2port = atihdmi_pin2port, 4010 .pin_eld_notify = generic_acomp_pin_eld_notify, 4011 .master_bind = generic_acomp_master_bind, 4012 .master_unbind = generic_acomp_master_unbind, 4013 }; 4014 4015 static int patch_atihdmi(struct hda_codec *codec) 4016 { 4017 struct hdmi_spec *spec; 4018 struct hdmi_spec_per_cvt *per_cvt; 4019 int err, cvt_idx; 4020 4021 err = patch_generic_hdmi(codec); 4022 4023 if (err) 4024 return err; 4025 4026 codec->patch_ops.init = atihdmi_init; 4027 4028 spec = codec->spec; 4029 4030 spec->ops.pin_get_eld = atihdmi_pin_get_eld; 4031 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; 4032 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; 4033 spec->ops.setup_stream = atihdmi_setup_stream; 4034 4035 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; 4036 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; 4037 4038 if (!has_amd_full_remap_support(codec)) { 4039 /* override to ATI/AMD-specific versions with pairwise mapping */ 4040 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4041 atihdmi_paired_chmap_cea_alloc_validate_get_type; 4042 spec->chmap.ops.cea_alloc_to_tlv_chmap = 4043 atihdmi_paired_cea_alloc_to_tlv_chmap; 4044 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; 4045 } 4046 4047 /* ATI/AMD converters do not advertise all of their capabilities */ 4048 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 4049 per_cvt = get_cvt(spec, cvt_idx); 4050 per_cvt->channels_max = max(per_cvt->channels_max, 8u); 4051 per_cvt->rates |= SUPPORTED_RATES; 4052 per_cvt->formats |= SUPPORTED_FORMATS; 4053 per_cvt->maxbps = max(per_cvt->maxbps, 24u); 4054 } 4055 4056 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); 4057 4058 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing 4059 * the link-down as is. Tell the core to allow it. 4060 */ 4061 codec->link_down_at_suspend = 1; 4062 4063 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin); 4064 4065 return 0; 4066 } 4067 4068 /* VIA HDMI Implementation */ 4069 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ 4070 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ 4071 4072 static int patch_via_hdmi(struct hda_codec *codec) 4073 { 4074 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); 4075 } 4076 4077 /* 4078 * patch entries 4079 */ 4080 static const struct hda_device_id snd_hda_id_hdmi[] = { 4081 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), 4082 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), 4083 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), 4084 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), 4085 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), 4086 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), 4087 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), 4088 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch), 4089 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4090 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4091 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x), 4092 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4093 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4094 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), 4095 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy), 4096 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy), 4097 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy), 4098 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy), 4099 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy), 4100 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy), 4101 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy), 4102 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy), 4103 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy), 4104 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy), 4105 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy), 4106 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy), 4107 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy), 4108 /* 17 is known to be absent */ 4109 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy), 4110 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy), 4111 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy), 4112 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy), 4113 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy), 4114 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), 4115 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), 4116 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), 4117 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), 4118 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi), 4119 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi), 4120 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), 4121 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), 4122 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), 4123 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), 4124 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), 4125 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), 4126 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), 4127 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi), 4128 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi), 4129 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), 4130 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi), 4131 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), 4132 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi), 4133 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi), 4134 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), 4135 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), 4136 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), 4137 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), 4138 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi), 4139 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi), 4140 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi), 4141 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi), 4142 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi), 4143 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), 4144 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi), 4145 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), 4146 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi), 4147 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), 4148 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), 4149 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi), 4150 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi), 4151 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi), 4152 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi), 4153 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi), 4154 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi), 4155 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi), 4156 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi), 4157 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), 4158 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), 4159 HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi), 4160 HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi), 4161 HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi), 4162 HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi), 4163 HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi), 4164 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), 4165 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), 4166 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), 4167 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), 4168 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), 4169 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), 4170 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4171 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), 4172 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), 4173 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), 4174 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), 4175 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4176 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), 4177 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), 4178 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), 4179 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), 4180 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), 4181 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), 4182 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), 4183 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), 4184 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), 4185 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi), 4186 HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi), 4187 HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi), 4188 HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi), 4189 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), 4190 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), 4191 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), 4192 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), 4193 /* special ID for generic HDMI */ 4194 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), 4195 {} /* terminator */ 4196 }; 4197 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); 4198 4199 MODULE_LICENSE("GPL"); 4200 MODULE_DESCRIPTION("HDMI HD-audio codec"); 4201 MODULE_ALIAS("snd-hda-codec-intelhdmi"); 4202 MODULE_ALIAS("snd-hda-codec-nvhdmi"); 4203 MODULE_ALIAS("snd-hda-codec-atihdmi"); 4204 4205 static struct hda_codec_driver hdmi_driver = { 4206 .id = snd_hda_id_hdmi, 4207 }; 4208 4209 module_hda_codec_driver(hdmi_driver); 4210