1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs 5 * 6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. 7 * Copyright (c) 2006 ATI Technologies Inc. 8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved. 9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com> 10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> 11 * 12 * Authors: 13 * Wu Fengguang <wfg@linux.intel.com> 14 * 15 * Maintained by: 16 * Wu Fengguang <wfg@linux.intel.com> 17 */ 18 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/pci.h> 22 #include <linux/slab.h> 23 #include <linux/module.h> 24 #include <linux/pm_runtime.h> 25 #include <sound/core.h> 26 #include <sound/jack.h> 27 #include <sound/asoundef.h> 28 #include <sound/tlv.h> 29 #include <sound/hdaudio.h> 30 #include <sound/hda_i915.h> 31 #include <sound/hda_chmap.h> 32 #include <sound/hda_codec.h> 33 #include "hda_local.h" 34 #include "hda_jack.h" 35 #include "hda_controller.h" 36 37 static bool static_hdmi_pcm; 38 module_param(static_hdmi_pcm, bool, 0644); 39 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); 40 41 static bool enable_acomp = true; 42 module_param(enable_acomp, bool, 0444); 43 MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)"); 44 45 static bool enable_silent_stream = 46 IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM); 47 module_param(enable_silent_stream, bool, 0644); 48 MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices"); 49 50 static bool enable_all_pins; 51 module_param(enable_all_pins, bool, 0444); 52 MODULE_PARM_DESC(enable_all_pins, "Forcibly enable all pins"); 53 54 struct hdmi_spec_per_cvt { 55 hda_nid_t cvt_nid; 56 bool assigned; /* the stream has been assigned */ 57 bool silent_stream; /* silent stream activated */ 58 unsigned int channels_min; 59 unsigned int channels_max; 60 u32 rates; 61 u64 formats; 62 unsigned int maxbps; 63 }; 64 65 /* max. connections to a widget */ 66 #define HDA_MAX_CONNECTIONS 32 67 68 struct hdmi_spec_per_pin { 69 hda_nid_t pin_nid; 70 int dev_id; 71 /* pin idx, different device entries on the same pin use the same idx */ 72 int pin_nid_idx; 73 int num_mux_nids; 74 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; 75 int mux_idx; 76 hda_nid_t cvt_nid; 77 78 struct hda_codec *codec; 79 struct hdmi_eld sink_eld; 80 struct mutex lock; 81 struct delayed_work work; 82 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ 83 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ 84 int repoll_count; 85 bool setup; /* the stream has been set up by prepare callback */ 86 bool silent_stream; 87 int channels; /* current number of channels */ 88 bool non_pcm; 89 bool chmap_set; /* channel-map override by ALSA API? */ 90 unsigned char chmap[8]; /* ALSA API channel-map */ 91 #ifdef CONFIG_SND_PROC_FS 92 struct snd_info_entry *proc_entry; 93 #endif 94 }; 95 96 /* operations used by generic code that can be overridden by patches */ 97 struct hdmi_ops { 98 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, 99 int dev_id, unsigned char *buf, int *eld_size); 100 101 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, 102 int dev_id, 103 int ca, int active_channels, int conn_type); 104 105 /* enable/disable HBR (HD passthrough) */ 106 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, 107 int dev_id, bool hbr); 108 109 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, 110 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 111 int format); 112 113 void (*pin_cvt_fixup)(struct hda_codec *codec, 114 struct hdmi_spec_per_pin *per_pin, 115 hda_nid_t cvt_nid); 116 }; 117 118 struct hdmi_pcm { 119 struct hda_pcm *pcm; 120 struct snd_jack *jack; 121 struct snd_kcontrol *eld_ctl; 122 }; 123 124 enum { 125 SILENT_STREAM_OFF = 0, 126 SILENT_STREAM_KAE, /* use standard HDA Keep-Alive */ 127 SILENT_STREAM_I915, /* Intel i915 extension */ 128 }; 129 130 struct hdmi_spec { 131 struct hda_codec *codec; 132 int num_cvts; 133 struct snd_array cvts; /* struct hdmi_spec_per_cvt */ 134 hda_nid_t cvt_nids[4]; /* only for haswell fix */ 135 136 /* 137 * num_pins is the number of virtual pins 138 * for example, there are 3 pins, and each pin 139 * has 4 device entries, then the num_pins is 12 140 */ 141 int num_pins; 142 /* 143 * num_nids is the number of real pins 144 * In the above example, num_nids is 3 145 */ 146 int num_nids; 147 /* 148 * dev_num is the number of device entries 149 * on each pin. 150 * In the above example, dev_num is 4 151 */ 152 int dev_num; 153 struct snd_array pins; /* struct hdmi_spec_per_pin */ 154 struct hdmi_pcm pcm_rec[8]; 155 struct mutex pcm_lock; 156 struct mutex bind_lock; /* for audio component binding */ 157 /* pcm_bitmap means which pcms have been assigned to pins*/ 158 unsigned long pcm_bitmap; 159 int pcm_used; /* counter of pcm_rec[] */ 160 /* bitmap shows whether the pcm is opened in user space 161 * bit 0 means the first playback PCM (PCM3); 162 * bit 1 means the second playback PCM, and so on. 163 */ 164 unsigned long pcm_in_use; 165 166 struct hdmi_eld temp_eld; 167 struct hdmi_ops ops; 168 169 bool dyn_pin_out; 170 /* hdmi interrupt trigger control flag for Nvidia codec */ 171 bool hdmi_intr_trig_ctrl; 172 bool nv_dp_workaround; /* workaround DP audio infoframe for Nvidia */ 173 174 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */ 175 /* 176 * Non-generic VIA/NVIDIA specific 177 */ 178 struct hda_multi_out multiout; 179 struct hda_pcm_stream pcm_playback; 180 181 bool use_acomp_notifier; /* use eld_notify callback for hotplug */ 182 bool acomp_registered; /* audio component registered in this driver */ 183 bool force_connect; /* force connectivity */ 184 struct drm_audio_component_audio_ops drm_audio_ops; 185 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */ 186 187 struct hdac_chmap chmap; 188 hda_nid_t vendor_nid; 189 const int *port_map; 190 int port_num; 191 int silent_stream_type; 192 }; 193 194 #ifdef CONFIG_SND_HDA_COMPONENT 195 static inline bool codec_has_acomp(struct hda_codec *codec) 196 { 197 struct hdmi_spec *spec = codec->spec; 198 return spec->use_acomp_notifier; 199 } 200 #else 201 #define codec_has_acomp(codec) false 202 #endif 203 204 struct hdmi_audio_infoframe { 205 u8 type; /* 0x84 */ 206 u8 ver; /* 0x01 */ 207 u8 len; /* 0x0a */ 208 209 u8 checksum; 210 211 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ 212 u8 SS01_SF24; 213 u8 CXT04; 214 u8 CA; 215 u8 LFEPBL01_LSV36_DM_INH7; 216 }; 217 218 struct dp_audio_infoframe { 219 u8 type; /* 0x84 */ 220 u8 len; /* 0x1b */ 221 u8 ver; /* 0x11 << 2 */ 222 223 u8 CC02_CT47; /* match with HDMI infoframe from this on */ 224 u8 SS01_SF24; 225 u8 CXT04; 226 u8 CA; 227 u8 LFEPBL01_LSV36_DM_INH7; 228 }; 229 230 union audio_infoframe { 231 struct hdmi_audio_infoframe hdmi; 232 struct dp_audio_infoframe dp; 233 DECLARE_FLEX_ARRAY(u8, bytes); 234 }; 235 236 /* 237 * HDMI routines 238 */ 239 240 #define get_pin(spec, idx) \ 241 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) 242 #define get_cvt(spec, idx) \ 243 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) 244 /* obtain hdmi_pcm object assigned to idx */ 245 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) 246 /* obtain hda_pcm object assigned to idx */ 247 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) 248 249 static int pin_id_to_pin_index(struct hda_codec *codec, 250 hda_nid_t pin_nid, int dev_id) 251 { 252 struct hdmi_spec *spec = codec->spec; 253 int pin_idx; 254 struct hdmi_spec_per_pin *per_pin; 255 256 /* 257 * (dev_id == -1) means it is NON-MST pin 258 * return the first virtual pin on this port 259 */ 260 if (dev_id == -1) 261 dev_id = 0; 262 263 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 264 per_pin = get_pin(spec, pin_idx); 265 if ((per_pin->pin_nid == pin_nid) && 266 (per_pin->dev_id == dev_id)) 267 return pin_idx; 268 } 269 270 codec_warn(codec, "HDMI: pin NID 0x%x not registered\n", pin_nid); 271 return -EINVAL; 272 } 273 274 static int hinfo_to_pcm_index(struct hda_codec *codec, 275 struct hda_pcm_stream *hinfo) 276 { 277 struct hdmi_spec *spec = codec->spec; 278 int pcm_idx; 279 280 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) 281 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) 282 return pcm_idx; 283 284 codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo); 285 return -EINVAL; 286 } 287 288 static int hinfo_to_pin_index(struct hda_codec *codec, 289 struct hda_pcm_stream *hinfo) 290 { 291 struct hdmi_spec *spec = codec->spec; 292 struct hdmi_spec_per_pin *per_pin; 293 int pin_idx; 294 295 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 296 per_pin = get_pin(spec, pin_idx); 297 if (per_pin->pcm && 298 per_pin->pcm->pcm->stream == hinfo) 299 return pin_idx; 300 } 301 302 codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo, 303 hinfo_to_pcm_index(codec, hinfo)); 304 return -EINVAL; 305 } 306 307 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, 308 int pcm_idx) 309 { 310 int i; 311 struct hdmi_spec_per_pin *per_pin; 312 313 for (i = 0; i < spec->num_pins; i++) { 314 per_pin = get_pin(spec, i); 315 if (per_pin->pcm_idx == pcm_idx) 316 return per_pin; 317 } 318 return NULL; 319 } 320 321 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) 322 { 323 struct hdmi_spec *spec = codec->spec; 324 int cvt_idx; 325 326 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) 327 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) 328 return cvt_idx; 329 330 codec_warn(codec, "HDMI: cvt NID 0x%x not registered\n", cvt_nid); 331 return -EINVAL; 332 } 333 334 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, 335 struct snd_ctl_elem_info *uinfo) 336 { 337 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 338 struct hdmi_spec *spec = codec->spec; 339 struct hdmi_spec_per_pin *per_pin; 340 struct hdmi_eld *eld; 341 int pcm_idx; 342 343 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 344 345 pcm_idx = kcontrol->private_value; 346 mutex_lock(&spec->pcm_lock); 347 per_pin = pcm_idx_to_pin(spec, pcm_idx); 348 if (!per_pin) { 349 /* no pin is bound to the pcm */ 350 uinfo->count = 0; 351 goto unlock; 352 } 353 eld = &per_pin->sink_eld; 354 uinfo->count = eld->eld_valid ? eld->eld_size : 0; 355 356 unlock: 357 mutex_unlock(&spec->pcm_lock); 358 return 0; 359 } 360 361 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, 362 struct snd_ctl_elem_value *ucontrol) 363 { 364 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 365 struct hdmi_spec *spec = codec->spec; 366 struct hdmi_spec_per_pin *per_pin; 367 struct hdmi_eld *eld; 368 int pcm_idx; 369 int err = 0; 370 371 pcm_idx = kcontrol->private_value; 372 mutex_lock(&spec->pcm_lock); 373 per_pin = pcm_idx_to_pin(spec, pcm_idx); 374 if (!per_pin) { 375 /* no pin is bound to the pcm */ 376 memset(ucontrol->value.bytes.data, 0, 377 ARRAY_SIZE(ucontrol->value.bytes.data)); 378 goto unlock; 379 } 380 381 eld = &per_pin->sink_eld; 382 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || 383 eld->eld_size > ELD_MAX_SIZE) { 384 snd_BUG(); 385 err = -EINVAL; 386 goto unlock; 387 } 388 389 memset(ucontrol->value.bytes.data, 0, 390 ARRAY_SIZE(ucontrol->value.bytes.data)); 391 if (eld->eld_valid) 392 memcpy(ucontrol->value.bytes.data, eld->eld_buffer, 393 eld->eld_size); 394 395 unlock: 396 mutex_unlock(&spec->pcm_lock); 397 return err; 398 } 399 400 static const struct snd_kcontrol_new eld_bytes_ctl = { 401 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE | 402 SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK, 403 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 404 .name = "ELD", 405 .info = hdmi_eld_ctl_info, 406 .get = hdmi_eld_ctl_get, 407 }; 408 409 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, 410 int device) 411 { 412 struct snd_kcontrol *kctl; 413 struct hdmi_spec *spec = codec->spec; 414 int err; 415 416 kctl = snd_ctl_new1(&eld_bytes_ctl, codec); 417 if (!kctl) 418 return -ENOMEM; 419 kctl->private_value = pcm_idx; 420 kctl->id.device = device; 421 422 /* no pin nid is associated with the kctl now 423 * tbd: associate pin nid to eld ctl later 424 */ 425 err = snd_hda_ctl_add(codec, 0, kctl); 426 if (err < 0) 427 return err; 428 429 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; 430 return 0; 431 } 432 433 #ifdef BE_PARANOID 434 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 435 int *packet_index, int *byte_index) 436 { 437 int val; 438 439 val = snd_hda_codec_read(codec, pin_nid, 0, 440 AC_VERB_GET_HDMI_DIP_INDEX, 0); 441 442 *packet_index = val >> 5; 443 *byte_index = val & 0x1f; 444 } 445 #endif 446 447 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 448 int packet_index, int byte_index) 449 { 450 int val; 451 452 val = (packet_index << 5) | (byte_index & 0x1f); 453 454 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); 455 } 456 457 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, 458 unsigned char val) 459 { 460 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); 461 } 462 463 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) 464 { 465 struct hdmi_spec *spec = codec->spec; 466 int pin_out; 467 468 /* Unmute */ 469 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 470 snd_hda_codec_write(codec, pin_nid, 0, 471 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); 472 473 if (spec->dyn_pin_out) 474 /* Disable pin out until stream is active */ 475 pin_out = 0; 476 else 477 /* Enable pin out: some machines with GM965 gets broken output 478 * when the pin is disabled or changed while using with HDMI 479 */ 480 pin_out = PIN_OUT; 481 482 snd_hda_codec_write(codec, pin_nid, 0, 483 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); 484 } 485 486 /* 487 * ELD proc files 488 */ 489 490 #ifdef CONFIG_SND_PROC_FS 491 static void print_eld_info(struct snd_info_entry *entry, 492 struct snd_info_buffer *buffer) 493 { 494 struct hdmi_spec_per_pin *per_pin = entry->private_data; 495 496 mutex_lock(&per_pin->lock); 497 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer, per_pin->pin_nid, 498 per_pin->dev_id, per_pin->cvt_nid); 499 mutex_unlock(&per_pin->lock); 500 } 501 502 static void write_eld_info(struct snd_info_entry *entry, 503 struct snd_info_buffer *buffer) 504 { 505 struct hdmi_spec_per_pin *per_pin = entry->private_data; 506 507 mutex_lock(&per_pin->lock); 508 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); 509 mutex_unlock(&per_pin->lock); 510 } 511 512 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) 513 { 514 char name[32]; 515 struct hda_codec *codec = per_pin->codec; 516 struct snd_info_entry *entry; 517 int err; 518 519 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); 520 err = snd_card_proc_new(codec->card, name, &entry); 521 if (err < 0) 522 return err; 523 524 snd_info_set_text_ops(entry, per_pin, print_eld_info); 525 entry->c.text.write = write_eld_info; 526 entry->mode |= 0200; 527 per_pin->proc_entry = entry; 528 529 return 0; 530 } 531 532 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 533 { 534 if (!per_pin->codec->bus->shutdown) { 535 snd_info_free_entry(per_pin->proc_entry); 536 per_pin->proc_entry = NULL; 537 } 538 } 539 #else 540 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, 541 int index) 542 { 543 return 0; 544 } 545 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 546 { 547 } 548 #endif 549 550 /* 551 * Audio InfoFrame routines 552 */ 553 554 /* 555 * Enable Audio InfoFrame Transmission 556 */ 557 static void hdmi_start_infoframe_trans(struct hda_codec *codec, 558 hda_nid_t pin_nid) 559 { 560 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 561 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 562 AC_DIPXMIT_BEST); 563 } 564 565 /* 566 * Disable Audio InfoFrame Transmission 567 */ 568 static void hdmi_stop_infoframe_trans(struct hda_codec *codec, 569 hda_nid_t pin_nid) 570 { 571 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 572 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 573 AC_DIPXMIT_DISABLE); 574 } 575 576 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) 577 { 578 #ifdef CONFIG_SND_DEBUG_VERBOSE 579 int i; 580 int size; 581 582 size = snd_hdmi_get_eld_size(codec, pin_nid); 583 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); 584 585 for (i = 0; i < 8; i++) { 586 size = snd_hda_codec_read(codec, pin_nid, 0, 587 AC_VERB_GET_HDMI_DIP_SIZE, i); 588 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); 589 } 590 #endif 591 } 592 593 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) 594 { 595 #ifdef BE_PARANOID 596 int i, j; 597 int size; 598 int pi, bi; 599 for (i = 0; i < 8; i++) { 600 size = snd_hda_codec_read(codec, pin_nid, 0, 601 AC_VERB_GET_HDMI_DIP_SIZE, i); 602 if (size == 0) 603 continue; 604 605 hdmi_set_dip_index(codec, pin_nid, i, 0x0); 606 for (j = 1; j < 1000; j++) { 607 hdmi_write_dip_byte(codec, pin_nid, 0x0); 608 hdmi_get_dip_index(codec, pin_nid, &pi, &bi); 609 if (pi != i) 610 codec_dbg(codec, "dip index %d: %d != %d\n", 611 bi, pi, i); 612 if (bi == 0) /* byte index wrapped around */ 613 break; 614 } 615 codec_dbg(codec, 616 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", 617 i, size, j); 618 } 619 #endif 620 } 621 622 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) 623 { 624 u8 *bytes = (u8 *)hdmi_ai; 625 u8 sum = 0; 626 int i; 627 628 hdmi_ai->checksum = 0; 629 630 for (i = 0; i < sizeof(*hdmi_ai); i++) 631 sum += bytes[i]; 632 633 hdmi_ai->checksum = -sum; 634 } 635 636 static void hdmi_fill_audio_infoframe(struct hda_codec *codec, 637 hda_nid_t pin_nid, 638 u8 *dip, int size) 639 { 640 int i; 641 642 hdmi_debug_dip_size(codec, pin_nid); 643 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ 644 645 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 646 for (i = 0; i < size; i++) 647 hdmi_write_dip_byte(codec, pin_nid, dip[i]); 648 } 649 650 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, 651 u8 *dip, int size) 652 { 653 u8 val; 654 int i; 655 656 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 657 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) 658 != AC_DIPXMIT_BEST) 659 return false; 660 661 for (i = 0; i < size; i++) { 662 val = snd_hda_codec_read(codec, pin_nid, 0, 663 AC_VERB_GET_HDMI_DIP_DATA, 0); 664 if (val != dip[i]) 665 return false; 666 } 667 668 return true; 669 } 670 671 static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 672 int dev_id, unsigned char *buf, int *eld_size) 673 { 674 snd_hda_set_dev_select(codec, nid, dev_id); 675 676 return snd_hdmi_get_eld(codec, nid, buf, eld_size); 677 } 678 679 static void hdmi_pin_setup_infoframe(struct hda_codec *codec, 680 hda_nid_t pin_nid, int dev_id, 681 int ca, int active_channels, 682 int conn_type) 683 { 684 struct hdmi_spec *spec = codec->spec; 685 union audio_infoframe ai; 686 687 memset(&ai, 0, sizeof(ai)); 688 if ((conn_type == 0) || /* HDMI */ 689 /* Nvidia DisplayPort: Nvidia HW expects same layout as HDMI */ 690 (conn_type == 1 && spec->nv_dp_workaround)) { 691 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; 692 693 if (conn_type == 0) { /* HDMI */ 694 hdmi_ai->type = 0x84; 695 hdmi_ai->ver = 0x01; 696 hdmi_ai->len = 0x0a; 697 } else {/* Nvidia DP */ 698 hdmi_ai->type = 0x84; 699 hdmi_ai->ver = 0x1b; 700 hdmi_ai->len = 0x11 << 2; 701 } 702 hdmi_ai->CC02_CT47 = active_channels - 1; 703 hdmi_ai->CA = ca; 704 hdmi_checksum_audio_infoframe(hdmi_ai); 705 } else if (conn_type == 1) { /* DisplayPort */ 706 struct dp_audio_infoframe *dp_ai = &ai.dp; 707 708 dp_ai->type = 0x84; 709 dp_ai->len = 0x1b; 710 dp_ai->ver = 0x11 << 2; 711 dp_ai->CC02_CT47 = active_channels - 1; 712 dp_ai->CA = ca; 713 } else { 714 codec_dbg(codec, "HDMI: unknown connection type at pin NID 0x%x\n", pin_nid); 715 return; 716 } 717 718 snd_hda_set_dev_select(codec, pin_nid, dev_id); 719 720 /* 721 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or 722 * sizeof(*dp_ai) to avoid partial match/update problems when 723 * the user switches between HDMI/DP monitors. 724 */ 725 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, 726 sizeof(ai))) { 727 codec_dbg(codec, "%s: pin NID=0x%x channels=%d ca=0x%02x\n", 728 __func__, pin_nid, active_channels, ca); 729 hdmi_stop_infoframe_trans(codec, pin_nid); 730 hdmi_fill_audio_infoframe(codec, pin_nid, 731 ai.bytes, sizeof(ai)); 732 hdmi_start_infoframe_trans(codec, pin_nid); 733 } 734 } 735 736 static void hdmi_setup_audio_infoframe(struct hda_codec *codec, 737 struct hdmi_spec_per_pin *per_pin, 738 bool non_pcm) 739 { 740 struct hdmi_spec *spec = codec->spec; 741 struct hdac_chmap *chmap = &spec->chmap; 742 hda_nid_t pin_nid = per_pin->pin_nid; 743 int dev_id = per_pin->dev_id; 744 int channels = per_pin->channels; 745 int active_channels; 746 struct hdmi_eld *eld; 747 int ca; 748 749 if (!channels) 750 return; 751 752 snd_hda_set_dev_select(codec, pin_nid, dev_id); 753 754 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ 755 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 756 snd_hda_codec_write(codec, pin_nid, 0, 757 AC_VERB_SET_AMP_GAIN_MUTE, 758 AMP_OUT_UNMUTE); 759 760 eld = &per_pin->sink_eld; 761 762 ca = snd_hdac_channel_allocation(&codec->core, 763 eld->info.spk_alloc, channels, 764 per_pin->chmap_set, non_pcm, per_pin->chmap); 765 766 active_channels = snd_hdac_get_active_channels(ca); 767 768 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, 769 active_channels); 770 771 /* 772 * always configure channel mapping, it may have been changed by the 773 * user in the meantime 774 */ 775 snd_hdac_setup_channel_mapping(&spec->chmap, 776 pin_nid, non_pcm, ca, channels, 777 per_pin->chmap, per_pin->chmap_set); 778 779 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id, 780 ca, active_channels, eld->info.conn_type); 781 782 per_pin->non_pcm = non_pcm; 783 } 784 785 /* 786 * Unsolicited events 787 */ 788 789 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); 790 791 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, 792 int dev_id) 793 { 794 struct hdmi_spec *spec = codec->spec; 795 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); 796 797 if (pin_idx < 0) 798 return; 799 mutex_lock(&spec->pcm_lock); 800 hdmi_present_sense(get_pin(spec, pin_idx), 1); 801 mutex_unlock(&spec->pcm_lock); 802 } 803 804 static void jack_callback(struct hda_codec *codec, 805 struct hda_jack_callback *jack) 806 { 807 /* stop polling when notification is enabled */ 808 if (codec_has_acomp(codec)) 809 return; 810 811 check_presence_and_report(codec, jack->nid, jack->dev_id); 812 } 813 814 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res, 815 struct hda_jack_tbl *jack) 816 { 817 jack->jack_dirty = 1; 818 819 codec_dbg(codec, 820 "HDMI hot plug event: Codec=%d NID=0x%x Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", 821 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA), 822 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); 823 824 check_presence_and_report(codec, jack->nid, jack->dev_id); 825 } 826 827 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) 828 { 829 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 830 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 831 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); 832 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); 833 834 codec_info(codec, 835 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", 836 codec->addr, 837 tag, 838 subtag, 839 cp_state, 840 cp_ready); 841 842 /* TODO */ 843 if (cp_state) { 844 ; 845 } 846 if (cp_ready) { 847 ; 848 } 849 } 850 851 852 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) 853 { 854 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 855 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 856 struct hda_jack_tbl *jack; 857 858 if (codec_has_acomp(codec)) 859 return; 860 861 if (codec->dp_mst) { 862 int dev_entry = 863 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 864 865 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry); 866 } else { 867 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0); 868 } 869 870 if (!jack) { 871 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); 872 return; 873 } 874 875 if (subtag == 0) 876 hdmi_intrinsic_event(codec, res, jack); 877 else 878 hdmi_non_intrinsic_event(codec, res); 879 } 880 881 static void haswell_verify_D0(struct hda_codec *codec, 882 hda_nid_t cvt_nid, hda_nid_t nid) 883 { 884 int pwr; 885 886 /* For Haswell, the converter 1/2 may keep in D3 state after bootup, 887 * thus pins could only choose converter 0 for use. Make sure the 888 * converters are in correct power state */ 889 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) 890 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); 891 892 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { 893 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, 894 AC_PWRST_D0); 895 msleep(40); 896 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); 897 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; 898 codec_dbg(codec, "Haswell HDMI audio: Power for NID 0x%x is now D%d\n", nid, pwr); 899 } 900 } 901 902 /* 903 * Callbacks 904 */ 905 906 /* HBR should be Non-PCM, 8 channels */ 907 #define is_hbr_format(format) \ 908 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) 909 910 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 911 int dev_id, bool hbr) 912 { 913 int pinctl, new_pinctl; 914 915 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { 916 snd_hda_set_dev_select(codec, pin_nid, dev_id); 917 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 918 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 919 920 if (pinctl < 0) 921 return hbr ? -EINVAL : 0; 922 923 new_pinctl = pinctl & ~AC_PINCTL_EPT; 924 if (hbr) 925 new_pinctl |= AC_PINCTL_EPT_HBR; 926 else 927 new_pinctl |= AC_PINCTL_EPT_NATIVE; 928 929 codec_dbg(codec, 930 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", 931 pin_nid, 932 pinctl == new_pinctl ? "" : "new-", 933 new_pinctl); 934 935 if (pinctl != new_pinctl) 936 snd_hda_codec_write(codec, pin_nid, 0, 937 AC_VERB_SET_PIN_WIDGET_CONTROL, 938 new_pinctl); 939 } else if (hbr) 940 return -EINVAL; 941 942 return 0; 943 } 944 945 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 946 hda_nid_t pin_nid, int dev_id, 947 u32 stream_tag, int format) 948 { 949 struct hdmi_spec *spec = codec->spec; 950 unsigned int param; 951 int err; 952 953 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id, 954 is_hbr_format(format)); 955 956 if (err) { 957 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); 958 return err; 959 } 960 961 if (spec->intel_hsw_fixup) { 962 963 /* 964 * on recent platforms IEC Coding Type is required for HBR 965 * support, read current Digital Converter settings and set 966 * ICT bitfield if needed. 967 */ 968 param = snd_hda_codec_read(codec, cvt_nid, 0, 969 AC_VERB_GET_DIGI_CONVERT_1, 0); 970 971 param = (param >> 16) & ~(AC_DIG3_ICT); 972 973 /* on recent platforms ICT mode is required for HBR support */ 974 if (is_hbr_format(format)) 975 param |= 0x1; 976 977 snd_hda_codec_write(codec, cvt_nid, 0, 978 AC_VERB_SET_DIGI_CONVERT_3, param); 979 } 980 981 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); 982 return 0; 983 } 984 985 /* Try to find an available converter 986 * If pin_idx is less then zero, just try to find an available converter. 987 * Otherwise, try to find an available converter and get the cvt mux index 988 * of the pin. 989 */ 990 static int hdmi_choose_cvt(struct hda_codec *codec, 991 int pin_idx, int *cvt_id, 992 bool silent) 993 { 994 struct hdmi_spec *spec = codec->spec; 995 struct hdmi_spec_per_pin *per_pin; 996 struct hdmi_spec_per_cvt *per_cvt = NULL; 997 int cvt_idx, mux_idx = 0; 998 999 /* pin_idx < 0 means no pin will be bound to the converter */ 1000 if (pin_idx < 0) 1001 per_pin = NULL; 1002 else 1003 per_pin = get_pin(spec, pin_idx); 1004 1005 if (per_pin && per_pin->silent_stream) { 1006 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid); 1007 per_cvt = get_cvt(spec, cvt_idx); 1008 if (per_cvt->assigned && !silent) 1009 return -EBUSY; 1010 if (cvt_id) 1011 *cvt_id = cvt_idx; 1012 return 0; 1013 } 1014 1015 /* Dynamically assign converter to stream */ 1016 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1017 per_cvt = get_cvt(spec, cvt_idx); 1018 1019 /* Must not already be assigned */ 1020 if (per_cvt->assigned || per_cvt->silent_stream) 1021 continue; 1022 if (per_pin == NULL) 1023 break; 1024 /* Must be in pin's mux's list of converters */ 1025 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1026 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) 1027 break; 1028 /* Not in mux list */ 1029 if (mux_idx == per_pin->num_mux_nids) 1030 continue; 1031 break; 1032 } 1033 1034 /* No free converters */ 1035 if (cvt_idx == spec->num_cvts) 1036 return -EBUSY; 1037 1038 if (per_pin != NULL) 1039 per_pin->mux_idx = mux_idx; 1040 1041 if (cvt_id) 1042 *cvt_id = cvt_idx; 1043 1044 return 0; 1045 } 1046 1047 /* Assure the pin select the right convetor */ 1048 static void intel_verify_pin_cvt_connect(struct hda_codec *codec, 1049 struct hdmi_spec_per_pin *per_pin) 1050 { 1051 hda_nid_t pin_nid = per_pin->pin_nid; 1052 int mux_idx, curr; 1053 1054 mux_idx = per_pin->mux_idx; 1055 curr = snd_hda_codec_read(codec, pin_nid, 0, 1056 AC_VERB_GET_CONNECT_SEL, 0); 1057 if (curr != mux_idx) 1058 snd_hda_codec_write_cache(codec, pin_nid, 0, 1059 AC_VERB_SET_CONNECT_SEL, 1060 mux_idx); 1061 } 1062 1063 /* get the mux index for the converter of the pins 1064 * converter's mux index is the same for all pins on Intel platform 1065 */ 1066 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, 1067 hda_nid_t cvt_nid) 1068 { 1069 int i; 1070 1071 for (i = 0; i < spec->num_cvts; i++) 1072 if (spec->cvt_nids[i] == cvt_nid) 1073 return i; 1074 return -EINVAL; 1075 } 1076 1077 /* Intel HDMI workaround to fix audio routing issue: 1078 * For some Intel display codecs, pins share the same connection list. 1079 * So a conveter can be selected by multiple pins and playback on any of these 1080 * pins will generate sound on the external display, because audio flows from 1081 * the same converter to the display pipeline. Also muting one pin may make 1082 * other pins have no sound output. 1083 * So this function assures that an assigned converter for a pin is not selected 1084 * by any other pins. 1085 */ 1086 static void intel_not_share_assigned_cvt(struct hda_codec *codec, 1087 hda_nid_t pin_nid, 1088 int dev_id, int mux_idx) 1089 { 1090 struct hdmi_spec *spec = codec->spec; 1091 hda_nid_t nid; 1092 int cvt_idx, curr; 1093 struct hdmi_spec_per_cvt *per_cvt; 1094 struct hdmi_spec_per_pin *per_pin; 1095 int pin_idx; 1096 1097 /* configure the pins connections */ 1098 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 1099 int dev_id_saved; 1100 int dev_num; 1101 1102 per_pin = get_pin(spec, pin_idx); 1103 /* 1104 * pin not connected to monitor 1105 * no need to operate on it 1106 */ 1107 if (!per_pin->pcm) 1108 continue; 1109 1110 if ((per_pin->pin_nid == pin_nid) && 1111 (per_pin->dev_id == dev_id)) 1112 continue; 1113 1114 /* 1115 * if per_pin->dev_id >= dev_num, 1116 * snd_hda_get_dev_select() will fail, 1117 * and the following operation is unpredictable. 1118 * So skip this situation. 1119 */ 1120 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; 1121 if (per_pin->dev_id >= dev_num) 1122 continue; 1123 1124 nid = per_pin->pin_nid; 1125 1126 /* 1127 * Calling this function should not impact 1128 * on the device entry selection 1129 * So let's save the dev id for each pin, 1130 * and restore it when return 1131 */ 1132 dev_id_saved = snd_hda_get_dev_select(codec, nid); 1133 snd_hda_set_dev_select(codec, nid, per_pin->dev_id); 1134 curr = snd_hda_codec_read(codec, nid, 0, 1135 AC_VERB_GET_CONNECT_SEL, 0); 1136 if (curr != mux_idx) { 1137 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1138 continue; 1139 } 1140 1141 1142 /* choose an unassigned converter. The conveters in the 1143 * connection list are in the same order as in the codec. 1144 */ 1145 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1146 per_cvt = get_cvt(spec, cvt_idx); 1147 if (!per_cvt->assigned) { 1148 codec_dbg(codec, 1149 "choose cvt %d for pin NID 0x%x\n", 1150 cvt_idx, nid); 1151 snd_hda_codec_write_cache(codec, nid, 0, 1152 AC_VERB_SET_CONNECT_SEL, 1153 cvt_idx); 1154 break; 1155 } 1156 } 1157 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1158 } 1159 } 1160 1161 /* A wrapper of intel_not_share_asigned_cvt() */ 1162 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, 1163 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) 1164 { 1165 int mux_idx; 1166 struct hdmi_spec *spec = codec->spec; 1167 1168 /* On Intel platform, the mapping of converter nid to 1169 * mux index of the pins are always the same. 1170 * The pin nid may be 0, this means all pins will not 1171 * share the converter. 1172 */ 1173 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); 1174 if (mux_idx >= 0) 1175 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); 1176 } 1177 1178 /* skeleton caller of pin_cvt_fixup ops */ 1179 static void pin_cvt_fixup(struct hda_codec *codec, 1180 struct hdmi_spec_per_pin *per_pin, 1181 hda_nid_t cvt_nid) 1182 { 1183 struct hdmi_spec *spec = codec->spec; 1184 1185 if (spec->ops.pin_cvt_fixup) 1186 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); 1187 } 1188 1189 /* called in hdmi_pcm_open when no pin is assigned to the PCM */ 1190 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, 1191 struct hda_codec *codec, 1192 struct snd_pcm_substream *substream) 1193 { 1194 struct hdmi_spec *spec = codec->spec; 1195 struct snd_pcm_runtime *runtime = substream->runtime; 1196 int cvt_idx, pcm_idx; 1197 struct hdmi_spec_per_cvt *per_cvt = NULL; 1198 int err; 1199 1200 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1201 if (pcm_idx < 0) 1202 return -EINVAL; 1203 1204 err = hdmi_choose_cvt(codec, -1, &cvt_idx, false); 1205 if (err) 1206 return err; 1207 1208 per_cvt = get_cvt(spec, cvt_idx); 1209 per_cvt->assigned = true; 1210 hinfo->nid = per_cvt->cvt_nid; 1211 1212 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); 1213 1214 set_bit(pcm_idx, &spec->pcm_in_use); 1215 /* todo: setup spdif ctls assign */ 1216 1217 /* Initially set the converter's capabilities */ 1218 hinfo->channels_min = per_cvt->channels_min; 1219 hinfo->channels_max = per_cvt->channels_max; 1220 hinfo->rates = per_cvt->rates; 1221 hinfo->formats = per_cvt->formats; 1222 hinfo->maxbps = per_cvt->maxbps; 1223 1224 /* Store the updated parameters */ 1225 runtime->hw.channels_min = hinfo->channels_min; 1226 runtime->hw.channels_max = hinfo->channels_max; 1227 runtime->hw.formats = hinfo->formats; 1228 runtime->hw.rates = hinfo->rates; 1229 1230 snd_pcm_hw_constraint_step(substream->runtime, 0, 1231 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1232 return 0; 1233 } 1234 1235 /* 1236 * HDA PCM callbacks 1237 */ 1238 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, 1239 struct hda_codec *codec, 1240 struct snd_pcm_substream *substream) 1241 { 1242 struct hdmi_spec *spec = codec->spec; 1243 struct snd_pcm_runtime *runtime = substream->runtime; 1244 int pin_idx, cvt_idx, pcm_idx; 1245 struct hdmi_spec_per_pin *per_pin; 1246 struct hdmi_eld *eld; 1247 struct hdmi_spec_per_cvt *per_cvt = NULL; 1248 int err; 1249 1250 /* Validate hinfo */ 1251 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1252 if (pcm_idx < 0) 1253 return -EINVAL; 1254 1255 mutex_lock(&spec->pcm_lock); 1256 pin_idx = hinfo_to_pin_index(codec, hinfo); 1257 /* no pin is assigned to the PCM 1258 * PA need pcm open successfully when probe 1259 */ 1260 if (pin_idx < 0) { 1261 err = hdmi_pcm_open_no_pin(hinfo, codec, substream); 1262 goto unlock; 1263 } 1264 1265 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, false); 1266 if (err < 0) 1267 goto unlock; 1268 1269 per_cvt = get_cvt(spec, cvt_idx); 1270 /* Claim converter */ 1271 per_cvt->assigned = true; 1272 1273 set_bit(pcm_idx, &spec->pcm_in_use); 1274 per_pin = get_pin(spec, pin_idx); 1275 per_pin->cvt_nid = per_cvt->cvt_nid; 1276 hinfo->nid = per_cvt->cvt_nid; 1277 1278 /* flip stripe flag for the assigned stream if supported */ 1279 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE) 1280 azx_stream(get_azx_dev(substream))->stripe = 1; 1281 1282 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1283 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1284 AC_VERB_SET_CONNECT_SEL, 1285 per_pin->mux_idx); 1286 1287 /* configure unused pins to choose other converters */ 1288 pin_cvt_fixup(codec, per_pin, 0); 1289 1290 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); 1291 1292 /* Initially set the converter's capabilities */ 1293 hinfo->channels_min = per_cvt->channels_min; 1294 hinfo->channels_max = per_cvt->channels_max; 1295 hinfo->rates = per_cvt->rates; 1296 hinfo->formats = per_cvt->formats; 1297 hinfo->maxbps = per_cvt->maxbps; 1298 1299 eld = &per_pin->sink_eld; 1300 /* Restrict capabilities by ELD if this isn't disabled */ 1301 if (!static_hdmi_pcm && eld->eld_valid) { 1302 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); 1303 if (hinfo->channels_min > hinfo->channels_max || 1304 !hinfo->rates || !hinfo->formats) { 1305 per_cvt->assigned = false; 1306 hinfo->nid = 0; 1307 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1308 err = -ENODEV; 1309 goto unlock; 1310 } 1311 } 1312 1313 /* Store the updated parameters */ 1314 runtime->hw.channels_min = hinfo->channels_min; 1315 runtime->hw.channels_max = hinfo->channels_max; 1316 runtime->hw.formats = hinfo->formats; 1317 runtime->hw.rates = hinfo->rates; 1318 1319 snd_pcm_hw_constraint_step(substream->runtime, 0, 1320 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1321 unlock: 1322 mutex_unlock(&spec->pcm_lock); 1323 return err; 1324 } 1325 1326 /* 1327 * HDA/HDMI auto parsing 1328 */ 1329 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) 1330 { 1331 struct hdmi_spec *spec = codec->spec; 1332 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1333 hda_nid_t pin_nid = per_pin->pin_nid; 1334 int dev_id = per_pin->dev_id; 1335 int conns; 1336 1337 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { 1338 codec_warn(codec, 1339 "HDMI: pin NID 0x%x wcaps %#x does not support connection list\n", 1340 pin_nid, get_wcaps(codec, pin_nid)); 1341 return -EINVAL; 1342 } 1343 1344 snd_hda_set_dev_select(codec, pin_nid, dev_id); 1345 1346 if (spec->intel_hsw_fixup) { 1347 conns = spec->num_cvts; 1348 memcpy(per_pin->mux_nids, spec->cvt_nids, 1349 sizeof(hda_nid_t) * conns); 1350 } else { 1351 conns = snd_hda_get_raw_connections(codec, pin_nid, 1352 per_pin->mux_nids, 1353 HDA_MAX_CONNECTIONS); 1354 } 1355 1356 /* all the device entries on the same pin have the same conn list */ 1357 per_pin->num_mux_nids = conns; 1358 1359 return 0; 1360 } 1361 1362 static int hdmi_find_pcm_slot(struct hdmi_spec *spec, 1363 struct hdmi_spec_per_pin *per_pin) 1364 { 1365 int i; 1366 1367 for (i = 0; i < spec->pcm_used; i++) { 1368 if (!test_bit(i, &spec->pcm_bitmap)) 1369 return i; 1370 } 1371 return -EBUSY; 1372 } 1373 1374 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, 1375 struct hdmi_spec_per_pin *per_pin) 1376 { 1377 int idx; 1378 1379 /* pcm already be attached to the pin */ 1380 if (per_pin->pcm) 1381 return; 1382 idx = hdmi_find_pcm_slot(spec, per_pin); 1383 if (idx == -EBUSY) 1384 return; 1385 per_pin->pcm_idx = idx; 1386 per_pin->pcm = get_hdmi_pcm(spec, idx); 1387 set_bit(idx, &spec->pcm_bitmap); 1388 } 1389 1390 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, 1391 struct hdmi_spec_per_pin *per_pin) 1392 { 1393 int idx; 1394 1395 /* pcm already be detached from the pin */ 1396 if (!per_pin->pcm) 1397 return; 1398 idx = per_pin->pcm_idx; 1399 per_pin->pcm_idx = -1; 1400 per_pin->pcm = NULL; 1401 if (idx >= 0 && idx < spec->pcm_used) 1402 clear_bit(idx, &spec->pcm_bitmap); 1403 } 1404 1405 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, 1406 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) 1407 { 1408 int mux_idx; 1409 1410 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1411 if (per_pin->mux_nids[mux_idx] == cvt_nid) 1412 break; 1413 return mux_idx; 1414 } 1415 1416 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); 1417 1418 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, 1419 struct hdmi_spec_per_pin *per_pin) 1420 { 1421 struct hda_codec *codec = per_pin->codec; 1422 struct hda_pcm *pcm; 1423 struct hda_pcm_stream *hinfo; 1424 struct snd_pcm_substream *substream; 1425 int mux_idx; 1426 bool non_pcm; 1427 1428 if (per_pin->pcm_idx < 0 || per_pin->pcm_idx >= spec->pcm_used) 1429 return; 1430 pcm = get_pcm_rec(spec, per_pin->pcm_idx); 1431 if (!pcm->pcm) 1432 return; 1433 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) 1434 return; 1435 1436 /* hdmi audio only uses playback and one substream */ 1437 hinfo = pcm->stream; 1438 substream = pcm->pcm->streams[0].substream; 1439 1440 per_pin->cvt_nid = hinfo->nid; 1441 1442 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); 1443 if (mux_idx < per_pin->num_mux_nids) { 1444 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1445 per_pin->dev_id); 1446 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1447 AC_VERB_SET_CONNECT_SEL, 1448 mux_idx); 1449 } 1450 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); 1451 1452 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); 1453 if (substream->runtime) 1454 per_pin->channels = substream->runtime->channels; 1455 per_pin->setup = true; 1456 per_pin->mux_idx = mux_idx; 1457 1458 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1459 } 1460 1461 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, 1462 struct hdmi_spec_per_pin *per_pin) 1463 { 1464 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1465 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); 1466 1467 per_pin->chmap_set = false; 1468 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1469 1470 per_pin->setup = false; 1471 per_pin->channels = 0; 1472 } 1473 1474 static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec, 1475 struct hdmi_spec_per_pin *per_pin) 1476 { 1477 struct hdmi_spec *spec = codec->spec; 1478 1479 if (per_pin->pcm_idx >= 0) 1480 return spec->pcm_rec[per_pin->pcm_idx].jack; 1481 else 1482 return NULL; 1483 } 1484 1485 /* update per_pin ELD from the given new ELD; 1486 * setup info frame and notification accordingly 1487 * also notify ELD kctl and report jack status changes 1488 */ 1489 static void update_eld(struct hda_codec *codec, 1490 struct hdmi_spec_per_pin *per_pin, 1491 struct hdmi_eld *eld, 1492 int repoll) 1493 { 1494 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 1495 struct hdmi_spec *spec = codec->spec; 1496 struct snd_jack *pcm_jack; 1497 bool old_eld_valid = pin_eld->eld_valid; 1498 bool eld_changed; 1499 int pcm_idx; 1500 1501 if (eld->eld_valid) { 1502 if (eld->eld_size <= 0 || 1503 snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, 1504 eld->eld_size) < 0) { 1505 eld->eld_valid = false; 1506 if (repoll) { 1507 schedule_delayed_work(&per_pin->work, 1508 msecs_to_jiffies(300)); 1509 return; 1510 } 1511 } 1512 } 1513 1514 if (!eld->eld_valid || eld->eld_size <= 0 || eld->info.sad_count <= 0) { 1515 eld->eld_valid = false; 1516 eld->eld_size = 0; 1517 } 1518 1519 /* for monitor disconnection, save pcm_idx firstly */ 1520 pcm_idx = per_pin->pcm_idx; 1521 1522 /* 1523 * pcm_idx >=0 before update_eld() means it is in monitor 1524 * disconnected event. Jack must be fetched before update_eld(). 1525 */ 1526 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); 1527 1528 if (eld->eld_valid) { 1529 hdmi_attach_hda_pcm(spec, per_pin); 1530 hdmi_pcm_setup_pin(spec, per_pin); 1531 } else { 1532 hdmi_pcm_reset_pin(spec, per_pin); 1533 hdmi_detach_hda_pcm(spec, per_pin); 1534 } 1535 /* if pcm_idx == -1, it means this is in monitor connection event 1536 * we can get the correct pcm_idx now. 1537 */ 1538 if (pcm_idx == -1) 1539 pcm_idx = per_pin->pcm_idx; 1540 if (!pcm_jack) 1541 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); 1542 1543 if (eld->eld_valid) 1544 snd_hdmi_show_eld(codec, &eld->info); 1545 1546 eld_changed = (pin_eld->eld_valid != eld->eld_valid); 1547 eld_changed |= (pin_eld->monitor_present != eld->monitor_present); 1548 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid) 1549 if (pin_eld->eld_size != eld->eld_size || 1550 memcmp(pin_eld->eld_buffer, eld->eld_buffer, 1551 eld->eld_size) != 0) 1552 eld_changed = true; 1553 1554 if (eld_changed) { 1555 pin_eld->monitor_present = eld->monitor_present; 1556 pin_eld->eld_valid = eld->eld_valid; 1557 pin_eld->eld_size = eld->eld_size; 1558 if (eld->eld_valid) 1559 memcpy(pin_eld->eld_buffer, eld->eld_buffer, 1560 eld->eld_size); 1561 pin_eld->info = eld->info; 1562 } 1563 1564 /* 1565 * Re-setup pin and infoframe. This is needed e.g. when 1566 * - sink is first plugged-in 1567 * - transcoder can change during stream playback on Haswell 1568 * and this can make HW reset converter selection on a pin. 1569 */ 1570 if (eld->eld_valid && !old_eld_valid && per_pin->setup) { 1571 pin_cvt_fixup(codec, per_pin, 0); 1572 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1573 } 1574 1575 if (eld_changed && pcm_idx >= 0) 1576 snd_ctl_notify(codec->card, 1577 SNDRV_CTL_EVENT_MASK_VALUE | 1578 SNDRV_CTL_EVENT_MASK_INFO, 1579 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); 1580 1581 if (eld_changed && pcm_jack) 1582 snd_jack_report(pcm_jack, 1583 (eld->monitor_present && eld->eld_valid) ? 1584 SND_JACK_AVOUT : 0); 1585 } 1586 1587 /* update ELD and jack state via HD-audio verbs */ 1588 static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, 1589 int repoll) 1590 { 1591 struct hda_codec *codec = per_pin->codec; 1592 struct hdmi_spec *spec = codec->spec; 1593 struct hdmi_eld *eld = &spec->temp_eld; 1594 struct device *dev = hda_codec_dev(codec); 1595 hda_nid_t pin_nid = per_pin->pin_nid; 1596 int dev_id = per_pin->dev_id; 1597 /* 1598 * Always execute a GetPinSense verb here, even when called from 1599 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited 1600 * response's PD bit is not the real PD value, but indicates that 1601 * the real PD value changed. An older version of the HD-audio 1602 * specification worked this way. Hence, we just ignore the data in 1603 * the unsolicited response to avoid custom WARs. 1604 */ 1605 int present; 1606 int ret; 1607 1608 #ifdef CONFIG_PM 1609 if (dev->power.runtime_status == RPM_SUSPENDING) 1610 return; 1611 #endif 1612 1613 ret = snd_hda_power_up_pm(codec); 1614 if (ret < 0 && pm_runtime_suspended(dev)) 1615 goto out; 1616 1617 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id); 1618 1619 mutex_lock(&per_pin->lock); 1620 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); 1621 if (eld->monitor_present) 1622 eld->eld_valid = !!(present & AC_PINSENSE_ELDV); 1623 else 1624 eld->eld_valid = false; 1625 1626 codec_dbg(codec, 1627 "HDMI status: Codec=%d NID=0x%x Presence_Detect=%d ELD_Valid=%d\n", 1628 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); 1629 1630 if (eld->eld_valid) { 1631 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id, 1632 eld->eld_buffer, &eld->eld_size) < 0) 1633 eld->eld_valid = false; 1634 } 1635 1636 update_eld(codec, per_pin, eld, repoll); 1637 mutex_unlock(&per_pin->lock); 1638 out: 1639 snd_hda_power_down_pm(codec); 1640 } 1641 1642 #define I915_SILENT_RATE 48000 1643 #define I915_SILENT_CHANNELS 2 1644 #define I915_SILENT_FORMAT SNDRV_PCM_FORMAT_S16_LE 1645 #define I915_SILENT_FORMAT_BITS 16 1646 #define I915_SILENT_FMT_MASK 0xf 1647 1648 static void silent_stream_enable_i915(struct hda_codec *codec, 1649 struct hdmi_spec_per_pin *per_pin) 1650 { 1651 unsigned int format; 1652 1653 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, 1654 per_pin->dev_id, I915_SILENT_RATE); 1655 1656 /* trigger silent stream generation in hw */ 1657 format = snd_hdac_calc_stream_format(I915_SILENT_RATE, I915_SILENT_CHANNELS, 1658 I915_SILENT_FORMAT, I915_SILENT_FORMAT_BITS, 0); 1659 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, 1660 I915_SILENT_FMT_MASK, I915_SILENT_FMT_MASK, format); 1661 usleep_range(100, 200); 1662 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, I915_SILENT_FMT_MASK, 0, format); 1663 1664 per_pin->channels = I915_SILENT_CHANNELS; 1665 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1666 } 1667 1668 static void silent_stream_set_kae(struct hda_codec *codec, 1669 struct hdmi_spec_per_pin *per_pin, 1670 bool enable) 1671 { 1672 unsigned int param; 1673 1674 codec_dbg(codec, "HDMI: KAE %d cvt-NID=0x%x\n", enable, per_pin->cvt_nid); 1675 1676 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, AC_VERB_GET_DIGI_CONVERT_1, 0); 1677 param = (param >> 16) & 0xff; 1678 1679 if (enable) 1680 param |= AC_DIG3_KAE; 1681 else 1682 param &= ~AC_DIG3_KAE; 1683 1684 snd_hda_codec_write(codec, per_pin->cvt_nid, 0, AC_VERB_SET_DIGI_CONVERT_3, param); 1685 } 1686 1687 static void silent_stream_enable(struct hda_codec *codec, 1688 struct hdmi_spec_per_pin *per_pin) 1689 { 1690 struct hdmi_spec *spec = codec->spec; 1691 struct hdmi_spec_per_cvt *per_cvt; 1692 int cvt_idx, pin_idx, err; 1693 int keep_power = 0; 1694 1695 /* 1696 * Power-up will call hdmi_present_sense, so the PM calls 1697 * have to be done without mutex held. 1698 */ 1699 1700 err = snd_hda_power_up_pm(codec); 1701 if (err < 0 && err != -EACCES) { 1702 codec_err(codec, 1703 "Failed to power up codec for silent stream enable ret=[%d]\n", err); 1704 snd_hda_power_down_pm(codec); 1705 return; 1706 } 1707 1708 mutex_lock(&per_pin->lock); 1709 1710 if (per_pin->setup) { 1711 codec_dbg(codec, "hdmi: PCM already open, no silent stream\n"); 1712 err = -EBUSY; 1713 goto unlock_out; 1714 } 1715 1716 pin_idx = pin_id_to_pin_index(codec, per_pin->pin_nid, per_pin->dev_id); 1717 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, true); 1718 if (err) { 1719 codec_err(codec, "hdmi: no free converter to enable silent mode\n"); 1720 goto unlock_out; 1721 } 1722 1723 per_cvt = get_cvt(spec, cvt_idx); 1724 per_cvt->silent_stream = true; 1725 per_pin->cvt_nid = per_cvt->cvt_nid; 1726 per_pin->silent_stream = true; 1727 1728 codec_dbg(codec, "hdmi: enabling silent stream pin-NID=0x%x cvt-NID=0x%x\n", 1729 per_pin->pin_nid, per_cvt->cvt_nid); 1730 1731 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1732 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1733 AC_VERB_SET_CONNECT_SEL, 1734 per_pin->mux_idx); 1735 1736 /* configure unused pins to choose other converters */ 1737 pin_cvt_fixup(codec, per_pin, 0); 1738 1739 switch (spec->silent_stream_type) { 1740 case SILENT_STREAM_KAE: 1741 silent_stream_set_kae(codec, per_pin, true); 1742 break; 1743 case SILENT_STREAM_I915: 1744 silent_stream_enable_i915(codec, per_pin); 1745 keep_power = 1; 1746 break; 1747 default: 1748 break; 1749 } 1750 1751 unlock_out: 1752 mutex_unlock(&per_pin->lock); 1753 1754 if (err || !keep_power) 1755 snd_hda_power_down_pm(codec); 1756 } 1757 1758 static void silent_stream_disable(struct hda_codec *codec, 1759 struct hdmi_spec_per_pin *per_pin) 1760 { 1761 struct hdmi_spec *spec = codec->spec; 1762 struct hdmi_spec_per_cvt *per_cvt; 1763 int cvt_idx, err; 1764 1765 err = snd_hda_power_up_pm(codec); 1766 if (err < 0 && err != -EACCES) { 1767 codec_err(codec, 1768 "Failed to power up codec for silent stream disable ret=[%d]\n", 1769 err); 1770 snd_hda_power_down_pm(codec); 1771 return; 1772 } 1773 1774 mutex_lock(&per_pin->lock); 1775 if (!per_pin->silent_stream) 1776 goto unlock_out; 1777 1778 codec_dbg(codec, "HDMI: disable silent stream on pin-NID=0x%x cvt-NID=0x%x\n", 1779 per_pin->pin_nid, per_pin->cvt_nid); 1780 1781 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid); 1782 if (cvt_idx >= 0 && cvt_idx < spec->num_cvts) { 1783 per_cvt = get_cvt(spec, cvt_idx); 1784 per_cvt->silent_stream = false; 1785 } 1786 1787 if (spec->silent_stream_type == SILENT_STREAM_I915) { 1788 /* release ref taken in silent_stream_enable() */ 1789 snd_hda_power_down_pm(codec); 1790 } else if (spec->silent_stream_type == SILENT_STREAM_KAE) { 1791 silent_stream_set_kae(codec, per_pin, false); 1792 } 1793 1794 per_pin->cvt_nid = 0; 1795 per_pin->silent_stream = false; 1796 1797 unlock_out: 1798 mutex_unlock(&per_pin->lock); 1799 1800 snd_hda_power_down_pm(codec); 1801 } 1802 1803 /* update ELD and jack state via audio component */ 1804 static void sync_eld_via_acomp(struct hda_codec *codec, 1805 struct hdmi_spec_per_pin *per_pin) 1806 { 1807 struct hdmi_spec *spec = codec->spec; 1808 struct hdmi_eld *eld = &spec->temp_eld; 1809 bool monitor_prev, monitor_next; 1810 1811 mutex_lock(&per_pin->lock); 1812 eld->monitor_present = false; 1813 monitor_prev = per_pin->sink_eld.monitor_present; 1814 eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, 1815 per_pin->dev_id, &eld->monitor_present, 1816 eld->eld_buffer, ELD_MAX_SIZE); 1817 eld->eld_valid = (eld->eld_size > 0); 1818 update_eld(codec, per_pin, eld, 0); 1819 monitor_next = per_pin->sink_eld.monitor_present; 1820 mutex_unlock(&per_pin->lock); 1821 1822 if (spec->silent_stream_type) { 1823 if (!monitor_prev && monitor_next) 1824 silent_stream_enable(codec, per_pin); 1825 else if (monitor_prev && !monitor_next) 1826 silent_stream_disable(codec, per_pin); 1827 } 1828 } 1829 1830 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) 1831 { 1832 struct hda_codec *codec = per_pin->codec; 1833 1834 if (!codec_has_acomp(codec)) 1835 hdmi_present_sense_via_verbs(per_pin, repoll); 1836 else 1837 sync_eld_via_acomp(codec, per_pin); 1838 } 1839 1840 static void hdmi_repoll_eld(struct work_struct *work) 1841 { 1842 struct hdmi_spec_per_pin *per_pin = 1843 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); 1844 struct hda_codec *codec = per_pin->codec; 1845 struct hdmi_spec *spec = codec->spec; 1846 struct hda_jack_tbl *jack; 1847 1848 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid, 1849 per_pin->dev_id); 1850 if (jack) 1851 jack->jack_dirty = 1; 1852 1853 if (per_pin->repoll_count++ > 6) 1854 per_pin->repoll_count = 0; 1855 1856 mutex_lock(&spec->pcm_lock); 1857 hdmi_present_sense(per_pin, per_pin->repoll_count); 1858 mutex_unlock(&spec->pcm_lock); 1859 } 1860 1861 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) 1862 { 1863 struct hdmi_spec *spec = codec->spec; 1864 unsigned int caps, config; 1865 int pin_idx; 1866 struct hdmi_spec_per_pin *per_pin; 1867 int err; 1868 int dev_num, i; 1869 1870 caps = snd_hda_query_pin_caps(codec, pin_nid); 1871 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) 1872 return 0; 1873 1874 /* 1875 * For DP MST audio, Configuration Default is the same for 1876 * all device entries on the same pin 1877 */ 1878 config = snd_hda_codec_get_pincfg(codec, pin_nid); 1879 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE && 1880 !spec->force_connect) 1881 return 0; 1882 1883 /* 1884 * To simplify the implementation, malloc all 1885 * the virtual pins in the initialization statically 1886 */ 1887 if (spec->intel_hsw_fixup) { 1888 /* 1889 * On Intel platforms, device entries count returned 1890 * by AC_PAR_DEVLIST_LEN is dynamic, and depends on 1891 * the type of receiver that is connected. Allocate pin 1892 * structures based on worst case. 1893 */ 1894 dev_num = spec->dev_num; 1895 } else if (codec->dp_mst) { 1896 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; 1897 /* 1898 * spec->dev_num is the maxinum number of device entries 1899 * among all the pins 1900 */ 1901 spec->dev_num = (spec->dev_num > dev_num) ? 1902 spec->dev_num : dev_num; 1903 } else { 1904 /* 1905 * If the platform doesn't support DP MST, 1906 * manually set dev_num to 1. This means 1907 * the pin has only one device entry. 1908 */ 1909 dev_num = 1; 1910 spec->dev_num = 1; 1911 } 1912 1913 for (i = 0; i < dev_num; i++) { 1914 pin_idx = spec->num_pins; 1915 per_pin = snd_array_new(&spec->pins); 1916 1917 if (!per_pin) 1918 return -ENOMEM; 1919 1920 per_pin->pcm = NULL; 1921 per_pin->pcm_idx = -1; 1922 per_pin->pin_nid = pin_nid; 1923 per_pin->pin_nid_idx = spec->num_nids; 1924 per_pin->dev_id = i; 1925 per_pin->non_pcm = false; 1926 snd_hda_set_dev_select(codec, pin_nid, i); 1927 err = hdmi_read_pin_conn(codec, pin_idx); 1928 if (err < 0) 1929 return err; 1930 if (!is_jack_detectable(codec, pin_nid)) 1931 codec_warn(codec, "HDMI: pin NID 0x%x - jack not detectable\n", pin_nid); 1932 spec->num_pins++; 1933 } 1934 spec->num_nids++; 1935 1936 return 0; 1937 } 1938 1939 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1940 { 1941 struct hdmi_spec *spec = codec->spec; 1942 struct hdmi_spec_per_cvt *per_cvt; 1943 unsigned int chans; 1944 int err; 1945 1946 chans = get_wcaps(codec, cvt_nid); 1947 chans = get_wcaps_channels(chans); 1948 1949 per_cvt = snd_array_new(&spec->cvts); 1950 if (!per_cvt) 1951 return -ENOMEM; 1952 1953 per_cvt->cvt_nid = cvt_nid; 1954 per_cvt->channels_min = 2; 1955 if (chans <= 16) { 1956 per_cvt->channels_max = chans; 1957 if (chans > spec->chmap.channels_max) 1958 spec->chmap.channels_max = chans; 1959 } 1960 1961 err = snd_hda_query_supported_pcm(codec, cvt_nid, 1962 &per_cvt->rates, 1963 &per_cvt->formats, 1964 &per_cvt->maxbps); 1965 if (err < 0) 1966 return err; 1967 1968 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) 1969 spec->cvt_nids[spec->num_cvts] = cvt_nid; 1970 spec->num_cvts++; 1971 1972 return 0; 1973 } 1974 1975 static const struct snd_pci_quirk force_connect_list[] = { 1976 SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1), 1977 SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1), 1978 SND_PCI_QUIRK(0x1462, 0xec94, "MS-7C94", 1), 1979 SND_PCI_QUIRK(0x8086, 0x2081, "Intel NUC 10", 1), 1980 {} 1981 }; 1982 1983 static int hdmi_parse_codec(struct hda_codec *codec) 1984 { 1985 struct hdmi_spec *spec = codec->spec; 1986 hda_nid_t start_nid; 1987 unsigned int caps; 1988 int i, nodes; 1989 const struct snd_pci_quirk *q; 1990 1991 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid); 1992 if (!start_nid || nodes < 0) { 1993 codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); 1994 return -EINVAL; 1995 } 1996 1997 if (enable_all_pins) 1998 spec->force_connect = true; 1999 2000 q = snd_pci_quirk_lookup(codec->bus->pci, force_connect_list); 2001 2002 if (q && q->value) 2003 spec->force_connect = true; 2004 2005 /* 2006 * hdmi_add_pin() assumes total amount of converters to 2007 * be known, so first discover all converters 2008 */ 2009 for (i = 0; i < nodes; i++) { 2010 hda_nid_t nid = start_nid + i; 2011 2012 caps = get_wcaps(codec, nid); 2013 2014 if (!(caps & AC_WCAP_DIGITAL)) 2015 continue; 2016 2017 if (get_wcaps_type(caps) == AC_WID_AUD_OUT) 2018 hdmi_add_cvt(codec, nid); 2019 } 2020 2021 /* discover audio pins */ 2022 for (i = 0; i < nodes; i++) { 2023 hda_nid_t nid = start_nid + i; 2024 2025 caps = get_wcaps(codec, nid); 2026 2027 if (!(caps & AC_WCAP_DIGITAL)) 2028 continue; 2029 2030 if (get_wcaps_type(caps) == AC_WID_PIN) 2031 hdmi_add_pin(codec, nid); 2032 } 2033 2034 return 0; 2035 } 2036 2037 /* 2038 */ 2039 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 2040 { 2041 struct hda_spdif_out *spdif; 2042 bool non_pcm; 2043 2044 mutex_lock(&codec->spdif_mutex); 2045 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); 2046 /* Add sanity check to pass klockwork check. 2047 * This should never happen. 2048 */ 2049 if (WARN_ON(spdif == NULL)) { 2050 mutex_unlock(&codec->spdif_mutex); 2051 return true; 2052 } 2053 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); 2054 mutex_unlock(&codec->spdif_mutex); 2055 return non_pcm; 2056 } 2057 2058 /* 2059 * HDMI callbacks 2060 */ 2061 2062 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 2063 struct hda_codec *codec, 2064 unsigned int stream_tag, 2065 unsigned int format, 2066 struct snd_pcm_substream *substream) 2067 { 2068 hda_nid_t cvt_nid = hinfo->nid; 2069 struct hdmi_spec *spec = codec->spec; 2070 int pin_idx; 2071 struct hdmi_spec_per_pin *per_pin; 2072 struct snd_pcm_runtime *runtime = substream->runtime; 2073 bool non_pcm; 2074 int pinctl, stripe; 2075 int err = 0; 2076 2077 mutex_lock(&spec->pcm_lock); 2078 pin_idx = hinfo_to_pin_index(codec, hinfo); 2079 if (pin_idx < 0) { 2080 /* when pcm is not bound to a pin skip pin setup and return 0 2081 * to make audio playback be ongoing 2082 */ 2083 pin_cvt_fixup(codec, NULL, cvt_nid); 2084 snd_hda_codec_setup_stream(codec, cvt_nid, 2085 stream_tag, 0, format); 2086 goto unlock; 2087 } 2088 2089 if (snd_BUG_ON(pin_idx < 0)) { 2090 err = -EINVAL; 2091 goto unlock; 2092 } 2093 per_pin = get_pin(spec, pin_idx); 2094 2095 /* Verify pin:cvt selections to avoid silent audio after S3. 2096 * After S3, the audio driver restores pin:cvt selections 2097 * but this can happen before gfx is ready and such selection 2098 * is overlooked by HW. Thus multiple pins can share a same 2099 * default convertor and mute control will affect each other, 2100 * which can cause a resumed audio playback become silent 2101 * after S3. 2102 */ 2103 pin_cvt_fixup(codec, per_pin, 0); 2104 2105 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ 2106 /* Todo: add DP1.2 MST audio support later */ 2107 if (codec_has_acomp(codec)) 2108 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, 2109 per_pin->dev_id, runtime->rate); 2110 2111 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); 2112 mutex_lock(&per_pin->lock); 2113 per_pin->channels = substream->runtime->channels; 2114 per_pin->setup = true; 2115 2116 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) { 2117 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core, 2118 substream); 2119 snd_hda_codec_write(codec, cvt_nid, 0, 2120 AC_VERB_SET_STRIPE_CONTROL, 2121 stripe); 2122 } 2123 2124 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 2125 mutex_unlock(&per_pin->lock); 2126 if (spec->dyn_pin_out) { 2127 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2128 per_pin->dev_id); 2129 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2130 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2131 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2132 AC_VERB_SET_PIN_WIDGET_CONTROL, 2133 pinctl | PIN_OUT); 2134 } 2135 2136 /* snd_hda_set_dev_select() has been called before */ 2137 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid, 2138 per_pin->dev_id, stream_tag, format); 2139 unlock: 2140 mutex_unlock(&spec->pcm_lock); 2141 return err; 2142 } 2143 2144 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 2145 struct hda_codec *codec, 2146 struct snd_pcm_substream *substream) 2147 { 2148 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 2149 return 0; 2150 } 2151 2152 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, 2153 struct hda_codec *codec, 2154 struct snd_pcm_substream *substream) 2155 { 2156 struct hdmi_spec *spec = codec->spec; 2157 int cvt_idx, pin_idx, pcm_idx; 2158 struct hdmi_spec_per_cvt *per_cvt; 2159 struct hdmi_spec_per_pin *per_pin; 2160 int pinctl; 2161 int err = 0; 2162 2163 mutex_lock(&spec->pcm_lock); 2164 if (hinfo->nid) { 2165 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 2166 if (snd_BUG_ON(pcm_idx < 0)) { 2167 err = -EINVAL; 2168 goto unlock; 2169 } 2170 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); 2171 if (snd_BUG_ON(cvt_idx < 0)) { 2172 err = -EINVAL; 2173 goto unlock; 2174 } 2175 per_cvt = get_cvt(spec, cvt_idx); 2176 per_cvt->assigned = false; 2177 hinfo->nid = 0; 2178 2179 azx_stream(get_azx_dev(substream))->stripe = 0; 2180 2181 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2182 clear_bit(pcm_idx, &spec->pcm_in_use); 2183 pin_idx = hinfo_to_pin_index(codec, hinfo); 2184 if (pin_idx < 0) 2185 goto unlock; 2186 2187 if (snd_BUG_ON(pin_idx < 0)) { 2188 err = -EINVAL; 2189 goto unlock; 2190 } 2191 per_pin = get_pin(spec, pin_idx); 2192 2193 if (spec->dyn_pin_out) { 2194 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2195 per_pin->dev_id); 2196 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2197 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2198 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2199 AC_VERB_SET_PIN_WIDGET_CONTROL, 2200 pinctl & ~PIN_OUT); 2201 } 2202 2203 mutex_lock(&per_pin->lock); 2204 per_pin->chmap_set = false; 2205 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 2206 2207 per_pin->setup = false; 2208 per_pin->channels = 0; 2209 mutex_unlock(&per_pin->lock); 2210 } 2211 2212 unlock: 2213 mutex_unlock(&spec->pcm_lock); 2214 2215 return err; 2216 } 2217 2218 static const struct hda_pcm_ops generic_ops = { 2219 .open = hdmi_pcm_open, 2220 .close = hdmi_pcm_close, 2221 .prepare = generic_hdmi_playback_pcm_prepare, 2222 .cleanup = generic_hdmi_playback_pcm_cleanup, 2223 }; 2224 2225 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) 2226 { 2227 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2228 struct hdmi_spec *spec = codec->spec; 2229 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2230 2231 if (!per_pin) 2232 return 0; 2233 2234 return per_pin->sink_eld.info.spk_alloc; 2235 } 2236 2237 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, 2238 unsigned char *chmap) 2239 { 2240 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2241 struct hdmi_spec *spec = codec->spec; 2242 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2243 2244 /* chmap is already set to 0 in caller */ 2245 if (!per_pin) 2246 return; 2247 2248 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); 2249 } 2250 2251 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, 2252 unsigned char *chmap, int prepared) 2253 { 2254 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2255 struct hdmi_spec *spec = codec->spec; 2256 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2257 2258 if (!per_pin) 2259 return; 2260 mutex_lock(&per_pin->lock); 2261 per_pin->chmap_set = true; 2262 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); 2263 if (prepared) 2264 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 2265 mutex_unlock(&per_pin->lock); 2266 } 2267 2268 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) 2269 { 2270 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2271 struct hdmi_spec *spec = codec->spec; 2272 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2273 2274 return per_pin ? true:false; 2275 } 2276 2277 static int generic_hdmi_build_pcms(struct hda_codec *codec) 2278 { 2279 struct hdmi_spec *spec = codec->spec; 2280 int idx, pcm_num; 2281 2282 /* limit the PCM devices to the codec converters */ 2283 pcm_num = spec->num_cvts; 2284 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num); 2285 2286 for (idx = 0; idx < pcm_num; idx++) { 2287 struct hda_pcm *info; 2288 struct hda_pcm_stream *pstr; 2289 2290 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); 2291 if (!info) 2292 return -ENOMEM; 2293 2294 spec->pcm_rec[idx].pcm = info; 2295 spec->pcm_used++; 2296 info->pcm_type = HDA_PCM_TYPE_HDMI; 2297 info->own_chmap = true; 2298 2299 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2300 pstr->substreams = 1; 2301 pstr->ops = generic_ops; 2302 /* pcm number is less than pcm_rec array size */ 2303 if (spec->pcm_used >= ARRAY_SIZE(spec->pcm_rec)) 2304 break; 2305 /* other pstr fields are set in open */ 2306 } 2307 2308 return 0; 2309 } 2310 2311 static void free_hdmi_jack_priv(struct snd_jack *jack) 2312 { 2313 struct hdmi_pcm *pcm = jack->private_data; 2314 2315 pcm->jack = NULL; 2316 } 2317 2318 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) 2319 { 2320 char hdmi_str[32] = "HDMI/DP"; 2321 struct hdmi_spec *spec = codec->spec; 2322 struct snd_jack *jack; 2323 int pcmdev = get_pcm_rec(spec, pcm_idx)->device; 2324 int err; 2325 2326 if (pcmdev > 0) 2327 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); 2328 2329 err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack, 2330 true, false); 2331 if (err < 0) 2332 return err; 2333 2334 spec->pcm_rec[pcm_idx].jack = jack; 2335 jack->private_data = &spec->pcm_rec[pcm_idx]; 2336 jack->private_free = free_hdmi_jack_priv; 2337 return 0; 2338 } 2339 2340 static int generic_hdmi_build_controls(struct hda_codec *codec) 2341 { 2342 struct hdmi_spec *spec = codec->spec; 2343 int dev, err; 2344 int pin_idx, pcm_idx; 2345 2346 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2347 if (!get_pcm_rec(spec, pcm_idx)->pcm) { 2348 /* no PCM: mark this for skipping permanently */ 2349 set_bit(pcm_idx, &spec->pcm_bitmap); 2350 continue; 2351 } 2352 2353 err = generic_hdmi_build_jack(codec, pcm_idx); 2354 if (err < 0) 2355 return err; 2356 2357 /* create the spdif for each pcm 2358 * pin will be bound when monitor is connected 2359 */ 2360 err = snd_hda_create_dig_out_ctls(codec, 2361 0, spec->cvt_nids[0], 2362 HDA_PCM_TYPE_HDMI); 2363 if (err < 0) 2364 return err; 2365 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2366 2367 dev = get_pcm_rec(spec, pcm_idx)->device; 2368 if (dev != SNDRV_PCM_INVALID_DEVICE) { 2369 /* add control for ELD Bytes */ 2370 err = hdmi_create_eld_ctl(codec, pcm_idx, dev); 2371 if (err < 0) 2372 return err; 2373 } 2374 } 2375 2376 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2377 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2378 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 2379 2380 pin_eld->eld_valid = false; 2381 hdmi_present_sense(per_pin, 0); 2382 } 2383 2384 /* add channel maps */ 2385 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2386 struct hda_pcm *pcm; 2387 2388 pcm = get_pcm_rec(spec, pcm_idx); 2389 if (!pcm || !pcm->pcm) 2390 break; 2391 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); 2392 if (err < 0) 2393 return err; 2394 } 2395 2396 return 0; 2397 } 2398 2399 static int generic_hdmi_init_per_pins(struct hda_codec *codec) 2400 { 2401 struct hdmi_spec *spec = codec->spec; 2402 int pin_idx; 2403 2404 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2405 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2406 2407 per_pin->codec = codec; 2408 mutex_init(&per_pin->lock); 2409 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); 2410 eld_proc_new(per_pin, pin_idx); 2411 } 2412 return 0; 2413 } 2414 2415 static int generic_hdmi_init(struct hda_codec *codec) 2416 { 2417 struct hdmi_spec *spec = codec->spec; 2418 int pin_idx; 2419 2420 mutex_lock(&spec->bind_lock); 2421 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2422 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2423 hda_nid_t pin_nid = per_pin->pin_nid; 2424 int dev_id = per_pin->dev_id; 2425 2426 snd_hda_set_dev_select(codec, pin_nid, dev_id); 2427 hdmi_init_pin(codec, pin_nid); 2428 if (codec_has_acomp(codec)) 2429 continue; 2430 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id, 2431 jack_callback); 2432 } 2433 mutex_unlock(&spec->bind_lock); 2434 return 0; 2435 } 2436 2437 static void hdmi_array_init(struct hdmi_spec *spec, int nums) 2438 { 2439 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); 2440 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); 2441 } 2442 2443 static void hdmi_array_free(struct hdmi_spec *spec) 2444 { 2445 snd_array_free(&spec->pins); 2446 snd_array_free(&spec->cvts); 2447 } 2448 2449 static void generic_spec_free(struct hda_codec *codec) 2450 { 2451 struct hdmi_spec *spec = codec->spec; 2452 2453 if (spec) { 2454 hdmi_array_free(spec); 2455 kfree(spec); 2456 codec->spec = NULL; 2457 } 2458 codec->dp_mst = false; 2459 } 2460 2461 static void generic_hdmi_free(struct hda_codec *codec) 2462 { 2463 struct hdmi_spec *spec = codec->spec; 2464 int pin_idx, pcm_idx; 2465 2466 if (spec->acomp_registered) { 2467 snd_hdac_acomp_exit(&codec->bus->core); 2468 } else if (codec_has_acomp(codec)) { 2469 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL); 2470 } 2471 codec->relaxed_resume = 0; 2472 2473 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2474 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2475 cancel_delayed_work_sync(&per_pin->work); 2476 eld_proc_free(per_pin); 2477 } 2478 2479 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2480 if (spec->pcm_rec[pcm_idx].jack == NULL) 2481 continue; 2482 snd_device_free(codec->card, spec->pcm_rec[pcm_idx].jack); 2483 } 2484 2485 generic_spec_free(codec); 2486 } 2487 2488 #ifdef CONFIG_PM 2489 static int generic_hdmi_suspend(struct hda_codec *codec) 2490 { 2491 struct hdmi_spec *spec = codec->spec; 2492 int pin_idx; 2493 2494 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2495 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2496 cancel_delayed_work_sync(&per_pin->work); 2497 } 2498 return 0; 2499 } 2500 2501 static int generic_hdmi_resume(struct hda_codec *codec) 2502 { 2503 struct hdmi_spec *spec = codec->spec; 2504 int pin_idx; 2505 2506 codec->patch_ops.init(codec); 2507 snd_hda_regmap_sync(codec); 2508 2509 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2510 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2511 hdmi_present_sense(per_pin, 1); 2512 } 2513 return 0; 2514 } 2515 #endif 2516 2517 static const struct hda_codec_ops generic_hdmi_patch_ops = { 2518 .init = generic_hdmi_init, 2519 .free = generic_hdmi_free, 2520 .build_pcms = generic_hdmi_build_pcms, 2521 .build_controls = generic_hdmi_build_controls, 2522 .unsol_event = hdmi_unsol_event, 2523 #ifdef CONFIG_PM 2524 .suspend = generic_hdmi_suspend, 2525 .resume = generic_hdmi_resume, 2526 #endif 2527 }; 2528 2529 static const struct hdmi_ops generic_standard_hdmi_ops = { 2530 .pin_get_eld = hdmi_pin_get_eld, 2531 .pin_setup_infoframe = hdmi_pin_setup_infoframe, 2532 .pin_hbr_setup = hdmi_pin_hbr_setup, 2533 .setup_stream = hdmi_setup_stream, 2534 }; 2535 2536 /* allocate codec->spec and assign/initialize generic parser ops */ 2537 static int alloc_generic_hdmi(struct hda_codec *codec) 2538 { 2539 struct hdmi_spec *spec; 2540 2541 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2542 if (!spec) 2543 return -ENOMEM; 2544 2545 spec->codec = codec; 2546 spec->ops = generic_standard_hdmi_ops; 2547 spec->dev_num = 1; /* initialize to 1 */ 2548 mutex_init(&spec->pcm_lock); 2549 mutex_init(&spec->bind_lock); 2550 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); 2551 2552 spec->chmap.ops.get_chmap = hdmi_get_chmap; 2553 spec->chmap.ops.set_chmap = hdmi_set_chmap; 2554 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; 2555 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc; 2556 2557 codec->spec = spec; 2558 hdmi_array_init(spec, 4); 2559 2560 codec->patch_ops = generic_hdmi_patch_ops; 2561 2562 return 0; 2563 } 2564 2565 /* generic HDMI parser */ 2566 static int patch_generic_hdmi(struct hda_codec *codec) 2567 { 2568 int err; 2569 2570 err = alloc_generic_hdmi(codec); 2571 if (err < 0) 2572 return err; 2573 2574 err = hdmi_parse_codec(codec); 2575 if (err < 0) { 2576 generic_spec_free(codec); 2577 return err; 2578 } 2579 2580 generic_hdmi_init_per_pins(codec); 2581 return 0; 2582 } 2583 2584 /* 2585 * generic audio component binding 2586 */ 2587 2588 /* turn on / off the unsol event jack detection dynamically */ 2589 static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid, 2590 int dev_id, bool use_acomp) 2591 { 2592 struct hda_jack_tbl *tbl; 2593 2594 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id); 2595 if (tbl) { 2596 /* clear unsol even if component notifier is used, or re-enable 2597 * if notifier is cleared 2598 */ 2599 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag); 2600 snd_hda_codec_write_cache(codec, nid, 0, 2601 AC_VERB_SET_UNSOLICITED_ENABLE, val); 2602 } 2603 } 2604 2605 /* set up / clear component notifier dynamically */ 2606 static void generic_acomp_notifier_set(struct drm_audio_component *acomp, 2607 bool use_acomp) 2608 { 2609 struct hdmi_spec *spec; 2610 int i; 2611 2612 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops); 2613 mutex_lock(&spec->bind_lock); 2614 spec->use_acomp_notifier = use_acomp; 2615 spec->codec->relaxed_resume = use_acomp; 2616 spec->codec->bus->keep_power = 0; 2617 /* reprogram each jack detection logic depending on the notifier */ 2618 for (i = 0; i < spec->num_pins; i++) 2619 reprogram_jack_detect(spec->codec, 2620 get_pin(spec, i)->pin_nid, 2621 get_pin(spec, i)->dev_id, 2622 use_acomp); 2623 mutex_unlock(&spec->bind_lock); 2624 } 2625 2626 /* enable / disable the notifier via master bind / unbind */ 2627 static int generic_acomp_master_bind(struct device *dev, 2628 struct drm_audio_component *acomp) 2629 { 2630 generic_acomp_notifier_set(acomp, true); 2631 return 0; 2632 } 2633 2634 static void generic_acomp_master_unbind(struct device *dev, 2635 struct drm_audio_component *acomp) 2636 { 2637 generic_acomp_notifier_set(acomp, false); 2638 } 2639 2640 /* check whether both HD-audio and DRM PCI devices belong to the same bus */ 2641 static int match_bound_vga(struct device *dev, int subtype, void *data) 2642 { 2643 struct hdac_bus *bus = data; 2644 struct pci_dev *pci, *master; 2645 2646 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev)) 2647 return 0; 2648 master = to_pci_dev(bus->dev); 2649 pci = to_pci_dev(dev); 2650 return master->bus == pci->bus; 2651 } 2652 2653 /* audio component notifier for AMD/Nvidia HDMI codecs */ 2654 static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id) 2655 { 2656 struct hda_codec *codec = audio_ptr; 2657 struct hdmi_spec *spec = codec->spec; 2658 hda_nid_t pin_nid = spec->port2pin(codec, port); 2659 2660 if (!pin_nid) 2661 return; 2662 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN) 2663 return; 2664 /* skip notification during system suspend (but not in runtime PM); 2665 * the state will be updated at resume 2666 */ 2667 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND) 2668 return; 2669 2670 check_presence_and_report(codec, pin_nid, dev_id); 2671 } 2672 2673 /* set up the private drm_audio_ops from the template */ 2674 static void setup_drm_audio_ops(struct hda_codec *codec, 2675 const struct drm_audio_component_audio_ops *ops) 2676 { 2677 struct hdmi_spec *spec = codec->spec; 2678 2679 spec->drm_audio_ops.audio_ptr = codec; 2680 /* intel_audio_codec_enable() or intel_audio_codec_disable() 2681 * will call pin_eld_notify with using audio_ptr pointer 2682 * We need make sure audio_ptr is really setup 2683 */ 2684 wmb(); 2685 spec->drm_audio_ops.pin2port = ops->pin2port; 2686 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify; 2687 spec->drm_audio_ops.master_bind = ops->master_bind; 2688 spec->drm_audio_ops.master_unbind = ops->master_unbind; 2689 } 2690 2691 /* initialize the generic HDMI audio component */ 2692 static void generic_acomp_init(struct hda_codec *codec, 2693 const struct drm_audio_component_audio_ops *ops, 2694 int (*port2pin)(struct hda_codec *, int)) 2695 { 2696 struct hdmi_spec *spec = codec->spec; 2697 2698 if (!enable_acomp) { 2699 codec_info(codec, "audio component disabled by module option\n"); 2700 return; 2701 } 2702 2703 spec->port2pin = port2pin; 2704 setup_drm_audio_ops(codec, ops); 2705 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops, 2706 match_bound_vga, 0)) { 2707 spec->acomp_registered = true; 2708 } 2709 } 2710 2711 /* 2712 * Intel codec parsers and helpers 2713 */ 2714 2715 #define INTEL_GET_VENDOR_VERB 0xf81 2716 #define INTEL_SET_VENDOR_VERB 0x781 2717 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ 2718 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ 2719 2720 static void intel_haswell_enable_all_pins(struct hda_codec *codec, 2721 bool update_tree) 2722 { 2723 unsigned int vendor_param; 2724 struct hdmi_spec *spec = codec->spec; 2725 2726 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2727 INTEL_GET_VENDOR_VERB, 0); 2728 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) 2729 return; 2730 2731 vendor_param |= INTEL_EN_ALL_PIN_CVTS; 2732 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2733 INTEL_SET_VENDOR_VERB, vendor_param); 2734 if (vendor_param == -1) 2735 return; 2736 2737 if (update_tree) 2738 snd_hda_codec_update_widgets(codec); 2739 } 2740 2741 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) 2742 { 2743 unsigned int vendor_param; 2744 struct hdmi_spec *spec = codec->spec; 2745 2746 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2747 INTEL_GET_VENDOR_VERB, 0); 2748 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) 2749 return; 2750 2751 /* enable DP1.2 mode */ 2752 vendor_param |= INTEL_EN_DP12; 2753 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); 2754 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, 2755 INTEL_SET_VENDOR_VERB, vendor_param); 2756 } 2757 2758 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. 2759 * Otherwise you may get severe h/w communication errors. 2760 */ 2761 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, 2762 unsigned int power_state) 2763 { 2764 if (power_state == AC_PWRST_D0) { 2765 intel_haswell_enable_all_pins(codec, false); 2766 intel_haswell_fixup_enable_dp12(codec); 2767 } 2768 2769 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); 2770 snd_hda_codec_set_power_to_all(codec, fg, power_state); 2771 } 2772 2773 /* There is a fixed mapping between audio pin node and display port. 2774 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL: 2775 * Pin Widget 5 - PORT B (port = 1 in i915 driver) 2776 * Pin Widget 6 - PORT C (port = 2 in i915 driver) 2777 * Pin Widget 7 - PORT D (port = 3 in i915 driver) 2778 * 2779 * on VLV, ILK: 2780 * Pin Widget 4 - PORT B (port = 1 in i915 driver) 2781 * Pin Widget 5 - PORT C (port = 2 in i915 driver) 2782 * Pin Widget 6 - PORT D (port = 3 in i915 driver) 2783 */ 2784 static int intel_base_nid(struct hda_codec *codec) 2785 { 2786 switch (codec->core.vendor_id) { 2787 case 0x80860054: /* ILK */ 2788 case 0x80862804: /* ILK */ 2789 case 0x80862882: /* VLV */ 2790 return 4; 2791 default: 2792 return 5; 2793 } 2794 } 2795 2796 static int intel_pin2port(void *audio_ptr, int pin_nid) 2797 { 2798 struct hda_codec *codec = audio_ptr; 2799 struct hdmi_spec *spec = codec->spec; 2800 int base_nid, i; 2801 2802 if (!spec->port_num) { 2803 base_nid = intel_base_nid(codec); 2804 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3)) 2805 return -1; 2806 return pin_nid - base_nid + 1; 2807 } 2808 2809 /* 2810 * looking for the pin number in the mapping table and return 2811 * the index which indicate the port number 2812 */ 2813 for (i = 0; i < spec->port_num; i++) { 2814 if (pin_nid == spec->port_map[i]) 2815 return i; 2816 } 2817 2818 codec_info(codec, "Can't find the HDMI/DP port for pin NID 0x%x\n", pin_nid); 2819 return -1; 2820 } 2821 2822 static int intel_port2pin(struct hda_codec *codec, int port) 2823 { 2824 struct hdmi_spec *spec = codec->spec; 2825 2826 if (!spec->port_num) { 2827 /* we assume only from port-B to port-D */ 2828 if (port < 1 || port > 3) 2829 return 0; 2830 return port + intel_base_nid(codec) - 1; 2831 } 2832 2833 if (port < 0 || port >= spec->port_num) 2834 return 0; 2835 return spec->port_map[port]; 2836 } 2837 2838 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) 2839 { 2840 struct hda_codec *codec = audio_ptr; 2841 int pin_nid; 2842 int dev_id = pipe; 2843 2844 pin_nid = intel_port2pin(codec, port); 2845 if (!pin_nid) 2846 return; 2847 /* skip notification during system suspend (but not in runtime PM); 2848 * the state will be updated at resume 2849 */ 2850 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND) 2851 return; 2852 2853 snd_hdac_i915_set_bclk(&codec->bus->core); 2854 check_presence_and_report(codec, pin_nid, dev_id); 2855 } 2856 2857 static const struct drm_audio_component_audio_ops intel_audio_ops = { 2858 .pin2port = intel_pin2port, 2859 .pin_eld_notify = intel_pin_eld_notify, 2860 }; 2861 2862 /* register i915 component pin_eld_notify callback */ 2863 static void register_i915_notifier(struct hda_codec *codec) 2864 { 2865 struct hdmi_spec *spec = codec->spec; 2866 2867 spec->use_acomp_notifier = true; 2868 spec->port2pin = intel_port2pin; 2869 setup_drm_audio_ops(codec, &intel_audio_ops); 2870 snd_hdac_acomp_register_notifier(&codec->bus->core, 2871 &spec->drm_audio_ops); 2872 /* no need for forcible resume for jack check thanks to notifier */ 2873 codec->relaxed_resume = 1; 2874 } 2875 2876 /* setup_stream ops override for HSW+ */ 2877 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 2878 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 2879 int format) 2880 { 2881 haswell_verify_D0(codec, cvt_nid, pin_nid); 2882 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 2883 stream_tag, format); 2884 } 2885 2886 /* pin_cvt_fixup ops override for HSW+ and VLV+ */ 2887 static void i915_pin_cvt_fixup(struct hda_codec *codec, 2888 struct hdmi_spec_per_pin *per_pin, 2889 hda_nid_t cvt_nid) 2890 { 2891 if (per_pin) { 2892 haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid); 2893 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2894 per_pin->dev_id); 2895 intel_verify_pin_cvt_connect(codec, per_pin); 2896 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, 2897 per_pin->dev_id, per_pin->mux_idx); 2898 } else { 2899 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); 2900 } 2901 } 2902 2903 /* precondition and allocation for Intel codecs */ 2904 static int alloc_intel_hdmi(struct hda_codec *codec) 2905 { 2906 int err; 2907 2908 /* requires i915 binding */ 2909 if (!codec->bus->core.audio_component) { 2910 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); 2911 /* set probe_id here to prevent generic fallback binding */ 2912 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE; 2913 return -ENODEV; 2914 } 2915 2916 err = alloc_generic_hdmi(codec); 2917 if (err < 0) 2918 return err; 2919 /* no need to handle unsol events */ 2920 codec->patch_ops.unsol_event = NULL; 2921 return 0; 2922 } 2923 2924 /* parse and post-process for Intel codecs */ 2925 static int parse_intel_hdmi(struct hda_codec *codec) 2926 { 2927 int err, retries = 3; 2928 2929 do { 2930 err = hdmi_parse_codec(codec); 2931 } while (err < 0 && retries--); 2932 2933 if (err < 0) { 2934 generic_spec_free(codec); 2935 return err; 2936 } 2937 2938 generic_hdmi_init_per_pins(codec); 2939 register_i915_notifier(codec); 2940 return 0; 2941 } 2942 2943 /* Intel Haswell and onwards; audio component with eld notifier */ 2944 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid, 2945 const int *port_map, int port_num, int dev_num, 2946 bool send_silent_stream) 2947 { 2948 struct hdmi_spec *spec; 2949 int err; 2950 2951 err = alloc_intel_hdmi(codec); 2952 if (err < 0) 2953 return err; 2954 spec = codec->spec; 2955 codec->dp_mst = true; 2956 spec->vendor_nid = vendor_nid; 2957 spec->port_map = port_map; 2958 spec->port_num = port_num; 2959 spec->intel_hsw_fixup = true; 2960 spec->dev_num = dev_num; 2961 2962 intel_haswell_enable_all_pins(codec, true); 2963 intel_haswell_fixup_enable_dp12(codec); 2964 2965 codec->display_power_control = 1; 2966 2967 codec->patch_ops.set_power_state = haswell_set_power_state; 2968 codec->depop_delay = 0; 2969 codec->auto_runtime_pm = 1; 2970 2971 spec->ops.setup_stream = i915_hsw_setup_stream; 2972 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2973 2974 /* 2975 * Enable silent stream feature, if it is enabled via 2976 * module param or Kconfig option 2977 */ 2978 if (send_silent_stream) 2979 spec->silent_stream_type = SILENT_STREAM_I915; 2980 2981 return parse_intel_hdmi(codec); 2982 } 2983 2984 static int patch_i915_hsw_hdmi(struct hda_codec *codec) 2985 { 2986 return intel_hsw_common_init(codec, 0x08, NULL, 0, 3, 2987 enable_silent_stream); 2988 } 2989 2990 static int patch_i915_glk_hdmi(struct hda_codec *codec) 2991 { 2992 /* 2993 * Silent stream calls audio component .get_power() from 2994 * .pin_eld_notify(). On GLK this will deadlock in i915 due 2995 * to the audio vs. CDCLK workaround. 2996 */ 2997 return intel_hsw_common_init(codec, 0x0b, NULL, 0, 3, false); 2998 } 2999 3000 static int patch_i915_icl_hdmi(struct hda_codec *codec) 3001 { 3002 /* 3003 * pin to port mapping table where the value indicate the pin number and 3004 * the index indicate the port number. 3005 */ 3006 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb}; 3007 3008 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 3, 3009 enable_silent_stream); 3010 } 3011 3012 static int patch_i915_tgl_hdmi(struct hda_codec *codec) 3013 { 3014 /* 3015 * pin to port mapping table where the value indicate the pin number and 3016 * the index indicate the port number. 3017 */ 3018 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf}; 3019 3020 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 4, 3021 enable_silent_stream); 3022 } 3023 3024 static int patch_i915_adlp_hdmi(struct hda_codec *codec) 3025 { 3026 struct hdmi_spec *spec; 3027 int res; 3028 3029 res = patch_i915_tgl_hdmi(codec); 3030 if (!res) { 3031 spec = codec->spec; 3032 3033 if (spec->silent_stream_type) 3034 spec->silent_stream_type = SILENT_STREAM_KAE; 3035 } 3036 3037 return res; 3038 } 3039 3040 /* Intel Baytrail and Braswell; with eld notifier */ 3041 static int patch_i915_byt_hdmi(struct hda_codec *codec) 3042 { 3043 struct hdmi_spec *spec; 3044 int err; 3045 3046 err = alloc_intel_hdmi(codec); 3047 if (err < 0) 3048 return err; 3049 spec = codec->spec; 3050 3051 /* For Valleyview/Cherryview, only the display codec is in the display 3052 * power well and can use link_power ops to request/release the power. 3053 */ 3054 codec->display_power_control = 1; 3055 3056 codec->depop_delay = 0; 3057 codec->auto_runtime_pm = 1; 3058 3059 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 3060 3061 return parse_intel_hdmi(codec); 3062 } 3063 3064 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ 3065 static int patch_i915_cpt_hdmi(struct hda_codec *codec) 3066 { 3067 int err; 3068 3069 err = alloc_intel_hdmi(codec); 3070 if (err < 0) 3071 return err; 3072 return parse_intel_hdmi(codec); 3073 } 3074 3075 /* 3076 * Shared non-generic implementations 3077 */ 3078 3079 static int simple_playback_build_pcms(struct hda_codec *codec) 3080 { 3081 struct hdmi_spec *spec = codec->spec; 3082 struct hda_pcm *info; 3083 unsigned int chans; 3084 struct hda_pcm_stream *pstr; 3085 struct hdmi_spec_per_cvt *per_cvt; 3086 3087 per_cvt = get_cvt(spec, 0); 3088 chans = get_wcaps(codec, per_cvt->cvt_nid); 3089 chans = get_wcaps_channels(chans); 3090 3091 info = snd_hda_codec_pcm_new(codec, "HDMI 0"); 3092 if (!info) 3093 return -ENOMEM; 3094 spec->pcm_rec[0].pcm = info; 3095 info->pcm_type = HDA_PCM_TYPE_HDMI; 3096 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3097 *pstr = spec->pcm_playback; 3098 pstr->nid = per_cvt->cvt_nid; 3099 if (pstr->channels_max <= 2 && chans && chans <= 16) 3100 pstr->channels_max = chans; 3101 3102 return 0; 3103 } 3104 3105 /* unsolicited event for jack sensing */ 3106 static void simple_hdmi_unsol_event(struct hda_codec *codec, 3107 unsigned int res) 3108 { 3109 snd_hda_jack_set_dirty_all(codec); 3110 snd_hda_jack_report_sync(codec); 3111 } 3112 3113 /* generic_hdmi_build_jack can be used for simple_hdmi, too, 3114 * as long as spec->pins[] is set correctly 3115 */ 3116 #define simple_hdmi_build_jack generic_hdmi_build_jack 3117 3118 static int simple_playback_build_controls(struct hda_codec *codec) 3119 { 3120 struct hdmi_spec *spec = codec->spec; 3121 struct hdmi_spec_per_cvt *per_cvt; 3122 int err; 3123 3124 per_cvt = get_cvt(spec, 0); 3125 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, 3126 per_cvt->cvt_nid, 3127 HDA_PCM_TYPE_HDMI); 3128 if (err < 0) 3129 return err; 3130 return simple_hdmi_build_jack(codec, 0); 3131 } 3132 3133 static int simple_playback_init(struct hda_codec *codec) 3134 { 3135 struct hdmi_spec *spec = codec->spec; 3136 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); 3137 hda_nid_t pin = per_pin->pin_nid; 3138 3139 snd_hda_codec_write(codec, pin, 0, 3140 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); 3141 /* some codecs require to unmute the pin */ 3142 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 3143 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, 3144 AMP_OUT_UNMUTE); 3145 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id); 3146 return 0; 3147 } 3148 3149 static void simple_playback_free(struct hda_codec *codec) 3150 { 3151 struct hdmi_spec *spec = codec->spec; 3152 3153 hdmi_array_free(spec); 3154 kfree(spec); 3155 } 3156 3157 /* 3158 * Nvidia specific implementations 3159 */ 3160 3161 #define Nv_VERB_SET_Channel_Allocation 0xF79 3162 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A 3163 #define Nv_VERB_SET_Audio_Protection_On 0xF98 3164 #define Nv_VERB_SET_Audio_Protection_Off 0xF99 3165 3166 #define nvhdmi_master_con_nid_7x 0x04 3167 #define nvhdmi_master_pin_nid_7x 0x05 3168 3169 static const hda_nid_t nvhdmi_con_nids_7x[4] = { 3170 /*front, rear, clfe, rear_surr */ 3171 0x6, 0x8, 0xa, 0xc, 3172 }; 3173 3174 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { 3175 /* set audio protect on */ 3176 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3177 /* enable digital output on pin widget */ 3178 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3179 {} /* terminator */ 3180 }; 3181 3182 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { 3183 /* set audio protect on */ 3184 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3185 /* enable digital output on pin widget */ 3186 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3187 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3188 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3189 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3190 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3191 {} /* terminator */ 3192 }; 3193 3194 #ifdef LIMITED_RATE_FMT_SUPPORT 3195 /* support only the safe format and rate */ 3196 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 3197 #define SUPPORTED_MAXBPS 16 3198 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE 3199 #else 3200 /* support all rates and formats */ 3201 #define SUPPORTED_RATES \ 3202 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ 3203 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ 3204 SNDRV_PCM_RATE_192000) 3205 #define SUPPORTED_MAXBPS 24 3206 #define SUPPORTED_FORMATS \ 3207 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 3208 #endif 3209 3210 static int nvhdmi_7x_init_2ch(struct hda_codec *codec) 3211 { 3212 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); 3213 return 0; 3214 } 3215 3216 static int nvhdmi_7x_init_8ch(struct hda_codec *codec) 3217 { 3218 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); 3219 return 0; 3220 } 3221 3222 static const unsigned int channels_2_6_8[] = { 3223 2, 6, 8 3224 }; 3225 3226 static const unsigned int channels_2_8[] = { 3227 2, 8 3228 }; 3229 3230 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { 3231 .count = ARRAY_SIZE(channels_2_6_8), 3232 .list = channels_2_6_8, 3233 .mask = 0, 3234 }; 3235 3236 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { 3237 .count = ARRAY_SIZE(channels_2_8), 3238 .list = channels_2_8, 3239 .mask = 0, 3240 }; 3241 3242 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, 3243 struct hda_codec *codec, 3244 struct snd_pcm_substream *substream) 3245 { 3246 struct hdmi_spec *spec = codec->spec; 3247 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; 3248 3249 switch (codec->preset->vendor_id) { 3250 case 0x10de0002: 3251 case 0x10de0003: 3252 case 0x10de0005: 3253 case 0x10de0006: 3254 hw_constraints_channels = &hw_constraints_2_8_channels; 3255 break; 3256 case 0x10de0007: 3257 hw_constraints_channels = &hw_constraints_2_6_8_channels; 3258 break; 3259 default: 3260 break; 3261 } 3262 3263 if (hw_constraints_channels != NULL) { 3264 snd_pcm_hw_constraint_list(substream->runtime, 0, 3265 SNDRV_PCM_HW_PARAM_CHANNELS, 3266 hw_constraints_channels); 3267 } else { 3268 snd_pcm_hw_constraint_step(substream->runtime, 0, 3269 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 3270 } 3271 3272 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3273 } 3274 3275 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, 3276 struct hda_codec *codec, 3277 struct snd_pcm_substream *substream) 3278 { 3279 struct hdmi_spec *spec = codec->spec; 3280 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3281 } 3282 3283 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3284 struct hda_codec *codec, 3285 unsigned int stream_tag, 3286 unsigned int format, 3287 struct snd_pcm_substream *substream) 3288 { 3289 struct hdmi_spec *spec = codec->spec; 3290 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3291 stream_tag, format, substream); 3292 } 3293 3294 static const struct hda_pcm_stream simple_pcm_playback = { 3295 .substreams = 1, 3296 .channels_min = 2, 3297 .channels_max = 2, 3298 .ops = { 3299 .open = simple_playback_pcm_open, 3300 .close = simple_playback_pcm_close, 3301 .prepare = simple_playback_pcm_prepare 3302 }, 3303 }; 3304 3305 static const struct hda_codec_ops simple_hdmi_patch_ops = { 3306 .build_controls = simple_playback_build_controls, 3307 .build_pcms = simple_playback_build_pcms, 3308 .init = simple_playback_init, 3309 .free = simple_playback_free, 3310 .unsol_event = simple_hdmi_unsol_event, 3311 }; 3312 3313 static int patch_simple_hdmi(struct hda_codec *codec, 3314 hda_nid_t cvt_nid, hda_nid_t pin_nid) 3315 { 3316 struct hdmi_spec *spec; 3317 struct hdmi_spec_per_cvt *per_cvt; 3318 struct hdmi_spec_per_pin *per_pin; 3319 3320 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 3321 if (!spec) 3322 return -ENOMEM; 3323 3324 spec->codec = codec; 3325 codec->spec = spec; 3326 hdmi_array_init(spec, 1); 3327 3328 spec->multiout.num_dacs = 0; /* no analog */ 3329 spec->multiout.max_channels = 2; 3330 spec->multiout.dig_out_nid = cvt_nid; 3331 spec->num_cvts = 1; 3332 spec->num_pins = 1; 3333 per_pin = snd_array_new(&spec->pins); 3334 per_cvt = snd_array_new(&spec->cvts); 3335 if (!per_pin || !per_cvt) { 3336 simple_playback_free(codec); 3337 return -ENOMEM; 3338 } 3339 per_cvt->cvt_nid = cvt_nid; 3340 per_pin->pin_nid = pin_nid; 3341 spec->pcm_playback = simple_pcm_playback; 3342 3343 codec->patch_ops = simple_hdmi_patch_ops; 3344 3345 return 0; 3346 } 3347 3348 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, 3349 int channels) 3350 { 3351 unsigned int chanmask; 3352 int chan = channels ? (channels - 1) : 1; 3353 3354 switch (channels) { 3355 default: 3356 case 0: 3357 case 2: 3358 chanmask = 0x00; 3359 break; 3360 case 4: 3361 chanmask = 0x08; 3362 break; 3363 case 6: 3364 chanmask = 0x0b; 3365 break; 3366 case 8: 3367 chanmask = 0x13; 3368 break; 3369 } 3370 3371 /* Set the audio infoframe channel allocation and checksum fields. The 3372 * channel count is computed implicitly by the hardware. */ 3373 snd_hda_codec_write(codec, 0x1, 0, 3374 Nv_VERB_SET_Channel_Allocation, chanmask); 3375 3376 snd_hda_codec_write(codec, 0x1, 0, 3377 Nv_VERB_SET_Info_Frame_Checksum, 3378 (0x71 - chan - chanmask)); 3379 } 3380 3381 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, 3382 struct hda_codec *codec, 3383 struct snd_pcm_substream *substream) 3384 { 3385 struct hdmi_spec *spec = codec->spec; 3386 int i; 3387 3388 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 3389 0, AC_VERB_SET_CHANNEL_STREAMID, 0); 3390 for (i = 0; i < 4; i++) { 3391 /* set the stream id */ 3392 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3393 AC_VERB_SET_CHANNEL_STREAMID, 0); 3394 /* set the stream format */ 3395 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3396 AC_VERB_SET_STREAM_FORMAT, 0); 3397 } 3398 3399 /* The audio hardware sends a channel count of 0x7 (8ch) when all the 3400 * streams are disabled. */ 3401 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3402 3403 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3404 } 3405 3406 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, 3407 struct hda_codec *codec, 3408 unsigned int stream_tag, 3409 unsigned int format, 3410 struct snd_pcm_substream *substream) 3411 { 3412 int chs; 3413 unsigned int dataDCC2, channel_id; 3414 int i; 3415 struct hdmi_spec *spec = codec->spec; 3416 struct hda_spdif_out *spdif; 3417 struct hdmi_spec_per_cvt *per_cvt; 3418 3419 mutex_lock(&codec->spdif_mutex); 3420 per_cvt = get_cvt(spec, 0); 3421 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); 3422 3423 chs = substream->runtime->channels; 3424 3425 dataDCC2 = 0x2; 3426 3427 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ 3428 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) 3429 snd_hda_codec_write(codec, 3430 nvhdmi_master_con_nid_7x, 3431 0, 3432 AC_VERB_SET_DIGI_CONVERT_1, 3433 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3434 3435 /* set the stream id */ 3436 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3437 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); 3438 3439 /* set the stream format */ 3440 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3441 AC_VERB_SET_STREAM_FORMAT, format); 3442 3443 /* turn on again (if needed) */ 3444 /* enable and set the channel status audio/data flag */ 3445 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { 3446 snd_hda_codec_write(codec, 3447 nvhdmi_master_con_nid_7x, 3448 0, 3449 AC_VERB_SET_DIGI_CONVERT_1, 3450 spdif->ctls & 0xff); 3451 snd_hda_codec_write(codec, 3452 nvhdmi_master_con_nid_7x, 3453 0, 3454 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3455 } 3456 3457 for (i = 0; i < 4; i++) { 3458 if (chs == 2) 3459 channel_id = 0; 3460 else 3461 channel_id = i * 2; 3462 3463 /* turn off SPDIF once; 3464 *otherwise the IEC958 bits won't be updated 3465 */ 3466 if (codec->spdif_status_reset && 3467 (spdif->ctls & AC_DIG1_ENABLE)) 3468 snd_hda_codec_write(codec, 3469 nvhdmi_con_nids_7x[i], 3470 0, 3471 AC_VERB_SET_DIGI_CONVERT_1, 3472 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3473 /* set the stream id */ 3474 snd_hda_codec_write(codec, 3475 nvhdmi_con_nids_7x[i], 3476 0, 3477 AC_VERB_SET_CHANNEL_STREAMID, 3478 (stream_tag << 4) | channel_id); 3479 /* set the stream format */ 3480 snd_hda_codec_write(codec, 3481 nvhdmi_con_nids_7x[i], 3482 0, 3483 AC_VERB_SET_STREAM_FORMAT, 3484 format); 3485 /* turn on again (if needed) */ 3486 /* enable and set the channel status audio/data flag */ 3487 if (codec->spdif_status_reset && 3488 (spdif->ctls & AC_DIG1_ENABLE)) { 3489 snd_hda_codec_write(codec, 3490 nvhdmi_con_nids_7x[i], 3491 0, 3492 AC_VERB_SET_DIGI_CONVERT_1, 3493 spdif->ctls & 0xff); 3494 snd_hda_codec_write(codec, 3495 nvhdmi_con_nids_7x[i], 3496 0, 3497 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3498 } 3499 } 3500 3501 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); 3502 3503 mutex_unlock(&codec->spdif_mutex); 3504 return 0; 3505 } 3506 3507 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { 3508 .substreams = 1, 3509 .channels_min = 2, 3510 .channels_max = 8, 3511 .nid = nvhdmi_master_con_nid_7x, 3512 .rates = SUPPORTED_RATES, 3513 .maxbps = SUPPORTED_MAXBPS, 3514 .formats = SUPPORTED_FORMATS, 3515 .ops = { 3516 .open = simple_playback_pcm_open, 3517 .close = nvhdmi_8ch_7x_pcm_close, 3518 .prepare = nvhdmi_8ch_7x_pcm_prepare 3519 }, 3520 }; 3521 3522 static int patch_nvhdmi_2ch(struct hda_codec *codec) 3523 { 3524 struct hdmi_spec *spec; 3525 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, 3526 nvhdmi_master_pin_nid_7x); 3527 if (err < 0) 3528 return err; 3529 3530 codec->patch_ops.init = nvhdmi_7x_init_2ch; 3531 /* override the PCM rates, etc, as the codec doesn't give full list */ 3532 spec = codec->spec; 3533 spec->pcm_playback.rates = SUPPORTED_RATES; 3534 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; 3535 spec->pcm_playback.formats = SUPPORTED_FORMATS; 3536 spec->nv_dp_workaround = true; 3537 return 0; 3538 } 3539 3540 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) 3541 { 3542 struct hdmi_spec *spec = codec->spec; 3543 int err = simple_playback_build_pcms(codec); 3544 if (!err) { 3545 struct hda_pcm *info = get_pcm_rec(spec, 0); 3546 info->own_chmap = true; 3547 } 3548 return err; 3549 } 3550 3551 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) 3552 { 3553 struct hdmi_spec *spec = codec->spec; 3554 struct hda_pcm *info; 3555 struct snd_pcm_chmap *chmap; 3556 int err; 3557 3558 err = simple_playback_build_controls(codec); 3559 if (err < 0) 3560 return err; 3561 3562 /* add channel maps */ 3563 info = get_pcm_rec(spec, 0); 3564 err = snd_pcm_add_chmap_ctls(info->pcm, 3565 SNDRV_PCM_STREAM_PLAYBACK, 3566 snd_pcm_alt_chmaps, 8, 0, &chmap); 3567 if (err < 0) 3568 return err; 3569 switch (codec->preset->vendor_id) { 3570 case 0x10de0002: 3571 case 0x10de0003: 3572 case 0x10de0005: 3573 case 0x10de0006: 3574 chmap->channel_mask = (1U << 2) | (1U << 8); 3575 break; 3576 case 0x10de0007: 3577 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); 3578 } 3579 return 0; 3580 } 3581 3582 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) 3583 { 3584 struct hdmi_spec *spec; 3585 int err = patch_nvhdmi_2ch(codec); 3586 if (err < 0) 3587 return err; 3588 spec = codec->spec; 3589 spec->multiout.max_channels = 8; 3590 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; 3591 codec->patch_ops.init = nvhdmi_7x_init_8ch; 3592 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; 3593 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; 3594 3595 /* Initialize the audio infoframe channel mask and checksum to something 3596 * valid */ 3597 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3598 3599 return 0; 3600 } 3601 3602 /* 3603 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: 3604 * - 0x10de0015 3605 * - 0x10de0040 3606 */ 3607 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, 3608 struct hdac_cea_channel_speaker_allocation *cap, int channels) 3609 { 3610 if (cap->ca_index == 0x00 && channels == 2) 3611 return SNDRV_CTL_TLVT_CHMAP_FIXED; 3612 3613 /* If the speaker allocation matches the channel count, it is OK. */ 3614 if (cap->channels != channels) 3615 return -1; 3616 3617 /* all channels are remappable freely */ 3618 return SNDRV_CTL_TLVT_CHMAP_VAR; 3619 } 3620 3621 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, 3622 int ca, int chs, unsigned char *map) 3623 { 3624 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) 3625 return -EINVAL; 3626 3627 return 0; 3628 } 3629 3630 /* map from pin NID to port; port is 0-based */ 3631 /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */ 3632 static int nvhdmi_pin2port(void *audio_ptr, int pin_nid) 3633 { 3634 return pin_nid - 4; 3635 } 3636 3637 /* reverse-map from port to pin NID: see above */ 3638 static int nvhdmi_port2pin(struct hda_codec *codec, int port) 3639 { 3640 return port + 4; 3641 } 3642 3643 static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = { 3644 .pin2port = nvhdmi_pin2port, 3645 .pin_eld_notify = generic_acomp_pin_eld_notify, 3646 .master_bind = generic_acomp_master_bind, 3647 .master_unbind = generic_acomp_master_unbind, 3648 }; 3649 3650 static int patch_nvhdmi(struct hda_codec *codec) 3651 { 3652 struct hdmi_spec *spec; 3653 int err; 3654 3655 err = alloc_generic_hdmi(codec); 3656 if (err < 0) 3657 return err; 3658 codec->dp_mst = true; 3659 3660 spec = codec->spec; 3661 3662 err = hdmi_parse_codec(codec); 3663 if (err < 0) { 3664 generic_spec_free(codec); 3665 return err; 3666 } 3667 3668 generic_hdmi_init_per_pins(codec); 3669 3670 spec->dyn_pin_out = true; 3671 3672 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3673 nvhdmi_chmap_cea_alloc_validate_get_type; 3674 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3675 spec->nv_dp_workaround = true; 3676 3677 codec->link_down_at_suspend = 1; 3678 3679 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin); 3680 3681 return 0; 3682 } 3683 3684 static int patch_nvhdmi_legacy(struct hda_codec *codec) 3685 { 3686 struct hdmi_spec *spec; 3687 int err; 3688 3689 err = patch_generic_hdmi(codec); 3690 if (err) 3691 return err; 3692 3693 spec = codec->spec; 3694 spec->dyn_pin_out = true; 3695 3696 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3697 nvhdmi_chmap_cea_alloc_validate_get_type; 3698 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3699 spec->nv_dp_workaround = true; 3700 3701 codec->link_down_at_suspend = 1; 3702 3703 return 0; 3704 } 3705 3706 /* 3707 * The HDA codec on NVIDIA Tegra contains two scratch registers that are 3708 * accessed using vendor-defined verbs. These registers can be used for 3709 * interoperability between the HDA and HDMI drivers. 3710 */ 3711 3712 /* Audio Function Group node */ 3713 #define NVIDIA_AFG_NID 0x01 3714 3715 /* 3716 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio 3717 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to 3718 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This 3719 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an 3720 * additional bit (at position 30) to signal the validity of the format. 3721 * 3722 * | 31 | 30 | 29 16 | 15 0 | 3723 * +---------+-------+--------+--------+ 3724 * | TRIGGER | VALID | UNUSED | FORMAT | 3725 * +-----------------------------------| 3726 * 3727 * Note that for the trigger bit to take effect it needs to change value 3728 * (i.e. it needs to be toggled). The trigger bit is not applicable from 3729 * TEGRA234 chip onwards, as new verb id 0xf80 will be used for interrupt 3730 * trigger to hdmi. 3731 */ 3732 #define NVIDIA_SET_HOST_INTR 0xf80 3733 #define NVIDIA_GET_SCRATCH0 0xfa6 3734 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 3735 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 3736 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 3737 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa 3738 #define NVIDIA_SCRATCH_TRIGGER (1 << 7) 3739 #define NVIDIA_SCRATCH_VALID (1 << 6) 3740 3741 #define NVIDIA_GET_SCRATCH1 0xfab 3742 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac 3743 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad 3744 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae 3745 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf 3746 3747 /* 3748 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, 3749 * the format is invalidated so that the HDMI codec can be disabled. 3750 */ 3751 static void tegra_hdmi_set_format(struct hda_codec *codec, 3752 hda_nid_t cvt_nid, 3753 unsigned int format) 3754 { 3755 unsigned int value; 3756 unsigned int nid = NVIDIA_AFG_NID; 3757 struct hdmi_spec *spec = codec->spec; 3758 3759 /* 3760 * Tegra HDA codec design from TEGRA234 chip onwards support DP MST. 3761 * This resulted in moving scratch registers from audio function 3762 * group to converter widget context. So CVT NID should be used for 3763 * scratch register read/write for DP MST supported Tegra HDA codec. 3764 */ 3765 if (codec->dp_mst) 3766 nid = cvt_nid; 3767 3768 /* bits [31:30] contain the trigger and valid bits */ 3769 value = snd_hda_codec_read(codec, nid, 0, 3770 NVIDIA_GET_SCRATCH0, 0); 3771 value = (value >> 24) & 0xff; 3772 3773 /* bits [15:0] are used to store the HDA format */ 3774 snd_hda_codec_write(codec, nid, 0, 3775 NVIDIA_SET_SCRATCH0_BYTE0, 3776 (format >> 0) & 0xff); 3777 snd_hda_codec_write(codec, nid, 0, 3778 NVIDIA_SET_SCRATCH0_BYTE1, 3779 (format >> 8) & 0xff); 3780 3781 /* bits [16:24] are unused */ 3782 snd_hda_codec_write(codec, nid, 0, 3783 NVIDIA_SET_SCRATCH0_BYTE2, 0); 3784 3785 /* 3786 * Bit 30 signals that the data is valid and hence that HDMI audio can 3787 * be enabled. 3788 */ 3789 if (format == 0) 3790 value &= ~NVIDIA_SCRATCH_VALID; 3791 else 3792 value |= NVIDIA_SCRATCH_VALID; 3793 3794 if (spec->hdmi_intr_trig_ctrl) { 3795 /* 3796 * For Tegra HDA Codec design from TEGRA234 onwards, the 3797 * Interrupt to hdmi driver is triggered by writing 3798 * non-zero values to verb 0xF80 instead of 31st bit of 3799 * scratch register. 3800 */ 3801 snd_hda_codec_write(codec, nid, 0, 3802 NVIDIA_SET_SCRATCH0_BYTE3, value); 3803 snd_hda_codec_write(codec, nid, 0, 3804 NVIDIA_SET_HOST_INTR, 0x1); 3805 } else { 3806 /* 3807 * Whenever the 31st trigger bit is toggled, an interrupt is raised 3808 * in the HDMI codec. The HDMI driver will use that as trigger 3809 * to update its configuration. 3810 */ 3811 value ^= NVIDIA_SCRATCH_TRIGGER; 3812 3813 snd_hda_codec_write(codec, nid, 0, 3814 NVIDIA_SET_SCRATCH0_BYTE3, value); 3815 } 3816 } 3817 3818 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, 3819 struct hda_codec *codec, 3820 unsigned int stream_tag, 3821 unsigned int format, 3822 struct snd_pcm_substream *substream) 3823 { 3824 int err; 3825 3826 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, 3827 format, substream); 3828 if (err < 0) 3829 return err; 3830 3831 /* notify the HDMI codec of the format change */ 3832 tegra_hdmi_set_format(codec, hinfo->nid, format); 3833 3834 return 0; 3835 } 3836 3837 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, 3838 struct hda_codec *codec, 3839 struct snd_pcm_substream *substream) 3840 { 3841 /* invalidate the format in the HDMI codec */ 3842 tegra_hdmi_set_format(codec, hinfo->nid, 0); 3843 3844 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); 3845 } 3846 3847 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) 3848 { 3849 struct hdmi_spec *spec = codec->spec; 3850 unsigned int i; 3851 3852 for (i = 0; i < spec->num_pins; i++) { 3853 struct hda_pcm *pcm = get_pcm_rec(spec, i); 3854 3855 if (pcm->pcm_type == type) 3856 return pcm; 3857 } 3858 3859 return NULL; 3860 } 3861 3862 static int tegra_hdmi_build_pcms(struct hda_codec *codec) 3863 { 3864 struct hda_pcm_stream *stream; 3865 struct hda_pcm *pcm; 3866 int err; 3867 3868 err = generic_hdmi_build_pcms(codec); 3869 if (err < 0) 3870 return err; 3871 3872 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); 3873 if (!pcm) 3874 return -ENODEV; 3875 3876 /* 3877 * Override ->prepare() and ->cleanup() operations to notify the HDMI 3878 * codec about format changes. 3879 */ 3880 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3881 stream->ops.prepare = tegra_hdmi_pcm_prepare; 3882 stream->ops.cleanup = tegra_hdmi_pcm_cleanup; 3883 3884 return 0; 3885 } 3886 3887 static int tegra_hdmi_init(struct hda_codec *codec) 3888 { 3889 struct hdmi_spec *spec = codec->spec; 3890 int i, err; 3891 3892 err = hdmi_parse_codec(codec); 3893 if (err < 0) { 3894 generic_spec_free(codec); 3895 return err; 3896 } 3897 3898 for (i = 0; i < spec->num_cvts; i++) 3899 snd_hda_codec_write(codec, spec->cvt_nids[i], 0, 3900 AC_VERB_SET_DIGI_CONVERT_1, 3901 AC_DIG1_ENABLE); 3902 3903 generic_hdmi_init_per_pins(codec); 3904 3905 codec->depop_delay = 10; 3906 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; 3907 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3908 nvhdmi_chmap_cea_alloc_validate_get_type; 3909 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3910 3911 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3912 nvhdmi_chmap_cea_alloc_validate_get_type; 3913 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3914 spec->nv_dp_workaround = true; 3915 3916 return 0; 3917 } 3918 3919 static int patch_tegra_hdmi(struct hda_codec *codec) 3920 { 3921 int err; 3922 3923 err = alloc_generic_hdmi(codec); 3924 if (err < 0) 3925 return err; 3926 3927 return tegra_hdmi_init(codec); 3928 } 3929 3930 static int patch_tegra234_hdmi(struct hda_codec *codec) 3931 { 3932 struct hdmi_spec *spec; 3933 int err; 3934 3935 err = alloc_generic_hdmi(codec); 3936 if (err < 0) 3937 return err; 3938 3939 codec->dp_mst = true; 3940 spec = codec->spec; 3941 spec->dyn_pin_out = true; 3942 spec->hdmi_intr_trig_ctrl = true; 3943 3944 return tegra_hdmi_init(codec); 3945 } 3946 3947 /* 3948 * ATI/AMD-specific implementations 3949 */ 3950 3951 #define is_amdhdmi_rev3_or_later(codec) \ 3952 ((codec)->core.vendor_id == 0x1002aa01 && \ 3953 ((codec)->core.revision_id & 0xff00) >= 0x0300) 3954 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) 3955 3956 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ 3957 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 3958 #define ATI_VERB_SET_DOWNMIX_INFO 0x772 3959 #define ATI_VERB_SET_MULTICHANNEL_01 0x777 3960 #define ATI_VERB_SET_MULTICHANNEL_23 0x778 3961 #define ATI_VERB_SET_MULTICHANNEL_45 0x779 3962 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a 3963 #define ATI_VERB_SET_HBR_CONTROL 0x77c 3964 #define ATI_VERB_SET_MULTICHANNEL_1 0x785 3965 #define ATI_VERB_SET_MULTICHANNEL_3 0x786 3966 #define ATI_VERB_SET_MULTICHANNEL_5 0x787 3967 #define ATI_VERB_SET_MULTICHANNEL_7 0x788 3968 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 3969 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 3970 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 3971 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 3972 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 3973 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 3974 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a 3975 #define ATI_VERB_GET_HBR_CONTROL 0xf7c 3976 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 3977 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 3978 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 3979 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 3980 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 3981 3982 /* AMD specific HDA cvt verbs */ 3983 #define ATI_VERB_SET_RAMP_RATE 0x770 3984 #define ATI_VERB_GET_RAMP_RATE 0xf70 3985 3986 #define ATI_OUT_ENABLE 0x1 3987 3988 #define ATI_MULTICHANNEL_MODE_PAIRED 0 3989 #define ATI_MULTICHANNEL_MODE_SINGLE 1 3990 3991 #define ATI_HBR_CAPABLE 0x01 3992 #define ATI_HBR_ENABLE 0x10 3993 3994 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 3995 int dev_id, unsigned char *buf, int *eld_size) 3996 { 3997 WARN_ON(dev_id != 0); 3998 /* call hda_eld.c ATI/AMD-specific function */ 3999 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, 4000 is_amdhdmi_rev3_or_later(codec)); 4001 } 4002 4003 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, 4004 hda_nid_t pin_nid, int dev_id, int ca, 4005 int active_channels, int conn_type) 4006 { 4007 WARN_ON(dev_id != 0); 4008 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); 4009 } 4010 4011 static int atihdmi_paired_swap_fc_lfe(int pos) 4012 { 4013 /* 4014 * ATI/AMD have automatic FC/LFE swap built-in 4015 * when in pairwise mapping mode. 4016 */ 4017 4018 switch (pos) { 4019 /* see channel_allocations[].speakers[] */ 4020 case 2: return 3; 4021 case 3: return 2; 4022 default: break; 4023 } 4024 4025 return pos; 4026 } 4027 4028 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, 4029 int ca, int chs, unsigned char *map) 4030 { 4031 struct hdac_cea_channel_speaker_allocation *cap; 4032 int i, j; 4033 4034 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ 4035 4036 cap = snd_hdac_get_ch_alloc_from_ca(ca); 4037 for (i = 0; i < chs; ++i) { 4038 int mask = snd_hdac_chmap_to_spk_mask(map[i]); 4039 bool ok = false; 4040 bool companion_ok = false; 4041 4042 if (!mask) 4043 continue; 4044 4045 for (j = 0 + i % 2; j < 8; j += 2) { 4046 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); 4047 if (cap->speakers[chan_idx] == mask) { 4048 /* channel is in a supported position */ 4049 ok = true; 4050 4051 if (i % 2 == 0 && i + 1 < chs) { 4052 /* even channel, check the odd companion */ 4053 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); 4054 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); 4055 int comp_mask_act = cap->speakers[comp_chan_idx]; 4056 4057 if (comp_mask_req == comp_mask_act) 4058 companion_ok = true; 4059 else 4060 return -EINVAL; 4061 } 4062 break; 4063 } 4064 } 4065 4066 if (!ok) 4067 return -EINVAL; 4068 4069 if (companion_ok) 4070 i++; /* companion channel already checked */ 4071 } 4072 4073 return 0; 4074 } 4075 4076 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, 4077 hda_nid_t pin_nid, int hdmi_slot, int stream_channel) 4078 { 4079 struct hda_codec *codec = hdac_to_hda_codec(hdac); 4080 int verb; 4081 int ati_channel_setup = 0; 4082 4083 if (hdmi_slot > 7) 4084 return -EINVAL; 4085 4086 if (!has_amd_full_remap_support(codec)) { 4087 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); 4088 4089 /* In case this is an odd slot but without stream channel, do not 4090 * disable the slot since the corresponding even slot could have a 4091 * channel. In case neither have a channel, the slot pair will be 4092 * disabled when this function is called for the even slot. */ 4093 if (hdmi_slot % 2 != 0 && stream_channel == 0xf) 4094 return 0; 4095 4096 hdmi_slot -= hdmi_slot % 2; 4097 4098 if (stream_channel != 0xf) 4099 stream_channel -= stream_channel % 2; 4100 } 4101 4102 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; 4103 4104 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ 4105 4106 if (stream_channel != 0xf) 4107 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; 4108 4109 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); 4110 } 4111 4112 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, 4113 hda_nid_t pin_nid, int asp_slot) 4114 { 4115 struct hda_codec *codec = hdac_to_hda_codec(hdac); 4116 bool was_odd = false; 4117 int ati_asp_slot = asp_slot; 4118 int verb; 4119 int ati_channel_setup; 4120 4121 if (asp_slot > 7) 4122 return -EINVAL; 4123 4124 if (!has_amd_full_remap_support(codec)) { 4125 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); 4126 if (ati_asp_slot % 2 != 0) { 4127 ati_asp_slot -= 1; 4128 was_odd = true; 4129 } 4130 } 4131 4132 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; 4133 4134 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); 4135 4136 if (!(ati_channel_setup & ATI_OUT_ENABLE)) 4137 return 0xf; 4138 4139 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; 4140 } 4141 4142 static int atihdmi_paired_chmap_cea_alloc_validate_get_type( 4143 struct hdac_chmap *chmap, 4144 struct hdac_cea_channel_speaker_allocation *cap, 4145 int channels) 4146 { 4147 int c; 4148 4149 /* 4150 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so 4151 * we need to take that into account (a single channel may take 2 4152 * channel slots if we need to carry a silent channel next to it). 4153 * On Rev3+ AMD codecs this function is not used. 4154 */ 4155 int chanpairs = 0; 4156 4157 /* We only produce even-numbered channel count TLVs */ 4158 if ((channels % 2) != 0) 4159 return -1; 4160 4161 for (c = 0; c < 7; c += 2) { 4162 if (cap->speakers[c] || cap->speakers[c+1]) 4163 chanpairs++; 4164 } 4165 4166 if (chanpairs * 2 != channels) 4167 return -1; 4168 4169 return SNDRV_CTL_TLVT_CHMAP_PAIRED; 4170 } 4171 4172 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, 4173 struct hdac_cea_channel_speaker_allocation *cap, 4174 unsigned int *chmap, int channels) 4175 { 4176 /* produce paired maps for pre-rev3 ATI/AMD codecs */ 4177 int count = 0; 4178 int c; 4179 4180 for (c = 7; c >= 0; c--) { 4181 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); 4182 int spk = cap->speakers[chan]; 4183 if (!spk) { 4184 /* add N/A channel if the companion channel is occupied */ 4185 if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) 4186 chmap[count++] = SNDRV_CHMAP_NA; 4187 4188 continue; 4189 } 4190 4191 chmap[count++] = snd_hdac_spk_to_chmap(spk); 4192 } 4193 4194 WARN_ON(count != channels); 4195 } 4196 4197 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 4198 int dev_id, bool hbr) 4199 { 4200 int hbr_ctl, hbr_ctl_new; 4201 4202 WARN_ON(dev_id != 0); 4203 4204 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); 4205 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { 4206 if (hbr) 4207 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; 4208 else 4209 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; 4210 4211 codec_dbg(codec, 4212 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", 4213 pin_nid, 4214 hbr_ctl == hbr_ctl_new ? "" : "new-", 4215 hbr_ctl_new); 4216 4217 if (hbr_ctl != hbr_ctl_new) 4218 snd_hda_codec_write(codec, pin_nid, 0, 4219 ATI_VERB_SET_HBR_CONTROL, 4220 hbr_ctl_new); 4221 4222 } else if (hbr) 4223 return -EINVAL; 4224 4225 return 0; 4226 } 4227 4228 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 4229 hda_nid_t pin_nid, int dev_id, 4230 u32 stream_tag, int format) 4231 { 4232 if (is_amdhdmi_rev3_or_later(codec)) { 4233 int ramp_rate = 180; /* default as per AMD spec */ 4234 /* disable ramp-up/down for non-pcm as per AMD spec */ 4235 if (format & AC_FMT_TYPE_NON_PCM) 4236 ramp_rate = 0; 4237 4238 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); 4239 } 4240 4241 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 4242 stream_tag, format); 4243 } 4244 4245 4246 static int atihdmi_init(struct hda_codec *codec) 4247 { 4248 struct hdmi_spec *spec = codec->spec; 4249 int pin_idx, err; 4250 4251 err = generic_hdmi_init(codec); 4252 4253 if (err) 4254 return err; 4255 4256 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 4257 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 4258 4259 /* make sure downmix information in infoframe is zero */ 4260 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); 4261 4262 /* enable channel-wise remap mode if supported */ 4263 if (has_amd_full_remap_support(codec)) 4264 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 4265 ATI_VERB_SET_MULTICHANNEL_MODE, 4266 ATI_MULTICHANNEL_MODE_SINGLE); 4267 } 4268 codec->auto_runtime_pm = 1; 4269 4270 return 0; 4271 } 4272 4273 /* map from pin NID to port; port is 0-based */ 4274 /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */ 4275 static int atihdmi_pin2port(void *audio_ptr, int pin_nid) 4276 { 4277 return pin_nid / 2 - 1; 4278 } 4279 4280 /* reverse-map from port to pin NID: see above */ 4281 static int atihdmi_port2pin(struct hda_codec *codec, int port) 4282 { 4283 return port * 2 + 3; 4284 } 4285 4286 static const struct drm_audio_component_audio_ops atihdmi_audio_ops = { 4287 .pin2port = atihdmi_pin2port, 4288 .pin_eld_notify = generic_acomp_pin_eld_notify, 4289 .master_bind = generic_acomp_master_bind, 4290 .master_unbind = generic_acomp_master_unbind, 4291 }; 4292 4293 static int patch_atihdmi(struct hda_codec *codec) 4294 { 4295 struct hdmi_spec *spec; 4296 struct hdmi_spec_per_cvt *per_cvt; 4297 int err, cvt_idx; 4298 4299 err = patch_generic_hdmi(codec); 4300 4301 if (err) 4302 return err; 4303 4304 codec->patch_ops.init = atihdmi_init; 4305 4306 spec = codec->spec; 4307 4308 spec->ops.pin_get_eld = atihdmi_pin_get_eld; 4309 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; 4310 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; 4311 spec->ops.setup_stream = atihdmi_setup_stream; 4312 4313 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; 4314 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; 4315 4316 if (!has_amd_full_remap_support(codec)) { 4317 /* override to ATI/AMD-specific versions with pairwise mapping */ 4318 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4319 atihdmi_paired_chmap_cea_alloc_validate_get_type; 4320 spec->chmap.ops.cea_alloc_to_tlv_chmap = 4321 atihdmi_paired_cea_alloc_to_tlv_chmap; 4322 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; 4323 } 4324 4325 /* ATI/AMD converters do not advertise all of their capabilities */ 4326 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 4327 per_cvt = get_cvt(spec, cvt_idx); 4328 per_cvt->channels_max = max(per_cvt->channels_max, 8u); 4329 per_cvt->rates |= SUPPORTED_RATES; 4330 per_cvt->formats |= SUPPORTED_FORMATS; 4331 per_cvt->maxbps = max(per_cvt->maxbps, 24u); 4332 } 4333 4334 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); 4335 4336 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing 4337 * the link-down as is. Tell the core to allow it. 4338 */ 4339 codec->link_down_at_suspend = 1; 4340 4341 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin); 4342 4343 return 0; 4344 } 4345 4346 /* VIA HDMI Implementation */ 4347 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ 4348 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ 4349 4350 static int patch_via_hdmi(struct hda_codec *codec) 4351 { 4352 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); 4353 } 4354 4355 /* 4356 * patch entries 4357 */ 4358 static const struct hda_device_id snd_hda_id_hdmi[] = { 4359 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), 4360 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), 4361 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), 4362 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), 4363 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), 4364 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), 4365 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), 4366 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch), 4367 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4368 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4369 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x), 4370 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4371 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4372 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), 4373 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy), 4374 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy), 4375 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy), 4376 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy), 4377 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy), 4378 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy), 4379 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy), 4380 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy), 4381 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy), 4382 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy), 4383 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy), 4384 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy), 4385 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy), 4386 /* 17 is known to be absent */ 4387 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy), 4388 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy), 4389 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy), 4390 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy), 4391 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy), 4392 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), 4393 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), 4394 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), 4395 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), 4396 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi), 4397 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi), 4398 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), 4399 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), 4400 HDA_CODEC_ENTRY(0x10de0031, "Tegra234 HDMI/DP", patch_tegra234_hdmi), 4401 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), 4402 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), 4403 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), 4404 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), 4405 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), 4406 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi), 4407 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi), 4408 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), 4409 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi), 4410 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), 4411 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi), 4412 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi), 4413 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), 4414 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), 4415 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), 4416 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), 4417 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi), 4418 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi), 4419 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi), 4420 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi), 4421 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi), 4422 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), 4423 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi), 4424 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), 4425 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi), 4426 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), 4427 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), 4428 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi), 4429 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi), 4430 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi), 4431 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi), 4432 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi), 4433 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi), 4434 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi), 4435 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi), 4436 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), 4437 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), 4438 HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi), 4439 HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi), 4440 HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi), 4441 HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi), 4442 HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi), 4443 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), 4444 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), 4445 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), 4446 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), 4447 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), 4448 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), 4449 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4450 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), 4451 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), 4452 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), 4453 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), 4454 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4455 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), 4456 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), 4457 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), 4458 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), 4459 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), 4460 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), 4461 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), 4462 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), 4463 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), 4464 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi), 4465 HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi), 4466 HDA_CODEC_ENTRY(0x80862814, "DG1 HDMI", patch_i915_tgl_hdmi), 4467 HDA_CODEC_ENTRY(0x80862815, "Alderlake HDMI", patch_i915_tgl_hdmi), 4468 HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI", patch_i915_tgl_hdmi), 4469 HDA_CODEC_ENTRY(0x80862818, "Raptorlake HDMI", patch_i915_tgl_hdmi), 4470 HDA_CODEC_ENTRY(0x80862819, "DG2 HDMI", patch_i915_adlp_hdmi), 4471 HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi), 4472 HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi), 4473 HDA_CODEC_ENTRY(0x8086281c, "Alderlake-P HDMI", patch_i915_adlp_hdmi), 4474 HDA_CODEC_ENTRY(0x8086281f, "Raptorlake-P HDMI", patch_i915_adlp_hdmi), 4475 HDA_CODEC_ENTRY(0x8086281d, "Meteorlake HDMI", patch_i915_adlp_hdmi), 4476 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), 4477 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), 4478 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), 4479 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), 4480 /* special ID for generic HDMI */ 4481 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), 4482 {} /* terminator */ 4483 }; 4484 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); 4485 4486 MODULE_LICENSE("GPL"); 4487 MODULE_DESCRIPTION("HDMI HD-audio codec"); 4488 MODULE_ALIAS("snd-hda-codec-intelhdmi"); 4489 MODULE_ALIAS("snd-hda-codec-nvhdmi"); 4490 MODULE_ALIAS("snd-hda-codec-atihdmi"); 4491 4492 static struct hda_codec_driver hdmi_driver = { 4493 .id = snd_hda_id_hdmi, 4494 }; 4495 4496 module_hda_codec_driver(hdmi_driver); 4497