1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs 5 * 6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. 7 * Copyright (c) 2006 ATI Technologies Inc. 8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved. 9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com> 10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> 11 * 12 * Authors: 13 * Wu Fengguang <wfg@linux.intel.com> 14 * 15 * Maintained by: 16 * Wu Fengguang <wfg@linux.intel.com> 17 */ 18 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/pci.h> 22 #include <linux/slab.h> 23 #include <linux/module.h> 24 #include <linux/pm_runtime.h> 25 #include <sound/core.h> 26 #include <sound/jack.h> 27 #include <sound/asoundef.h> 28 #include <sound/tlv.h> 29 #include <sound/hdaudio.h> 30 #include <sound/hda_i915.h> 31 #include <sound/hda_chmap.h> 32 #include <sound/hda_codec.h> 33 #include "hda_local.h" 34 #include "hda_jack.h" 35 #include "hda_controller.h" 36 37 static bool static_hdmi_pcm; 38 module_param(static_hdmi_pcm, bool, 0644); 39 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); 40 41 static bool enable_acomp = true; 42 module_param(enable_acomp, bool, 0444); 43 MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)"); 44 45 static bool enable_silent_stream = 46 IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM); 47 module_param(enable_silent_stream, bool, 0644); 48 MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices"); 49 50 struct hdmi_spec_per_cvt { 51 hda_nid_t cvt_nid; 52 int assigned; 53 unsigned int channels_min; 54 unsigned int channels_max; 55 u32 rates; 56 u64 formats; 57 unsigned int maxbps; 58 }; 59 60 /* max. connections to a widget */ 61 #define HDA_MAX_CONNECTIONS 32 62 63 struct hdmi_spec_per_pin { 64 hda_nid_t pin_nid; 65 int dev_id; 66 /* pin idx, different device entries on the same pin use the same idx */ 67 int pin_nid_idx; 68 int num_mux_nids; 69 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; 70 int mux_idx; 71 hda_nid_t cvt_nid; 72 73 struct hda_codec *codec; 74 struct hdmi_eld sink_eld; 75 struct mutex lock; 76 struct delayed_work work; 77 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ 78 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ 79 int repoll_count; 80 bool setup; /* the stream has been set up by prepare callback */ 81 bool silent_stream; 82 int channels; /* current number of channels */ 83 bool non_pcm; 84 bool chmap_set; /* channel-map override by ALSA API? */ 85 unsigned char chmap[8]; /* ALSA API channel-map */ 86 #ifdef CONFIG_SND_PROC_FS 87 struct snd_info_entry *proc_entry; 88 #endif 89 }; 90 91 /* operations used by generic code that can be overridden by patches */ 92 struct hdmi_ops { 93 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, 94 int dev_id, unsigned char *buf, int *eld_size); 95 96 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, 97 int dev_id, 98 int ca, int active_channels, int conn_type); 99 100 /* enable/disable HBR (HD passthrough) */ 101 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, 102 int dev_id, bool hbr); 103 104 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, 105 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 106 int format); 107 108 void (*pin_cvt_fixup)(struct hda_codec *codec, 109 struct hdmi_spec_per_pin *per_pin, 110 hda_nid_t cvt_nid); 111 }; 112 113 struct hdmi_pcm { 114 struct hda_pcm *pcm; 115 struct snd_jack *jack; 116 struct snd_kcontrol *eld_ctl; 117 }; 118 119 struct hdmi_spec { 120 struct hda_codec *codec; 121 int num_cvts; 122 struct snd_array cvts; /* struct hdmi_spec_per_cvt */ 123 hda_nid_t cvt_nids[4]; /* only for haswell fix */ 124 125 /* 126 * num_pins is the number of virtual pins 127 * for example, there are 3 pins, and each pin 128 * has 4 device entries, then the num_pins is 12 129 */ 130 int num_pins; 131 /* 132 * num_nids is the number of real pins 133 * In the above example, num_nids is 3 134 */ 135 int num_nids; 136 /* 137 * dev_num is the number of device entries 138 * on each pin. 139 * In the above example, dev_num is 4 140 */ 141 int dev_num; 142 struct snd_array pins; /* struct hdmi_spec_per_pin */ 143 struct hdmi_pcm pcm_rec[16]; 144 struct mutex pcm_lock; 145 struct mutex bind_lock; /* for audio component binding */ 146 /* pcm_bitmap means which pcms have been assigned to pins*/ 147 unsigned long pcm_bitmap; 148 int pcm_used; /* counter of pcm_rec[] */ 149 /* bitmap shows whether the pcm is opened in user space 150 * bit 0 means the first playback PCM (PCM3); 151 * bit 1 means the second playback PCM, and so on. 152 */ 153 unsigned long pcm_in_use; 154 155 struct hdmi_eld temp_eld; 156 struct hdmi_ops ops; 157 158 bool dyn_pin_out; 159 bool dyn_pcm_assign; 160 bool dyn_pcm_no_legacy; 161 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */ 162 /* 163 * Non-generic VIA/NVIDIA specific 164 */ 165 struct hda_multi_out multiout; 166 struct hda_pcm_stream pcm_playback; 167 168 bool use_acomp_notifier; /* use eld_notify callback for hotplug */ 169 bool acomp_registered; /* audio component registered in this driver */ 170 bool force_connect; /* force connectivity */ 171 struct drm_audio_component_audio_ops drm_audio_ops; 172 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */ 173 174 struct hdac_chmap chmap; 175 hda_nid_t vendor_nid; 176 const int *port_map; 177 int port_num; 178 bool send_silent_stream; /* Flag to enable silent stream feature */ 179 }; 180 181 #ifdef CONFIG_SND_HDA_COMPONENT 182 static inline bool codec_has_acomp(struct hda_codec *codec) 183 { 184 struct hdmi_spec *spec = codec->spec; 185 return spec->use_acomp_notifier; 186 } 187 #else 188 #define codec_has_acomp(codec) false 189 #endif 190 191 struct hdmi_audio_infoframe { 192 u8 type; /* 0x84 */ 193 u8 ver; /* 0x01 */ 194 u8 len; /* 0x0a */ 195 196 u8 checksum; 197 198 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ 199 u8 SS01_SF24; 200 u8 CXT04; 201 u8 CA; 202 u8 LFEPBL01_LSV36_DM_INH7; 203 }; 204 205 struct dp_audio_infoframe { 206 u8 type; /* 0x84 */ 207 u8 len; /* 0x1b */ 208 u8 ver; /* 0x11 << 2 */ 209 210 u8 CC02_CT47; /* match with HDMI infoframe from this on */ 211 u8 SS01_SF24; 212 u8 CXT04; 213 u8 CA; 214 u8 LFEPBL01_LSV36_DM_INH7; 215 }; 216 217 union audio_infoframe { 218 struct hdmi_audio_infoframe hdmi; 219 struct dp_audio_infoframe dp; 220 u8 bytes[0]; 221 }; 222 223 /* 224 * HDMI routines 225 */ 226 227 #define get_pin(spec, idx) \ 228 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) 229 #define get_cvt(spec, idx) \ 230 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) 231 /* obtain hdmi_pcm object assigned to idx */ 232 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) 233 /* obtain hda_pcm object assigned to idx */ 234 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) 235 236 static int pin_id_to_pin_index(struct hda_codec *codec, 237 hda_nid_t pin_nid, int dev_id) 238 { 239 struct hdmi_spec *spec = codec->spec; 240 int pin_idx; 241 struct hdmi_spec_per_pin *per_pin; 242 243 /* 244 * (dev_id == -1) means it is NON-MST pin 245 * return the first virtual pin on this port 246 */ 247 if (dev_id == -1) 248 dev_id = 0; 249 250 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 251 per_pin = get_pin(spec, pin_idx); 252 if ((per_pin->pin_nid == pin_nid) && 253 (per_pin->dev_id == dev_id)) 254 return pin_idx; 255 } 256 257 codec_warn(codec, "HDMI: pin NID 0x%x not registered\n", pin_nid); 258 return -EINVAL; 259 } 260 261 static int hinfo_to_pcm_index(struct hda_codec *codec, 262 struct hda_pcm_stream *hinfo) 263 { 264 struct hdmi_spec *spec = codec->spec; 265 int pcm_idx; 266 267 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) 268 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) 269 return pcm_idx; 270 271 codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo); 272 return -EINVAL; 273 } 274 275 static int hinfo_to_pin_index(struct hda_codec *codec, 276 struct hda_pcm_stream *hinfo) 277 { 278 struct hdmi_spec *spec = codec->spec; 279 struct hdmi_spec_per_pin *per_pin; 280 int pin_idx; 281 282 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 283 per_pin = get_pin(spec, pin_idx); 284 if (per_pin->pcm && 285 per_pin->pcm->pcm->stream == hinfo) 286 return pin_idx; 287 } 288 289 codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo, 290 hinfo_to_pcm_index(codec, hinfo)); 291 return -EINVAL; 292 } 293 294 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, 295 int pcm_idx) 296 { 297 int i; 298 struct hdmi_spec_per_pin *per_pin; 299 300 for (i = 0; i < spec->num_pins; i++) { 301 per_pin = get_pin(spec, i); 302 if (per_pin->pcm_idx == pcm_idx) 303 return per_pin; 304 } 305 return NULL; 306 } 307 308 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) 309 { 310 struct hdmi_spec *spec = codec->spec; 311 int cvt_idx; 312 313 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) 314 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) 315 return cvt_idx; 316 317 codec_warn(codec, "HDMI: cvt NID 0x%x not registered\n", cvt_nid); 318 return -EINVAL; 319 } 320 321 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, 322 struct snd_ctl_elem_info *uinfo) 323 { 324 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 325 struct hdmi_spec *spec = codec->spec; 326 struct hdmi_spec_per_pin *per_pin; 327 struct hdmi_eld *eld; 328 int pcm_idx; 329 330 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 331 332 pcm_idx = kcontrol->private_value; 333 mutex_lock(&spec->pcm_lock); 334 per_pin = pcm_idx_to_pin(spec, pcm_idx); 335 if (!per_pin) { 336 /* no pin is bound to the pcm */ 337 uinfo->count = 0; 338 goto unlock; 339 } 340 eld = &per_pin->sink_eld; 341 uinfo->count = eld->eld_valid ? eld->eld_size : 0; 342 343 unlock: 344 mutex_unlock(&spec->pcm_lock); 345 return 0; 346 } 347 348 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, 349 struct snd_ctl_elem_value *ucontrol) 350 { 351 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 352 struct hdmi_spec *spec = codec->spec; 353 struct hdmi_spec_per_pin *per_pin; 354 struct hdmi_eld *eld; 355 int pcm_idx; 356 int err = 0; 357 358 pcm_idx = kcontrol->private_value; 359 mutex_lock(&spec->pcm_lock); 360 per_pin = pcm_idx_to_pin(spec, pcm_idx); 361 if (!per_pin) { 362 /* no pin is bound to the pcm */ 363 memset(ucontrol->value.bytes.data, 0, 364 ARRAY_SIZE(ucontrol->value.bytes.data)); 365 goto unlock; 366 } 367 368 eld = &per_pin->sink_eld; 369 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || 370 eld->eld_size > ELD_MAX_SIZE) { 371 snd_BUG(); 372 err = -EINVAL; 373 goto unlock; 374 } 375 376 memset(ucontrol->value.bytes.data, 0, 377 ARRAY_SIZE(ucontrol->value.bytes.data)); 378 if (eld->eld_valid) 379 memcpy(ucontrol->value.bytes.data, eld->eld_buffer, 380 eld->eld_size); 381 382 unlock: 383 mutex_unlock(&spec->pcm_lock); 384 return err; 385 } 386 387 static const struct snd_kcontrol_new eld_bytes_ctl = { 388 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE | 389 SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK, 390 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 391 .name = "ELD", 392 .info = hdmi_eld_ctl_info, 393 .get = hdmi_eld_ctl_get, 394 }; 395 396 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, 397 int device) 398 { 399 struct snd_kcontrol *kctl; 400 struct hdmi_spec *spec = codec->spec; 401 int err; 402 403 kctl = snd_ctl_new1(&eld_bytes_ctl, codec); 404 if (!kctl) 405 return -ENOMEM; 406 kctl->private_value = pcm_idx; 407 kctl->id.device = device; 408 409 /* no pin nid is associated with the kctl now 410 * tbd: associate pin nid to eld ctl later 411 */ 412 err = snd_hda_ctl_add(codec, 0, kctl); 413 if (err < 0) 414 return err; 415 416 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; 417 return 0; 418 } 419 420 #ifdef BE_PARANOID 421 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 422 int *packet_index, int *byte_index) 423 { 424 int val; 425 426 val = snd_hda_codec_read(codec, pin_nid, 0, 427 AC_VERB_GET_HDMI_DIP_INDEX, 0); 428 429 *packet_index = val >> 5; 430 *byte_index = val & 0x1f; 431 } 432 #endif 433 434 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 435 int packet_index, int byte_index) 436 { 437 int val; 438 439 val = (packet_index << 5) | (byte_index & 0x1f); 440 441 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); 442 } 443 444 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, 445 unsigned char val) 446 { 447 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); 448 } 449 450 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) 451 { 452 struct hdmi_spec *spec = codec->spec; 453 int pin_out; 454 455 /* Unmute */ 456 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 457 snd_hda_codec_write(codec, pin_nid, 0, 458 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); 459 460 if (spec->dyn_pin_out) 461 /* Disable pin out until stream is active */ 462 pin_out = 0; 463 else 464 /* Enable pin out: some machines with GM965 gets broken output 465 * when the pin is disabled or changed while using with HDMI 466 */ 467 pin_out = PIN_OUT; 468 469 snd_hda_codec_write(codec, pin_nid, 0, 470 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); 471 } 472 473 /* 474 * ELD proc files 475 */ 476 477 #ifdef CONFIG_SND_PROC_FS 478 static void print_eld_info(struct snd_info_entry *entry, 479 struct snd_info_buffer *buffer) 480 { 481 struct hdmi_spec_per_pin *per_pin = entry->private_data; 482 483 mutex_lock(&per_pin->lock); 484 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer); 485 mutex_unlock(&per_pin->lock); 486 } 487 488 static void write_eld_info(struct snd_info_entry *entry, 489 struct snd_info_buffer *buffer) 490 { 491 struct hdmi_spec_per_pin *per_pin = entry->private_data; 492 493 mutex_lock(&per_pin->lock); 494 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); 495 mutex_unlock(&per_pin->lock); 496 } 497 498 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) 499 { 500 char name[32]; 501 struct hda_codec *codec = per_pin->codec; 502 struct snd_info_entry *entry; 503 int err; 504 505 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); 506 err = snd_card_proc_new(codec->card, name, &entry); 507 if (err < 0) 508 return err; 509 510 snd_info_set_text_ops(entry, per_pin, print_eld_info); 511 entry->c.text.write = write_eld_info; 512 entry->mode |= 0200; 513 per_pin->proc_entry = entry; 514 515 return 0; 516 } 517 518 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 519 { 520 if (!per_pin->codec->bus->shutdown) { 521 snd_info_free_entry(per_pin->proc_entry); 522 per_pin->proc_entry = NULL; 523 } 524 } 525 #else 526 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, 527 int index) 528 { 529 return 0; 530 } 531 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 532 { 533 } 534 #endif 535 536 /* 537 * Audio InfoFrame routines 538 */ 539 540 /* 541 * Enable Audio InfoFrame Transmission 542 */ 543 static void hdmi_start_infoframe_trans(struct hda_codec *codec, 544 hda_nid_t pin_nid) 545 { 546 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 547 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 548 AC_DIPXMIT_BEST); 549 } 550 551 /* 552 * Disable Audio InfoFrame Transmission 553 */ 554 static void hdmi_stop_infoframe_trans(struct hda_codec *codec, 555 hda_nid_t pin_nid) 556 { 557 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 558 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 559 AC_DIPXMIT_DISABLE); 560 } 561 562 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) 563 { 564 #ifdef CONFIG_SND_DEBUG_VERBOSE 565 int i; 566 int size; 567 568 size = snd_hdmi_get_eld_size(codec, pin_nid); 569 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); 570 571 for (i = 0; i < 8; i++) { 572 size = snd_hda_codec_read(codec, pin_nid, 0, 573 AC_VERB_GET_HDMI_DIP_SIZE, i); 574 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); 575 } 576 #endif 577 } 578 579 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) 580 { 581 #ifdef BE_PARANOID 582 int i, j; 583 int size; 584 int pi, bi; 585 for (i = 0; i < 8; i++) { 586 size = snd_hda_codec_read(codec, pin_nid, 0, 587 AC_VERB_GET_HDMI_DIP_SIZE, i); 588 if (size == 0) 589 continue; 590 591 hdmi_set_dip_index(codec, pin_nid, i, 0x0); 592 for (j = 1; j < 1000; j++) { 593 hdmi_write_dip_byte(codec, pin_nid, 0x0); 594 hdmi_get_dip_index(codec, pin_nid, &pi, &bi); 595 if (pi != i) 596 codec_dbg(codec, "dip index %d: %d != %d\n", 597 bi, pi, i); 598 if (bi == 0) /* byte index wrapped around */ 599 break; 600 } 601 codec_dbg(codec, 602 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", 603 i, size, j); 604 } 605 #endif 606 } 607 608 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) 609 { 610 u8 *bytes = (u8 *)hdmi_ai; 611 u8 sum = 0; 612 int i; 613 614 hdmi_ai->checksum = 0; 615 616 for (i = 0; i < sizeof(*hdmi_ai); i++) 617 sum += bytes[i]; 618 619 hdmi_ai->checksum = -sum; 620 } 621 622 static void hdmi_fill_audio_infoframe(struct hda_codec *codec, 623 hda_nid_t pin_nid, 624 u8 *dip, int size) 625 { 626 int i; 627 628 hdmi_debug_dip_size(codec, pin_nid); 629 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ 630 631 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 632 for (i = 0; i < size; i++) 633 hdmi_write_dip_byte(codec, pin_nid, dip[i]); 634 } 635 636 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, 637 u8 *dip, int size) 638 { 639 u8 val; 640 int i; 641 642 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 643 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) 644 != AC_DIPXMIT_BEST) 645 return false; 646 647 for (i = 0; i < size; i++) { 648 val = snd_hda_codec_read(codec, pin_nid, 0, 649 AC_VERB_GET_HDMI_DIP_DATA, 0); 650 if (val != dip[i]) 651 return false; 652 } 653 654 return true; 655 } 656 657 static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 658 int dev_id, unsigned char *buf, int *eld_size) 659 { 660 snd_hda_set_dev_select(codec, nid, dev_id); 661 662 return snd_hdmi_get_eld(codec, nid, buf, eld_size); 663 } 664 665 static void hdmi_pin_setup_infoframe(struct hda_codec *codec, 666 hda_nid_t pin_nid, int dev_id, 667 int ca, int active_channels, 668 int conn_type) 669 { 670 union audio_infoframe ai; 671 672 memset(&ai, 0, sizeof(ai)); 673 if (conn_type == 0) { /* HDMI */ 674 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; 675 676 hdmi_ai->type = 0x84; 677 hdmi_ai->ver = 0x01; 678 hdmi_ai->len = 0x0a; 679 hdmi_ai->CC02_CT47 = active_channels - 1; 680 hdmi_ai->CA = ca; 681 hdmi_checksum_audio_infoframe(hdmi_ai); 682 } else if (conn_type == 1) { /* DisplayPort */ 683 struct dp_audio_infoframe *dp_ai = &ai.dp; 684 685 dp_ai->type = 0x84; 686 dp_ai->len = 0x1b; 687 dp_ai->ver = 0x11 << 2; 688 dp_ai->CC02_CT47 = active_channels - 1; 689 dp_ai->CA = ca; 690 } else { 691 codec_dbg(codec, "HDMI: unknown connection type at pin NID 0x%x\n", pin_nid); 692 return; 693 } 694 695 snd_hda_set_dev_select(codec, pin_nid, dev_id); 696 697 /* 698 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or 699 * sizeof(*dp_ai) to avoid partial match/update problems when 700 * the user switches between HDMI/DP monitors. 701 */ 702 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, 703 sizeof(ai))) { 704 codec_dbg(codec, "%s: pin NID=0x%x channels=%d ca=0x%02x\n", 705 __func__, pin_nid, active_channels, ca); 706 hdmi_stop_infoframe_trans(codec, pin_nid); 707 hdmi_fill_audio_infoframe(codec, pin_nid, 708 ai.bytes, sizeof(ai)); 709 hdmi_start_infoframe_trans(codec, pin_nid); 710 } 711 } 712 713 static void hdmi_setup_audio_infoframe(struct hda_codec *codec, 714 struct hdmi_spec_per_pin *per_pin, 715 bool non_pcm) 716 { 717 struct hdmi_spec *spec = codec->spec; 718 struct hdac_chmap *chmap = &spec->chmap; 719 hda_nid_t pin_nid = per_pin->pin_nid; 720 int dev_id = per_pin->dev_id; 721 int channels = per_pin->channels; 722 int active_channels; 723 struct hdmi_eld *eld; 724 int ca; 725 726 if (!channels) 727 return; 728 729 snd_hda_set_dev_select(codec, pin_nid, dev_id); 730 731 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ 732 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 733 snd_hda_codec_write(codec, pin_nid, 0, 734 AC_VERB_SET_AMP_GAIN_MUTE, 735 AMP_OUT_UNMUTE); 736 737 eld = &per_pin->sink_eld; 738 739 ca = snd_hdac_channel_allocation(&codec->core, 740 eld->info.spk_alloc, channels, 741 per_pin->chmap_set, non_pcm, per_pin->chmap); 742 743 active_channels = snd_hdac_get_active_channels(ca); 744 745 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, 746 active_channels); 747 748 /* 749 * always configure channel mapping, it may have been changed by the 750 * user in the meantime 751 */ 752 snd_hdac_setup_channel_mapping(&spec->chmap, 753 pin_nid, non_pcm, ca, channels, 754 per_pin->chmap, per_pin->chmap_set); 755 756 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id, 757 ca, active_channels, eld->info.conn_type); 758 759 per_pin->non_pcm = non_pcm; 760 } 761 762 /* 763 * Unsolicited events 764 */ 765 766 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); 767 768 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, 769 int dev_id) 770 { 771 struct hdmi_spec *spec = codec->spec; 772 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); 773 774 if (pin_idx < 0) 775 return; 776 mutex_lock(&spec->pcm_lock); 777 hdmi_present_sense(get_pin(spec, pin_idx), 1); 778 mutex_unlock(&spec->pcm_lock); 779 } 780 781 static void jack_callback(struct hda_codec *codec, 782 struct hda_jack_callback *jack) 783 { 784 /* stop polling when notification is enabled */ 785 if (codec_has_acomp(codec)) 786 return; 787 788 check_presence_and_report(codec, jack->nid, jack->dev_id); 789 } 790 791 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res, 792 struct hda_jack_tbl *jack) 793 { 794 jack->jack_dirty = 1; 795 796 codec_dbg(codec, 797 "HDMI hot plug event: Codec=%d NID=0x%x Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", 798 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA), 799 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); 800 801 check_presence_and_report(codec, jack->nid, jack->dev_id); 802 } 803 804 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) 805 { 806 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 807 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 808 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); 809 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); 810 811 codec_info(codec, 812 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", 813 codec->addr, 814 tag, 815 subtag, 816 cp_state, 817 cp_ready); 818 819 /* TODO */ 820 if (cp_state) { 821 ; 822 } 823 if (cp_ready) { 824 ; 825 } 826 } 827 828 829 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) 830 { 831 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 832 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 833 struct hda_jack_tbl *jack; 834 835 if (codec_has_acomp(codec)) 836 return; 837 838 if (codec->dp_mst) { 839 int dev_entry = 840 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 841 842 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry); 843 } else { 844 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0); 845 } 846 847 if (!jack) { 848 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); 849 return; 850 } 851 852 if (subtag == 0) 853 hdmi_intrinsic_event(codec, res, jack); 854 else 855 hdmi_non_intrinsic_event(codec, res); 856 } 857 858 static void haswell_verify_D0(struct hda_codec *codec, 859 hda_nid_t cvt_nid, hda_nid_t nid) 860 { 861 int pwr; 862 863 /* For Haswell, the converter 1/2 may keep in D3 state after bootup, 864 * thus pins could only choose converter 0 for use. Make sure the 865 * converters are in correct power state */ 866 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) 867 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); 868 869 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { 870 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, 871 AC_PWRST_D0); 872 msleep(40); 873 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); 874 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; 875 codec_dbg(codec, "Haswell HDMI audio: Power for NID 0x%x is now D%d\n", nid, pwr); 876 } 877 } 878 879 /* 880 * Callbacks 881 */ 882 883 /* HBR should be Non-PCM, 8 channels */ 884 #define is_hbr_format(format) \ 885 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) 886 887 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 888 int dev_id, bool hbr) 889 { 890 int pinctl, new_pinctl; 891 892 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { 893 snd_hda_set_dev_select(codec, pin_nid, dev_id); 894 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 895 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 896 897 if (pinctl < 0) 898 return hbr ? -EINVAL : 0; 899 900 new_pinctl = pinctl & ~AC_PINCTL_EPT; 901 if (hbr) 902 new_pinctl |= AC_PINCTL_EPT_HBR; 903 else 904 new_pinctl |= AC_PINCTL_EPT_NATIVE; 905 906 codec_dbg(codec, 907 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", 908 pin_nid, 909 pinctl == new_pinctl ? "" : "new-", 910 new_pinctl); 911 912 if (pinctl != new_pinctl) 913 snd_hda_codec_write(codec, pin_nid, 0, 914 AC_VERB_SET_PIN_WIDGET_CONTROL, 915 new_pinctl); 916 } else if (hbr) 917 return -EINVAL; 918 919 return 0; 920 } 921 922 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 923 hda_nid_t pin_nid, int dev_id, 924 u32 stream_tag, int format) 925 { 926 struct hdmi_spec *spec = codec->spec; 927 unsigned int param; 928 int err; 929 930 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id, 931 is_hbr_format(format)); 932 933 if (err) { 934 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); 935 return err; 936 } 937 938 if (spec->intel_hsw_fixup) { 939 940 /* 941 * on recent platforms IEC Coding Type is required for HBR 942 * support, read current Digital Converter settings and set 943 * ICT bitfield if needed. 944 */ 945 param = snd_hda_codec_read(codec, cvt_nid, 0, 946 AC_VERB_GET_DIGI_CONVERT_1, 0); 947 948 param = (param >> 16) & ~(AC_DIG3_ICT); 949 950 /* on recent platforms ICT mode is required for HBR support */ 951 if (is_hbr_format(format)) 952 param |= 0x1; 953 954 snd_hda_codec_write(codec, cvt_nid, 0, 955 AC_VERB_SET_DIGI_CONVERT_3, param); 956 } 957 958 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); 959 return 0; 960 } 961 962 /* Try to find an available converter 963 * If pin_idx is less then zero, just try to find an available converter. 964 * Otherwise, try to find an available converter and get the cvt mux index 965 * of the pin. 966 */ 967 static int hdmi_choose_cvt(struct hda_codec *codec, 968 int pin_idx, int *cvt_id) 969 { 970 struct hdmi_spec *spec = codec->spec; 971 struct hdmi_spec_per_pin *per_pin; 972 struct hdmi_spec_per_cvt *per_cvt = NULL; 973 int cvt_idx, mux_idx = 0; 974 975 /* pin_idx < 0 means no pin will be bound to the converter */ 976 if (pin_idx < 0) 977 per_pin = NULL; 978 else 979 per_pin = get_pin(spec, pin_idx); 980 981 if (per_pin && per_pin->silent_stream) { 982 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid); 983 if (cvt_id) 984 *cvt_id = cvt_idx; 985 return 0; 986 } 987 988 /* Dynamically assign converter to stream */ 989 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 990 per_cvt = get_cvt(spec, cvt_idx); 991 992 /* Must not already be assigned */ 993 if (per_cvt->assigned) 994 continue; 995 if (per_pin == NULL) 996 break; 997 /* Must be in pin's mux's list of converters */ 998 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 999 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) 1000 break; 1001 /* Not in mux list */ 1002 if (mux_idx == per_pin->num_mux_nids) 1003 continue; 1004 break; 1005 } 1006 1007 /* No free converters */ 1008 if (cvt_idx == spec->num_cvts) 1009 return -EBUSY; 1010 1011 if (per_pin != NULL) 1012 per_pin->mux_idx = mux_idx; 1013 1014 if (cvt_id) 1015 *cvt_id = cvt_idx; 1016 1017 return 0; 1018 } 1019 1020 /* Assure the pin select the right convetor */ 1021 static void intel_verify_pin_cvt_connect(struct hda_codec *codec, 1022 struct hdmi_spec_per_pin *per_pin) 1023 { 1024 hda_nid_t pin_nid = per_pin->pin_nid; 1025 int mux_idx, curr; 1026 1027 mux_idx = per_pin->mux_idx; 1028 curr = snd_hda_codec_read(codec, pin_nid, 0, 1029 AC_VERB_GET_CONNECT_SEL, 0); 1030 if (curr != mux_idx) 1031 snd_hda_codec_write_cache(codec, pin_nid, 0, 1032 AC_VERB_SET_CONNECT_SEL, 1033 mux_idx); 1034 } 1035 1036 /* get the mux index for the converter of the pins 1037 * converter's mux index is the same for all pins on Intel platform 1038 */ 1039 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, 1040 hda_nid_t cvt_nid) 1041 { 1042 int i; 1043 1044 for (i = 0; i < spec->num_cvts; i++) 1045 if (spec->cvt_nids[i] == cvt_nid) 1046 return i; 1047 return -EINVAL; 1048 } 1049 1050 /* Intel HDMI workaround to fix audio routing issue: 1051 * For some Intel display codecs, pins share the same connection list. 1052 * So a conveter can be selected by multiple pins and playback on any of these 1053 * pins will generate sound on the external display, because audio flows from 1054 * the same converter to the display pipeline. Also muting one pin may make 1055 * other pins have no sound output. 1056 * So this function assures that an assigned converter for a pin is not selected 1057 * by any other pins. 1058 */ 1059 static void intel_not_share_assigned_cvt(struct hda_codec *codec, 1060 hda_nid_t pin_nid, 1061 int dev_id, int mux_idx) 1062 { 1063 struct hdmi_spec *spec = codec->spec; 1064 hda_nid_t nid; 1065 int cvt_idx, curr; 1066 struct hdmi_spec_per_cvt *per_cvt; 1067 struct hdmi_spec_per_pin *per_pin; 1068 int pin_idx; 1069 1070 /* configure the pins connections */ 1071 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 1072 int dev_id_saved; 1073 int dev_num; 1074 1075 per_pin = get_pin(spec, pin_idx); 1076 /* 1077 * pin not connected to monitor 1078 * no need to operate on it 1079 */ 1080 if (!per_pin->pcm) 1081 continue; 1082 1083 if ((per_pin->pin_nid == pin_nid) && 1084 (per_pin->dev_id == dev_id)) 1085 continue; 1086 1087 /* 1088 * if per_pin->dev_id >= dev_num, 1089 * snd_hda_get_dev_select() will fail, 1090 * and the following operation is unpredictable. 1091 * So skip this situation. 1092 */ 1093 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; 1094 if (per_pin->dev_id >= dev_num) 1095 continue; 1096 1097 nid = per_pin->pin_nid; 1098 1099 /* 1100 * Calling this function should not impact 1101 * on the device entry selection 1102 * So let's save the dev id for each pin, 1103 * and restore it when return 1104 */ 1105 dev_id_saved = snd_hda_get_dev_select(codec, nid); 1106 snd_hda_set_dev_select(codec, nid, per_pin->dev_id); 1107 curr = snd_hda_codec_read(codec, nid, 0, 1108 AC_VERB_GET_CONNECT_SEL, 0); 1109 if (curr != mux_idx) { 1110 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1111 continue; 1112 } 1113 1114 1115 /* choose an unassigned converter. The conveters in the 1116 * connection list are in the same order as in the codec. 1117 */ 1118 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1119 per_cvt = get_cvt(spec, cvt_idx); 1120 if (!per_cvt->assigned) { 1121 codec_dbg(codec, 1122 "choose cvt %d for pin NID 0x%x\n", 1123 cvt_idx, nid); 1124 snd_hda_codec_write_cache(codec, nid, 0, 1125 AC_VERB_SET_CONNECT_SEL, 1126 cvt_idx); 1127 break; 1128 } 1129 } 1130 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1131 } 1132 } 1133 1134 /* A wrapper of intel_not_share_asigned_cvt() */ 1135 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, 1136 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) 1137 { 1138 int mux_idx; 1139 struct hdmi_spec *spec = codec->spec; 1140 1141 /* On Intel platform, the mapping of converter nid to 1142 * mux index of the pins are always the same. 1143 * The pin nid may be 0, this means all pins will not 1144 * share the converter. 1145 */ 1146 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); 1147 if (mux_idx >= 0) 1148 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); 1149 } 1150 1151 /* skeleton caller of pin_cvt_fixup ops */ 1152 static void pin_cvt_fixup(struct hda_codec *codec, 1153 struct hdmi_spec_per_pin *per_pin, 1154 hda_nid_t cvt_nid) 1155 { 1156 struct hdmi_spec *spec = codec->spec; 1157 1158 if (spec->ops.pin_cvt_fixup) 1159 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); 1160 } 1161 1162 /* called in hdmi_pcm_open when no pin is assigned to the PCM 1163 * in dyn_pcm_assign mode. 1164 */ 1165 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, 1166 struct hda_codec *codec, 1167 struct snd_pcm_substream *substream) 1168 { 1169 struct hdmi_spec *spec = codec->spec; 1170 struct snd_pcm_runtime *runtime = substream->runtime; 1171 int cvt_idx, pcm_idx; 1172 struct hdmi_spec_per_cvt *per_cvt = NULL; 1173 int err; 1174 1175 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1176 if (pcm_idx < 0) 1177 return -EINVAL; 1178 1179 err = hdmi_choose_cvt(codec, -1, &cvt_idx); 1180 if (err) 1181 return err; 1182 1183 per_cvt = get_cvt(spec, cvt_idx); 1184 per_cvt->assigned = 1; 1185 hinfo->nid = per_cvt->cvt_nid; 1186 1187 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); 1188 1189 set_bit(pcm_idx, &spec->pcm_in_use); 1190 /* todo: setup spdif ctls assign */ 1191 1192 /* Initially set the converter's capabilities */ 1193 hinfo->channels_min = per_cvt->channels_min; 1194 hinfo->channels_max = per_cvt->channels_max; 1195 hinfo->rates = per_cvt->rates; 1196 hinfo->formats = per_cvt->formats; 1197 hinfo->maxbps = per_cvt->maxbps; 1198 1199 /* Store the updated parameters */ 1200 runtime->hw.channels_min = hinfo->channels_min; 1201 runtime->hw.channels_max = hinfo->channels_max; 1202 runtime->hw.formats = hinfo->formats; 1203 runtime->hw.rates = hinfo->rates; 1204 1205 snd_pcm_hw_constraint_step(substream->runtime, 0, 1206 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1207 return 0; 1208 } 1209 1210 /* 1211 * HDA PCM callbacks 1212 */ 1213 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, 1214 struct hda_codec *codec, 1215 struct snd_pcm_substream *substream) 1216 { 1217 struct hdmi_spec *spec = codec->spec; 1218 struct snd_pcm_runtime *runtime = substream->runtime; 1219 int pin_idx, cvt_idx, pcm_idx; 1220 struct hdmi_spec_per_pin *per_pin; 1221 struct hdmi_eld *eld; 1222 struct hdmi_spec_per_cvt *per_cvt = NULL; 1223 int err; 1224 1225 /* Validate hinfo */ 1226 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1227 if (pcm_idx < 0) 1228 return -EINVAL; 1229 1230 mutex_lock(&spec->pcm_lock); 1231 pin_idx = hinfo_to_pin_index(codec, hinfo); 1232 if (!spec->dyn_pcm_assign) { 1233 if (snd_BUG_ON(pin_idx < 0)) { 1234 err = -EINVAL; 1235 goto unlock; 1236 } 1237 } else { 1238 /* no pin is assigned to the PCM 1239 * PA need pcm open successfully when probe 1240 */ 1241 if (pin_idx < 0) { 1242 err = hdmi_pcm_open_no_pin(hinfo, codec, substream); 1243 goto unlock; 1244 } 1245 } 1246 1247 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx); 1248 if (err < 0) 1249 goto unlock; 1250 1251 per_cvt = get_cvt(spec, cvt_idx); 1252 /* Claim converter */ 1253 per_cvt->assigned = 1; 1254 1255 set_bit(pcm_idx, &spec->pcm_in_use); 1256 per_pin = get_pin(spec, pin_idx); 1257 per_pin->cvt_nid = per_cvt->cvt_nid; 1258 hinfo->nid = per_cvt->cvt_nid; 1259 1260 /* flip stripe flag for the assigned stream if supported */ 1261 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE) 1262 azx_stream(get_azx_dev(substream))->stripe = 1; 1263 1264 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1265 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1266 AC_VERB_SET_CONNECT_SEL, 1267 per_pin->mux_idx); 1268 1269 /* configure unused pins to choose other converters */ 1270 pin_cvt_fixup(codec, per_pin, 0); 1271 1272 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); 1273 1274 /* Initially set the converter's capabilities */ 1275 hinfo->channels_min = per_cvt->channels_min; 1276 hinfo->channels_max = per_cvt->channels_max; 1277 hinfo->rates = per_cvt->rates; 1278 hinfo->formats = per_cvt->formats; 1279 hinfo->maxbps = per_cvt->maxbps; 1280 1281 eld = &per_pin->sink_eld; 1282 /* Restrict capabilities by ELD if this isn't disabled */ 1283 if (!static_hdmi_pcm && eld->eld_valid) { 1284 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); 1285 if (hinfo->channels_min > hinfo->channels_max || 1286 !hinfo->rates || !hinfo->formats) { 1287 per_cvt->assigned = 0; 1288 hinfo->nid = 0; 1289 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1290 err = -ENODEV; 1291 goto unlock; 1292 } 1293 } 1294 1295 /* Store the updated parameters */ 1296 runtime->hw.channels_min = hinfo->channels_min; 1297 runtime->hw.channels_max = hinfo->channels_max; 1298 runtime->hw.formats = hinfo->formats; 1299 runtime->hw.rates = hinfo->rates; 1300 1301 snd_pcm_hw_constraint_step(substream->runtime, 0, 1302 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1303 unlock: 1304 mutex_unlock(&spec->pcm_lock); 1305 return err; 1306 } 1307 1308 /* 1309 * HDA/HDMI auto parsing 1310 */ 1311 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) 1312 { 1313 struct hdmi_spec *spec = codec->spec; 1314 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1315 hda_nid_t pin_nid = per_pin->pin_nid; 1316 int dev_id = per_pin->dev_id; 1317 int conns; 1318 1319 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { 1320 codec_warn(codec, 1321 "HDMI: pin NID 0x%x wcaps %#x does not support connection list\n", 1322 pin_nid, get_wcaps(codec, pin_nid)); 1323 return -EINVAL; 1324 } 1325 1326 snd_hda_set_dev_select(codec, pin_nid, dev_id); 1327 1328 if (spec->intel_hsw_fixup) { 1329 conns = spec->num_cvts; 1330 memcpy(per_pin->mux_nids, spec->cvt_nids, 1331 sizeof(hda_nid_t) * conns); 1332 } else { 1333 conns = snd_hda_get_raw_connections(codec, pin_nid, 1334 per_pin->mux_nids, 1335 HDA_MAX_CONNECTIONS); 1336 } 1337 1338 /* all the device entries on the same pin have the same conn list */ 1339 per_pin->num_mux_nids = conns; 1340 1341 return 0; 1342 } 1343 1344 static int hdmi_find_pcm_slot(struct hdmi_spec *spec, 1345 struct hdmi_spec_per_pin *per_pin) 1346 { 1347 int i; 1348 1349 /* on the new machines, try to assign the pcm slot dynamically, 1350 * not use the preferred fixed map (legacy way) anymore. 1351 */ 1352 if (spec->dyn_pcm_no_legacy) 1353 goto last_try; 1354 1355 /* 1356 * generic_hdmi_build_pcms() may allocate extra PCMs on some 1357 * platforms (with maximum of 'num_nids + dev_num - 1') 1358 * 1359 * The per_pin of pin_nid_idx=n and dev_id=m prefers to get pcm-n 1360 * if m==0. This guarantees that dynamic pcm assignments are compatible 1361 * with the legacy static per_pin-pcm assignment that existed in the 1362 * days before DP-MST. 1363 * 1364 * Intel DP-MST prefers this legacy behavior for compatibility, too. 1365 * 1366 * per_pin of m!=0 prefers to get pcm=(num_nids + (m - 1)). 1367 */ 1368 1369 if (per_pin->dev_id == 0 || spec->intel_hsw_fixup) { 1370 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap)) 1371 return per_pin->pin_nid_idx; 1372 } else { 1373 i = spec->num_nids + (per_pin->dev_id - 1); 1374 if (i < spec->pcm_used && !(test_bit(i, &spec->pcm_bitmap))) 1375 return i; 1376 } 1377 1378 /* have a second try; check the area over num_nids */ 1379 for (i = spec->num_nids; i < spec->pcm_used; i++) { 1380 if (!test_bit(i, &spec->pcm_bitmap)) 1381 return i; 1382 } 1383 1384 last_try: 1385 /* the last try; check the empty slots in pins */ 1386 for (i = 0; i < spec->num_nids; i++) { 1387 if (!test_bit(i, &spec->pcm_bitmap)) 1388 return i; 1389 } 1390 return -EBUSY; 1391 } 1392 1393 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, 1394 struct hdmi_spec_per_pin *per_pin) 1395 { 1396 int idx; 1397 1398 /* pcm already be attached to the pin */ 1399 if (per_pin->pcm) 1400 return; 1401 idx = hdmi_find_pcm_slot(spec, per_pin); 1402 if (idx == -EBUSY) 1403 return; 1404 per_pin->pcm_idx = idx; 1405 per_pin->pcm = get_hdmi_pcm(spec, idx); 1406 set_bit(idx, &spec->pcm_bitmap); 1407 } 1408 1409 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, 1410 struct hdmi_spec_per_pin *per_pin) 1411 { 1412 int idx; 1413 1414 /* pcm already be detached from the pin */ 1415 if (!per_pin->pcm) 1416 return; 1417 idx = per_pin->pcm_idx; 1418 per_pin->pcm_idx = -1; 1419 per_pin->pcm = NULL; 1420 if (idx >= 0 && idx < spec->pcm_used) 1421 clear_bit(idx, &spec->pcm_bitmap); 1422 } 1423 1424 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, 1425 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) 1426 { 1427 int mux_idx; 1428 1429 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1430 if (per_pin->mux_nids[mux_idx] == cvt_nid) 1431 break; 1432 return mux_idx; 1433 } 1434 1435 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); 1436 1437 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, 1438 struct hdmi_spec_per_pin *per_pin) 1439 { 1440 struct hda_codec *codec = per_pin->codec; 1441 struct hda_pcm *pcm; 1442 struct hda_pcm_stream *hinfo; 1443 struct snd_pcm_substream *substream; 1444 int mux_idx; 1445 bool non_pcm; 1446 1447 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1448 pcm = get_pcm_rec(spec, per_pin->pcm_idx); 1449 else 1450 return; 1451 if (!pcm->pcm) 1452 return; 1453 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) 1454 return; 1455 1456 /* hdmi audio only uses playback and one substream */ 1457 hinfo = pcm->stream; 1458 substream = pcm->pcm->streams[0].substream; 1459 1460 per_pin->cvt_nid = hinfo->nid; 1461 1462 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); 1463 if (mux_idx < per_pin->num_mux_nids) { 1464 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1465 per_pin->dev_id); 1466 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1467 AC_VERB_SET_CONNECT_SEL, 1468 mux_idx); 1469 } 1470 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); 1471 1472 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); 1473 if (substream->runtime) 1474 per_pin->channels = substream->runtime->channels; 1475 per_pin->setup = true; 1476 per_pin->mux_idx = mux_idx; 1477 1478 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1479 } 1480 1481 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, 1482 struct hdmi_spec_per_pin *per_pin) 1483 { 1484 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1485 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); 1486 1487 per_pin->chmap_set = false; 1488 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1489 1490 per_pin->setup = false; 1491 per_pin->channels = 0; 1492 } 1493 1494 static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec, 1495 struct hdmi_spec_per_pin *per_pin) 1496 { 1497 struct hdmi_spec *spec = codec->spec; 1498 1499 if (per_pin->pcm_idx >= 0) 1500 return spec->pcm_rec[per_pin->pcm_idx].jack; 1501 else 1502 return NULL; 1503 } 1504 1505 /* update per_pin ELD from the given new ELD; 1506 * setup info frame and notification accordingly 1507 * also notify ELD kctl and report jack status changes 1508 */ 1509 static void update_eld(struct hda_codec *codec, 1510 struct hdmi_spec_per_pin *per_pin, 1511 struct hdmi_eld *eld, 1512 int repoll) 1513 { 1514 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 1515 struct hdmi_spec *spec = codec->spec; 1516 struct snd_jack *pcm_jack; 1517 bool old_eld_valid = pin_eld->eld_valid; 1518 bool eld_changed; 1519 int pcm_idx; 1520 1521 if (eld->eld_valid) { 1522 if (eld->eld_size <= 0 || 1523 snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, 1524 eld->eld_size) < 0) { 1525 eld->eld_valid = false; 1526 if (repoll) { 1527 schedule_delayed_work(&per_pin->work, 1528 msecs_to_jiffies(300)); 1529 return; 1530 } 1531 } 1532 } 1533 1534 if (!eld->eld_valid || eld->eld_size <= 0) { 1535 eld->eld_valid = false; 1536 eld->eld_size = 0; 1537 } 1538 1539 /* for monitor disconnection, save pcm_idx firstly */ 1540 pcm_idx = per_pin->pcm_idx; 1541 1542 /* 1543 * pcm_idx >=0 before update_eld() means it is in monitor 1544 * disconnected event. Jack must be fetched before update_eld(). 1545 */ 1546 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); 1547 1548 if (spec->dyn_pcm_assign) { 1549 if (eld->eld_valid) { 1550 hdmi_attach_hda_pcm(spec, per_pin); 1551 hdmi_pcm_setup_pin(spec, per_pin); 1552 } else { 1553 hdmi_pcm_reset_pin(spec, per_pin); 1554 hdmi_detach_hda_pcm(spec, per_pin); 1555 } 1556 } 1557 /* if pcm_idx == -1, it means this is in monitor connection event 1558 * we can get the correct pcm_idx now. 1559 */ 1560 if (pcm_idx == -1) 1561 pcm_idx = per_pin->pcm_idx; 1562 if (!pcm_jack) 1563 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); 1564 1565 if (eld->eld_valid) 1566 snd_hdmi_show_eld(codec, &eld->info); 1567 1568 eld_changed = (pin_eld->eld_valid != eld->eld_valid); 1569 eld_changed |= (pin_eld->monitor_present != eld->monitor_present); 1570 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid) 1571 if (pin_eld->eld_size != eld->eld_size || 1572 memcmp(pin_eld->eld_buffer, eld->eld_buffer, 1573 eld->eld_size) != 0) 1574 eld_changed = true; 1575 1576 if (eld_changed) { 1577 pin_eld->monitor_present = eld->monitor_present; 1578 pin_eld->eld_valid = eld->eld_valid; 1579 pin_eld->eld_size = eld->eld_size; 1580 if (eld->eld_valid) 1581 memcpy(pin_eld->eld_buffer, eld->eld_buffer, 1582 eld->eld_size); 1583 pin_eld->info = eld->info; 1584 } 1585 1586 /* 1587 * Re-setup pin and infoframe. This is needed e.g. when 1588 * - sink is first plugged-in 1589 * - transcoder can change during stream playback on Haswell 1590 * and this can make HW reset converter selection on a pin. 1591 */ 1592 if (eld->eld_valid && !old_eld_valid && per_pin->setup) { 1593 pin_cvt_fixup(codec, per_pin, 0); 1594 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1595 } 1596 1597 if (eld_changed && pcm_idx >= 0) 1598 snd_ctl_notify(codec->card, 1599 SNDRV_CTL_EVENT_MASK_VALUE | 1600 SNDRV_CTL_EVENT_MASK_INFO, 1601 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); 1602 1603 if (eld_changed && pcm_jack) 1604 snd_jack_report(pcm_jack, 1605 (eld->monitor_present && eld->eld_valid) ? 1606 SND_JACK_AVOUT : 0); 1607 } 1608 1609 /* update ELD and jack state via HD-audio verbs */ 1610 static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, 1611 int repoll) 1612 { 1613 struct hda_codec *codec = per_pin->codec; 1614 struct hdmi_spec *spec = codec->spec; 1615 struct hdmi_eld *eld = &spec->temp_eld; 1616 hda_nid_t pin_nid = per_pin->pin_nid; 1617 int dev_id = per_pin->dev_id; 1618 /* 1619 * Always execute a GetPinSense verb here, even when called from 1620 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited 1621 * response's PD bit is not the real PD value, but indicates that 1622 * the real PD value changed. An older version of the HD-audio 1623 * specification worked this way. Hence, we just ignore the data in 1624 * the unsolicited response to avoid custom WARs. 1625 */ 1626 int present; 1627 int ret; 1628 1629 ret = snd_hda_power_up_pm(codec); 1630 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) 1631 goto out; 1632 1633 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id); 1634 1635 mutex_lock(&per_pin->lock); 1636 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); 1637 if (eld->monitor_present) 1638 eld->eld_valid = !!(present & AC_PINSENSE_ELDV); 1639 else 1640 eld->eld_valid = false; 1641 1642 codec_dbg(codec, 1643 "HDMI status: Codec=%d NID=0x%x Presence_Detect=%d ELD_Valid=%d\n", 1644 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); 1645 1646 if (eld->eld_valid) { 1647 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id, 1648 eld->eld_buffer, &eld->eld_size) < 0) 1649 eld->eld_valid = false; 1650 } 1651 1652 update_eld(codec, per_pin, eld, repoll); 1653 mutex_unlock(&per_pin->lock); 1654 out: 1655 snd_hda_power_down_pm(codec); 1656 } 1657 1658 #define I915_SILENT_RATE 48000 1659 #define I915_SILENT_CHANNELS 2 1660 #define I915_SILENT_FORMAT SNDRV_PCM_FORMAT_S16_LE 1661 #define I915_SILENT_FORMAT_BITS 16 1662 #define I915_SILENT_FMT_MASK 0xf 1663 1664 static void silent_stream_enable(struct hda_codec *codec, 1665 struct hdmi_spec_per_pin *per_pin) 1666 { 1667 struct hdmi_spec *spec = codec->spec; 1668 struct hdmi_spec_per_cvt *per_cvt; 1669 int cvt_idx, pin_idx, err; 1670 unsigned int format; 1671 1672 mutex_lock(&per_pin->lock); 1673 1674 if (per_pin->setup) { 1675 codec_dbg(codec, "hdmi: PCM already open, no silent stream\n"); 1676 goto unlock_out; 1677 } 1678 1679 pin_idx = pin_id_to_pin_index(codec, per_pin->pin_nid, per_pin->dev_id); 1680 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx); 1681 if (err) { 1682 codec_err(codec, "hdmi: no free converter to enable silent mode\n"); 1683 goto unlock_out; 1684 } 1685 1686 per_cvt = get_cvt(spec, cvt_idx); 1687 per_cvt->assigned = 1; 1688 per_pin->cvt_nid = per_cvt->cvt_nid; 1689 per_pin->silent_stream = true; 1690 1691 codec_dbg(codec, "hdmi: enabling silent stream pin-NID=0x%x cvt-NID=0x%x\n", 1692 per_pin->pin_nid, per_cvt->cvt_nid); 1693 1694 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1695 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1696 AC_VERB_SET_CONNECT_SEL, 1697 per_pin->mux_idx); 1698 1699 /* configure unused pins to choose other converters */ 1700 pin_cvt_fixup(codec, per_pin, 0); 1701 1702 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, 1703 per_pin->dev_id, I915_SILENT_RATE); 1704 1705 /* trigger silent stream generation in hw */ 1706 format = snd_hdac_calc_stream_format(I915_SILENT_RATE, I915_SILENT_CHANNELS, 1707 I915_SILENT_FORMAT, I915_SILENT_FORMAT_BITS, 0); 1708 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, 1709 I915_SILENT_FMT_MASK, I915_SILENT_FMT_MASK, format); 1710 usleep_range(100, 200); 1711 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, I915_SILENT_FMT_MASK, 0, format); 1712 1713 per_pin->channels = I915_SILENT_CHANNELS; 1714 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1715 1716 unlock_out: 1717 mutex_unlock(&per_pin->lock); 1718 } 1719 1720 static void silent_stream_disable(struct hda_codec *codec, 1721 struct hdmi_spec_per_pin *per_pin) 1722 { 1723 struct hdmi_spec *spec = codec->spec; 1724 struct hdmi_spec_per_cvt *per_cvt; 1725 int cvt_idx; 1726 1727 mutex_lock(&per_pin->lock); 1728 if (!per_pin->silent_stream) 1729 goto unlock_out; 1730 1731 codec_dbg(codec, "HDMI: disable silent stream on pin-NID=0x%x cvt-NID=0x%x\n", 1732 per_pin->pin_nid, per_pin->cvt_nid); 1733 1734 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid); 1735 if (cvt_idx >= 0 && cvt_idx < spec->num_cvts) { 1736 per_cvt = get_cvt(spec, cvt_idx); 1737 per_cvt->assigned = 0; 1738 } 1739 1740 per_pin->cvt_nid = 0; 1741 per_pin->silent_stream = false; 1742 1743 unlock_out: 1744 mutex_unlock(&per_pin->lock); 1745 } 1746 1747 /* update ELD and jack state via audio component */ 1748 static void sync_eld_via_acomp(struct hda_codec *codec, 1749 struct hdmi_spec_per_pin *per_pin) 1750 { 1751 struct hdmi_spec *spec = codec->spec; 1752 struct hdmi_eld *eld = &spec->temp_eld; 1753 bool monitor_prev, monitor_next; 1754 1755 mutex_lock(&per_pin->lock); 1756 eld->monitor_present = false; 1757 monitor_prev = per_pin->sink_eld.monitor_present; 1758 eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, 1759 per_pin->dev_id, &eld->monitor_present, 1760 eld->eld_buffer, ELD_MAX_SIZE); 1761 eld->eld_valid = (eld->eld_size > 0); 1762 update_eld(codec, per_pin, eld, 0); 1763 monitor_next = per_pin->sink_eld.monitor_present; 1764 mutex_unlock(&per_pin->lock); 1765 1766 /* 1767 * Power-up will call hdmi_present_sense, so the PM calls 1768 * have to be done without mutex held. 1769 */ 1770 1771 if (spec->send_silent_stream) { 1772 int pm_ret; 1773 1774 if (!monitor_prev && monitor_next) { 1775 pm_ret = snd_hda_power_up_pm(codec); 1776 if (pm_ret < 0) 1777 codec_err(codec, 1778 "Monitor plugged-in, Failed to power up codec ret=[%d]\n", 1779 pm_ret); 1780 silent_stream_enable(codec, per_pin); 1781 } else if (monitor_prev && !monitor_next) { 1782 silent_stream_disable(codec, per_pin); 1783 pm_ret = snd_hda_power_down_pm(codec); 1784 if (pm_ret < 0) 1785 codec_err(codec, 1786 "Monitor plugged-out, Failed to power down codec ret=[%d]\n", 1787 pm_ret); 1788 } 1789 } 1790 } 1791 1792 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) 1793 { 1794 struct hda_codec *codec = per_pin->codec; 1795 1796 if (!codec_has_acomp(codec)) 1797 hdmi_present_sense_via_verbs(per_pin, repoll); 1798 else 1799 sync_eld_via_acomp(codec, per_pin); 1800 } 1801 1802 static void hdmi_repoll_eld(struct work_struct *work) 1803 { 1804 struct hdmi_spec_per_pin *per_pin = 1805 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); 1806 struct hda_codec *codec = per_pin->codec; 1807 struct hdmi_spec *spec = codec->spec; 1808 struct hda_jack_tbl *jack; 1809 1810 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid, 1811 per_pin->dev_id); 1812 if (jack) 1813 jack->jack_dirty = 1; 1814 1815 if (per_pin->repoll_count++ > 6) 1816 per_pin->repoll_count = 0; 1817 1818 mutex_lock(&spec->pcm_lock); 1819 hdmi_present_sense(per_pin, per_pin->repoll_count); 1820 mutex_unlock(&spec->pcm_lock); 1821 } 1822 1823 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) 1824 { 1825 struct hdmi_spec *spec = codec->spec; 1826 unsigned int caps, config; 1827 int pin_idx; 1828 struct hdmi_spec_per_pin *per_pin; 1829 int err; 1830 int dev_num, i; 1831 1832 caps = snd_hda_query_pin_caps(codec, pin_nid); 1833 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) 1834 return 0; 1835 1836 /* 1837 * For DP MST audio, Configuration Default is the same for 1838 * all device entries on the same pin 1839 */ 1840 config = snd_hda_codec_get_pincfg(codec, pin_nid); 1841 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE && 1842 !spec->force_connect) 1843 return 0; 1844 1845 /* 1846 * To simplify the implementation, malloc all 1847 * the virtual pins in the initialization statically 1848 */ 1849 if (spec->intel_hsw_fixup) { 1850 /* 1851 * On Intel platforms, device entries number is 1852 * changed dynamically. If there is a DP MST 1853 * hub connected, the device entries number is 3. 1854 * Otherwise, it is 1. 1855 * Here we manually set dev_num to 3, so that 1856 * we can initialize all the device entries when 1857 * bootup statically. 1858 */ 1859 dev_num = 3; 1860 spec->dev_num = 3; 1861 } else if (spec->dyn_pcm_assign && codec->dp_mst) { 1862 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; 1863 /* 1864 * spec->dev_num is the maxinum number of device entries 1865 * among all the pins 1866 */ 1867 spec->dev_num = (spec->dev_num > dev_num) ? 1868 spec->dev_num : dev_num; 1869 } else { 1870 /* 1871 * If the platform doesn't support DP MST, 1872 * manually set dev_num to 1. This means 1873 * the pin has only one device entry. 1874 */ 1875 dev_num = 1; 1876 spec->dev_num = 1; 1877 } 1878 1879 for (i = 0; i < dev_num; i++) { 1880 pin_idx = spec->num_pins; 1881 per_pin = snd_array_new(&spec->pins); 1882 1883 if (!per_pin) 1884 return -ENOMEM; 1885 1886 if (spec->dyn_pcm_assign) { 1887 per_pin->pcm = NULL; 1888 per_pin->pcm_idx = -1; 1889 } else { 1890 per_pin->pcm = get_hdmi_pcm(spec, pin_idx); 1891 per_pin->pcm_idx = pin_idx; 1892 } 1893 per_pin->pin_nid = pin_nid; 1894 per_pin->pin_nid_idx = spec->num_nids; 1895 per_pin->dev_id = i; 1896 per_pin->non_pcm = false; 1897 snd_hda_set_dev_select(codec, pin_nid, i); 1898 err = hdmi_read_pin_conn(codec, pin_idx); 1899 if (err < 0) 1900 return err; 1901 spec->num_pins++; 1902 } 1903 spec->num_nids++; 1904 1905 return 0; 1906 } 1907 1908 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1909 { 1910 struct hdmi_spec *spec = codec->spec; 1911 struct hdmi_spec_per_cvt *per_cvt; 1912 unsigned int chans; 1913 int err; 1914 1915 chans = get_wcaps(codec, cvt_nid); 1916 chans = get_wcaps_channels(chans); 1917 1918 per_cvt = snd_array_new(&spec->cvts); 1919 if (!per_cvt) 1920 return -ENOMEM; 1921 1922 per_cvt->cvt_nid = cvt_nid; 1923 per_cvt->channels_min = 2; 1924 if (chans <= 16) { 1925 per_cvt->channels_max = chans; 1926 if (chans > spec->chmap.channels_max) 1927 spec->chmap.channels_max = chans; 1928 } 1929 1930 err = snd_hda_query_supported_pcm(codec, cvt_nid, 1931 &per_cvt->rates, 1932 &per_cvt->formats, 1933 &per_cvt->maxbps); 1934 if (err < 0) 1935 return err; 1936 1937 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) 1938 spec->cvt_nids[spec->num_cvts] = cvt_nid; 1939 spec->num_cvts++; 1940 1941 return 0; 1942 } 1943 1944 static const struct snd_pci_quirk force_connect_list[] = { 1945 SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1), 1946 SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1), 1947 {} 1948 }; 1949 1950 static int hdmi_parse_codec(struct hda_codec *codec) 1951 { 1952 struct hdmi_spec *spec = codec->spec; 1953 hda_nid_t start_nid; 1954 unsigned int caps; 1955 int i, nodes; 1956 const struct snd_pci_quirk *q; 1957 1958 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid); 1959 if (!start_nid || nodes < 0) { 1960 codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); 1961 return -EINVAL; 1962 } 1963 1964 q = snd_pci_quirk_lookup(codec->bus->pci, force_connect_list); 1965 1966 if (q && q->value) 1967 spec->force_connect = true; 1968 1969 /* 1970 * hdmi_add_pin() assumes total amount of converters to 1971 * be known, so first discover all converters 1972 */ 1973 for (i = 0; i < nodes; i++) { 1974 hda_nid_t nid = start_nid + i; 1975 1976 caps = get_wcaps(codec, nid); 1977 1978 if (!(caps & AC_WCAP_DIGITAL)) 1979 continue; 1980 1981 if (get_wcaps_type(caps) == AC_WID_AUD_OUT) 1982 hdmi_add_cvt(codec, nid); 1983 } 1984 1985 /* discover audio pins */ 1986 for (i = 0; i < nodes; i++) { 1987 hda_nid_t nid = start_nid + i; 1988 1989 caps = get_wcaps(codec, nid); 1990 1991 if (!(caps & AC_WCAP_DIGITAL)) 1992 continue; 1993 1994 if (get_wcaps_type(caps) == AC_WID_PIN) 1995 hdmi_add_pin(codec, nid); 1996 } 1997 1998 return 0; 1999 } 2000 2001 /* 2002 */ 2003 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 2004 { 2005 struct hda_spdif_out *spdif; 2006 bool non_pcm; 2007 2008 mutex_lock(&codec->spdif_mutex); 2009 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); 2010 /* Add sanity check to pass klockwork check. 2011 * This should never happen. 2012 */ 2013 if (WARN_ON(spdif == NULL)) { 2014 mutex_unlock(&codec->spdif_mutex); 2015 return true; 2016 } 2017 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); 2018 mutex_unlock(&codec->spdif_mutex); 2019 return non_pcm; 2020 } 2021 2022 /* 2023 * HDMI callbacks 2024 */ 2025 2026 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 2027 struct hda_codec *codec, 2028 unsigned int stream_tag, 2029 unsigned int format, 2030 struct snd_pcm_substream *substream) 2031 { 2032 hda_nid_t cvt_nid = hinfo->nid; 2033 struct hdmi_spec *spec = codec->spec; 2034 int pin_idx; 2035 struct hdmi_spec_per_pin *per_pin; 2036 struct snd_pcm_runtime *runtime = substream->runtime; 2037 bool non_pcm; 2038 int pinctl, stripe; 2039 int err = 0; 2040 2041 mutex_lock(&spec->pcm_lock); 2042 pin_idx = hinfo_to_pin_index(codec, hinfo); 2043 if (spec->dyn_pcm_assign && pin_idx < 0) { 2044 /* when dyn_pcm_assign and pcm is not bound to a pin 2045 * skip pin setup and return 0 to make audio playback 2046 * be ongoing 2047 */ 2048 pin_cvt_fixup(codec, NULL, cvt_nid); 2049 snd_hda_codec_setup_stream(codec, cvt_nid, 2050 stream_tag, 0, format); 2051 goto unlock; 2052 } 2053 2054 if (snd_BUG_ON(pin_idx < 0)) { 2055 err = -EINVAL; 2056 goto unlock; 2057 } 2058 per_pin = get_pin(spec, pin_idx); 2059 2060 /* Verify pin:cvt selections to avoid silent audio after S3. 2061 * After S3, the audio driver restores pin:cvt selections 2062 * but this can happen before gfx is ready and such selection 2063 * is overlooked by HW. Thus multiple pins can share a same 2064 * default convertor and mute control will affect each other, 2065 * which can cause a resumed audio playback become silent 2066 * after S3. 2067 */ 2068 pin_cvt_fixup(codec, per_pin, 0); 2069 2070 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ 2071 /* Todo: add DP1.2 MST audio support later */ 2072 if (codec_has_acomp(codec)) 2073 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, 2074 per_pin->dev_id, runtime->rate); 2075 2076 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); 2077 mutex_lock(&per_pin->lock); 2078 per_pin->channels = substream->runtime->channels; 2079 per_pin->setup = true; 2080 2081 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) { 2082 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core, 2083 substream); 2084 snd_hda_codec_write(codec, cvt_nid, 0, 2085 AC_VERB_SET_STRIPE_CONTROL, 2086 stripe); 2087 } 2088 2089 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 2090 mutex_unlock(&per_pin->lock); 2091 if (spec->dyn_pin_out) { 2092 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2093 per_pin->dev_id); 2094 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2095 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2096 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2097 AC_VERB_SET_PIN_WIDGET_CONTROL, 2098 pinctl | PIN_OUT); 2099 } 2100 2101 /* snd_hda_set_dev_select() has been called before */ 2102 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid, 2103 per_pin->dev_id, stream_tag, format); 2104 unlock: 2105 mutex_unlock(&spec->pcm_lock); 2106 return err; 2107 } 2108 2109 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 2110 struct hda_codec *codec, 2111 struct snd_pcm_substream *substream) 2112 { 2113 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 2114 return 0; 2115 } 2116 2117 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, 2118 struct hda_codec *codec, 2119 struct snd_pcm_substream *substream) 2120 { 2121 struct hdmi_spec *spec = codec->spec; 2122 int cvt_idx, pin_idx, pcm_idx; 2123 struct hdmi_spec_per_cvt *per_cvt; 2124 struct hdmi_spec_per_pin *per_pin; 2125 int pinctl; 2126 int err = 0; 2127 2128 mutex_lock(&spec->pcm_lock); 2129 if (hinfo->nid) { 2130 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 2131 if (snd_BUG_ON(pcm_idx < 0)) { 2132 err = -EINVAL; 2133 goto unlock; 2134 } 2135 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); 2136 if (snd_BUG_ON(cvt_idx < 0)) { 2137 err = -EINVAL; 2138 goto unlock; 2139 } 2140 per_cvt = get_cvt(spec, cvt_idx); 2141 per_cvt->assigned = 0; 2142 hinfo->nid = 0; 2143 2144 azx_stream(get_azx_dev(substream))->stripe = 0; 2145 2146 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2147 clear_bit(pcm_idx, &spec->pcm_in_use); 2148 pin_idx = hinfo_to_pin_index(codec, hinfo); 2149 if (spec->dyn_pcm_assign && pin_idx < 0) 2150 goto unlock; 2151 2152 if (snd_BUG_ON(pin_idx < 0)) { 2153 err = -EINVAL; 2154 goto unlock; 2155 } 2156 per_pin = get_pin(spec, pin_idx); 2157 2158 if (spec->dyn_pin_out) { 2159 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2160 per_pin->dev_id); 2161 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2162 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2163 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2164 AC_VERB_SET_PIN_WIDGET_CONTROL, 2165 pinctl & ~PIN_OUT); 2166 } 2167 2168 mutex_lock(&per_pin->lock); 2169 per_pin->chmap_set = false; 2170 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 2171 2172 per_pin->setup = false; 2173 per_pin->channels = 0; 2174 mutex_unlock(&per_pin->lock); 2175 } 2176 2177 unlock: 2178 mutex_unlock(&spec->pcm_lock); 2179 2180 return err; 2181 } 2182 2183 static const struct hda_pcm_ops generic_ops = { 2184 .open = hdmi_pcm_open, 2185 .close = hdmi_pcm_close, 2186 .prepare = generic_hdmi_playback_pcm_prepare, 2187 .cleanup = generic_hdmi_playback_pcm_cleanup, 2188 }; 2189 2190 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) 2191 { 2192 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2193 struct hdmi_spec *spec = codec->spec; 2194 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2195 2196 if (!per_pin) 2197 return 0; 2198 2199 return per_pin->sink_eld.info.spk_alloc; 2200 } 2201 2202 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, 2203 unsigned char *chmap) 2204 { 2205 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2206 struct hdmi_spec *spec = codec->spec; 2207 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2208 2209 /* chmap is already set to 0 in caller */ 2210 if (!per_pin) 2211 return; 2212 2213 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); 2214 } 2215 2216 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, 2217 unsigned char *chmap, int prepared) 2218 { 2219 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2220 struct hdmi_spec *spec = codec->spec; 2221 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2222 2223 if (!per_pin) 2224 return; 2225 mutex_lock(&per_pin->lock); 2226 per_pin->chmap_set = true; 2227 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); 2228 if (prepared) 2229 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 2230 mutex_unlock(&per_pin->lock); 2231 } 2232 2233 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) 2234 { 2235 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2236 struct hdmi_spec *spec = codec->spec; 2237 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2238 2239 return per_pin ? true:false; 2240 } 2241 2242 static int generic_hdmi_build_pcms(struct hda_codec *codec) 2243 { 2244 struct hdmi_spec *spec = codec->spec; 2245 int idx, pcm_num; 2246 2247 /* 2248 * for non-mst mode, pcm number is the same as before 2249 * for DP MST mode without extra PCM, pcm number is same 2250 * for DP MST mode with extra PCMs, pcm number is 2251 * (nid number + dev_num - 1) 2252 * dev_num is the device entry number in a pin 2253 */ 2254 2255 if (codec->mst_no_extra_pcms) 2256 pcm_num = spec->num_nids; 2257 else 2258 pcm_num = spec->num_nids + spec->dev_num - 1; 2259 2260 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num); 2261 2262 for (idx = 0; idx < pcm_num; idx++) { 2263 struct hda_pcm *info; 2264 struct hda_pcm_stream *pstr; 2265 2266 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); 2267 if (!info) 2268 return -ENOMEM; 2269 2270 spec->pcm_rec[idx].pcm = info; 2271 spec->pcm_used++; 2272 info->pcm_type = HDA_PCM_TYPE_HDMI; 2273 info->own_chmap = true; 2274 2275 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2276 pstr->substreams = 1; 2277 pstr->ops = generic_ops; 2278 /* pcm number is less than 16 */ 2279 if (spec->pcm_used >= 16) 2280 break; 2281 /* other pstr fields are set in open */ 2282 } 2283 2284 return 0; 2285 } 2286 2287 static void free_hdmi_jack_priv(struct snd_jack *jack) 2288 { 2289 struct hdmi_pcm *pcm = jack->private_data; 2290 2291 pcm->jack = NULL; 2292 } 2293 2294 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) 2295 { 2296 char hdmi_str[32] = "HDMI/DP"; 2297 struct hdmi_spec *spec = codec->spec; 2298 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pcm_idx); 2299 struct snd_jack *jack; 2300 int pcmdev = get_pcm_rec(spec, pcm_idx)->device; 2301 int err; 2302 2303 if (pcmdev > 0) 2304 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); 2305 if (!spec->dyn_pcm_assign && 2306 !is_jack_detectable(codec, per_pin->pin_nid)) 2307 strncat(hdmi_str, " Phantom", 2308 sizeof(hdmi_str) - strlen(hdmi_str) - 1); 2309 2310 err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack, 2311 true, false); 2312 if (err < 0) 2313 return err; 2314 2315 spec->pcm_rec[pcm_idx].jack = jack; 2316 jack->private_data = &spec->pcm_rec[pcm_idx]; 2317 jack->private_free = free_hdmi_jack_priv; 2318 return 0; 2319 } 2320 2321 static int generic_hdmi_build_controls(struct hda_codec *codec) 2322 { 2323 struct hdmi_spec *spec = codec->spec; 2324 int dev, err; 2325 int pin_idx, pcm_idx; 2326 2327 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2328 if (!get_pcm_rec(spec, pcm_idx)->pcm) { 2329 /* no PCM: mark this for skipping permanently */ 2330 set_bit(pcm_idx, &spec->pcm_bitmap); 2331 continue; 2332 } 2333 2334 err = generic_hdmi_build_jack(codec, pcm_idx); 2335 if (err < 0) 2336 return err; 2337 2338 /* create the spdif for each pcm 2339 * pin will be bound when monitor is connected 2340 */ 2341 if (spec->dyn_pcm_assign) 2342 err = snd_hda_create_dig_out_ctls(codec, 2343 0, spec->cvt_nids[0], 2344 HDA_PCM_TYPE_HDMI); 2345 else { 2346 struct hdmi_spec_per_pin *per_pin = 2347 get_pin(spec, pcm_idx); 2348 err = snd_hda_create_dig_out_ctls(codec, 2349 per_pin->pin_nid, 2350 per_pin->mux_nids[0], 2351 HDA_PCM_TYPE_HDMI); 2352 } 2353 if (err < 0) 2354 return err; 2355 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2356 2357 dev = get_pcm_rec(spec, pcm_idx)->device; 2358 if (dev != SNDRV_PCM_INVALID_DEVICE) { 2359 /* add control for ELD Bytes */ 2360 err = hdmi_create_eld_ctl(codec, pcm_idx, dev); 2361 if (err < 0) 2362 return err; 2363 } 2364 } 2365 2366 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2367 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2368 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 2369 2370 pin_eld->eld_valid = false; 2371 hdmi_present_sense(per_pin, 0); 2372 } 2373 2374 /* add channel maps */ 2375 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2376 struct hda_pcm *pcm; 2377 2378 pcm = get_pcm_rec(spec, pcm_idx); 2379 if (!pcm || !pcm->pcm) 2380 break; 2381 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); 2382 if (err < 0) 2383 return err; 2384 } 2385 2386 return 0; 2387 } 2388 2389 static int generic_hdmi_init_per_pins(struct hda_codec *codec) 2390 { 2391 struct hdmi_spec *spec = codec->spec; 2392 int pin_idx; 2393 2394 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2395 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2396 2397 per_pin->codec = codec; 2398 mutex_init(&per_pin->lock); 2399 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); 2400 eld_proc_new(per_pin, pin_idx); 2401 } 2402 return 0; 2403 } 2404 2405 static int generic_hdmi_init(struct hda_codec *codec) 2406 { 2407 struct hdmi_spec *spec = codec->spec; 2408 int pin_idx; 2409 2410 mutex_lock(&spec->bind_lock); 2411 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2412 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2413 hda_nid_t pin_nid = per_pin->pin_nid; 2414 int dev_id = per_pin->dev_id; 2415 2416 snd_hda_set_dev_select(codec, pin_nid, dev_id); 2417 hdmi_init_pin(codec, pin_nid); 2418 if (codec_has_acomp(codec)) 2419 continue; 2420 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id, 2421 jack_callback); 2422 } 2423 mutex_unlock(&spec->bind_lock); 2424 return 0; 2425 } 2426 2427 static void hdmi_array_init(struct hdmi_spec *spec, int nums) 2428 { 2429 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); 2430 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); 2431 } 2432 2433 static void hdmi_array_free(struct hdmi_spec *spec) 2434 { 2435 snd_array_free(&spec->pins); 2436 snd_array_free(&spec->cvts); 2437 } 2438 2439 static void generic_spec_free(struct hda_codec *codec) 2440 { 2441 struct hdmi_spec *spec = codec->spec; 2442 2443 if (spec) { 2444 hdmi_array_free(spec); 2445 kfree(spec); 2446 codec->spec = NULL; 2447 } 2448 codec->dp_mst = false; 2449 } 2450 2451 static void generic_hdmi_free(struct hda_codec *codec) 2452 { 2453 struct hdmi_spec *spec = codec->spec; 2454 int pin_idx, pcm_idx; 2455 2456 if (spec->acomp_registered) { 2457 snd_hdac_acomp_exit(&codec->bus->core); 2458 } else if (codec_has_acomp(codec)) { 2459 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL); 2460 } 2461 codec->relaxed_resume = 0; 2462 2463 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2464 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2465 cancel_delayed_work_sync(&per_pin->work); 2466 eld_proc_free(per_pin); 2467 } 2468 2469 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2470 if (spec->pcm_rec[pcm_idx].jack == NULL) 2471 continue; 2472 if (spec->dyn_pcm_assign) 2473 snd_device_free(codec->card, 2474 spec->pcm_rec[pcm_idx].jack); 2475 else 2476 spec->pcm_rec[pcm_idx].jack = NULL; 2477 } 2478 2479 generic_spec_free(codec); 2480 } 2481 2482 #ifdef CONFIG_PM 2483 static int generic_hdmi_suspend(struct hda_codec *codec) 2484 { 2485 struct hdmi_spec *spec = codec->spec; 2486 int pin_idx; 2487 2488 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2489 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2490 cancel_delayed_work_sync(&per_pin->work); 2491 } 2492 return 0; 2493 } 2494 2495 static int generic_hdmi_resume(struct hda_codec *codec) 2496 { 2497 struct hdmi_spec *spec = codec->spec; 2498 int pin_idx; 2499 2500 codec->patch_ops.init(codec); 2501 snd_hda_regmap_sync(codec); 2502 2503 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2504 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2505 hdmi_present_sense(per_pin, 1); 2506 } 2507 return 0; 2508 } 2509 #endif 2510 2511 static const struct hda_codec_ops generic_hdmi_patch_ops = { 2512 .init = generic_hdmi_init, 2513 .free = generic_hdmi_free, 2514 .build_pcms = generic_hdmi_build_pcms, 2515 .build_controls = generic_hdmi_build_controls, 2516 .unsol_event = hdmi_unsol_event, 2517 #ifdef CONFIG_PM 2518 .suspend = generic_hdmi_suspend, 2519 .resume = generic_hdmi_resume, 2520 #endif 2521 }; 2522 2523 static const struct hdmi_ops generic_standard_hdmi_ops = { 2524 .pin_get_eld = hdmi_pin_get_eld, 2525 .pin_setup_infoframe = hdmi_pin_setup_infoframe, 2526 .pin_hbr_setup = hdmi_pin_hbr_setup, 2527 .setup_stream = hdmi_setup_stream, 2528 }; 2529 2530 /* allocate codec->spec and assign/initialize generic parser ops */ 2531 static int alloc_generic_hdmi(struct hda_codec *codec) 2532 { 2533 struct hdmi_spec *spec; 2534 2535 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2536 if (!spec) 2537 return -ENOMEM; 2538 2539 spec->codec = codec; 2540 spec->ops = generic_standard_hdmi_ops; 2541 spec->dev_num = 1; /* initialize to 1 */ 2542 mutex_init(&spec->pcm_lock); 2543 mutex_init(&spec->bind_lock); 2544 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); 2545 2546 spec->chmap.ops.get_chmap = hdmi_get_chmap; 2547 spec->chmap.ops.set_chmap = hdmi_set_chmap; 2548 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; 2549 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc; 2550 2551 codec->spec = spec; 2552 hdmi_array_init(spec, 4); 2553 2554 codec->patch_ops = generic_hdmi_patch_ops; 2555 2556 return 0; 2557 } 2558 2559 /* generic HDMI parser */ 2560 static int patch_generic_hdmi(struct hda_codec *codec) 2561 { 2562 int err; 2563 2564 err = alloc_generic_hdmi(codec); 2565 if (err < 0) 2566 return err; 2567 2568 err = hdmi_parse_codec(codec); 2569 if (err < 0) { 2570 generic_spec_free(codec); 2571 return err; 2572 } 2573 2574 generic_hdmi_init_per_pins(codec); 2575 return 0; 2576 } 2577 2578 /* 2579 * generic audio component binding 2580 */ 2581 2582 /* turn on / off the unsol event jack detection dynamically */ 2583 static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid, 2584 int dev_id, bool use_acomp) 2585 { 2586 struct hda_jack_tbl *tbl; 2587 2588 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id); 2589 if (tbl) { 2590 /* clear unsol even if component notifier is used, or re-enable 2591 * if notifier is cleared 2592 */ 2593 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag); 2594 snd_hda_codec_write_cache(codec, nid, 0, 2595 AC_VERB_SET_UNSOLICITED_ENABLE, val); 2596 } 2597 } 2598 2599 /* set up / clear component notifier dynamically */ 2600 static void generic_acomp_notifier_set(struct drm_audio_component *acomp, 2601 bool use_acomp) 2602 { 2603 struct hdmi_spec *spec; 2604 int i; 2605 2606 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops); 2607 mutex_lock(&spec->bind_lock); 2608 spec->use_acomp_notifier = use_acomp; 2609 spec->codec->relaxed_resume = use_acomp; 2610 spec->codec->bus->keep_power = 0; 2611 /* reprogram each jack detection logic depending on the notifier */ 2612 for (i = 0; i < spec->num_pins; i++) 2613 reprogram_jack_detect(spec->codec, 2614 get_pin(spec, i)->pin_nid, 2615 get_pin(spec, i)->dev_id, 2616 use_acomp); 2617 mutex_unlock(&spec->bind_lock); 2618 } 2619 2620 /* enable / disable the notifier via master bind / unbind */ 2621 static int generic_acomp_master_bind(struct device *dev, 2622 struct drm_audio_component *acomp) 2623 { 2624 generic_acomp_notifier_set(acomp, true); 2625 return 0; 2626 } 2627 2628 static void generic_acomp_master_unbind(struct device *dev, 2629 struct drm_audio_component *acomp) 2630 { 2631 generic_acomp_notifier_set(acomp, false); 2632 } 2633 2634 /* check whether both HD-audio and DRM PCI devices belong to the same bus */ 2635 static int match_bound_vga(struct device *dev, int subtype, void *data) 2636 { 2637 struct hdac_bus *bus = data; 2638 struct pci_dev *pci, *master; 2639 2640 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev)) 2641 return 0; 2642 master = to_pci_dev(bus->dev); 2643 pci = to_pci_dev(dev); 2644 return master->bus == pci->bus; 2645 } 2646 2647 /* audio component notifier for AMD/Nvidia HDMI codecs */ 2648 static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id) 2649 { 2650 struct hda_codec *codec = audio_ptr; 2651 struct hdmi_spec *spec = codec->spec; 2652 hda_nid_t pin_nid = spec->port2pin(codec, port); 2653 2654 if (!pin_nid) 2655 return; 2656 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN) 2657 return; 2658 /* skip notification during system suspend (but not in runtime PM); 2659 * the state will be updated at resume 2660 */ 2661 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) 2662 return; 2663 /* ditto during suspend/resume process itself */ 2664 if (snd_hdac_is_in_pm(&codec->core)) 2665 return; 2666 2667 check_presence_and_report(codec, pin_nid, dev_id); 2668 } 2669 2670 /* set up the private drm_audio_ops from the template */ 2671 static void setup_drm_audio_ops(struct hda_codec *codec, 2672 const struct drm_audio_component_audio_ops *ops) 2673 { 2674 struct hdmi_spec *spec = codec->spec; 2675 2676 spec->drm_audio_ops.audio_ptr = codec; 2677 /* intel_audio_codec_enable() or intel_audio_codec_disable() 2678 * will call pin_eld_notify with using audio_ptr pointer 2679 * We need make sure audio_ptr is really setup 2680 */ 2681 wmb(); 2682 spec->drm_audio_ops.pin2port = ops->pin2port; 2683 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify; 2684 spec->drm_audio_ops.master_bind = ops->master_bind; 2685 spec->drm_audio_ops.master_unbind = ops->master_unbind; 2686 } 2687 2688 /* initialize the generic HDMI audio component */ 2689 static void generic_acomp_init(struct hda_codec *codec, 2690 const struct drm_audio_component_audio_ops *ops, 2691 int (*port2pin)(struct hda_codec *, int)) 2692 { 2693 struct hdmi_spec *spec = codec->spec; 2694 2695 if (!enable_acomp) { 2696 codec_info(codec, "audio component disabled by module option\n"); 2697 return; 2698 } 2699 2700 spec->port2pin = port2pin; 2701 setup_drm_audio_ops(codec, ops); 2702 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops, 2703 match_bound_vga, 0)) { 2704 spec->acomp_registered = true; 2705 } 2706 } 2707 2708 /* 2709 * Intel codec parsers and helpers 2710 */ 2711 2712 #define INTEL_GET_VENDOR_VERB 0xf81 2713 #define INTEL_SET_VENDOR_VERB 0x781 2714 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ 2715 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ 2716 2717 static void intel_haswell_enable_all_pins(struct hda_codec *codec, 2718 bool update_tree) 2719 { 2720 unsigned int vendor_param; 2721 struct hdmi_spec *spec = codec->spec; 2722 2723 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2724 INTEL_GET_VENDOR_VERB, 0); 2725 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) 2726 return; 2727 2728 vendor_param |= INTEL_EN_ALL_PIN_CVTS; 2729 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2730 INTEL_SET_VENDOR_VERB, vendor_param); 2731 if (vendor_param == -1) 2732 return; 2733 2734 if (update_tree) 2735 snd_hda_codec_update_widgets(codec); 2736 } 2737 2738 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) 2739 { 2740 unsigned int vendor_param; 2741 struct hdmi_spec *spec = codec->spec; 2742 2743 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2744 INTEL_GET_VENDOR_VERB, 0); 2745 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) 2746 return; 2747 2748 /* enable DP1.2 mode */ 2749 vendor_param |= INTEL_EN_DP12; 2750 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); 2751 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, 2752 INTEL_SET_VENDOR_VERB, vendor_param); 2753 } 2754 2755 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. 2756 * Otherwise you may get severe h/w communication errors. 2757 */ 2758 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, 2759 unsigned int power_state) 2760 { 2761 if (power_state == AC_PWRST_D0) { 2762 intel_haswell_enable_all_pins(codec, false); 2763 intel_haswell_fixup_enable_dp12(codec); 2764 } 2765 2766 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); 2767 snd_hda_codec_set_power_to_all(codec, fg, power_state); 2768 } 2769 2770 /* There is a fixed mapping between audio pin node and display port. 2771 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL: 2772 * Pin Widget 5 - PORT B (port = 1 in i915 driver) 2773 * Pin Widget 6 - PORT C (port = 2 in i915 driver) 2774 * Pin Widget 7 - PORT D (port = 3 in i915 driver) 2775 * 2776 * on VLV, ILK: 2777 * Pin Widget 4 - PORT B (port = 1 in i915 driver) 2778 * Pin Widget 5 - PORT C (port = 2 in i915 driver) 2779 * Pin Widget 6 - PORT D (port = 3 in i915 driver) 2780 */ 2781 static int intel_base_nid(struct hda_codec *codec) 2782 { 2783 switch (codec->core.vendor_id) { 2784 case 0x80860054: /* ILK */ 2785 case 0x80862804: /* ILK */ 2786 case 0x80862882: /* VLV */ 2787 return 4; 2788 default: 2789 return 5; 2790 } 2791 } 2792 2793 static int intel_pin2port(void *audio_ptr, int pin_nid) 2794 { 2795 struct hda_codec *codec = audio_ptr; 2796 struct hdmi_spec *spec = codec->spec; 2797 int base_nid, i; 2798 2799 if (!spec->port_num) { 2800 base_nid = intel_base_nid(codec); 2801 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3)) 2802 return -1; 2803 return pin_nid - base_nid + 1; 2804 } 2805 2806 /* 2807 * looking for the pin number in the mapping table and return 2808 * the index which indicate the port number 2809 */ 2810 for (i = 0; i < spec->port_num; i++) { 2811 if (pin_nid == spec->port_map[i]) 2812 return i; 2813 } 2814 2815 codec_info(codec, "Can't find the HDMI/DP port for pin NID 0x%x\n", pin_nid); 2816 return -1; 2817 } 2818 2819 static int intel_port2pin(struct hda_codec *codec, int port) 2820 { 2821 struct hdmi_spec *spec = codec->spec; 2822 2823 if (!spec->port_num) { 2824 /* we assume only from port-B to port-D */ 2825 if (port < 1 || port > 3) 2826 return 0; 2827 return port + intel_base_nid(codec) - 1; 2828 } 2829 2830 if (port < 0 || port >= spec->port_num) 2831 return 0; 2832 return spec->port_map[port]; 2833 } 2834 2835 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) 2836 { 2837 struct hda_codec *codec = audio_ptr; 2838 int pin_nid; 2839 int dev_id = pipe; 2840 2841 pin_nid = intel_port2pin(codec, port); 2842 if (!pin_nid) 2843 return; 2844 /* skip notification during system suspend (but not in runtime PM); 2845 * the state will be updated at resume 2846 */ 2847 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) 2848 return; 2849 /* ditto during suspend/resume process itself */ 2850 if (snd_hdac_is_in_pm(&codec->core)) 2851 return; 2852 2853 snd_hdac_i915_set_bclk(&codec->bus->core); 2854 check_presence_and_report(codec, pin_nid, dev_id); 2855 } 2856 2857 static const struct drm_audio_component_audio_ops intel_audio_ops = { 2858 .pin2port = intel_pin2port, 2859 .pin_eld_notify = intel_pin_eld_notify, 2860 }; 2861 2862 /* register i915 component pin_eld_notify callback */ 2863 static void register_i915_notifier(struct hda_codec *codec) 2864 { 2865 struct hdmi_spec *spec = codec->spec; 2866 2867 spec->use_acomp_notifier = true; 2868 spec->port2pin = intel_port2pin; 2869 setup_drm_audio_ops(codec, &intel_audio_ops); 2870 snd_hdac_acomp_register_notifier(&codec->bus->core, 2871 &spec->drm_audio_ops); 2872 /* no need for forcible resume for jack check thanks to notifier */ 2873 codec->relaxed_resume = 1; 2874 } 2875 2876 /* setup_stream ops override for HSW+ */ 2877 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 2878 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 2879 int format) 2880 { 2881 haswell_verify_D0(codec, cvt_nid, pin_nid); 2882 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 2883 stream_tag, format); 2884 } 2885 2886 /* pin_cvt_fixup ops override for HSW+ and VLV+ */ 2887 static void i915_pin_cvt_fixup(struct hda_codec *codec, 2888 struct hdmi_spec_per_pin *per_pin, 2889 hda_nid_t cvt_nid) 2890 { 2891 if (per_pin) { 2892 haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid); 2893 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2894 per_pin->dev_id); 2895 intel_verify_pin_cvt_connect(codec, per_pin); 2896 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, 2897 per_pin->dev_id, per_pin->mux_idx); 2898 } else { 2899 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); 2900 } 2901 } 2902 2903 /* precondition and allocation for Intel codecs */ 2904 static int alloc_intel_hdmi(struct hda_codec *codec) 2905 { 2906 int err; 2907 2908 /* requires i915 binding */ 2909 if (!codec->bus->core.audio_component) { 2910 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); 2911 /* set probe_id here to prevent generic fallback binding */ 2912 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE; 2913 return -ENODEV; 2914 } 2915 2916 err = alloc_generic_hdmi(codec); 2917 if (err < 0) 2918 return err; 2919 /* no need to handle unsol events */ 2920 codec->patch_ops.unsol_event = NULL; 2921 return 0; 2922 } 2923 2924 /* parse and post-process for Intel codecs */ 2925 static int parse_intel_hdmi(struct hda_codec *codec) 2926 { 2927 int err, retries = 3; 2928 2929 do { 2930 err = hdmi_parse_codec(codec); 2931 } while (err < 0 && retries--); 2932 2933 if (err < 0) { 2934 generic_spec_free(codec); 2935 return err; 2936 } 2937 2938 generic_hdmi_init_per_pins(codec); 2939 register_i915_notifier(codec); 2940 return 0; 2941 } 2942 2943 /* Intel Haswell and onwards; audio component with eld notifier */ 2944 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid, 2945 const int *port_map, int port_num) 2946 { 2947 struct hdmi_spec *spec; 2948 int err; 2949 2950 err = alloc_intel_hdmi(codec); 2951 if (err < 0) 2952 return err; 2953 spec = codec->spec; 2954 codec->dp_mst = true; 2955 spec->dyn_pcm_assign = true; 2956 spec->vendor_nid = vendor_nid; 2957 spec->port_map = port_map; 2958 spec->port_num = port_num; 2959 spec->intel_hsw_fixup = true; 2960 2961 intel_haswell_enable_all_pins(codec, true); 2962 intel_haswell_fixup_enable_dp12(codec); 2963 2964 codec->display_power_control = 1; 2965 2966 codec->patch_ops.set_power_state = haswell_set_power_state; 2967 codec->depop_delay = 0; 2968 codec->auto_runtime_pm = 1; 2969 2970 spec->ops.setup_stream = i915_hsw_setup_stream; 2971 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2972 2973 /* 2974 * Enable silent stream feature, if it is enabled via 2975 * module param or Kconfig option 2976 */ 2977 if (enable_silent_stream) 2978 spec->send_silent_stream = true; 2979 2980 return parse_intel_hdmi(codec); 2981 } 2982 2983 static int patch_i915_hsw_hdmi(struct hda_codec *codec) 2984 { 2985 return intel_hsw_common_init(codec, 0x08, NULL, 0); 2986 } 2987 2988 static int patch_i915_glk_hdmi(struct hda_codec *codec) 2989 { 2990 return intel_hsw_common_init(codec, 0x0b, NULL, 0); 2991 } 2992 2993 static int patch_i915_icl_hdmi(struct hda_codec *codec) 2994 { 2995 /* 2996 * pin to port mapping table where the value indicate the pin number and 2997 * the index indicate the port number. 2998 */ 2999 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb}; 3000 3001 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map)); 3002 } 3003 3004 static int patch_i915_tgl_hdmi(struct hda_codec *codec) 3005 { 3006 /* 3007 * pin to port mapping table where the value indicate the pin number and 3008 * the index indicate the port number. 3009 */ 3010 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf}; 3011 int ret; 3012 3013 ret = intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map)); 3014 if (!ret) { 3015 struct hdmi_spec *spec = codec->spec; 3016 3017 spec->dyn_pcm_no_legacy = true; 3018 } 3019 3020 return ret; 3021 } 3022 3023 /* Intel Baytrail and Braswell; with eld notifier */ 3024 static int patch_i915_byt_hdmi(struct hda_codec *codec) 3025 { 3026 struct hdmi_spec *spec; 3027 int err; 3028 3029 err = alloc_intel_hdmi(codec); 3030 if (err < 0) 3031 return err; 3032 spec = codec->spec; 3033 3034 /* For Valleyview/Cherryview, only the display codec is in the display 3035 * power well and can use link_power ops to request/release the power. 3036 */ 3037 codec->display_power_control = 1; 3038 3039 codec->depop_delay = 0; 3040 codec->auto_runtime_pm = 1; 3041 3042 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 3043 3044 return parse_intel_hdmi(codec); 3045 } 3046 3047 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ 3048 static int patch_i915_cpt_hdmi(struct hda_codec *codec) 3049 { 3050 int err; 3051 3052 err = alloc_intel_hdmi(codec); 3053 if (err < 0) 3054 return err; 3055 return parse_intel_hdmi(codec); 3056 } 3057 3058 /* 3059 * Shared non-generic implementations 3060 */ 3061 3062 static int simple_playback_build_pcms(struct hda_codec *codec) 3063 { 3064 struct hdmi_spec *spec = codec->spec; 3065 struct hda_pcm *info; 3066 unsigned int chans; 3067 struct hda_pcm_stream *pstr; 3068 struct hdmi_spec_per_cvt *per_cvt; 3069 3070 per_cvt = get_cvt(spec, 0); 3071 chans = get_wcaps(codec, per_cvt->cvt_nid); 3072 chans = get_wcaps_channels(chans); 3073 3074 info = snd_hda_codec_pcm_new(codec, "HDMI 0"); 3075 if (!info) 3076 return -ENOMEM; 3077 spec->pcm_rec[0].pcm = info; 3078 info->pcm_type = HDA_PCM_TYPE_HDMI; 3079 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3080 *pstr = spec->pcm_playback; 3081 pstr->nid = per_cvt->cvt_nid; 3082 if (pstr->channels_max <= 2 && chans && chans <= 16) 3083 pstr->channels_max = chans; 3084 3085 return 0; 3086 } 3087 3088 /* unsolicited event for jack sensing */ 3089 static void simple_hdmi_unsol_event(struct hda_codec *codec, 3090 unsigned int res) 3091 { 3092 snd_hda_jack_set_dirty_all(codec); 3093 snd_hda_jack_report_sync(codec); 3094 } 3095 3096 /* generic_hdmi_build_jack can be used for simple_hdmi, too, 3097 * as long as spec->pins[] is set correctly 3098 */ 3099 #define simple_hdmi_build_jack generic_hdmi_build_jack 3100 3101 static int simple_playback_build_controls(struct hda_codec *codec) 3102 { 3103 struct hdmi_spec *spec = codec->spec; 3104 struct hdmi_spec_per_cvt *per_cvt; 3105 int err; 3106 3107 per_cvt = get_cvt(spec, 0); 3108 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, 3109 per_cvt->cvt_nid, 3110 HDA_PCM_TYPE_HDMI); 3111 if (err < 0) 3112 return err; 3113 return simple_hdmi_build_jack(codec, 0); 3114 } 3115 3116 static int simple_playback_init(struct hda_codec *codec) 3117 { 3118 struct hdmi_spec *spec = codec->spec; 3119 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); 3120 hda_nid_t pin = per_pin->pin_nid; 3121 3122 snd_hda_codec_write(codec, pin, 0, 3123 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); 3124 /* some codecs require to unmute the pin */ 3125 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 3126 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, 3127 AMP_OUT_UNMUTE); 3128 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id); 3129 return 0; 3130 } 3131 3132 static void simple_playback_free(struct hda_codec *codec) 3133 { 3134 struct hdmi_spec *spec = codec->spec; 3135 3136 hdmi_array_free(spec); 3137 kfree(spec); 3138 } 3139 3140 /* 3141 * Nvidia specific implementations 3142 */ 3143 3144 #define Nv_VERB_SET_Channel_Allocation 0xF79 3145 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A 3146 #define Nv_VERB_SET_Audio_Protection_On 0xF98 3147 #define Nv_VERB_SET_Audio_Protection_Off 0xF99 3148 3149 #define nvhdmi_master_con_nid_7x 0x04 3150 #define nvhdmi_master_pin_nid_7x 0x05 3151 3152 static const hda_nid_t nvhdmi_con_nids_7x[4] = { 3153 /*front, rear, clfe, rear_surr */ 3154 0x6, 0x8, 0xa, 0xc, 3155 }; 3156 3157 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { 3158 /* set audio protect on */ 3159 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3160 /* enable digital output on pin widget */ 3161 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3162 {} /* terminator */ 3163 }; 3164 3165 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { 3166 /* set audio protect on */ 3167 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3168 /* enable digital output on pin widget */ 3169 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3170 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3171 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3172 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3173 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3174 {} /* terminator */ 3175 }; 3176 3177 #ifdef LIMITED_RATE_FMT_SUPPORT 3178 /* support only the safe format and rate */ 3179 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 3180 #define SUPPORTED_MAXBPS 16 3181 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE 3182 #else 3183 /* support all rates and formats */ 3184 #define SUPPORTED_RATES \ 3185 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ 3186 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ 3187 SNDRV_PCM_RATE_192000) 3188 #define SUPPORTED_MAXBPS 24 3189 #define SUPPORTED_FORMATS \ 3190 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 3191 #endif 3192 3193 static int nvhdmi_7x_init_2ch(struct hda_codec *codec) 3194 { 3195 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); 3196 return 0; 3197 } 3198 3199 static int nvhdmi_7x_init_8ch(struct hda_codec *codec) 3200 { 3201 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); 3202 return 0; 3203 } 3204 3205 static const unsigned int channels_2_6_8[] = { 3206 2, 6, 8 3207 }; 3208 3209 static const unsigned int channels_2_8[] = { 3210 2, 8 3211 }; 3212 3213 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { 3214 .count = ARRAY_SIZE(channels_2_6_8), 3215 .list = channels_2_6_8, 3216 .mask = 0, 3217 }; 3218 3219 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { 3220 .count = ARRAY_SIZE(channels_2_8), 3221 .list = channels_2_8, 3222 .mask = 0, 3223 }; 3224 3225 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, 3226 struct hda_codec *codec, 3227 struct snd_pcm_substream *substream) 3228 { 3229 struct hdmi_spec *spec = codec->spec; 3230 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; 3231 3232 switch (codec->preset->vendor_id) { 3233 case 0x10de0002: 3234 case 0x10de0003: 3235 case 0x10de0005: 3236 case 0x10de0006: 3237 hw_constraints_channels = &hw_constraints_2_8_channels; 3238 break; 3239 case 0x10de0007: 3240 hw_constraints_channels = &hw_constraints_2_6_8_channels; 3241 break; 3242 default: 3243 break; 3244 } 3245 3246 if (hw_constraints_channels != NULL) { 3247 snd_pcm_hw_constraint_list(substream->runtime, 0, 3248 SNDRV_PCM_HW_PARAM_CHANNELS, 3249 hw_constraints_channels); 3250 } else { 3251 snd_pcm_hw_constraint_step(substream->runtime, 0, 3252 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 3253 } 3254 3255 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3256 } 3257 3258 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, 3259 struct hda_codec *codec, 3260 struct snd_pcm_substream *substream) 3261 { 3262 struct hdmi_spec *spec = codec->spec; 3263 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3264 } 3265 3266 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3267 struct hda_codec *codec, 3268 unsigned int stream_tag, 3269 unsigned int format, 3270 struct snd_pcm_substream *substream) 3271 { 3272 struct hdmi_spec *spec = codec->spec; 3273 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3274 stream_tag, format, substream); 3275 } 3276 3277 static const struct hda_pcm_stream simple_pcm_playback = { 3278 .substreams = 1, 3279 .channels_min = 2, 3280 .channels_max = 2, 3281 .ops = { 3282 .open = simple_playback_pcm_open, 3283 .close = simple_playback_pcm_close, 3284 .prepare = simple_playback_pcm_prepare 3285 }, 3286 }; 3287 3288 static const struct hda_codec_ops simple_hdmi_patch_ops = { 3289 .build_controls = simple_playback_build_controls, 3290 .build_pcms = simple_playback_build_pcms, 3291 .init = simple_playback_init, 3292 .free = simple_playback_free, 3293 .unsol_event = simple_hdmi_unsol_event, 3294 }; 3295 3296 static int patch_simple_hdmi(struct hda_codec *codec, 3297 hda_nid_t cvt_nid, hda_nid_t pin_nid) 3298 { 3299 struct hdmi_spec *spec; 3300 struct hdmi_spec_per_cvt *per_cvt; 3301 struct hdmi_spec_per_pin *per_pin; 3302 3303 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 3304 if (!spec) 3305 return -ENOMEM; 3306 3307 spec->codec = codec; 3308 codec->spec = spec; 3309 hdmi_array_init(spec, 1); 3310 3311 spec->multiout.num_dacs = 0; /* no analog */ 3312 spec->multiout.max_channels = 2; 3313 spec->multiout.dig_out_nid = cvt_nid; 3314 spec->num_cvts = 1; 3315 spec->num_pins = 1; 3316 per_pin = snd_array_new(&spec->pins); 3317 per_cvt = snd_array_new(&spec->cvts); 3318 if (!per_pin || !per_cvt) { 3319 simple_playback_free(codec); 3320 return -ENOMEM; 3321 } 3322 per_cvt->cvt_nid = cvt_nid; 3323 per_pin->pin_nid = pin_nid; 3324 spec->pcm_playback = simple_pcm_playback; 3325 3326 codec->patch_ops = simple_hdmi_patch_ops; 3327 3328 return 0; 3329 } 3330 3331 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, 3332 int channels) 3333 { 3334 unsigned int chanmask; 3335 int chan = channels ? (channels - 1) : 1; 3336 3337 switch (channels) { 3338 default: 3339 case 0: 3340 case 2: 3341 chanmask = 0x00; 3342 break; 3343 case 4: 3344 chanmask = 0x08; 3345 break; 3346 case 6: 3347 chanmask = 0x0b; 3348 break; 3349 case 8: 3350 chanmask = 0x13; 3351 break; 3352 } 3353 3354 /* Set the audio infoframe channel allocation and checksum fields. The 3355 * channel count is computed implicitly by the hardware. */ 3356 snd_hda_codec_write(codec, 0x1, 0, 3357 Nv_VERB_SET_Channel_Allocation, chanmask); 3358 3359 snd_hda_codec_write(codec, 0x1, 0, 3360 Nv_VERB_SET_Info_Frame_Checksum, 3361 (0x71 - chan - chanmask)); 3362 } 3363 3364 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, 3365 struct hda_codec *codec, 3366 struct snd_pcm_substream *substream) 3367 { 3368 struct hdmi_spec *spec = codec->spec; 3369 int i; 3370 3371 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 3372 0, AC_VERB_SET_CHANNEL_STREAMID, 0); 3373 for (i = 0; i < 4; i++) { 3374 /* set the stream id */ 3375 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3376 AC_VERB_SET_CHANNEL_STREAMID, 0); 3377 /* set the stream format */ 3378 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3379 AC_VERB_SET_STREAM_FORMAT, 0); 3380 } 3381 3382 /* The audio hardware sends a channel count of 0x7 (8ch) when all the 3383 * streams are disabled. */ 3384 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3385 3386 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3387 } 3388 3389 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, 3390 struct hda_codec *codec, 3391 unsigned int stream_tag, 3392 unsigned int format, 3393 struct snd_pcm_substream *substream) 3394 { 3395 int chs; 3396 unsigned int dataDCC2, channel_id; 3397 int i; 3398 struct hdmi_spec *spec = codec->spec; 3399 struct hda_spdif_out *spdif; 3400 struct hdmi_spec_per_cvt *per_cvt; 3401 3402 mutex_lock(&codec->spdif_mutex); 3403 per_cvt = get_cvt(spec, 0); 3404 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); 3405 3406 chs = substream->runtime->channels; 3407 3408 dataDCC2 = 0x2; 3409 3410 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ 3411 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) 3412 snd_hda_codec_write(codec, 3413 nvhdmi_master_con_nid_7x, 3414 0, 3415 AC_VERB_SET_DIGI_CONVERT_1, 3416 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3417 3418 /* set the stream id */ 3419 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3420 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); 3421 3422 /* set the stream format */ 3423 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3424 AC_VERB_SET_STREAM_FORMAT, format); 3425 3426 /* turn on again (if needed) */ 3427 /* enable and set the channel status audio/data flag */ 3428 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { 3429 snd_hda_codec_write(codec, 3430 nvhdmi_master_con_nid_7x, 3431 0, 3432 AC_VERB_SET_DIGI_CONVERT_1, 3433 spdif->ctls & 0xff); 3434 snd_hda_codec_write(codec, 3435 nvhdmi_master_con_nid_7x, 3436 0, 3437 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3438 } 3439 3440 for (i = 0; i < 4; i++) { 3441 if (chs == 2) 3442 channel_id = 0; 3443 else 3444 channel_id = i * 2; 3445 3446 /* turn off SPDIF once; 3447 *otherwise the IEC958 bits won't be updated 3448 */ 3449 if (codec->spdif_status_reset && 3450 (spdif->ctls & AC_DIG1_ENABLE)) 3451 snd_hda_codec_write(codec, 3452 nvhdmi_con_nids_7x[i], 3453 0, 3454 AC_VERB_SET_DIGI_CONVERT_1, 3455 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3456 /* set the stream id */ 3457 snd_hda_codec_write(codec, 3458 nvhdmi_con_nids_7x[i], 3459 0, 3460 AC_VERB_SET_CHANNEL_STREAMID, 3461 (stream_tag << 4) | channel_id); 3462 /* set the stream format */ 3463 snd_hda_codec_write(codec, 3464 nvhdmi_con_nids_7x[i], 3465 0, 3466 AC_VERB_SET_STREAM_FORMAT, 3467 format); 3468 /* turn on again (if needed) */ 3469 /* enable and set the channel status audio/data flag */ 3470 if (codec->spdif_status_reset && 3471 (spdif->ctls & AC_DIG1_ENABLE)) { 3472 snd_hda_codec_write(codec, 3473 nvhdmi_con_nids_7x[i], 3474 0, 3475 AC_VERB_SET_DIGI_CONVERT_1, 3476 spdif->ctls & 0xff); 3477 snd_hda_codec_write(codec, 3478 nvhdmi_con_nids_7x[i], 3479 0, 3480 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3481 } 3482 } 3483 3484 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); 3485 3486 mutex_unlock(&codec->spdif_mutex); 3487 return 0; 3488 } 3489 3490 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { 3491 .substreams = 1, 3492 .channels_min = 2, 3493 .channels_max = 8, 3494 .nid = nvhdmi_master_con_nid_7x, 3495 .rates = SUPPORTED_RATES, 3496 .maxbps = SUPPORTED_MAXBPS, 3497 .formats = SUPPORTED_FORMATS, 3498 .ops = { 3499 .open = simple_playback_pcm_open, 3500 .close = nvhdmi_8ch_7x_pcm_close, 3501 .prepare = nvhdmi_8ch_7x_pcm_prepare 3502 }, 3503 }; 3504 3505 static int patch_nvhdmi_2ch(struct hda_codec *codec) 3506 { 3507 struct hdmi_spec *spec; 3508 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, 3509 nvhdmi_master_pin_nid_7x); 3510 if (err < 0) 3511 return err; 3512 3513 codec->patch_ops.init = nvhdmi_7x_init_2ch; 3514 /* override the PCM rates, etc, as the codec doesn't give full list */ 3515 spec = codec->spec; 3516 spec->pcm_playback.rates = SUPPORTED_RATES; 3517 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; 3518 spec->pcm_playback.formats = SUPPORTED_FORMATS; 3519 return 0; 3520 } 3521 3522 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) 3523 { 3524 struct hdmi_spec *spec = codec->spec; 3525 int err = simple_playback_build_pcms(codec); 3526 if (!err) { 3527 struct hda_pcm *info = get_pcm_rec(spec, 0); 3528 info->own_chmap = true; 3529 } 3530 return err; 3531 } 3532 3533 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) 3534 { 3535 struct hdmi_spec *spec = codec->spec; 3536 struct hda_pcm *info; 3537 struct snd_pcm_chmap *chmap; 3538 int err; 3539 3540 err = simple_playback_build_controls(codec); 3541 if (err < 0) 3542 return err; 3543 3544 /* add channel maps */ 3545 info = get_pcm_rec(spec, 0); 3546 err = snd_pcm_add_chmap_ctls(info->pcm, 3547 SNDRV_PCM_STREAM_PLAYBACK, 3548 snd_pcm_alt_chmaps, 8, 0, &chmap); 3549 if (err < 0) 3550 return err; 3551 switch (codec->preset->vendor_id) { 3552 case 0x10de0002: 3553 case 0x10de0003: 3554 case 0x10de0005: 3555 case 0x10de0006: 3556 chmap->channel_mask = (1U << 2) | (1U << 8); 3557 break; 3558 case 0x10de0007: 3559 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); 3560 } 3561 return 0; 3562 } 3563 3564 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) 3565 { 3566 struct hdmi_spec *spec; 3567 int err = patch_nvhdmi_2ch(codec); 3568 if (err < 0) 3569 return err; 3570 spec = codec->spec; 3571 spec->multiout.max_channels = 8; 3572 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; 3573 codec->patch_ops.init = nvhdmi_7x_init_8ch; 3574 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; 3575 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; 3576 3577 /* Initialize the audio infoframe channel mask and checksum to something 3578 * valid */ 3579 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3580 3581 return 0; 3582 } 3583 3584 /* 3585 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: 3586 * - 0x10de0015 3587 * - 0x10de0040 3588 */ 3589 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, 3590 struct hdac_cea_channel_speaker_allocation *cap, int channels) 3591 { 3592 if (cap->ca_index == 0x00 && channels == 2) 3593 return SNDRV_CTL_TLVT_CHMAP_FIXED; 3594 3595 /* If the speaker allocation matches the channel count, it is OK. */ 3596 if (cap->channels != channels) 3597 return -1; 3598 3599 /* all channels are remappable freely */ 3600 return SNDRV_CTL_TLVT_CHMAP_VAR; 3601 } 3602 3603 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, 3604 int ca, int chs, unsigned char *map) 3605 { 3606 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) 3607 return -EINVAL; 3608 3609 return 0; 3610 } 3611 3612 /* map from pin NID to port; port is 0-based */ 3613 /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */ 3614 static int nvhdmi_pin2port(void *audio_ptr, int pin_nid) 3615 { 3616 return pin_nid - 4; 3617 } 3618 3619 /* reverse-map from port to pin NID: see above */ 3620 static int nvhdmi_port2pin(struct hda_codec *codec, int port) 3621 { 3622 return port + 4; 3623 } 3624 3625 static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = { 3626 .pin2port = nvhdmi_pin2port, 3627 .pin_eld_notify = generic_acomp_pin_eld_notify, 3628 .master_bind = generic_acomp_master_bind, 3629 .master_unbind = generic_acomp_master_unbind, 3630 }; 3631 3632 static int patch_nvhdmi(struct hda_codec *codec) 3633 { 3634 struct hdmi_spec *spec; 3635 int err; 3636 3637 err = alloc_generic_hdmi(codec); 3638 if (err < 0) 3639 return err; 3640 codec->dp_mst = true; 3641 3642 spec = codec->spec; 3643 spec->dyn_pcm_assign = true; 3644 3645 err = hdmi_parse_codec(codec); 3646 if (err < 0) { 3647 generic_spec_free(codec); 3648 return err; 3649 } 3650 3651 generic_hdmi_init_per_pins(codec); 3652 3653 spec->dyn_pin_out = true; 3654 3655 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3656 nvhdmi_chmap_cea_alloc_validate_get_type; 3657 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3658 3659 codec->link_down_at_suspend = 1; 3660 3661 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin); 3662 3663 return 0; 3664 } 3665 3666 static int patch_nvhdmi_legacy(struct hda_codec *codec) 3667 { 3668 struct hdmi_spec *spec; 3669 int err; 3670 3671 err = patch_generic_hdmi(codec); 3672 if (err) 3673 return err; 3674 3675 spec = codec->spec; 3676 spec->dyn_pin_out = true; 3677 3678 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3679 nvhdmi_chmap_cea_alloc_validate_get_type; 3680 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3681 3682 codec->link_down_at_suspend = 1; 3683 3684 return 0; 3685 } 3686 3687 /* 3688 * The HDA codec on NVIDIA Tegra contains two scratch registers that are 3689 * accessed using vendor-defined verbs. These registers can be used for 3690 * interoperability between the HDA and HDMI drivers. 3691 */ 3692 3693 /* Audio Function Group node */ 3694 #define NVIDIA_AFG_NID 0x01 3695 3696 /* 3697 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio 3698 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to 3699 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This 3700 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an 3701 * additional bit (at position 30) to signal the validity of the format. 3702 * 3703 * | 31 | 30 | 29 16 | 15 0 | 3704 * +---------+-------+--------+--------+ 3705 * | TRIGGER | VALID | UNUSED | FORMAT | 3706 * +-----------------------------------| 3707 * 3708 * Note that for the trigger bit to take effect it needs to change value 3709 * (i.e. it needs to be toggled). 3710 */ 3711 #define NVIDIA_GET_SCRATCH0 0xfa6 3712 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 3713 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 3714 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 3715 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa 3716 #define NVIDIA_SCRATCH_TRIGGER (1 << 7) 3717 #define NVIDIA_SCRATCH_VALID (1 << 6) 3718 3719 #define NVIDIA_GET_SCRATCH1 0xfab 3720 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac 3721 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad 3722 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae 3723 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf 3724 3725 /* 3726 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, 3727 * the format is invalidated so that the HDMI codec can be disabled. 3728 */ 3729 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format) 3730 { 3731 unsigned int value; 3732 3733 /* bits [31:30] contain the trigger and valid bits */ 3734 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0, 3735 NVIDIA_GET_SCRATCH0, 0); 3736 value = (value >> 24) & 0xff; 3737 3738 /* bits [15:0] are used to store the HDA format */ 3739 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3740 NVIDIA_SET_SCRATCH0_BYTE0, 3741 (format >> 0) & 0xff); 3742 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3743 NVIDIA_SET_SCRATCH0_BYTE1, 3744 (format >> 8) & 0xff); 3745 3746 /* bits [16:24] are unused */ 3747 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3748 NVIDIA_SET_SCRATCH0_BYTE2, 0); 3749 3750 /* 3751 * Bit 30 signals that the data is valid and hence that HDMI audio can 3752 * be enabled. 3753 */ 3754 if (format == 0) 3755 value &= ~NVIDIA_SCRATCH_VALID; 3756 else 3757 value |= NVIDIA_SCRATCH_VALID; 3758 3759 /* 3760 * Whenever the trigger bit is toggled, an interrupt is raised in the 3761 * HDMI codec. The HDMI driver will use that as trigger to update its 3762 * configuration. 3763 */ 3764 value ^= NVIDIA_SCRATCH_TRIGGER; 3765 3766 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3767 NVIDIA_SET_SCRATCH0_BYTE3, value); 3768 } 3769 3770 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, 3771 struct hda_codec *codec, 3772 unsigned int stream_tag, 3773 unsigned int format, 3774 struct snd_pcm_substream *substream) 3775 { 3776 int err; 3777 3778 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, 3779 format, substream); 3780 if (err < 0) 3781 return err; 3782 3783 /* notify the HDMI codec of the format change */ 3784 tegra_hdmi_set_format(codec, format); 3785 3786 return 0; 3787 } 3788 3789 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, 3790 struct hda_codec *codec, 3791 struct snd_pcm_substream *substream) 3792 { 3793 /* invalidate the format in the HDMI codec */ 3794 tegra_hdmi_set_format(codec, 0); 3795 3796 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); 3797 } 3798 3799 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) 3800 { 3801 struct hdmi_spec *spec = codec->spec; 3802 unsigned int i; 3803 3804 for (i = 0; i < spec->num_pins; i++) { 3805 struct hda_pcm *pcm = get_pcm_rec(spec, i); 3806 3807 if (pcm->pcm_type == type) 3808 return pcm; 3809 } 3810 3811 return NULL; 3812 } 3813 3814 static int tegra_hdmi_build_pcms(struct hda_codec *codec) 3815 { 3816 struct hda_pcm_stream *stream; 3817 struct hda_pcm *pcm; 3818 int err; 3819 3820 err = generic_hdmi_build_pcms(codec); 3821 if (err < 0) 3822 return err; 3823 3824 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); 3825 if (!pcm) 3826 return -ENODEV; 3827 3828 /* 3829 * Override ->prepare() and ->cleanup() operations to notify the HDMI 3830 * codec about format changes. 3831 */ 3832 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3833 stream->ops.prepare = tegra_hdmi_pcm_prepare; 3834 stream->ops.cleanup = tegra_hdmi_pcm_cleanup; 3835 3836 return 0; 3837 } 3838 3839 static int patch_tegra_hdmi(struct hda_codec *codec) 3840 { 3841 struct hdmi_spec *spec; 3842 int err; 3843 3844 err = patch_generic_hdmi(codec); 3845 if (err) 3846 return err; 3847 3848 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; 3849 spec = codec->spec; 3850 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3851 nvhdmi_chmap_cea_alloc_validate_get_type; 3852 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3853 3854 return 0; 3855 } 3856 3857 /* 3858 * ATI/AMD-specific implementations 3859 */ 3860 3861 #define is_amdhdmi_rev3_or_later(codec) \ 3862 ((codec)->core.vendor_id == 0x1002aa01 && \ 3863 ((codec)->core.revision_id & 0xff00) >= 0x0300) 3864 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) 3865 3866 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ 3867 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 3868 #define ATI_VERB_SET_DOWNMIX_INFO 0x772 3869 #define ATI_VERB_SET_MULTICHANNEL_01 0x777 3870 #define ATI_VERB_SET_MULTICHANNEL_23 0x778 3871 #define ATI_VERB_SET_MULTICHANNEL_45 0x779 3872 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a 3873 #define ATI_VERB_SET_HBR_CONTROL 0x77c 3874 #define ATI_VERB_SET_MULTICHANNEL_1 0x785 3875 #define ATI_VERB_SET_MULTICHANNEL_3 0x786 3876 #define ATI_VERB_SET_MULTICHANNEL_5 0x787 3877 #define ATI_VERB_SET_MULTICHANNEL_7 0x788 3878 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 3879 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 3880 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 3881 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 3882 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 3883 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 3884 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a 3885 #define ATI_VERB_GET_HBR_CONTROL 0xf7c 3886 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 3887 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 3888 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 3889 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 3890 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 3891 3892 /* AMD specific HDA cvt verbs */ 3893 #define ATI_VERB_SET_RAMP_RATE 0x770 3894 #define ATI_VERB_GET_RAMP_RATE 0xf70 3895 3896 #define ATI_OUT_ENABLE 0x1 3897 3898 #define ATI_MULTICHANNEL_MODE_PAIRED 0 3899 #define ATI_MULTICHANNEL_MODE_SINGLE 1 3900 3901 #define ATI_HBR_CAPABLE 0x01 3902 #define ATI_HBR_ENABLE 0x10 3903 3904 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 3905 int dev_id, unsigned char *buf, int *eld_size) 3906 { 3907 WARN_ON(dev_id != 0); 3908 /* call hda_eld.c ATI/AMD-specific function */ 3909 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, 3910 is_amdhdmi_rev3_or_later(codec)); 3911 } 3912 3913 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, 3914 hda_nid_t pin_nid, int dev_id, int ca, 3915 int active_channels, int conn_type) 3916 { 3917 WARN_ON(dev_id != 0); 3918 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); 3919 } 3920 3921 static int atihdmi_paired_swap_fc_lfe(int pos) 3922 { 3923 /* 3924 * ATI/AMD have automatic FC/LFE swap built-in 3925 * when in pairwise mapping mode. 3926 */ 3927 3928 switch (pos) { 3929 /* see channel_allocations[].speakers[] */ 3930 case 2: return 3; 3931 case 3: return 2; 3932 default: break; 3933 } 3934 3935 return pos; 3936 } 3937 3938 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, 3939 int ca, int chs, unsigned char *map) 3940 { 3941 struct hdac_cea_channel_speaker_allocation *cap; 3942 int i, j; 3943 3944 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ 3945 3946 cap = snd_hdac_get_ch_alloc_from_ca(ca); 3947 for (i = 0; i < chs; ++i) { 3948 int mask = snd_hdac_chmap_to_spk_mask(map[i]); 3949 bool ok = false; 3950 bool companion_ok = false; 3951 3952 if (!mask) 3953 continue; 3954 3955 for (j = 0 + i % 2; j < 8; j += 2) { 3956 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); 3957 if (cap->speakers[chan_idx] == mask) { 3958 /* channel is in a supported position */ 3959 ok = true; 3960 3961 if (i % 2 == 0 && i + 1 < chs) { 3962 /* even channel, check the odd companion */ 3963 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); 3964 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); 3965 int comp_mask_act = cap->speakers[comp_chan_idx]; 3966 3967 if (comp_mask_req == comp_mask_act) 3968 companion_ok = true; 3969 else 3970 return -EINVAL; 3971 } 3972 break; 3973 } 3974 } 3975 3976 if (!ok) 3977 return -EINVAL; 3978 3979 if (companion_ok) 3980 i++; /* companion channel already checked */ 3981 } 3982 3983 return 0; 3984 } 3985 3986 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, 3987 hda_nid_t pin_nid, int hdmi_slot, int stream_channel) 3988 { 3989 struct hda_codec *codec = hdac_to_hda_codec(hdac); 3990 int verb; 3991 int ati_channel_setup = 0; 3992 3993 if (hdmi_slot > 7) 3994 return -EINVAL; 3995 3996 if (!has_amd_full_remap_support(codec)) { 3997 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); 3998 3999 /* In case this is an odd slot but without stream channel, do not 4000 * disable the slot since the corresponding even slot could have a 4001 * channel. In case neither have a channel, the slot pair will be 4002 * disabled when this function is called for the even slot. */ 4003 if (hdmi_slot % 2 != 0 && stream_channel == 0xf) 4004 return 0; 4005 4006 hdmi_slot -= hdmi_slot % 2; 4007 4008 if (stream_channel != 0xf) 4009 stream_channel -= stream_channel % 2; 4010 } 4011 4012 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; 4013 4014 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ 4015 4016 if (stream_channel != 0xf) 4017 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; 4018 4019 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); 4020 } 4021 4022 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, 4023 hda_nid_t pin_nid, int asp_slot) 4024 { 4025 struct hda_codec *codec = hdac_to_hda_codec(hdac); 4026 bool was_odd = false; 4027 int ati_asp_slot = asp_slot; 4028 int verb; 4029 int ati_channel_setup; 4030 4031 if (asp_slot > 7) 4032 return -EINVAL; 4033 4034 if (!has_amd_full_remap_support(codec)) { 4035 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); 4036 if (ati_asp_slot % 2 != 0) { 4037 ati_asp_slot -= 1; 4038 was_odd = true; 4039 } 4040 } 4041 4042 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; 4043 4044 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); 4045 4046 if (!(ati_channel_setup & ATI_OUT_ENABLE)) 4047 return 0xf; 4048 4049 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; 4050 } 4051 4052 static int atihdmi_paired_chmap_cea_alloc_validate_get_type( 4053 struct hdac_chmap *chmap, 4054 struct hdac_cea_channel_speaker_allocation *cap, 4055 int channels) 4056 { 4057 int c; 4058 4059 /* 4060 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so 4061 * we need to take that into account (a single channel may take 2 4062 * channel slots if we need to carry a silent channel next to it). 4063 * On Rev3+ AMD codecs this function is not used. 4064 */ 4065 int chanpairs = 0; 4066 4067 /* We only produce even-numbered channel count TLVs */ 4068 if ((channels % 2) != 0) 4069 return -1; 4070 4071 for (c = 0; c < 7; c += 2) { 4072 if (cap->speakers[c] || cap->speakers[c+1]) 4073 chanpairs++; 4074 } 4075 4076 if (chanpairs * 2 != channels) 4077 return -1; 4078 4079 return SNDRV_CTL_TLVT_CHMAP_PAIRED; 4080 } 4081 4082 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, 4083 struct hdac_cea_channel_speaker_allocation *cap, 4084 unsigned int *chmap, int channels) 4085 { 4086 /* produce paired maps for pre-rev3 ATI/AMD codecs */ 4087 int count = 0; 4088 int c; 4089 4090 for (c = 7; c >= 0; c--) { 4091 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); 4092 int spk = cap->speakers[chan]; 4093 if (!spk) { 4094 /* add N/A channel if the companion channel is occupied */ 4095 if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) 4096 chmap[count++] = SNDRV_CHMAP_NA; 4097 4098 continue; 4099 } 4100 4101 chmap[count++] = snd_hdac_spk_to_chmap(spk); 4102 } 4103 4104 WARN_ON(count != channels); 4105 } 4106 4107 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 4108 int dev_id, bool hbr) 4109 { 4110 int hbr_ctl, hbr_ctl_new; 4111 4112 WARN_ON(dev_id != 0); 4113 4114 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); 4115 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { 4116 if (hbr) 4117 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; 4118 else 4119 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; 4120 4121 codec_dbg(codec, 4122 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", 4123 pin_nid, 4124 hbr_ctl == hbr_ctl_new ? "" : "new-", 4125 hbr_ctl_new); 4126 4127 if (hbr_ctl != hbr_ctl_new) 4128 snd_hda_codec_write(codec, pin_nid, 0, 4129 ATI_VERB_SET_HBR_CONTROL, 4130 hbr_ctl_new); 4131 4132 } else if (hbr) 4133 return -EINVAL; 4134 4135 return 0; 4136 } 4137 4138 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 4139 hda_nid_t pin_nid, int dev_id, 4140 u32 stream_tag, int format) 4141 { 4142 if (is_amdhdmi_rev3_or_later(codec)) { 4143 int ramp_rate = 180; /* default as per AMD spec */ 4144 /* disable ramp-up/down for non-pcm as per AMD spec */ 4145 if (format & AC_FMT_TYPE_NON_PCM) 4146 ramp_rate = 0; 4147 4148 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); 4149 } 4150 4151 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 4152 stream_tag, format); 4153 } 4154 4155 4156 static int atihdmi_init(struct hda_codec *codec) 4157 { 4158 struct hdmi_spec *spec = codec->spec; 4159 int pin_idx, err; 4160 4161 err = generic_hdmi_init(codec); 4162 4163 if (err) 4164 return err; 4165 4166 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 4167 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 4168 4169 /* make sure downmix information in infoframe is zero */ 4170 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); 4171 4172 /* enable channel-wise remap mode if supported */ 4173 if (has_amd_full_remap_support(codec)) 4174 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 4175 ATI_VERB_SET_MULTICHANNEL_MODE, 4176 ATI_MULTICHANNEL_MODE_SINGLE); 4177 } 4178 codec->auto_runtime_pm = 1; 4179 4180 return 0; 4181 } 4182 4183 /* map from pin NID to port; port is 0-based */ 4184 /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */ 4185 static int atihdmi_pin2port(void *audio_ptr, int pin_nid) 4186 { 4187 return pin_nid / 2 - 1; 4188 } 4189 4190 /* reverse-map from port to pin NID: see above */ 4191 static int atihdmi_port2pin(struct hda_codec *codec, int port) 4192 { 4193 return port * 2 + 3; 4194 } 4195 4196 static const struct drm_audio_component_audio_ops atihdmi_audio_ops = { 4197 .pin2port = atihdmi_pin2port, 4198 .pin_eld_notify = generic_acomp_pin_eld_notify, 4199 .master_bind = generic_acomp_master_bind, 4200 .master_unbind = generic_acomp_master_unbind, 4201 }; 4202 4203 static int patch_atihdmi(struct hda_codec *codec) 4204 { 4205 struct hdmi_spec *spec; 4206 struct hdmi_spec_per_cvt *per_cvt; 4207 int err, cvt_idx; 4208 4209 err = patch_generic_hdmi(codec); 4210 4211 if (err) 4212 return err; 4213 4214 codec->patch_ops.init = atihdmi_init; 4215 4216 spec = codec->spec; 4217 4218 spec->ops.pin_get_eld = atihdmi_pin_get_eld; 4219 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; 4220 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; 4221 spec->ops.setup_stream = atihdmi_setup_stream; 4222 4223 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; 4224 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; 4225 4226 if (!has_amd_full_remap_support(codec)) { 4227 /* override to ATI/AMD-specific versions with pairwise mapping */ 4228 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4229 atihdmi_paired_chmap_cea_alloc_validate_get_type; 4230 spec->chmap.ops.cea_alloc_to_tlv_chmap = 4231 atihdmi_paired_cea_alloc_to_tlv_chmap; 4232 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; 4233 } 4234 4235 /* ATI/AMD converters do not advertise all of their capabilities */ 4236 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 4237 per_cvt = get_cvt(spec, cvt_idx); 4238 per_cvt->channels_max = max(per_cvt->channels_max, 8u); 4239 per_cvt->rates |= SUPPORTED_RATES; 4240 per_cvt->formats |= SUPPORTED_FORMATS; 4241 per_cvt->maxbps = max(per_cvt->maxbps, 24u); 4242 } 4243 4244 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); 4245 4246 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing 4247 * the link-down as is. Tell the core to allow it. 4248 */ 4249 codec->link_down_at_suspend = 1; 4250 4251 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin); 4252 4253 return 0; 4254 } 4255 4256 /* VIA HDMI Implementation */ 4257 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ 4258 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ 4259 4260 static int patch_via_hdmi(struct hda_codec *codec) 4261 { 4262 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); 4263 } 4264 4265 /* 4266 * patch entries 4267 */ 4268 static const struct hda_device_id snd_hda_id_hdmi[] = { 4269 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), 4270 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), 4271 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), 4272 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), 4273 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), 4274 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), 4275 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), 4276 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch), 4277 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4278 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4279 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x), 4280 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4281 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4282 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), 4283 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy), 4284 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy), 4285 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy), 4286 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy), 4287 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy), 4288 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy), 4289 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy), 4290 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy), 4291 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy), 4292 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy), 4293 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy), 4294 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy), 4295 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy), 4296 /* 17 is known to be absent */ 4297 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy), 4298 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy), 4299 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy), 4300 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy), 4301 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy), 4302 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), 4303 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), 4304 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), 4305 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), 4306 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi), 4307 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi), 4308 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), 4309 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), 4310 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), 4311 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), 4312 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), 4313 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), 4314 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), 4315 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi), 4316 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi), 4317 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), 4318 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi), 4319 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), 4320 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi), 4321 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi), 4322 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), 4323 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), 4324 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), 4325 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), 4326 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi), 4327 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi), 4328 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi), 4329 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi), 4330 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi), 4331 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), 4332 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi), 4333 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), 4334 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi), 4335 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), 4336 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), 4337 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi), 4338 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi), 4339 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi), 4340 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi), 4341 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi), 4342 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi), 4343 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi), 4344 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi), 4345 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), 4346 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), 4347 HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi), 4348 HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi), 4349 HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi), 4350 HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi), 4351 HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi), 4352 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), 4353 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), 4354 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), 4355 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), 4356 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), 4357 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), 4358 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4359 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), 4360 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), 4361 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), 4362 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), 4363 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4364 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), 4365 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), 4366 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), 4367 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), 4368 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), 4369 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), 4370 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), 4371 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), 4372 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), 4373 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi), 4374 HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi), 4375 HDA_CODEC_ENTRY(0x80862814, "DG1 HDMI", patch_i915_tgl_hdmi), 4376 HDA_CODEC_ENTRY(0x80862815, "Alderlake HDMI", patch_i915_tgl_hdmi), 4377 HDA_CODEC_ENTRY(0x8086281c, "Alderlake-P HDMI", patch_i915_tgl_hdmi), 4378 HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI", patch_i915_tgl_hdmi), 4379 HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi), 4380 HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi), 4381 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), 4382 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), 4383 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), 4384 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), 4385 /* special ID for generic HDMI */ 4386 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), 4387 {} /* terminator */ 4388 }; 4389 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); 4390 4391 MODULE_LICENSE("GPL"); 4392 MODULE_DESCRIPTION("HDMI HD-audio codec"); 4393 MODULE_ALIAS("snd-hda-codec-intelhdmi"); 4394 MODULE_ALIAS("snd-hda-codec-nvhdmi"); 4395 MODULE_ALIAS("snd-hda-codec-atihdmi"); 4396 4397 static struct hda_codec_driver hdmi_driver = { 4398 .id = snd_hda_id_hdmi, 4399 }; 4400 4401 module_hda_codec_driver(hdmi_driver); 4402