1 /* 2 * 3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs 4 * 5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. 6 * Copyright (c) 2006 ATI Technologies Inc. 7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved. 8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com> 9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> 10 * 11 * Authors: 12 * Wu Fengguang <wfg@linux.intel.com> 13 * 14 * Maintained by: 15 * Wu Fengguang <wfg@linux.intel.com> 16 * 17 * This program is free software; you can redistribute it and/or modify it 18 * under the terms of the GNU General Public License as published by the Free 19 * Software Foundation; either version 2 of the License, or (at your option) 20 * any later version. 21 * 22 * This program is distributed in the hope that it will be useful, but 23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 25 * for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software Foundation, 29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 30 */ 31 32 #include <linux/init.h> 33 #include <linux/delay.h> 34 #include <linux/slab.h> 35 #include <linux/module.h> 36 #include <linux/pm_runtime.h> 37 #include <sound/core.h> 38 #include <sound/jack.h> 39 #include <sound/asoundef.h> 40 #include <sound/tlv.h> 41 #include <sound/hdaudio.h> 42 #include <sound/hda_i915.h> 43 #include <sound/hda_chmap.h> 44 #include <sound/hda_codec.h> 45 #include "hda_local.h" 46 #include "hda_jack.h" 47 48 static bool static_hdmi_pcm; 49 module_param(static_hdmi_pcm, bool, 0644); 50 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); 51 52 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807) 53 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808) 54 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809) 55 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a) 56 #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b) 57 #define is_geminilake(codec) (((codec)->core.vendor_id == 0x8086280d) || \ 58 ((codec)->core.vendor_id == 0x80862800)) 59 #define is_cannonlake(codec) ((codec)->core.vendor_id == 0x8086280c) 60 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \ 61 || is_skylake(codec) || is_broxton(codec) \ 62 || is_kabylake(codec)) || is_geminilake(codec) \ 63 || is_cannonlake(codec) 64 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882) 65 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883) 66 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec)) 67 68 struct hdmi_spec_per_cvt { 69 hda_nid_t cvt_nid; 70 int assigned; 71 unsigned int channels_min; 72 unsigned int channels_max; 73 u32 rates; 74 u64 formats; 75 unsigned int maxbps; 76 }; 77 78 /* max. connections to a widget */ 79 #define HDA_MAX_CONNECTIONS 32 80 81 struct hdmi_spec_per_pin { 82 hda_nid_t pin_nid; 83 int dev_id; 84 /* pin idx, different device entries on the same pin use the same idx */ 85 int pin_nid_idx; 86 int num_mux_nids; 87 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; 88 int mux_idx; 89 hda_nid_t cvt_nid; 90 91 struct hda_codec *codec; 92 struct hdmi_eld sink_eld; 93 struct mutex lock; 94 struct delayed_work work; 95 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ 96 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ 97 int repoll_count; 98 bool setup; /* the stream has been set up by prepare callback */ 99 int channels; /* current number of channels */ 100 bool non_pcm; 101 bool chmap_set; /* channel-map override by ALSA API? */ 102 unsigned char chmap[8]; /* ALSA API channel-map */ 103 #ifdef CONFIG_SND_PROC_FS 104 struct snd_info_entry *proc_entry; 105 #endif 106 }; 107 108 /* operations used by generic code that can be overridden by patches */ 109 struct hdmi_ops { 110 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, 111 unsigned char *buf, int *eld_size); 112 113 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, 114 int ca, int active_channels, int conn_type); 115 116 /* enable/disable HBR (HD passthrough) */ 117 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr); 118 119 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, 120 hda_nid_t pin_nid, u32 stream_tag, int format); 121 122 void (*pin_cvt_fixup)(struct hda_codec *codec, 123 struct hdmi_spec_per_pin *per_pin, 124 hda_nid_t cvt_nid); 125 }; 126 127 struct hdmi_pcm { 128 struct hda_pcm *pcm; 129 struct snd_jack *jack; 130 struct snd_kcontrol *eld_ctl; 131 }; 132 133 struct hdmi_spec { 134 int num_cvts; 135 struct snd_array cvts; /* struct hdmi_spec_per_cvt */ 136 hda_nid_t cvt_nids[4]; /* only for haswell fix */ 137 138 /* 139 * num_pins is the number of virtual pins 140 * for example, there are 3 pins, and each pin 141 * has 4 device entries, then the num_pins is 12 142 */ 143 int num_pins; 144 /* 145 * num_nids is the number of real pins 146 * In the above example, num_nids is 3 147 */ 148 int num_nids; 149 /* 150 * dev_num is the number of device entries 151 * on each pin. 152 * In the above example, dev_num is 4 153 */ 154 int dev_num; 155 struct snd_array pins; /* struct hdmi_spec_per_pin */ 156 struct hdmi_pcm pcm_rec[16]; 157 struct mutex pcm_lock; 158 /* pcm_bitmap means which pcms have been assigned to pins*/ 159 unsigned long pcm_bitmap; 160 int pcm_used; /* counter of pcm_rec[] */ 161 /* bitmap shows whether the pcm is opened in user space 162 * bit 0 means the first playback PCM (PCM3); 163 * bit 1 means the second playback PCM, and so on. 164 */ 165 unsigned long pcm_in_use; 166 167 struct hdmi_eld temp_eld; 168 struct hdmi_ops ops; 169 170 bool dyn_pin_out; 171 bool dyn_pcm_assign; 172 /* 173 * Non-generic VIA/NVIDIA specific 174 */ 175 struct hda_multi_out multiout; 176 struct hda_pcm_stream pcm_playback; 177 178 /* i915/powerwell (Haswell+/Valleyview+) specific */ 179 bool use_acomp_notifier; /* use i915 eld_notify callback for hotplug */ 180 struct drm_audio_component_audio_ops drm_audio_ops; 181 182 struct hdac_chmap chmap; 183 hda_nid_t vendor_nid; 184 }; 185 186 #ifdef CONFIG_SND_HDA_COMPONENT 187 static inline bool codec_has_acomp(struct hda_codec *codec) 188 { 189 struct hdmi_spec *spec = codec->spec; 190 return spec->use_acomp_notifier; 191 } 192 #else 193 #define codec_has_acomp(codec) false 194 #endif 195 196 struct hdmi_audio_infoframe { 197 u8 type; /* 0x84 */ 198 u8 ver; /* 0x01 */ 199 u8 len; /* 0x0a */ 200 201 u8 checksum; 202 203 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ 204 u8 SS01_SF24; 205 u8 CXT04; 206 u8 CA; 207 u8 LFEPBL01_LSV36_DM_INH7; 208 }; 209 210 struct dp_audio_infoframe { 211 u8 type; /* 0x84 */ 212 u8 len; /* 0x1b */ 213 u8 ver; /* 0x11 << 2 */ 214 215 u8 CC02_CT47; /* match with HDMI infoframe from this on */ 216 u8 SS01_SF24; 217 u8 CXT04; 218 u8 CA; 219 u8 LFEPBL01_LSV36_DM_INH7; 220 }; 221 222 union audio_infoframe { 223 struct hdmi_audio_infoframe hdmi; 224 struct dp_audio_infoframe dp; 225 u8 bytes[0]; 226 }; 227 228 /* 229 * HDMI routines 230 */ 231 232 #define get_pin(spec, idx) \ 233 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) 234 #define get_cvt(spec, idx) \ 235 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) 236 /* obtain hdmi_pcm object assigned to idx */ 237 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) 238 /* obtain hda_pcm object assigned to idx */ 239 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) 240 241 static int pin_id_to_pin_index(struct hda_codec *codec, 242 hda_nid_t pin_nid, int dev_id) 243 { 244 struct hdmi_spec *spec = codec->spec; 245 int pin_idx; 246 struct hdmi_spec_per_pin *per_pin; 247 248 /* 249 * (dev_id == -1) means it is NON-MST pin 250 * return the first virtual pin on this port 251 */ 252 if (dev_id == -1) 253 dev_id = 0; 254 255 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 256 per_pin = get_pin(spec, pin_idx); 257 if ((per_pin->pin_nid == pin_nid) && 258 (per_pin->dev_id == dev_id)) 259 return pin_idx; 260 } 261 262 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid); 263 return -EINVAL; 264 } 265 266 static int hinfo_to_pcm_index(struct hda_codec *codec, 267 struct hda_pcm_stream *hinfo) 268 { 269 struct hdmi_spec *spec = codec->spec; 270 int pcm_idx; 271 272 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) 273 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) 274 return pcm_idx; 275 276 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo); 277 return -EINVAL; 278 } 279 280 static int hinfo_to_pin_index(struct hda_codec *codec, 281 struct hda_pcm_stream *hinfo) 282 { 283 struct hdmi_spec *spec = codec->spec; 284 struct hdmi_spec_per_pin *per_pin; 285 int pin_idx; 286 287 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 288 per_pin = get_pin(spec, pin_idx); 289 if (per_pin->pcm && 290 per_pin->pcm->pcm->stream == hinfo) 291 return pin_idx; 292 } 293 294 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo); 295 return -EINVAL; 296 } 297 298 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, 299 int pcm_idx) 300 { 301 int i; 302 struct hdmi_spec_per_pin *per_pin; 303 304 for (i = 0; i < spec->num_pins; i++) { 305 per_pin = get_pin(spec, i); 306 if (per_pin->pcm_idx == pcm_idx) 307 return per_pin; 308 } 309 return NULL; 310 } 311 312 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) 313 { 314 struct hdmi_spec *spec = codec->spec; 315 int cvt_idx; 316 317 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) 318 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) 319 return cvt_idx; 320 321 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid); 322 return -EINVAL; 323 } 324 325 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, 326 struct snd_ctl_elem_info *uinfo) 327 { 328 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 329 struct hdmi_spec *spec = codec->spec; 330 struct hdmi_spec_per_pin *per_pin; 331 struct hdmi_eld *eld; 332 int pcm_idx; 333 334 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 335 336 pcm_idx = kcontrol->private_value; 337 mutex_lock(&spec->pcm_lock); 338 per_pin = pcm_idx_to_pin(spec, pcm_idx); 339 if (!per_pin) { 340 /* no pin is bound to the pcm */ 341 uinfo->count = 0; 342 goto unlock; 343 } 344 eld = &per_pin->sink_eld; 345 uinfo->count = eld->eld_valid ? eld->eld_size : 0; 346 347 unlock: 348 mutex_unlock(&spec->pcm_lock); 349 return 0; 350 } 351 352 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, 353 struct snd_ctl_elem_value *ucontrol) 354 { 355 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 356 struct hdmi_spec *spec = codec->spec; 357 struct hdmi_spec_per_pin *per_pin; 358 struct hdmi_eld *eld; 359 int pcm_idx; 360 int err = 0; 361 362 pcm_idx = kcontrol->private_value; 363 mutex_lock(&spec->pcm_lock); 364 per_pin = pcm_idx_to_pin(spec, pcm_idx); 365 if (!per_pin) { 366 /* no pin is bound to the pcm */ 367 memset(ucontrol->value.bytes.data, 0, 368 ARRAY_SIZE(ucontrol->value.bytes.data)); 369 goto unlock; 370 } 371 372 eld = &per_pin->sink_eld; 373 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || 374 eld->eld_size > ELD_MAX_SIZE) { 375 snd_BUG(); 376 err = -EINVAL; 377 goto unlock; 378 } 379 380 memset(ucontrol->value.bytes.data, 0, 381 ARRAY_SIZE(ucontrol->value.bytes.data)); 382 if (eld->eld_valid) 383 memcpy(ucontrol->value.bytes.data, eld->eld_buffer, 384 eld->eld_size); 385 386 unlock: 387 mutex_unlock(&spec->pcm_lock); 388 return err; 389 } 390 391 static const struct snd_kcontrol_new eld_bytes_ctl = { 392 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, 393 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 394 .name = "ELD", 395 .info = hdmi_eld_ctl_info, 396 .get = hdmi_eld_ctl_get, 397 }; 398 399 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, 400 int device) 401 { 402 struct snd_kcontrol *kctl; 403 struct hdmi_spec *spec = codec->spec; 404 int err; 405 406 kctl = snd_ctl_new1(&eld_bytes_ctl, codec); 407 if (!kctl) 408 return -ENOMEM; 409 kctl->private_value = pcm_idx; 410 kctl->id.device = device; 411 412 /* no pin nid is associated with the kctl now 413 * tbd: associate pin nid to eld ctl later 414 */ 415 err = snd_hda_ctl_add(codec, 0, kctl); 416 if (err < 0) 417 return err; 418 419 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; 420 return 0; 421 } 422 423 #ifdef BE_PARANOID 424 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 425 int *packet_index, int *byte_index) 426 { 427 int val; 428 429 val = snd_hda_codec_read(codec, pin_nid, 0, 430 AC_VERB_GET_HDMI_DIP_INDEX, 0); 431 432 *packet_index = val >> 5; 433 *byte_index = val & 0x1f; 434 } 435 #endif 436 437 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 438 int packet_index, int byte_index) 439 { 440 int val; 441 442 val = (packet_index << 5) | (byte_index & 0x1f); 443 444 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); 445 } 446 447 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, 448 unsigned char val) 449 { 450 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); 451 } 452 453 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) 454 { 455 struct hdmi_spec *spec = codec->spec; 456 int pin_out; 457 458 /* Unmute */ 459 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 460 snd_hda_codec_write(codec, pin_nid, 0, 461 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); 462 463 if (spec->dyn_pin_out) 464 /* Disable pin out until stream is active */ 465 pin_out = 0; 466 else 467 /* Enable pin out: some machines with GM965 gets broken output 468 * when the pin is disabled or changed while using with HDMI 469 */ 470 pin_out = PIN_OUT; 471 472 snd_hda_codec_write(codec, pin_nid, 0, 473 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); 474 } 475 476 /* 477 * ELD proc files 478 */ 479 480 #ifdef CONFIG_SND_PROC_FS 481 static void print_eld_info(struct snd_info_entry *entry, 482 struct snd_info_buffer *buffer) 483 { 484 struct hdmi_spec_per_pin *per_pin = entry->private_data; 485 486 mutex_lock(&per_pin->lock); 487 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer); 488 mutex_unlock(&per_pin->lock); 489 } 490 491 static void write_eld_info(struct snd_info_entry *entry, 492 struct snd_info_buffer *buffer) 493 { 494 struct hdmi_spec_per_pin *per_pin = entry->private_data; 495 496 mutex_lock(&per_pin->lock); 497 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); 498 mutex_unlock(&per_pin->lock); 499 } 500 501 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) 502 { 503 char name[32]; 504 struct hda_codec *codec = per_pin->codec; 505 struct snd_info_entry *entry; 506 int err; 507 508 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); 509 err = snd_card_proc_new(codec->card, name, &entry); 510 if (err < 0) 511 return err; 512 513 snd_info_set_text_ops(entry, per_pin, print_eld_info); 514 entry->c.text.write = write_eld_info; 515 entry->mode |= 0200; 516 per_pin->proc_entry = entry; 517 518 return 0; 519 } 520 521 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 522 { 523 if (!per_pin->codec->bus->shutdown) { 524 snd_info_free_entry(per_pin->proc_entry); 525 per_pin->proc_entry = NULL; 526 } 527 } 528 #else 529 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, 530 int index) 531 { 532 return 0; 533 } 534 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 535 { 536 } 537 #endif 538 539 /* 540 * Audio InfoFrame routines 541 */ 542 543 /* 544 * Enable Audio InfoFrame Transmission 545 */ 546 static void hdmi_start_infoframe_trans(struct hda_codec *codec, 547 hda_nid_t pin_nid) 548 { 549 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 550 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 551 AC_DIPXMIT_BEST); 552 } 553 554 /* 555 * Disable Audio InfoFrame Transmission 556 */ 557 static void hdmi_stop_infoframe_trans(struct hda_codec *codec, 558 hda_nid_t pin_nid) 559 { 560 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 561 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 562 AC_DIPXMIT_DISABLE); 563 } 564 565 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) 566 { 567 #ifdef CONFIG_SND_DEBUG_VERBOSE 568 int i; 569 int size; 570 571 size = snd_hdmi_get_eld_size(codec, pin_nid); 572 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); 573 574 for (i = 0; i < 8; i++) { 575 size = snd_hda_codec_read(codec, pin_nid, 0, 576 AC_VERB_GET_HDMI_DIP_SIZE, i); 577 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); 578 } 579 #endif 580 } 581 582 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) 583 { 584 #ifdef BE_PARANOID 585 int i, j; 586 int size; 587 int pi, bi; 588 for (i = 0; i < 8; i++) { 589 size = snd_hda_codec_read(codec, pin_nid, 0, 590 AC_VERB_GET_HDMI_DIP_SIZE, i); 591 if (size == 0) 592 continue; 593 594 hdmi_set_dip_index(codec, pin_nid, i, 0x0); 595 for (j = 1; j < 1000; j++) { 596 hdmi_write_dip_byte(codec, pin_nid, 0x0); 597 hdmi_get_dip_index(codec, pin_nid, &pi, &bi); 598 if (pi != i) 599 codec_dbg(codec, "dip index %d: %d != %d\n", 600 bi, pi, i); 601 if (bi == 0) /* byte index wrapped around */ 602 break; 603 } 604 codec_dbg(codec, 605 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", 606 i, size, j); 607 } 608 #endif 609 } 610 611 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) 612 { 613 u8 *bytes = (u8 *)hdmi_ai; 614 u8 sum = 0; 615 int i; 616 617 hdmi_ai->checksum = 0; 618 619 for (i = 0; i < sizeof(*hdmi_ai); i++) 620 sum += bytes[i]; 621 622 hdmi_ai->checksum = -sum; 623 } 624 625 static void hdmi_fill_audio_infoframe(struct hda_codec *codec, 626 hda_nid_t pin_nid, 627 u8 *dip, int size) 628 { 629 int i; 630 631 hdmi_debug_dip_size(codec, pin_nid); 632 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ 633 634 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 635 for (i = 0; i < size; i++) 636 hdmi_write_dip_byte(codec, pin_nid, dip[i]); 637 } 638 639 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, 640 u8 *dip, int size) 641 { 642 u8 val; 643 int i; 644 645 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) 646 != AC_DIPXMIT_BEST) 647 return false; 648 649 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 650 for (i = 0; i < size; i++) { 651 val = snd_hda_codec_read(codec, pin_nid, 0, 652 AC_VERB_GET_HDMI_DIP_DATA, 0); 653 if (val != dip[i]) 654 return false; 655 } 656 657 return true; 658 } 659 660 static void hdmi_pin_setup_infoframe(struct hda_codec *codec, 661 hda_nid_t pin_nid, 662 int ca, int active_channels, 663 int conn_type) 664 { 665 union audio_infoframe ai; 666 667 memset(&ai, 0, sizeof(ai)); 668 if (conn_type == 0) { /* HDMI */ 669 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; 670 671 hdmi_ai->type = 0x84; 672 hdmi_ai->ver = 0x01; 673 hdmi_ai->len = 0x0a; 674 hdmi_ai->CC02_CT47 = active_channels - 1; 675 hdmi_ai->CA = ca; 676 hdmi_checksum_audio_infoframe(hdmi_ai); 677 } else if (conn_type == 1) { /* DisplayPort */ 678 struct dp_audio_infoframe *dp_ai = &ai.dp; 679 680 dp_ai->type = 0x84; 681 dp_ai->len = 0x1b; 682 dp_ai->ver = 0x11 << 2; 683 dp_ai->CC02_CT47 = active_channels - 1; 684 dp_ai->CA = ca; 685 } else { 686 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n", 687 pin_nid); 688 return; 689 } 690 691 /* 692 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or 693 * sizeof(*dp_ai) to avoid partial match/update problems when 694 * the user switches between HDMI/DP monitors. 695 */ 696 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, 697 sizeof(ai))) { 698 codec_dbg(codec, 699 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n", 700 pin_nid, 701 active_channels, ca); 702 hdmi_stop_infoframe_trans(codec, pin_nid); 703 hdmi_fill_audio_infoframe(codec, pin_nid, 704 ai.bytes, sizeof(ai)); 705 hdmi_start_infoframe_trans(codec, pin_nid); 706 } 707 } 708 709 static void hdmi_setup_audio_infoframe(struct hda_codec *codec, 710 struct hdmi_spec_per_pin *per_pin, 711 bool non_pcm) 712 { 713 struct hdmi_spec *spec = codec->spec; 714 struct hdac_chmap *chmap = &spec->chmap; 715 hda_nid_t pin_nid = per_pin->pin_nid; 716 int channels = per_pin->channels; 717 int active_channels; 718 struct hdmi_eld *eld; 719 int ca; 720 721 if (!channels) 722 return; 723 724 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ 725 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 726 snd_hda_codec_write(codec, pin_nid, 0, 727 AC_VERB_SET_AMP_GAIN_MUTE, 728 AMP_OUT_UNMUTE); 729 730 eld = &per_pin->sink_eld; 731 732 ca = snd_hdac_channel_allocation(&codec->core, 733 eld->info.spk_alloc, channels, 734 per_pin->chmap_set, non_pcm, per_pin->chmap); 735 736 active_channels = snd_hdac_get_active_channels(ca); 737 738 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, 739 active_channels); 740 741 /* 742 * always configure channel mapping, it may have been changed by the 743 * user in the meantime 744 */ 745 snd_hdac_setup_channel_mapping(&spec->chmap, 746 pin_nid, non_pcm, ca, channels, 747 per_pin->chmap, per_pin->chmap_set); 748 749 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels, 750 eld->info.conn_type); 751 752 per_pin->non_pcm = non_pcm; 753 } 754 755 /* 756 * Unsolicited events 757 */ 758 759 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); 760 761 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, 762 int dev_id) 763 { 764 struct hdmi_spec *spec = codec->spec; 765 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); 766 767 if (pin_idx < 0) 768 return; 769 mutex_lock(&spec->pcm_lock); 770 if (hdmi_present_sense(get_pin(spec, pin_idx), 1)) 771 snd_hda_jack_report_sync(codec); 772 mutex_unlock(&spec->pcm_lock); 773 } 774 775 static void jack_callback(struct hda_codec *codec, 776 struct hda_jack_callback *jack) 777 { 778 /* hda_jack don't support DP MST */ 779 check_presence_and_report(codec, jack->nid, 0); 780 } 781 782 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res) 783 { 784 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 785 struct hda_jack_tbl *jack; 786 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 787 788 /* 789 * assume DP MST uses dyn_pcm_assign and acomp and 790 * never comes here 791 * if DP MST supports unsol event, below code need 792 * consider dev_entry 793 */ 794 jack = snd_hda_jack_tbl_get_from_tag(codec, tag); 795 if (!jack) 796 return; 797 jack->jack_dirty = 1; 798 799 codec_dbg(codec, 800 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", 801 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA), 802 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); 803 804 /* hda_jack don't support DP MST */ 805 check_presence_and_report(codec, jack->nid, 0); 806 } 807 808 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) 809 { 810 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 811 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 812 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); 813 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); 814 815 codec_info(codec, 816 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", 817 codec->addr, 818 tag, 819 subtag, 820 cp_state, 821 cp_ready); 822 823 /* TODO */ 824 if (cp_state) 825 ; 826 if (cp_ready) 827 ; 828 } 829 830 831 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) 832 { 833 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 834 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 835 836 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) { 837 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); 838 return; 839 } 840 841 if (subtag == 0) 842 hdmi_intrinsic_event(codec, res); 843 else 844 hdmi_non_intrinsic_event(codec, res); 845 } 846 847 static void haswell_verify_D0(struct hda_codec *codec, 848 hda_nid_t cvt_nid, hda_nid_t nid) 849 { 850 int pwr; 851 852 /* For Haswell, the converter 1/2 may keep in D3 state after bootup, 853 * thus pins could only choose converter 0 for use. Make sure the 854 * converters are in correct power state */ 855 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) 856 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); 857 858 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { 859 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, 860 AC_PWRST_D0); 861 msleep(40); 862 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); 863 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; 864 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr); 865 } 866 } 867 868 /* 869 * Callbacks 870 */ 871 872 /* HBR should be Non-PCM, 8 channels */ 873 #define is_hbr_format(format) \ 874 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) 875 876 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 877 bool hbr) 878 { 879 int pinctl, new_pinctl; 880 881 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { 882 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 883 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 884 885 if (pinctl < 0) 886 return hbr ? -EINVAL : 0; 887 888 new_pinctl = pinctl & ~AC_PINCTL_EPT; 889 if (hbr) 890 new_pinctl |= AC_PINCTL_EPT_HBR; 891 else 892 new_pinctl |= AC_PINCTL_EPT_NATIVE; 893 894 codec_dbg(codec, 895 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", 896 pin_nid, 897 pinctl == new_pinctl ? "" : "new-", 898 new_pinctl); 899 900 if (pinctl != new_pinctl) 901 snd_hda_codec_write(codec, pin_nid, 0, 902 AC_VERB_SET_PIN_WIDGET_CONTROL, 903 new_pinctl); 904 } else if (hbr) 905 return -EINVAL; 906 907 return 0; 908 } 909 910 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 911 hda_nid_t pin_nid, u32 stream_tag, int format) 912 { 913 struct hdmi_spec *spec = codec->spec; 914 unsigned int param; 915 int err; 916 917 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format)); 918 919 if (err) { 920 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); 921 return err; 922 } 923 924 if (is_haswell_plus(codec)) { 925 926 /* 927 * on recent platforms IEC Coding Type is required for HBR 928 * support, read current Digital Converter settings and set 929 * ICT bitfield if needed. 930 */ 931 param = snd_hda_codec_read(codec, cvt_nid, 0, 932 AC_VERB_GET_DIGI_CONVERT_1, 0); 933 934 param = (param >> 16) & ~(AC_DIG3_ICT); 935 936 /* on recent platforms ICT mode is required for HBR support */ 937 if (is_hbr_format(format)) 938 param |= 0x1; 939 940 snd_hda_codec_write(codec, cvt_nid, 0, 941 AC_VERB_SET_DIGI_CONVERT_3, param); 942 } 943 944 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); 945 return 0; 946 } 947 948 /* Try to find an available converter 949 * If pin_idx is less then zero, just try to find an available converter. 950 * Otherwise, try to find an available converter and get the cvt mux index 951 * of the pin. 952 */ 953 static int hdmi_choose_cvt(struct hda_codec *codec, 954 int pin_idx, int *cvt_id) 955 { 956 struct hdmi_spec *spec = codec->spec; 957 struct hdmi_spec_per_pin *per_pin; 958 struct hdmi_spec_per_cvt *per_cvt = NULL; 959 int cvt_idx, mux_idx = 0; 960 961 /* pin_idx < 0 means no pin will be bound to the converter */ 962 if (pin_idx < 0) 963 per_pin = NULL; 964 else 965 per_pin = get_pin(spec, pin_idx); 966 967 /* Dynamically assign converter to stream */ 968 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 969 per_cvt = get_cvt(spec, cvt_idx); 970 971 /* Must not already be assigned */ 972 if (per_cvt->assigned) 973 continue; 974 if (per_pin == NULL) 975 break; 976 /* Must be in pin's mux's list of converters */ 977 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 978 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) 979 break; 980 /* Not in mux list */ 981 if (mux_idx == per_pin->num_mux_nids) 982 continue; 983 break; 984 } 985 986 /* No free converters */ 987 if (cvt_idx == spec->num_cvts) 988 return -EBUSY; 989 990 if (per_pin != NULL) 991 per_pin->mux_idx = mux_idx; 992 993 if (cvt_id) 994 *cvt_id = cvt_idx; 995 996 return 0; 997 } 998 999 /* Assure the pin select the right convetor */ 1000 static void intel_verify_pin_cvt_connect(struct hda_codec *codec, 1001 struct hdmi_spec_per_pin *per_pin) 1002 { 1003 hda_nid_t pin_nid = per_pin->pin_nid; 1004 int mux_idx, curr; 1005 1006 mux_idx = per_pin->mux_idx; 1007 curr = snd_hda_codec_read(codec, pin_nid, 0, 1008 AC_VERB_GET_CONNECT_SEL, 0); 1009 if (curr != mux_idx) 1010 snd_hda_codec_write_cache(codec, pin_nid, 0, 1011 AC_VERB_SET_CONNECT_SEL, 1012 mux_idx); 1013 } 1014 1015 /* get the mux index for the converter of the pins 1016 * converter's mux index is the same for all pins on Intel platform 1017 */ 1018 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, 1019 hda_nid_t cvt_nid) 1020 { 1021 int i; 1022 1023 for (i = 0; i < spec->num_cvts; i++) 1024 if (spec->cvt_nids[i] == cvt_nid) 1025 return i; 1026 return -EINVAL; 1027 } 1028 1029 /* Intel HDMI workaround to fix audio routing issue: 1030 * For some Intel display codecs, pins share the same connection list. 1031 * So a conveter can be selected by multiple pins and playback on any of these 1032 * pins will generate sound on the external display, because audio flows from 1033 * the same converter to the display pipeline. Also muting one pin may make 1034 * other pins have no sound output. 1035 * So this function assures that an assigned converter for a pin is not selected 1036 * by any other pins. 1037 */ 1038 static void intel_not_share_assigned_cvt(struct hda_codec *codec, 1039 hda_nid_t pin_nid, 1040 int dev_id, int mux_idx) 1041 { 1042 struct hdmi_spec *spec = codec->spec; 1043 hda_nid_t nid; 1044 int cvt_idx, curr; 1045 struct hdmi_spec_per_cvt *per_cvt; 1046 struct hdmi_spec_per_pin *per_pin; 1047 int pin_idx; 1048 1049 /* configure the pins connections */ 1050 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 1051 int dev_id_saved; 1052 int dev_num; 1053 1054 per_pin = get_pin(spec, pin_idx); 1055 /* 1056 * pin not connected to monitor 1057 * no need to operate on it 1058 */ 1059 if (!per_pin->pcm) 1060 continue; 1061 1062 if ((per_pin->pin_nid == pin_nid) && 1063 (per_pin->dev_id == dev_id)) 1064 continue; 1065 1066 /* 1067 * if per_pin->dev_id >= dev_num, 1068 * snd_hda_get_dev_select() will fail, 1069 * and the following operation is unpredictable. 1070 * So skip this situation. 1071 */ 1072 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; 1073 if (per_pin->dev_id >= dev_num) 1074 continue; 1075 1076 nid = per_pin->pin_nid; 1077 1078 /* 1079 * Calling this function should not impact 1080 * on the device entry selection 1081 * So let's save the dev id for each pin, 1082 * and restore it when return 1083 */ 1084 dev_id_saved = snd_hda_get_dev_select(codec, nid); 1085 snd_hda_set_dev_select(codec, nid, per_pin->dev_id); 1086 curr = snd_hda_codec_read(codec, nid, 0, 1087 AC_VERB_GET_CONNECT_SEL, 0); 1088 if (curr != mux_idx) { 1089 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1090 continue; 1091 } 1092 1093 1094 /* choose an unassigned converter. The conveters in the 1095 * connection list are in the same order as in the codec. 1096 */ 1097 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1098 per_cvt = get_cvt(spec, cvt_idx); 1099 if (!per_cvt->assigned) { 1100 codec_dbg(codec, 1101 "choose cvt %d for pin nid %d\n", 1102 cvt_idx, nid); 1103 snd_hda_codec_write_cache(codec, nid, 0, 1104 AC_VERB_SET_CONNECT_SEL, 1105 cvt_idx); 1106 break; 1107 } 1108 } 1109 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1110 } 1111 } 1112 1113 /* A wrapper of intel_not_share_asigned_cvt() */ 1114 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, 1115 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) 1116 { 1117 int mux_idx; 1118 struct hdmi_spec *spec = codec->spec; 1119 1120 /* On Intel platform, the mapping of converter nid to 1121 * mux index of the pins are always the same. 1122 * The pin nid may be 0, this means all pins will not 1123 * share the converter. 1124 */ 1125 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); 1126 if (mux_idx >= 0) 1127 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); 1128 } 1129 1130 /* skeleton caller of pin_cvt_fixup ops */ 1131 static void pin_cvt_fixup(struct hda_codec *codec, 1132 struct hdmi_spec_per_pin *per_pin, 1133 hda_nid_t cvt_nid) 1134 { 1135 struct hdmi_spec *spec = codec->spec; 1136 1137 if (spec->ops.pin_cvt_fixup) 1138 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); 1139 } 1140 1141 /* called in hdmi_pcm_open when no pin is assigned to the PCM 1142 * in dyn_pcm_assign mode. 1143 */ 1144 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, 1145 struct hda_codec *codec, 1146 struct snd_pcm_substream *substream) 1147 { 1148 struct hdmi_spec *spec = codec->spec; 1149 struct snd_pcm_runtime *runtime = substream->runtime; 1150 int cvt_idx, pcm_idx; 1151 struct hdmi_spec_per_cvt *per_cvt = NULL; 1152 int err; 1153 1154 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1155 if (pcm_idx < 0) 1156 return -EINVAL; 1157 1158 err = hdmi_choose_cvt(codec, -1, &cvt_idx); 1159 if (err) 1160 return err; 1161 1162 per_cvt = get_cvt(spec, cvt_idx); 1163 per_cvt->assigned = 1; 1164 hinfo->nid = per_cvt->cvt_nid; 1165 1166 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); 1167 1168 set_bit(pcm_idx, &spec->pcm_in_use); 1169 /* todo: setup spdif ctls assign */ 1170 1171 /* Initially set the converter's capabilities */ 1172 hinfo->channels_min = per_cvt->channels_min; 1173 hinfo->channels_max = per_cvt->channels_max; 1174 hinfo->rates = per_cvt->rates; 1175 hinfo->formats = per_cvt->formats; 1176 hinfo->maxbps = per_cvt->maxbps; 1177 1178 /* Store the updated parameters */ 1179 runtime->hw.channels_min = hinfo->channels_min; 1180 runtime->hw.channels_max = hinfo->channels_max; 1181 runtime->hw.formats = hinfo->formats; 1182 runtime->hw.rates = hinfo->rates; 1183 1184 snd_pcm_hw_constraint_step(substream->runtime, 0, 1185 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1186 return 0; 1187 } 1188 1189 /* 1190 * HDA PCM callbacks 1191 */ 1192 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, 1193 struct hda_codec *codec, 1194 struct snd_pcm_substream *substream) 1195 { 1196 struct hdmi_spec *spec = codec->spec; 1197 struct snd_pcm_runtime *runtime = substream->runtime; 1198 int pin_idx, cvt_idx, pcm_idx; 1199 struct hdmi_spec_per_pin *per_pin; 1200 struct hdmi_eld *eld; 1201 struct hdmi_spec_per_cvt *per_cvt = NULL; 1202 int err; 1203 1204 /* Validate hinfo */ 1205 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1206 if (pcm_idx < 0) 1207 return -EINVAL; 1208 1209 mutex_lock(&spec->pcm_lock); 1210 pin_idx = hinfo_to_pin_index(codec, hinfo); 1211 if (!spec->dyn_pcm_assign) { 1212 if (snd_BUG_ON(pin_idx < 0)) { 1213 err = -EINVAL; 1214 goto unlock; 1215 } 1216 } else { 1217 /* no pin is assigned to the PCM 1218 * PA need pcm open successfully when probe 1219 */ 1220 if (pin_idx < 0) { 1221 err = hdmi_pcm_open_no_pin(hinfo, codec, substream); 1222 goto unlock; 1223 } 1224 } 1225 1226 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx); 1227 if (err < 0) 1228 goto unlock; 1229 1230 per_cvt = get_cvt(spec, cvt_idx); 1231 /* Claim converter */ 1232 per_cvt->assigned = 1; 1233 1234 set_bit(pcm_idx, &spec->pcm_in_use); 1235 per_pin = get_pin(spec, pin_idx); 1236 per_pin->cvt_nid = per_cvt->cvt_nid; 1237 hinfo->nid = per_cvt->cvt_nid; 1238 1239 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1240 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1241 AC_VERB_SET_CONNECT_SEL, 1242 per_pin->mux_idx); 1243 1244 /* configure unused pins to choose other converters */ 1245 pin_cvt_fixup(codec, per_pin, 0); 1246 1247 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); 1248 1249 /* Initially set the converter's capabilities */ 1250 hinfo->channels_min = per_cvt->channels_min; 1251 hinfo->channels_max = per_cvt->channels_max; 1252 hinfo->rates = per_cvt->rates; 1253 hinfo->formats = per_cvt->formats; 1254 hinfo->maxbps = per_cvt->maxbps; 1255 1256 eld = &per_pin->sink_eld; 1257 /* Restrict capabilities by ELD if this isn't disabled */ 1258 if (!static_hdmi_pcm && eld->eld_valid) { 1259 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); 1260 if (hinfo->channels_min > hinfo->channels_max || 1261 !hinfo->rates || !hinfo->formats) { 1262 per_cvt->assigned = 0; 1263 hinfo->nid = 0; 1264 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1265 err = -ENODEV; 1266 goto unlock; 1267 } 1268 } 1269 1270 /* Store the updated parameters */ 1271 runtime->hw.channels_min = hinfo->channels_min; 1272 runtime->hw.channels_max = hinfo->channels_max; 1273 runtime->hw.formats = hinfo->formats; 1274 runtime->hw.rates = hinfo->rates; 1275 1276 snd_pcm_hw_constraint_step(substream->runtime, 0, 1277 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1278 unlock: 1279 mutex_unlock(&spec->pcm_lock); 1280 return err; 1281 } 1282 1283 /* 1284 * HDA/HDMI auto parsing 1285 */ 1286 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) 1287 { 1288 struct hdmi_spec *spec = codec->spec; 1289 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1290 hda_nid_t pin_nid = per_pin->pin_nid; 1291 1292 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { 1293 codec_warn(codec, 1294 "HDMI: pin %d wcaps %#x does not support connection list\n", 1295 pin_nid, get_wcaps(codec, pin_nid)); 1296 return -EINVAL; 1297 } 1298 1299 /* all the device entries on the same pin have the same conn list */ 1300 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid, 1301 per_pin->mux_nids, 1302 HDA_MAX_CONNECTIONS); 1303 1304 return 0; 1305 } 1306 1307 static int hdmi_find_pcm_slot(struct hdmi_spec *spec, 1308 struct hdmi_spec_per_pin *per_pin) 1309 { 1310 int i; 1311 1312 /* try the prefer PCM */ 1313 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap)) 1314 return per_pin->pin_nid_idx; 1315 1316 /* have a second try; check the "reserved area" over num_pins */ 1317 for (i = spec->num_nids; i < spec->pcm_used; i++) { 1318 if (!test_bit(i, &spec->pcm_bitmap)) 1319 return i; 1320 } 1321 1322 /* the last try; check the empty slots in pins */ 1323 for (i = 0; i < spec->num_nids; i++) { 1324 if (!test_bit(i, &spec->pcm_bitmap)) 1325 return i; 1326 } 1327 return -EBUSY; 1328 } 1329 1330 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, 1331 struct hdmi_spec_per_pin *per_pin) 1332 { 1333 int idx; 1334 1335 /* pcm already be attached to the pin */ 1336 if (per_pin->pcm) 1337 return; 1338 idx = hdmi_find_pcm_slot(spec, per_pin); 1339 if (idx == -EBUSY) 1340 return; 1341 per_pin->pcm_idx = idx; 1342 per_pin->pcm = get_hdmi_pcm(spec, idx); 1343 set_bit(idx, &spec->pcm_bitmap); 1344 } 1345 1346 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, 1347 struct hdmi_spec_per_pin *per_pin) 1348 { 1349 int idx; 1350 1351 /* pcm already be detached from the pin */ 1352 if (!per_pin->pcm) 1353 return; 1354 idx = per_pin->pcm_idx; 1355 per_pin->pcm_idx = -1; 1356 per_pin->pcm = NULL; 1357 if (idx >= 0 && idx < spec->pcm_used) 1358 clear_bit(idx, &spec->pcm_bitmap); 1359 } 1360 1361 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, 1362 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) 1363 { 1364 int mux_idx; 1365 1366 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1367 if (per_pin->mux_nids[mux_idx] == cvt_nid) 1368 break; 1369 return mux_idx; 1370 } 1371 1372 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); 1373 1374 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, 1375 struct hdmi_spec_per_pin *per_pin) 1376 { 1377 struct hda_codec *codec = per_pin->codec; 1378 struct hda_pcm *pcm; 1379 struct hda_pcm_stream *hinfo; 1380 struct snd_pcm_substream *substream; 1381 int mux_idx; 1382 bool non_pcm; 1383 1384 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1385 pcm = get_pcm_rec(spec, per_pin->pcm_idx); 1386 else 1387 return; 1388 if (!pcm->pcm) 1389 return; 1390 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) 1391 return; 1392 1393 /* hdmi audio only uses playback and one substream */ 1394 hinfo = pcm->stream; 1395 substream = pcm->pcm->streams[0].substream; 1396 1397 per_pin->cvt_nid = hinfo->nid; 1398 1399 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); 1400 if (mux_idx < per_pin->num_mux_nids) { 1401 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1402 per_pin->dev_id); 1403 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1404 AC_VERB_SET_CONNECT_SEL, 1405 mux_idx); 1406 } 1407 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); 1408 1409 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); 1410 if (substream->runtime) 1411 per_pin->channels = substream->runtime->channels; 1412 per_pin->setup = true; 1413 per_pin->mux_idx = mux_idx; 1414 1415 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1416 } 1417 1418 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, 1419 struct hdmi_spec_per_pin *per_pin) 1420 { 1421 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1422 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); 1423 1424 per_pin->chmap_set = false; 1425 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1426 1427 per_pin->setup = false; 1428 per_pin->channels = 0; 1429 } 1430 1431 /* update per_pin ELD from the given new ELD; 1432 * setup info frame and notification accordingly 1433 */ 1434 static void update_eld(struct hda_codec *codec, 1435 struct hdmi_spec_per_pin *per_pin, 1436 struct hdmi_eld *eld) 1437 { 1438 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 1439 struct hdmi_spec *spec = codec->spec; 1440 bool old_eld_valid = pin_eld->eld_valid; 1441 bool eld_changed; 1442 int pcm_idx = -1; 1443 1444 /* for monitor disconnection, save pcm_idx firstly */ 1445 pcm_idx = per_pin->pcm_idx; 1446 if (spec->dyn_pcm_assign) { 1447 if (eld->eld_valid) { 1448 hdmi_attach_hda_pcm(spec, per_pin); 1449 hdmi_pcm_setup_pin(spec, per_pin); 1450 } else { 1451 hdmi_pcm_reset_pin(spec, per_pin); 1452 hdmi_detach_hda_pcm(spec, per_pin); 1453 } 1454 } 1455 /* if pcm_idx == -1, it means this is in monitor connection event 1456 * we can get the correct pcm_idx now. 1457 */ 1458 if (pcm_idx == -1) 1459 pcm_idx = per_pin->pcm_idx; 1460 1461 if (eld->eld_valid) 1462 snd_hdmi_show_eld(codec, &eld->info); 1463 1464 eld_changed = (pin_eld->eld_valid != eld->eld_valid); 1465 if (eld->eld_valid && pin_eld->eld_valid) 1466 if (pin_eld->eld_size != eld->eld_size || 1467 memcmp(pin_eld->eld_buffer, eld->eld_buffer, 1468 eld->eld_size) != 0) 1469 eld_changed = true; 1470 1471 pin_eld->monitor_present = eld->monitor_present; 1472 pin_eld->eld_valid = eld->eld_valid; 1473 pin_eld->eld_size = eld->eld_size; 1474 if (eld->eld_valid) 1475 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size); 1476 pin_eld->info = eld->info; 1477 1478 /* 1479 * Re-setup pin and infoframe. This is needed e.g. when 1480 * - sink is first plugged-in 1481 * - transcoder can change during stream playback on Haswell 1482 * and this can make HW reset converter selection on a pin. 1483 */ 1484 if (eld->eld_valid && !old_eld_valid && per_pin->setup) { 1485 pin_cvt_fixup(codec, per_pin, 0); 1486 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1487 } 1488 1489 if (eld_changed && pcm_idx >= 0) 1490 snd_ctl_notify(codec->card, 1491 SNDRV_CTL_EVENT_MASK_VALUE | 1492 SNDRV_CTL_EVENT_MASK_INFO, 1493 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); 1494 } 1495 1496 /* update ELD and jack state via HD-audio verbs */ 1497 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, 1498 int repoll) 1499 { 1500 struct hda_jack_tbl *jack; 1501 struct hda_codec *codec = per_pin->codec; 1502 struct hdmi_spec *spec = codec->spec; 1503 struct hdmi_eld *eld = &spec->temp_eld; 1504 hda_nid_t pin_nid = per_pin->pin_nid; 1505 /* 1506 * Always execute a GetPinSense verb here, even when called from 1507 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited 1508 * response's PD bit is not the real PD value, but indicates that 1509 * the real PD value changed. An older version of the HD-audio 1510 * specification worked this way. Hence, we just ignore the data in 1511 * the unsolicited response to avoid custom WARs. 1512 */ 1513 int present; 1514 bool ret; 1515 bool do_repoll = false; 1516 1517 present = snd_hda_pin_sense(codec, pin_nid); 1518 1519 mutex_lock(&per_pin->lock); 1520 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); 1521 if (eld->monitor_present) 1522 eld->eld_valid = !!(present & AC_PINSENSE_ELDV); 1523 else 1524 eld->eld_valid = false; 1525 1526 codec_dbg(codec, 1527 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n", 1528 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); 1529 1530 if (eld->eld_valid) { 1531 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer, 1532 &eld->eld_size) < 0) 1533 eld->eld_valid = false; 1534 else { 1535 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, 1536 eld->eld_size) < 0) 1537 eld->eld_valid = false; 1538 } 1539 if (!eld->eld_valid && repoll) 1540 do_repoll = true; 1541 } 1542 1543 if (do_repoll) 1544 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300)); 1545 else 1546 update_eld(codec, per_pin, eld); 1547 1548 ret = !repoll || !eld->monitor_present || eld->eld_valid; 1549 1550 jack = snd_hda_jack_tbl_get(codec, pin_nid); 1551 if (jack) 1552 jack->block_report = !ret; 1553 1554 mutex_unlock(&per_pin->lock); 1555 return ret; 1556 } 1557 1558 static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec, 1559 struct hdmi_spec_per_pin *per_pin) 1560 { 1561 struct hdmi_spec *spec = codec->spec; 1562 struct snd_jack *jack = NULL; 1563 struct hda_jack_tbl *jack_tbl; 1564 1565 /* if !dyn_pcm_assign, get jack from hda_jack_tbl 1566 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not 1567 * NULL even after snd_hda_jack_tbl_clear() is called to 1568 * free snd_jack. This may cause access invalid memory 1569 * when calling snd_jack_report 1570 */ 1571 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign) 1572 jack = spec->pcm_rec[per_pin->pcm_idx].jack; 1573 else if (!spec->dyn_pcm_assign) { 1574 /* 1575 * jack tbl doesn't support DP MST 1576 * DP MST will use dyn_pcm_assign, 1577 * so DP MST will never come here 1578 */ 1579 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid); 1580 if (jack_tbl) 1581 jack = jack_tbl->jack; 1582 } 1583 return jack; 1584 } 1585 1586 /* update ELD and jack state via audio component */ 1587 static void sync_eld_via_acomp(struct hda_codec *codec, 1588 struct hdmi_spec_per_pin *per_pin) 1589 { 1590 struct hdmi_spec *spec = codec->spec; 1591 struct hdmi_eld *eld = &spec->temp_eld; 1592 struct snd_jack *jack = NULL; 1593 int size; 1594 1595 mutex_lock(&per_pin->lock); 1596 eld->monitor_present = false; 1597 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, 1598 per_pin->dev_id, &eld->monitor_present, 1599 eld->eld_buffer, ELD_MAX_SIZE); 1600 if (size > 0) { 1601 size = min(size, ELD_MAX_SIZE); 1602 if (snd_hdmi_parse_eld(codec, &eld->info, 1603 eld->eld_buffer, size) < 0) 1604 size = -EINVAL; 1605 } 1606 1607 if (size > 0) { 1608 eld->eld_valid = true; 1609 eld->eld_size = size; 1610 } else { 1611 eld->eld_valid = false; 1612 eld->eld_size = 0; 1613 } 1614 1615 /* pcm_idx >=0 before update_eld() means it is in monitor 1616 * disconnected event. Jack must be fetched before update_eld() 1617 */ 1618 jack = pin_idx_to_jack(codec, per_pin); 1619 update_eld(codec, per_pin, eld); 1620 if (jack == NULL) 1621 jack = pin_idx_to_jack(codec, per_pin); 1622 if (jack == NULL) 1623 goto unlock; 1624 snd_jack_report(jack, 1625 eld->monitor_present ? SND_JACK_AVOUT : 0); 1626 unlock: 1627 mutex_unlock(&per_pin->lock); 1628 } 1629 1630 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) 1631 { 1632 struct hda_codec *codec = per_pin->codec; 1633 int ret; 1634 1635 /* no temporary power up/down needed for component notifier */ 1636 if (!codec_has_acomp(codec)) { 1637 ret = snd_hda_power_up_pm(codec); 1638 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) { 1639 snd_hda_power_down_pm(codec); 1640 return false; 1641 } 1642 } 1643 1644 if (codec_has_acomp(codec)) { 1645 sync_eld_via_acomp(codec, per_pin); 1646 ret = false; /* don't call snd_hda_jack_report_sync() */ 1647 } else { 1648 ret = hdmi_present_sense_via_verbs(per_pin, repoll); 1649 } 1650 1651 if (!codec_has_acomp(codec)) 1652 snd_hda_power_down_pm(codec); 1653 1654 return ret; 1655 } 1656 1657 static void hdmi_repoll_eld(struct work_struct *work) 1658 { 1659 struct hdmi_spec_per_pin *per_pin = 1660 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); 1661 struct hda_codec *codec = per_pin->codec; 1662 struct hdmi_spec *spec = codec->spec; 1663 1664 if (per_pin->repoll_count++ > 6) 1665 per_pin->repoll_count = 0; 1666 1667 mutex_lock(&spec->pcm_lock); 1668 if (hdmi_present_sense(per_pin, per_pin->repoll_count)) 1669 snd_hda_jack_report_sync(per_pin->codec); 1670 mutex_unlock(&spec->pcm_lock); 1671 } 1672 1673 static void intel_haswell_fixup_connect_list(struct hda_codec *codec, 1674 hda_nid_t nid); 1675 1676 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) 1677 { 1678 struct hdmi_spec *spec = codec->spec; 1679 unsigned int caps, config; 1680 int pin_idx; 1681 struct hdmi_spec_per_pin *per_pin; 1682 int err; 1683 int dev_num, i; 1684 1685 caps = snd_hda_query_pin_caps(codec, pin_nid); 1686 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) 1687 return 0; 1688 1689 /* 1690 * For DP MST audio, Configuration Default is the same for 1691 * all device entries on the same pin 1692 */ 1693 config = snd_hda_codec_get_pincfg(codec, pin_nid); 1694 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE) 1695 return 0; 1696 1697 /* 1698 * To simplify the implementation, malloc all 1699 * the virtual pins in the initialization statically 1700 */ 1701 if (is_haswell_plus(codec)) { 1702 /* 1703 * On Intel platforms, device entries number is 1704 * changed dynamically. If there is a DP MST 1705 * hub connected, the device entries number is 3. 1706 * Otherwise, it is 1. 1707 * Here we manually set dev_num to 3, so that 1708 * we can initialize all the device entries when 1709 * bootup statically. 1710 */ 1711 dev_num = 3; 1712 spec->dev_num = 3; 1713 } else if (spec->dyn_pcm_assign && codec->dp_mst) { 1714 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; 1715 /* 1716 * spec->dev_num is the maxinum number of device entries 1717 * among all the pins 1718 */ 1719 spec->dev_num = (spec->dev_num > dev_num) ? 1720 spec->dev_num : dev_num; 1721 } else { 1722 /* 1723 * If the platform doesn't support DP MST, 1724 * manually set dev_num to 1. This means 1725 * the pin has only one device entry. 1726 */ 1727 dev_num = 1; 1728 spec->dev_num = 1; 1729 } 1730 1731 for (i = 0; i < dev_num; i++) { 1732 pin_idx = spec->num_pins; 1733 per_pin = snd_array_new(&spec->pins); 1734 1735 if (!per_pin) 1736 return -ENOMEM; 1737 1738 if (spec->dyn_pcm_assign) { 1739 per_pin->pcm = NULL; 1740 per_pin->pcm_idx = -1; 1741 } else { 1742 per_pin->pcm = get_hdmi_pcm(spec, pin_idx); 1743 per_pin->pcm_idx = pin_idx; 1744 } 1745 per_pin->pin_nid = pin_nid; 1746 per_pin->pin_nid_idx = spec->num_nids; 1747 per_pin->dev_id = i; 1748 per_pin->non_pcm = false; 1749 snd_hda_set_dev_select(codec, pin_nid, i); 1750 if (is_haswell_plus(codec)) 1751 intel_haswell_fixup_connect_list(codec, pin_nid); 1752 err = hdmi_read_pin_conn(codec, pin_idx); 1753 if (err < 0) 1754 return err; 1755 spec->num_pins++; 1756 } 1757 spec->num_nids++; 1758 1759 return 0; 1760 } 1761 1762 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1763 { 1764 struct hdmi_spec *spec = codec->spec; 1765 struct hdmi_spec_per_cvt *per_cvt; 1766 unsigned int chans; 1767 int err; 1768 1769 chans = get_wcaps(codec, cvt_nid); 1770 chans = get_wcaps_channels(chans); 1771 1772 per_cvt = snd_array_new(&spec->cvts); 1773 if (!per_cvt) 1774 return -ENOMEM; 1775 1776 per_cvt->cvt_nid = cvt_nid; 1777 per_cvt->channels_min = 2; 1778 if (chans <= 16) { 1779 per_cvt->channels_max = chans; 1780 if (chans > spec->chmap.channels_max) 1781 spec->chmap.channels_max = chans; 1782 } 1783 1784 err = snd_hda_query_supported_pcm(codec, cvt_nid, 1785 &per_cvt->rates, 1786 &per_cvt->formats, 1787 &per_cvt->maxbps); 1788 if (err < 0) 1789 return err; 1790 1791 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) 1792 spec->cvt_nids[spec->num_cvts] = cvt_nid; 1793 spec->num_cvts++; 1794 1795 return 0; 1796 } 1797 1798 static int hdmi_parse_codec(struct hda_codec *codec) 1799 { 1800 hda_nid_t nid; 1801 int i, nodes; 1802 1803 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid); 1804 if (!nid || nodes < 0) { 1805 codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); 1806 return -EINVAL; 1807 } 1808 1809 for (i = 0; i < nodes; i++, nid++) { 1810 unsigned int caps; 1811 unsigned int type; 1812 1813 caps = get_wcaps(codec, nid); 1814 type = get_wcaps_type(caps); 1815 1816 if (!(caps & AC_WCAP_DIGITAL)) 1817 continue; 1818 1819 switch (type) { 1820 case AC_WID_AUD_OUT: 1821 hdmi_add_cvt(codec, nid); 1822 break; 1823 case AC_WID_PIN: 1824 hdmi_add_pin(codec, nid); 1825 break; 1826 } 1827 } 1828 1829 return 0; 1830 } 1831 1832 /* 1833 */ 1834 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1835 { 1836 struct hda_spdif_out *spdif; 1837 bool non_pcm; 1838 1839 mutex_lock(&codec->spdif_mutex); 1840 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); 1841 /* Add sanity check to pass klockwork check. 1842 * This should never happen. 1843 */ 1844 if (WARN_ON(spdif == NULL)) 1845 return true; 1846 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); 1847 mutex_unlock(&codec->spdif_mutex); 1848 return non_pcm; 1849 } 1850 1851 /* 1852 * HDMI callbacks 1853 */ 1854 1855 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 1856 struct hda_codec *codec, 1857 unsigned int stream_tag, 1858 unsigned int format, 1859 struct snd_pcm_substream *substream) 1860 { 1861 hda_nid_t cvt_nid = hinfo->nid; 1862 struct hdmi_spec *spec = codec->spec; 1863 int pin_idx; 1864 struct hdmi_spec_per_pin *per_pin; 1865 hda_nid_t pin_nid; 1866 struct snd_pcm_runtime *runtime = substream->runtime; 1867 bool non_pcm; 1868 int pinctl; 1869 int err = 0; 1870 1871 mutex_lock(&spec->pcm_lock); 1872 pin_idx = hinfo_to_pin_index(codec, hinfo); 1873 if (spec->dyn_pcm_assign && pin_idx < 0) { 1874 /* when dyn_pcm_assign and pcm is not bound to a pin 1875 * skip pin setup and return 0 to make audio playback 1876 * be ongoing 1877 */ 1878 pin_cvt_fixup(codec, NULL, cvt_nid); 1879 snd_hda_codec_setup_stream(codec, cvt_nid, 1880 stream_tag, 0, format); 1881 goto unlock; 1882 } 1883 1884 if (snd_BUG_ON(pin_idx < 0)) { 1885 err = -EINVAL; 1886 goto unlock; 1887 } 1888 per_pin = get_pin(spec, pin_idx); 1889 pin_nid = per_pin->pin_nid; 1890 1891 /* Verify pin:cvt selections to avoid silent audio after S3. 1892 * After S3, the audio driver restores pin:cvt selections 1893 * but this can happen before gfx is ready and such selection 1894 * is overlooked by HW. Thus multiple pins can share a same 1895 * default convertor and mute control will affect each other, 1896 * which can cause a resumed audio playback become silent 1897 * after S3. 1898 */ 1899 pin_cvt_fixup(codec, per_pin, 0); 1900 1901 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ 1902 /* Todo: add DP1.2 MST audio support later */ 1903 if (codec_has_acomp(codec)) 1904 snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id, 1905 runtime->rate); 1906 1907 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); 1908 mutex_lock(&per_pin->lock); 1909 per_pin->channels = substream->runtime->channels; 1910 per_pin->setup = true; 1911 1912 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1913 mutex_unlock(&per_pin->lock); 1914 if (spec->dyn_pin_out) { 1915 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 1916 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 1917 snd_hda_codec_write(codec, pin_nid, 0, 1918 AC_VERB_SET_PIN_WIDGET_CONTROL, 1919 pinctl | PIN_OUT); 1920 } 1921 1922 /* snd_hda_set_dev_select() has been called before */ 1923 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid, 1924 stream_tag, format); 1925 unlock: 1926 mutex_unlock(&spec->pcm_lock); 1927 return err; 1928 } 1929 1930 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 1931 struct hda_codec *codec, 1932 struct snd_pcm_substream *substream) 1933 { 1934 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 1935 return 0; 1936 } 1937 1938 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, 1939 struct hda_codec *codec, 1940 struct snd_pcm_substream *substream) 1941 { 1942 struct hdmi_spec *spec = codec->spec; 1943 int cvt_idx, pin_idx, pcm_idx; 1944 struct hdmi_spec_per_cvt *per_cvt; 1945 struct hdmi_spec_per_pin *per_pin; 1946 int pinctl; 1947 int err = 0; 1948 1949 if (hinfo->nid) { 1950 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1951 if (snd_BUG_ON(pcm_idx < 0)) 1952 return -EINVAL; 1953 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); 1954 if (snd_BUG_ON(cvt_idx < 0)) 1955 return -EINVAL; 1956 per_cvt = get_cvt(spec, cvt_idx); 1957 1958 snd_BUG_ON(!per_cvt->assigned); 1959 per_cvt->assigned = 0; 1960 hinfo->nid = 0; 1961 1962 mutex_lock(&spec->pcm_lock); 1963 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1964 clear_bit(pcm_idx, &spec->pcm_in_use); 1965 pin_idx = hinfo_to_pin_index(codec, hinfo); 1966 if (spec->dyn_pcm_assign && pin_idx < 0) 1967 goto unlock; 1968 1969 if (snd_BUG_ON(pin_idx < 0)) { 1970 err = -EINVAL; 1971 goto unlock; 1972 } 1973 per_pin = get_pin(spec, pin_idx); 1974 1975 if (spec->dyn_pin_out) { 1976 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 1977 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 1978 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 1979 AC_VERB_SET_PIN_WIDGET_CONTROL, 1980 pinctl & ~PIN_OUT); 1981 } 1982 1983 mutex_lock(&per_pin->lock); 1984 per_pin->chmap_set = false; 1985 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1986 1987 per_pin->setup = false; 1988 per_pin->channels = 0; 1989 mutex_unlock(&per_pin->lock); 1990 unlock: 1991 mutex_unlock(&spec->pcm_lock); 1992 } 1993 1994 return err; 1995 } 1996 1997 static const struct hda_pcm_ops generic_ops = { 1998 .open = hdmi_pcm_open, 1999 .close = hdmi_pcm_close, 2000 .prepare = generic_hdmi_playback_pcm_prepare, 2001 .cleanup = generic_hdmi_playback_pcm_cleanup, 2002 }; 2003 2004 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) 2005 { 2006 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2007 struct hdmi_spec *spec = codec->spec; 2008 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2009 2010 if (!per_pin) 2011 return 0; 2012 2013 return per_pin->sink_eld.info.spk_alloc; 2014 } 2015 2016 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, 2017 unsigned char *chmap) 2018 { 2019 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2020 struct hdmi_spec *spec = codec->spec; 2021 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2022 2023 /* chmap is already set to 0 in caller */ 2024 if (!per_pin) 2025 return; 2026 2027 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); 2028 } 2029 2030 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, 2031 unsigned char *chmap, int prepared) 2032 { 2033 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2034 struct hdmi_spec *spec = codec->spec; 2035 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2036 2037 if (!per_pin) 2038 return; 2039 mutex_lock(&per_pin->lock); 2040 per_pin->chmap_set = true; 2041 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); 2042 if (prepared) 2043 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 2044 mutex_unlock(&per_pin->lock); 2045 } 2046 2047 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) 2048 { 2049 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2050 struct hdmi_spec *spec = codec->spec; 2051 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2052 2053 return per_pin ? true:false; 2054 } 2055 2056 static int generic_hdmi_build_pcms(struct hda_codec *codec) 2057 { 2058 struct hdmi_spec *spec = codec->spec; 2059 int idx; 2060 2061 /* 2062 * for non-mst mode, pcm number is the same as before 2063 * for DP MST mode, pcm number is (nid number + dev_num - 1) 2064 * dev_num is the device entry number in a pin 2065 * 2066 */ 2067 for (idx = 0; idx < spec->num_nids + spec->dev_num - 1; idx++) { 2068 struct hda_pcm *info; 2069 struct hda_pcm_stream *pstr; 2070 2071 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); 2072 if (!info) 2073 return -ENOMEM; 2074 2075 spec->pcm_rec[idx].pcm = info; 2076 spec->pcm_used++; 2077 info->pcm_type = HDA_PCM_TYPE_HDMI; 2078 info->own_chmap = true; 2079 2080 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2081 pstr->substreams = 1; 2082 pstr->ops = generic_ops; 2083 /* pcm number is less than 16 */ 2084 if (spec->pcm_used >= 16) 2085 break; 2086 /* other pstr fields are set in open */ 2087 } 2088 2089 return 0; 2090 } 2091 2092 static void free_hdmi_jack_priv(struct snd_jack *jack) 2093 { 2094 struct hdmi_pcm *pcm = jack->private_data; 2095 2096 pcm->jack = NULL; 2097 } 2098 2099 static int add_hdmi_jack_kctl(struct hda_codec *codec, 2100 struct hdmi_spec *spec, 2101 int pcm_idx, 2102 const char *name) 2103 { 2104 struct snd_jack *jack; 2105 int err; 2106 2107 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack, 2108 true, false); 2109 if (err < 0) 2110 return err; 2111 2112 spec->pcm_rec[pcm_idx].jack = jack; 2113 jack->private_data = &spec->pcm_rec[pcm_idx]; 2114 jack->private_free = free_hdmi_jack_priv; 2115 return 0; 2116 } 2117 2118 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) 2119 { 2120 char hdmi_str[32] = "HDMI/DP"; 2121 struct hdmi_spec *spec = codec->spec; 2122 struct hdmi_spec_per_pin *per_pin; 2123 struct hda_jack_tbl *jack; 2124 int pcmdev = get_pcm_rec(spec, pcm_idx)->device; 2125 bool phantom_jack; 2126 int ret; 2127 2128 if (pcmdev > 0) 2129 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); 2130 2131 if (spec->dyn_pcm_assign) 2132 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str); 2133 2134 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */ 2135 /* if !dyn_pcm_assign, it must be non-MST mode. 2136 * This means pcms and pins are statically mapped. 2137 * And pcm_idx is pin_idx. 2138 */ 2139 per_pin = get_pin(spec, pcm_idx); 2140 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid); 2141 if (phantom_jack) 2142 strncat(hdmi_str, " Phantom", 2143 sizeof(hdmi_str) - strlen(hdmi_str) - 1); 2144 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 2145 phantom_jack, 0, NULL); 2146 if (ret < 0) 2147 return ret; 2148 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid); 2149 if (jack == NULL) 2150 return 0; 2151 /* assign jack->jack to pcm_rec[].jack to 2152 * align with dyn_pcm_assign mode 2153 */ 2154 spec->pcm_rec[pcm_idx].jack = jack->jack; 2155 return 0; 2156 } 2157 2158 static int generic_hdmi_build_controls(struct hda_codec *codec) 2159 { 2160 struct hdmi_spec *spec = codec->spec; 2161 int dev, err; 2162 int pin_idx, pcm_idx; 2163 2164 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2165 if (!get_pcm_rec(spec, pcm_idx)->pcm) { 2166 /* no PCM: mark this for skipping permanently */ 2167 set_bit(pcm_idx, &spec->pcm_bitmap); 2168 continue; 2169 } 2170 2171 err = generic_hdmi_build_jack(codec, pcm_idx); 2172 if (err < 0) 2173 return err; 2174 2175 /* create the spdif for each pcm 2176 * pin will be bound when monitor is connected 2177 */ 2178 if (spec->dyn_pcm_assign) 2179 err = snd_hda_create_dig_out_ctls(codec, 2180 0, spec->cvt_nids[0], 2181 HDA_PCM_TYPE_HDMI); 2182 else { 2183 struct hdmi_spec_per_pin *per_pin = 2184 get_pin(spec, pcm_idx); 2185 err = snd_hda_create_dig_out_ctls(codec, 2186 per_pin->pin_nid, 2187 per_pin->mux_nids[0], 2188 HDA_PCM_TYPE_HDMI); 2189 } 2190 if (err < 0) 2191 return err; 2192 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2193 2194 dev = get_pcm_rec(spec, pcm_idx)->device; 2195 if (dev != SNDRV_PCM_INVALID_DEVICE) { 2196 /* add control for ELD Bytes */ 2197 err = hdmi_create_eld_ctl(codec, pcm_idx, dev); 2198 if (err < 0) 2199 return err; 2200 } 2201 } 2202 2203 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2204 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2205 2206 hdmi_present_sense(per_pin, 0); 2207 } 2208 2209 /* add channel maps */ 2210 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2211 struct hda_pcm *pcm; 2212 2213 pcm = get_pcm_rec(spec, pcm_idx); 2214 if (!pcm || !pcm->pcm) 2215 break; 2216 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); 2217 if (err < 0) 2218 return err; 2219 } 2220 2221 return 0; 2222 } 2223 2224 static int generic_hdmi_init_per_pins(struct hda_codec *codec) 2225 { 2226 struct hdmi_spec *spec = codec->spec; 2227 int pin_idx; 2228 2229 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2230 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2231 2232 per_pin->codec = codec; 2233 mutex_init(&per_pin->lock); 2234 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); 2235 eld_proc_new(per_pin, pin_idx); 2236 } 2237 return 0; 2238 } 2239 2240 static int generic_hdmi_init(struct hda_codec *codec) 2241 { 2242 struct hdmi_spec *spec = codec->spec; 2243 int pin_idx; 2244 2245 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2246 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2247 hda_nid_t pin_nid = per_pin->pin_nid; 2248 int dev_id = per_pin->dev_id; 2249 2250 snd_hda_set_dev_select(codec, pin_nid, dev_id); 2251 hdmi_init_pin(codec, pin_nid); 2252 if (!codec_has_acomp(codec)) 2253 snd_hda_jack_detect_enable_callback(codec, pin_nid, 2254 codec->jackpoll_interval > 0 ? 2255 jack_callback : NULL); 2256 } 2257 return 0; 2258 } 2259 2260 static void hdmi_array_init(struct hdmi_spec *spec, int nums) 2261 { 2262 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); 2263 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); 2264 } 2265 2266 static void hdmi_array_free(struct hdmi_spec *spec) 2267 { 2268 snd_array_free(&spec->pins); 2269 snd_array_free(&spec->cvts); 2270 } 2271 2272 static void generic_spec_free(struct hda_codec *codec) 2273 { 2274 struct hdmi_spec *spec = codec->spec; 2275 2276 if (spec) { 2277 hdmi_array_free(spec); 2278 kfree(spec); 2279 codec->spec = NULL; 2280 } 2281 codec->dp_mst = false; 2282 } 2283 2284 static void generic_hdmi_free(struct hda_codec *codec) 2285 { 2286 struct hdmi_spec *spec = codec->spec; 2287 int pin_idx, pcm_idx; 2288 2289 if (codec_has_acomp(codec)) 2290 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL); 2291 2292 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2293 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2294 cancel_delayed_work_sync(&per_pin->work); 2295 eld_proc_free(per_pin); 2296 } 2297 2298 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2299 if (spec->pcm_rec[pcm_idx].jack == NULL) 2300 continue; 2301 if (spec->dyn_pcm_assign) 2302 snd_device_free(codec->card, 2303 spec->pcm_rec[pcm_idx].jack); 2304 else 2305 spec->pcm_rec[pcm_idx].jack = NULL; 2306 } 2307 2308 generic_spec_free(codec); 2309 } 2310 2311 #ifdef CONFIG_PM 2312 static int generic_hdmi_resume(struct hda_codec *codec) 2313 { 2314 struct hdmi_spec *spec = codec->spec; 2315 int pin_idx; 2316 2317 codec->patch_ops.init(codec); 2318 regcache_sync(codec->core.regmap); 2319 2320 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2321 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2322 hdmi_present_sense(per_pin, 1); 2323 } 2324 return 0; 2325 } 2326 #endif 2327 2328 static const struct hda_codec_ops generic_hdmi_patch_ops = { 2329 .init = generic_hdmi_init, 2330 .free = generic_hdmi_free, 2331 .build_pcms = generic_hdmi_build_pcms, 2332 .build_controls = generic_hdmi_build_controls, 2333 .unsol_event = hdmi_unsol_event, 2334 #ifdef CONFIG_PM 2335 .resume = generic_hdmi_resume, 2336 #endif 2337 }; 2338 2339 static const struct hdmi_ops generic_standard_hdmi_ops = { 2340 .pin_get_eld = snd_hdmi_get_eld, 2341 .pin_setup_infoframe = hdmi_pin_setup_infoframe, 2342 .pin_hbr_setup = hdmi_pin_hbr_setup, 2343 .setup_stream = hdmi_setup_stream, 2344 }; 2345 2346 /* allocate codec->spec and assign/initialize generic parser ops */ 2347 static int alloc_generic_hdmi(struct hda_codec *codec) 2348 { 2349 struct hdmi_spec *spec; 2350 2351 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2352 if (!spec) 2353 return -ENOMEM; 2354 2355 spec->ops = generic_standard_hdmi_ops; 2356 spec->dev_num = 1; /* initialize to 1 */ 2357 mutex_init(&spec->pcm_lock); 2358 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); 2359 2360 spec->chmap.ops.get_chmap = hdmi_get_chmap; 2361 spec->chmap.ops.set_chmap = hdmi_set_chmap; 2362 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; 2363 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc, 2364 2365 codec->spec = spec; 2366 hdmi_array_init(spec, 4); 2367 2368 codec->patch_ops = generic_hdmi_patch_ops; 2369 2370 return 0; 2371 } 2372 2373 /* generic HDMI parser */ 2374 static int patch_generic_hdmi(struct hda_codec *codec) 2375 { 2376 int err; 2377 2378 err = alloc_generic_hdmi(codec); 2379 if (err < 0) 2380 return err; 2381 2382 err = hdmi_parse_codec(codec); 2383 if (err < 0) { 2384 generic_spec_free(codec); 2385 return err; 2386 } 2387 2388 generic_hdmi_init_per_pins(codec); 2389 return 0; 2390 } 2391 2392 /* 2393 * Intel codec parsers and helpers 2394 */ 2395 2396 static void intel_haswell_fixup_connect_list(struct hda_codec *codec, 2397 hda_nid_t nid) 2398 { 2399 struct hdmi_spec *spec = codec->spec; 2400 hda_nid_t conns[4]; 2401 int nconns; 2402 2403 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns)); 2404 if (nconns == spec->num_cvts && 2405 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t))) 2406 return; 2407 2408 /* override pins connection list */ 2409 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid); 2410 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids); 2411 } 2412 2413 #define INTEL_VENDOR_NID 0x08 2414 #define INTEL_GLK_VENDOR_NID 0x0B 2415 #define INTEL_GET_VENDOR_VERB 0xf81 2416 #define INTEL_SET_VENDOR_VERB 0x781 2417 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ 2418 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ 2419 2420 static void intel_haswell_enable_all_pins(struct hda_codec *codec, 2421 bool update_tree) 2422 { 2423 unsigned int vendor_param; 2424 struct hdmi_spec *spec = codec->spec; 2425 2426 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2427 INTEL_GET_VENDOR_VERB, 0); 2428 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) 2429 return; 2430 2431 vendor_param |= INTEL_EN_ALL_PIN_CVTS; 2432 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2433 INTEL_SET_VENDOR_VERB, vendor_param); 2434 if (vendor_param == -1) 2435 return; 2436 2437 if (update_tree) 2438 snd_hda_codec_update_widgets(codec); 2439 } 2440 2441 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) 2442 { 2443 unsigned int vendor_param; 2444 struct hdmi_spec *spec = codec->spec; 2445 2446 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2447 INTEL_GET_VENDOR_VERB, 0); 2448 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) 2449 return; 2450 2451 /* enable DP1.2 mode */ 2452 vendor_param |= INTEL_EN_DP12; 2453 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); 2454 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, 2455 INTEL_SET_VENDOR_VERB, vendor_param); 2456 } 2457 2458 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. 2459 * Otherwise you may get severe h/w communication errors. 2460 */ 2461 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, 2462 unsigned int power_state) 2463 { 2464 if (power_state == AC_PWRST_D0) { 2465 intel_haswell_enable_all_pins(codec, false); 2466 intel_haswell_fixup_enable_dp12(codec); 2467 } 2468 2469 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); 2470 snd_hda_codec_set_power_to_all(codec, fg, power_state); 2471 } 2472 2473 /* There is a fixed mapping between audio pin node and display port. 2474 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL: 2475 * Pin Widget 5 - PORT B (port = 1 in i915 driver) 2476 * Pin Widget 6 - PORT C (port = 2 in i915 driver) 2477 * Pin Widget 7 - PORT D (port = 3 in i915 driver) 2478 * 2479 * on VLV, ILK: 2480 * Pin Widget 4 - PORT B (port = 1 in i915 driver) 2481 * Pin Widget 5 - PORT C (port = 2 in i915 driver) 2482 * Pin Widget 6 - PORT D (port = 3 in i915 driver) 2483 */ 2484 static int intel_base_nid(struct hda_codec *codec) 2485 { 2486 switch (codec->core.vendor_id) { 2487 case 0x80860054: /* ILK */ 2488 case 0x80862804: /* ILK */ 2489 case 0x80862882: /* VLV */ 2490 return 4; 2491 default: 2492 return 5; 2493 } 2494 } 2495 2496 static int intel_pin2port(void *audio_ptr, int pin_nid) 2497 { 2498 int base_nid = intel_base_nid(audio_ptr); 2499 2500 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3)) 2501 return -1; 2502 return pin_nid - base_nid + 1; /* intel port is 1-based */ 2503 } 2504 2505 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) 2506 { 2507 struct hda_codec *codec = audio_ptr; 2508 int pin_nid; 2509 int dev_id = pipe; 2510 2511 /* we assume only from port-B to port-D */ 2512 if (port < 1 || port > 3) 2513 return; 2514 2515 pin_nid = port + intel_base_nid(codec) - 1; /* intel port is 1-based */ 2516 2517 /* skip notification during system suspend (but not in runtime PM); 2518 * the state will be updated at resume 2519 */ 2520 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) 2521 return; 2522 /* ditto during suspend/resume process itself */ 2523 if (snd_hdac_is_in_pm(&codec->core)) 2524 return; 2525 2526 snd_hdac_i915_set_bclk(&codec->bus->core); 2527 check_presence_and_report(codec, pin_nid, dev_id); 2528 } 2529 2530 /* register i915 component pin_eld_notify callback */ 2531 static void register_i915_notifier(struct hda_codec *codec) 2532 { 2533 struct hdmi_spec *spec = codec->spec; 2534 2535 spec->use_acomp_notifier = true; 2536 spec->drm_audio_ops.audio_ptr = codec; 2537 /* intel_audio_codec_enable() or intel_audio_codec_disable() 2538 * will call pin_eld_notify with using audio_ptr pointer 2539 * We need make sure audio_ptr is really setup 2540 */ 2541 wmb(); 2542 spec->drm_audio_ops.pin2port = intel_pin2port; 2543 spec->drm_audio_ops.pin_eld_notify = intel_pin_eld_notify; 2544 snd_hdac_acomp_register_notifier(&codec->bus->core, 2545 &spec->drm_audio_ops); 2546 } 2547 2548 /* setup_stream ops override for HSW+ */ 2549 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 2550 hda_nid_t pin_nid, u32 stream_tag, int format) 2551 { 2552 haswell_verify_D0(codec, cvt_nid, pin_nid); 2553 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format); 2554 } 2555 2556 /* pin_cvt_fixup ops override for HSW+ and VLV+ */ 2557 static void i915_pin_cvt_fixup(struct hda_codec *codec, 2558 struct hdmi_spec_per_pin *per_pin, 2559 hda_nid_t cvt_nid) 2560 { 2561 if (per_pin) { 2562 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2563 per_pin->dev_id); 2564 intel_verify_pin_cvt_connect(codec, per_pin); 2565 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, 2566 per_pin->dev_id, per_pin->mux_idx); 2567 } else { 2568 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); 2569 } 2570 } 2571 2572 /* precondition and allocation for Intel codecs */ 2573 static int alloc_intel_hdmi(struct hda_codec *codec) 2574 { 2575 /* requires i915 binding */ 2576 if (!codec->bus->core.audio_component) { 2577 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); 2578 /* set probe_id here to prevent generic fallback binding */ 2579 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE; 2580 return -ENODEV; 2581 } 2582 2583 return alloc_generic_hdmi(codec); 2584 } 2585 2586 /* parse and post-process for Intel codecs */ 2587 static int parse_intel_hdmi(struct hda_codec *codec) 2588 { 2589 int err; 2590 2591 err = hdmi_parse_codec(codec); 2592 if (err < 0) { 2593 generic_spec_free(codec); 2594 return err; 2595 } 2596 2597 generic_hdmi_init_per_pins(codec); 2598 register_i915_notifier(codec); 2599 return 0; 2600 } 2601 2602 /* Intel Haswell and onwards; audio component with eld notifier */ 2603 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid) 2604 { 2605 struct hdmi_spec *spec; 2606 int err; 2607 2608 err = alloc_intel_hdmi(codec); 2609 if (err < 0) 2610 return err; 2611 spec = codec->spec; 2612 codec->dp_mst = true; 2613 spec->dyn_pcm_assign = true; 2614 spec->vendor_nid = vendor_nid; 2615 2616 intel_haswell_enable_all_pins(codec, true); 2617 intel_haswell_fixup_enable_dp12(codec); 2618 2619 codec->display_power_control = 1; 2620 2621 codec->patch_ops.set_power_state = haswell_set_power_state; 2622 codec->depop_delay = 0; 2623 codec->auto_runtime_pm = 1; 2624 2625 spec->ops.setup_stream = i915_hsw_setup_stream; 2626 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2627 2628 return parse_intel_hdmi(codec); 2629 } 2630 2631 static int patch_i915_hsw_hdmi(struct hda_codec *codec) 2632 { 2633 return intel_hsw_common_init(codec, INTEL_VENDOR_NID); 2634 } 2635 2636 static int patch_i915_glk_hdmi(struct hda_codec *codec) 2637 { 2638 return intel_hsw_common_init(codec, INTEL_GLK_VENDOR_NID); 2639 } 2640 2641 /* Intel Baytrail and Braswell; with eld notifier */ 2642 static int patch_i915_byt_hdmi(struct hda_codec *codec) 2643 { 2644 struct hdmi_spec *spec; 2645 int err; 2646 2647 err = alloc_intel_hdmi(codec); 2648 if (err < 0) 2649 return err; 2650 spec = codec->spec; 2651 2652 /* For Valleyview/Cherryview, only the display codec is in the display 2653 * power well and can use link_power ops to request/release the power. 2654 */ 2655 codec->display_power_control = 1; 2656 2657 codec->depop_delay = 0; 2658 codec->auto_runtime_pm = 1; 2659 2660 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2661 2662 return parse_intel_hdmi(codec); 2663 } 2664 2665 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ 2666 static int patch_i915_cpt_hdmi(struct hda_codec *codec) 2667 { 2668 int err; 2669 2670 err = alloc_intel_hdmi(codec); 2671 if (err < 0) 2672 return err; 2673 return parse_intel_hdmi(codec); 2674 } 2675 2676 /* 2677 * Shared non-generic implementations 2678 */ 2679 2680 static int simple_playback_build_pcms(struct hda_codec *codec) 2681 { 2682 struct hdmi_spec *spec = codec->spec; 2683 struct hda_pcm *info; 2684 unsigned int chans; 2685 struct hda_pcm_stream *pstr; 2686 struct hdmi_spec_per_cvt *per_cvt; 2687 2688 per_cvt = get_cvt(spec, 0); 2689 chans = get_wcaps(codec, per_cvt->cvt_nid); 2690 chans = get_wcaps_channels(chans); 2691 2692 info = snd_hda_codec_pcm_new(codec, "HDMI 0"); 2693 if (!info) 2694 return -ENOMEM; 2695 spec->pcm_rec[0].pcm = info; 2696 info->pcm_type = HDA_PCM_TYPE_HDMI; 2697 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2698 *pstr = spec->pcm_playback; 2699 pstr->nid = per_cvt->cvt_nid; 2700 if (pstr->channels_max <= 2 && chans && chans <= 16) 2701 pstr->channels_max = chans; 2702 2703 return 0; 2704 } 2705 2706 /* unsolicited event for jack sensing */ 2707 static void simple_hdmi_unsol_event(struct hda_codec *codec, 2708 unsigned int res) 2709 { 2710 snd_hda_jack_set_dirty_all(codec); 2711 snd_hda_jack_report_sync(codec); 2712 } 2713 2714 /* generic_hdmi_build_jack can be used for simple_hdmi, too, 2715 * as long as spec->pins[] is set correctly 2716 */ 2717 #define simple_hdmi_build_jack generic_hdmi_build_jack 2718 2719 static int simple_playback_build_controls(struct hda_codec *codec) 2720 { 2721 struct hdmi_spec *spec = codec->spec; 2722 struct hdmi_spec_per_cvt *per_cvt; 2723 int err; 2724 2725 per_cvt = get_cvt(spec, 0); 2726 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, 2727 per_cvt->cvt_nid, 2728 HDA_PCM_TYPE_HDMI); 2729 if (err < 0) 2730 return err; 2731 return simple_hdmi_build_jack(codec, 0); 2732 } 2733 2734 static int simple_playback_init(struct hda_codec *codec) 2735 { 2736 struct hdmi_spec *spec = codec->spec; 2737 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); 2738 hda_nid_t pin = per_pin->pin_nid; 2739 2740 snd_hda_codec_write(codec, pin, 0, 2741 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); 2742 /* some codecs require to unmute the pin */ 2743 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 2744 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, 2745 AMP_OUT_UNMUTE); 2746 snd_hda_jack_detect_enable(codec, pin); 2747 return 0; 2748 } 2749 2750 static void simple_playback_free(struct hda_codec *codec) 2751 { 2752 struct hdmi_spec *spec = codec->spec; 2753 2754 hdmi_array_free(spec); 2755 kfree(spec); 2756 } 2757 2758 /* 2759 * Nvidia specific implementations 2760 */ 2761 2762 #define Nv_VERB_SET_Channel_Allocation 0xF79 2763 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A 2764 #define Nv_VERB_SET_Audio_Protection_On 0xF98 2765 #define Nv_VERB_SET_Audio_Protection_Off 0xF99 2766 2767 #define nvhdmi_master_con_nid_7x 0x04 2768 #define nvhdmi_master_pin_nid_7x 0x05 2769 2770 static const hda_nid_t nvhdmi_con_nids_7x[4] = { 2771 /*front, rear, clfe, rear_surr */ 2772 0x6, 0x8, 0xa, 0xc, 2773 }; 2774 2775 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { 2776 /* set audio protect on */ 2777 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 2778 /* enable digital output on pin widget */ 2779 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2780 {} /* terminator */ 2781 }; 2782 2783 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { 2784 /* set audio protect on */ 2785 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 2786 /* enable digital output on pin widget */ 2787 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2788 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2789 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2790 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2791 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2792 {} /* terminator */ 2793 }; 2794 2795 #ifdef LIMITED_RATE_FMT_SUPPORT 2796 /* support only the safe format and rate */ 2797 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 2798 #define SUPPORTED_MAXBPS 16 2799 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE 2800 #else 2801 /* support all rates and formats */ 2802 #define SUPPORTED_RATES \ 2803 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ 2804 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ 2805 SNDRV_PCM_RATE_192000) 2806 #define SUPPORTED_MAXBPS 24 2807 #define SUPPORTED_FORMATS \ 2808 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 2809 #endif 2810 2811 static int nvhdmi_7x_init_2ch(struct hda_codec *codec) 2812 { 2813 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); 2814 return 0; 2815 } 2816 2817 static int nvhdmi_7x_init_8ch(struct hda_codec *codec) 2818 { 2819 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); 2820 return 0; 2821 } 2822 2823 static const unsigned int channels_2_6_8[] = { 2824 2, 6, 8 2825 }; 2826 2827 static const unsigned int channels_2_8[] = { 2828 2, 8 2829 }; 2830 2831 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { 2832 .count = ARRAY_SIZE(channels_2_6_8), 2833 .list = channels_2_6_8, 2834 .mask = 0, 2835 }; 2836 2837 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { 2838 .count = ARRAY_SIZE(channels_2_8), 2839 .list = channels_2_8, 2840 .mask = 0, 2841 }; 2842 2843 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, 2844 struct hda_codec *codec, 2845 struct snd_pcm_substream *substream) 2846 { 2847 struct hdmi_spec *spec = codec->spec; 2848 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; 2849 2850 switch (codec->preset->vendor_id) { 2851 case 0x10de0002: 2852 case 0x10de0003: 2853 case 0x10de0005: 2854 case 0x10de0006: 2855 hw_constraints_channels = &hw_constraints_2_8_channels; 2856 break; 2857 case 0x10de0007: 2858 hw_constraints_channels = &hw_constraints_2_6_8_channels; 2859 break; 2860 default: 2861 break; 2862 } 2863 2864 if (hw_constraints_channels != NULL) { 2865 snd_pcm_hw_constraint_list(substream->runtime, 0, 2866 SNDRV_PCM_HW_PARAM_CHANNELS, 2867 hw_constraints_channels); 2868 } else { 2869 snd_pcm_hw_constraint_step(substream->runtime, 0, 2870 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 2871 } 2872 2873 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 2874 } 2875 2876 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, 2877 struct hda_codec *codec, 2878 struct snd_pcm_substream *substream) 2879 { 2880 struct hdmi_spec *spec = codec->spec; 2881 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 2882 } 2883 2884 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 2885 struct hda_codec *codec, 2886 unsigned int stream_tag, 2887 unsigned int format, 2888 struct snd_pcm_substream *substream) 2889 { 2890 struct hdmi_spec *spec = codec->spec; 2891 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 2892 stream_tag, format, substream); 2893 } 2894 2895 static const struct hda_pcm_stream simple_pcm_playback = { 2896 .substreams = 1, 2897 .channels_min = 2, 2898 .channels_max = 2, 2899 .ops = { 2900 .open = simple_playback_pcm_open, 2901 .close = simple_playback_pcm_close, 2902 .prepare = simple_playback_pcm_prepare 2903 }, 2904 }; 2905 2906 static const struct hda_codec_ops simple_hdmi_patch_ops = { 2907 .build_controls = simple_playback_build_controls, 2908 .build_pcms = simple_playback_build_pcms, 2909 .init = simple_playback_init, 2910 .free = simple_playback_free, 2911 .unsol_event = simple_hdmi_unsol_event, 2912 }; 2913 2914 static int patch_simple_hdmi(struct hda_codec *codec, 2915 hda_nid_t cvt_nid, hda_nid_t pin_nid) 2916 { 2917 struct hdmi_spec *spec; 2918 struct hdmi_spec_per_cvt *per_cvt; 2919 struct hdmi_spec_per_pin *per_pin; 2920 2921 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2922 if (!spec) 2923 return -ENOMEM; 2924 2925 codec->spec = spec; 2926 hdmi_array_init(spec, 1); 2927 2928 spec->multiout.num_dacs = 0; /* no analog */ 2929 spec->multiout.max_channels = 2; 2930 spec->multiout.dig_out_nid = cvt_nid; 2931 spec->num_cvts = 1; 2932 spec->num_pins = 1; 2933 per_pin = snd_array_new(&spec->pins); 2934 per_cvt = snd_array_new(&spec->cvts); 2935 if (!per_pin || !per_cvt) { 2936 simple_playback_free(codec); 2937 return -ENOMEM; 2938 } 2939 per_cvt->cvt_nid = cvt_nid; 2940 per_pin->pin_nid = pin_nid; 2941 spec->pcm_playback = simple_pcm_playback; 2942 2943 codec->patch_ops = simple_hdmi_patch_ops; 2944 2945 return 0; 2946 } 2947 2948 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, 2949 int channels) 2950 { 2951 unsigned int chanmask; 2952 int chan = channels ? (channels - 1) : 1; 2953 2954 switch (channels) { 2955 default: 2956 case 0: 2957 case 2: 2958 chanmask = 0x00; 2959 break; 2960 case 4: 2961 chanmask = 0x08; 2962 break; 2963 case 6: 2964 chanmask = 0x0b; 2965 break; 2966 case 8: 2967 chanmask = 0x13; 2968 break; 2969 } 2970 2971 /* Set the audio infoframe channel allocation and checksum fields. The 2972 * channel count is computed implicitly by the hardware. */ 2973 snd_hda_codec_write(codec, 0x1, 0, 2974 Nv_VERB_SET_Channel_Allocation, chanmask); 2975 2976 snd_hda_codec_write(codec, 0x1, 0, 2977 Nv_VERB_SET_Info_Frame_Checksum, 2978 (0x71 - chan - chanmask)); 2979 } 2980 2981 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, 2982 struct hda_codec *codec, 2983 struct snd_pcm_substream *substream) 2984 { 2985 struct hdmi_spec *spec = codec->spec; 2986 int i; 2987 2988 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 2989 0, AC_VERB_SET_CHANNEL_STREAMID, 0); 2990 for (i = 0; i < 4; i++) { 2991 /* set the stream id */ 2992 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 2993 AC_VERB_SET_CHANNEL_STREAMID, 0); 2994 /* set the stream format */ 2995 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 2996 AC_VERB_SET_STREAM_FORMAT, 0); 2997 } 2998 2999 /* The audio hardware sends a channel count of 0x7 (8ch) when all the 3000 * streams are disabled. */ 3001 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3002 3003 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3004 } 3005 3006 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, 3007 struct hda_codec *codec, 3008 unsigned int stream_tag, 3009 unsigned int format, 3010 struct snd_pcm_substream *substream) 3011 { 3012 int chs; 3013 unsigned int dataDCC2, channel_id; 3014 int i; 3015 struct hdmi_spec *spec = codec->spec; 3016 struct hda_spdif_out *spdif; 3017 struct hdmi_spec_per_cvt *per_cvt; 3018 3019 mutex_lock(&codec->spdif_mutex); 3020 per_cvt = get_cvt(spec, 0); 3021 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); 3022 3023 chs = substream->runtime->channels; 3024 3025 dataDCC2 = 0x2; 3026 3027 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ 3028 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) 3029 snd_hda_codec_write(codec, 3030 nvhdmi_master_con_nid_7x, 3031 0, 3032 AC_VERB_SET_DIGI_CONVERT_1, 3033 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3034 3035 /* set the stream id */ 3036 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3037 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); 3038 3039 /* set the stream format */ 3040 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3041 AC_VERB_SET_STREAM_FORMAT, format); 3042 3043 /* turn on again (if needed) */ 3044 /* enable and set the channel status audio/data flag */ 3045 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { 3046 snd_hda_codec_write(codec, 3047 nvhdmi_master_con_nid_7x, 3048 0, 3049 AC_VERB_SET_DIGI_CONVERT_1, 3050 spdif->ctls & 0xff); 3051 snd_hda_codec_write(codec, 3052 nvhdmi_master_con_nid_7x, 3053 0, 3054 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3055 } 3056 3057 for (i = 0; i < 4; i++) { 3058 if (chs == 2) 3059 channel_id = 0; 3060 else 3061 channel_id = i * 2; 3062 3063 /* turn off SPDIF once; 3064 *otherwise the IEC958 bits won't be updated 3065 */ 3066 if (codec->spdif_status_reset && 3067 (spdif->ctls & AC_DIG1_ENABLE)) 3068 snd_hda_codec_write(codec, 3069 nvhdmi_con_nids_7x[i], 3070 0, 3071 AC_VERB_SET_DIGI_CONVERT_1, 3072 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3073 /* set the stream id */ 3074 snd_hda_codec_write(codec, 3075 nvhdmi_con_nids_7x[i], 3076 0, 3077 AC_VERB_SET_CHANNEL_STREAMID, 3078 (stream_tag << 4) | channel_id); 3079 /* set the stream format */ 3080 snd_hda_codec_write(codec, 3081 nvhdmi_con_nids_7x[i], 3082 0, 3083 AC_VERB_SET_STREAM_FORMAT, 3084 format); 3085 /* turn on again (if needed) */ 3086 /* enable and set the channel status audio/data flag */ 3087 if (codec->spdif_status_reset && 3088 (spdif->ctls & AC_DIG1_ENABLE)) { 3089 snd_hda_codec_write(codec, 3090 nvhdmi_con_nids_7x[i], 3091 0, 3092 AC_VERB_SET_DIGI_CONVERT_1, 3093 spdif->ctls & 0xff); 3094 snd_hda_codec_write(codec, 3095 nvhdmi_con_nids_7x[i], 3096 0, 3097 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3098 } 3099 } 3100 3101 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); 3102 3103 mutex_unlock(&codec->spdif_mutex); 3104 return 0; 3105 } 3106 3107 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { 3108 .substreams = 1, 3109 .channels_min = 2, 3110 .channels_max = 8, 3111 .nid = nvhdmi_master_con_nid_7x, 3112 .rates = SUPPORTED_RATES, 3113 .maxbps = SUPPORTED_MAXBPS, 3114 .formats = SUPPORTED_FORMATS, 3115 .ops = { 3116 .open = simple_playback_pcm_open, 3117 .close = nvhdmi_8ch_7x_pcm_close, 3118 .prepare = nvhdmi_8ch_7x_pcm_prepare 3119 }, 3120 }; 3121 3122 static int patch_nvhdmi_2ch(struct hda_codec *codec) 3123 { 3124 struct hdmi_spec *spec; 3125 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, 3126 nvhdmi_master_pin_nid_7x); 3127 if (err < 0) 3128 return err; 3129 3130 codec->patch_ops.init = nvhdmi_7x_init_2ch; 3131 /* override the PCM rates, etc, as the codec doesn't give full list */ 3132 spec = codec->spec; 3133 spec->pcm_playback.rates = SUPPORTED_RATES; 3134 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; 3135 spec->pcm_playback.formats = SUPPORTED_FORMATS; 3136 return 0; 3137 } 3138 3139 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) 3140 { 3141 struct hdmi_spec *spec = codec->spec; 3142 int err = simple_playback_build_pcms(codec); 3143 if (!err) { 3144 struct hda_pcm *info = get_pcm_rec(spec, 0); 3145 info->own_chmap = true; 3146 } 3147 return err; 3148 } 3149 3150 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) 3151 { 3152 struct hdmi_spec *spec = codec->spec; 3153 struct hda_pcm *info; 3154 struct snd_pcm_chmap *chmap; 3155 int err; 3156 3157 err = simple_playback_build_controls(codec); 3158 if (err < 0) 3159 return err; 3160 3161 /* add channel maps */ 3162 info = get_pcm_rec(spec, 0); 3163 err = snd_pcm_add_chmap_ctls(info->pcm, 3164 SNDRV_PCM_STREAM_PLAYBACK, 3165 snd_pcm_alt_chmaps, 8, 0, &chmap); 3166 if (err < 0) 3167 return err; 3168 switch (codec->preset->vendor_id) { 3169 case 0x10de0002: 3170 case 0x10de0003: 3171 case 0x10de0005: 3172 case 0x10de0006: 3173 chmap->channel_mask = (1U << 2) | (1U << 8); 3174 break; 3175 case 0x10de0007: 3176 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); 3177 } 3178 return 0; 3179 } 3180 3181 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) 3182 { 3183 struct hdmi_spec *spec; 3184 int err = patch_nvhdmi_2ch(codec); 3185 if (err < 0) 3186 return err; 3187 spec = codec->spec; 3188 spec->multiout.max_channels = 8; 3189 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; 3190 codec->patch_ops.init = nvhdmi_7x_init_8ch; 3191 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; 3192 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; 3193 3194 /* Initialize the audio infoframe channel mask and checksum to something 3195 * valid */ 3196 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3197 3198 return 0; 3199 } 3200 3201 /* 3202 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: 3203 * - 0x10de0015 3204 * - 0x10de0040 3205 */ 3206 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, 3207 struct hdac_cea_channel_speaker_allocation *cap, int channels) 3208 { 3209 if (cap->ca_index == 0x00 && channels == 2) 3210 return SNDRV_CTL_TLVT_CHMAP_FIXED; 3211 3212 /* If the speaker allocation matches the channel count, it is OK. */ 3213 if (cap->channels != channels) 3214 return -1; 3215 3216 /* all channels are remappable freely */ 3217 return SNDRV_CTL_TLVT_CHMAP_VAR; 3218 } 3219 3220 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, 3221 int ca, int chs, unsigned char *map) 3222 { 3223 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) 3224 return -EINVAL; 3225 3226 return 0; 3227 } 3228 3229 static int patch_nvhdmi(struct hda_codec *codec) 3230 { 3231 struct hdmi_spec *spec; 3232 int err; 3233 3234 err = patch_generic_hdmi(codec); 3235 if (err) 3236 return err; 3237 3238 spec = codec->spec; 3239 spec->dyn_pin_out = true; 3240 3241 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3242 nvhdmi_chmap_cea_alloc_validate_get_type; 3243 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3244 3245 return 0; 3246 } 3247 3248 /* 3249 * The HDA codec on NVIDIA Tegra contains two scratch registers that are 3250 * accessed using vendor-defined verbs. These registers can be used for 3251 * interoperability between the HDA and HDMI drivers. 3252 */ 3253 3254 /* Audio Function Group node */ 3255 #define NVIDIA_AFG_NID 0x01 3256 3257 /* 3258 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio 3259 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to 3260 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This 3261 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an 3262 * additional bit (at position 30) to signal the validity of the format. 3263 * 3264 * | 31 | 30 | 29 16 | 15 0 | 3265 * +---------+-------+--------+--------+ 3266 * | TRIGGER | VALID | UNUSED | FORMAT | 3267 * +-----------------------------------| 3268 * 3269 * Note that for the trigger bit to take effect it needs to change value 3270 * (i.e. it needs to be toggled). 3271 */ 3272 #define NVIDIA_GET_SCRATCH0 0xfa6 3273 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 3274 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 3275 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 3276 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa 3277 #define NVIDIA_SCRATCH_TRIGGER (1 << 7) 3278 #define NVIDIA_SCRATCH_VALID (1 << 6) 3279 3280 #define NVIDIA_GET_SCRATCH1 0xfab 3281 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac 3282 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad 3283 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae 3284 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf 3285 3286 /* 3287 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, 3288 * the format is invalidated so that the HDMI codec can be disabled. 3289 */ 3290 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format) 3291 { 3292 unsigned int value; 3293 3294 /* bits [31:30] contain the trigger and valid bits */ 3295 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0, 3296 NVIDIA_GET_SCRATCH0, 0); 3297 value = (value >> 24) & 0xff; 3298 3299 /* bits [15:0] are used to store the HDA format */ 3300 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3301 NVIDIA_SET_SCRATCH0_BYTE0, 3302 (format >> 0) & 0xff); 3303 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3304 NVIDIA_SET_SCRATCH0_BYTE1, 3305 (format >> 8) & 0xff); 3306 3307 /* bits [16:24] are unused */ 3308 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3309 NVIDIA_SET_SCRATCH0_BYTE2, 0); 3310 3311 /* 3312 * Bit 30 signals that the data is valid and hence that HDMI audio can 3313 * be enabled. 3314 */ 3315 if (format == 0) 3316 value &= ~NVIDIA_SCRATCH_VALID; 3317 else 3318 value |= NVIDIA_SCRATCH_VALID; 3319 3320 /* 3321 * Whenever the trigger bit is toggled, an interrupt is raised in the 3322 * HDMI codec. The HDMI driver will use that as trigger to update its 3323 * configuration. 3324 */ 3325 value ^= NVIDIA_SCRATCH_TRIGGER; 3326 3327 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3328 NVIDIA_SET_SCRATCH0_BYTE3, value); 3329 } 3330 3331 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, 3332 struct hda_codec *codec, 3333 unsigned int stream_tag, 3334 unsigned int format, 3335 struct snd_pcm_substream *substream) 3336 { 3337 int err; 3338 3339 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, 3340 format, substream); 3341 if (err < 0) 3342 return err; 3343 3344 /* notify the HDMI codec of the format change */ 3345 tegra_hdmi_set_format(codec, format); 3346 3347 return 0; 3348 } 3349 3350 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, 3351 struct hda_codec *codec, 3352 struct snd_pcm_substream *substream) 3353 { 3354 /* invalidate the format in the HDMI codec */ 3355 tegra_hdmi_set_format(codec, 0); 3356 3357 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); 3358 } 3359 3360 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) 3361 { 3362 struct hdmi_spec *spec = codec->spec; 3363 unsigned int i; 3364 3365 for (i = 0; i < spec->num_pins; i++) { 3366 struct hda_pcm *pcm = get_pcm_rec(spec, i); 3367 3368 if (pcm->pcm_type == type) 3369 return pcm; 3370 } 3371 3372 return NULL; 3373 } 3374 3375 static int tegra_hdmi_build_pcms(struct hda_codec *codec) 3376 { 3377 struct hda_pcm_stream *stream; 3378 struct hda_pcm *pcm; 3379 int err; 3380 3381 err = generic_hdmi_build_pcms(codec); 3382 if (err < 0) 3383 return err; 3384 3385 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); 3386 if (!pcm) 3387 return -ENODEV; 3388 3389 /* 3390 * Override ->prepare() and ->cleanup() operations to notify the HDMI 3391 * codec about format changes. 3392 */ 3393 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3394 stream->ops.prepare = tegra_hdmi_pcm_prepare; 3395 stream->ops.cleanup = tegra_hdmi_pcm_cleanup; 3396 3397 return 0; 3398 } 3399 3400 static int patch_tegra_hdmi(struct hda_codec *codec) 3401 { 3402 int err; 3403 3404 err = patch_generic_hdmi(codec); 3405 if (err) 3406 return err; 3407 3408 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; 3409 3410 return 0; 3411 } 3412 3413 /* 3414 * ATI/AMD-specific implementations 3415 */ 3416 3417 #define is_amdhdmi_rev3_or_later(codec) \ 3418 ((codec)->core.vendor_id == 0x1002aa01 && \ 3419 ((codec)->core.revision_id & 0xff00) >= 0x0300) 3420 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) 3421 3422 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ 3423 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 3424 #define ATI_VERB_SET_DOWNMIX_INFO 0x772 3425 #define ATI_VERB_SET_MULTICHANNEL_01 0x777 3426 #define ATI_VERB_SET_MULTICHANNEL_23 0x778 3427 #define ATI_VERB_SET_MULTICHANNEL_45 0x779 3428 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a 3429 #define ATI_VERB_SET_HBR_CONTROL 0x77c 3430 #define ATI_VERB_SET_MULTICHANNEL_1 0x785 3431 #define ATI_VERB_SET_MULTICHANNEL_3 0x786 3432 #define ATI_VERB_SET_MULTICHANNEL_5 0x787 3433 #define ATI_VERB_SET_MULTICHANNEL_7 0x788 3434 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 3435 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 3436 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 3437 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 3438 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 3439 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 3440 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a 3441 #define ATI_VERB_GET_HBR_CONTROL 0xf7c 3442 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 3443 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 3444 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 3445 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 3446 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 3447 3448 /* AMD specific HDA cvt verbs */ 3449 #define ATI_VERB_SET_RAMP_RATE 0x770 3450 #define ATI_VERB_GET_RAMP_RATE 0xf70 3451 3452 #define ATI_OUT_ENABLE 0x1 3453 3454 #define ATI_MULTICHANNEL_MODE_PAIRED 0 3455 #define ATI_MULTICHANNEL_MODE_SINGLE 1 3456 3457 #define ATI_HBR_CAPABLE 0x01 3458 #define ATI_HBR_ENABLE 0x10 3459 3460 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 3461 unsigned char *buf, int *eld_size) 3462 { 3463 /* call hda_eld.c ATI/AMD-specific function */ 3464 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, 3465 is_amdhdmi_rev3_or_later(codec)); 3466 } 3467 3468 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca, 3469 int active_channels, int conn_type) 3470 { 3471 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); 3472 } 3473 3474 static int atihdmi_paired_swap_fc_lfe(int pos) 3475 { 3476 /* 3477 * ATI/AMD have automatic FC/LFE swap built-in 3478 * when in pairwise mapping mode. 3479 */ 3480 3481 switch (pos) { 3482 /* see channel_allocations[].speakers[] */ 3483 case 2: return 3; 3484 case 3: return 2; 3485 default: break; 3486 } 3487 3488 return pos; 3489 } 3490 3491 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, 3492 int ca, int chs, unsigned char *map) 3493 { 3494 struct hdac_cea_channel_speaker_allocation *cap; 3495 int i, j; 3496 3497 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ 3498 3499 cap = snd_hdac_get_ch_alloc_from_ca(ca); 3500 for (i = 0; i < chs; ++i) { 3501 int mask = snd_hdac_chmap_to_spk_mask(map[i]); 3502 bool ok = false; 3503 bool companion_ok = false; 3504 3505 if (!mask) 3506 continue; 3507 3508 for (j = 0 + i % 2; j < 8; j += 2) { 3509 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); 3510 if (cap->speakers[chan_idx] == mask) { 3511 /* channel is in a supported position */ 3512 ok = true; 3513 3514 if (i % 2 == 0 && i + 1 < chs) { 3515 /* even channel, check the odd companion */ 3516 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); 3517 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); 3518 int comp_mask_act = cap->speakers[comp_chan_idx]; 3519 3520 if (comp_mask_req == comp_mask_act) 3521 companion_ok = true; 3522 else 3523 return -EINVAL; 3524 } 3525 break; 3526 } 3527 } 3528 3529 if (!ok) 3530 return -EINVAL; 3531 3532 if (companion_ok) 3533 i++; /* companion channel already checked */ 3534 } 3535 3536 return 0; 3537 } 3538 3539 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, 3540 hda_nid_t pin_nid, int hdmi_slot, int stream_channel) 3541 { 3542 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 3543 int verb; 3544 int ati_channel_setup = 0; 3545 3546 if (hdmi_slot > 7) 3547 return -EINVAL; 3548 3549 if (!has_amd_full_remap_support(codec)) { 3550 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); 3551 3552 /* In case this is an odd slot but without stream channel, do not 3553 * disable the slot since the corresponding even slot could have a 3554 * channel. In case neither have a channel, the slot pair will be 3555 * disabled when this function is called for the even slot. */ 3556 if (hdmi_slot % 2 != 0 && stream_channel == 0xf) 3557 return 0; 3558 3559 hdmi_slot -= hdmi_slot % 2; 3560 3561 if (stream_channel != 0xf) 3562 stream_channel -= stream_channel % 2; 3563 } 3564 3565 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; 3566 3567 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ 3568 3569 if (stream_channel != 0xf) 3570 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; 3571 3572 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); 3573 } 3574 3575 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, 3576 hda_nid_t pin_nid, int asp_slot) 3577 { 3578 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 3579 bool was_odd = false; 3580 int ati_asp_slot = asp_slot; 3581 int verb; 3582 int ati_channel_setup; 3583 3584 if (asp_slot > 7) 3585 return -EINVAL; 3586 3587 if (!has_amd_full_remap_support(codec)) { 3588 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); 3589 if (ati_asp_slot % 2 != 0) { 3590 ati_asp_slot -= 1; 3591 was_odd = true; 3592 } 3593 } 3594 3595 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; 3596 3597 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); 3598 3599 if (!(ati_channel_setup & ATI_OUT_ENABLE)) 3600 return 0xf; 3601 3602 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; 3603 } 3604 3605 static int atihdmi_paired_chmap_cea_alloc_validate_get_type( 3606 struct hdac_chmap *chmap, 3607 struct hdac_cea_channel_speaker_allocation *cap, 3608 int channels) 3609 { 3610 int c; 3611 3612 /* 3613 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so 3614 * we need to take that into account (a single channel may take 2 3615 * channel slots if we need to carry a silent channel next to it). 3616 * On Rev3+ AMD codecs this function is not used. 3617 */ 3618 int chanpairs = 0; 3619 3620 /* We only produce even-numbered channel count TLVs */ 3621 if ((channels % 2) != 0) 3622 return -1; 3623 3624 for (c = 0; c < 7; c += 2) { 3625 if (cap->speakers[c] || cap->speakers[c+1]) 3626 chanpairs++; 3627 } 3628 3629 if (chanpairs * 2 != channels) 3630 return -1; 3631 3632 return SNDRV_CTL_TLVT_CHMAP_PAIRED; 3633 } 3634 3635 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, 3636 struct hdac_cea_channel_speaker_allocation *cap, 3637 unsigned int *chmap, int channels) 3638 { 3639 /* produce paired maps for pre-rev3 ATI/AMD codecs */ 3640 int count = 0; 3641 int c; 3642 3643 for (c = 7; c >= 0; c--) { 3644 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); 3645 int spk = cap->speakers[chan]; 3646 if (!spk) { 3647 /* add N/A channel if the companion channel is occupied */ 3648 if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) 3649 chmap[count++] = SNDRV_CHMAP_NA; 3650 3651 continue; 3652 } 3653 3654 chmap[count++] = snd_hdac_spk_to_chmap(spk); 3655 } 3656 3657 WARN_ON(count != channels); 3658 } 3659 3660 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 3661 bool hbr) 3662 { 3663 int hbr_ctl, hbr_ctl_new; 3664 3665 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); 3666 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { 3667 if (hbr) 3668 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; 3669 else 3670 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; 3671 3672 codec_dbg(codec, 3673 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", 3674 pin_nid, 3675 hbr_ctl == hbr_ctl_new ? "" : "new-", 3676 hbr_ctl_new); 3677 3678 if (hbr_ctl != hbr_ctl_new) 3679 snd_hda_codec_write(codec, pin_nid, 0, 3680 ATI_VERB_SET_HBR_CONTROL, 3681 hbr_ctl_new); 3682 3683 } else if (hbr) 3684 return -EINVAL; 3685 3686 return 0; 3687 } 3688 3689 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 3690 hda_nid_t pin_nid, u32 stream_tag, int format) 3691 { 3692 3693 if (is_amdhdmi_rev3_or_later(codec)) { 3694 int ramp_rate = 180; /* default as per AMD spec */ 3695 /* disable ramp-up/down for non-pcm as per AMD spec */ 3696 if (format & AC_FMT_TYPE_NON_PCM) 3697 ramp_rate = 0; 3698 3699 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); 3700 } 3701 3702 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format); 3703 } 3704 3705 3706 static int atihdmi_init(struct hda_codec *codec) 3707 { 3708 struct hdmi_spec *spec = codec->spec; 3709 int pin_idx, err; 3710 3711 err = generic_hdmi_init(codec); 3712 3713 if (err) 3714 return err; 3715 3716 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 3717 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 3718 3719 /* make sure downmix information in infoframe is zero */ 3720 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); 3721 3722 /* enable channel-wise remap mode if supported */ 3723 if (has_amd_full_remap_support(codec)) 3724 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 3725 ATI_VERB_SET_MULTICHANNEL_MODE, 3726 ATI_MULTICHANNEL_MODE_SINGLE); 3727 } 3728 3729 return 0; 3730 } 3731 3732 static int patch_atihdmi(struct hda_codec *codec) 3733 { 3734 struct hdmi_spec *spec; 3735 struct hdmi_spec_per_cvt *per_cvt; 3736 int err, cvt_idx; 3737 3738 err = patch_generic_hdmi(codec); 3739 3740 if (err) 3741 return err; 3742 3743 codec->patch_ops.init = atihdmi_init; 3744 3745 spec = codec->spec; 3746 3747 spec->ops.pin_get_eld = atihdmi_pin_get_eld; 3748 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; 3749 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; 3750 spec->ops.setup_stream = atihdmi_setup_stream; 3751 3752 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; 3753 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; 3754 3755 if (!has_amd_full_remap_support(codec)) { 3756 /* override to ATI/AMD-specific versions with pairwise mapping */ 3757 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3758 atihdmi_paired_chmap_cea_alloc_validate_get_type; 3759 spec->chmap.ops.cea_alloc_to_tlv_chmap = 3760 atihdmi_paired_cea_alloc_to_tlv_chmap; 3761 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; 3762 } 3763 3764 /* ATI/AMD converters do not advertise all of their capabilities */ 3765 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 3766 per_cvt = get_cvt(spec, cvt_idx); 3767 per_cvt->channels_max = max(per_cvt->channels_max, 8u); 3768 per_cvt->rates |= SUPPORTED_RATES; 3769 per_cvt->formats |= SUPPORTED_FORMATS; 3770 per_cvt->maxbps = max(per_cvt->maxbps, 24u); 3771 } 3772 3773 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); 3774 3775 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing 3776 * the link-down as is. Tell the core to allow it. 3777 */ 3778 codec->link_down_at_suspend = 1; 3779 3780 return 0; 3781 } 3782 3783 /* VIA HDMI Implementation */ 3784 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ 3785 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ 3786 3787 static int patch_via_hdmi(struct hda_codec *codec) 3788 { 3789 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); 3790 } 3791 3792 /* 3793 * patch entries 3794 */ 3795 static const struct hda_device_id snd_hda_id_hdmi[] = { 3796 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), 3797 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), 3798 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), 3799 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), 3800 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), 3801 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), 3802 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), 3803 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch), 3804 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 3805 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 3806 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x), 3807 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 3808 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 3809 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), 3810 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi), 3811 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi), 3812 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi), 3813 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi), 3814 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi), 3815 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi), 3816 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi), 3817 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi), 3818 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi), 3819 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi), 3820 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi), 3821 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi), 3822 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi), 3823 /* 17 is known to be absent */ 3824 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi), 3825 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi), 3826 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi), 3827 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi), 3828 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi), 3829 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), 3830 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), 3831 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), 3832 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), 3833 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi), 3834 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi), 3835 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), 3836 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), 3837 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), 3838 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), 3839 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), 3840 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), 3841 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), 3842 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi), 3843 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi), 3844 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), 3845 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi), 3846 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), 3847 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi), 3848 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi), 3849 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), 3850 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), 3851 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), 3852 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), 3853 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi), 3854 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi), 3855 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi), 3856 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi), 3857 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi), 3858 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), 3859 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi), 3860 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), 3861 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi), 3862 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), 3863 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), 3864 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi), 3865 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi), 3866 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi), 3867 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi), 3868 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi), 3869 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi), 3870 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi), 3871 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi), 3872 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), 3873 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), 3874 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), 3875 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), 3876 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), 3877 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), 3878 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), 3879 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), 3880 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), 3881 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), 3882 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), 3883 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), 3884 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), 3885 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), 3886 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), 3887 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), 3888 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), 3889 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), 3890 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), 3891 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), 3892 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), 3893 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), 3894 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), 3895 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), 3896 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), 3897 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), 3898 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), 3899 /* special ID for generic HDMI */ 3900 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), 3901 {} /* terminator */ 3902 }; 3903 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); 3904 3905 MODULE_LICENSE("GPL"); 3906 MODULE_DESCRIPTION("HDMI HD-audio codec"); 3907 MODULE_ALIAS("snd-hda-codec-intelhdmi"); 3908 MODULE_ALIAS("snd-hda-codec-nvhdmi"); 3909 MODULE_ALIAS("snd-hda-codec-atihdmi"); 3910 3911 static struct hda_codec_driver hdmi_driver = { 3912 .id = snd_hda_id_hdmi, 3913 }; 3914 3915 module_hda_codec_driver(hdmi_driver); 3916