1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs 5 * 6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. 7 * Copyright (c) 2006 ATI Technologies Inc. 8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved. 9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com> 10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> 11 * 12 * Authors: 13 * Wu Fengguang <wfg@linux.intel.com> 14 * 15 * Maintained by: 16 * Wu Fengguang <wfg@linux.intel.com> 17 */ 18 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/pci.h> 22 #include <linux/slab.h> 23 #include <linux/module.h> 24 #include <linux/pm_runtime.h> 25 #include <sound/core.h> 26 #include <sound/jack.h> 27 #include <sound/asoundef.h> 28 #include <sound/tlv.h> 29 #include <sound/hdaudio.h> 30 #include <sound/hda_i915.h> 31 #include <sound/hda_chmap.h> 32 #include <sound/hda_codec.h> 33 #include "hda_local.h" 34 #include "hda_jack.h" 35 #include "hda_controller.h" 36 37 static bool static_hdmi_pcm; 38 module_param(static_hdmi_pcm, bool, 0644); 39 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); 40 41 static bool enable_acomp = true; 42 module_param(enable_acomp, bool, 0444); 43 MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)"); 44 45 static bool enable_silent_stream = 46 IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM); 47 module_param(enable_silent_stream, bool, 0644); 48 MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices"); 49 50 static bool enable_all_pins; 51 module_param(enable_all_pins, bool, 0444); 52 MODULE_PARM_DESC(enable_all_pins, "Forcibly enable all pins"); 53 54 struct hdmi_spec_per_cvt { 55 hda_nid_t cvt_nid; 56 bool assigned; /* the stream has been assigned */ 57 bool silent_stream; /* silent stream activated */ 58 unsigned int channels_min; 59 unsigned int channels_max; 60 u32 rates; 61 u64 formats; 62 unsigned int maxbps; 63 }; 64 65 /* max. connections to a widget */ 66 #define HDA_MAX_CONNECTIONS 32 67 68 struct hdmi_spec_per_pin { 69 hda_nid_t pin_nid; 70 int dev_id; 71 /* pin idx, different device entries on the same pin use the same idx */ 72 int pin_nid_idx; 73 int num_mux_nids; 74 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; 75 int mux_idx; 76 hda_nid_t cvt_nid; 77 78 struct hda_codec *codec; 79 struct hdmi_eld sink_eld; 80 struct mutex lock; 81 struct delayed_work work; 82 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ 83 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ 84 int repoll_count; 85 bool setup; /* the stream has been set up by prepare callback */ 86 bool silent_stream; 87 int channels; /* current number of channels */ 88 bool non_pcm; 89 bool chmap_set; /* channel-map override by ALSA API? */ 90 unsigned char chmap[8]; /* ALSA API channel-map */ 91 #ifdef CONFIG_SND_PROC_FS 92 struct snd_info_entry *proc_entry; 93 #endif 94 }; 95 96 /* operations used by generic code that can be overridden by patches */ 97 struct hdmi_ops { 98 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, 99 int dev_id, unsigned char *buf, int *eld_size); 100 101 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, 102 int dev_id, 103 int ca, int active_channels, int conn_type); 104 105 /* enable/disable HBR (HD passthrough) */ 106 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, 107 int dev_id, bool hbr); 108 109 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, 110 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 111 int format); 112 113 void (*pin_cvt_fixup)(struct hda_codec *codec, 114 struct hdmi_spec_per_pin *per_pin, 115 hda_nid_t cvt_nid); 116 }; 117 118 struct hdmi_pcm { 119 struct hda_pcm *pcm; 120 struct snd_jack *jack; 121 struct snd_kcontrol *eld_ctl; 122 }; 123 124 enum { 125 SILENT_STREAM_OFF = 0, 126 SILENT_STREAM_KAE, /* use standard HDA Keep-Alive */ 127 SILENT_STREAM_I915, /* Intel i915 extension */ 128 }; 129 130 struct hdmi_spec { 131 struct hda_codec *codec; 132 int num_cvts; 133 struct snd_array cvts; /* struct hdmi_spec_per_cvt */ 134 hda_nid_t cvt_nids[4]; /* only for haswell fix */ 135 136 /* 137 * num_pins is the number of virtual pins 138 * for example, there are 3 pins, and each pin 139 * has 4 device entries, then the num_pins is 12 140 */ 141 int num_pins; 142 /* 143 * num_nids is the number of real pins 144 * In the above example, num_nids is 3 145 */ 146 int num_nids; 147 /* 148 * dev_num is the number of device entries 149 * on each pin. 150 * In the above example, dev_num is 4 151 */ 152 int dev_num; 153 struct snd_array pins; /* struct hdmi_spec_per_pin */ 154 struct hdmi_pcm pcm_rec[8]; 155 struct mutex pcm_lock; 156 struct mutex bind_lock; /* for audio component binding */ 157 /* pcm_bitmap means which pcms have been assigned to pins*/ 158 unsigned long pcm_bitmap; 159 int pcm_used; /* counter of pcm_rec[] */ 160 /* bitmap shows whether the pcm is opened in user space 161 * bit 0 means the first playback PCM (PCM3); 162 * bit 1 means the second playback PCM, and so on. 163 */ 164 unsigned long pcm_in_use; 165 166 struct hdmi_eld temp_eld; 167 struct hdmi_ops ops; 168 169 bool dyn_pin_out; 170 bool static_pcm_mapping; 171 /* hdmi interrupt trigger control flag for Nvidia codec */ 172 bool hdmi_intr_trig_ctrl; 173 bool nv_dp_workaround; /* workaround DP audio infoframe for Nvidia */ 174 175 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */ 176 /* 177 * Non-generic VIA/NVIDIA specific 178 */ 179 struct hda_multi_out multiout; 180 struct hda_pcm_stream pcm_playback; 181 182 bool use_acomp_notifier; /* use eld_notify callback for hotplug */ 183 bool acomp_registered; /* audio component registered in this driver */ 184 bool force_connect; /* force connectivity */ 185 struct drm_audio_component_audio_ops drm_audio_ops; 186 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */ 187 188 struct hdac_chmap chmap; 189 hda_nid_t vendor_nid; 190 const int *port_map; 191 int port_num; 192 int silent_stream_type; 193 }; 194 195 #ifdef CONFIG_SND_HDA_COMPONENT 196 static inline bool codec_has_acomp(struct hda_codec *codec) 197 { 198 struct hdmi_spec *spec = codec->spec; 199 return spec->use_acomp_notifier; 200 } 201 #else 202 #define codec_has_acomp(codec) false 203 #endif 204 205 struct hdmi_audio_infoframe { 206 u8 type; /* 0x84 */ 207 u8 ver; /* 0x01 */ 208 u8 len; /* 0x0a */ 209 210 u8 checksum; 211 212 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ 213 u8 SS01_SF24; 214 u8 CXT04; 215 u8 CA; 216 u8 LFEPBL01_LSV36_DM_INH7; 217 }; 218 219 struct dp_audio_infoframe { 220 u8 type; /* 0x84 */ 221 u8 len; /* 0x1b */ 222 u8 ver; /* 0x11 << 2 */ 223 224 u8 CC02_CT47; /* match with HDMI infoframe from this on */ 225 u8 SS01_SF24; 226 u8 CXT04; 227 u8 CA; 228 u8 LFEPBL01_LSV36_DM_INH7; 229 }; 230 231 union audio_infoframe { 232 struct hdmi_audio_infoframe hdmi; 233 struct dp_audio_infoframe dp; 234 DECLARE_FLEX_ARRAY(u8, bytes); 235 }; 236 237 /* 238 * HDMI routines 239 */ 240 241 #define get_pin(spec, idx) \ 242 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) 243 #define get_cvt(spec, idx) \ 244 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) 245 /* obtain hdmi_pcm object assigned to idx */ 246 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) 247 /* obtain hda_pcm object assigned to idx */ 248 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) 249 250 static int pin_id_to_pin_index(struct hda_codec *codec, 251 hda_nid_t pin_nid, int dev_id) 252 { 253 struct hdmi_spec *spec = codec->spec; 254 int pin_idx; 255 struct hdmi_spec_per_pin *per_pin; 256 257 /* 258 * (dev_id == -1) means it is NON-MST pin 259 * return the first virtual pin on this port 260 */ 261 if (dev_id == -1) 262 dev_id = 0; 263 264 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 265 per_pin = get_pin(spec, pin_idx); 266 if ((per_pin->pin_nid == pin_nid) && 267 (per_pin->dev_id == dev_id)) 268 return pin_idx; 269 } 270 271 codec_warn(codec, "HDMI: pin NID 0x%x not registered\n", pin_nid); 272 return -EINVAL; 273 } 274 275 static int hinfo_to_pcm_index(struct hda_codec *codec, 276 struct hda_pcm_stream *hinfo) 277 { 278 struct hdmi_spec *spec = codec->spec; 279 int pcm_idx; 280 281 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) 282 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) 283 return pcm_idx; 284 285 codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo); 286 return -EINVAL; 287 } 288 289 static int hinfo_to_pin_index(struct hda_codec *codec, 290 struct hda_pcm_stream *hinfo) 291 { 292 struct hdmi_spec *spec = codec->spec; 293 struct hdmi_spec_per_pin *per_pin; 294 int pin_idx; 295 296 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 297 per_pin = get_pin(spec, pin_idx); 298 if (per_pin->pcm && 299 per_pin->pcm->pcm->stream == hinfo) 300 return pin_idx; 301 } 302 303 codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo, 304 hinfo_to_pcm_index(codec, hinfo)); 305 return -EINVAL; 306 } 307 308 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, 309 int pcm_idx) 310 { 311 int i; 312 struct hdmi_spec_per_pin *per_pin; 313 314 for (i = 0; i < spec->num_pins; i++) { 315 per_pin = get_pin(spec, i); 316 if (per_pin->pcm_idx == pcm_idx) 317 return per_pin; 318 } 319 return NULL; 320 } 321 322 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) 323 { 324 struct hdmi_spec *spec = codec->spec; 325 int cvt_idx; 326 327 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) 328 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) 329 return cvt_idx; 330 331 codec_warn(codec, "HDMI: cvt NID 0x%x not registered\n", cvt_nid); 332 return -EINVAL; 333 } 334 335 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, 336 struct snd_ctl_elem_info *uinfo) 337 { 338 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 339 struct hdmi_spec *spec = codec->spec; 340 struct hdmi_spec_per_pin *per_pin; 341 struct hdmi_eld *eld; 342 int pcm_idx; 343 344 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 345 346 pcm_idx = kcontrol->private_value; 347 mutex_lock(&spec->pcm_lock); 348 per_pin = pcm_idx_to_pin(spec, pcm_idx); 349 if (!per_pin) { 350 /* no pin is bound to the pcm */ 351 uinfo->count = 0; 352 goto unlock; 353 } 354 eld = &per_pin->sink_eld; 355 uinfo->count = eld->eld_valid ? eld->eld_size : 0; 356 357 unlock: 358 mutex_unlock(&spec->pcm_lock); 359 return 0; 360 } 361 362 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, 363 struct snd_ctl_elem_value *ucontrol) 364 { 365 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 366 struct hdmi_spec *spec = codec->spec; 367 struct hdmi_spec_per_pin *per_pin; 368 struct hdmi_eld *eld; 369 int pcm_idx; 370 int err = 0; 371 372 pcm_idx = kcontrol->private_value; 373 mutex_lock(&spec->pcm_lock); 374 per_pin = pcm_idx_to_pin(spec, pcm_idx); 375 if (!per_pin) { 376 /* no pin is bound to the pcm */ 377 memset(ucontrol->value.bytes.data, 0, 378 ARRAY_SIZE(ucontrol->value.bytes.data)); 379 goto unlock; 380 } 381 382 eld = &per_pin->sink_eld; 383 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || 384 eld->eld_size > ELD_MAX_SIZE) { 385 snd_BUG(); 386 err = -EINVAL; 387 goto unlock; 388 } 389 390 memset(ucontrol->value.bytes.data, 0, 391 ARRAY_SIZE(ucontrol->value.bytes.data)); 392 if (eld->eld_valid) 393 memcpy(ucontrol->value.bytes.data, eld->eld_buffer, 394 eld->eld_size); 395 396 unlock: 397 mutex_unlock(&spec->pcm_lock); 398 return err; 399 } 400 401 static const struct snd_kcontrol_new eld_bytes_ctl = { 402 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE | 403 SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK, 404 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 405 .name = "ELD", 406 .info = hdmi_eld_ctl_info, 407 .get = hdmi_eld_ctl_get, 408 }; 409 410 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, 411 int device) 412 { 413 struct snd_kcontrol *kctl; 414 struct hdmi_spec *spec = codec->spec; 415 int err; 416 417 kctl = snd_ctl_new1(&eld_bytes_ctl, codec); 418 if (!kctl) 419 return -ENOMEM; 420 kctl->private_value = pcm_idx; 421 kctl->id.device = device; 422 423 /* no pin nid is associated with the kctl now 424 * tbd: associate pin nid to eld ctl later 425 */ 426 err = snd_hda_ctl_add(codec, 0, kctl); 427 if (err < 0) 428 return err; 429 430 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; 431 return 0; 432 } 433 434 #ifdef BE_PARANOID 435 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 436 int *packet_index, int *byte_index) 437 { 438 int val; 439 440 val = snd_hda_codec_read(codec, pin_nid, 0, 441 AC_VERB_GET_HDMI_DIP_INDEX, 0); 442 443 *packet_index = val >> 5; 444 *byte_index = val & 0x1f; 445 } 446 #endif 447 448 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 449 int packet_index, int byte_index) 450 { 451 int val; 452 453 val = (packet_index << 5) | (byte_index & 0x1f); 454 455 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); 456 } 457 458 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, 459 unsigned char val) 460 { 461 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); 462 } 463 464 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) 465 { 466 struct hdmi_spec *spec = codec->spec; 467 int pin_out; 468 469 /* Unmute */ 470 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 471 snd_hda_codec_write(codec, pin_nid, 0, 472 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); 473 474 if (spec->dyn_pin_out) 475 /* Disable pin out until stream is active */ 476 pin_out = 0; 477 else 478 /* Enable pin out: some machines with GM965 gets broken output 479 * when the pin is disabled or changed while using with HDMI 480 */ 481 pin_out = PIN_OUT; 482 483 snd_hda_codec_write(codec, pin_nid, 0, 484 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); 485 } 486 487 /* 488 * ELD proc files 489 */ 490 491 #ifdef CONFIG_SND_PROC_FS 492 static void print_eld_info(struct snd_info_entry *entry, 493 struct snd_info_buffer *buffer) 494 { 495 struct hdmi_spec_per_pin *per_pin = entry->private_data; 496 497 mutex_lock(&per_pin->lock); 498 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer, per_pin->pin_nid, 499 per_pin->dev_id, per_pin->cvt_nid); 500 mutex_unlock(&per_pin->lock); 501 } 502 503 static void write_eld_info(struct snd_info_entry *entry, 504 struct snd_info_buffer *buffer) 505 { 506 struct hdmi_spec_per_pin *per_pin = entry->private_data; 507 508 mutex_lock(&per_pin->lock); 509 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); 510 mutex_unlock(&per_pin->lock); 511 } 512 513 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) 514 { 515 char name[32]; 516 struct hda_codec *codec = per_pin->codec; 517 struct snd_info_entry *entry; 518 int err; 519 520 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); 521 err = snd_card_proc_new(codec->card, name, &entry); 522 if (err < 0) 523 return err; 524 525 snd_info_set_text_ops(entry, per_pin, print_eld_info); 526 entry->c.text.write = write_eld_info; 527 entry->mode |= 0200; 528 per_pin->proc_entry = entry; 529 530 return 0; 531 } 532 533 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 534 { 535 if (!per_pin->codec->bus->shutdown) { 536 snd_info_free_entry(per_pin->proc_entry); 537 per_pin->proc_entry = NULL; 538 } 539 } 540 #else 541 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, 542 int index) 543 { 544 return 0; 545 } 546 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 547 { 548 } 549 #endif 550 551 /* 552 * Audio InfoFrame routines 553 */ 554 555 /* 556 * Enable Audio InfoFrame Transmission 557 */ 558 static void hdmi_start_infoframe_trans(struct hda_codec *codec, 559 hda_nid_t pin_nid) 560 { 561 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 562 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 563 AC_DIPXMIT_BEST); 564 } 565 566 /* 567 * Disable Audio InfoFrame Transmission 568 */ 569 static void hdmi_stop_infoframe_trans(struct hda_codec *codec, 570 hda_nid_t pin_nid) 571 { 572 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 573 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 574 AC_DIPXMIT_DISABLE); 575 } 576 577 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) 578 { 579 #ifdef CONFIG_SND_DEBUG_VERBOSE 580 int i; 581 int size; 582 583 size = snd_hdmi_get_eld_size(codec, pin_nid); 584 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); 585 586 for (i = 0; i < 8; i++) { 587 size = snd_hda_codec_read(codec, pin_nid, 0, 588 AC_VERB_GET_HDMI_DIP_SIZE, i); 589 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); 590 } 591 #endif 592 } 593 594 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) 595 { 596 #ifdef BE_PARANOID 597 int i, j; 598 int size; 599 int pi, bi; 600 for (i = 0; i < 8; i++) { 601 size = snd_hda_codec_read(codec, pin_nid, 0, 602 AC_VERB_GET_HDMI_DIP_SIZE, i); 603 if (size == 0) 604 continue; 605 606 hdmi_set_dip_index(codec, pin_nid, i, 0x0); 607 for (j = 1; j < 1000; j++) { 608 hdmi_write_dip_byte(codec, pin_nid, 0x0); 609 hdmi_get_dip_index(codec, pin_nid, &pi, &bi); 610 if (pi != i) 611 codec_dbg(codec, "dip index %d: %d != %d\n", 612 bi, pi, i); 613 if (bi == 0) /* byte index wrapped around */ 614 break; 615 } 616 codec_dbg(codec, 617 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", 618 i, size, j); 619 } 620 #endif 621 } 622 623 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) 624 { 625 u8 *bytes = (u8 *)hdmi_ai; 626 u8 sum = 0; 627 int i; 628 629 hdmi_ai->checksum = 0; 630 631 for (i = 0; i < sizeof(*hdmi_ai); i++) 632 sum += bytes[i]; 633 634 hdmi_ai->checksum = -sum; 635 } 636 637 static void hdmi_fill_audio_infoframe(struct hda_codec *codec, 638 hda_nid_t pin_nid, 639 u8 *dip, int size) 640 { 641 int i; 642 643 hdmi_debug_dip_size(codec, pin_nid); 644 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ 645 646 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 647 for (i = 0; i < size; i++) 648 hdmi_write_dip_byte(codec, pin_nid, dip[i]); 649 } 650 651 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, 652 u8 *dip, int size) 653 { 654 u8 val; 655 int i; 656 657 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 658 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) 659 != AC_DIPXMIT_BEST) 660 return false; 661 662 for (i = 0; i < size; i++) { 663 val = snd_hda_codec_read(codec, pin_nid, 0, 664 AC_VERB_GET_HDMI_DIP_DATA, 0); 665 if (val != dip[i]) 666 return false; 667 } 668 669 return true; 670 } 671 672 static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 673 int dev_id, unsigned char *buf, int *eld_size) 674 { 675 snd_hda_set_dev_select(codec, nid, dev_id); 676 677 return snd_hdmi_get_eld(codec, nid, buf, eld_size); 678 } 679 680 static void hdmi_pin_setup_infoframe(struct hda_codec *codec, 681 hda_nid_t pin_nid, int dev_id, 682 int ca, int active_channels, 683 int conn_type) 684 { 685 struct hdmi_spec *spec = codec->spec; 686 union audio_infoframe ai; 687 688 memset(&ai, 0, sizeof(ai)); 689 if ((conn_type == 0) || /* HDMI */ 690 /* Nvidia DisplayPort: Nvidia HW expects same layout as HDMI */ 691 (conn_type == 1 && spec->nv_dp_workaround)) { 692 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; 693 694 if (conn_type == 0) { /* HDMI */ 695 hdmi_ai->type = 0x84; 696 hdmi_ai->ver = 0x01; 697 hdmi_ai->len = 0x0a; 698 } else {/* Nvidia DP */ 699 hdmi_ai->type = 0x84; 700 hdmi_ai->ver = 0x1b; 701 hdmi_ai->len = 0x11 << 2; 702 } 703 hdmi_ai->CC02_CT47 = active_channels - 1; 704 hdmi_ai->CA = ca; 705 hdmi_checksum_audio_infoframe(hdmi_ai); 706 } else if (conn_type == 1) { /* DisplayPort */ 707 struct dp_audio_infoframe *dp_ai = &ai.dp; 708 709 dp_ai->type = 0x84; 710 dp_ai->len = 0x1b; 711 dp_ai->ver = 0x11 << 2; 712 dp_ai->CC02_CT47 = active_channels - 1; 713 dp_ai->CA = ca; 714 } else { 715 codec_dbg(codec, "HDMI: unknown connection type at pin NID 0x%x\n", pin_nid); 716 return; 717 } 718 719 snd_hda_set_dev_select(codec, pin_nid, dev_id); 720 721 /* 722 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or 723 * sizeof(*dp_ai) to avoid partial match/update problems when 724 * the user switches between HDMI/DP monitors. 725 */ 726 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, 727 sizeof(ai))) { 728 codec_dbg(codec, "%s: pin NID=0x%x channels=%d ca=0x%02x\n", 729 __func__, pin_nid, active_channels, ca); 730 hdmi_stop_infoframe_trans(codec, pin_nid); 731 hdmi_fill_audio_infoframe(codec, pin_nid, 732 ai.bytes, sizeof(ai)); 733 hdmi_start_infoframe_trans(codec, pin_nid); 734 } 735 } 736 737 static void hdmi_setup_audio_infoframe(struct hda_codec *codec, 738 struct hdmi_spec_per_pin *per_pin, 739 bool non_pcm) 740 { 741 struct hdmi_spec *spec = codec->spec; 742 struct hdac_chmap *chmap = &spec->chmap; 743 hda_nid_t pin_nid = per_pin->pin_nid; 744 int dev_id = per_pin->dev_id; 745 int channels = per_pin->channels; 746 int active_channels; 747 struct hdmi_eld *eld; 748 int ca; 749 750 if (!channels) 751 return; 752 753 snd_hda_set_dev_select(codec, pin_nid, dev_id); 754 755 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ 756 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 757 snd_hda_codec_write(codec, pin_nid, 0, 758 AC_VERB_SET_AMP_GAIN_MUTE, 759 AMP_OUT_UNMUTE); 760 761 eld = &per_pin->sink_eld; 762 763 ca = snd_hdac_channel_allocation(&codec->core, 764 eld->info.spk_alloc, channels, 765 per_pin->chmap_set, non_pcm, per_pin->chmap); 766 767 active_channels = snd_hdac_get_active_channels(ca); 768 769 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, 770 active_channels); 771 772 /* 773 * always configure channel mapping, it may have been changed by the 774 * user in the meantime 775 */ 776 snd_hdac_setup_channel_mapping(&spec->chmap, 777 pin_nid, non_pcm, ca, channels, 778 per_pin->chmap, per_pin->chmap_set); 779 780 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id, 781 ca, active_channels, eld->info.conn_type); 782 783 per_pin->non_pcm = non_pcm; 784 } 785 786 /* 787 * Unsolicited events 788 */ 789 790 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); 791 792 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, 793 int dev_id) 794 { 795 struct hdmi_spec *spec = codec->spec; 796 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); 797 798 if (pin_idx < 0) 799 return; 800 mutex_lock(&spec->pcm_lock); 801 hdmi_present_sense(get_pin(spec, pin_idx), 1); 802 mutex_unlock(&spec->pcm_lock); 803 } 804 805 static void jack_callback(struct hda_codec *codec, 806 struct hda_jack_callback *jack) 807 { 808 /* stop polling when notification is enabled */ 809 if (codec_has_acomp(codec)) 810 return; 811 812 check_presence_and_report(codec, jack->nid, jack->dev_id); 813 } 814 815 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res, 816 struct hda_jack_tbl *jack) 817 { 818 jack->jack_dirty = 1; 819 820 codec_dbg(codec, 821 "HDMI hot plug event: Codec=%d NID=0x%x Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", 822 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA), 823 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); 824 825 check_presence_and_report(codec, jack->nid, jack->dev_id); 826 } 827 828 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) 829 { 830 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 831 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 832 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); 833 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); 834 835 codec_info(codec, 836 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", 837 codec->addr, 838 tag, 839 subtag, 840 cp_state, 841 cp_ready); 842 843 /* TODO */ 844 if (cp_state) { 845 ; 846 } 847 if (cp_ready) { 848 ; 849 } 850 } 851 852 853 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) 854 { 855 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 856 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 857 struct hda_jack_tbl *jack; 858 859 if (codec_has_acomp(codec)) 860 return; 861 862 if (codec->dp_mst) { 863 int dev_entry = 864 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 865 866 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry); 867 } else { 868 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0); 869 } 870 871 if (!jack) { 872 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); 873 return; 874 } 875 876 if (subtag == 0) 877 hdmi_intrinsic_event(codec, res, jack); 878 else 879 hdmi_non_intrinsic_event(codec, res); 880 } 881 882 static void haswell_verify_D0(struct hda_codec *codec, 883 hda_nid_t cvt_nid, hda_nid_t nid) 884 { 885 int pwr; 886 887 /* For Haswell, the converter 1/2 may keep in D3 state after bootup, 888 * thus pins could only choose converter 0 for use. Make sure the 889 * converters are in correct power state */ 890 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) 891 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); 892 893 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { 894 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, 895 AC_PWRST_D0); 896 msleep(40); 897 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); 898 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; 899 codec_dbg(codec, "Haswell HDMI audio: Power for NID 0x%x is now D%d\n", nid, pwr); 900 } 901 } 902 903 /* 904 * Callbacks 905 */ 906 907 /* HBR should be Non-PCM, 8 channels */ 908 #define is_hbr_format(format) \ 909 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) 910 911 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 912 int dev_id, bool hbr) 913 { 914 int pinctl, new_pinctl; 915 916 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { 917 snd_hda_set_dev_select(codec, pin_nid, dev_id); 918 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 919 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 920 921 if (pinctl < 0) 922 return hbr ? -EINVAL : 0; 923 924 new_pinctl = pinctl & ~AC_PINCTL_EPT; 925 if (hbr) 926 new_pinctl |= AC_PINCTL_EPT_HBR; 927 else 928 new_pinctl |= AC_PINCTL_EPT_NATIVE; 929 930 codec_dbg(codec, 931 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", 932 pin_nid, 933 pinctl == new_pinctl ? "" : "new-", 934 new_pinctl); 935 936 if (pinctl != new_pinctl) 937 snd_hda_codec_write(codec, pin_nid, 0, 938 AC_VERB_SET_PIN_WIDGET_CONTROL, 939 new_pinctl); 940 } else if (hbr) 941 return -EINVAL; 942 943 return 0; 944 } 945 946 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 947 hda_nid_t pin_nid, int dev_id, 948 u32 stream_tag, int format) 949 { 950 struct hdmi_spec *spec = codec->spec; 951 unsigned int param; 952 int err; 953 954 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id, 955 is_hbr_format(format)); 956 957 if (err) { 958 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); 959 return err; 960 } 961 962 if (spec->intel_hsw_fixup) { 963 964 /* 965 * on recent platforms IEC Coding Type is required for HBR 966 * support, read current Digital Converter settings and set 967 * ICT bitfield if needed. 968 */ 969 param = snd_hda_codec_read(codec, cvt_nid, 0, 970 AC_VERB_GET_DIGI_CONVERT_1, 0); 971 972 param = (param >> 16) & ~(AC_DIG3_ICT); 973 974 /* on recent platforms ICT mode is required for HBR support */ 975 if (is_hbr_format(format)) 976 param |= 0x1; 977 978 snd_hda_codec_write(codec, cvt_nid, 0, 979 AC_VERB_SET_DIGI_CONVERT_3, param); 980 } 981 982 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); 983 return 0; 984 } 985 986 /* Try to find an available converter 987 * If pin_idx is less then zero, just try to find an available converter. 988 * Otherwise, try to find an available converter and get the cvt mux index 989 * of the pin. 990 */ 991 static int hdmi_choose_cvt(struct hda_codec *codec, 992 int pin_idx, int *cvt_id, 993 bool silent) 994 { 995 struct hdmi_spec *spec = codec->spec; 996 struct hdmi_spec_per_pin *per_pin; 997 struct hdmi_spec_per_cvt *per_cvt = NULL; 998 int cvt_idx, mux_idx = 0; 999 1000 /* pin_idx < 0 means no pin will be bound to the converter */ 1001 if (pin_idx < 0) 1002 per_pin = NULL; 1003 else 1004 per_pin = get_pin(spec, pin_idx); 1005 1006 if (per_pin && per_pin->silent_stream) { 1007 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid); 1008 per_cvt = get_cvt(spec, cvt_idx); 1009 if (per_cvt->assigned && !silent) 1010 return -EBUSY; 1011 if (cvt_id) 1012 *cvt_id = cvt_idx; 1013 return 0; 1014 } 1015 1016 /* Dynamically assign converter to stream */ 1017 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1018 per_cvt = get_cvt(spec, cvt_idx); 1019 1020 /* Must not already be assigned */ 1021 if (per_cvt->assigned || per_cvt->silent_stream) 1022 continue; 1023 if (per_pin == NULL) 1024 break; 1025 /* Must be in pin's mux's list of converters */ 1026 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1027 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) 1028 break; 1029 /* Not in mux list */ 1030 if (mux_idx == per_pin->num_mux_nids) 1031 continue; 1032 break; 1033 } 1034 1035 /* No free converters */ 1036 if (cvt_idx == spec->num_cvts) 1037 return -EBUSY; 1038 1039 if (per_pin != NULL) 1040 per_pin->mux_idx = mux_idx; 1041 1042 if (cvt_id) 1043 *cvt_id = cvt_idx; 1044 1045 return 0; 1046 } 1047 1048 /* Assure the pin select the right convetor */ 1049 static void intel_verify_pin_cvt_connect(struct hda_codec *codec, 1050 struct hdmi_spec_per_pin *per_pin) 1051 { 1052 hda_nid_t pin_nid = per_pin->pin_nid; 1053 int mux_idx, curr; 1054 1055 mux_idx = per_pin->mux_idx; 1056 curr = snd_hda_codec_read(codec, pin_nid, 0, 1057 AC_VERB_GET_CONNECT_SEL, 0); 1058 if (curr != mux_idx) 1059 snd_hda_codec_write_cache(codec, pin_nid, 0, 1060 AC_VERB_SET_CONNECT_SEL, 1061 mux_idx); 1062 } 1063 1064 /* get the mux index for the converter of the pins 1065 * converter's mux index is the same for all pins on Intel platform 1066 */ 1067 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, 1068 hda_nid_t cvt_nid) 1069 { 1070 int i; 1071 1072 for (i = 0; i < spec->num_cvts; i++) 1073 if (spec->cvt_nids[i] == cvt_nid) 1074 return i; 1075 return -EINVAL; 1076 } 1077 1078 /* Intel HDMI workaround to fix audio routing issue: 1079 * For some Intel display codecs, pins share the same connection list. 1080 * So a conveter can be selected by multiple pins and playback on any of these 1081 * pins will generate sound on the external display, because audio flows from 1082 * the same converter to the display pipeline. Also muting one pin may make 1083 * other pins have no sound output. 1084 * So this function assures that an assigned converter for a pin is not selected 1085 * by any other pins. 1086 */ 1087 static void intel_not_share_assigned_cvt(struct hda_codec *codec, 1088 hda_nid_t pin_nid, 1089 int dev_id, int mux_idx) 1090 { 1091 struct hdmi_spec *spec = codec->spec; 1092 hda_nid_t nid; 1093 int cvt_idx, curr; 1094 struct hdmi_spec_per_cvt *per_cvt; 1095 struct hdmi_spec_per_pin *per_pin; 1096 int pin_idx; 1097 1098 /* configure the pins connections */ 1099 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 1100 int dev_id_saved; 1101 int dev_num; 1102 1103 per_pin = get_pin(spec, pin_idx); 1104 /* 1105 * pin not connected to monitor 1106 * no need to operate on it 1107 */ 1108 if (!per_pin->pcm) 1109 continue; 1110 1111 if ((per_pin->pin_nid == pin_nid) && 1112 (per_pin->dev_id == dev_id)) 1113 continue; 1114 1115 /* 1116 * if per_pin->dev_id >= dev_num, 1117 * snd_hda_get_dev_select() will fail, 1118 * and the following operation is unpredictable. 1119 * So skip this situation. 1120 */ 1121 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; 1122 if (per_pin->dev_id >= dev_num) 1123 continue; 1124 1125 nid = per_pin->pin_nid; 1126 1127 /* 1128 * Calling this function should not impact 1129 * on the device entry selection 1130 * So let's save the dev id for each pin, 1131 * and restore it when return 1132 */ 1133 dev_id_saved = snd_hda_get_dev_select(codec, nid); 1134 snd_hda_set_dev_select(codec, nid, per_pin->dev_id); 1135 curr = snd_hda_codec_read(codec, nid, 0, 1136 AC_VERB_GET_CONNECT_SEL, 0); 1137 if (curr != mux_idx) { 1138 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1139 continue; 1140 } 1141 1142 1143 /* choose an unassigned converter. The conveters in the 1144 * connection list are in the same order as in the codec. 1145 */ 1146 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1147 per_cvt = get_cvt(spec, cvt_idx); 1148 if (!per_cvt->assigned) { 1149 codec_dbg(codec, 1150 "choose cvt %d for pin NID 0x%x\n", 1151 cvt_idx, nid); 1152 snd_hda_codec_write_cache(codec, nid, 0, 1153 AC_VERB_SET_CONNECT_SEL, 1154 cvt_idx); 1155 break; 1156 } 1157 } 1158 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1159 } 1160 } 1161 1162 /* A wrapper of intel_not_share_asigned_cvt() */ 1163 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, 1164 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) 1165 { 1166 int mux_idx; 1167 struct hdmi_spec *spec = codec->spec; 1168 1169 /* On Intel platform, the mapping of converter nid to 1170 * mux index of the pins are always the same. 1171 * The pin nid may be 0, this means all pins will not 1172 * share the converter. 1173 */ 1174 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); 1175 if (mux_idx >= 0) 1176 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); 1177 } 1178 1179 /* skeleton caller of pin_cvt_fixup ops */ 1180 static void pin_cvt_fixup(struct hda_codec *codec, 1181 struct hdmi_spec_per_pin *per_pin, 1182 hda_nid_t cvt_nid) 1183 { 1184 struct hdmi_spec *spec = codec->spec; 1185 1186 if (spec->ops.pin_cvt_fixup) 1187 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); 1188 } 1189 1190 /* called in hdmi_pcm_open when no pin is assigned to the PCM */ 1191 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, 1192 struct hda_codec *codec, 1193 struct snd_pcm_substream *substream) 1194 { 1195 struct hdmi_spec *spec = codec->spec; 1196 struct snd_pcm_runtime *runtime = substream->runtime; 1197 int cvt_idx, pcm_idx; 1198 struct hdmi_spec_per_cvt *per_cvt = NULL; 1199 int err; 1200 1201 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1202 if (pcm_idx < 0) 1203 return -EINVAL; 1204 1205 err = hdmi_choose_cvt(codec, -1, &cvt_idx, false); 1206 if (err) 1207 return err; 1208 1209 per_cvt = get_cvt(spec, cvt_idx); 1210 per_cvt->assigned = true; 1211 hinfo->nid = per_cvt->cvt_nid; 1212 1213 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); 1214 1215 set_bit(pcm_idx, &spec->pcm_in_use); 1216 /* todo: setup spdif ctls assign */ 1217 1218 /* Initially set the converter's capabilities */ 1219 hinfo->channels_min = per_cvt->channels_min; 1220 hinfo->channels_max = per_cvt->channels_max; 1221 hinfo->rates = per_cvt->rates; 1222 hinfo->formats = per_cvt->formats; 1223 hinfo->maxbps = per_cvt->maxbps; 1224 1225 /* Store the updated parameters */ 1226 runtime->hw.channels_min = hinfo->channels_min; 1227 runtime->hw.channels_max = hinfo->channels_max; 1228 runtime->hw.formats = hinfo->formats; 1229 runtime->hw.rates = hinfo->rates; 1230 1231 snd_pcm_hw_constraint_step(substream->runtime, 0, 1232 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1233 return 0; 1234 } 1235 1236 /* 1237 * HDA PCM callbacks 1238 */ 1239 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, 1240 struct hda_codec *codec, 1241 struct snd_pcm_substream *substream) 1242 { 1243 struct hdmi_spec *spec = codec->spec; 1244 struct snd_pcm_runtime *runtime = substream->runtime; 1245 int pin_idx, cvt_idx, pcm_idx; 1246 struct hdmi_spec_per_pin *per_pin; 1247 struct hdmi_eld *eld; 1248 struct hdmi_spec_per_cvt *per_cvt = NULL; 1249 int err; 1250 1251 /* Validate hinfo */ 1252 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1253 if (pcm_idx < 0) 1254 return -EINVAL; 1255 1256 mutex_lock(&spec->pcm_lock); 1257 pin_idx = hinfo_to_pin_index(codec, hinfo); 1258 /* no pin is assigned to the PCM 1259 * PA need pcm open successfully when probe 1260 */ 1261 if (pin_idx < 0) { 1262 err = hdmi_pcm_open_no_pin(hinfo, codec, substream); 1263 goto unlock; 1264 } 1265 1266 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, false); 1267 if (err < 0) 1268 goto unlock; 1269 1270 per_cvt = get_cvt(spec, cvt_idx); 1271 /* Claim converter */ 1272 per_cvt->assigned = true; 1273 1274 set_bit(pcm_idx, &spec->pcm_in_use); 1275 per_pin = get_pin(spec, pin_idx); 1276 per_pin->cvt_nid = per_cvt->cvt_nid; 1277 hinfo->nid = per_cvt->cvt_nid; 1278 1279 /* flip stripe flag for the assigned stream if supported */ 1280 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE) 1281 azx_stream(get_azx_dev(substream))->stripe = 1; 1282 1283 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1284 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1285 AC_VERB_SET_CONNECT_SEL, 1286 per_pin->mux_idx); 1287 1288 /* configure unused pins to choose other converters */ 1289 pin_cvt_fixup(codec, per_pin, 0); 1290 1291 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); 1292 1293 /* Initially set the converter's capabilities */ 1294 hinfo->channels_min = per_cvt->channels_min; 1295 hinfo->channels_max = per_cvt->channels_max; 1296 hinfo->rates = per_cvt->rates; 1297 hinfo->formats = per_cvt->formats; 1298 hinfo->maxbps = per_cvt->maxbps; 1299 1300 eld = &per_pin->sink_eld; 1301 /* Restrict capabilities by ELD if this isn't disabled */ 1302 if (!static_hdmi_pcm && eld->eld_valid) { 1303 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); 1304 if (hinfo->channels_min > hinfo->channels_max || 1305 !hinfo->rates || !hinfo->formats) { 1306 per_cvt->assigned = false; 1307 hinfo->nid = 0; 1308 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1309 err = -ENODEV; 1310 goto unlock; 1311 } 1312 } 1313 1314 /* Store the updated parameters */ 1315 runtime->hw.channels_min = hinfo->channels_min; 1316 runtime->hw.channels_max = hinfo->channels_max; 1317 runtime->hw.formats = hinfo->formats; 1318 runtime->hw.rates = hinfo->rates; 1319 1320 snd_pcm_hw_constraint_step(substream->runtime, 0, 1321 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1322 unlock: 1323 mutex_unlock(&spec->pcm_lock); 1324 return err; 1325 } 1326 1327 /* 1328 * HDA/HDMI auto parsing 1329 */ 1330 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) 1331 { 1332 struct hdmi_spec *spec = codec->spec; 1333 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1334 hda_nid_t pin_nid = per_pin->pin_nid; 1335 int dev_id = per_pin->dev_id; 1336 int conns; 1337 1338 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { 1339 codec_warn(codec, 1340 "HDMI: pin NID 0x%x wcaps %#x does not support connection list\n", 1341 pin_nid, get_wcaps(codec, pin_nid)); 1342 return -EINVAL; 1343 } 1344 1345 snd_hda_set_dev_select(codec, pin_nid, dev_id); 1346 1347 if (spec->intel_hsw_fixup) { 1348 conns = spec->num_cvts; 1349 memcpy(per_pin->mux_nids, spec->cvt_nids, 1350 sizeof(hda_nid_t) * conns); 1351 } else { 1352 conns = snd_hda_get_raw_connections(codec, pin_nid, 1353 per_pin->mux_nids, 1354 HDA_MAX_CONNECTIONS); 1355 } 1356 1357 /* all the device entries on the same pin have the same conn list */ 1358 per_pin->num_mux_nids = conns; 1359 1360 return 0; 1361 } 1362 1363 static int hdmi_find_pcm_slot(struct hdmi_spec *spec, 1364 struct hdmi_spec_per_pin *per_pin) 1365 { 1366 int i; 1367 1368 for (i = 0; i < spec->pcm_used; i++) { 1369 if (!test_bit(i, &spec->pcm_bitmap)) 1370 return i; 1371 } 1372 return -EBUSY; 1373 } 1374 1375 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, 1376 struct hdmi_spec_per_pin *per_pin) 1377 { 1378 int idx; 1379 1380 /* pcm already be attached to the pin */ 1381 if (per_pin->pcm) 1382 return; 1383 idx = hdmi_find_pcm_slot(spec, per_pin); 1384 if (idx == -EBUSY) 1385 return; 1386 per_pin->pcm_idx = idx; 1387 per_pin->pcm = get_hdmi_pcm(spec, idx); 1388 set_bit(idx, &spec->pcm_bitmap); 1389 } 1390 1391 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, 1392 struct hdmi_spec_per_pin *per_pin) 1393 { 1394 int idx; 1395 1396 /* pcm already be detached from the pin */ 1397 if (!per_pin->pcm) 1398 return; 1399 idx = per_pin->pcm_idx; 1400 per_pin->pcm_idx = -1; 1401 per_pin->pcm = NULL; 1402 if (idx >= 0 && idx < spec->pcm_used) 1403 clear_bit(idx, &spec->pcm_bitmap); 1404 } 1405 1406 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, 1407 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) 1408 { 1409 int mux_idx; 1410 1411 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1412 if (per_pin->mux_nids[mux_idx] == cvt_nid) 1413 break; 1414 return mux_idx; 1415 } 1416 1417 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); 1418 1419 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, 1420 struct hdmi_spec_per_pin *per_pin) 1421 { 1422 struct hda_codec *codec = per_pin->codec; 1423 struct hda_pcm *pcm; 1424 struct hda_pcm_stream *hinfo; 1425 struct snd_pcm_substream *substream; 1426 int mux_idx; 1427 bool non_pcm; 1428 1429 if (per_pin->pcm_idx < 0 || per_pin->pcm_idx >= spec->pcm_used) 1430 return; 1431 pcm = get_pcm_rec(spec, per_pin->pcm_idx); 1432 if (!pcm->pcm) 1433 return; 1434 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) 1435 return; 1436 1437 /* hdmi audio only uses playback and one substream */ 1438 hinfo = pcm->stream; 1439 substream = pcm->pcm->streams[0].substream; 1440 1441 per_pin->cvt_nid = hinfo->nid; 1442 1443 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); 1444 if (mux_idx < per_pin->num_mux_nids) { 1445 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1446 per_pin->dev_id); 1447 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1448 AC_VERB_SET_CONNECT_SEL, 1449 mux_idx); 1450 } 1451 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); 1452 1453 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); 1454 if (substream->runtime) 1455 per_pin->channels = substream->runtime->channels; 1456 per_pin->setup = true; 1457 per_pin->mux_idx = mux_idx; 1458 1459 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1460 } 1461 1462 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, 1463 struct hdmi_spec_per_pin *per_pin) 1464 { 1465 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1466 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); 1467 1468 per_pin->chmap_set = false; 1469 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1470 1471 per_pin->setup = false; 1472 per_pin->channels = 0; 1473 } 1474 1475 static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec, 1476 struct hdmi_spec_per_pin *per_pin) 1477 { 1478 struct hdmi_spec *spec = codec->spec; 1479 1480 if (per_pin->pcm_idx >= 0) 1481 return spec->pcm_rec[per_pin->pcm_idx].jack; 1482 else 1483 return NULL; 1484 } 1485 1486 /* update per_pin ELD from the given new ELD; 1487 * setup info frame and notification accordingly 1488 * also notify ELD kctl and report jack status changes 1489 */ 1490 static void update_eld(struct hda_codec *codec, 1491 struct hdmi_spec_per_pin *per_pin, 1492 struct hdmi_eld *eld, 1493 int repoll) 1494 { 1495 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 1496 struct hdmi_spec *spec = codec->spec; 1497 struct snd_jack *pcm_jack; 1498 bool old_eld_valid = pin_eld->eld_valid; 1499 bool eld_changed; 1500 int pcm_idx; 1501 1502 if (eld->eld_valid) { 1503 if (eld->eld_size <= 0 || 1504 snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, 1505 eld->eld_size) < 0) { 1506 eld->eld_valid = false; 1507 if (repoll) { 1508 schedule_delayed_work(&per_pin->work, 1509 msecs_to_jiffies(300)); 1510 return; 1511 } 1512 } 1513 } 1514 1515 if (!eld->eld_valid || eld->eld_size <= 0 || eld->info.sad_count <= 0) { 1516 eld->eld_valid = false; 1517 eld->eld_size = 0; 1518 } 1519 1520 /* for monitor disconnection, save pcm_idx firstly */ 1521 pcm_idx = per_pin->pcm_idx; 1522 1523 /* 1524 * pcm_idx >=0 before update_eld() means it is in monitor 1525 * disconnected event. Jack must be fetched before update_eld(). 1526 */ 1527 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); 1528 1529 if (!spec->static_pcm_mapping) { 1530 if (eld->eld_valid) { 1531 hdmi_attach_hda_pcm(spec, per_pin); 1532 hdmi_pcm_setup_pin(spec, per_pin); 1533 } else { 1534 hdmi_pcm_reset_pin(spec, per_pin); 1535 hdmi_detach_hda_pcm(spec, per_pin); 1536 } 1537 } 1538 1539 /* if pcm_idx == -1, it means this is in monitor connection event 1540 * we can get the correct pcm_idx now. 1541 */ 1542 if (pcm_idx == -1) 1543 pcm_idx = per_pin->pcm_idx; 1544 if (!pcm_jack) 1545 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); 1546 1547 if (eld->eld_valid) 1548 snd_hdmi_show_eld(codec, &eld->info); 1549 1550 eld_changed = (pin_eld->eld_valid != eld->eld_valid); 1551 eld_changed |= (pin_eld->monitor_present != eld->monitor_present); 1552 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid) 1553 if (pin_eld->eld_size != eld->eld_size || 1554 memcmp(pin_eld->eld_buffer, eld->eld_buffer, 1555 eld->eld_size) != 0) 1556 eld_changed = true; 1557 1558 if (eld_changed) { 1559 pin_eld->monitor_present = eld->monitor_present; 1560 pin_eld->eld_valid = eld->eld_valid; 1561 pin_eld->eld_size = eld->eld_size; 1562 if (eld->eld_valid) 1563 memcpy(pin_eld->eld_buffer, eld->eld_buffer, 1564 eld->eld_size); 1565 pin_eld->info = eld->info; 1566 } 1567 1568 /* 1569 * Re-setup pin and infoframe. This is needed e.g. when 1570 * - sink is first plugged-in 1571 * - transcoder can change during stream playback on Haswell 1572 * and this can make HW reset converter selection on a pin. 1573 */ 1574 if (eld->eld_valid && !old_eld_valid && per_pin->setup) { 1575 pin_cvt_fixup(codec, per_pin, 0); 1576 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1577 } 1578 1579 if (eld_changed && pcm_idx >= 0) 1580 snd_ctl_notify(codec->card, 1581 SNDRV_CTL_EVENT_MASK_VALUE | 1582 SNDRV_CTL_EVENT_MASK_INFO, 1583 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); 1584 1585 if (eld_changed && pcm_jack) 1586 snd_jack_report(pcm_jack, 1587 (eld->monitor_present && eld->eld_valid) ? 1588 SND_JACK_AVOUT : 0); 1589 } 1590 1591 /* update ELD and jack state via HD-audio verbs */ 1592 static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, 1593 int repoll) 1594 { 1595 struct hda_codec *codec = per_pin->codec; 1596 struct hdmi_spec *spec = codec->spec; 1597 struct hdmi_eld *eld = &spec->temp_eld; 1598 struct device *dev = hda_codec_dev(codec); 1599 hda_nid_t pin_nid = per_pin->pin_nid; 1600 int dev_id = per_pin->dev_id; 1601 /* 1602 * Always execute a GetPinSense verb here, even when called from 1603 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited 1604 * response's PD bit is not the real PD value, but indicates that 1605 * the real PD value changed. An older version of the HD-audio 1606 * specification worked this way. Hence, we just ignore the data in 1607 * the unsolicited response to avoid custom WARs. 1608 */ 1609 int present; 1610 int ret; 1611 1612 #ifdef CONFIG_PM 1613 if (dev->power.runtime_status == RPM_SUSPENDING) 1614 return; 1615 #endif 1616 1617 ret = snd_hda_power_up_pm(codec); 1618 if (ret < 0 && pm_runtime_suspended(dev)) 1619 goto out; 1620 1621 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id); 1622 1623 mutex_lock(&per_pin->lock); 1624 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); 1625 if (eld->monitor_present) 1626 eld->eld_valid = !!(present & AC_PINSENSE_ELDV); 1627 else 1628 eld->eld_valid = false; 1629 1630 codec_dbg(codec, 1631 "HDMI status: Codec=%d NID=0x%x Presence_Detect=%d ELD_Valid=%d\n", 1632 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); 1633 1634 if (eld->eld_valid) { 1635 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id, 1636 eld->eld_buffer, &eld->eld_size) < 0) 1637 eld->eld_valid = false; 1638 } 1639 1640 update_eld(codec, per_pin, eld, repoll); 1641 mutex_unlock(&per_pin->lock); 1642 out: 1643 snd_hda_power_down_pm(codec); 1644 } 1645 1646 #define I915_SILENT_RATE 48000 1647 #define I915_SILENT_CHANNELS 2 1648 #define I915_SILENT_FORMAT SNDRV_PCM_FORMAT_S16_LE 1649 #define I915_SILENT_FORMAT_BITS 16 1650 #define I915_SILENT_FMT_MASK 0xf 1651 1652 static void silent_stream_enable_i915(struct hda_codec *codec, 1653 struct hdmi_spec_per_pin *per_pin) 1654 { 1655 unsigned int format; 1656 1657 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, 1658 per_pin->dev_id, I915_SILENT_RATE); 1659 1660 /* trigger silent stream generation in hw */ 1661 format = snd_hdac_calc_stream_format(I915_SILENT_RATE, I915_SILENT_CHANNELS, 1662 I915_SILENT_FORMAT, I915_SILENT_FORMAT_BITS, 0); 1663 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, 1664 I915_SILENT_FMT_MASK, I915_SILENT_FMT_MASK, format); 1665 usleep_range(100, 200); 1666 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, I915_SILENT_FMT_MASK, 0, format); 1667 1668 per_pin->channels = I915_SILENT_CHANNELS; 1669 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1670 } 1671 1672 static void silent_stream_set_kae(struct hda_codec *codec, 1673 struct hdmi_spec_per_pin *per_pin, 1674 bool enable) 1675 { 1676 unsigned int param; 1677 1678 codec_dbg(codec, "HDMI: KAE %d cvt-NID=0x%x\n", enable, per_pin->cvt_nid); 1679 1680 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, AC_VERB_GET_DIGI_CONVERT_1, 0); 1681 param = (param >> 16) & 0xff; 1682 1683 if (enable) 1684 param |= AC_DIG3_KAE; 1685 else 1686 param &= ~AC_DIG3_KAE; 1687 1688 snd_hda_codec_write(codec, per_pin->cvt_nid, 0, AC_VERB_SET_DIGI_CONVERT_3, param); 1689 } 1690 1691 static void silent_stream_enable(struct hda_codec *codec, 1692 struct hdmi_spec_per_pin *per_pin) 1693 { 1694 struct hdmi_spec *spec = codec->spec; 1695 struct hdmi_spec_per_cvt *per_cvt; 1696 int cvt_idx, pin_idx, err; 1697 int keep_power = 0; 1698 1699 /* 1700 * Power-up will call hdmi_present_sense, so the PM calls 1701 * have to be done without mutex held. 1702 */ 1703 1704 err = snd_hda_power_up_pm(codec); 1705 if (err < 0 && err != -EACCES) { 1706 codec_err(codec, 1707 "Failed to power up codec for silent stream enable ret=[%d]\n", err); 1708 snd_hda_power_down_pm(codec); 1709 return; 1710 } 1711 1712 mutex_lock(&per_pin->lock); 1713 1714 if (per_pin->setup) { 1715 codec_dbg(codec, "hdmi: PCM already open, no silent stream\n"); 1716 err = -EBUSY; 1717 goto unlock_out; 1718 } 1719 1720 pin_idx = pin_id_to_pin_index(codec, per_pin->pin_nid, per_pin->dev_id); 1721 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, true); 1722 if (err) { 1723 codec_err(codec, "hdmi: no free converter to enable silent mode\n"); 1724 goto unlock_out; 1725 } 1726 1727 per_cvt = get_cvt(spec, cvt_idx); 1728 per_cvt->silent_stream = true; 1729 per_pin->cvt_nid = per_cvt->cvt_nid; 1730 per_pin->silent_stream = true; 1731 1732 codec_dbg(codec, "hdmi: enabling silent stream pin-NID=0x%x cvt-NID=0x%x\n", 1733 per_pin->pin_nid, per_cvt->cvt_nid); 1734 1735 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1736 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1737 AC_VERB_SET_CONNECT_SEL, 1738 per_pin->mux_idx); 1739 1740 /* configure unused pins to choose other converters */ 1741 pin_cvt_fixup(codec, per_pin, 0); 1742 1743 switch (spec->silent_stream_type) { 1744 case SILENT_STREAM_KAE: 1745 silent_stream_enable_i915(codec, per_pin); 1746 silent_stream_set_kae(codec, per_pin, true); 1747 break; 1748 case SILENT_STREAM_I915: 1749 silent_stream_enable_i915(codec, per_pin); 1750 keep_power = 1; 1751 break; 1752 default: 1753 break; 1754 } 1755 1756 unlock_out: 1757 mutex_unlock(&per_pin->lock); 1758 1759 if (err || !keep_power) 1760 snd_hda_power_down_pm(codec); 1761 } 1762 1763 static void silent_stream_disable(struct hda_codec *codec, 1764 struct hdmi_spec_per_pin *per_pin) 1765 { 1766 struct hdmi_spec *spec = codec->spec; 1767 struct hdmi_spec_per_cvt *per_cvt; 1768 int cvt_idx, err; 1769 1770 err = snd_hda_power_up_pm(codec); 1771 if (err < 0 && err != -EACCES) { 1772 codec_err(codec, 1773 "Failed to power up codec for silent stream disable ret=[%d]\n", 1774 err); 1775 snd_hda_power_down_pm(codec); 1776 return; 1777 } 1778 1779 mutex_lock(&per_pin->lock); 1780 if (!per_pin->silent_stream) 1781 goto unlock_out; 1782 1783 codec_dbg(codec, "HDMI: disable silent stream on pin-NID=0x%x cvt-NID=0x%x\n", 1784 per_pin->pin_nid, per_pin->cvt_nid); 1785 1786 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid); 1787 if (cvt_idx >= 0 && cvt_idx < spec->num_cvts) { 1788 per_cvt = get_cvt(spec, cvt_idx); 1789 per_cvt->silent_stream = false; 1790 } 1791 1792 if (spec->silent_stream_type == SILENT_STREAM_I915) { 1793 /* release ref taken in silent_stream_enable() */ 1794 snd_hda_power_down_pm(codec); 1795 } else if (spec->silent_stream_type == SILENT_STREAM_KAE) { 1796 silent_stream_set_kae(codec, per_pin, false); 1797 } 1798 1799 per_pin->cvt_nid = 0; 1800 per_pin->silent_stream = false; 1801 1802 unlock_out: 1803 mutex_unlock(&per_pin->lock); 1804 1805 snd_hda_power_down_pm(codec); 1806 } 1807 1808 /* update ELD and jack state via audio component */ 1809 static void sync_eld_via_acomp(struct hda_codec *codec, 1810 struct hdmi_spec_per_pin *per_pin) 1811 { 1812 struct hdmi_spec *spec = codec->spec; 1813 struct hdmi_eld *eld = &spec->temp_eld; 1814 bool monitor_prev, monitor_next; 1815 1816 mutex_lock(&per_pin->lock); 1817 eld->monitor_present = false; 1818 monitor_prev = per_pin->sink_eld.monitor_present; 1819 eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, 1820 per_pin->dev_id, &eld->monitor_present, 1821 eld->eld_buffer, ELD_MAX_SIZE); 1822 eld->eld_valid = (eld->eld_size > 0); 1823 update_eld(codec, per_pin, eld, 0); 1824 monitor_next = per_pin->sink_eld.monitor_present; 1825 mutex_unlock(&per_pin->lock); 1826 1827 if (spec->silent_stream_type) { 1828 if (!monitor_prev && monitor_next) 1829 silent_stream_enable(codec, per_pin); 1830 else if (monitor_prev && !monitor_next) 1831 silent_stream_disable(codec, per_pin); 1832 } 1833 } 1834 1835 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) 1836 { 1837 struct hda_codec *codec = per_pin->codec; 1838 1839 if (!codec_has_acomp(codec)) 1840 hdmi_present_sense_via_verbs(per_pin, repoll); 1841 else 1842 sync_eld_via_acomp(codec, per_pin); 1843 } 1844 1845 static void hdmi_repoll_eld(struct work_struct *work) 1846 { 1847 struct hdmi_spec_per_pin *per_pin = 1848 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); 1849 struct hda_codec *codec = per_pin->codec; 1850 struct hdmi_spec *spec = codec->spec; 1851 struct hda_jack_tbl *jack; 1852 1853 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid, 1854 per_pin->dev_id); 1855 if (jack) 1856 jack->jack_dirty = 1; 1857 1858 if (per_pin->repoll_count++ > 6) 1859 per_pin->repoll_count = 0; 1860 1861 mutex_lock(&spec->pcm_lock); 1862 hdmi_present_sense(per_pin, per_pin->repoll_count); 1863 mutex_unlock(&spec->pcm_lock); 1864 } 1865 1866 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) 1867 { 1868 struct hdmi_spec *spec = codec->spec; 1869 unsigned int caps, config; 1870 int pin_idx; 1871 struct hdmi_spec_per_pin *per_pin; 1872 int err; 1873 int dev_num, i; 1874 1875 caps = snd_hda_query_pin_caps(codec, pin_nid); 1876 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) 1877 return 0; 1878 1879 /* 1880 * For DP MST audio, Configuration Default is the same for 1881 * all device entries on the same pin 1882 */ 1883 config = snd_hda_codec_get_pincfg(codec, pin_nid); 1884 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE && 1885 !spec->force_connect) 1886 return 0; 1887 1888 /* 1889 * To simplify the implementation, malloc all 1890 * the virtual pins in the initialization statically 1891 */ 1892 if (spec->intel_hsw_fixup) { 1893 /* 1894 * On Intel platforms, device entries count returned 1895 * by AC_PAR_DEVLIST_LEN is dynamic, and depends on 1896 * the type of receiver that is connected. Allocate pin 1897 * structures based on worst case. 1898 */ 1899 dev_num = spec->dev_num; 1900 } else if (codec->dp_mst) { 1901 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; 1902 /* 1903 * spec->dev_num is the maxinum number of device entries 1904 * among all the pins 1905 */ 1906 spec->dev_num = (spec->dev_num > dev_num) ? 1907 spec->dev_num : dev_num; 1908 } else { 1909 /* 1910 * If the platform doesn't support DP MST, 1911 * manually set dev_num to 1. This means 1912 * the pin has only one device entry. 1913 */ 1914 dev_num = 1; 1915 spec->dev_num = 1; 1916 } 1917 1918 for (i = 0; i < dev_num; i++) { 1919 pin_idx = spec->num_pins; 1920 per_pin = snd_array_new(&spec->pins); 1921 1922 if (!per_pin) 1923 return -ENOMEM; 1924 1925 per_pin->pcm = NULL; 1926 per_pin->pcm_idx = -1; 1927 per_pin->pin_nid = pin_nid; 1928 per_pin->pin_nid_idx = spec->num_nids; 1929 per_pin->dev_id = i; 1930 per_pin->non_pcm = false; 1931 snd_hda_set_dev_select(codec, pin_nid, i); 1932 err = hdmi_read_pin_conn(codec, pin_idx); 1933 if (err < 0) 1934 return err; 1935 if (!is_jack_detectable(codec, pin_nid)) 1936 codec_warn(codec, "HDMI: pin NID 0x%x - jack not detectable\n", pin_nid); 1937 spec->num_pins++; 1938 } 1939 spec->num_nids++; 1940 1941 return 0; 1942 } 1943 1944 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1945 { 1946 struct hdmi_spec *spec = codec->spec; 1947 struct hdmi_spec_per_cvt *per_cvt; 1948 unsigned int chans; 1949 int err; 1950 1951 chans = get_wcaps(codec, cvt_nid); 1952 chans = get_wcaps_channels(chans); 1953 1954 per_cvt = snd_array_new(&spec->cvts); 1955 if (!per_cvt) 1956 return -ENOMEM; 1957 1958 per_cvt->cvt_nid = cvt_nid; 1959 per_cvt->channels_min = 2; 1960 if (chans <= 16) { 1961 per_cvt->channels_max = chans; 1962 if (chans > spec->chmap.channels_max) 1963 spec->chmap.channels_max = chans; 1964 } 1965 1966 err = snd_hda_query_supported_pcm(codec, cvt_nid, 1967 &per_cvt->rates, 1968 &per_cvt->formats, 1969 &per_cvt->maxbps); 1970 if (err < 0) 1971 return err; 1972 1973 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) 1974 spec->cvt_nids[spec->num_cvts] = cvt_nid; 1975 spec->num_cvts++; 1976 1977 return 0; 1978 } 1979 1980 static const struct snd_pci_quirk force_connect_list[] = { 1981 SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1), 1982 SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1), 1983 SND_PCI_QUIRK(0x103c, 0x8711, "HP", 1), 1984 SND_PCI_QUIRK(0x1462, 0xec94, "MS-7C94", 1), 1985 SND_PCI_QUIRK(0x8086, 0x2081, "Intel NUC 10", 1), 1986 {} 1987 }; 1988 1989 static int hdmi_parse_codec(struct hda_codec *codec) 1990 { 1991 struct hdmi_spec *spec = codec->spec; 1992 hda_nid_t start_nid; 1993 unsigned int caps; 1994 int i, nodes; 1995 const struct snd_pci_quirk *q; 1996 1997 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid); 1998 if (!start_nid || nodes < 0) { 1999 codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); 2000 return -EINVAL; 2001 } 2002 2003 if (enable_all_pins) 2004 spec->force_connect = true; 2005 2006 q = snd_pci_quirk_lookup(codec->bus->pci, force_connect_list); 2007 2008 if (q && q->value) 2009 spec->force_connect = true; 2010 2011 /* 2012 * hdmi_add_pin() assumes total amount of converters to 2013 * be known, so first discover all converters 2014 */ 2015 for (i = 0; i < nodes; i++) { 2016 hda_nid_t nid = start_nid + i; 2017 2018 caps = get_wcaps(codec, nid); 2019 2020 if (!(caps & AC_WCAP_DIGITAL)) 2021 continue; 2022 2023 if (get_wcaps_type(caps) == AC_WID_AUD_OUT) 2024 hdmi_add_cvt(codec, nid); 2025 } 2026 2027 /* discover audio pins */ 2028 for (i = 0; i < nodes; i++) { 2029 hda_nid_t nid = start_nid + i; 2030 2031 caps = get_wcaps(codec, nid); 2032 2033 if (!(caps & AC_WCAP_DIGITAL)) 2034 continue; 2035 2036 if (get_wcaps_type(caps) == AC_WID_PIN) 2037 hdmi_add_pin(codec, nid); 2038 } 2039 2040 return 0; 2041 } 2042 2043 /* 2044 */ 2045 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 2046 { 2047 struct hda_spdif_out *spdif; 2048 bool non_pcm; 2049 2050 mutex_lock(&codec->spdif_mutex); 2051 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); 2052 /* Add sanity check to pass klockwork check. 2053 * This should never happen. 2054 */ 2055 if (WARN_ON(spdif == NULL)) { 2056 mutex_unlock(&codec->spdif_mutex); 2057 return true; 2058 } 2059 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); 2060 mutex_unlock(&codec->spdif_mutex); 2061 return non_pcm; 2062 } 2063 2064 /* 2065 * HDMI callbacks 2066 */ 2067 2068 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 2069 struct hda_codec *codec, 2070 unsigned int stream_tag, 2071 unsigned int format, 2072 struct snd_pcm_substream *substream) 2073 { 2074 hda_nid_t cvt_nid = hinfo->nid; 2075 struct hdmi_spec *spec = codec->spec; 2076 int pin_idx; 2077 struct hdmi_spec_per_pin *per_pin; 2078 struct snd_pcm_runtime *runtime = substream->runtime; 2079 bool non_pcm; 2080 int pinctl, stripe; 2081 int err = 0; 2082 2083 mutex_lock(&spec->pcm_lock); 2084 pin_idx = hinfo_to_pin_index(codec, hinfo); 2085 if (pin_idx < 0) { 2086 /* when pcm is not bound to a pin skip pin setup and return 0 2087 * to make audio playback be ongoing 2088 */ 2089 pin_cvt_fixup(codec, NULL, cvt_nid); 2090 snd_hda_codec_setup_stream(codec, cvt_nid, 2091 stream_tag, 0, format); 2092 goto unlock; 2093 } 2094 2095 if (snd_BUG_ON(pin_idx < 0)) { 2096 err = -EINVAL; 2097 goto unlock; 2098 } 2099 per_pin = get_pin(spec, pin_idx); 2100 2101 /* Verify pin:cvt selections to avoid silent audio after S3. 2102 * After S3, the audio driver restores pin:cvt selections 2103 * but this can happen before gfx is ready and such selection 2104 * is overlooked by HW. Thus multiple pins can share a same 2105 * default convertor and mute control will affect each other, 2106 * which can cause a resumed audio playback become silent 2107 * after S3. 2108 */ 2109 pin_cvt_fixup(codec, per_pin, 0); 2110 2111 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ 2112 /* Todo: add DP1.2 MST audio support later */ 2113 if (codec_has_acomp(codec)) 2114 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, 2115 per_pin->dev_id, runtime->rate); 2116 2117 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); 2118 mutex_lock(&per_pin->lock); 2119 per_pin->channels = substream->runtime->channels; 2120 per_pin->setup = true; 2121 2122 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) { 2123 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core, 2124 substream); 2125 snd_hda_codec_write(codec, cvt_nid, 0, 2126 AC_VERB_SET_STRIPE_CONTROL, 2127 stripe); 2128 } 2129 2130 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 2131 mutex_unlock(&per_pin->lock); 2132 if (spec->dyn_pin_out) { 2133 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2134 per_pin->dev_id); 2135 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2136 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2137 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2138 AC_VERB_SET_PIN_WIDGET_CONTROL, 2139 pinctl | PIN_OUT); 2140 } 2141 2142 /* snd_hda_set_dev_select() has been called before */ 2143 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid, 2144 per_pin->dev_id, stream_tag, format); 2145 unlock: 2146 mutex_unlock(&spec->pcm_lock); 2147 return err; 2148 } 2149 2150 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 2151 struct hda_codec *codec, 2152 struct snd_pcm_substream *substream) 2153 { 2154 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 2155 return 0; 2156 } 2157 2158 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, 2159 struct hda_codec *codec, 2160 struct snd_pcm_substream *substream) 2161 { 2162 struct hdmi_spec *spec = codec->spec; 2163 int cvt_idx, pin_idx, pcm_idx; 2164 struct hdmi_spec_per_cvt *per_cvt; 2165 struct hdmi_spec_per_pin *per_pin; 2166 int pinctl; 2167 int err = 0; 2168 2169 mutex_lock(&spec->pcm_lock); 2170 if (hinfo->nid) { 2171 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 2172 if (snd_BUG_ON(pcm_idx < 0)) { 2173 err = -EINVAL; 2174 goto unlock; 2175 } 2176 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); 2177 if (snd_BUG_ON(cvt_idx < 0)) { 2178 err = -EINVAL; 2179 goto unlock; 2180 } 2181 per_cvt = get_cvt(spec, cvt_idx); 2182 per_cvt->assigned = false; 2183 hinfo->nid = 0; 2184 2185 azx_stream(get_azx_dev(substream))->stripe = 0; 2186 2187 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2188 clear_bit(pcm_idx, &spec->pcm_in_use); 2189 pin_idx = hinfo_to_pin_index(codec, hinfo); 2190 if (pin_idx < 0) 2191 goto unlock; 2192 2193 if (snd_BUG_ON(pin_idx < 0)) { 2194 err = -EINVAL; 2195 goto unlock; 2196 } 2197 per_pin = get_pin(spec, pin_idx); 2198 2199 if (spec->dyn_pin_out) { 2200 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2201 per_pin->dev_id); 2202 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2203 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2204 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2205 AC_VERB_SET_PIN_WIDGET_CONTROL, 2206 pinctl & ~PIN_OUT); 2207 } 2208 2209 mutex_lock(&per_pin->lock); 2210 per_pin->chmap_set = false; 2211 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 2212 2213 per_pin->setup = false; 2214 per_pin->channels = 0; 2215 mutex_unlock(&per_pin->lock); 2216 } 2217 2218 unlock: 2219 mutex_unlock(&spec->pcm_lock); 2220 2221 return err; 2222 } 2223 2224 static const struct hda_pcm_ops generic_ops = { 2225 .open = hdmi_pcm_open, 2226 .close = hdmi_pcm_close, 2227 .prepare = generic_hdmi_playback_pcm_prepare, 2228 .cleanup = generic_hdmi_playback_pcm_cleanup, 2229 }; 2230 2231 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) 2232 { 2233 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2234 struct hdmi_spec *spec = codec->spec; 2235 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2236 2237 if (!per_pin) 2238 return 0; 2239 2240 return per_pin->sink_eld.info.spk_alloc; 2241 } 2242 2243 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, 2244 unsigned char *chmap) 2245 { 2246 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2247 struct hdmi_spec *spec = codec->spec; 2248 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2249 2250 /* chmap is already set to 0 in caller */ 2251 if (!per_pin) 2252 return; 2253 2254 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); 2255 } 2256 2257 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, 2258 unsigned char *chmap, int prepared) 2259 { 2260 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2261 struct hdmi_spec *spec = codec->spec; 2262 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2263 2264 if (!per_pin) 2265 return; 2266 mutex_lock(&per_pin->lock); 2267 per_pin->chmap_set = true; 2268 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); 2269 if (prepared) 2270 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 2271 mutex_unlock(&per_pin->lock); 2272 } 2273 2274 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) 2275 { 2276 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2277 struct hdmi_spec *spec = codec->spec; 2278 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2279 2280 return per_pin ? true:false; 2281 } 2282 2283 static int generic_hdmi_build_pcms(struct hda_codec *codec) 2284 { 2285 struct hdmi_spec *spec = codec->spec; 2286 int idx, pcm_num; 2287 2288 /* limit the PCM devices to the codec converters or available PINs */ 2289 pcm_num = min(spec->num_cvts, spec->num_pins); 2290 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num); 2291 2292 for (idx = 0; idx < pcm_num; idx++) { 2293 struct hda_pcm *info; 2294 struct hda_pcm_stream *pstr; 2295 2296 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); 2297 if (!info) 2298 return -ENOMEM; 2299 2300 spec->pcm_rec[idx].pcm = info; 2301 spec->pcm_used++; 2302 info->pcm_type = HDA_PCM_TYPE_HDMI; 2303 info->own_chmap = true; 2304 2305 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2306 pstr->substreams = 1; 2307 pstr->ops = generic_ops; 2308 /* pcm number is less than pcm_rec array size */ 2309 if (spec->pcm_used >= ARRAY_SIZE(spec->pcm_rec)) 2310 break; 2311 /* other pstr fields are set in open */ 2312 } 2313 2314 return 0; 2315 } 2316 2317 static void free_hdmi_jack_priv(struct snd_jack *jack) 2318 { 2319 struct hdmi_pcm *pcm = jack->private_data; 2320 2321 pcm->jack = NULL; 2322 } 2323 2324 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) 2325 { 2326 char hdmi_str[32] = "HDMI/DP"; 2327 struct hdmi_spec *spec = codec->spec; 2328 struct snd_jack *jack; 2329 int pcmdev = get_pcm_rec(spec, pcm_idx)->device; 2330 int err; 2331 2332 if (pcmdev > 0) 2333 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); 2334 2335 err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack, 2336 true, false); 2337 if (err < 0) 2338 return err; 2339 2340 spec->pcm_rec[pcm_idx].jack = jack; 2341 jack->private_data = &spec->pcm_rec[pcm_idx]; 2342 jack->private_free = free_hdmi_jack_priv; 2343 return 0; 2344 } 2345 2346 static int generic_hdmi_build_controls(struct hda_codec *codec) 2347 { 2348 struct hdmi_spec *spec = codec->spec; 2349 int dev, err; 2350 int pin_idx, pcm_idx; 2351 2352 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2353 if (!get_pcm_rec(spec, pcm_idx)->pcm) { 2354 /* no PCM: mark this for skipping permanently */ 2355 set_bit(pcm_idx, &spec->pcm_bitmap); 2356 continue; 2357 } 2358 2359 err = generic_hdmi_build_jack(codec, pcm_idx); 2360 if (err < 0) 2361 return err; 2362 2363 /* create the spdif for each pcm 2364 * pin will be bound when monitor is connected 2365 */ 2366 err = snd_hda_create_dig_out_ctls(codec, 2367 0, spec->cvt_nids[0], 2368 HDA_PCM_TYPE_HDMI); 2369 if (err < 0) 2370 return err; 2371 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2372 2373 dev = get_pcm_rec(spec, pcm_idx)->device; 2374 if (dev != SNDRV_PCM_INVALID_DEVICE) { 2375 /* add control for ELD Bytes */ 2376 err = hdmi_create_eld_ctl(codec, pcm_idx, dev); 2377 if (err < 0) 2378 return err; 2379 } 2380 } 2381 2382 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2383 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2384 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 2385 2386 if (spec->static_pcm_mapping) { 2387 hdmi_attach_hda_pcm(spec, per_pin); 2388 hdmi_pcm_setup_pin(spec, per_pin); 2389 } 2390 2391 pin_eld->eld_valid = false; 2392 hdmi_present_sense(per_pin, 0); 2393 } 2394 2395 /* add channel maps */ 2396 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2397 struct hda_pcm *pcm; 2398 2399 pcm = get_pcm_rec(spec, pcm_idx); 2400 if (!pcm || !pcm->pcm) 2401 break; 2402 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); 2403 if (err < 0) 2404 return err; 2405 } 2406 2407 return 0; 2408 } 2409 2410 static int generic_hdmi_init_per_pins(struct hda_codec *codec) 2411 { 2412 struct hdmi_spec *spec = codec->spec; 2413 int pin_idx; 2414 2415 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2416 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2417 2418 per_pin->codec = codec; 2419 mutex_init(&per_pin->lock); 2420 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); 2421 eld_proc_new(per_pin, pin_idx); 2422 } 2423 return 0; 2424 } 2425 2426 static int generic_hdmi_init(struct hda_codec *codec) 2427 { 2428 struct hdmi_spec *spec = codec->spec; 2429 int pin_idx; 2430 2431 mutex_lock(&spec->bind_lock); 2432 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2433 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2434 hda_nid_t pin_nid = per_pin->pin_nid; 2435 int dev_id = per_pin->dev_id; 2436 2437 snd_hda_set_dev_select(codec, pin_nid, dev_id); 2438 hdmi_init_pin(codec, pin_nid); 2439 if (codec_has_acomp(codec)) 2440 continue; 2441 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id, 2442 jack_callback); 2443 } 2444 mutex_unlock(&spec->bind_lock); 2445 return 0; 2446 } 2447 2448 static void hdmi_array_init(struct hdmi_spec *spec, int nums) 2449 { 2450 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); 2451 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); 2452 } 2453 2454 static void hdmi_array_free(struct hdmi_spec *spec) 2455 { 2456 snd_array_free(&spec->pins); 2457 snd_array_free(&spec->cvts); 2458 } 2459 2460 static void generic_spec_free(struct hda_codec *codec) 2461 { 2462 struct hdmi_spec *spec = codec->spec; 2463 2464 if (spec) { 2465 hdmi_array_free(spec); 2466 kfree(spec); 2467 codec->spec = NULL; 2468 } 2469 codec->dp_mst = false; 2470 } 2471 2472 static void generic_hdmi_free(struct hda_codec *codec) 2473 { 2474 struct hdmi_spec *spec = codec->spec; 2475 int pin_idx, pcm_idx; 2476 2477 if (spec->acomp_registered) { 2478 snd_hdac_acomp_exit(&codec->bus->core); 2479 } else if (codec_has_acomp(codec)) { 2480 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL); 2481 } 2482 codec->relaxed_resume = 0; 2483 2484 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2485 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2486 cancel_delayed_work_sync(&per_pin->work); 2487 eld_proc_free(per_pin); 2488 } 2489 2490 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2491 if (spec->pcm_rec[pcm_idx].jack == NULL) 2492 continue; 2493 snd_device_free(codec->card, spec->pcm_rec[pcm_idx].jack); 2494 } 2495 2496 generic_spec_free(codec); 2497 } 2498 2499 #ifdef CONFIG_PM 2500 static int generic_hdmi_suspend(struct hda_codec *codec) 2501 { 2502 struct hdmi_spec *spec = codec->spec; 2503 int pin_idx; 2504 2505 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2506 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2507 cancel_delayed_work_sync(&per_pin->work); 2508 } 2509 return 0; 2510 } 2511 2512 static int generic_hdmi_resume(struct hda_codec *codec) 2513 { 2514 struct hdmi_spec *spec = codec->spec; 2515 int pin_idx; 2516 2517 codec->patch_ops.init(codec); 2518 snd_hda_regmap_sync(codec); 2519 2520 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2521 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2522 hdmi_present_sense(per_pin, 1); 2523 } 2524 return 0; 2525 } 2526 #endif 2527 2528 static const struct hda_codec_ops generic_hdmi_patch_ops = { 2529 .init = generic_hdmi_init, 2530 .free = generic_hdmi_free, 2531 .build_pcms = generic_hdmi_build_pcms, 2532 .build_controls = generic_hdmi_build_controls, 2533 .unsol_event = hdmi_unsol_event, 2534 #ifdef CONFIG_PM 2535 .suspend = generic_hdmi_suspend, 2536 .resume = generic_hdmi_resume, 2537 #endif 2538 }; 2539 2540 static const struct hdmi_ops generic_standard_hdmi_ops = { 2541 .pin_get_eld = hdmi_pin_get_eld, 2542 .pin_setup_infoframe = hdmi_pin_setup_infoframe, 2543 .pin_hbr_setup = hdmi_pin_hbr_setup, 2544 .setup_stream = hdmi_setup_stream, 2545 }; 2546 2547 /* allocate codec->spec and assign/initialize generic parser ops */ 2548 static int alloc_generic_hdmi(struct hda_codec *codec) 2549 { 2550 struct hdmi_spec *spec; 2551 2552 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2553 if (!spec) 2554 return -ENOMEM; 2555 2556 spec->codec = codec; 2557 spec->ops = generic_standard_hdmi_ops; 2558 spec->dev_num = 1; /* initialize to 1 */ 2559 mutex_init(&spec->pcm_lock); 2560 mutex_init(&spec->bind_lock); 2561 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); 2562 2563 spec->chmap.ops.get_chmap = hdmi_get_chmap; 2564 spec->chmap.ops.set_chmap = hdmi_set_chmap; 2565 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; 2566 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc; 2567 2568 codec->spec = spec; 2569 hdmi_array_init(spec, 4); 2570 2571 codec->patch_ops = generic_hdmi_patch_ops; 2572 2573 return 0; 2574 } 2575 2576 /* generic HDMI parser */ 2577 static int patch_generic_hdmi(struct hda_codec *codec) 2578 { 2579 int err; 2580 2581 err = alloc_generic_hdmi(codec); 2582 if (err < 0) 2583 return err; 2584 2585 err = hdmi_parse_codec(codec); 2586 if (err < 0) { 2587 generic_spec_free(codec); 2588 return err; 2589 } 2590 2591 generic_hdmi_init_per_pins(codec); 2592 return 0; 2593 } 2594 2595 /* 2596 * generic audio component binding 2597 */ 2598 2599 /* turn on / off the unsol event jack detection dynamically */ 2600 static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid, 2601 int dev_id, bool use_acomp) 2602 { 2603 struct hda_jack_tbl *tbl; 2604 2605 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id); 2606 if (tbl) { 2607 /* clear unsol even if component notifier is used, or re-enable 2608 * if notifier is cleared 2609 */ 2610 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag); 2611 snd_hda_codec_write_cache(codec, nid, 0, 2612 AC_VERB_SET_UNSOLICITED_ENABLE, val); 2613 } 2614 } 2615 2616 /* set up / clear component notifier dynamically */ 2617 static void generic_acomp_notifier_set(struct drm_audio_component *acomp, 2618 bool use_acomp) 2619 { 2620 struct hdmi_spec *spec; 2621 int i; 2622 2623 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops); 2624 mutex_lock(&spec->bind_lock); 2625 spec->use_acomp_notifier = use_acomp; 2626 spec->codec->relaxed_resume = use_acomp; 2627 spec->codec->bus->keep_power = 0; 2628 /* reprogram each jack detection logic depending on the notifier */ 2629 for (i = 0; i < spec->num_pins; i++) 2630 reprogram_jack_detect(spec->codec, 2631 get_pin(spec, i)->pin_nid, 2632 get_pin(spec, i)->dev_id, 2633 use_acomp); 2634 mutex_unlock(&spec->bind_lock); 2635 } 2636 2637 /* enable / disable the notifier via master bind / unbind */ 2638 static int generic_acomp_master_bind(struct device *dev, 2639 struct drm_audio_component *acomp) 2640 { 2641 generic_acomp_notifier_set(acomp, true); 2642 return 0; 2643 } 2644 2645 static void generic_acomp_master_unbind(struct device *dev, 2646 struct drm_audio_component *acomp) 2647 { 2648 generic_acomp_notifier_set(acomp, false); 2649 } 2650 2651 /* check whether both HD-audio and DRM PCI devices belong to the same bus */ 2652 static int match_bound_vga(struct device *dev, int subtype, void *data) 2653 { 2654 struct hdac_bus *bus = data; 2655 struct pci_dev *pci, *master; 2656 2657 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev)) 2658 return 0; 2659 master = to_pci_dev(bus->dev); 2660 pci = to_pci_dev(dev); 2661 return master->bus == pci->bus; 2662 } 2663 2664 /* audio component notifier for AMD/Nvidia HDMI codecs */ 2665 static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id) 2666 { 2667 struct hda_codec *codec = audio_ptr; 2668 struct hdmi_spec *spec = codec->spec; 2669 hda_nid_t pin_nid = spec->port2pin(codec, port); 2670 2671 if (!pin_nid) 2672 return; 2673 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN) 2674 return; 2675 /* skip notification during system suspend (but not in runtime PM); 2676 * the state will be updated at resume 2677 */ 2678 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND) 2679 return; 2680 2681 check_presence_and_report(codec, pin_nid, dev_id); 2682 } 2683 2684 /* set up the private drm_audio_ops from the template */ 2685 static void setup_drm_audio_ops(struct hda_codec *codec, 2686 const struct drm_audio_component_audio_ops *ops) 2687 { 2688 struct hdmi_spec *spec = codec->spec; 2689 2690 spec->drm_audio_ops.audio_ptr = codec; 2691 /* intel_audio_codec_enable() or intel_audio_codec_disable() 2692 * will call pin_eld_notify with using audio_ptr pointer 2693 * We need make sure audio_ptr is really setup 2694 */ 2695 wmb(); 2696 spec->drm_audio_ops.pin2port = ops->pin2port; 2697 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify; 2698 spec->drm_audio_ops.master_bind = ops->master_bind; 2699 spec->drm_audio_ops.master_unbind = ops->master_unbind; 2700 } 2701 2702 /* initialize the generic HDMI audio component */ 2703 static void generic_acomp_init(struct hda_codec *codec, 2704 const struct drm_audio_component_audio_ops *ops, 2705 int (*port2pin)(struct hda_codec *, int)) 2706 { 2707 struct hdmi_spec *spec = codec->spec; 2708 2709 if (!enable_acomp) { 2710 codec_info(codec, "audio component disabled by module option\n"); 2711 return; 2712 } 2713 2714 spec->port2pin = port2pin; 2715 setup_drm_audio_ops(codec, ops); 2716 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops, 2717 match_bound_vga, 0)) { 2718 spec->acomp_registered = true; 2719 } 2720 } 2721 2722 /* 2723 * Intel codec parsers and helpers 2724 */ 2725 2726 #define INTEL_GET_VENDOR_VERB 0xf81 2727 #define INTEL_SET_VENDOR_VERB 0x781 2728 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ 2729 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ 2730 2731 static void intel_haswell_enable_all_pins(struct hda_codec *codec, 2732 bool update_tree) 2733 { 2734 unsigned int vendor_param; 2735 struct hdmi_spec *spec = codec->spec; 2736 2737 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2738 INTEL_GET_VENDOR_VERB, 0); 2739 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) 2740 return; 2741 2742 vendor_param |= INTEL_EN_ALL_PIN_CVTS; 2743 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2744 INTEL_SET_VENDOR_VERB, vendor_param); 2745 if (vendor_param == -1) 2746 return; 2747 2748 if (update_tree) 2749 snd_hda_codec_update_widgets(codec); 2750 } 2751 2752 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) 2753 { 2754 unsigned int vendor_param; 2755 struct hdmi_spec *spec = codec->spec; 2756 2757 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2758 INTEL_GET_VENDOR_VERB, 0); 2759 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) 2760 return; 2761 2762 /* enable DP1.2 mode */ 2763 vendor_param |= INTEL_EN_DP12; 2764 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); 2765 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, 2766 INTEL_SET_VENDOR_VERB, vendor_param); 2767 } 2768 2769 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. 2770 * Otherwise you may get severe h/w communication errors. 2771 */ 2772 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, 2773 unsigned int power_state) 2774 { 2775 if (power_state == AC_PWRST_D0) { 2776 intel_haswell_enable_all_pins(codec, false); 2777 intel_haswell_fixup_enable_dp12(codec); 2778 } 2779 2780 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); 2781 snd_hda_codec_set_power_to_all(codec, fg, power_state); 2782 } 2783 2784 /* There is a fixed mapping between audio pin node and display port. 2785 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL: 2786 * Pin Widget 5 - PORT B (port = 1 in i915 driver) 2787 * Pin Widget 6 - PORT C (port = 2 in i915 driver) 2788 * Pin Widget 7 - PORT D (port = 3 in i915 driver) 2789 * 2790 * on VLV, ILK: 2791 * Pin Widget 4 - PORT B (port = 1 in i915 driver) 2792 * Pin Widget 5 - PORT C (port = 2 in i915 driver) 2793 * Pin Widget 6 - PORT D (port = 3 in i915 driver) 2794 */ 2795 static int intel_base_nid(struct hda_codec *codec) 2796 { 2797 switch (codec->core.vendor_id) { 2798 case 0x80860054: /* ILK */ 2799 case 0x80862804: /* ILK */ 2800 case 0x80862882: /* VLV */ 2801 return 4; 2802 default: 2803 return 5; 2804 } 2805 } 2806 2807 static int intel_pin2port(void *audio_ptr, int pin_nid) 2808 { 2809 struct hda_codec *codec = audio_ptr; 2810 struct hdmi_spec *spec = codec->spec; 2811 int base_nid, i; 2812 2813 if (!spec->port_num) { 2814 base_nid = intel_base_nid(codec); 2815 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3)) 2816 return -1; 2817 return pin_nid - base_nid + 1; 2818 } 2819 2820 /* 2821 * looking for the pin number in the mapping table and return 2822 * the index which indicate the port number 2823 */ 2824 for (i = 0; i < spec->port_num; i++) { 2825 if (pin_nid == spec->port_map[i]) 2826 return i; 2827 } 2828 2829 codec_info(codec, "Can't find the HDMI/DP port for pin NID 0x%x\n", pin_nid); 2830 return -1; 2831 } 2832 2833 static int intel_port2pin(struct hda_codec *codec, int port) 2834 { 2835 struct hdmi_spec *spec = codec->spec; 2836 2837 if (!spec->port_num) { 2838 /* we assume only from port-B to port-D */ 2839 if (port < 1 || port > 3) 2840 return 0; 2841 return port + intel_base_nid(codec) - 1; 2842 } 2843 2844 if (port < 0 || port >= spec->port_num) 2845 return 0; 2846 return spec->port_map[port]; 2847 } 2848 2849 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) 2850 { 2851 struct hda_codec *codec = audio_ptr; 2852 int pin_nid; 2853 int dev_id = pipe; 2854 2855 pin_nid = intel_port2pin(codec, port); 2856 if (!pin_nid) 2857 return; 2858 /* skip notification during system suspend (but not in runtime PM); 2859 * the state will be updated at resume 2860 */ 2861 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND) 2862 return; 2863 2864 snd_hdac_i915_set_bclk(&codec->bus->core); 2865 check_presence_and_report(codec, pin_nid, dev_id); 2866 } 2867 2868 static const struct drm_audio_component_audio_ops intel_audio_ops = { 2869 .pin2port = intel_pin2port, 2870 .pin_eld_notify = intel_pin_eld_notify, 2871 }; 2872 2873 /* register i915 component pin_eld_notify callback */ 2874 static void register_i915_notifier(struct hda_codec *codec) 2875 { 2876 struct hdmi_spec *spec = codec->spec; 2877 2878 spec->use_acomp_notifier = true; 2879 spec->port2pin = intel_port2pin; 2880 setup_drm_audio_ops(codec, &intel_audio_ops); 2881 snd_hdac_acomp_register_notifier(&codec->bus->core, 2882 &spec->drm_audio_ops); 2883 /* no need for forcible resume for jack check thanks to notifier */ 2884 codec->relaxed_resume = 1; 2885 } 2886 2887 /* setup_stream ops override for HSW+ */ 2888 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 2889 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 2890 int format) 2891 { 2892 struct hdmi_spec *spec = codec->spec; 2893 int pin_idx = pin_id_to_pin_index(codec, pin_nid, dev_id); 2894 struct hdmi_spec_per_pin *per_pin; 2895 int res; 2896 2897 if (pin_idx < 0) 2898 per_pin = NULL; 2899 else 2900 per_pin = get_pin(spec, pin_idx); 2901 2902 haswell_verify_D0(codec, cvt_nid, pin_nid); 2903 2904 if (spec->silent_stream_type == SILENT_STREAM_KAE && per_pin && per_pin->silent_stream) { 2905 silent_stream_set_kae(codec, per_pin, false); 2906 /* wait for pending transfers in codec to clear */ 2907 usleep_range(100, 200); 2908 } 2909 2910 res = hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 2911 stream_tag, format); 2912 2913 if (spec->silent_stream_type == SILENT_STREAM_KAE && per_pin && per_pin->silent_stream) { 2914 usleep_range(100, 200); 2915 silent_stream_set_kae(codec, per_pin, true); 2916 } 2917 2918 return res; 2919 } 2920 2921 /* pin_cvt_fixup ops override for HSW+ and VLV+ */ 2922 static void i915_pin_cvt_fixup(struct hda_codec *codec, 2923 struct hdmi_spec_per_pin *per_pin, 2924 hda_nid_t cvt_nid) 2925 { 2926 if (per_pin) { 2927 haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid); 2928 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2929 per_pin->dev_id); 2930 intel_verify_pin_cvt_connect(codec, per_pin); 2931 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, 2932 per_pin->dev_id, per_pin->mux_idx); 2933 } else { 2934 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); 2935 } 2936 } 2937 2938 #ifdef CONFIG_PM 2939 static int i915_adlp_hdmi_suspend(struct hda_codec *codec) 2940 { 2941 struct hdmi_spec *spec = codec->spec; 2942 bool silent_streams = false; 2943 int pin_idx, res; 2944 2945 res = generic_hdmi_suspend(codec); 2946 2947 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2948 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2949 2950 if (per_pin->silent_stream) { 2951 silent_streams = true; 2952 break; 2953 } 2954 } 2955 2956 if (silent_streams && spec->silent_stream_type == SILENT_STREAM_KAE) { 2957 /* 2958 * stream-id should remain programmed when codec goes 2959 * to runtime suspend 2960 */ 2961 codec->no_stream_clean_at_suspend = 1; 2962 2963 /* 2964 * the system might go to S3, in which case keep-alive 2965 * must be reprogrammed upon resume 2966 */ 2967 codec->forced_resume = 1; 2968 2969 codec_dbg(codec, "HDMI: KAE active at suspend\n"); 2970 } else { 2971 codec->no_stream_clean_at_suspend = 0; 2972 codec->forced_resume = 0; 2973 } 2974 2975 return res; 2976 } 2977 2978 static int i915_adlp_hdmi_resume(struct hda_codec *codec) 2979 { 2980 struct hdmi_spec *spec = codec->spec; 2981 int pin_idx, res; 2982 2983 res = generic_hdmi_resume(codec); 2984 2985 /* KAE not programmed at suspend, nothing to do here */ 2986 if (!codec->no_stream_clean_at_suspend) 2987 return res; 2988 2989 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2990 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2991 2992 /* 2993 * If system was in suspend with monitor connected, 2994 * the codec setting may have been lost. Re-enable 2995 * keep-alive. 2996 */ 2997 if (per_pin->silent_stream) { 2998 unsigned int param; 2999 3000 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, 3001 AC_VERB_GET_CONV, 0); 3002 if (!param) { 3003 codec_dbg(codec, "HDMI: KAE: restore stream id\n"); 3004 silent_stream_enable_i915(codec, per_pin); 3005 } 3006 3007 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, 3008 AC_VERB_GET_DIGI_CONVERT_1, 0); 3009 if (!(param & (AC_DIG3_KAE << 16))) { 3010 codec_dbg(codec, "HDMI: KAE: restore DIG3_KAE\n"); 3011 silent_stream_set_kae(codec, per_pin, true); 3012 } 3013 } 3014 } 3015 3016 return res; 3017 } 3018 #endif 3019 3020 /* precondition and allocation for Intel codecs */ 3021 static int alloc_intel_hdmi(struct hda_codec *codec) 3022 { 3023 int err; 3024 3025 /* requires i915 binding */ 3026 if (!codec->bus->core.audio_component) { 3027 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); 3028 /* set probe_id here to prevent generic fallback binding */ 3029 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE; 3030 return -ENODEV; 3031 } 3032 3033 err = alloc_generic_hdmi(codec); 3034 if (err < 0) 3035 return err; 3036 /* no need to handle unsol events */ 3037 codec->patch_ops.unsol_event = NULL; 3038 return 0; 3039 } 3040 3041 /* parse and post-process for Intel codecs */ 3042 static int parse_intel_hdmi(struct hda_codec *codec) 3043 { 3044 int err, retries = 3; 3045 3046 do { 3047 err = hdmi_parse_codec(codec); 3048 } while (err < 0 && retries--); 3049 3050 if (err < 0) { 3051 generic_spec_free(codec); 3052 return err; 3053 } 3054 3055 generic_hdmi_init_per_pins(codec); 3056 register_i915_notifier(codec); 3057 return 0; 3058 } 3059 3060 /* Intel Haswell and onwards; audio component with eld notifier */ 3061 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid, 3062 const int *port_map, int port_num, int dev_num, 3063 bool send_silent_stream) 3064 { 3065 struct hdmi_spec *spec; 3066 int err; 3067 3068 err = alloc_intel_hdmi(codec); 3069 if (err < 0) 3070 return err; 3071 spec = codec->spec; 3072 codec->dp_mst = true; 3073 spec->vendor_nid = vendor_nid; 3074 spec->port_map = port_map; 3075 spec->port_num = port_num; 3076 spec->intel_hsw_fixup = true; 3077 spec->dev_num = dev_num; 3078 3079 intel_haswell_enable_all_pins(codec, true); 3080 intel_haswell_fixup_enable_dp12(codec); 3081 3082 codec->display_power_control = 1; 3083 3084 codec->patch_ops.set_power_state = haswell_set_power_state; 3085 codec->depop_delay = 0; 3086 codec->auto_runtime_pm = 1; 3087 3088 spec->ops.setup_stream = i915_hsw_setup_stream; 3089 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 3090 3091 /* 3092 * Enable silent stream feature, if it is enabled via 3093 * module param or Kconfig option 3094 */ 3095 if (send_silent_stream) 3096 spec->silent_stream_type = SILENT_STREAM_I915; 3097 3098 return parse_intel_hdmi(codec); 3099 } 3100 3101 static int patch_i915_hsw_hdmi(struct hda_codec *codec) 3102 { 3103 return intel_hsw_common_init(codec, 0x08, NULL, 0, 3, 3104 enable_silent_stream); 3105 } 3106 3107 static int patch_i915_glk_hdmi(struct hda_codec *codec) 3108 { 3109 /* 3110 * Silent stream calls audio component .get_power() from 3111 * .pin_eld_notify(). On GLK this will deadlock in i915 due 3112 * to the audio vs. CDCLK workaround. 3113 */ 3114 return intel_hsw_common_init(codec, 0x0b, NULL, 0, 3, false); 3115 } 3116 3117 static int patch_i915_icl_hdmi(struct hda_codec *codec) 3118 { 3119 /* 3120 * pin to port mapping table where the value indicate the pin number and 3121 * the index indicate the port number. 3122 */ 3123 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb}; 3124 3125 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 3, 3126 enable_silent_stream); 3127 } 3128 3129 static int patch_i915_tgl_hdmi(struct hda_codec *codec) 3130 { 3131 /* 3132 * pin to port mapping table where the value indicate the pin number and 3133 * the index indicate the port number. 3134 */ 3135 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf}; 3136 3137 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 4, 3138 enable_silent_stream); 3139 } 3140 3141 static int patch_i915_adlp_hdmi(struct hda_codec *codec) 3142 { 3143 struct hdmi_spec *spec; 3144 int res; 3145 3146 res = patch_i915_tgl_hdmi(codec); 3147 if (!res) { 3148 spec = codec->spec; 3149 3150 if (spec->silent_stream_type) { 3151 spec->silent_stream_type = SILENT_STREAM_KAE; 3152 3153 #ifdef CONFIG_PM 3154 codec->patch_ops.resume = i915_adlp_hdmi_resume; 3155 codec->patch_ops.suspend = i915_adlp_hdmi_suspend; 3156 #endif 3157 } 3158 } 3159 3160 return res; 3161 } 3162 3163 /* Intel Baytrail and Braswell; with eld notifier */ 3164 static int patch_i915_byt_hdmi(struct hda_codec *codec) 3165 { 3166 struct hdmi_spec *spec; 3167 int err; 3168 3169 err = alloc_intel_hdmi(codec); 3170 if (err < 0) 3171 return err; 3172 spec = codec->spec; 3173 3174 /* For Valleyview/Cherryview, only the display codec is in the display 3175 * power well and can use link_power ops to request/release the power. 3176 */ 3177 codec->display_power_control = 1; 3178 3179 codec->depop_delay = 0; 3180 codec->auto_runtime_pm = 1; 3181 3182 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 3183 3184 return parse_intel_hdmi(codec); 3185 } 3186 3187 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ 3188 static int patch_i915_cpt_hdmi(struct hda_codec *codec) 3189 { 3190 int err; 3191 3192 err = alloc_intel_hdmi(codec); 3193 if (err < 0) 3194 return err; 3195 return parse_intel_hdmi(codec); 3196 } 3197 3198 /* 3199 * Shared non-generic implementations 3200 */ 3201 3202 static int simple_playback_build_pcms(struct hda_codec *codec) 3203 { 3204 struct hdmi_spec *spec = codec->spec; 3205 struct hda_pcm *info; 3206 unsigned int chans; 3207 struct hda_pcm_stream *pstr; 3208 struct hdmi_spec_per_cvt *per_cvt; 3209 3210 per_cvt = get_cvt(spec, 0); 3211 chans = get_wcaps(codec, per_cvt->cvt_nid); 3212 chans = get_wcaps_channels(chans); 3213 3214 info = snd_hda_codec_pcm_new(codec, "HDMI 0"); 3215 if (!info) 3216 return -ENOMEM; 3217 spec->pcm_rec[0].pcm = info; 3218 info->pcm_type = HDA_PCM_TYPE_HDMI; 3219 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3220 *pstr = spec->pcm_playback; 3221 pstr->nid = per_cvt->cvt_nid; 3222 if (pstr->channels_max <= 2 && chans && chans <= 16) 3223 pstr->channels_max = chans; 3224 3225 return 0; 3226 } 3227 3228 /* unsolicited event for jack sensing */ 3229 static void simple_hdmi_unsol_event(struct hda_codec *codec, 3230 unsigned int res) 3231 { 3232 snd_hda_jack_set_dirty_all(codec); 3233 snd_hda_jack_report_sync(codec); 3234 } 3235 3236 /* generic_hdmi_build_jack can be used for simple_hdmi, too, 3237 * as long as spec->pins[] is set correctly 3238 */ 3239 #define simple_hdmi_build_jack generic_hdmi_build_jack 3240 3241 static int simple_playback_build_controls(struct hda_codec *codec) 3242 { 3243 struct hdmi_spec *spec = codec->spec; 3244 struct hdmi_spec_per_cvt *per_cvt; 3245 int err; 3246 3247 per_cvt = get_cvt(spec, 0); 3248 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, 3249 per_cvt->cvt_nid, 3250 HDA_PCM_TYPE_HDMI); 3251 if (err < 0) 3252 return err; 3253 return simple_hdmi_build_jack(codec, 0); 3254 } 3255 3256 static int simple_playback_init(struct hda_codec *codec) 3257 { 3258 struct hdmi_spec *spec = codec->spec; 3259 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); 3260 hda_nid_t pin = per_pin->pin_nid; 3261 3262 snd_hda_codec_write(codec, pin, 0, 3263 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); 3264 /* some codecs require to unmute the pin */ 3265 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 3266 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, 3267 AMP_OUT_UNMUTE); 3268 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id); 3269 return 0; 3270 } 3271 3272 static void simple_playback_free(struct hda_codec *codec) 3273 { 3274 struct hdmi_spec *spec = codec->spec; 3275 3276 hdmi_array_free(spec); 3277 kfree(spec); 3278 } 3279 3280 /* 3281 * Nvidia specific implementations 3282 */ 3283 3284 #define Nv_VERB_SET_Channel_Allocation 0xF79 3285 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A 3286 #define Nv_VERB_SET_Audio_Protection_On 0xF98 3287 #define Nv_VERB_SET_Audio_Protection_Off 0xF99 3288 3289 #define nvhdmi_master_con_nid_7x 0x04 3290 #define nvhdmi_master_pin_nid_7x 0x05 3291 3292 static const hda_nid_t nvhdmi_con_nids_7x[4] = { 3293 /*front, rear, clfe, rear_surr */ 3294 0x6, 0x8, 0xa, 0xc, 3295 }; 3296 3297 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { 3298 /* set audio protect on */ 3299 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3300 /* enable digital output on pin widget */ 3301 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3302 {} /* terminator */ 3303 }; 3304 3305 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { 3306 /* set audio protect on */ 3307 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3308 /* enable digital output on pin widget */ 3309 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3310 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3311 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3312 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3313 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3314 {} /* terminator */ 3315 }; 3316 3317 #ifdef LIMITED_RATE_FMT_SUPPORT 3318 /* support only the safe format and rate */ 3319 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 3320 #define SUPPORTED_MAXBPS 16 3321 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE 3322 #else 3323 /* support all rates and formats */ 3324 #define SUPPORTED_RATES \ 3325 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ 3326 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ 3327 SNDRV_PCM_RATE_192000) 3328 #define SUPPORTED_MAXBPS 24 3329 #define SUPPORTED_FORMATS \ 3330 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 3331 #endif 3332 3333 static int nvhdmi_7x_init_2ch(struct hda_codec *codec) 3334 { 3335 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); 3336 return 0; 3337 } 3338 3339 static int nvhdmi_7x_init_8ch(struct hda_codec *codec) 3340 { 3341 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); 3342 return 0; 3343 } 3344 3345 static const unsigned int channels_2_6_8[] = { 3346 2, 6, 8 3347 }; 3348 3349 static const unsigned int channels_2_8[] = { 3350 2, 8 3351 }; 3352 3353 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { 3354 .count = ARRAY_SIZE(channels_2_6_8), 3355 .list = channels_2_6_8, 3356 .mask = 0, 3357 }; 3358 3359 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { 3360 .count = ARRAY_SIZE(channels_2_8), 3361 .list = channels_2_8, 3362 .mask = 0, 3363 }; 3364 3365 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, 3366 struct hda_codec *codec, 3367 struct snd_pcm_substream *substream) 3368 { 3369 struct hdmi_spec *spec = codec->spec; 3370 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; 3371 3372 switch (codec->preset->vendor_id) { 3373 case 0x10de0002: 3374 case 0x10de0003: 3375 case 0x10de0005: 3376 case 0x10de0006: 3377 hw_constraints_channels = &hw_constraints_2_8_channels; 3378 break; 3379 case 0x10de0007: 3380 hw_constraints_channels = &hw_constraints_2_6_8_channels; 3381 break; 3382 default: 3383 break; 3384 } 3385 3386 if (hw_constraints_channels != NULL) { 3387 snd_pcm_hw_constraint_list(substream->runtime, 0, 3388 SNDRV_PCM_HW_PARAM_CHANNELS, 3389 hw_constraints_channels); 3390 } else { 3391 snd_pcm_hw_constraint_step(substream->runtime, 0, 3392 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 3393 } 3394 3395 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3396 } 3397 3398 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, 3399 struct hda_codec *codec, 3400 struct snd_pcm_substream *substream) 3401 { 3402 struct hdmi_spec *spec = codec->spec; 3403 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3404 } 3405 3406 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3407 struct hda_codec *codec, 3408 unsigned int stream_tag, 3409 unsigned int format, 3410 struct snd_pcm_substream *substream) 3411 { 3412 struct hdmi_spec *spec = codec->spec; 3413 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3414 stream_tag, format, substream); 3415 } 3416 3417 static const struct hda_pcm_stream simple_pcm_playback = { 3418 .substreams = 1, 3419 .channels_min = 2, 3420 .channels_max = 2, 3421 .ops = { 3422 .open = simple_playback_pcm_open, 3423 .close = simple_playback_pcm_close, 3424 .prepare = simple_playback_pcm_prepare 3425 }, 3426 }; 3427 3428 static const struct hda_codec_ops simple_hdmi_patch_ops = { 3429 .build_controls = simple_playback_build_controls, 3430 .build_pcms = simple_playback_build_pcms, 3431 .init = simple_playback_init, 3432 .free = simple_playback_free, 3433 .unsol_event = simple_hdmi_unsol_event, 3434 }; 3435 3436 static int patch_simple_hdmi(struct hda_codec *codec, 3437 hda_nid_t cvt_nid, hda_nid_t pin_nid) 3438 { 3439 struct hdmi_spec *spec; 3440 struct hdmi_spec_per_cvt *per_cvt; 3441 struct hdmi_spec_per_pin *per_pin; 3442 3443 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 3444 if (!spec) 3445 return -ENOMEM; 3446 3447 spec->codec = codec; 3448 codec->spec = spec; 3449 hdmi_array_init(spec, 1); 3450 3451 spec->multiout.num_dacs = 0; /* no analog */ 3452 spec->multiout.max_channels = 2; 3453 spec->multiout.dig_out_nid = cvt_nid; 3454 spec->num_cvts = 1; 3455 spec->num_pins = 1; 3456 per_pin = snd_array_new(&spec->pins); 3457 per_cvt = snd_array_new(&spec->cvts); 3458 if (!per_pin || !per_cvt) { 3459 simple_playback_free(codec); 3460 return -ENOMEM; 3461 } 3462 per_cvt->cvt_nid = cvt_nid; 3463 per_pin->pin_nid = pin_nid; 3464 spec->pcm_playback = simple_pcm_playback; 3465 3466 codec->patch_ops = simple_hdmi_patch_ops; 3467 3468 return 0; 3469 } 3470 3471 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, 3472 int channels) 3473 { 3474 unsigned int chanmask; 3475 int chan = channels ? (channels - 1) : 1; 3476 3477 switch (channels) { 3478 default: 3479 case 0: 3480 case 2: 3481 chanmask = 0x00; 3482 break; 3483 case 4: 3484 chanmask = 0x08; 3485 break; 3486 case 6: 3487 chanmask = 0x0b; 3488 break; 3489 case 8: 3490 chanmask = 0x13; 3491 break; 3492 } 3493 3494 /* Set the audio infoframe channel allocation and checksum fields. The 3495 * channel count is computed implicitly by the hardware. */ 3496 snd_hda_codec_write(codec, 0x1, 0, 3497 Nv_VERB_SET_Channel_Allocation, chanmask); 3498 3499 snd_hda_codec_write(codec, 0x1, 0, 3500 Nv_VERB_SET_Info_Frame_Checksum, 3501 (0x71 - chan - chanmask)); 3502 } 3503 3504 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, 3505 struct hda_codec *codec, 3506 struct snd_pcm_substream *substream) 3507 { 3508 struct hdmi_spec *spec = codec->spec; 3509 int i; 3510 3511 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 3512 0, AC_VERB_SET_CHANNEL_STREAMID, 0); 3513 for (i = 0; i < 4; i++) { 3514 /* set the stream id */ 3515 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3516 AC_VERB_SET_CHANNEL_STREAMID, 0); 3517 /* set the stream format */ 3518 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3519 AC_VERB_SET_STREAM_FORMAT, 0); 3520 } 3521 3522 /* The audio hardware sends a channel count of 0x7 (8ch) when all the 3523 * streams are disabled. */ 3524 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3525 3526 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3527 } 3528 3529 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, 3530 struct hda_codec *codec, 3531 unsigned int stream_tag, 3532 unsigned int format, 3533 struct snd_pcm_substream *substream) 3534 { 3535 int chs; 3536 unsigned int dataDCC2, channel_id; 3537 int i; 3538 struct hdmi_spec *spec = codec->spec; 3539 struct hda_spdif_out *spdif; 3540 struct hdmi_spec_per_cvt *per_cvt; 3541 3542 mutex_lock(&codec->spdif_mutex); 3543 per_cvt = get_cvt(spec, 0); 3544 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); 3545 3546 chs = substream->runtime->channels; 3547 3548 dataDCC2 = 0x2; 3549 3550 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ 3551 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) 3552 snd_hda_codec_write(codec, 3553 nvhdmi_master_con_nid_7x, 3554 0, 3555 AC_VERB_SET_DIGI_CONVERT_1, 3556 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3557 3558 /* set the stream id */ 3559 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3560 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); 3561 3562 /* set the stream format */ 3563 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3564 AC_VERB_SET_STREAM_FORMAT, format); 3565 3566 /* turn on again (if needed) */ 3567 /* enable and set the channel status audio/data flag */ 3568 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { 3569 snd_hda_codec_write(codec, 3570 nvhdmi_master_con_nid_7x, 3571 0, 3572 AC_VERB_SET_DIGI_CONVERT_1, 3573 spdif->ctls & 0xff); 3574 snd_hda_codec_write(codec, 3575 nvhdmi_master_con_nid_7x, 3576 0, 3577 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3578 } 3579 3580 for (i = 0; i < 4; i++) { 3581 if (chs == 2) 3582 channel_id = 0; 3583 else 3584 channel_id = i * 2; 3585 3586 /* turn off SPDIF once; 3587 *otherwise the IEC958 bits won't be updated 3588 */ 3589 if (codec->spdif_status_reset && 3590 (spdif->ctls & AC_DIG1_ENABLE)) 3591 snd_hda_codec_write(codec, 3592 nvhdmi_con_nids_7x[i], 3593 0, 3594 AC_VERB_SET_DIGI_CONVERT_1, 3595 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3596 /* set the stream id */ 3597 snd_hda_codec_write(codec, 3598 nvhdmi_con_nids_7x[i], 3599 0, 3600 AC_VERB_SET_CHANNEL_STREAMID, 3601 (stream_tag << 4) | channel_id); 3602 /* set the stream format */ 3603 snd_hda_codec_write(codec, 3604 nvhdmi_con_nids_7x[i], 3605 0, 3606 AC_VERB_SET_STREAM_FORMAT, 3607 format); 3608 /* turn on again (if needed) */ 3609 /* enable and set the channel status audio/data flag */ 3610 if (codec->spdif_status_reset && 3611 (spdif->ctls & AC_DIG1_ENABLE)) { 3612 snd_hda_codec_write(codec, 3613 nvhdmi_con_nids_7x[i], 3614 0, 3615 AC_VERB_SET_DIGI_CONVERT_1, 3616 spdif->ctls & 0xff); 3617 snd_hda_codec_write(codec, 3618 nvhdmi_con_nids_7x[i], 3619 0, 3620 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3621 } 3622 } 3623 3624 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); 3625 3626 mutex_unlock(&codec->spdif_mutex); 3627 return 0; 3628 } 3629 3630 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { 3631 .substreams = 1, 3632 .channels_min = 2, 3633 .channels_max = 8, 3634 .nid = nvhdmi_master_con_nid_7x, 3635 .rates = SUPPORTED_RATES, 3636 .maxbps = SUPPORTED_MAXBPS, 3637 .formats = SUPPORTED_FORMATS, 3638 .ops = { 3639 .open = simple_playback_pcm_open, 3640 .close = nvhdmi_8ch_7x_pcm_close, 3641 .prepare = nvhdmi_8ch_7x_pcm_prepare 3642 }, 3643 }; 3644 3645 static int patch_nvhdmi_2ch(struct hda_codec *codec) 3646 { 3647 struct hdmi_spec *spec; 3648 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, 3649 nvhdmi_master_pin_nid_7x); 3650 if (err < 0) 3651 return err; 3652 3653 codec->patch_ops.init = nvhdmi_7x_init_2ch; 3654 /* override the PCM rates, etc, as the codec doesn't give full list */ 3655 spec = codec->spec; 3656 spec->pcm_playback.rates = SUPPORTED_RATES; 3657 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; 3658 spec->pcm_playback.formats = SUPPORTED_FORMATS; 3659 spec->nv_dp_workaround = true; 3660 return 0; 3661 } 3662 3663 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) 3664 { 3665 struct hdmi_spec *spec = codec->spec; 3666 int err = simple_playback_build_pcms(codec); 3667 if (!err) { 3668 struct hda_pcm *info = get_pcm_rec(spec, 0); 3669 info->own_chmap = true; 3670 } 3671 return err; 3672 } 3673 3674 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) 3675 { 3676 struct hdmi_spec *spec = codec->spec; 3677 struct hda_pcm *info; 3678 struct snd_pcm_chmap *chmap; 3679 int err; 3680 3681 err = simple_playback_build_controls(codec); 3682 if (err < 0) 3683 return err; 3684 3685 /* add channel maps */ 3686 info = get_pcm_rec(spec, 0); 3687 err = snd_pcm_add_chmap_ctls(info->pcm, 3688 SNDRV_PCM_STREAM_PLAYBACK, 3689 snd_pcm_alt_chmaps, 8, 0, &chmap); 3690 if (err < 0) 3691 return err; 3692 switch (codec->preset->vendor_id) { 3693 case 0x10de0002: 3694 case 0x10de0003: 3695 case 0x10de0005: 3696 case 0x10de0006: 3697 chmap->channel_mask = (1U << 2) | (1U << 8); 3698 break; 3699 case 0x10de0007: 3700 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); 3701 } 3702 return 0; 3703 } 3704 3705 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) 3706 { 3707 struct hdmi_spec *spec; 3708 int err = patch_nvhdmi_2ch(codec); 3709 if (err < 0) 3710 return err; 3711 spec = codec->spec; 3712 spec->multiout.max_channels = 8; 3713 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; 3714 codec->patch_ops.init = nvhdmi_7x_init_8ch; 3715 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; 3716 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; 3717 3718 /* Initialize the audio infoframe channel mask and checksum to something 3719 * valid */ 3720 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3721 3722 return 0; 3723 } 3724 3725 /* 3726 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: 3727 * - 0x10de0015 3728 * - 0x10de0040 3729 */ 3730 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, 3731 struct hdac_cea_channel_speaker_allocation *cap, int channels) 3732 { 3733 if (cap->ca_index == 0x00 && channels == 2) 3734 return SNDRV_CTL_TLVT_CHMAP_FIXED; 3735 3736 /* If the speaker allocation matches the channel count, it is OK. */ 3737 if (cap->channels != channels) 3738 return -1; 3739 3740 /* all channels are remappable freely */ 3741 return SNDRV_CTL_TLVT_CHMAP_VAR; 3742 } 3743 3744 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, 3745 int ca, int chs, unsigned char *map) 3746 { 3747 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) 3748 return -EINVAL; 3749 3750 return 0; 3751 } 3752 3753 /* map from pin NID to port; port is 0-based */ 3754 /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */ 3755 static int nvhdmi_pin2port(void *audio_ptr, int pin_nid) 3756 { 3757 return pin_nid - 4; 3758 } 3759 3760 /* reverse-map from port to pin NID: see above */ 3761 static int nvhdmi_port2pin(struct hda_codec *codec, int port) 3762 { 3763 return port + 4; 3764 } 3765 3766 static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = { 3767 .pin2port = nvhdmi_pin2port, 3768 .pin_eld_notify = generic_acomp_pin_eld_notify, 3769 .master_bind = generic_acomp_master_bind, 3770 .master_unbind = generic_acomp_master_unbind, 3771 }; 3772 3773 static int patch_nvhdmi(struct hda_codec *codec) 3774 { 3775 struct hdmi_spec *spec; 3776 int err; 3777 3778 err = alloc_generic_hdmi(codec); 3779 if (err < 0) 3780 return err; 3781 codec->dp_mst = true; 3782 3783 spec = codec->spec; 3784 3785 err = hdmi_parse_codec(codec); 3786 if (err < 0) { 3787 generic_spec_free(codec); 3788 return err; 3789 } 3790 3791 generic_hdmi_init_per_pins(codec); 3792 3793 spec->dyn_pin_out = true; 3794 3795 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3796 nvhdmi_chmap_cea_alloc_validate_get_type; 3797 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3798 spec->nv_dp_workaround = true; 3799 3800 codec->link_down_at_suspend = 1; 3801 3802 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin); 3803 3804 return 0; 3805 } 3806 3807 static int patch_nvhdmi_legacy(struct hda_codec *codec) 3808 { 3809 struct hdmi_spec *spec; 3810 int err; 3811 3812 err = patch_generic_hdmi(codec); 3813 if (err) 3814 return err; 3815 3816 spec = codec->spec; 3817 spec->dyn_pin_out = true; 3818 3819 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3820 nvhdmi_chmap_cea_alloc_validate_get_type; 3821 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3822 spec->nv_dp_workaround = true; 3823 3824 codec->link_down_at_suspend = 1; 3825 3826 return 0; 3827 } 3828 3829 /* 3830 * The HDA codec on NVIDIA Tegra contains two scratch registers that are 3831 * accessed using vendor-defined verbs. These registers can be used for 3832 * interoperability between the HDA and HDMI drivers. 3833 */ 3834 3835 /* Audio Function Group node */ 3836 #define NVIDIA_AFG_NID 0x01 3837 3838 /* 3839 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio 3840 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to 3841 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This 3842 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an 3843 * additional bit (at position 30) to signal the validity of the format. 3844 * 3845 * | 31 | 30 | 29 16 | 15 0 | 3846 * +---------+-------+--------+--------+ 3847 * | TRIGGER | VALID | UNUSED | FORMAT | 3848 * +-----------------------------------| 3849 * 3850 * Note that for the trigger bit to take effect it needs to change value 3851 * (i.e. it needs to be toggled). The trigger bit is not applicable from 3852 * TEGRA234 chip onwards, as new verb id 0xf80 will be used for interrupt 3853 * trigger to hdmi. 3854 */ 3855 #define NVIDIA_SET_HOST_INTR 0xf80 3856 #define NVIDIA_GET_SCRATCH0 0xfa6 3857 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 3858 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 3859 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 3860 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa 3861 #define NVIDIA_SCRATCH_TRIGGER (1 << 7) 3862 #define NVIDIA_SCRATCH_VALID (1 << 6) 3863 3864 #define NVIDIA_GET_SCRATCH1 0xfab 3865 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac 3866 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad 3867 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae 3868 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf 3869 3870 /* 3871 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, 3872 * the format is invalidated so that the HDMI codec can be disabled. 3873 */ 3874 static void tegra_hdmi_set_format(struct hda_codec *codec, 3875 hda_nid_t cvt_nid, 3876 unsigned int format) 3877 { 3878 unsigned int value; 3879 unsigned int nid = NVIDIA_AFG_NID; 3880 struct hdmi_spec *spec = codec->spec; 3881 3882 /* 3883 * Tegra HDA codec design from TEGRA234 chip onwards support DP MST. 3884 * This resulted in moving scratch registers from audio function 3885 * group to converter widget context. So CVT NID should be used for 3886 * scratch register read/write for DP MST supported Tegra HDA codec. 3887 */ 3888 if (codec->dp_mst) 3889 nid = cvt_nid; 3890 3891 /* bits [31:30] contain the trigger and valid bits */ 3892 value = snd_hda_codec_read(codec, nid, 0, 3893 NVIDIA_GET_SCRATCH0, 0); 3894 value = (value >> 24) & 0xff; 3895 3896 /* bits [15:0] are used to store the HDA format */ 3897 snd_hda_codec_write(codec, nid, 0, 3898 NVIDIA_SET_SCRATCH0_BYTE0, 3899 (format >> 0) & 0xff); 3900 snd_hda_codec_write(codec, nid, 0, 3901 NVIDIA_SET_SCRATCH0_BYTE1, 3902 (format >> 8) & 0xff); 3903 3904 /* bits [16:24] are unused */ 3905 snd_hda_codec_write(codec, nid, 0, 3906 NVIDIA_SET_SCRATCH0_BYTE2, 0); 3907 3908 /* 3909 * Bit 30 signals that the data is valid and hence that HDMI audio can 3910 * be enabled. 3911 */ 3912 if (format == 0) 3913 value &= ~NVIDIA_SCRATCH_VALID; 3914 else 3915 value |= NVIDIA_SCRATCH_VALID; 3916 3917 if (spec->hdmi_intr_trig_ctrl) { 3918 /* 3919 * For Tegra HDA Codec design from TEGRA234 onwards, the 3920 * Interrupt to hdmi driver is triggered by writing 3921 * non-zero values to verb 0xF80 instead of 31st bit of 3922 * scratch register. 3923 */ 3924 snd_hda_codec_write(codec, nid, 0, 3925 NVIDIA_SET_SCRATCH0_BYTE3, value); 3926 snd_hda_codec_write(codec, nid, 0, 3927 NVIDIA_SET_HOST_INTR, 0x1); 3928 } else { 3929 /* 3930 * Whenever the 31st trigger bit is toggled, an interrupt is raised 3931 * in the HDMI codec. The HDMI driver will use that as trigger 3932 * to update its configuration. 3933 */ 3934 value ^= NVIDIA_SCRATCH_TRIGGER; 3935 3936 snd_hda_codec_write(codec, nid, 0, 3937 NVIDIA_SET_SCRATCH0_BYTE3, value); 3938 } 3939 } 3940 3941 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, 3942 struct hda_codec *codec, 3943 unsigned int stream_tag, 3944 unsigned int format, 3945 struct snd_pcm_substream *substream) 3946 { 3947 int err; 3948 3949 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, 3950 format, substream); 3951 if (err < 0) 3952 return err; 3953 3954 /* notify the HDMI codec of the format change */ 3955 tegra_hdmi_set_format(codec, hinfo->nid, format); 3956 3957 return 0; 3958 } 3959 3960 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, 3961 struct hda_codec *codec, 3962 struct snd_pcm_substream *substream) 3963 { 3964 /* invalidate the format in the HDMI codec */ 3965 tegra_hdmi_set_format(codec, hinfo->nid, 0); 3966 3967 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); 3968 } 3969 3970 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) 3971 { 3972 struct hdmi_spec *spec = codec->spec; 3973 unsigned int i; 3974 3975 for (i = 0; i < spec->num_pins; i++) { 3976 struct hda_pcm *pcm = get_pcm_rec(spec, i); 3977 3978 if (pcm->pcm_type == type) 3979 return pcm; 3980 } 3981 3982 return NULL; 3983 } 3984 3985 static int tegra_hdmi_build_pcms(struct hda_codec *codec) 3986 { 3987 struct hda_pcm_stream *stream; 3988 struct hda_pcm *pcm; 3989 int err; 3990 3991 err = generic_hdmi_build_pcms(codec); 3992 if (err < 0) 3993 return err; 3994 3995 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); 3996 if (!pcm) 3997 return -ENODEV; 3998 3999 /* 4000 * Override ->prepare() and ->cleanup() operations to notify the HDMI 4001 * codec about format changes. 4002 */ 4003 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 4004 stream->ops.prepare = tegra_hdmi_pcm_prepare; 4005 stream->ops.cleanup = tegra_hdmi_pcm_cleanup; 4006 4007 return 0; 4008 } 4009 4010 static int tegra_hdmi_init(struct hda_codec *codec) 4011 { 4012 struct hdmi_spec *spec = codec->spec; 4013 int i, err; 4014 4015 err = hdmi_parse_codec(codec); 4016 if (err < 0) { 4017 generic_spec_free(codec); 4018 return err; 4019 } 4020 4021 for (i = 0; i < spec->num_cvts; i++) 4022 snd_hda_codec_write(codec, spec->cvt_nids[i], 0, 4023 AC_VERB_SET_DIGI_CONVERT_1, 4024 AC_DIG1_ENABLE); 4025 4026 generic_hdmi_init_per_pins(codec); 4027 4028 codec->depop_delay = 10; 4029 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; 4030 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4031 nvhdmi_chmap_cea_alloc_validate_get_type; 4032 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 4033 4034 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4035 nvhdmi_chmap_cea_alloc_validate_get_type; 4036 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 4037 spec->nv_dp_workaround = true; 4038 4039 return 0; 4040 } 4041 4042 static int patch_tegra_hdmi(struct hda_codec *codec) 4043 { 4044 int err; 4045 4046 err = alloc_generic_hdmi(codec); 4047 if (err < 0) 4048 return err; 4049 4050 return tegra_hdmi_init(codec); 4051 } 4052 4053 static int patch_tegra234_hdmi(struct hda_codec *codec) 4054 { 4055 struct hdmi_spec *spec; 4056 int err; 4057 4058 err = alloc_generic_hdmi(codec); 4059 if (err < 0) 4060 return err; 4061 4062 codec->dp_mst = true; 4063 spec = codec->spec; 4064 spec->dyn_pin_out = true; 4065 spec->hdmi_intr_trig_ctrl = true; 4066 4067 return tegra_hdmi_init(codec); 4068 } 4069 4070 /* 4071 * ATI/AMD-specific implementations 4072 */ 4073 4074 #define is_amdhdmi_rev3_or_later(codec) \ 4075 ((codec)->core.vendor_id == 0x1002aa01 && \ 4076 ((codec)->core.revision_id & 0xff00) >= 0x0300) 4077 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) 4078 4079 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ 4080 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 4081 #define ATI_VERB_SET_DOWNMIX_INFO 0x772 4082 #define ATI_VERB_SET_MULTICHANNEL_01 0x777 4083 #define ATI_VERB_SET_MULTICHANNEL_23 0x778 4084 #define ATI_VERB_SET_MULTICHANNEL_45 0x779 4085 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a 4086 #define ATI_VERB_SET_HBR_CONTROL 0x77c 4087 #define ATI_VERB_SET_MULTICHANNEL_1 0x785 4088 #define ATI_VERB_SET_MULTICHANNEL_3 0x786 4089 #define ATI_VERB_SET_MULTICHANNEL_5 0x787 4090 #define ATI_VERB_SET_MULTICHANNEL_7 0x788 4091 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 4092 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 4093 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 4094 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 4095 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 4096 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 4097 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a 4098 #define ATI_VERB_GET_HBR_CONTROL 0xf7c 4099 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 4100 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 4101 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 4102 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 4103 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 4104 4105 /* AMD specific HDA cvt verbs */ 4106 #define ATI_VERB_SET_RAMP_RATE 0x770 4107 #define ATI_VERB_GET_RAMP_RATE 0xf70 4108 4109 #define ATI_OUT_ENABLE 0x1 4110 4111 #define ATI_MULTICHANNEL_MODE_PAIRED 0 4112 #define ATI_MULTICHANNEL_MODE_SINGLE 1 4113 4114 #define ATI_HBR_CAPABLE 0x01 4115 #define ATI_HBR_ENABLE 0x10 4116 4117 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 4118 int dev_id, unsigned char *buf, int *eld_size) 4119 { 4120 WARN_ON(dev_id != 0); 4121 /* call hda_eld.c ATI/AMD-specific function */ 4122 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, 4123 is_amdhdmi_rev3_or_later(codec)); 4124 } 4125 4126 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, 4127 hda_nid_t pin_nid, int dev_id, int ca, 4128 int active_channels, int conn_type) 4129 { 4130 WARN_ON(dev_id != 0); 4131 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); 4132 } 4133 4134 static int atihdmi_paired_swap_fc_lfe(int pos) 4135 { 4136 /* 4137 * ATI/AMD have automatic FC/LFE swap built-in 4138 * when in pairwise mapping mode. 4139 */ 4140 4141 switch (pos) { 4142 /* see channel_allocations[].speakers[] */ 4143 case 2: return 3; 4144 case 3: return 2; 4145 default: break; 4146 } 4147 4148 return pos; 4149 } 4150 4151 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, 4152 int ca, int chs, unsigned char *map) 4153 { 4154 struct hdac_cea_channel_speaker_allocation *cap; 4155 int i, j; 4156 4157 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ 4158 4159 cap = snd_hdac_get_ch_alloc_from_ca(ca); 4160 for (i = 0; i < chs; ++i) { 4161 int mask = snd_hdac_chmap_to_spk_mask(map[i]); 4162 bool ok = false; 4163 bool companion_ok = false; 4164 4165 if (!mask) 4166 continue; 4167 4168 for (j = 0 + i % 2; j < 8; j += 2) { 4169 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); 4170 if (cap->speakers[chan_idx] == mask) { 4171 /* channel is in a supported position */ 4172 ok = true; 4173 4174 if (i % 2 == 0 && i + 1 < chs) { 4175 /* even channel, check the odd companion */ 4176 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); 4177 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); 4178 int comp_mask_act = cap->speakers[comp_chan_idx]; 4179 4180 if (comp_mask_req == comp_mask_act) 4181 companion_ok = true; 4182 else 4183 return -EINVAL; 4184 } 4185 break; 4186 } 4187 } 4188 4189 if (!ok) 4190 return -EINVAL; 4191 4192 if (companion_ok) 4193 i++; /* companion channel already checked */ 4194 } 4195 4196 return 0; 4197 } 4198 4199 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, 4200 hda_nid_t pin_nid, int hdmi_slot, int stream_channel) 4201 { 4202 struct hda_codec *codec = hdac_to_hda_codec(hdac); 4203 int verb; 4204 int ati_channel_setup = 0; 4205 4206 if (hdmi_slot > 7) 4207 return -EINVAL; 4208 4209 if (!has_amd_full_remap_support(codec)) { 4210 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); 4211 4212 /* In case this is an odd slot but without stream channel, do not 4213 * disable the slot since the corresponding even slot could have a 4214 * channel. In case neither have a channel, the slot pair will be 4215 * disabled when this function is called for the even slot. */ 4216 if (hdmi_slot % 2 != 0 && stream_channel == 0xf) 4217 return 0; 4218 4219 hdmi_slot -= hdmi_slot % 2; 4220 4221 if (stream_channel != 0xf) 4222 stream_channel -= stream_channel % 2; 4223 } 4224 4225 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; 4226 4227 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ 4228 4229 if (stream_channel != 0xf) 4230 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; 4231 4232 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); 4233 } 4234 4235 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, 4236 hda_nid_t pin_nid, int asp_slot) 4237 { 4238 struct hda_codec *codec = hdac_to_hda_codec(hdac); 4239 bool was_odd = false; 4240 int ati_asp_slot = asp_slot; 4241 int verb; 4242 int ati_channel_setup; 4243 4244 if (asp_slot > 7) 4245 return -EINVAL; 4246 4247 if (!has_amd_full_remap_support(codec)) { 4248 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); 4249 if (ati_asp_slot % 2 != 0) { 4250 ati_asp_slot -= 1; 4251 was_odd = true; 4252 } 4253 } 4254 4255 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; 4256 4257 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); 4258 4259 if (!(ati_channel_setup & ATI_OUT_ENABLE)) 4260 return 0xf; 4261 4262 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; 4263 } 4264 4265 static int atihdmi_paired_chmap_cea_alloc_validate_get_type( 4266 struct hdac_chmap *chmap, 4267 struct hdac_cea_channel_speaker_allocation *cap, 4268 int channels) 4269 { 4270 int c; 4271 4272 /* 4273 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so 4274 * we need to take that into account (a single channel may take 2 4275 * channel slots if we need to carry a silent channel next to it). 4276 * On Rev3+ AMD codecs this function is not used. 4277 */ 4278 int chanpairs = 0; 4279 4280 /* We only produce even-numbered channel count TLVs */ 4281 if ((channels % 2) != 0) 4282 return -1; 4283 4284 for (c = 0; c < 7; c += 2) { 4285 if (cap->speakers[c] || cap->speakers[c+1]) 4286 chanpairs++; 4287 } 4288 4289 if (chanpairs * 2 != channels) 4290 return -1; 4291 4292 return SNDRV_CTL_TLVT_CHMAP_PAIRED; 4293 } 4294 4295 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, 4296 struct hdac_cea_channel_speaker_allocation *cap, 4297 unsigned int *chmap, int channels) 4298 { 4299 /* produce paired maps for pre-rev3 ATI/AMD codecs */ 4300 int count = 0; 4301 int c; 4302 4303 for (c = 7; c >= 0; c--) { 4304 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); 4305 int spk = cap->speakers[chan]; 4306 if (!spk) { 4307 /* add N/A channel if the companion channel is occupied */ 4308 if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) 4309 chmap[count++] = SNDRV_CHMAP_NA; 4310 4311 continue; 4312 } 4313 4314 chmap[count++] = snd_hdac_spk_to_chmap(spk); 4315 } 4316 4317 WARN_ON(count != channels); 4318 } 4319 4320 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 4321 int dev_id, bool hbr) 4322 { 4323 int hbr_ctl, hbr_ctl_new; 4324 4325 WARN_ON(dev_id != 0); 4326 4327 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); 4328 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { 4329 if (hbr) 4330 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; 4331 else 4332 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; 4333 4334 codec_dbg(codec, 4335 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", 4336 pin_nid, 4337 hbr_ctl == hbr_ctl_new ? "" : "new-", 4338 hbr_ctl_new); 4339 4340 if (hbr_ctl != hbr_ctl_new) 4341 snd_hda_codec_write(codec, pin_nid, 0, 4342 ATI_VERB_SET_HBR_CONTROL, 4343 hbr_ctl_new); 4344 4345 } else if (hbr) 4346 return -EINVAL; 4347 4348 return 0; 4349 } 4350 4351 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 4352 hda_nid_t pin_nid, int dev_id, 4353 u32 stream_tag, int format) 4354 { 4355 if (is_amdhdmi_rev3_or_later(codec)) { 4356 int ramp_rate = 180; /* default as per AMD spec */ 4357 /* disable ramp-up/down for non-pcm as per AMD spec */ 4358 if (format & AC_FMT_TYPE_NON_PCM) 4359 ramp_rate = 0; 4360 4361 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); 4362 } 4363 4364 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 4365 stream_tag, format); 4366 } 4367 4368 4369 static int atihdmi_init(struct hda_codec *codec) 4370 { 4371 struct hdmi_spec *spec = codec->spec; 4372 int pin_idx, err; 4373 4374 err = generic_hdmi_init(codec); 4375 4376 if (err) 4377 return err; 4378 4379 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 4380 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 4381 4382 /* make sure downmix information in infoframe is zero */ 4383 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); 4384 4385 /* enable channel-wise remap mode if supported */ 4386 if (has_amd_full_remap_support(codec)) 4387 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 4388 ATI_VERB_SET_MULTICHANNEL_MODE, 4389 ATI_MULTICHANNEL_MODE_SINGLE); 4390 } 4391 codec->auto_runtime_pm = 1; 4392 4393 return 0; 4394 } 4395 4396 /* map from pin NID to port; port is 0-based */ 4397 /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */ 4398 static int atihdmi_pin2port(void *audio_ptr, int pin_nid) 4399 { 4400 return pin_nid / 2 - 1; 4401 } 4402 4403 /* reverse-map from port to pin NID: see above */ 4404 static int atihdmi_port2pin(struct hda_codec *codec, int port) 4405 { 4406 return port * 2 + 3; 4407 } 4408 4409 static const struct drm_audio_component_audio_ops atihdmi_audio_ops = { 4410 .pin2port = atihdmi_pin2port, 4411 .pin_eld_notify = generic_acomp_pin_eld_notify, 4412 .master_bind = generic_acomp_master_bind, 4413 .master_unbind = generic_acomp_master_unbind, 4414 }; 4415 4416 static int patch_atihdmi(struct hda_codec *codec) 4417 { 4418 struct hdmi_spec *spec; 4419 struct hdmi_spec_per_cvt *per_cvt; 4420 int err, cvt_idx; 4421 4422 err = patch_generic_hdmi(codec); 4423 4424 if (err) 4425 return err; 4426 4427 codec->patch_ops.init = atihdmi_init; 4428 4429 spec = codec->spec; 4430 4431 spec->static_pcm_mapping = true; 4432 4433 spec->ops.pin_get_eld = atihdmi_pin_get_eld; 4434 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; 4435 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; 4436 spec->ops.setup_stream = atihdmi_setup_stream; 4437 4438 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; 4439 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; 4440 4441 if (!has_amd_full_remap_support(codec)) { 4442 /* override to ATI/AMD-specific versions with pairwise mapping */ 4443 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4444 atihdmi_paired_chmap_cea_alloc_validate_get_type; 4445 spec->chmap.ops.cea_alloc_to_tlv_chmap = 4446 atihdmi_paired_cea_alloc_to_tlv_chmap; 4447 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; 4448 } 4449 4450 /* ATI/AMD converters do not advertise all of their capabilities */ 4451 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 4452 per_cvt = get_cvt(spec, cvt_idx); 4453 per_cvt->channels_max = max(per_cvt->channels_max, 8u); 4454 per_cvt->rates |= SUPPORTED_RATES; 4455 per_cvt->formats |= SUPPORTED_FORMATS; 4456 per_cvt->maxbps = max(per_cvt->maxbps, 24u); 4457 } 4458 4459 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); 4460 4461 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing 4462 * the link-down as is. Tell the core to allow it. 4463 */ 4464 codec->link_down_at_suspend = 1; 4465 4466 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin); 4467 4468 return 0; 4469 } 4470 4471 /* VIA HDMI Implementation */ 4472 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ 4473 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ 4474 4475 static int patch_via_hdmi(struct hda_codec *codec) 4476 { 4477 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); 4478 } 4479 4480 /* 4481 * patch entries 4482 */ 4483 static const struct hda_device_id snd_hda_id_hdmi[] = { 4484 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), 4485 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), 4486 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), 4487 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), 4488 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), 4489 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), 4490 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), 4491 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch), 4492 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4493 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4494 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x), 4495 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4496 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4497 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), 4498 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy), 4499 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy), 4500 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy), 4501 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy), 4502 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy), 4503 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy), 4504 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy), 4505 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy), 4506 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy), 4507 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy), 4508 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy), 4509 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy), 4510 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy), 4511 /* 17 is known to be absent */ 4512 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy), 4513 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy), 4514 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy), 4515 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy), 4516 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy), 4517 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), 4518 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), 4519 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), 4520 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), 4521 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi), 4522 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi), 4523 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), 4524 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), 4525 HDA_CODEC_ENTRY(0x10de0031, "Tegra234 HDMI/DP", patch_tegra234_hdmi), 4526 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), 4527 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), 4528 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), 4529 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), 4530 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), 4531 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi), 4532 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi), 4533 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), 4534 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi), 4535 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), 4536 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi), 4537 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi), 4538 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), 4539 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), 4540 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), 4541 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), 4542 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi), 4543 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi), 4544 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi), 4545 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi), 4546 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi), 4547 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), 4548 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi), 4549 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), 4550 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi), 4551 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), 4552 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), 4553 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi), 4554 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi), 4555 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi), 4556 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi), 4557 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi), 4558 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi), 4559 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi), 4560 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi), 4561 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), 4562 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), 4563 HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi), 4564 HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi), 4565 HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi), 4566 HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi), 4567 HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi), 4568 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), 4569 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), 4570 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), 4571 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), 4572 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), 4573 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), 4574 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4575 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), 4576 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), 4577 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), 4578 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), 4579 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4580 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), 4581 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), 4582 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), 4583 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), 4584 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), 4585 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), 4586 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), 4587 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), 4588 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), 4589 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi), 4590 HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi), 4591 HDA_CODEC_ENTRY(0x80862814, "DG1 HDMI", patch_i915_tgl_hdmi), 4592 HDA_CODEC_ENTRY(0x80862815, "Alderlake HDMI", patch_i915_tgl_hdmi), 4593 HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI", patch_i915_tgl_hdmi), 4594 HDA_CODEC_ENTRY(0x80862818, "Raptorlake HDMI", patch_i915_tgl_hdmi), 4595 HDA_CODEC_ENTRY(0x80862819, "DG2 HDMI", patch_i915_adlp_hdmi), 4596 HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi), 4597 HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi), 4598 HDA_CODEC_ENTRY(0x8086281c, "Alderlake-P HDMI", patch_i915_adlp_hdmi), 4599 HDA_CODEC_ENTRY(0x8086281f, "Raptorlake-P HDMI", patch_i915_adlp_hdmi), 4600 HDA_CODEC_ENTRY(0x8086281d, "Meteorlake HDMI", patch_i915_adlp_hdmi), 4601 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), 4602 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), 4603 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), 4604 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), 4605 /* special ID for generic HDMI */ 4606 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), 4607 {} /* terminator */ 4608 }; 4609 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); 4610 4611 MODULE_LICENSE("GPL"); 4612 MODULE_DESCRIPTION("HDMI HD-audio codec"); 4613 MODULE_ALIAS("snd-hda-codec-intelhdmi"); 4614 MODULE_ALIAS("snd-hda-codec-nvhdmi"); 4615 MODULE_ALIAS("snd-hda-codec-atihdmi"); 4616 4617 static struct hda_codec_driver hdmi_driver = { 4618 .id = snd_hda_id_hdmi, 4619 }; 4620 4621 module_hda_codec_driver(hdmi_driver); 4622