18c70461bSLucas Tanure /* SPDX-License-Identifier: GPL-2.0-or-later */ 28c70461bSLucas Tanure /* 38c70461bSLucas Tanure * HD audio interface patch for Cirrus Logic CS8409 HDA bridge chip 48c70461bSLucas Tanure * 58c70461bSLucas Tanure * Copyright (C) 2021 Cirrus Logic, Inc. and 68c70461bSLucas Tanure * Cirrus Logic International Semiconductor Ltd. 78c70461bSLucas Tanure */ 88c70461bSLucas Tanure 98c70461bSLucas Tanure #ifndef __CS8409_PATCH_H 108c70461bSLucas Tanure #define __CS8409_PATCH_H 118c70461bSLucas Tanure 129e7647b5SLucas Tanure #include <linux/pci.h> 139e7647b5SLucas Tanure #include <sound/tlv.h> 14647d50a0SLucas Tanure #include <linux/workqueue.h> 159e7647b5SLucas Tanure #include <sound/hda_codec.h> 169e7647b5SLucas Tanure #include "hda_local.h" 179e7647b5SLucas Tanure #include "hda_auto_parser.h" 189e7647b5SLucas Tanure #include "hda_jack.h" 199e7647b5SLucas Tanure #include "hda_generic.h" 209e7647b5SLucas Tanure 21ccff0064SStefan Binding /* CS8409 Specific Definitions */ 22ccff0064SStefan Binding 23ccff0064SStefan Binding enum cs8409_pins { 24ccff0064SStefan Binding CS8409_PIN_ROOT, 25ccff0064SStefan Binding CS8409_PIN_AFG, 26ccff0064SStefan Binding CS8409_PIN_ASP1_OUT_A, 27ccff0064SStefan Binding CS8409_PIN_ASP1_OUT_B, 28ccff0064SStefan Binding CS8409_PIN_ASP1_OUT_C, 29ccff0064SStefan Binding CS8409_PIN_ASP1_OUT_D, 30ccff0064SStefan Binding CS8409_PIN_ASP1_OUT_E, 31ccff0064SStefan Binding CS8409_PIN_ASP1_OUT_F, 32ccff0064SStefan Binding CS8409_PIN_ASP1_OUT_G, 33ccff0064SStefan Binding CS8409_PIN_ASP1_OUT_H, 34ccff0064SStefan Binding CS8409_PIN_ASP2_OUT_A, 35ccff0064SStefan Binding CS8409_PIN_ASP2_OUT_B, 36ccff0064SStefan Binding CS8409_PIN_ASP2_OUT_C, 37ccff0064SStefan Binding CS8409_PIN_ASP2_OUT_D, 38ccff0064SStefan Binding CS8409_PIN_ASP2_OUT_E, 39ccff0064SStefan Binding CS8409_PIN_ASP2_OUT_F, 40ccff0064SStefan Binding CS8409_PIN_ASP2_OUT_G, 41ccff0064SStefan Binding CS8409_PIN_ASP2_OUT_H, 42ccff0064SStefan Binding CS8409_PIN_ASP1_IN_A, 43ccff0064SStefan Binding CS8409_PIN_ASP1_IN_B, 44ccff0064SStefan Binding CS8409_PIN_ASP1_IN_C, 45ccff0064SStefan Binding CS8409_PIN_ASP1_IN_D, 46ccff0064SStefan Binding CS8409_PIN_ASP1_IN_E, 47ccff0064SStefan Binding CS8409_PIN_ASP1_IN_F, 48ccff0064SStefan Binding CS8409_PIN_ASP1_IN_G, 49ccff0064SStefan Binding CS8409_PIN_ASP1_IN_H, 50ccff0064SStefan Binding CS8409_PIN_ASP2_IN_A, 51ccff0064SStefan Binding CS8409_PIN_ASP2_IN_B, 52ccff0064SStefan Binding CS8409_PIN_ASP2_IN_C, 53ccff0064SStefan Binding CS8409_PIN_ASP2_IN_D, 54ccff0064SStefan Binding CS8409_PIN_ASP2_IN_E, 55ccff0064SStefan Binding CS8409_PIN_ASP2_IN_F, 56ccff0064SStefan Binding CS8409_PIN_ASP2_IN_G, 57ccff0064SStefan Binding CS8409_PIN_ASP2_IN_H, 58ccff0064SStefan Binding CS8409_PIN_DMIC1, 59ccff0064SStefan Binding CS8409_PIN_DMIC2, 60ccff0064SStefan Binding CS8409_PIN_ASP1_TRANSMITTER_A, 61ccff0064SStefan Binding CS8409_PIN_ASP1_TRANSMITTER_B, 62ccff0064SStefan Binding CS8409_PIN_ASP1_TRANSMITTER_C, 63ccff0064SStefan Binding CS8409_PIN_ASP1_TRANSMITTER_D, 64ccff0064SStefan Binding CS8409_PIN_ASP1_TRANSMITTER_E, 65ccff0064SStefan Binding CS8409_PIN_ASP1_TRANSMITTER_F, 66ccff0064SStefan Binding CS8409_PIN_ASP1_TRANSMITTER_G, 67ccff0064SStefan Binding CS8409_PIN_ASP1_TRANSMITTER_H, 68ccff0064SStefan Binding CS8409_PIN_ASP2_TRANSMITTER_A, 69ccff0064SStefan Binding CS8409_PIN_ASP2_TRANSMITTER_B, 70ccff0064SStefan Binding CS8409_PIN_ASP2_TRANSMITTER_C, 71ccff0064SStefan Binding CS8409_PIN_ASP2_TRANSMITTER_D, 72ccff0064SStefan Binding CS8409_PIN_ASP2_TRANSMITTER_E, 73ccff0064SStefan Binding CS8409_PIN_ASP2_TRANSMITTER_F, 74ccff0064SStefan Binding CS8409_PIN_ASP2_TRANSMITTER_G, 75ccff0064SStefan Binding CS8409_PIN_ASP2_TRANSMITTER_H, 76ccff0064SStefan Binding CS8409_PIN_ASP1_RECEIVER_A, 77ccff0064SStefan Binding CS8409_PIN_ASP1_RECEIVER_B, 78ccff0064SStefan Binding CS8409_PIN_ASP1_RECEIVER_C, 79ccff0064SStefan Binding CS8409_PIN_ASP1_RECEIVER_D, 80ccff0064SStefan Binding CS8409_PIN_ASP1_RECEIVER_E, 81ccff0064SStefan Binding CS8409_PIN_ASP1_RECEIVER_F, 82ccff0064SStefan Binding CS8409_PIN_ASP1_RECEIVER_G, 83ccff0064SStefan Binding CS8409_PIN_ASP1_RECEIVER_H, 84ccff0064SStefan Binding CS8409_PIN_ASP2_RECEIVER_A, 85ccff0064SStefan Binding CS8409_PIN_ASP2_RECEIVER_B, 86ccff0064SStefan Binding CS8409_PIN_ASP2_RECEIVER_C, 87ccff0064SStefan Binding CS8409_PIN_ASP2_RECEIVER_D, 88ccff0064SStefan Binding CS8409_PIN_ASP2_RECEIVER_E, 89ccff0064SStefan Binding CS8409_PIN_ASP2_RECEIVER_F, 90ccff0064SStefan Binding CS8409_PIN_ASP2_RECEIVER_G, 91ccff0064SStefan Binding CS8409_PIN_ASP2_RECEIVER_H, 92ccff0064SStefan Binding CS8409_PIN_DMIC1_IN, 93ccff0064SStefan Binding CS8409_PIN_DMIC2_IN, 94ccff0064SStefan Binding CS8409_PIN_BEEP_GEN, 95ccff0064SStefan Binding CS8409_PIN_VENDOR_WIDGET 96ccff0064SStefan Binding }; 97ccff0064SStefan Binding 98ccff0064SStefan Binding enum cs8409_coefficient_index_registers { 99ccff0064SStefan Binding CS8409_DEV_CFG1, 100ccff0064SStefan Binding CS8409_DEV_CFG2, 101ccff0064SStefan Binding CS8409_DEV_CFG3, 102ccff0064SStefan Binding CS8409_ASP1_CLK_CTRL1, 103ccff0064SStefan Binding CS8409_ASP1_CLK_CTRL2, 104ccff0064SStefan Binding CS8409_ASP1_CLK_CTRL3, 105ccff0064SStefan Binding CS8409_ASP2_CLK_CTRL1, 106ccff0064SStefan Binding CS8409_ASP2_CLK_CTRL2, 107ccff0064SStefan Binding CS8409_ASP2_CLK_CTRL3, 108ccff0064SStefan Binding CS8409_DMIC_CFG, 109ccff0064SStefan Binding CS8409_BEEP_CFG, 110ccff0064SStefan Binding ASP1_RX_NULL_INS_RMV, 111ccff0064SStefan Binding ASP1_Rx_RATE1, 112ccff0064SStefan Binding ASP1_Rx_RATE2, 113ccff0064SStefan Binding ASP1_Tx_NULL_INS_RMV, 114ccff0064SStefan Binding ASP1_Tx_RATE1, 115ccff0064SStefan Binding ASP1_Tx_RATE2, 116ccff0064SStefan Binding ASP2_Rx_NULL_INS_RMV, 117ccff0064SStefan Binding ASP2_Rx_RATE1, 118ccff0064SStefan Binding ASP2_Rx_RATE2, 119ccff0064SStefan Binding ASP2_Tx_NULL_INS_RMV, 120ccff0064SStefan Binding ASP2_Tx_RATE1, 121ccff0064SStefan Binding ASP2_Tx_RATE2, 122ccff0064SStefan Binding ASP1_SYNC_CTRL, 123ccff0064SStefan Binding ASP2_SYNC_CTRL, 124ccff0064SStefan Binding ASP1_A_TX_CTRL1, 125ccff0064SStefan Binding ASP1_A_TX_CTRL2, 126ccff0064SStefan Binding ASP1_B_TX_CTRL1, 127ccff0064SStefan Binding ASP1_B_TX_CTRL2, 128ccff0064SStefan Binding ASP1_C_TX_CTRL1, 129ccff0064SStefan Binding ASP1_C_TX_CTRL2, 130ccff0064SStefan Binding ASP1_D_TX_CTRL1, 131ccff0064SStefan Binding ASP1_D_TX_CTRL2, 132ccff0064SStefan Binding ASP1_E_TX_CTRL1, 133ccff0064SStefan Binding ASP1_E_TX_CTRL2, 134ccff0064SStefan Binding ASP1_F_TX_CTRL1, 135ccff0064SStefan Binding ASP1_F_TX_CTRL2, 136ccff0064SStefan Binding ASP1_G_TX_CTRL1, 137ccff0064SStefan Binding ASP1_G_TX_CTRL2, 138ccff0064SStefan Binding ASP1_H_TX_CTRL1, 139ccff0064SStefan Binding ASP1_H_TX_CTRL2, 140ccff0064SStefan Binding ASP2_A_TX_CTRL1, 141ccff0064SStefan Binding ASP2_A_TX_CTRL2, 142ccff0064SStefan Binding ASP2_B_TX_CTRL1, 143ccff0064SStefan Binding ASP2_B_TX_CTRL2, 144ccff0064SStefan Binding ASP2_C_TX_CTRL1, 145ccff0064SStefan Binding ASP2_C_TX_CTRL2, 146ccff0064SStefan Binding ASP2_D_TX_CTRL1, 147ccff0064SStefan Binding ASP2_D_TX_CTRL2, 148ccff0064SStefan Binding ASP2_E_TX_CTRL1, 149ccff0064SStefan Binding ASP2_E_TX_CTRL2, 150ccff0064SStefan Binding ASP2_F_TX_CTRL1, 151ccff0064SStefan Binding ASP2_F_TX_CTRL2, 152ccff0064SStefan Binding ASP2_G_TX_CTRL1, 153ccff0064SStefan Binding ASP2_G_TX_CTRL2, 154ccff0064SStefan Binding ASP2_H_TX_CTRL1, 155ccff0064SStefan Binding ASP2_H_TX_CTRL2, 156ccff0064SStefan Binding ASP1_A_RX_CTRL1, 157ccff0064SStefan Binding ASP1_A_RX_CTRL2, 158ccff0064SStefan Binding ASP1_B_RX_CTRL1, 159ccff0064SStefan Binding ASP1_B_RX_CTRL2, 160ccff0064SStefan Binding ASP1_C_RX_CTRL1, 161ccff0064SStefan Binding ASP1_C_RX_CTRL2, 162ccff0064SStefan Binding ASP1_D_RX_CTRL1, 163ccff0064SStefan Binding ASP1_D_RX_CTRL2, 164ccff0064SStefan Binding ASP1_E_RX_CTRL1, 165ccff0064SStefan Binding ASP1_E_RX_CTRL2, 166ccff0064SStefan Binding ASP1_F_RX_CTRL1, 167ccff0064SStefan Binding ASP1_F_RX_CTRL2, 168ccff0064SStefan Binding ASP1_G_RX_CTRL1, 169ccff0064SStefan Binding ASP1_G_RX_CTRL2, 170ccff0064SStefan Binding ASP1_H_RX_CTRL1, 171ccff0064SStefan Binding ASP1_H_RX_CTRL2, 172ccff0064SStefan Binding ASP2_A_RX_CTRL1, 173ccff0064SStefan Binding ASP2_A_RX_CTRL2, 174ccff0064SStefan Binding ASP2_B_RX_CTRL1, 175ccff0064SStefan Binding ASP2_B_RX_CTRL2, 176ccff0064SStefan Binding ASP2_C_RX_CTRL1, 177ccff0064SStefan Binding ASP2_C_RX_CTRL2, 178ccff0064SStefan Binding ASP2_D_RX_CTRL1, 179ccff0064SStefan Binding ASP2_D_RX_CTRL2, 180ccff0064SStefan Binding ASP2_E_RX_CTRL1, 181ccff0064SStefan Binding ASP2_E_RX_CTRL2, 182ccff0064SStefan Binding ASP2_F_RX_CTRL1, 183ccff0064SStefan Binding ASP2_F_RX_CTRL2, 184ccff0064SStefan Binding ASP2_G_RX_CTRL1, 185ccff0064SStefan Binding ASP2_G_RX_CTRL2, 186ccff0064SStefan Binding ASP2_H_RX_CTRL1, 187ccff0064SStefan Binding ASP2_H_RX_CTRL2, 188ccff0064SStefan Binding CS8409_I2C_ADDR, 189ccff0064SStefan Binding CS8409_I2C_DATA, 190ccff0064SStefan Binding CS8409_I2C_CTRL, 191ccff0064SStefan Binding CS8409_I2C_STS, 192ccff0064SStefan Binding CS8409_I2C_QWRITE, 193ccff0064SStefan Binding CS8409_I2C_QREAD, 194ccff0064SStefan Binding CS8409_SPI_CTRL, 195ccff0064SStefan Binding CS8409_SPI_TX_DATA, 196ccff0064SStefan Binding CS8409_SPI_RX_DATA, 197ccff0064SStefan Binding CS8409_SPI_STS, 198ccff0064SStefan Binding CS8409_PFE_COEF_W1, /* Parametric filter engine coefficient write 1*/ 199ccff0064SStefan Binding CS8409_PFE_COEF_W2, 200ccff0064SStefan Binding CS8409_PFE_CTRL1, 201ccff0064SStefan Binding CS8409_PFE_CTRL2, 202ccff0064SStefan Binding CS8409_PRE_SCALE_ATTN1, 203ccff0064SStefan Binding CS8409_PRE_SCALE_ATTN2, 204ccff0064SStefan Binding CS8409_PFE_COEF_MON1, /* Parametric filter engine coefficient monitor 1*/ 205ccff0064SStefan Binding CS8409_PFE_COEF_MON2, 206ccff0064SStefan Binding CS8409_ASP1_INTRN_STS, 207ccff0064SStefan Binding CS8409_ASP2_INTRN_STS, 208ccff0064SStefan Binding CS8409_ASP1_RX_SCLK_COUNT, 209ccff0064SStefan Binding CS8409_ASP1_TX_SCLK_COUNT, 210ccff0064SStefan Binding CS8409_ASP2_RX_SCLK_COUNT, 211ccff0064SStefan Binding CS8409_ASP2_TX_SCLK_COUNT, 212ccff0064SStefan Binding CS8409_ASP_UNS_RESP_MASK, 213ccff0064SStefan Binding CS8409_LOOPBACK_CTRL = 0x80, 214ccff0064SStefan Binding CS8409_PAD_CFG_SLW_RATE_CTRL = 0x82, /* Pad Config and Slew Rate Control (CIR = 0x0082) */ 215ccff0064SStefan Binding }; 216ccff0064SStefan Binding 217ccff0064SStefan Binding /* CS42L42 Specific Definitions */ 218ccff0064SStefan Binding 21924f7ac3dSLucas Tanure #define CS8409_MAX_CODECS 8 220b2a88774SLucas Tanure #define CS42L42_VOLUMES (4U) 221636eb9d2SLucas Tanure #define CS42L42_HP_VOL_REAL_MIN (-63) 222636eb9d2SLucas Tanure #define CS42L42_HP_VOL_REAL_MAX (0) 223636eb9d2SLucas Tanure #define CS42L42_AMIC_VOL_REAL_MIN (-97) 224636eb9d2SLucas Tanure #define CS42L42_AMIC_VOL_REAL_MAX (12) 225636eb9d2SLucas Tanure #define CS42L42_REG_HS_VOL_CHA (0x2301) 226636eb9d2SLucas Tanure #define CS42L42_REG_HS_VOL_CHB (0x2303) 227636eb9d2SLucas Tanure #define CS42L42_REG_HS_VOL_MASK (0x003F) 228636eb9d2SLucas Tanure #define CS42L42_REG_AMIC_VOL (0x1D03) 229636eb9d2SLucas Tanure #define CS42L42_REG_AMIC_VOL_MASK (0x00FF) 230ccff0064SStefan Binding #define CS42L42_HSDET_AUTO_DONE (0x02) 231ccff0064SStefan Binding #define CS42L42_HSTYPE_MASK (0x03) 232ccff0064SStefan Binding #define CS42L42_JACK_INSERTED (0x0C) 233ccff0064SStefan Binding #define CS42L42_JACK_REMOVED (0x00) 234928adf0eSStefan Binding #define CS42L42_I2C_TIMEOUT_US (20000) 235928adf0eSStefan Binding #define CS42L42_I2C_SLEEP_US (2000) 2364ff2ae3aSStefan Binding #define CS42L42_PDN_TIMEOUT_US (250000) 2374ff2ae3aSStefan Binding #define CS42L42_PDN_SLEEP_US (2000) 238*342b6b61SStefan Binding #define CS42L42_FULL_SCALE_VOL_MASK (2) 239*342b6b61SStefan Binding #define CS42L42_FULL_SCALE_VOL_0DB (1) 240*342b6b61SStefan Binding #define CS42L42_FULL_SCALE_VOL_MINUS6DB (0) 241ccff0064SStefan Binding 242ccff0064SStefan Binding /* Dell BULLSEYE / WARLOCK / CYBORG Specific Definitions */ 243ccff0064SStefan Binding 244ccff0064SStefan Binding #define CS42L42_I2C_ADDR (0x48 << 1) 245ccff0064SStefan Binding #define CS8409_CS42L42_RESET GENMASK(5, 5) /* CS8409_GPIO5 */ 246ccff0064SStefan Binding #define CS8409_CS42L42_INT GENMASK(4, 4) /* CS8409_GPIO4 */ 247ccff0064SStefan Binding #define CS8409_CS42L42_HP_PIN_NID CS8409_PIN_ASP1_TRANSMITTER_A 248ccff0064SStefan Binding #define CS8409_CS42L42_SPK_PIN_NID CS8409_PIN_ASP2_TRANSMITTER_A 249ccff0064SStefan Binding #define CS8409_CS42L42_AMIC_PIN_NID CS8409_PIN_ASP1_RECEIVER_A 250ccff0064SStefan Binding #define CS8409_CS42L42_DMIC_PIN_NID CS8409_PIN_DMIC1_IN 251ccff0064SStefan Binding #define CS8409_CS42L42_DMIC_ADC_PIN_NID CS8409_PIN_DMIC1 2528c70461bSLucas Tanure 25320e50772SLucas Tanure /* Dolphin */ 25420e50772SLucas Tanure 25520e50772SLucas Tanure #define DOLPHIN_C0_I2C_ADDR (0x48 << 1) 25620e50772SLucas Tanure #define DOLPHIN_C1_I2C_ADDR (0x49 << 1) 25720e50772SLucas Tanure #define DOLPHIN_HP_PIN_NID CS8409_PIN_ASP1_TRANSMITTER_A 25820e50772SLucas Tanure #define DOLPHIN_LO_PIN_NID CS8409_PIN_ASP1_TRANSMITTER_B 25920e50772SLucas Tanure #define DOLPHIN_AMIC_PIN_NID CS8409_PIN_ASP1_RECEIVER_A 26020e50772SLucas Tanure 26120e50772SLucas Tanure #define DOLPHIN_C0_INT GENMASK(4, 4) 26220e50772SLucas Tanure #define DOLPHIN_C1_INT GENMASK(0, 0) 26320e50772SLucas Tanure #define DOLPHIN_C0_RESET GENMASK(5, 5) 26420e50772SLucas Tanure #define DOLPHIN_C1_RESET GENMASK(1, 1) 26520e50772SLucas Tanure #define DOLPHIN_WAKE (DOLPHIN_C0_INT | DOLPHIN_C1_INT) 26620e50772SLucas Tanure 2678c70461bSLucas Tanure enum { 2688c70461bSLucas Tanure CS8409_BULLSEYE, 2698c70461bSLucas Tanure CS8409_WARLOCK, 2708c70461bSLucas Tanure CS8409_CYBORG, 2718c70461bSLucas Tanure CS8409_FIXUPS, 27220e50772SLucas Tanure CS8409_DOLPHIN, 27320e50772SLucas Tanure CS8409_DOLPHIN_FIXUPS, 2748c70461bSLucas Tanure }; 2758c70461bSLucas Tanure 276b2a88774SLucas Tanure enum { 27724f7ac3dSLucas Tanure CS8409_CODEC0, 27820e50772SLucas Tanure CS8409_CODEC1 27924f7ac3dSLucas Tanure }; 28024f7ac3dSLucas Tanure 28124f7ac3dSLucas Tanure enum { 282b2a88774SLucas Tanure CS42L42_VOL_ADC, 283b2a88774SLucas Tanure CS42L42_VOL_DAC, 284b2a88774SLucas Tanure }; 285b2a88774SLucas Tanure 2867482ec71SStefan Binding #define CS42L42_ADC_VOL_OFFSET (CS42L42_VOL_ADC) 2877482ec71SStefan Binding #define CS42L42_DAC_CH0_VOL_OFFSET (CS42L42_VOL_DAC) 2887482ec71SStefan Binding #define CS42L42_DAC_CH1_VOL_OFFSET (CS42L42_VOL_DAC + 1) 2897482ec71SStefan Binding 2908c70461bSLucas Tanure struct cs8409_i2c_param { 2918c70461bSLucas Tanure unsigned int addr; 292165b81c4SLucas Tanure unsigned int value; 2938c70461bSLucas Tanure }; 2948c70461bSLucas Tanure 2958c70461bSLucas Tanure struct cs8409_cir_param { 2968c70461bSLucas Tanure unsigned int nid; 2978c70461bSLucas Tanure unsigned int cir; 2988c70461bSLucas Tanure unsigned int coeff; 2998c70461bSLucas Tanure }; 3008c70461bSLucas Tanure 30124f7ac3dSLucas Tanure struct sub_codec { 30224f7ac3dSLucas Tanure struct hda_codec *codec; 30324f7ac3dSLucas Tanure unsigned int addr; 30424f7ac3dSLucas Tanure unsigned int reset_gpio; 30524f7ac3dSLucas Tanure unsigned int irq_mask; 30624f7ac3dSLucas Tanure const struct cs8409_i2c_param *init_seq; 30724f7ac3dSLucas Tanure unsigned int init_seq_num; 30824f7ac3dSLucas Tanure 30924f7ac3dSLucas Tanure unsigned int hp_jack_in:1; 31024f7ac3dSLucas Tanure unsigned int mic_jack_in:1; 31157f23424SChristian A. Ehrhardt unsigned int force_status_change:1; 31224f7ac3dSLucas Tanure unsigned int suspended:1; 31324f7ac3dSLucas Tanure unsigned int paged:1; 31424f7ac3dSLucas Tanure unsigned int last_page; 31524f7ac3dSLucas Tanure unsigned int hsbias_hiz; 31624f7ac3dSLucas Tanure unsigned int full_scale_vol:1; 317404e770aSStefan Binding unsigned int no_type_dect:1; 31824f7ac3dSLucas Tanure 31924f7ac3dSLucas Tanure s8 vol[CS42L42_VOLUMES]; 32024f7ac3dSLucas Tanure }; 32124f7ac3dSLucas Tanure 3228c70461bSLucas Tanure struct cs8409_spec { 3238c70461bSLucas Tanure struct hda_gen_spec gen; 324647d50a0SLucas Tanure struct hda_codec *codec; 3258c70461bSLucas Tanure 32624f7ac3dSLucas Tanure struct sub_codec *scodecs[CS8409_MAX_CODECS]; 32724f7ac3dSLucas Tanure unsigned int num_scodecs; 32824f7ac3dSLucas Tanure 3298c70461bSLucas Tanure unsigned int gpio_mask; 3308c70461bSLucas Tanure unsigned int gpio_dir; 3318c70461bSLucas Tanure unsigned int gpio_data; 3328c70461bSLucas Tanure 333165b81c4SLucas Tanure struct mutex i2c_mux; 334647d50a0SLucas Tanure unsigned int i2c_clck_enabled; 335d395fd78SLucas Tanure unsigned int dev_addr; 336647d50a0SLucas Tanure struct delayed_work i2c_clk_work; 3378c70461bSLucas Tanure 3387482ec71SStefan Binding unsigned int playback_started:1; 3397482ec71SStefan Binding unsigned int capture_started:1; 340424e531bSStefan Binding unsigned int init_done:1; 341424e531bSStefan Binding unsigned int build_ctrl_done:1; 3427482ec71SStefan Binding 3438c70461bSLucas Tanure /* verb exec op override */ 3448c70461bSLucas Tanure int (*exec_verb)(struct hdac_device *dev, unsigned int cmd, unsigned int flags, 3458c70461bSLucas Tanure unsigned int *res); 3468c70461bSLucas Tanure }; 3478c70461bSLucas Tanure 348b2a88774SLucas Tanure extern const struct snd_kcontrol_new cs42l42_dac_volume_mixer; 349b2a88774SLucas Tanure extern const struct snd_kcontrol_new cs42l42_adc_volume_mixer; 350b2a88774SLucas Tanure 351636eb9d2SLucas Tanure int cs42l42_volume_info(struct snd_kcontrol *kctrl, struct snd_ctl_elem_info *uinfo); 352636eb9d2SLucas Tanure int cs42l42_volume_get(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl); 353636eb9d2SLucas Tanure int cs42l42_volume_put(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl); 354b2a88774SLucas Tanure 355fed0aacaSStefan Binding extern const struct hda_pcm_stream cs42l42_48k_pcm_analog_playback; 356fed0aacaSStefan Binding extern const struct hda_pcm_stream cs42l42_48k_pcm_analog_capture; 3579e7647b5SLucas Tanure extern const struct snd_pci_quirk cs8409_fixup_tbl[]; 3589e7647b5SLucas Tanure extern const struct hda_model_fixup cs8409_models[]; 3599e7647b5SLucas Tanure extern const struct hda_fixup cs8409_fixups[]; 3609e7647b5SLucas Tanure extern const struct hda_verb cs8409_cs42l42_init_verbs[]; 3619e7647b5SLucas Tanure extern const struct hda_pintbl cs8409_cs42l42_pincfgs[]; 3629e7647b5SLucas Tanure extern const struct cs8409_cir_param cs8409_cs42l42_hw_cfg[]; 3639e7647b5SLucas Tanure extern const struct cs8409_cir_param cs8409_cs42l42_bullseye_atn[]; 36424f7ac3dSLucas Tanure extern struct sub_codec cs8409_cs42l42_codec; 3659e7647b5SLucas Tanure 36620e50772SLucas Tanure extern const struct hda_verb dolphin_init_verbs[]; 36720e50772SLucas Tanure extern const struct hda_pintbl dolphin_pincfgs[]; 36820e50772SLucas Tanure extern const struct cs8409_cir_param dolphin_hw_cfg[]; 36920e50772SLucas Tanure extern struct sub_codec dolphin_cs42l42_0; 37020e50772SLucas Tanure extern struct sub_codec dolphin_cs42l42_1; 37120e50772SLucas Tanure 3729e7647b5SLucas Tanure void cs8409_cs42l42_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action); 37320e50772SLucas Tanure void dolphin_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action); 3749e7647b5SLucas Tanure 3758c70461bSLucas Tanure #endif 376