1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * HD audio interface patch for Cirrus Logic CS420x chip 4 * 5 * Copyright (c) 2009 Takashi Iwai <tiwai@suse.de> 6 */ 7 8 #include <linux/init.h> 9 #include <linux/slab.h> 10 #include <linux/module.h> 11 #include <sound/core.h> 12 #include <linux/mutex.h> 13 #include <linux/pci.h> 14 #include <sound/tlv.h> 15 #include <sound/hda_codec.h> 16 #include "hda_local.h" 17 #include "hda_auto_parser.h" 18 #include "hda_jack.h" 19 #include "hda_generic.h" 20 21 /* 22 */ 23 24 #define CS42L42_HP_CH (2U) 25 #define CS42L42_HS_MIC_CH (1U) 26 27 struct cs_spec { 28 struct hda_gen_spec gen; 29 30 unsigned int gpio_mask; 31 unsigned int gpio_dir; 32 unsigned int gpio_data; 33 unsigned int gpio_eapd_hp; /* EAPD GPIO bit for headphones */ 34 unsigned int gpio_eapd_speaker; /* EAPD GPIO bit for speakers */ 35 36 /* CS421x */ 37 unsigned int spdif_detect:1; 38 unsigned int spdif_present:1; 39 unsigned int sense_b:1; 40 hda_nid_t vendor_nid; 41 42 /* for MBP SPDIF control */ 43 int (*spdif_sw_put)(struct snd_kcontrol *kcontrol, 44 struct snd_ctl_elem_value *ucontrol); 45 46 unsigned int cs42l42_hp_jack_in:1; 47 unsigned int cs42l42_mic_jack_in:1; 48 unsigned int cs42l42_volume_init:1; 49 char cs42l42_hp_volume[CS42L42_HP_CH]; 50 char cs42l42_hs_mic_volume[CS42L42_HS_MIC_CH]; 51 52 struct mutex cs8409_i2c_mux; 53 54 /* verb exec op override */ 55 int (*exec_verb)(struct hdac_device *dev, unsigned int cmd, 56 unsigned int flags, unsigned int *res); 57 }; 58 59 /* available models with CS420x */ 60 enum { 61 CS420X_MBP53, 62 CS420X_MBP55, 63 CS420X_IMAC27, 64 CS420X_GPIO_13, 65 CS420X_GPIO_23, 66 CS420X_MBP101, 67 CS420X_MBP81, 68 CS420X_MBA42, 69 CS420X_AUTO, 70 /* aliases */ 71 CS420X_IMAC27_122 = CS420X_GPIO_23, 72 CS420X_APPLE = CS420X_GPIO_13, 73 }; 74 75 /* CS421x boards */ 76 enum { 77 CS421X_CDB4210, 78 CS421X_SENSE_B, 79 CS421X_STUMPY, 80 }; 81 82 /* Vendor-specific processing widget */ 83 #define CS420X_VENDOR_NID 0x11 84 #define CS_DIG_OUT1_PIN_NID 0x10 85 #define CS_DIG_OUT2_PIN_NID 0x15 86 #define CS_DMIC1_PIN_NID 0x0e 87 #define CS_DMIC2_PIN_NID 0x12 88 89 /* coef indices */ 90 #define IDX_SPDIF_STAT 0x0000 91 #define IDX_SPDIF_CTL 0x0001 92 #define IDX_ADC_CFG 0x0002 93 /* SZC bitmask, 4 modes below: 94 * 0 = immediate, 95 * 1 = digital immediate, analog zero-cross 96 * 2 = digtail & analog soft-ramp 97 * 3 = digital soft-ramp, analog zero-cross 98 */ 99 #define CS_COEF_ADC_SZC_MASK (3 << 0) 100 #define CS_COEF_ADC_MIC_SZC_MODE (3 << 0) /* SZC setup for mic */ 101 #define CS_COEF_ADC_LI_SZC_MODE (3 << 0) /* SZC setup for line-in */ 102 /* PGA mode: 0 = differential, 1 = signle-ended */ 103 #define CS_COEF_ADC_MIC_PGA_MODE (1 << 5) /* PGA setup for mic */ 104 #define CS_COEF_ADC_LI_PGA_MODE (1 << 6) /* PGA setup for line-in */ 105 #define IDX_DAC_CFG 0x0003 106 /* SZC bitmask, 4 modes below: 107 * 0 = Immediate 108 * 1 = zero-cross 109 * 2 = soft-ramp 110 * 3 = soft-ramp on zero-cross 111 */ 112 #define CS_COEF_DAC_HP_SZC_MODE (3 << 0) /* nid 0x02 */ 113 #define CS_COEF_DAC_LO_SZC_MODE (3 << 2) /* nid 0x03 */ 114 #define CS_COEF_DAC_SPK_SZC_MODE (3 << 4) /* nid 0x04 */ 115 116 #define IDX_BEEP_CFG 0x0004 117 /* 0x0008 - test reg key */ 118 /* 0x0009 - 0x0014 -> 12 test regs */ 119 /* 0x0015 - visibility reg */ 120 121 /* Cirrus Logic CS4208 */ 122 #define CS4208_VENDOR_NID 0x24 123 124 /* 125 * Cirrus Logic CS4210 126 * 127 * 1 DAC => HP(sense) / Speakers, 128 * 1 ADC <= LineIn(sense) / MicIn / DMicIn, 129 * 1 SPDIF OUT => SPDIF Trasmitter(sense) 130 */ 131 #define CS4210_DAC_NID 0x02 132 #define CS4210_ADC_NID 0x03 133 #define CS4210_VENDOR_NID 0x0B 134 #define CS421X_DMIC_PIN_NID 0x09 /* Port E */ 135 #define CS421X_SPDIF_PIN_NID 0x0A /* Port H */ 136 137 #define CS421X_IDX_DEV_CFG 0x01 138 #define CS421X_IDX_ADC_CFG 0x02 139 #define CS421X_IDX_DAC_CFG 0x03 140 #define CS421X_IDX_SPK_CTL 0x04 141 142 /* Cirrus Logic CS4213 is like CS4210 but does not have SPDIF input/output */ 143 #define CS4213_VENDOR_NID 0x09 144 145 146 static inline int cs_vendor_coef_get(struct hda_codec *codec, unsigned int idx) 147 { 148 struct cs_spec *spec = codec->spec; 149 150 snd_hda_codec_write(codec, spec->vendor_nid, 0, 151 AC_VERB_SET_COEF_INDEX, idx); 152 return snd_hda_codec_read(codec, spec->vendor_nid, 0, 153 AC_VERB_GET_PROC_COEF, 0); 154 } 155 156 static inline void cs_vendor_coef_set(struct hda_codec *codec, unsigned int idx, 157 unsigned int coef) 158 { 159 struct cs_spec *spec = codec->spec; 160 161 snd_hda_codec_write(codec, spec->vendor_nid, 0, 162 AC_VERB_SET_COEF_INDEX, idx); 163 snd_hda_codec_write(codec, spec->vendor_nid, 0, 164 AC_VERB_SET_PROC_COEF, coef); 165 } 166 167 /* 168 * auto-mute and auto-mic switching 169 * CS421x auto-output redirecting 170 * HP/SPK/SPDIF 171 */ 172 173 static void cs_automute(struct hda_codec *codec) 174 { 175 struct cs_spec *spec = codec->spec; 176 177 /* mute HPs if spdif jack (SENSE_B) is present */ 178 spec->gen.master_mute = !!(spec->spdif_present && spec->sense_b); 179 180 snd_hda_gen_update_outputs(codec); 181 182 if (spec->gpio_eapd_hp || spec->gpio_eapd_speaker) { 183 if (spec->gen.automute_speaker) 184 spec->gpio_data = spec->gen.hp_jack_present ? 185 spec->gpio_eapd_hp : spec->gpio_eapd_speaker; 186 else 187 spec->gpio_data = 188 spec->gpio_eapd_hp | spec->gpio_eapd_speaker; 189 snd_hda_codec_write(codec, 0x01, 0, 190 AC_VERB_SET_GPIO_DATA, spec->gpio_data); 191 } 192 } 193 194 static bool is_active_pin(struct hda_codec *codec, hda_nid_t nid) 195 { 196 unsigned int val; 197 198 val = snd_hda_codec_get_pincfg(codec, nid); 199 return (get_defcfg_connect(val) != AC_JACK_PORT_NONE); 200 } 201 202 static void init_input_coef(struct hda_codec *codec) 203 { 204 struct cs_spec *spec = codec->spec; 205 unsigned int coef; 206 207 /* CS420x has multiple ADC, CS421x has single ADC */ 208 if (spec->vendor_nid == CS420X_VENDOR_NID) { 209 coef = cs_vendor_coef_get(codec, IDX_BEEP_CFG); 210 if (is_active_pin(codec, CS_DMIC2_PIN_NID)) 211 coef |= 1 << 4; /* DMIC2 2 chan on, GPIO1 off */ 212 if (is_active_pin(codec, CS_DMIC1_PIN_NID)) 213 coef |= 1 << 3; /* DMIC1 2 chan on, GPIO0 off 214 * No effect if SPDIF_OUT2 is 215 * selected in IDX_SPDIF_CTL. 216 */ 217 218 cs_vendor_coef_set(codec, IDX_BEEP_CFG, coef); 219 } 220 } 221 222 static const struct hda_verb cs_coef_init_verbs[] = { 223 {0x11, AC_VERB_SET_PROC_STATE, 1}, 224 {0x11, AC_VERB_SET_COEF_INDEX, IDX_DAC_CFG}, 225 {0x11, AC_VERB_SET_PROC_COEF, 226 (0x002a /* DAC1/2/3 SZCMode Soft Ramp */ 227 | 0x0040 /* Mute DACs on FIFO error */ 228 | 0x1000 /* Enable DACs High Pass Filter */ 229 | 0x0400 /* Disable Coefficient Auto increment */ 230 )}, 231 /* ADC1/2 - Digital and Analog Soft Ramp */ 232 {0x11, AC_VERB_SET_COEF_INDEX, IDX_ADC_CFG}, 233 {0x11, AC_VERB_SET_PROC_COEF, 0x000a}, 234 /* Beep */ 235 {0x11, AC_VERB_SET_COEF_INDEX, IDX_BEEP_CFG}, 236 {0x11, AC_VERB_SET_PROC_COEF, 0x0007}, /* Enable Beep thru DAC1/2/3 */ 237 238 {} /* terminator */ 239 }; 240 241 static const struct hda_verb cs4208_coef_init_verbs[] = { 242 {0x01, AC_VERB_SET_POWER_STATE, 0x00}, /* AFG: D0 */ 243 {0x24, AC_VERB_SET_PROC_STATE, 0x01}, /* VPW: processing on */ 244 {0x24, AC_VERB_SET_COEF_INDEX, 0x0033}, 245 {0x24, AC_VERB_SET_PROC_COEF, 0x0001}, /* A1 ICS */ 246 {0x24, AC_VERB_SET_COEF_INDEX, 0x0034}, 247 {0x24, AC_VERB_SET_PROC_COEF, 0x1C01}, /* A1 Enable, A Thresh = 300mV */ 248 {} /* terminator */ 249 }; 250 251 /* Errata: CS4207 rev C0/C1/C2 Silicon 252 * 253 * http://www.cirrus.com/en/pubs/errata/ER880C3.pdf 254 * 255 * 6. At high temperature (TA > +85°C), the digital supply current (IVD) 256 * may be excessive (up to an additional 200 μA), which is most easily 257 * observed while the part is being held in reset (RESET# active low). 258 * 259 * Root Cause: At initial powerup of the device, the logic that drives 260 * the clock and write enable to the S/PDIF SRC RAMs is not properly 261 * initialized. 262 * Certain random patterns will cause a steady leakage current in those 263 * RAM cells. The issue will resolve once the SRCs are used (turned on). 264 * 265 * Workaround: The following verb sequence briefly turns on the S/PDIF SRC 266 * blocks, which will alleviate the issue. 267 */ 268 269 static const struct hda_verb cs_errata_init_verbs[] = { 270 {0x01, AC_VERB_SET_POWER_STATE, 0x00}, /* AFG: D0 */ 271 {0x11, AC_VERB_SET_PROC_STATE, 0x01}, /* VPW: processing on */ 272 273 {0x11, AC_VERB_SET_COEF_INDEX, 0x0008}, 274 {0x11, AC_VERB_SET_PROC_COEF, 0x9999}, 275 {0x11, AC_VERB_SET_COEF_INDEX, 0x0017}, 276 {0x11, AC_VERB_SET_PROC_COEF, 0xa412}, 277 {0x11, AC_VERB_SET_COEF_INDEX, 0x0001}, 278 {0x11, AC_VERB_SET_PROC_COEF, 0x0009}, 279 280 {0x07, AC_VERB_SET_POWER_STATE, 0x00}, /* S/PDIF Rx: D0 */ 281 {0x08, AC_VERB_SET_POWER_STATE, 0x00}, /* S/PDIF Tx: D0 */ 282 283 {0x11, AC_VERB_SET_COEF_INDEX, 0x0017}, 284 {0x11, AC_VERB_SET_PROC_COEF, 0x2412}, 285 {0x11, AC_VERB_SET_COEF_INDEX, 0x0008}, 286 {0x11, AC_VERB_SET_PROC_COEF, 0x0000}, 287 {0x11, AC_VERB_SET_COEF_INDEX, 0x0001}, 288 {0x11, AC_VERB_SET_PROC_COEF, 0x0008}, 289 {0x11, AC_VERB_SET_PROC_STATE, 0x00}, 290 {} /* terminator */ 291 }; 292 293 /* SPDIF setup */ 294 static void init_digital_coef(struct hda_codec *codec) 295 { 296 unsigned int coef; 297 298 coef = 0x0002; /* SRC_MUTE soft-mute on SPDIF (if no lock) */ 299 coef |= 0x0008; /* Replace with mute on error */ 300 if (is_active_pin(codec, CS_DIG_OUT2_PIN_NID)) 301 coef |= 0x4000; /* RX to TX1 or TX2 Loopthru / SPDIF2 302 * SPDIF_OUT2 is shared with GPIO1 and 303 * DMIC_SDA2. 304 */ 305 cs_vendor_coef_set(codec, IDX_SPDIF_CTL, coef); 306 } 307 308 static int cs_init(struct hda_codec *codec) 309 { 310 struct cs_spec *spec = codec->spec; 311 312 if (spec->vendor_nid == CS420X_VENDOR_NID) { 313 /* init_verb sequence for C0/C1/C2 errata*/ 314 snd_hda_sequence_write(codec, cs_errata_init_verbs); 315 snd_hda_sequence_write(codec, cs_coef_init_verbs); 316 } else if (spec->vendor_nid == CS4208_VENDOR_NID) { 317 snd_hda_sequence_write(codec, cs4208_coef_init_verbs); 318 } 319 320 snd_hda_gen_init(codec); 321 322 if (spec->gpio_mask) { 323 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_MASK, 324 spec->gpio_mask); 325 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DIRECTION, 326 spec->gpio_dir); 327 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 328 spec->gpio_data); 329 } 330 331 if (spec->vendor_nid == CS420X_VENDOR_NID) { 332 init_input_coef(codec); 333 init_digital_coef(codec); 334 } 335 336 return 0; 337 } 338 339 static int cs_build_controls(struct hda_codec *codec) 340 { 341 int err; 342 343 err = snd_hda_gen_build_controls(codec); 344 if (err < 0) 345 return err; 346 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_BUILD); 347 return 0; 348 } 349 350 #define cs_free snd_hda_gen_free 351 352 static const struct hda_codec_ops cs_patch_ops = { 353 .build_controls = cs_build_controls, 354 .build_pcms = snd_hda_gen_build_pcms, 355 .init = cs_init, 356 .free = cs_free, 357 .unsol_event = snd_hda_jack_unsol_event, 358 }; 359 360 static int cs_parse_auto_config(struct hda_codec *codec) 361 { 362 struct cs_spec *spec = codec->spec; 363 int err; 364 int i; 365 366 err = snd_hda_parse_pin_defcfg(codec, &spec->gen.autocfg, NULL, 0); 367 if (err < 0) 368 return err; 369 370 err = snd_hda_gen_parse_auto_config(codec, &spec->gen.autocfg); 371 if (err < 0) 372 return err; 373 374 /* keep the ADCs powered up when it's dynamically switchable */ 375 if (spec->gen.dyn_adc_switch) { 376 unsigned int done = 0; 377 378 for (i = 0; i < spec->gen.input_mux.num_items; i++) { 379 int idx = spec->gen.dyn_adc_idx[i]; 380 381 if (done & (1 << idx)) 382 continue; 383 snd_hda_gen_fix_pin_power(codec, 384 spec->gen.adc_nids[idx]); 385 done |= 1 << idx; 386 } 387 } 388 389 return 0; 390 } 391 392 static const struct hda_model_fixup cs420x_models[] = { 393 { .id = CS420X_MBP53, .name = "mbp53" }, 394 { .id = CS420X_MBP55, .name = "mbp55" }, 395 { .id = CS420X_IMAC27, .name = "imac27" }, 396 { .id = CS420X_IMAC27_122, .name = "imac27_122" }, 397 { .id = CS420X_APPLE, .name = "apple" }, 398 { .id = CS420X_MBP101, .name = "mbp101" }, 399 { .id = CS420X_MBP81, .name = "mbp81" }, 400 { .id = CS420X_MBA42, .name = "mba42" }, 401 {} 402 }; 403 404 static const struct snd_pci_quirk cs420x_fixup_tbl[] = { 405 SND_PCI_QUIRK(0x10de, 0x0ac0, "MacBookPro 5,3", CS420X_MBP53), 406 SND_PCI_QUIRK(0x10de, 0x0d94, "MacBookAir 3,1(2)", CS420X_MBP55), 407 SND_PCI_QUIRK(0x10de, 0xcb79, "MacBookPro 5,5", CS420X_MBP55), 408 SND_PCI_QUIRK(0x10de, 0xcb89, "MacBookPro 7,1", CS420X_MBP55), 409 /* this conflicts with too many other models */ 410 /*SND_PCI_QUIRK(0x8086, 0x7270, "IMac 27 Inch", CS420X_IMAC27),*/ 411 412 /* codec SSID */ 413 SND_PCI_QUIRK(0x106b, 0x0600, "iMac 14,1", CS420X_IMAC27_122), 414 SND_PCI_QUIRK(0x106b, 0x1c00, "MacBookPro 8,1", CS420X_MBP81), 415 SND_PCI_QUIRK(0x106b, 0x2000, "iMac 12,2", CS420X_IMAC27_122), 416 SND_PCI_QUIRK(0x106b, 0x2800, "MacBookPro 10,1", CS420X_MBP101), 417 SND_PCI_QUIRK(0x106b, 0x5600, "MacBookAir 5,2", CS420X_MBP81), 418 SND_PCI_QUIRK(0x106b, 0x5b00, "MacBookAir 4,2", CS420X_MBA42), 419 SND_PCI_QUIRK_VENDOR(0x106b, "Apple", CS420X_APPLE), 420 {} /* terminator */ 421 }; 422 423 static const struct hda_pintbl mbp53_pincfgs[] = { 424 { 0x09, 0x012b4050 }, 425 { 0x0a, 0x90100141 }, 426 { 0x0b, 0x90100140 }, 427 { 0x0c, 0x018b3020 }, 428 { 0x0d, 0x90a00110 }, 429 { 0x0e, 0x400000f0 }, 430 { 0x0f, 0x01cbe030 }, 431 { 0x10, 0x014be060 }, 432 { 0x12, 0x400000f0 }, 433 { 0x15, 0x400000f0 }, 434 {} /* terminator */ 435 }; 436 437 static const struct hda_pintbl mbp55_pincfgs[] = { 438 { 0x09, 0x012b4030 }, 439 { 0x0a, 0x90100121 }, 440 { 0x0b, 0x90100120 }, 441 { 0x0c, 0x400000f0 }, 442 { 0x0d, 0x90a00110 }, 443 { 0x0e, 0x400000f0 }, 444 { 0x0f, 0x400000f0 }, 445 { 0x10, 0x014be040 }, 446 { 0x12, 0x400000f0 }, 447 { 0x15, 0x400000f0 }, 448 {} /* terminator */ 449 }; 450 451 static const struct hda_pintbl imac27_pincfgs[] = { 452 { 0x09, 0x012b4050 }, 453 { 0x0a, 0x90100140 }, 454 { 0x0b, 0x90100142 }, 455 { 0x0c, 0x018b3020 }, 456 { 0x0d, 0x90a00110 }, 457 { 0x0e, 0x400000f0 }, 458 { 0x0f, 0x01cbe030 }, 459 { 0x10, 0x014be060 }, 460 { 0x12, 0x01ab9070 }, 461 { 0x15, 0x400000f0 }, 462 {} /* terminator */ 463 }; 464 465 static const struct hda_pintbl mbp101_pincfgs[] = { 466 { 0x0d, 0x40ab90f0 }, 467 { 0x0e, 0x90a600f0 }, 468 { 0x12, 0x50a600f0 }, 469 {} /* terminator */ 470 }; 471 472 static const struct hda_pintbl mba42_pincfgs[] = { 473 { 0x09, 0x012b4030 }, /* HP */ 474 { 0x0a, 0x400000f0 }, 475 { 0x0b, 0x90100120 }, /* speaker */ 476 { 0x0c, 0x400000f0 }, 477 { 0x0d, 0x90a00110 }, /* mic */ 478 { 0x0e, 0x400000f0 }, 479 { 0x0f, 0x400000f0 }, 480 { 0x10, 0x400000f0 }, 481 { 0x12, 0x400000f0 }, 482 { 0x15, 0x400000f0 }, 483 {} /* terminator */ 484 }; 485 486 static const struct hda_pintbl mba6_pincfgs[] = { 487 { 0x10, 0x032120f0 }, /* HP */ 488 { 0x11, 0x500000f0 }, 489 { 0x12, 0x90100010 }, /* Speaker */ 490 { 0x13, 0x500000f0 }, 491 { 0x14, 0x500000f0 }, 492 { 0x15, 0x770000f0 }, 493 { 0x16, 0x770000f0 }, 494 { 0x17, 0x430000f0 }, 495 { 0x18, 0x43ab9030 }, /* Mic */ 496 { 0x19, 0x770000f0 }, 497 { 0x1a, 0x770000f0 }, 498 { 0x1b, 0x770000f0 }, 499 { 0x1c, 0x90a00090 }, 500 { 0x1d, 0x500000f0 }, 501 { 0x1e, 0x500000f0 }, 502 { 0x1f, 0x500000f0 }, 503 { 0x20, 0x500000f0 }, 504 { 0x21, 0x430000f0 }, 505 { 0x22, 0x430000f0 }, 506 {} /* terminator */ 507 }; 508 509 static void cs420x_fixup_gpio_13(struct hda_codec *codec, 510 const struct hda_fixup *fix, int action) 511 { 512 if (action == HDA_FIXUP_ACT_PRE_PROBE) { 513 struct cs_spec *spec = codec->spec; 514 515 spec->gpio_eapd_hp = 2; /* GPIO1 = headphones */ 516 spec->gpio_eapd_speaker = 8; /* GPIO3 = speakers */ 517 spec->gpio_mask = spec->gpio_dir = 518 spec->gpio_eapd_hp | spec->gpio_eapd_speaker; 519 } 520 } 521 522 static void cs420x_fixup_gpio_23(struct hda_codec *codec, 523 const struct hda_fixup *fix, int action) 524 { 525 if (action == HDA_FIXUP_ACT_PRE_PROBE) { 526 struct cs_spec *spec = codec->spec; 527 528 spec->gpio_eapd_hp = 4; /* GPIO2 = headphones */ 529 spec->gpio_eapd_speaker = 8; /* GPIO3 = speakers */ 530 spec->gpio_mask = spec->gpio_dir = 531 spec->gpio_eapd_hp | spec->gpio_eapd_speaker; 532 } 533 } 534 535 static const struct hda_fixup cs420x_fixups[] = { 536 [CS420X_MBP53] = { 537 .type = HDA_FIXUP_PINS, 538 .v.pins = mbp53_pincfgs, 539 .chained = true, 540 .chain_id = CS420X_APPLE, 541 }, 542 [CS420X_MBP55] = { 543 .type = HDA_FIXUP_PINS, 544 .v.pins = mbp55_pincfgs, 545 .chained = true, 546 .chain_id = CS420X_GPIO_13, 547 }, 548 [CS420X_IMAC27] = { 549 .type = HDA_FIXUP_PINS, 550 .v.pins = imac27_pincfgs, 551 .chained = true, 552 .chain_id = CS420X_GPIO_13, 553 }, 554 [CS420X_GPIO_13] = { 555 .type = HDA_FIXUP_FUNC, 556 .v.func = cs420x_fixup_gpio_13, 557 }, 558 [CS420X_GPIO_23] = { 559 .type = HDA_FIXUP_FUNC, 560 .v.func = cs420x_fixup_gpio_23, 561 }, 562 [CS420X_MBP101] = { 563 .type = HDA_FIXUP_PINS, 564 .v.pins = mbp101_pincfgs, 565 .chained = true, 566 .chain_id = CS420X_GPIO_13, 567 }, 568 [CS420X_MBP81] = { 569 .type = HDA_FIXUP_VERBS, 570 .v.verbs = (const struct hda_verb[]) { 571 /* internal mic ADC2: right only, single ended */ 572 {0x11, AC_VERB_SET_COEF_INDEX, IDX_ADC_CFG}, 573 {0x11, AC_VERB_SET_PROC_COEF, 0x102a}, 574 {} 575 }, 576 .chained = true, 577 .chain_id = CS420X_GPIO_13, 578 }, 579 [CS420X_MBA42] = { 580 .type = HDA_FIXUP_PINS, 581 .v.pins = mba42_pincfgs, 582 .chained = true, 583 .chain_id = CS420X_GPIO_13, 584 }, 585 }; 586 587 static struct cs_spec *cs_alloc_spec(struct hda_codec *codec, int vendor_nid) 588 { 589 struct cs_spec *spec; 590 591 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 592 if (!spec) 593 return NULL; 594 codec->spec = spec; 595 spec->vendor_nid = vendor_nid; 596 codec->power_save_node = 1; 597 snd_hda_gen_spec_init(&spec->gen); 598 599 return spec; 600 } 601 602 static int patch_cs420x(struct hda_codec *codec) 603 { 604 struct cs_spec *spec; 605 int err; 606 607 spec = cs_alloc_spec(codec, CS420X_VENDOR_NID); 608 if (!spec) 609 return -ENOMEM; 610 611 codec->patch_ops = cs_patch_ops; 612 spec->gen.automute_hook = cs_automute; 613 codec->single_adc_amp = 1; 614 615 snd_hda_pick_fixup(codec, cs420x_models, cs420x_fixup_tbl, 616 cs420x_fixups); 617 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE); 618 619 err = cs_parse_auto_config(codec); 620 if (err < 0) 621 goto error; 622 623 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE); 624 625 return 0; 626 627 error: 628 cs_free(codec); 629 return err; 630 } 631 632 /* 633 * CS4208 support: 634 * Its layout is no longer compatible with CS4206/CS4207 635 */ 636 enum { 637 CS4208_MAC_AUTO, 638 CS4208_MBA6, 639 CS4208_MBP11, 640 CS4208_MACMINI, 641 CS4208_GPIO0, 642 }; 643 644 static const struct hda_model_fixup cs4208_models[] = { 645 { .id = CS4208_GPIO0, .name = "gpio0" }, 646 { .id = CS4208_MBA6, .name = "mba6" }, 647 { .id = CS4208_MBP11, .name = "mbp11" }, 648 { .id = CS4208_MACMINI, .name = "macmini" }, 649 {} 650 }; 651 652 static const struct snd_pci_quirk cs4208_fixup_tbl[] = { 653 SND_PCI_QUIRK_VENDOR(0x106b, "Apple", CS4208_MAC_AUTO), 654 {} /* terminator */ 655 }; 656 657 /* codec SSID matching */ 658 static const struct snd_pci_quirk cs4208_mac_fixup_tbl[] = { 659 SND_PCI_QUIRK(0x106b, 0x5e00, "MacBookPro 11,2", CS4208_MBP11), 660 SND_PCI_QUIRK(0x106b, 0x6c00, "MacMini 7,1", CS4208_MACMINI), 661 SND_PCI_QUIRK(0x106b, 0x7100, "MacBookAir 6,1", CS4208_MBA6), 662 SND_PCI_QUIRK(0x106b, 0x7200, "MacBookAir 6,2", CS4208_MBA6), 663 SND_PCI_QUIRK(0x106b, 0x7b00, "MacBookPro 12,1", CS4208_MBP11), 664 {} /* terminator */ 665 }; 666 667 static void cs4208_fixup_gpio0(struct hda_codec *codec, 668 const struct hda_fixup *fix, int action) 669 { 670 if (action == HDA_FIXUP_ACT_PRE_PROBE) { 671 struct cs_spec *spec = codec->spec; 672 673 spec->gpio_eapd_hp = 0; 674 spec->gpio_eapd_speaker = 1; 675 spec->gpio_mask = spec->gpio_dir = 676 spec->gpio_eapd_hp | spec->gpio_eapd_speaker; 677 } 678 } 679 680 static const struct hda_fixup cs4208_fixups[]; 681 682 /* remap the fixup from codec SSID and apply it */ 683 static void cs4208_fixup_mac(struct hda_codec *codec, 684 const struct hda_fixup *fix, int action) 685 { 686 if (action != HDA_FIXUP_ACT_PRE_PROBE) 687 return; 688 689 codec->fixup_id = HDA_FIXUP_ID_NOT_SET; 690 snd_hda_pick_fixup(codec, NULL, cs4208_mac_fixup_tbl, cs4208_fixups); 691 if (codec->fixup_id == HDA_FIXUP_ID_NOT_SET) 692 codec->fixup_id = CS4208_GPIO0; /* default fixup */ 693 snd_hda_apply_fixup(codec, action); 694 } 695 696 /* MacMini 7,1 has the inverted jack detection */ 697 static void cs4208_fixup_macmini(struct hda_codec *codec, 698 const struct hda_fixup *fix, int action) 699 { 700 static const struct hda_pintbl pincfgs[] = { 701 { 0x18, 0x00ab9150 }, /* mic (audio-in) jack: disable detect */ 702 { 0x21, 0x004be140 }, /* SPDIF: disable detect */ 703 { } 704 }; 705 706 if (action == HDA_FIXUP_ACT_PRE_PROBE) { 707 /* HP pin (0x10) has an inverted detection */ 708 codec->inv_jack_detect = 1; 709 /* disable the bogus Mic and SPDIF jack detections */ 710 snd_hda_apply_pincfgs(codec, pincfgs); 711 } 712 } 713 714 static int cs4208_spdif_sw_put(struct snd_kcontrol *kcontrol, 715 struct snd_ctl_elem_value *ucontrol) 716 { 717 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 718 struct cs_spec *spec = codec->spec; 719 hda_nid_t pin = spec->gen.autocfg.dig_out_pins[0]; 720 int pinctl = ucontrol->value.integer.value[0] ? PIN_OUT : 0; 721 722 snd_hda_set_pin_ctl_cache(codec, pin, pinctl); 723 return spec->spdif_sw_put(kcontrol, ucontrol); 724 } 725 726 /* hook the SPDIF switch */ 727 static void cs4208_fixup_spdif_switch(struct hda_codec *codec, 728 const struct hda_fixup *fix, int action) 729 { 730 if (action == HDA_FIXUP_ACT_BUILD) { 731 struct cs_spec *spec = codec->spec; 732 struct snd_kcontrol *kctl; 733 734 if (!spec->gen.autocfg.dig_out_pins[0]) 735 return; 736 kctl = snd_hda_find_mixer_ctl(codec, "IEC958 Playback Switch"); 737 if (!kctl) 738 return; 739 spec->spdif_sw_put = kctl->put; 740 kctl->put = cs4208_spdif_sw_put; 741 } 742 } 743 744 static const struct hda_fixup cs4208_fixups[] = { 745 [CS4208_MBA6] = { 746 .type = HDA_FIXUP_PINS, 747 .v.pins = mba6_pincfgs, 748 .chained = true, 749 .chain_id = CS4208_GPIO0, 750 }, 751 [CS4208_MBP11] = { 752 .type = HDA_FIXUP_FUNC, 753 .v.func = cs4208_fixup_spdif_switch, 754 .chained = true, 755 .chain_id = CS4208_GPIO0, 756 }, 757 [CS4208_MACMINI] = { 758 .type = HDA_FIXUP_FUNC, 759 .v.func = cs4208_fixup_macmini, 760 .chained = true, 761 .chain_id = CS4208_GPIO0, 762 }, 763 [CS4208_GPIO0] = { 764 .type = HDA_FIXUP_FUNC, 765 .v.func = cs4208_fixup_gpio0, 766 }, 767 [CS4208_MAC_AUTO] = { 768 .type = HDA_FIXUP_FUNC, 769 .v.func = cs4208_fixup_mac, 770 }, 771 }; 772 773 /* correct the 0dB offset of input pins */ 774 static void cs4208_fix_amp_caps(struct hda_codec *codec, hda_nid_t adc) 775 { 776 unsigned int caps; 777 778 caps = query_amp_caps(codec, adc, HDA_INPUT); 779 caps &= ~(AC_AMPCAP_OFFSET); 780 caps |= 0x02; 781 snd_hda_override_amp_caps(codec, adc, HDA_INPUT, caps); 782 } 783 784 static int patch_cs4208(struct hda_codec *codec) 785 { 786 struct cs_spec *spec; 787 int err; 788 789 spec = cs_alloc_spec(codec, CS4208_VENDOR_NID); 790 if (!spec) 791 return -ENOMEM; 792 793 codec->patch_ops = cs_patch_ops; 794 spec->gen.automute_hook = cs_automute; 795 /* exclude NID 0x10 (HP) from output volumes due to different steps */ 796 spec->gen.out_vol_mask = 1ULL << 0x10; 797 798 snd_hda_pick_fixup(codec, cs4208_models, cs4208_fixup_tbl, 799 cs4208_fixups); 800 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE); 801 802 snd_hda_override_wcaps(codec, 0x18, 803 get_wcaps(codec, 0x18) | AC_WCAP_STEREO); 804 cs4208_fix_amp_caps(codec, 0x18); 805 cs4208_fix_amp_caps(codec, 0x1b); 806 cs4208_fix_amp_caps(codec, 0x1c); 807 808 err = cs_parse_auto_config(codec); 809 if (err < 0) 810 goto error; 811 812 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE); 813 814 return 0; 815 816 error: 817 cs_free(codec); 818 return err; 819 } 820 821 /* 822 * Cirrus Logic CS4210 823 * 824 * 1 DAC => HP(sense) / Speakers, 825 * 1 ADC <= LineIn(sense) / MicIn / DMicIn, 826 * 1 SPDIF OUT => SPDIF Trasmitter(sense) 827 */ 828 829 /* CS4210 board names */ 830 static const struct hda_model_fixup cs421x_models[] = { 831 { .id = CS421X_CDB4210, .name = "cdb4210" }, 832 { .id = CS421X_STUMPY, .name = "stumpy" }, 833 {} 834 }; 835 836 static const struct snd_pci_quirk cs421x_fixup_tbl[] = { 837 /* Test Intel board + CDB2410 */ 838 SND_PCI_QUIRK(0x8086, 0x5001, "DP45SG/CDB4210", CS421X_CDB4210), 839 {} /* terminator */ 840 }; 841 842 /* CS4210 board pinconfigs */ 843 /* Default CS4210 (CDB4210)*/ 844 static const struct hda_pintbl cdb4210_pincfgs[] = { 845 { 0x05, 0x0321401f }, 846 { 0x06, 0x90170010 }, 847 { 0x07, 0x03813031 }, 848 { 0x08, 0xb7a70037 }, 849 { 0x09, 0xb7a6003e }, 850 { 0x0a, 0x034510f0 }, 851 {} /* terminator */ 852 }; 853 854 /* Stumpy ChromeBox */ 855 static const struct hda_pintbl stumpy_pincfgs[] = { 856 { 0x05, 0x022120f0 }, 857 { 0x06, 0x901700f0 }, 858 { 0x07, 0x02a120f0 }, 859 { 0x08, 0x77a70037 }, 860 { 0x09, 0x77a6003e }, 861 { 0x0a, 0x434510f0 }, 862 {} /* terminator */ 863 }; 864 865 /* Setup GPIO/SENSE for each board (if used) */ 866 static void cs421x_fixup_sense_b(struct hda_codec *codec, 867 const struct hda_fixup *fix, int action) 868 { 869 struct cs_spec *spec = codec->spec; 870 871 if (action == HDA_FIXUP_ACT_PRE_PROBE) 872 spec->sense_b = 1; 873 } 874 875 static const struct hda_fixup cs421x_fixups[] = { 876 [CS421X_CDB4210] = { 877 .type = HDA_FIXUP_PINS, 878 .v.pins = cdb4210_pincfgs, 879 .chained = true, 880 .chain_id = CS421X_SENSE_B, 881 }, 882 [CS421X_SENSE_B] = { 883 .type = HDA_FIXUP_FUNC, 884 .v.func = cs421x_fixup_sense_b, 885 }, 886 [CS421X_STUMPY] = { 887 .type = HDA_FIXUP_PINS, 888 .v.pins = stumpy_pincfgs, 889 }, 890 }; 891 892 static const struct hda_verb cs421x_coef_init_verbs[] = { 893 {0x0B, AC_VERB_SET_PROC_STATE, 1}, 894 {0x0B, AC_VERB_SET_COEF_INDEX, CS421X_IDX_DEV_CFG}, 895 /* 896 * Disable Coefficient Index Auto-Increment(DAI)=1, 897 * PDREF=0 898 */ 899 {0x0B, AC_VERB_SET_PROC_COEF, 0x0001 }, 900 901 {0x0B, AC_VERB_SET_COEF_INDEX, CS421X_IDX_ADC_CFG}, 902 /* ADC SZCMode = Digital Soft Ramp */ 903 {0x0B, AC_VERB_SET_PROC_COEF, 0x0002 }, 904 905 {0x0B, AC_VERB_SET_COEF_INDEX, CS421X_IDX_DAC_CFG}, 906 {0x0B, AC_VERB_SET_PROC_COEF, 907 (0x0002 /* DAC SZCMode = Digital Soft Ramp */ 908 | 0x0004 /* Mute DAC on FIFO error */ 909 | 0x0008 /* Enable DAC High Pass Filter */ 910 )}, 911 {} /* terminator */ 912 }; 913 914 /* Errata: CS4210 rev A1 Silicon 915 * 916 * http://www.cirrus.com/en/pubs/errata/ 917 * 918 * Description: 919 * 1. Performance degredation is present in the ADC. 920 * 2. Speaker output is not completely muted upon HP detect. 921 * 3. Noise is present when clipping occurs on the amplified 922 * speaker outputs. 923 * 924 * Workaround: 925 * The following verb sequence written to the registers during 926 * initialization will correct the issues listed above. 927 */ 928 929 static const struct hda_verb cs421x_coef_init_verbs_A1_silicon_fixes[] = { 930 {0x0B, AC_VERB_SET_PROC_STATE, 0x01}, /* VPW: processing on */ 931 932 {0x0B, AC_VERB_SET_COEF_INDEX, 0x0006}, 933 {0x0B, AC_VERB_SET_PROC_COEF, 0x9999}, /* Test mode: on */ 934 935 {0x0B, AC_VERB_SET_COEF_INDEX, 0x000A}, 936 {0x0B, AC_VERB_SET_PROC_COEF, 0x14CB}, /* Chop double */ 937 938 {0x0B, AC_VERB_SET_COEF_INDEX, 0x0011}, 939 {0x0B, AC_VERB_SET_PROC_COEF, 0xA2D0}, /* Increase ADC current */ 940 941 {0x0B, AC_VERB_SET_COEF_INDEX, 0x001A}, 942 {0x0B, AC_VERB_SET_PROC_COEF, 0x02A9}, /* Mute speaker */ 943 944 {0x0B, AC_VERB_SET_COEF_INDEX, 0x001B}, 945 {0x0B, AC_VERB_SET_PROC_COEF, 0X1006}, /* Remove noise */ 946 947 {} /* terminator */ 948 }; 949 950 /* Speaker Amp Gain is controlled by the vendor widget's coef 4 */ 951 static const DECLARE_TLV_DB_SCALE(cs421x_speaker_boost_db_scale, 900, 300, 0); 952 953 static int cs421x_boost_vol_info(struct snd_kcontrol *kcontrol, 954 struct snd_ctl_elem_info *uinfo) 955 { 956 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 957 uinfo->count = 1; 958 uinfo->value.integer.min = 0; 959 uinfo->value.integer.max = 3; 960 return 0; 961 } 962 963 static int cs421x_boost_vol_get(struct snd_kcontrol *kcontrol, 964 struct snd_ctl_elem_value *ucontrol) 965 { 966 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 967 968 ucontrol->value.integer.value[0] = 969 cs_vendor_coef_get(codec, CS421X_IDX_SPK_CTL) & 0x0003; 970 return 0; 971 } 972 973 static int cs421x_boost_vol_put(struct snd_kcontrol *kcontrol, 974 struct snd_ctl_elem_value *ucontrol) 975 { 976 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 977 978 unsigned int vol = ucontrol->value.integer.value[0]; 979 unsigned int coef = 980 cs_vendor_coef_get(codec, CS421X_IDX_SPK_CTL); 981 unsigned int original_coef = coef; 982 983 coef &= ~0x0003; 984 coef |= (vol & 0x0003); 985 if (original_coef != coef) { 986 cs_vendor_coef_set(codec, CS421X_IDX_SPK_CTL, coef); 987 return 1; 988 } 989 990 return 0; 991 } 992 993 static const struct snd_kcontrol_new cs421x_speaker_boost_ctl = { 994 995 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 996 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | 997 SNDRV_CTL_ELEM_ACCESS_TLV_READ), 998 .name = "Speaker Boost Playback Volume", 999 .info = cs421x_boost_vol_info, 1000 .get = cs421x_boost_vol_get, 1001 .put = cs421x_boost_vol_put, 1002 .tlv = { .p = cs421x_speaker_boost_db_scale }, 1003 }; 1004 1005 static void cs4210_pinmux_init(struct hda_codec *codec) 1006 { 1007 struct cs_spec *spec = codec->spec; 1008 unsigned int def_conf, coef; 1009 1010 /* GPIO, DMIC_SCL, DMIC_SDA and SENSE_B are multiplexed */ 1011 coef = cs_vendor_coef_get(codec, CS421X_IDX_DEV_CFG); 1012 1013 if (spec->gpio_mask) 1014 coef |= 0x0008; /* B1,B2 are GPIOs */ 1015 else 1016 coef &= ~0x0008; 1017 1018 if (spec->sense_b) 1019 coef |= 0x0010; /* B2 is SENSE_B, not inverted */ 1020 else 1021 coef &= ~0x0010; 1022 1023 cs_vendor_coef_set(codec, CS421X_IDX_DEV_CFG, coef); 1024 1025 if ((spec->gpio_mask || spec->sense_b) && 1026 is_active_pin(codec, CS421X_DMIC_PIN_NID)) { 1027 1028 /* 1029 * GPIO or SENSE_B forced - disconnect the DMIC pin. 1030 */ 1031 def_conf = snd_hda_codec_get_pincfg(codec, CS421X_DMIC_PIN_NID); 1032 def_conf &= ~AC_DEFCFG_PORT_CONN; 1033 def_conf |= (AC_JACK_PORT_NONE << AC_DEFCFG_PORT_CONN_SHIFT); 1034 snd_hda_codec_set_pincfg(codec, CS421X_DMIC_PIN_NID, def_conf); 1035 } 1036 } 1037 1038 static void cs4210_spdif_automute(struct hda_codec *codec, 1039 struct hda_jack_callback *tbl) 1040 { 1041 struct cs_spec *spec = codec->spec; 1042 bool spdif_present = false; 1043 hda_nid_t spdif_pin = spec->gen.autocfg.dig_out_pins[0]; 1044 1045 /* detect on spdif is specific to CS4210 */ 1046 if (!spec->spdif_detect || 1047 spec->vendor_nid != CS4210_VENDOR_NID) 1048 return; 1049 1050 spdif_present = snd_hda_jack_detect(codec, spdif_pin); 1051 if (spdif_present == spec->spdif_present) 1052 return; 1053 1054 spec->spdif_present = spdif_present; 1055 /* SPDIF TX on/off */ 1056 snd_hda_set_pin_ctl(codec, spdif_pin, spdif_present ? PIN_OUT : 0); 1057 1058 cs_automute(codec); 1059 } 1060 1061 static void parse_cs421x_digital(struct hda_codec *codec) 1062 { 1063 struct cs_spec *spec = codec->spec; 1064 struct auto_pin_cfg *cfg = &spec->gen.autocfg; 1065 int i; 1066 1067 for (i = 0; i < cfg->dig_outs; i++) { 1068 hda_nid_t nid = cfg->dig_out_pins[i]; 1069 1070 if (get_wcaps(codec, nid) & AC_WCAP_UNSOL_CAP) { 1071 spec->spdif_detect = 1; 1072 snd_hda_jack_detect_enable_callback(codec, nid, 1073 cs4210_spdif_automute); 1074 } 1075 } 1076 } 1077 1078 static int cs421x_init(struct hda_codec *codec) 1079 { 1080 struct cs_spec *spec = codec->spec; 1081 1082 if (spec->vendor_nid == CS4210_VENDOR_NID) { 1083 snd_hda_sequence_write(codec, cs421x_coef_init_verbs); 1084 snd_hda_sequence_write(codec, cs421x_coef_init_verbs_A1_silicon_fixes); 1085 cs4210_pinmux_init(codec); 1086 } 1087 1088 snd_hda_gen_init(codec); 1089 1090 if (spec->gpio_mask) { 1091 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_MASK, 1092 spec->gpio_mask); 1093 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DIRECTION, 1094 spec->gpio_dir); 1095 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 1096 spec->gpio_data); 1097 } 1098 1099 init_input_coef(codec); 1100 1101 cs4210_spdif_automute(codec, NULL); 1102 1103 return 0; 1104 } 1105 1106 static void fix_volume_caps(struct hda_codec *codec, hda_nid_t dac) 1107 { 1108 unsigned int caps; 1109 1110 /* set the upper-limit for mixer amp to 0dB */ 1111 caps = query_amp_caps(codec, dac, HDA_OUTPUT); 1112 caps &= ~(0x7f << AC_AMPCAP_NUM_STEPS_SHIFT); 1113 caps |= ((caps >> AC_AMPCAP_OFFSET_SHIFT) & 0x7f) 1114 << AC_AMPCAP_NUM_STEPS_SHIFT; 1115 snd_hda_override_amp_caps(codec, dac, HDA_OUTPUT, caps); 1116 } 1117 1118 static int cs421x_parse_auto_config(struct hda_codec *codec) 1119 { 1120 struct cs_spec *spec = codec->spec; 1121 hda_nid_t dac = CS4210_DAC_NID; 1122 int err; 1123 1124 fix_volume_caps(codec, dac); 1125 1126 err = snd_hda_parse_pin_defcfg(codec, &spec->gen.autocfg, NULL, 0); 1127 if (err < 0) 1128 return err; 1129 1130 err = snd_hda_gen_parse_auto_config(codec, &spec->gen.autocfg); 1131 if (err < 0) 1132 return err; 1133 1134 parse_cs421x_digital(codec); 1135 1136 if (spec->gen.autocfg.speaker_outs && 1137 spec->vendor_nid == CS4210_VENDOR_NID) { 1138 if (!snd_hda_gen_add_kctl(&spec->gen, NULL, 1139 &cs421x_speaker_boost_ctl)) 1140 return -ENOMEM; 1141 } 1142 1143 return 0; 1144 } 1145 1146 #ifdef CONFIG_PM 1147 /* 1148 * Manage PDREF, when transitioning to D3hot 1149 * (DAC,ADC) -> D3, PDREF=1, AFG->D3 1150 */ 1151 static int cs421x_suspend(struct hda_codec *codec) 1152 { 1153 struct cs_spec *spec = codec->spec; 1154 unsigned int coef; 1155 1156 snd_hda_shutup_pins(codec); 1157 1158 snd_hda_codec_write(codec, CS4210_DAC_NID, 0, 1159 AC_VERB_SET_POWER_STATE, AC_PWRST_D3); 1160 snd_hda_codec_write(codec, CS4210_ADC_NID, 0, 1161 AC_VERB_SET_POWER_STATE, AC_PWRST_D3); 1162 1163 if (spec->vendor_nid == CS4210_VENDOR_NID) { 1164 coef = cs_vendor_coef_get(codec, CS421X_IDX_DEV_CFG); 1165 coef |= 0x0004; /* PDREF */ 1166 cs_vendor_coef_set(codec, CS421X_IDX_DEV_CFG, coef); 1167 } 1168 1169 return 0; 1170 } 1171 #endif 1172 1173 static const struct hda_codec_ops cs421x_patch_ops = { 1174 .build_controls = snd_hda_gen_build_controls, 1175 .build_pcms = snd_hda_gen_build_pcms, 1176 .init = cs421x_init, 1177 .free = cs_free, 1178 .unsol_event = snd_hda_jack_unsol_event, 1179 #ifdef CONFIG_PM 1180 .suspend = cs421x_suspend, 1181 #endif 1182 }; 1183 1184 static int patch_cs4210(struct hda_codec *codec) 1185 { 1186 struct cs_spec *spec; 1187 int err; 1188 1189 spec = cs_alloc_spec(codec, CS4210_VENDOR_NID); 1190 if (!spec) 1191 return -ENOMEM; 1192 1193 codec->patch_ops = cs421x_patch_ops; 1194 spec->gen.automute_hook = cs_automute; 1195 1196 snd_hda_pick_fixup(codec, cs421x_models, cs421x_fixup_tbl, 1197 cs421x_fixups); 1198 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE); 1199 1200 /* 1201 * Update the GPIO/DMIC/SENSE_B pinmux before the configuration 1202 * is auto-parsed. If GPIO or SENSE_B is forced, DMIC input 1203 * is disabled. 1204 */ 1205 cs4210_pinmux_init(codec); 1206 1207 err = cs421x_parse_auto_config(codec); 1208 if (err < 0) 1209 goto error; 1210 1211 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE); 1212 1213 return 0; 1214 1215 error: 1216 cs_free(codec); 1217 return err; 1218 } 1219 1220 static int patch_cs4213(struct hda_codec *codec) 1221 { 1222 struct cs_spec *spec; 1223 int err; 1224 1225 spec = cs_alloc_spec(codec, CS4213_VENDOR_NID); 1226 if (!spec) 1227 return -ENOMEM; 1228 1229 codec->patch_ops = cs421x_patch_ops; 1230 1231 err = cs421x_parse_auto_config(codec); 1232 if (err < 0) 1233 goto error; 1234 1235 return 0; 1236 1237 error: 1238 cs_free(codec); 1239 return err; 1240 } 1241 1242 /* Cirrus Logic CS8409 HDA bridge with 1243 * companion codec CS42L42 1244 */ 1245 #define CS8409_VENDOR_NID 0x47 1246 1247 #define CS8409_CS42L42_HP_PIN_NID 0x24 1248 #define CS8409_CS42L42_SPK_PIN_NID 0x2c 1249 #define CS8409_CS42L42_AMIC_PIN_NID 0x34 1250 #define CS8409_CS42L42_DMIC_PIN_NID 0x44 1251 #define CS8409_CS42L42_DMIC_ADC_PIN_NID 0x22 1252 1253 #define CS42L42_HSDET_AUTO_DONE 0x02 1254 #define CS42L42_HSTYPE_MASK 0x03 1255 1256 #define CS42L42_JACK_INSERTED 0x0C 1257 #define CS42L42_JACK_REMOVED 0x00 1258 1259 #define GPIO3_INT (1 << 3) 1260 #define GPIO4_INT (1 << 4) 1261 #define GPIO5_INT (1 << 5) 1262 1263 #define CS42L42_I2C_ADDR (0x48 << 1) 1264 1265 #define CIR_I2C_ADDR 0x0059 1266 #define CIR_I2C_DATA 0x005A 1267 #define CIR_I2C_CTRL 0x005B 1268 #define CIR_I2C_STATUS 0x005C 1269 #define CIR_I2C_QWRITE 0x005D 1270 #define CIR_I2C_QREAD 0x005E 1271 1272 #define CS8409_CS42L42_HP_VOL_REAL_MIN (-63) 1273 #define CS8409_CS42L42_HP_VOL_REAL_MAX (0) 1274 #define CS8409_CS42L42_AMIC_VOL_REAL_MIN (-97) 1275 #define CS8409_CS42L42_AMIC_VOL_REAL_MAX (12) 1276 #define CS8409_CS42L42_REG_HS_VOLUME_CHA (0x2301) 1277 #define CS8409_CS42L42_REG_HS_VOLUME_CHB (0x2303) 1278 #define CS8409_CS42L42_REG_AMIC_VOLUME (0x1D03) 1279 1280 struct cs8409_i2c_param { 1281 unsigned int addr; 1282 unsigned int reg; 1283 }; 1284 1285 struct cs8409_cir_param { 1286 unsigned int nid; 1287 unsigned int cir; 1288 unsigned int coeff; 1289 }; 1290 1291 enum { 1292 CS8409_BULLSEYE, 1293 CS8409_WARLOCK, 1294 CS8409_CYBORG, 1295 CS8409_FIXUPS, 1296 }; 1297 1298 static void cs8409_cs42l42_fixups(struct hda_codec *codec, 1299 const struct hda_fixup *fix, int action); 1300 static int cs8409_cs42l42_exec_verb(struct hdac_device *dev, 1301 unsigned int cmd, unsigned int flags, unsigned int *res); 1302 1303 /* Dell Inspiron models with cs8409/cs42l42 */ 1304 static const struct hda_model_fixup cs8409_models[] = { 1305 { .id = CS8409_BULLSEYE, .name = "bullseye" }, 1306 { .id = CS8409_WARLOCK, .name = "warlock" }, 1307 { .id = CS8409_CYBORG, .name = "cyborg" }, 1308 {} 1309 }; 1310 1311 /* Dell Inspiron platforms 1312 * with cs8409 bridge and cs42l42 codec 1313 */ 1314 static const struct snd_pci_quirk cs8409_fixup_tbl[] = { 1315 SND_PCI_QUIRK(0x1028, 0x0A11, "Bullseye", CS8409_BULLSEYE), 1316 SND_PCI_QUIRK(0x1028, 0x0A12, "Bullseye", CS8409_BULLSEYE), 1317 SND_PCI_QUIRK(0x1028, 0x0A23, "Bullseye", CS8409_BULLSEYE), 1318 SND_PCI_QUIRK(0x1028, 0x0A24, "Bullseye", CS8409_BULLSEYE), 1319 SND_PCI_QUIRK(0x1028, 0x0A25, "Bullseye", CS8409_BULLSEYE), 1320 SND_PCI_QUIRK(0x1028, 0x0A29, "Bullseye", CS8409_BULLSEYE), 1321 SND_PCI_QUIRK(0x1028, 0x0A2A, "Bullseye", CS8409_BULLSEYE), 1322 SND_PCI_QUIRK(0x1028, 0x0A2B, "Bullseye", CS8409_BULLSEYE), 1323 SND_PCI_QUIRK(0x1028, 0x0AB0, "Warlock", CS8409_WARLOCK), 1324 SND_PCI_QUIRK(0x1028, 0x0AB2, "Warlock", CS8409_WARLOCK), 1325 SND_PCI_QUIRK(0x1028, 0x0AB1, "Warlock", CS8409_WARLOCK), 1326 SND_PCI_QUIRK(0x1028, 0x0AB3, "Warlock", CS8409_WARLOCK), 1327 SND_PCI_QUIRK(0x1028, 0x0AB4, "Warlock", CS8409_WARLOCK), 1328 SND_PCI_QUIRK(0x1028, 0x0AB5, "Warlock", CS8409_WARLOCK), 1329 SND_PCI_QUIRK(0x1028, 0x0AD9, "Warlock", CS8409_WARLOCK), 1330 SND_PCI_QUIRK(0x1028, 0x0ADA, "Warlock", CS8409_WARLOCK), 1331 SND_PCI_QUIRK(0x1028, 0x0ADB, "Warlock", CS8409_WARLOCK), 1332 SND_PCI_QUIRK(0x1028, 0x0ADC, "Warlock", CS8409_WARLOCK), 1333 SND_PCI_QUIRK(0x1028, 0x0AF4, "Warlock", CS8409_WARLOCK), 1334 SND_PCI_QUIRK(0x1028, 0x0AF5, "Warlock", CS8409_WARLOCK), 1335 SND_PCI_QUIRK(0x1028, 0x0A77, "Cyborg", CS8409_CYBORG), 1336 SND_PCI_QUIRK(0x1028, 0x0A78, "Cyborg", CS8409_CYBORG), 1337 SND_PCI_QUIRK(0x1028, 0x0A79, "Cyborg", CS8409_CYBORG), 1338 SND_PCI_QUIRK(0x1028, 0x0A7A, "Cyborg", CS8409_CYBORG), 1339 SND_PCI_QUIRK(0x1028, 0x0A7D, "Cyborg", CS8409_CYBORG), 1340 SND_PCI_QUIRK(0x1028, 0x0A7E, "Cyborg", CS8409_CYBORG), 1341 SND_PCI_QUIRK(0x1028, 0x0A7F, "Cyborg", CS8409_CYBORG), 1342 SND_PCI_QUIRK(0x1028, 0x0A80, "Cyborg", CS8409_CYBORG), 1343 SND_PCI_QUIRK(0x1028, 0x0ADF, "Cyborg", CS8409_CYBORG), 1344 SND_PCI_QUIRK(0x1028, 0x0AE0, "Cyborg", CS8409_CYBORG), 1345 SND_PCI_QUIRK(0x1028, 0x0AE1, "Cyborg", CS8409_CYBORG), 1346 SND_PCI_QUIRK(0x1028, 0x0AE2, "Cyborg", CS8409_CYBORG), 1347 SND_PCI_QUIRK(0x1028, 0x0AE9, "Cyborg", CS8409_CYBORG), 1348 SND_PCI_QUIRK(0x1028, 0x0AEA, "Cyborg", CS8409_CYBORG), 1349 SND_PCI_QUIRK(0x1028, 0x0AEB, "Cyborg", CS8409_CYBORG), 1350 SND_PCI_QUIRK(0x1028, 0x0AEC, "Cyborg", CS8409_CYBORG), 1351 SND_PCI_QUIRK(0x1028, 0x0AED, "Cyborg", CS8409_CYBORG), 1352 SND_PCI_QUIRK(0x1028, 0x0AEE, "Cyborg", CS8409_CYBORG), 1353 SND_PCI_QUIRK(0x1028, 0x0AEF, "Cyborg", CS8409_CYBORG), 1354 SND_PCI_QUIRK(0x1028, 0x0AF0, "Cyborg", CS8409_CYBORG), 1355 {} /* terminator */ 1356 }; 1357 1358 static const struct hda_verb cs8409_cs42l42_init_verbs[] = { 1359 { 0x01, AC_VERB_SET_GPIO_WAKE_MASK, 0x0018 }, /* WAKE from GPIO 3,4 */ 1360 { 0x47, AC_VERB_SET_PROC_STATE, 0x0001 }, /* Enable VPW processing */ 1361 { 0x47, AC_VERB_SET_COEF_INDEX, 0x0002 }, /* Configure GPIO 6,7 */ 1362 { 0x47, AC_VERB_SET_PROC_COEF, 0x0080 }, /* I2C mode */ 1363 { 0x47, AC_VERB_SET_COEF_INDEX, 0x005b }, /* Set I2C bus speed */ 1364 { 0x47, AC_VERB_SET_PROC_COEF, 0x0200 }, /* 100kHz I2C_STO = 2 */ 1365 {} /* terminator */ 1366 }; 1367 1368 static const struct hda_pintbl cs8409_cs42l42_pincfgs[] = { 1369 { 0x24, 0x042120f0 }, /* ASP-1-TX */ 1370 { 0x34, 0x04a12050 }, /* ASP-1-RX */ 1371 { 0x2c, 0x901000f0 }, /* ASP-2-TX */ 1372 { 0x44, 0x90a00090 }, /* DMIC-1 */ 1373 {} /* terminator */ 1374 }; 1375 1376 static const struct hda_fixup cs8409_fixups[] = { 1377 [CS8409_BULLSEYE] = { 1378 .type = HDA_FIXUP_PINS, 1379 .v.pins = cs8409_cs42l42_pincfgs, 1380 .chained = true, 1381 .chain_id = CS8409_FIXUPS, 1382 }, 1383 [CS8409_WARLOCK] = { 1384 .type = HDA_FIXUP_PINS, 1385 .v.pins = cs8409_cs42l42_pincfgs, 1386 .chained = true, 1387 .chain_id = CS8409_FIXUPS, 1388 }, 1389 [CS8409_CYBORG] = { 1390 .type = HDA_FIXUP_PINS, 1391 .v.pins = cs8409_cs42l42_pincfgs, 1392 .chained = true, 1393 .chain_id = CS8409_FIXUPS, 1394 }, 1395 [CS8409_FIXUPS] = { 1396 .type = HDA_FIXUP_FUNC, 1397 .v.func = cs8409_cs42l42_fixups, 1398 }, 1399 }; 1400 1401 /* Vendor specific HW configuration for CS42L42 */ 1402 static const struct cs8409_i2c_param cs42l42_init_reg_seq[] = { 1403 { 0x1010, 0xB0 }, 1404 { 0x1D01, 0x00 }, 1405 { 0x1D02, 0x06 }, 1406 { 0x1D03, 0x00 }, 1407 { 0x1107, 0x01 }, 1408 { 0x1009, 0x02 }, 1409 { 0x1007, 0x03 }, 1410 { 0x1201, 0x00 }, 1411 { 0x1208, 0x13 }, 1412 { 0x1205, 0xFF }, 1413 { 0x1206, 0x00 }, 1414 { 0x1207, 0x20 }, 1415 { 0x1202, 0x0D }, 1416 { 0x2A02, 0x02 }, 1417 { 0x2A03, 0x00 }, 1418 { 0x2A04, 0x00 }, 1419 { 0x2A05, 0x02 }, 1420 { 0x2A06, 0x00 }, 1421 { 0x2A07, 0x20 }, 1422 { 0x2A08, 0x02 }, 1423 { 0x2A09, 0x00 }, 1424 { 0x2A0A, 0x80 }, 1425 { 0x2A0B, 0x02 }, 1426 { 0x2A0C, 0x00 }, 1427 { 0x2A0D, 0xA0 }, 1428 { 0x2A01, 0x0C }, 1429 { 0x2902, 0x01 }, 1430 { 0x2903, 0x02 }, 1431 { 0x2904, 0x00 }, 1432 { 0x2905, 0x00 }, 1433 { 0x2901, 0x01 }, 1434 { 0x1101, 0x0A }, 1435 { 0x1102, 0x84 }, 1436 { 0x2301, 0x00 }, 1437 { 0x2303, 0x00 }, 1438 { 0x2302, 0x3f }, 1439 { 0x2001, 0x03 }, 1440 { 0x1B75, 0xB6 }, 1441 { 0x1B73, 0xC2 }, 1442 { 0x1129, 0x01 }, 1443 { 0x1121, 0xF3 }, 1444 { 0x1103, 0x20 }, 1445 { 0x1105, 0x00 }, 1446 { 0x1112, 0xC0 }, 1447 { 0x1113, 0x80 }, 1448 { 0x1C03, 0xC0 }, 1449 { 0x1105, 0x00 }, 1450 { 0x1112, 0xC0 }, 1451 { 0x1101, 0x02 }, 1452 {} /* Terminator */ 1453 }; 1454 1455 /* Vendor specific hw configuration for CS8409 */ 1456 static const struct cs8409_cir_param cs8409_cs42l42_hw_cfg[] = { 1457 { 0x47, 0x00, 0xb008 }, /* +PLL1/2_EN, +I2C_EN */ 1458 { 0x47, 0x01, 0x0002 }, /* ASP1/2_EN=0, ASP1_STP=1 */ 1459 { 0x47, 0x02, 0x0a80 }, /* ASP1/2_BUS_IDLE=10, +GPIO_I2C */ 1460 { 0x47, 0x19, 0x0800 }, /* ASP1.A: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=0 */ 1461 { 0x47, 0x1a, 0x0820 }, /* ASP1.A: TX.RAP=0, TX.RSZ=24 bits, TX.RCS=32 */ 1462 { 0x47, 0x29, 0x0800 }, /* ASP2.A: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=0 */ 1463 { 0x47, 0x2a, 0x2800 }, /* ASP2.A: TX.RAP=1, TX.RSZ=24 bits, TX.RCS=0 */ 1464 { 0x47, 0x39, 0x0800 }, /* ASP1.A: RX.LAP=0, RX.LSZ=24 bits, RX.LCS=0 */ 1465 { 0x47, 0x3a, 0x0800 }, /* ASP1.A: RX.RAP=0, RX.RSZ=24 bits, RX.RCS=0 */ 1466 { 0x47, 0x03, 0x8000 }, /* ASP1: LCHI = 00h */ 1467 { 0x47, 0x04, 0x28ff }, /* ASP1: MC/SC_SRCSEL=PLL1, LCPR=FFh */ 1468 { 0x47, 0x05, 0x0062 }, /* ASP1: MCEN=0, FSD=011, SCPOL_IN/OUT=0, SCDIV=1:4 */ 1469 { 0x47, 0x06, 0x801f }, /* ASP2: LCHI=1Fh */ 1470 { 0x47, 0x07, 0x283f }, /* ASP2: MC/SC_SRCSEL=PLL1, LCPR=3Fh */ 1471 { 0x47, 0x08, 0x805c }, /* ASP2: 5050=1, MCEN=0, FSD=010, SCPOL_IN/OUT=1, SCDIV=1:16 */ 1472 { 0x47, 0x09, 0x0023 }, /* DMIC1_MO=10b, DMIC1/2_SR=1 */ 1473 { 0x47, 0x0a, 0x0000 }, /* ASP1/2_BEEP=0 */ 1474 { 0x47, 0x01, 0x0062 }, /* ASP1/2_EN=1, ASP1_STP=1 */ 1475 { 0x47, 0x00, 0x9008 }, /* -PLL2_EN */ 1476 { 0x47, 0x68, 0x0000 }, /* TX2.A: pre-scale att.=0 dB */ 1477 { 0x47, 0x82, 0xfc03 }, /* ASP1/2_xxx_EN=1, ASP1/2_MCLK_EN=0, DMIC1_SCL_EN=1 */ 1478 { 0x47, 0xc0, 0x9999 }, /* test mode on */ 1479 { 0x47, 0xc5, 0x0000 }, /* GPIO hysteresis = 30 us */ 1480 { 0x47, 0xc0, 0x0000 }, /* test mode off */ 1481 {} /* Terminator */ 1482 }; 1483 1484 static const struct cs8409_cir_param cs8409_cs42l42_bullseye_atn[] = { 1485 { 0x47, 0x65, 0x4000 }, /* EQ_SEL=1, EQ1/2_EN=0 */ 1486 { 0x47, 0x64, 0x4000 }, /* +EQ_ACC */ 1487 { 0x47, 0x65, 0x4010 }, /* +EQ2_EN */ 1488 { 0x47, 0x63, 0x0647 }, /* EQ_DATA_HI=0x0647 */ 1489 { 0x47, 0x64, 0xc0c7 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=0, EQ_DATA_LO=0x67 */ 1490 { 0x47, 0x63, 0x0647 }, /* EQ_DATA_HI=0x0647 */ 1491 { 0x47, 0x64, 0xc1c7 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=1, EQ_DATA_LO=0x67 */ 1492 { 0x47, 0x63, 0xf370 }, /* EQ_DATA_HI=0xf370 */ 1493 { 0x47, 0x64, 0xc271 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=2, EQ_DATA_LO=0x71 */ 1494 { 0x47, 0x63, 0x1ef8 }, /* EQ_DATA_HI=0x1ef8 */ 1495 { 0x47, 0x64, 0xc348 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=3, EQ_DATA_LO=0x48 */ 1496 { 0x47, 0x63, 0xc110 }, /* EQ_DATA_HI=0xc110 */ 1497 { 0x47, 0x64, 0xc45a }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=4, EQ_DATA_LO=0x5a */ 1498 { 0x47, 0x63, 0x1f29 }, /* EQ_DATA_HI=0x1f29 */ 1499 { 0x47, 0x64, 0xc574 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=5, EQ_DATA_LO=0x74 */ 1500 { 0x47, 0x63, 0x1d7a }, /* EQ_DATA_HI=0x1d7a */ 1501 { 0x47, 0x64, 0xc653 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=6, EQ_DATA_LO=0x53 */ 1502 { 0x47, 0x63, 0xc38c }, /* EQ_DATA_HI=0xc38c */ 1503 { 0x47, 0x64, 0xc714 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=7, EQ_DATA_LO=0x14 */ 1504 { 0x47, 0x63, 0x1ca3 }, /* EQ_DATA_HI=0x1ca3 */ 1505 { 0x47, 0x64, 0xc8c7 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=8, EQ_DATA_LO=0xc7 */ 1506 { 0x47, 0x63, 0xc38c }, /* EQ_DATA_HI=0xc38c */ 1507 { 0x47, 0x64, 0xc914 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=9, EQ_DATA_LO=0x14 */ 1508 { 0x47, 0x64, 0x0000 }, /* -EQ_ACC, -EQ_WRT */ 1509 {} /* Terminator */ 1510 }; 1511 1512 /** 1513 * cs8409_enable_i2c_clock - Enable I2C clocks 1514 * @codec: the codec instance 1515 * @enable: Enable or disable I2C clocks 1516 * 1517 * Enable or Disable I2C clocks. 1518 */ 1519 static void cs8409_enable_i2c_clock(struct hda_codec *codec, unsigned int enable) 1520 { 1521 unsigned int retval; 1522 unsigned int newval; 1523 1524 retval = cs_vendor_coef_get(codec, 0x0); 1525 newval = (enable) ? (retval | 0x8) : (retval & 0xfffffff7); 1526 cs_vendor_coef_set(codec, 0x0, newval); 1527 } 1528 1529 /** 1530 * cs8409_i2c_wait_complete - Wait for I2C transaction 1531 * @codec: the codec instance 1532 * 1533 * Wait for I2C transaction to complete. 1534 * Return -1 if transaction wait times out. 1535 */ 1536 static int cs8409_i2c_wait_complete(struct hda_codec *codec) 1537 { 1538 int repeat = 5; 1539 unsigned int retval; 1540 1541 do { 1542 retval = cs_vendor_coef_get(codec, CIR_I2C_STATUS); 1543 if ((retval & 0x18) != 0x18) { 1544 usleep_range(2000, 4000); 1545 --repeat; 1546 } else 1547 return 0; 1548 1549 } while (repeat); 1550 1551 return -1; 1552 } 1553 1554 /** 1555 * cs8409_i2c_read - CS8409 I2C Read. 1556 * @codec: the codec instance 1557 * @i2c_address: I2C Address 1558 * @i2c_reg: Register to read 1559 * @paged: Is a paged transaction 1560 * 1561 * CS8409 I2C Read. 1562 * Returns negative on error, otherwise returns read value in bits 0-7. 1563 */ 1564 static int cs8409_i2c_read(struct hda_codec *codec, 1565 unsigned int i2c_address, 1566 unsigned int i2c_reg, 1567 unsigned int paged) 1568 { 1569 unsigned int i2c_reg_data; 1570 unsigned int read_data; 1571 1572 cs8409_enable_i2c_clock(codec, 1); 1573 cs_vendor_coef_set(codec, CIR_I2C_ADDR, i2c_address); 1574 1575 if (paged) { 1576 cs_vendor_coef_set(codec, CIR_I2C_QWRITE, i2c_reg >> 8); 1577 if (cs8409_i2c_wait_complete(codec) < 0) { 1578 codec_err(codec, 1579 "%s() Paged Transaction Failed 0x%02x : 0x%04x\n", 1580 __func__, i2c_address, i2c_reg); 1581 return -EIO; 1582 } 1583 } 1584 1585 i2c_reg_data = (i2c_reg << 8) & 0x0ffff; 1586 cs_vendor_coef_set(codec, CIR_I2C_QREAD, i2c_reg_data); 1587 if (cs8409_i2c_wait_complete(codec) < 0) { 1588 codec_err(codec, "%s() Transaction Failed 0x%02x : 0x%04x\n", 1589 __func__, i2c_address, i2c_reg); 1590 return -EIO; 1591 } 1592 1593 /* Register in bits 15-8 and the data in 7-0 */ 1594 read_data = cs_vendor_coef_get(codec, CIR_I2C_QREAD); 1595 1596 cs8409_enable_i2c_clock(codec, 0); 1597 1598 return read_data & 0x0ff; 1599 } 1600 1601 /** 1602 * cs8409_i2c_write - CS8409 I2C Write. 1603 * @codec: the codec instance 1604 * @i2c_address: I2C Address 1605 * @i2c_reg: Register to write to 1606 * @i2c_data: Data to write 1607 * @paged: Is a paged transaction 1608 * 1609 * CS8409 I2C Write. 1610 * Returns negative on error, otherwise returns 0. 1611 */ 1612 static int cs8409_i2c_write(struct hda_codec *codec, 1613 unsigned int i2c_address, unsigned int i2c_reg, 1614 unsigned int i2c_data, 1615 unsigned int paged) 1616 { 1617 unsigned int i2c_reg_data; 1618 1619 cs8409_enable_i2c_clock(codec, 1); 1620 cs_vendor_coef_set(codec, CIR_I2C_ADDR, i2c_address); 1621 1622 if (paged) { 1623 cs_vendor_coef_set(codec, CIR_I2C_QWRITE, i2c_reg >> 8); 1624 if (cs8409_i2c_wait_complete(codec) < 0) { 1625 codec_err(codec, 1626 "%s() Paged Transaction Failed 0x%02x : 0x%04x\n", 1627 __func__, i2c_address, i2c_reg); 1628 return -EIO; 1629 } 1630 } 1631 1632 i2c_reg_data = ((i2c_reg << 8) & 0x0ff00) | (i2c_data & 0x0ff); 1633 cs_vendor_coef_set(codec, CIR_I2C_QWRITE, i2c_reg_data); 1634 1635 if (cs8409_i2c_wait_complete(codec) < 0) { 1636 codec_err(codec, "%s() Transaction Failed 0x%02x : 0x%04x\n", 1637 __func__, i2c_address, i2c_reg); 1638 return -EIO; 1639 } 1640 1641 cs8409_enable_i2c_clock(codec, 0); 1642 1643 return 0; 1644 } 1645 1646 static int cs8409_cs42l42_volume_info(struct snd_kcontrol *kcontrol, 1647 struct snd_ctl_elem_info *uinfo) 1648 { 1649 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 1650 u16 nid = get_amp_nid(kcontrol); 1651 u8 chs = get_amp_channels(kcontrol); 1652 1653 codec_dbg(codec, "%s() nid: %d\n", __func__, nid); 1654 switch (nid) { 1655 case CS8409_CS42L42_HP_PIN_NID: 1656 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1657 uinfo->count = chs == 3 ? 2 : 1; 1658 uinfo->value.integer.min = CS8409_CS42L42_HP_VOL_REAL_MIN; 1659 uinfo->value.integer.max = CS8409_CS42L42_HP_VOL_REAL_MAX; 1660 break; 1661 case CS8409_CS42L42_AMIC_PIN_NID: 1662 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1663 uinfo->count = chs == 3 ? 2 : 1; 1664 uinfo->value.integer.min = CS8409_CS42L42_AMIC_VOL_REAL_MIN; 1665 uinfo->value.integer.max = CS8409_CS42L42_AMIC_VOL_REAL_MAX; 1666 break; 1667 default: 1668 break; 1669 } 1670 return 0; 1671 } 1672 1673 static void cs8409_cs42l42_update_volume(struct hda_codec *codec) 1674 { 1675 struct cs_spec *spec = codec->spec; 1676 int data; 1677 1678 mutex_lock(&spec->cs8409_i2c_mux); 1679 data = cs8409_i2c_read(codec, CS42L42_I2C_ADDR, 1680 CS8409_CS42L42_REG_HS_VOLUME_CHA, 1); 1681 if (data >= 0) 1682 spec->cs42l42_hp_volume[0] = -data; 1683 else 1684 spec->cs42l42_hp_volume[0] = CS8409_CS42L42_HP_VOL_REAL_MIN; 1685 data = cs8409_i2c_read(codec, CS42L42_I2C_ADDR, 1686 CS8409_CS42L42_REG_HS_VOLUME_CHB, 1); 1687 if (data >= 0) 1688 spec->cs42l42_hp_volume[1] = -data; 1689 else 1690 spec->cs42l42_hp_volume[1] = CS8409_CS42L42_HP_VOL_REAL_MIN; 1691 data = cs8409_i2c_read(codec, CS42L42_I2C_ADDR, 1692 CS8409_CS42L42_REG_AMIC_VOLUME, 1); 1693 if (data >= 0) 1694 spec->cs42l42_hs_mic_volume[0] = -data; 1695 else 1696 spec->cs42l42_hs_mic_volume[0] = CS8409_CS42L42_AMIC_VOL_REAL_MIN; 1697 mutex_unlock(&spec->cs8409_i2c_mux); 1698 spec->cs42l42_volume_init = 1; 1699 } 1700 1701 static int cs8409_cs42l42_volume_get(struct snd_kcontrol *kcontrol, 1702 struct snd_ctl_elem_value *ucontrol) 1703 { 1704 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 1705 struct cs_spec *spec = codec->spec; 1706 hda_nid_t nid = get_amp_nid(kcontrol); 1707 int chs = get_amp_channels(kcontrol); 1708 long *valp = ucontrol->value.integer.value; 1709 1710 if (!spec->cs42l42_volume_init) { 1711 snd_hda_power_up(codec); 1712 cs8409_cs42l42_update_volume(codec); 1713 snd_hda_power_down(codec); 1714 } 1715 switch (nid) { 1716 case CS8409_CS42L42_HP_PIN_NID: 1717 if (chs & BIT(0)) 1718 *valp++ = spec->cs42l42_hp_volume[0]; 1719 if (chs & BIT(1)) 1720 *valp++ = spec->cs42l42_hp_volume[1]; 1721 break; 1722 case CS8409_CS42L42_AMIC_PIN_NID: 1723 if (chs & BIT(0)) 1724 *valp++ = spec->cs42l42_hs_mic_volume[0]; 1725 break; 1726 default: 1727 break; 1728 } 1729 return 0; 1730 } 1731 1732 static int cs8409_cs42l42_volume_put(struct snd_kcontrol *kcontrol, 1733 struct snd_ctl_elem_value *ucontrol) 1734 { 1735 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 1736 struct cs_spec *spec = codec->spec; 1737 hda_nid_t nid = get_amp_nid(kcontrol); 1738 int chs = get_amp_channels(kcontrol); 1739 long *valp = ucontrol->value.integer.value; 1740 int change = 0; 1741 char vol; 1742 1743 snd_hda_power_up(codec); 1744 switch (nid) { 1745 case CS8409_CS42L42_HP_PIN_NID: 1746 mutex_lock(&spec->cs8409_i2c_mux); 1747 if (chs & BIT(0)) { 1748 vol = -(*valp); 1749 change = cs8409_i2c_write(codec, CS42L42_I2C_ADDR, 1750 CS8409_CS42L42_REG_HS_VOLUME_CHA, vol, 1); 1751 valp++; 1752 } 1753 if (chs & BIT(1)) { 1754 vol = -(*valp); 1755 change |= cs8409_i2c_write(codec, CS42L42_I2C_ADDR, 1756 CS8409_CS42L42_REG_HS_VOLUME_CHB, vol, 1); 1757 } 1758 mutex_unlock(&spec->cs8409_i2c_mux); 1759 break; 1760 case CS8409_CS42L42_AMIC_PIN_NID: 1761 mutex_lock(&spec->cs8409_i2c_mux); 1762 if (chs & BIT(0)) { 1763 change = cs8409_i2c_write( 1764 codec, CS42L42_I2C_ADDR, 1765 CS8409_CS42L42_REG_AMIC_VOLUME, (char)*valp, 1); 1766 valp++; 1767 } 1768 mutex_unlock(&spec->cs8409_i2c_mux); 1769 break; 1770 default: 1771 break; 1772 } 1773 cs8409_cs42l42_update_volume(codec); 1774 snd_hda_power_down(codec); 1775 return change; 1776 } 1777 1778 static const DECLARE_TLV_DB_SCALE( 1779 cs8409_cs42l42_hp_db_scale, 1780 CS8409_CS42L42_HP_VOL_REAL_MIN * 100, 100, 1); 1781 1782 static const DECLARE_TLV_DB_SCALE( 1783 cs8409_cs42l42_amic_db_scale, 1784 CS8409_CS42L42_AMIC_VOL_REAL_MIN * 100, 100, 1); 1785 1786 static const struct snd_kcontrol_new cs8409_cs42l42_hp_volume_mixer = { 1787 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1788 .index = 0, 1789 .name = "Headphone Playback Volume", 1790 .subdevice = (HDA_SUBDEV_AMP_FLAG | HDA_SUBDEV_NID_FLAG), 1791 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE 1792 | SNDRV_CTL_ELEM_ACCESS_TLV_READ), 1793 .info = cs8409_cs42l42_volume_info, 1794 .get = cs8409_cs42l42_volume_get, 1795 .put = cs8409_cs42l42_volume_put, 1796 .tlv = { .p = cs8409_cs42l42_hp_db_scale }, 1797 .private_value = HDA_COMPOSE_AMP_VAL( 1798 CS8409_CS42L42_HP_PIN_NID, 3, 0, HDA_OUTPUT) 1799 | HDA_AMP_VAL_MIN_MUTE 1800 }; 1801 1802 static const struct snd_kcontrol_new cs8409_cs42l42_amic_volume_mixer = { 1803 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1804 .index = 0, 1805 .name = "Mic Capture Volume", 1806 .subdevice = (HDA_SUBDEV_AMP_FLAG | HDA_SUBDEV_NID_FLAG), 1807 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE 1808 | SNDRV_CTL_ELEM_ACCESS_TLV_READ), 1809 .info = cs8409_cs42l42_volume_info, 1810 .get = cs8409_cs42l42_volume_get, 1811 .put = cs8409_cs42l42_volume_put, 1812 .tlv = { .p = cs8409_cs42l42_amic_db_scale }, 1813 .private_value = HDA_COMPOSE_AMP_VAL( 1814 CS8409_CS42L42_AMIC_PIN_NID, 1, 0, HDA_INPUT) 1815 | HDA_AMP_VAL_MIN_MUTE 1816 }; 1817 1818 /* Assert/release RTS# line to CS42L42 */ 1819 static void cs8409_cs42l42_reset(struct hda_codec *codec) 1820 { 1821 struct cs_spec *spec = codec->spec; 1822 1823 /* Assert RTS# line */ 1824 snd_hda_codec_write(codec, 1825 codec->core.afg, 0, AC_VERB_SET_GPIO_DATA, 0); 1826 /* wait ~10ms */ 1827 usleep_range(10000, 15000); 1828 /* Release RTS# line */ 1829 snd_hda_codec_write(codec, 1830 codec->core.afg, 0, AC_VERB_SET_GPIO_DATA, GPIO5_INT); 1831 /* wait ~10ms */ 1832 usleep_range(10000, 15000); 1833 1834 mutex_lock(&spec->cs8409_i2c_mux); 1835 1836 /* Clear interrupts, by reading interrupt status registers */ 1837 cs8409_i2c_read(codec, CS42L42_I2C_ADDR, 0x1308, 1); 1838 cs8409_i2c_read(codec, CS42L42_I2C_ADDR, 0x1309, 1); 1839 cs8409_i2c_read(codec, CS42L42_I2C_ADDR, 0x130A, 1); 1840 cs8409_i2c_read(codec, CS42L42_I2C_ADDR, 0x130F, 1); 1841 1842 mutex_unlock(&spec->cs8409_i2c_mux); 1843 1844 } 1845 1846 /* Configure CS42L42 slave codec for jack autodetect */ 1847 static void cs8409_cs42l42_enable_jack_detect(struct hda_codec *codec) 1848 { 1849 struct cs_spec *spec = codec->spec; 1850 1851 mutex_lock(&spec->cs8409_i2c_mux); 1852 1853 /* Set TIP_SENSE_EN for analog front-end of tip sense. */ 1854 cs8409_i2c_write(codec, CS42L42_I2C_ADDR, 0x1b70, 0x0020, 1); 1855 /* Clear WAKE# */ 1856 cs8409_i2c_write(codec, CS42L42_I2C_ADDR, 0x1b71, 0x0001, 1); 1857 /* Wait ~2.5ms */ 1858 usleep_range(2500, 3000); 1859 /* Set mode WAKE# output follows the combination logic directly */ 1860 cs8409_i2c_write(codec, CS42L42_I2C_ADDR, 0x1b71, 0x0020, 1); 1861 /* Clear interrupts status */ 1862 cs8409_i2c_read(codec, CS42L42_I2C_ADDR, 0x130f, 1); 1863 cs8409_i2c_read(codec, CS42L42_I2C_ADDR, 0x1b7b, 1); 1864 /* Enable interrupt */ 1865 cs8409_i2c_write(codec, CS42L42_I2C_ADDR, 0x1320, 0x03, 1); 1866 cs8409_i2c_write(codec, CS42L42_I2C_ADDR, 0x1b79, 0x00, 1); 1867 1868 mutex_unlock(&spec->cs8409_i2c_mux); 1869 } 1870 1871 /* Enable and run CS42L42 slave codec jack auto detect */ 1872 static void cs8409_cs42l42_run_jack_detect(struct hda_codec *codec) 1873 { 1874 struct cs_spec *spec = codec->spec; 1875 1876 mutex_lock(&spec->cs8409_i2c_mux); 1877 1878 /* Clear interrupts */ 1879 cs8409_i2c_read(codec, CS42L42_I2C_ADDR, 0x1308, 1); 1880 cs8409_i2c_read(codec, CS42L42_I2C_ADDR, 0x1b77, 1); 1881 1882 cs8409_i2c_write(codec, CS42L42_I2C_ADDR, 0x1102, 0x87, 1); 1883 cs8409_i2c_write(codec, CS42L42_I2C_ADDR, 0x1f06, 0x86, 1); 1884 cs8409_i2c_write(codec, CS42L42_I2C_ADDR, 0x1b74, 0x07, 1); 1885 cs8409_i2c_write(codec, CS42L42_I2C_ADDR, 0x131b, 0x01, 1); 1886 cs8409_i2c_write(codec, CS42L42_I2C_ADDR, 0x1120, 0x80, 1); 1887 /* Wait ~110ms*/ 1888 usleep_range(110000, 200000); 1889 cs8409_i2c_write(codec, CS42L42_I2C_ADDR, 0x111f, 0x77, 1); 1890 cs8409_i2c_write(codec, CS42L42_I2C_ADDR, 0x1120, 0xc0, 1); 1891 /* Wait ~10ms */ 1892 usleep_range(10000, 25000); 1893 1894 mutex_unlock(&spec->cs8409_i2c_mux); 1895 1896 } 1897 1898 static void cs8409_cs42l42_reg_setup(struct hda_codec *codec) 1899 { 1900 const struct cs8409_i2c_param *seq = cs42l42_init_reg_seq; 1901 struct cs_spec *spec = codec->spec; 1902 1903 mutex_lock(&spec->cs8409_i2c_mux); 1904 1905 for (; seq->addr; seq++) 1906 cs8409_i2c_write(codec, CS42L42_I2C_ADDR, seq->addr, seq->reg, 1); 1907 1908 mutex_unlock(&spec->cs8409_i2c_mux); 1909 1910 } 1911 1912 /* 1913 * In the case of CS8409 we do not have unsolicited events from NID's 0x24 1914 * and 0x34 where hs mic and hp are connected. Companion codec CS42L42 will 1915 * generate interrupt via gpio 4 to notify jack events. We have to overwrite 1916 * generic snd_hda_jack_unsol_event(), read CS42L42 jack detect status registers 1917 * and then notify status via generic snd_hda_jack_unsol_event() call. 1918 */ 1919 static void cs8409_jack_unsol_event(struct hda_codec *codec, unsigned int res) 1920 { 1921 struct cs_spec *spec = codec->spec; 1922 int status_changed = 0; 1923 int reg_cdc_status; 1924 int reg_hs_status; 1925 int reg_ts_status; 1926 int type; 1927 struct hda_jack_tbl *jk; 1928 1929 /* jack_unsol_event() will be called every time gpio line changing state. 1930 * In this case gpio4 line goes up as a result of reading interrupt status 1931 * registers in previous cs8409_jack_unsol_event() call. 1932 * We don't need to handle this event, ignoring... 1933 */ 1934 if ((res & (1 << 4))) 1935 return; 1936 1937 mutex_lock(&spec->cs8409_i2c_mux); 1938 1939 /* Read jack detect status registers */ 1940 reg_cdc_status = cs8409_i2c_read(codec, CS42L42_I2C_ADDR, 0x1308, 1); 1941 reg_hs_status = cs8409_i2c_read(codec, CS42L42_I2C_ADDR, 0x1124, 1); 1942 reg_ts_status = cs8409_i2c_read(codec, CS42L42_I2C_ADDR, 0x130f, 1); 1943 1944 /* Clear interrupts, by reading interrupt status registers */ 1945 cs8409_i2c_read(codec, CS42L42_I2C_ADDR, 0x1b7b, 1); 1946 1947 mutex_unlock(&spec->cs8409_i2c_mux); 1948 1949 /* If status values are < 0, read error has occurred. */ 1950 if (reg_cdc_status < 0 || reg_hs_status < 0 || reg_ts_status < 0) 1951 return; 1952 1953 /* HSDET_AUTO_DONE */ 1954 if (reg_cdc_status & CS42L42_HSDET_AUTO_DONE) { 1955 1956 type = ((reg_hs_status & CS42L42_HSTYPE_MASK) + 1); 1957 /* CS42L42 reports optical jack as type 4 1958 * We don't handle optical jack 1959 */ 1960 if (type != 4) { 1961 if (!spec->cs42l42_hp_jack_in) { 1962 status_changed = 1; 1963 spec->cs42l42_hp_jack_in = 1; 1964 } 1965 /* type = 3 has no mic */ 1966 if ((!spec->cs42l42_mic_jack_in) && (type != 3)) { 1967 status_changed = 1; 1968 spec->cs42l42_mic_jack_in = 1; 1969 } 1970 } else { 1971 if (spec->cs42l42_hp_jack_in || spec->cs42l42_mic_jack_in) { 1972 status_changed = 1; 1973 spec->cs42l42_hp_jack_in = 0; 1974 spec->cs42l42_mic_jack_in = 0; 1975 } 1976 } 1977 1978 } else { 1979 /* TIP_SENSE INSERT/REMOVE */ 1980 switch (reg_ts_status) { 1981 case CS42L42_JACK_INSERTED: 1982 cs8409_cs42l42_run_jack_detect(codec); 1983 break; 1984 1985 case CS42L42_JACK_REMOVED: 1986 if (spec->cs42l42_hp_jack_in || spec->cs42l42_mic_jack_in) { 1987 status_changed = 1; 1988 spec->cs42l42_hp_jack_in = 0; 1989 spec->cs42l42_mic_jack_in = 0; 1990 } 1991 break; 1992 1993 default: 1994 /* jack in transition */ 1995 status_changed = 0; 1996 break; 1997 } 1998 } 1999 2000 if (status_changed) { 2001 2002 snd_hda_set_pin_ctl(codec, CS8409_CS42L42_SPK_PIN_NID, 2003 spec->cs42l42_hp_jack_in ? 0 : PIN_OUT); 2004 2005 /* Report jack*/ 2006 jk = snd_hda_jack_tbl_get_mst(codec, CS8409_CS42L42_HP_PIN_NID, 0); 2007 if (jk) { 2008 snd_hda_jack_unsol_event(codec, 2009 (jk->tag << AC_UNSOL_RES_TAG_SHIFT) & AC_UNSOL_RES_TAG); 2010 } 2011 /* Report jack*/ 2012 jk = snd_hda_jack_tbl_get_mst(codec, CS8409_CS42L42_AMIC_PIN_NID, 0); 2013 if (jk) { 2014 snd_hda_jack_unsol_event(codec, 2015 (jk->tag << AC_UNSOL_RES_TAG_SHIFT) & AC_UNSOL_RES_TAG); 2016 } 2017 } 2018 } 2019 2020 #ifdef CONFIG_PM 2021 /* Manage PDREF, when transition to D3hot */ 2022 static int cs8409_suspend(struct hda_codec *codec) 2023 { 2024 struct cs_spec *spec = codec->spec; 2025 2026 mutex_lock(&spec->cs8409_i2c_mux); 2027 /* Power down CS42L42 ASP/EQ/MIX/HP */ 2028 cs8409_i2c_write(codec, CS42L42_I2C_ADDR, 0x1101, 0xfe, 1); 2029 mutex_unlock(&spec->cs8409_i2c_mux); 2030 /* Assert CS42L42 RTS# line */ 2031 snd_hda_codec_write(codec, 2032 codec->core.afg, 0, AC_VERB_SET_GPIO_DATA, 0); 2033 2034 snd_hda_shutup_pins(codec); 2035 2036 return 0; 2037 } 2038 #endif 2039 2040 /* Enable/Disable Unsolicited Response for gpio(s) 3,4 */ 2041 static void cs8409_enable_ur(struct hda_codec *codec, int flag) 2042 { 2043 /* GPIO4 INT# and GPIO3 WAKE# */ 2044 snd_hda_codec_write(codec, codec->core.afg, 2045 0, AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK, 2046 flag ? (GPIO3_INT | GPIO4_INT) : 0); 2047 2048 snd_hda_codec_write(codec, codec->core.afg, 2049 0, AC_VERB_SET_UNSOLICITED_ENABLE, 2050 flag ? AC_UNSOL_ENABLED : 0); 2051 2052 } 2053 2054 /* Vendor specific HW configuration 2055 * PLL, ASP, I2C, SPI, GPIOs, DMIC etc... 2056 */ 2057 static void cs8409_cs42l42_hw_init(struct hda_codec *codec) 2058 { 2059 const struct cs8409_cir_param *seq = cs8409_cs42l42_hw_cfg; 2060 const struct cs8409_cir_param *seq_bullseye = cs8409_cs42l42_bullseye_atn; 2061 struct cs_spec *spec = codec->spec; 2062 2063 if (spec->gpio_mask) { 2064 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_MASK, 2065 spec->gpio_mask); 2066 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DIRECTION, 2067 spec->gpio_dir); 2068 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 2069 spec->gpio_data); 2070 } 2071 2072 for (; seq->nid; seq++) 2073 cs_vendor_coef_set(codec, seq->cir, seq->coeff); 2074 2075 if (codec->fixup_id == CS8409_BULLSEYE) 2076 for (; seq_bullseye->nid; seq_bullseye++) 2077 cs_vendor_coef_set(codec, seq_bullseye->cir, seq_bullseye->coeff); 2078 2079 /* Disable Unsolicited Response during boot */ 2080 cs8409_enable_ur(codec, 0); 2081 2082 /* Reset CS42L42 */ 2083 cs8409_cs42l42_reset(codec); 2084 2085 /* Initialise CS42L42 companion codec */ 2086 cs8409_cs42l42_reg_setup(codec); 2087 2088 if (codec->fixup_id == CS8409_WARLOCK || 2089 codec->fixup_id == CS8409_CYBORG) { 2090 /* FULL_SCALE_VOL = 0 for Warlock / Cyborg */ 2091 mutex_lock(&spec->cs8409_i2c_mux); 2092 cs8409_i2c_write(codec, CS42L42_I2C_ADDR, 0x2001, 0x01, 1); 2093 mutex_unlock(&spec->cs8409_i2c_mux); 2094 /* DMIC1_MO=00b, DMIC1/2_SR=1 */ 2095 cs_vendor_coef_set(codec, 0x09, 0x0003); 2096 } 2097 2098 /* Restore Volumes after Resume */ 2099 if (spec->cs42l42_volume_init) { 2100 mutex_lock(&spec->cs8409_i2c_mux); 2101 cs8409_i2c_write(codec, CS42L42_I2C_ADDR, 2102 CS8409_CS42L42_REG_HS_VOLUME_CHA, 2103 -spec->cs42l42_hp_volume[0], 2104 1); 2105 cs8409_i2c_write(codec, CS42L42_I2C_ADDR, 2106 CS8409_CS42L42_REG_HS_VOLUME_CHB, 2107 -spec->cs42l42_hp_volume[1], 2108 1); 2109 cs8409_i2c_write(codec, CS42L42_I2C_ADDR, 2110 CS8409_CS42L42_REG_AMIC_VOLUME, 2111 spec->cs42l42_hs_mic_volume[0], 2112 1); 2113 mutex_unlock(&spec->cs8409_i2c_mux); 2114 } 2115 2116 cs8409_cs42l42_update_volume(codec); 2117 2118 cs8409_cs42l42_enable_jack_detect(codec); 2119 2120 /* Enable Unsolicited Response */ 2121 cs8409_enable_ur(codec, 1); 2122 } 2123 2124 static int cs8409_cs42l42_init(struct hda_codec *codec) 2125 { 2126 int ret = snd_hda_gen_init(codec); 2127 2128 if (!ret) 2129 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_INIT); 2130 2131 return ret; 2132 } 2133 2134 static const struct hda_codec_ops cs8409_cs42l42_patch_ops = { 2135 .build_controls = cs_build_controls, 2136 .build_pcms = snd_hda_gen_build_pcms, 2137 .init = cs8409_cs42l42_init, 2138 .free = cs_free, 2139 .unsol_event = cs8409_jack_unsol_event, 2140 #ifdef CONFIG_PM 2141 .suspend = cs8409_suspend, 2142 #endif 2143 }; 2144 2145 static void cs8409_cs42l42_fixups(struct hda_codec *codec, 2146 const struct hda_fixup *fix, int action) 2147 { 2148 struct cs_spec *spec = codec->spec; 2149 int caps; 2150 2151 switch (action) { 2152 case HDA_FIXUP_ACT_PRE_PROBE: 2153 snd_hda_add_verbs(codec, cs8409_cs42l42_init_verbs); 2154 /* verb exec op override */ 2155 spec->exec_verb = codec->core.exec_verb; 2156 codec->core.exec_verb = cs8409_cs42l42_exec_verb; 2157 2158 mutex_init(&spec->cs8409_i2c_mux); 2159 2160 codec->patch_ops = cs8409_cs42l42_patch_ops; 2161 2162 spec->gen.suppress_auto_mute = 1; 2163 spec->gen.no_primary_hp = 1; 2164 spec->gen.suppress_vmaster = 1; 2165 2166 /* GPIO 5 out, 3,4 in */ 2167 spec->gpio_dir = GPIO5_INT; 2168 spec->gpio_data = 0; 2169 spec->gpio_mask = 0x03f; 2170 2171 spec->cs42l42_hp_jack_in = 0; 2172 spec->cs42l42_mic_jack_in = 0; 2173 2174 /* Basic initial sequence for specific hw configuration */ 2175 snd_hda_sequence_write(codec, cs8409_cs42l42_init_verbs); 2176 2177 /* CS8409 is simple HDA bridge and intended to be used with a remote 2178 * companion codec. Most of input/output PIN(s) have only basic 2179 * capabilities. NID(s) 0x24 and 0x34 have only OUTC and INC 2180 * capabilities and no presence detect capable (PDC) and call to 2181 * snd_hda_gen_build_controls() will mark them as non detectable 2182 * phantom jacks. However, in this configuration companion codec 2183 * CS42L42 is connected to these pins and it has jack detect 2184 * capabilities. We have to override pin capabilities, 2185 * otherwise they will not be created as input devices. 2186 */ 2187 caps = snd_hdac_read_parm(&codec->core, CS8409_CS42L42_HP_PIN_NID, 2188 AC_PAR_PIN_CAP); 2189 if (caps >= 0) 2190 snd_hdac_override_parm(&codec->core, 2191 CS8409_CS42L42_HP_PIN_NID, AC_PAR_PIN_CAP, 2192 (caps | (AC_PINCAP_IMP_SENSE | AC_PINCAP_PRES_DETECT))); 2193 2194 caps = snd_hdac_read_parm(&codec->core, CS8409_CS42L42_AMIC_PIN_NID, 2195 AC_PAR_PIN_CAP); 2196 if (caps >= 0) 2197 snd_hdac_override_parm(&codec->core, 2198 CS8409_CS42L42_AMIC_PIN_NID, AC_PAR_PIN_CAP, 2199 (caps | (AC_PINCAP_IMP_SENSE | AC_PINCAP_PRES_DETECT))); 2200 2201 snd_hda_override_wcaps(codec, CS8409_CS42L42_HP_PIN_NID, 2202 (get_wcaps(codec, CS8409_CS42L42_HP_PIN_NID) | AC_WCAP_UNSOL_CAP)); 2203 2204 snd_hda_override_wcaps(codec, CS8409_CS42L42_AMIC_PIN_NID, 2205 (get_wcaps(codec, CS8409_CS42L42_AMIC_PIN_NID) | AC_WCAP_UNSOL_CAP)); 2206 break; 2207 case HDA_FIXUP_ACT_PROBE: 2208 2209 /* Set initial volume on Bullseye to -26 dB */ 2210 if (codec->fixup_id == CS8409_BULLSEYE) 2211 snd_hda_codec_amp_init_stereo(codec, CS8409_CS42L42_DMIC_ADC_PIN_NID, 2212 HDA_INPUT, 0, 0xff, 0x19); 2213 snd_hda_gen_add_kctl(&spec->gen, 2214 NULL, &cs8409_cs42l42_hp_volume_mixer); 2215 snd_hda_gen_add_kctl(&spec->gen, 2216 NULL, &cs8409_cs42l42_amic_volume_mixer); 2217 cs8409_cs42l42_hw_init(codec); 2218 snd_hda_codec_set_name(codec, "CS8409/CS42L42"); 2219 break; 2220 case HDA_FIXUP_ACT_INIT: 2221 cs8409_cs42l42_hw_init(codec); 2222 fallthrough; 2223 case HDA_FIXUP_ACT_BUILD: 2224 /* Run jack auto detect first time on boot 2225 * after controls have been added, to check if jack has 2226 * been already plugged in. 2227 * Run immediately after init. 2228 */ 2229 cs8409_cs42l42_run_jack_detect(codec); 2230 usleep_range(100000, 150000); 2231 break; 2232 default: 2233 break; 2234 } 2235 } 2236 2237 static int cs8409_cs42l42_exec_verb(struct hdac_device *dev, 2238 unsigned int cmd, unsigned int flags, unsigned int *res) 2239 { 2240 struct hda_codec *codec = container_of(dev, struct hda_codec, core); 2241 struct cs_spec *spec = codec->spec; 2242 2243 unsigned int nid = ((cmd >> 20) & 0x07f); 2244 unsigned int verb = ((cmd >> 8) & 0x0fff); 2245 2246 /* CS8409 pins have no AC_PINSENSE_PRESENCE 2247 * capabilities. We have to intercept 2 calls for pins 0x24 and 0x34 2248 * and return correct pin sense values for read_pin_sense() call from 2249 * hda_jack based on CS42L42 jack detect status. 2250 */ 2251 switch (nid) { 2252 case CS8409_CS42L42_HP_PIN_NID: 2253 if (verb == AC_VERB_GET_PIN_SENSE) { 2254 *res = (spec->cs42l42_hp_jack_in) ? AC_PINSENSE_PRESENCE : 0; 2255 return 0; 2256 } 2257 break; 2258 2259 case CS8409_CS42L42_AMIC_PIN_NID: 2260 if (verb == AC_VERB_GET_PIN_SENSE) { 2261 *res = (spec->cs42l42_mic_jack_in) ? AC_PINSENSE_PRESENCE : 0; 2262 return 0; 2263 } 2264 break; 2265 2266 default: 2267 break; 2268 } 2269 2270 return spec->exec_verb(dev, cmd, flags, res); 2271 } 2272 2273 static int patch_cs8409(struct hda_codec *codec) 2274 { 2275 int err; 2276 2277 if (!cs_alloc_spec(codec, CS8409_VENDOR_NID)) 2278 return -ENOMEM; 2279 2280 snd_hda_pick_fixup(codec, 2281 cs8409_models, cs8409_fixup_tbl, cs8409_fixups); 2282 2283 codec_dbg(codec, "Picked ID=%d, VID=%08x, DEV=%08x\n", 2284 codec->fixup_id, 2285 codec->bus->pci->subsystem_vendor, 2286 codec->bus->pci->subsystem_device); 2287 2288 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE); 2289 2290 err = cs_parse_auto_config(codec); 2291 if (err < 0) { 2292 cs_free(codec); 2293 return err; 2294 } 2295 2296 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE); 2297 return 0; 2298 } 2299 2300 /* 2301 * patch entries 2302 */ 2303 static const struct hda_device_id snd_hda_id_cirrus[] = { 2304 HDA_CODEC_ENTRY(0x10134206, "CS4206", patch_cs420x), 2305 HDA_CODEC_ENTRY(0x10134207, "CS4207", patch_cs420x), 2306 HDA_CODEC_ENTRY(0x10134208, "CS4208", patch_cs4208), 2307 HDA_CODEC_ENTRY(0x10134210, "CS4210", patch_cs4210), 2308 HDA_CODEC_ENTRY(0x10134213, "CS4213", patch_cs4213), 2309 HDA_CODEC_ENTRY(0x10138409, "CS8409", patch_cs8409), 2310 {} /* terminator */ 2311 }; 2312 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_cirrus); 2313 2314 MODULE_LICENSE("GPL"); 2315 MODULE_DESCRIPTION("Cirrus Logic HD-audio codec"); 2316 2317 static struct hda_codec_driver cirrus_driver = { 2318 .id = snd_hda_id_cirrus, 2319 }; 2320 2321 module_hda_codec_driver(cirrus_driver); 2322