1 /* 2 * HD audio interface patch for Creative CA0132 chip 3 * 4 * Copyright (c) 2011, Creative Technology Ltd. 5 * 6 * Based on patch_ca0110.c 7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de> 8 * 9 * This driver is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This driver is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 */ 23 24 #include <linux/init.h> 25 #include <linux/delay.h> 26 #include <linux/slab.h> 27 #include <linux/mutex.h> 28 #include <linux/module.h> 29 #include <linux/firmware.h> 30 #include <sound/core.h> 31 #include "hda_codec.h" 32 #include "hda_local.h" 33 #include "hda_auto_parser.h" 34 #include "hda_jack.h" 35 36 #include "ca0132_regs.h" 37 38 /* Enable this to see controls for tuning purpose. */ 39 /*#define ENABLE_TUNING_CONTROLS*/ 40 41 #define FLOAT_ZERO 0x00000000 42 #define FLOAT_ONE 0x3f800000 43 #define FLOAT_TWO 0x40000000 44 #define FLOAT_MINUS_5 0xc0a00000 45 46 #define UNSOL_TAG_HP 0x10 47 #define UNSOL_TAG_AMIC1 0x12 48 #define UNSOL_TAG_DSP 0x16 49 50 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18) 51 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15) 52 53 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8 54 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32 55 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2 56 57 #define MASTERCONTROL 0x80 58 #define MASTERCONTROL_ALLOC_DMA_CHAN 10 59 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60 60 61 #define WIDGET_CHIP_CTRL 0x15 62 #define WIDGET_DSP_CTRL 0x16 63 64 #define MEM_CONNID_MICIN1 3 65 #define MEM_CONNID_MICIN2 5 66 #define MEM_CONNID_MICOUT1 12 67 #define MEM_CONNID_MICOUT2 14 68 #define MEM_CONNID_WUH 10 69 #define MEM_CONNID_DSP 16 70 #define MEM_CONNID_DMIC 100 71 72 #define SCP_SET 0 73 #define SCP_GET 1 74 75 #define EFX_FILE "ctefx.bin" 76 77 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 78 MODULE_FIRMWARE(EFX_FILE); 79 #endif 80 81 static char *dirstr[2] = { "Playback", "Capture" }; 82 83 enum { 84 SPEAKER_OUT, 85 HEADPHONE_OUT 86 }; 87 88 enum { 89 DIGITAL_MIC, 90 LINE_MIC_IN 91 }; 92 93 enum { 94 #define VNODE_START_NID 0x80 95 VNID_SPK = VNODE_START_NID, /* Speaker vnid */ 96 VNID_MIC, 97 VNID_HP_SEL, 98 VNID_AMIC1_SEL, 99 VNID_HP_ASEL, 100 VNID_AMIC1_ASEL, 101 VNODE_END_NID, 102 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID) 103 104 #define EFFECT_START_NID 0x90 105 #define OUT_EFFECT_START_NID EFFECT_START_NID 106 SURROUND = OUT_EFFECT_START_NID, 107 CRYSTALIZER, 108 DIALOG_PLUS, 109 SMART_VOLUME, 110 X_BASS, 111 EQUALIZER, 112 OUT_EFFECT_END_NID, 113 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID) 114 115 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID 116 ECHO_CANCELLATION = IN_EFFECT_START_NID, 117 VOICE_FOCUS, 118 MIC_SVM, 119 NOISE_REDUCTION, 120 IN_EFFECT_END_NID, 121 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID) 122 123 VOICEFX = IN_EFFECT_END_NID, 124 PLAY_ENHANCEMENT, 125 CRYSTAL_VOICE, 126 EFFECT_END_NID 127 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID) 128 }; 129 130 /* Effects values size*/ 131 #define EFFECT_VALS_MAX_COUNT 12 132 133 /* Latency introduced by DSP blocks in milliseconds. */ 134 #define DSP_CAPTURE_INIT_LATENCY 0 135 #define DSP_CRYSTAL_VOICE_LATENCY 124 136 #define DSP_PLAYBACK_INIT_LATENCY 13 137 #define DSP_PLAY_ENHANCEMENT_LATENCY 30 138 #define DSP_SPEAKER_OUT_LATENCY 7 139 140 struct ct_effect { 141 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 142 hda_nid_t nid; 143 int mid; /*effect module ID*/ 144 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/ 145 int direct; /* 0:output; 1:input*/ 146 int params; /* number of default non-on/off params */ 147 /*effect default values, 1st is on/off. */ 148 unsigned int def_vals[EFFECT_VALS_MAX_COUNT]; 149 }; 150 151 #define EFX_DIR_OUT 0 152 #define EFX_DIR_IN 1 153 154 static struct ct_effect ca0132_effects[EFFECTS_COUNT] = { 155 { .name = "Surround", 156 .nid = SURROUND, 157 .mid = 0x96, 158 .reqs = {0, 1}, 159 .direct = EFX_DIR_OUT, 160 .params = 1, 161 .def_vals = {0x3F800000, 0x3F2B851F} 162 }, 163 { .name = "Crystalizer", 164 .nid = CRYSTALIZER, 165 .mid = 0x96, 166 .reqs = {7, 8}, 167 .direct = EFX_DIR_OUT, 168 .params = 1, 169 .def_vals = {0x3F800000, 0x3F266666} 170 }, 171 { .name = "Dialog Plus", 172 .nid = DIALOG_PLUS, 173 .mid = 0x96, 174 .reqs = {2, 3}, 175 .direct = EFX_DIR_OUT, 176 .params = 1, 177 .def_vals = {0x00000000, 0x3F000000} 178 }, 179 { .name = "Smart Volume", 180 .nid = SMART_VOLUME, 181 .mid = 0x96, 182 .reqs = {4, 5, 6}, 183 .direct = EFX_DIR_OUT, 184 .params = 2, 185 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000} 186 }, 187 { .name = "X-Bass", 188 .nid = X_BASS, 189 .mid = 0x96, 190 .reqs = {24, 23, 25}, 191 .direct = EFX_DIR_OUT, 192 .params = 2, 193 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000} 194 }, 195 { .name = "Equalizer", 196 .nid = EQUALIZER, 197 .mid = 0x96, 198 .reqs = {9, 10, 11, 12, 13, 14, 199 15, 16, 17, 18, 19, 20}, 200 .direct = EFX_DIR_OUT, 201 .params = 11, 202 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000, 203 0x00000000, 0x00000000, 0x00000000, 0x00000000, 204 0x00000000, 0x00000000, 0x00000000, 0x00000000} 205 }, 206 { .name = "Echo Cancellation", 207 .nid = ECHO_CANCELLATION, 208 .mid = 0x95, 209 .reqs = {0, 1, 2, 3}, 210 .direct = EFX_DIR_IN, 211 .params = 3, 212 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000} 213 }, 214 { .name = "Voice Focus", 215 .nid = VOICE_FOCUS, 216 .mid = 0x95, 217 .reqs = {6, 7, 8, 9}, 218 .direct = EFX_DIR_IN, 219 .params = 3, 220 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000} 221 }, 222 { .name = "Mic SVM", 223 .nid = MIC_SVM, 224 .mid = 0x95, 225 .reqs = {44, 45}, 226 .direct = EFX_DIR_IN, 227 .params = 1, 228 .def_vals = {0x00000000, 0x3F3D70A4} 229 }, 230 { .name = "Noise Reduction", 231 .nid = NOISE_REDUCTION, 232 .mid = 0x95, 233 .reqs = {4, 5}, 234 .direct = EFX_DIR_IN, 235 .params = 1, 236 .def_vals = {0x3F800000, 0x3F000000} 237 }, 238 { .name = "VoiceFX", 239 .nid = VOICEFX, 240 .mid = 0x95, 241 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}, 242 .direct = EFX_DIR_IN, 243 .params = 8, 244 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000, 245 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000, 246 0x00000000} 247 } 248 }; 249 250 /* Tuning controls */ 251 #ifdef ENABLE_TUNING_CONTROLS 252 253 enum { 254 #define TUNING_CTL_START_NID 0xC0 255 WEDGE_ANGLE = TUNING_CTL_START_NID, 256 SVM_LEVEL, 257 EQUALIZER_BAND_0, 258 EQUALIZER_BAND_1, 259 EQUALIZER_BAND_2, 260 EQUALIZER_BAND_3, 261 EQUALIZER_BAND_4, 262 EQUALIZER_BAND_5, 263 EQUALIZER_BAND_6, 264 EQUALIZER_BAND_7, 265 EQUALIZER_BAND_8, 266 EQUALIZER_BAND_9, 267 TUNING_CTL_END_NID 268 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID) 269 }; 270 271 struct ct_tuning_ctl { 272 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 273 hda_nid_t parent_nid; 274 hda_nid_t nid; 275 int mid; /*effect module ID*/ 276 int req; /*effect module request*/ 277 int direct; /* 0:output; 1:input*/ 278 unsigned int def_val;/*effect default values*/ 279 }; 280 281 static struct ct_tuning_ctl ca0132_tuning_ctls[] = { 282 { .name = "Wedge Angle", 283 .parent_nid = VOICE_FOCUS, 284 .nid = WEDGE_ANGLE, 285 .mid = 0x95, 286 .req = 8, 287 .direct = EFX_DIR_IN, 288 .def_val = 0x41F00000 289 }, 290 { .name = "SVM Level", 291 .parent_nid = MIC_SVM, 292 .nid = SVM_LEVEL, 293 .mid = 0x95, 294 .req = 45, 295 .direct = EFX_DIR_IN, 296 .def_val = 0x3F3D70A4 297 }, 298 { .name = "EQ Band0", 299 .parent_nid = EQUALIZER, 300 .nid = EQUALIZER_BAND_0, 301 .mid = 0x96, 302 .req = 11, 303 .direct = EFX_DIR_OUT, 304 .def_val = 0x00000000 305 }, 306 { .name = "EQ Band1", 307 .parent_nid = EQUALIZER, 308 .nid = EQUALIZER_BAND_1, 309 .mid = 0x96, 310 .req = 12, 311 .direct = EFX_DIR_OUT, 312 .def_val = 0x00000000 313 }, 314 { .name = "EQ Band2", 315 .parent_nid = EQUALIZER, 316 .nid = EQUALIZER_BAND_2, 317 .mid = 0x96, 318 .req = 13, 319 .direct = EFX_DIR_OUT, 320 .def_val = 0x00000000 321 }, 322 { .name = "EQ Band3", 323 .parent_nid = EQUALIZER, 324 .nid = EQUALIZER_BAND_3, 325 .mid = 0x96, 326 .req = 14, 327 .direct = EFX_DIR_OUT, 328 .def_val = 0x00000000 329 }, 330 { .name = "EQ Band4", 331 .parent_nid = EQUALIZER, 332 .nid = EQUALIZER_BAND_4, 333 .mid = 0x96, 334 .req = 15, 335 .direct = EFX_DIR_OUT, 336 .def_val = 0x00000000 337 }, 338 { .name = "EQ Band5", 339 .parent_nid = EQUALIZER, 340 .nid = EQUALIZER_BAND_5, 341 .mid = 0x96, 342 .req = 16, 343 .direct = EFX_DIR_OUT, 344 .def_val = 0x00000000 345 }, 346 { .name = "EQ Band6", 347 .parent_nid = EQUALIZER, 348 .nid = EQUALIZER_BAND_6, 349 .mid = 0x96, 350 .req = 17, 351 .direct = EFX_DIR_OUT, 352 .def_val = 0x00000000 353 }, 354 { .name = "EQ Band7", 355 .parent_nid = EQUALIZER, 356 .nid = EQUALIZER_BAND_7, 357 .mid = 0x96, 358 .req = 18, 359 .direct = EFX_DIR_OUT, 360 .def_val = 0x00000000 361 }, 362 { .name = "EQ Band8", 363 .parent_nid = EQUALIZER, 364 .nid = EQUALIZER_BAND_8, 365 .mid = 0x96, 366 .req = 19, 367 .direct = EFX_DIR_OUT, 368 .def_val = 0x00000000 369 }, 370 { .name = "EQ Band9", 371 .parent_nid = EQUALIZER, 372 .nid = EQUALIZER_BAND_9, 373 .mid = 0x96, 374 .req = 20, 375 .direct = EFX_DIR_OUT, 376 .def_val = 0x00000000 377 } 378 }; 379 #endif 380 381 /* Voice FX Presets */ 382 #define VOICEFX_MAX_PARAM_COUNT 9 383 384 struct ct_voicefx { 385 char *name; 386 hda_nid_t nid; 387 int mid; 388 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/ 389 }; 390 391 struct ct_voicefx_preset { 392 char *name; /*preset name*/ 393 unsigned int vals[VOICEFX_MAX_PARAM_COUNT]; 394 }; 395 396 static struct ct_voicefx ca0132_voicefx = { 397 .name = "VoiceFX Capture Switch", 398 .nid = VOICEFX, 399 .mid = 0x95, 400 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18} 401 }; 402 403 static struct ct_voicefx_preset ca0132_voicefx_presets[] = { 404 { .name = "Neutral", 405 .vals = { 0x00000000, 0x43C80000, 0x44AF0000, 406 0x44FA0000, 0x3F800000, 0x3F800000, 407 0x3F800000, 0x00000000, 0x00000000 } 408 }, 409 { .name = "Female2Male", 410 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 411 0x44FA0000, 0x3F19999A, 0x3F866666, 412 0x3F800000, 0x00000000, 0x00000000 } 413 }, 414 { .name = "Male2Female", 415 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 416 0x450AC000, 0x4017AE14, 0x3F6B851F, 417 0x3F800000, 0x00000000, 0x00000000 } 418 }, 419 { .name = "ScrappyKid", 420 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 421 0x44FA0000, 0x40400000, 0x3F28F5C3, 422 0x3F800000, 0x00000000, 0x00000000 } 423 }, 424 { .name = "Elderly", 425 .vals = { 0x3F800000, 0x44324000, 0x44BB8000, 426 0x44E10000, 0x3FB33333, 0x3FB9999A, 427 0x3F800000, 0x3E3A2E43, 0x00000000 } 428 }, 429 { .name = "Orc", 430 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000, 431 0x45098000, 0x3F266666, 0x3FC00000, 432 0x3F800000, 0x00000000, 0x00000000 } 433 }, 434 { .name = "Elf", 435 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000, 436 0x45193000, 0x3F8E147B, 0x3F75C28F, 437 0x3F800000, 0x00000000, 0x00000000 } 438 }, 439 { .name = "Dwarf", 440 .vals = { 0x3F800000, 0x43930000, 0x44BEE000, 441 0x45007000, 0x3F451EB8, 0x3F7851EC, 442 0x3F800000, 0x00000000, 0x00000000 } 443 }, 444 { .name = "AlienBrute", 445 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF, 446 0x451F6000, 0x3F266666, 0x3FA7D945, 447 0x3F800000, 0x3CF5C28F, 0x00000000 } 448 }, 449 { .name = "Robot", 450 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 451 0x44FA0000, 0x3FB2718B, 0x3F800000, 452 0xBC07010E, 0x00000000, 0x00000000 } 453 }, 454 { .name = "Marine", 455 .vals = { 0x3F800000, 0x43C20000, 0x44906000, 456 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71, 457 0x3F0A3D71, 0x00000000, 0x00000000 } 458 }, 459 { .name = "Emo", 460 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 461 0x44FA0000, 0x3F800000, 0x3F800000, 462 0x3E4CCCCD, 0x00000000, 0x00000000 } 463 }, 464 { .name = "DeepVoice", 465 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF, 466 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA, 467 0x3F800000, 0x00000000, 0x00000000 } 468 }, 469 { .name = "Munchkin", 470 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 471 0x44FA0000, 0x3F800000, 0x3F1A043C, 472 0x3F800000, 0x00000000, 0x00000000 } 473 } 474 }; 475 476 enum hda_cmd_vendor_io { 477 /* for DspIO node */ 478 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000, 479 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100, 480 481 VENDOR_DSPIO_STATUS = 0xF01, 482 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702, 483 VENDOR_DSPIO_SCP_READ_DATA = 0xF02, 484 VENDOR_DSPIO_DSP_INIT = 0x703, 485 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704, 486 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04, 487 488 /* for ChipIO node */ 489 VENDOR_CHIPIO_ADDRESS_LOW = 0x000, 490 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100, 491 VENDOR_CHIPIO_STREAM_FORMAT = 0x200, 492 VENDOR_CHIPIO_DATA_LOW = 0x300, 493 VENDOR_CHIPIO_DATA_HIGH = 0x400, 494 495 VENDOR_CHIPIO_GET_PARAMETER = 0xF00, 496 VENDOR_CHIPIO_STATUS = 0xF01, 497 VENDOR_CHIPIO_HIC_POST_READ = 0x702, 498 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03, 499 500 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707, 501 VENDOR_CHIPIO_8051_DATA_READ = 0xF07, 502 503 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A, 504 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A, 505 506 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C, 507 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C, 508 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D, 509 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E, 510 VENDOR_CHIPIO_FLAG_SET = 0x70F, 511 VENDOR_CHIPIO_FLAGS_GET = 0xF0F, 512 VENDOR_CHIPIO_PARAM_SET = 0x710, 513 VENDOR_CHIPIO_PARAM_GET = 0xF10, 514 515 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711, 516 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712, 517 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12, 518 VENDOR_CHIPIO_PORT_FREE_SET = 0x713, 519 520 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17, 521 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717, 522 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18, 523 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718, 524 525 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788, 526 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88, 527 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789, 528 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89, 529 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A, 530 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A, 531 532 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D 533 }; 534 535 /* 536 * Control flag IDs 537 */ 538 enum control_flag_id { 539 /* Connection manager stream setup is bypassed/enabled */ 540 CONTROL_FLAG_C_MGR = 0, 541 /* DSP DMA is bypassed/enabled */ 542 CONTROL_FLAG_DMA = 1, 543 /* 8051 'idle' mode is disabled/enabled */ 544 CONTROL_FLAG_IDLE_ENABLE = 2, 545 /* Tracker for the SPDIF-in path is bypassed/enabled */ 546 CONTROL_FLAG_TRACKER = 3, 547 /* DigitalOut to Spdif2Out connection is disabled/enabled */ 548 CONTROL_FLAG_SPDIF2OUT = 4, 549 /* Digital Microphone is disabled/enabled */ 550 CONTROL_FLAG_DMIC = 5, 551 /* ADC_B rate is 48 kHz/96 kHz */ 552 CONTROL_FLAG_ADC_B_96KHZ = 6, 553 /* ADC_C rate is 48 kHz/96 kHz */ 554 CONTROL_FLAG_ADC_C_96KHZ = 7, 555 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */ 556 CONTROL_FLAG_DAC_96KHZ = 8, 557 /* DSP rate is 48 kHz/96 kHz */ 558 CONTROL_FLAG_DSP_96KHZ = 9, 559 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */ 560 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10, 561 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */ 562 CONTROL_FLAG_SRC_RATE_96KHZ = 11, 563 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */ 564 CONTROL_FLAG_DECODE_LOOP = 12, 565 /* De-emphasis filter on DAC-1 disabled/enabled */ 566 CONTROL_FLAG_DAC1_DEEMPHASIS = 13, 567 /* De-emphasis filter on DAC-2 disabled/enabled */ 568 CONTROL_FLAG_DAC2_DEEMPHASIS = 14, 569 /* De-emphasis filter on DAC-3 disabled/enabled */ 570 CONTROL_FLAG_DAC3_DEEMPHASIS = 15, 571 /* High-pass filter on ADC_B disabled/enabled */ 572 CONTROL_FLAG_ADC_B_HIGH_PASS = 16, 573 /* High-pass filter on ADC_C disabled/enabled */ 574 CONTROL_FLAG_ADC_C_HIGH_PASS = 17, 575 /* Common mode on Port_A disabled/enabled */ 576 CONTROL_FLAG_PORT_A_COMMON_MODE = 18, 577 /* Common mode on Port_D disabled/enabled */ 578 CONTROL_FLAG_PORT_D_COMMON_MODE = 19, 579 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */ 580 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20, 581 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */ 582 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21, 583 /* ASI rate is 48kHz/96kHz */ 584 CONTROL_FLAG_ASI_96KHZ = 22, 585 /* DAC power settings able to control attached ports no/yes */ 586 CONTROL_FLAG_DACS_CONTROL_PORTS = 23, 587 /* Clock Stop OK reporting is disabled/enabled */ 588 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24, 589 /* Number of control flags */ 590 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1) 591 }; 592 593 /* 594 * Control parameter IDs 595 */ 596 enum control_param_id { 597 /* 0: None, 1: Mic1In*/ 598 CONTROL_PARAM_VIP_SOURCE = 1, 599 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */ 600 CONTROL_PARAM_SPDIF1_SOURCE = 2, 601 /* Port A output stage gain setting to use when 16 Ohm output 602 * impedance is selected*/ 603 CONTROL_PARAM_PORTA_160OHM_GAIN = 8, 604 /* Port D output stage gain setting to use when 16 Ohm output 605 * impedance is selected*/ 606 CONTROL_PARAM_PORTD_160OHM_GAIN = 10, 607 608 /* Stream Control */ 609 610 /* Select stream with the given ID */ 611 CONTROL_PARAM_STREAM_ID = 24, 612 /* Source connection point for the selected stream */ 613 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25, 614 /* Destination connection point for the selected stream */ 615 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26, 616 /* Number of audio channels in the selected stream */ 617 CONTROL_PARAM_STREAMS_CHANNELS = 27, 618 /*Enable control for the selected stream */ 619 CONTROL_PARAM_STREAM_CONTROL = 28, 620 621 /* Connection Point Control */ 622 623 /* Select connection point with the given ID */ 624 CONTROL_PARAM_CONN_POINT_ID = 29, 625 /* Connection point sample rate */ 626 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30, 627 628 /* Node Control */ 629 630 /* Select HDA node with the given ID */ 631 CONTROL_PARAM_NODE_ID = 31 632 }; 633 634 /* 635 * Dsp Io Status codes 636 */ 637 enum hda_vendor_status_dspio { 638 /* Success */ 639 VENDOR_STATUS_DSPIO_OK = 0x00, 640 /* Busy, unable to accept new command, the host must retry */ 641 VENDOR_STATUS_DSPIO_BUSY = 0x01, 642 /* SCP command queue is full */ 643 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02, 644 /* SCP response queue is empty */ 645 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03 646 }; 647 648 /* 649 * Chip Io Status codes 650 */ 651 enum hda_vendor_status_chipio { 652 /* Success */ 653 VENDOR_STATUS_CHIPIO_OK = 0x00, 654 /* Busy, unable to accept new command, the host must retry */ 655 VENDOR_STATUS_CHIPIO_BUSY = 0x01 656 }; 657 658 /* 659 * CA0132 sample rate 660 */ 661 enum ca0132_sample_rate { 662 SR_6_000 = 0x00, 663 SR_8_000 = 0x01, 664 SR_9_600 = 0x02, 665 SR_11_025 = 0x03, 666 SR_16_000 = 0x04, 667 SR_22_050 = 0x05, 668 SR_24_000 = 0x06, 669 SR_32_000 = 0x07, 670 SR_44_100 = 0x08, 671 SR_48_000 = 0x09, 672 SR_88_200 = 0x0A, 673 SR_96_000 = 0x0B, 674 SR_144_000 = 0x0C, 675 SR_176_400 = 0x0D, 676 SR_192_000 = 0x0E, 677 SR_384_000 = 0x0F, 678 679 SR_COUNT = 0x10, 680 681 SR_RATE_UNKNOWN = 0x1F 682 }; 683 684 enum dsp_download_state { 685 DSP_DOWNLOAD_FAILED = -1, 686 DSP_DOWNLOAD_INIT = 0, 687 DSP_DOWNLOADING = 1, 688 DSP_DOWNLOADED = 2 689 }; 690 691 /* retrieve parameters from hda format */ 692 #define get_hdafmt_chs(fmt) (fmt & 0xf) 693 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7) 694 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f) 695 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1) 696 697 /* 698 * CA0132 specific 699 */ 700 701 struct ca0132_spec { 702 struct snd_kcontrol_new *mixers[5]; 703 unsigned int num_mixers; 704 const struct hda_verb *base_init_verbs; 705 const struct hda_verb *base_exit_verbs; 706 const struct hda_verb *init_verbs[5]; 707 unsigned int num_init_verbs; /* exclude base init verbs */ 708 struct auto_pin_cfg autocfg; 709 710 /* Nodes configurations */ 711 struct hda_multi_out multiout; 712 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS]; 713 hda_nid_t dacs[AUTO_CFG_MAX_OUTS]; 714 unsigned int num_outputs; 715 hda_nid_t input_pins[AUTO_PIN_LAST]; 716 hda_nid_t adcs[AUTO_PIN_LAST]; 717 hda_nid_t dig_out; 718 hda_nid_t dig_in; 719 unsigned int num_inputs; 720 hda_nid_t shared_mic_nid; 721 hda_nid_t shared_out_nid; 722 struct hda_pcm pcm_rec[5]; /* PCM information */ 723 724 /* chip access */ 725 struct mutex chipio_mutex; /* chip access mutex */ 726 u32 curr_chip_addx; 727 728 /* DSP download related */ 729 enum dsp_download_state dsp_state; 730 unsigned int dsp_stream_id; 731 unsigned int wait_scp; 732 unsigned int wait_scp_header; 733 unsigned int wait_num_data; 734 unsigned int scp_resp_header; 735 unsigned int scp_resp_data[4]; 736 unsigned int scp_resp_count; 737 738 /* mixer and effects related */ 739 unsigned char dmic_ctl; 740 int cur_out_type; 741 int cur_mic_type; 742 long vnode_lvol[VNODES_COUNT]; 743 long vnode_rvol[VNODES_COUNT]; 744 long vnode_lswitch[VNODES_COUNT]; 745 long vnode_rswitch[VNODES_COUNT]; 746 long effects_switch[EFFECTS_COUNT]; 747 long voicefx_val; 748 long cur_mic_boost; 749 750 struct hda_codec *codec; 751 struct delayed_work unsol_hp_work; 752 753 #ifdef ENABLE_TUNING_CONTROLS 754 long cur_ctl_vals[TUNING_CTLS_COUNT]; 755 #endif 756 }; 757 758 /* 759 * CA0132 codec access 760 */ 761 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid, 762 unsigned int verb, unsigned int parm, unsigned int *res) 763 { 764 unsigned int response; 765 response = snd_hda_codec_read(codec, nid, 0, verb, parm); 766 *res = response; 767 768 return ((response == -1) ? -1 : 0); 769 } 770 771 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid, 772 unsigned short converter_format, unsigned int *res) 773 { 774 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT, 775 converter_format & 0xffff, res); 776 } 777 778 static int codec_set_converter_stream_channel(struct hda_codec *codec, 779 hda_nid_t nid, unsigned char stream, 780 unsigned char channel, unsigned int *res) 781 { 782 unsigned char converter_stream_channel = 0; 783 784 converter_stream_channel = (stream << 4) | (channel & 0x0f); 785 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID, 786 converter_stream_channel, res); 787 } 788 789 /* Chip access helper function */ 790 static int chipio_send(struct hda_codec *codec, 791 unsigned int reg, 792 unsigned int data) 793 { 794 unsigned int res; 795 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 796 797 /* send bits of data specified by reg */ 798 do { 799 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 800 reg, data); 801 if (res == VENDOR_STATUS_CHIPIO_OK) 802 return 0; 803 msleep(20); 804 } while (time_before(jiffies, timeout)); 805 806 return -EIO; 807 } 808 809 /* 810 * Write chip address through the vendor widget -- NOT protected by the Mutex! 811 */ 812 static int chipio_write_address(struct hda_codec *codec, 813 unsigned int chip_addx) 814 { 815 struct ca0132_spec *spec = codec->spec; 816 int res; 817 818 if (spec->curr_chip_addx == chip_addx) 819 return 0; 820 821 /* send low 16 bits of the address */ 822 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW, 823 chip_addx & 0xffff); 824 825 if (res != -EIO) { 826 /* send high 16 bits of the address */ 827 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH, 828 chip_addx >> 16); 829 } 830 831 spec->curr_chip_addx = (res < 0) ? ~0UL : chip_addx; 832 833 return res; 834 } 835 836 /* 837 * Write data through the vendor widget -- NOT protected by the Mutex! 838 */ 839 static int chipio_write_data(struct hda_codec *codec, unsigned int data) 840 { 841 struct ca0132_spec *spec = codec->spec; 842 int res; 843 844 /* send low 16 bits of the data */ 845 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff); 846 847 if (res != -EIO) { 848 /* send high 16 bits of the data */ 849 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH, 850 data >> 16); 851 } 852 853 /*If no error encountered, automatically increment the address 854 as per chip behaviour*/ 855 spec->curr_chip_addx = (res != -EIO) ? 856 (spec->curr_chip_addx + 4) : ~0UL; 857 return res; 858 } 859 860 /* 861 * Write multiple data through the vendor widget -- NOT protected by the Mutex! 862 */ 863 static int chipio_write_data_multiple(struct hda_codec *codec, 864 const u32 *data, 865 unsigned int count) 866 { 867 int status = 0; 868 869 if (data == NULL) { 870 codec_dbg(codec, "chipio_write_data null ptr\n"); 871 return -EINVAL; 872 } 873 874 while ((count-- != 0) && (status == 0)) 875 status = chipio_write_data(codec, *data++); 876 877 return status; 878 } 879 880 881 /* 882 * Read data through the vendor widget -- NOT protected by the Mutex! 883 */ 884 static int chipio_read_data(struct hda_codec *codec, unsigned int *data) 885 { 886 struct ca0132_spec *spec = codec->spec; 887 int res; 888 889 /* post read */ 890 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0); 891 892 if (res != -EIO) { 893 /* read status */ 894 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 895 } 896 897 if (res != -EIO) { 898 /* read data */ 899 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 900 VENDOR_CHIPIO_HIC_READ_DATA, 901 0); 902 } 903 904 /*If no error encountered, automatically increment the address 905 as per chip behaviour*/ 906 spec->curr_chip_addx = (res != -EIO) ? 907 (spec->curr_chip_addx + 4) : ~0UL; 908 return res; 909 } 910 911 /* 912 * Write given value to the given address through the chip I/O widget. 913 * protected by the Mutex 914 */ 915 static int chipio_write(struct hda_codec *codec, 916 unsigned int chip_addx, const unsigned int data) 917 { 918 struct ca0132_spec *spec = codec->spec; 919 int err; 920 921 mutex_lock(&spec->chipio_mutex); 922 923 /* write the address, and if successful proceed to write data */ 924 err = chipio_write_address(codec, chip_addx); 925 if (err < 0) 926 goto exit; 927 928 err = chipio_write_data(codec, data); 929 if (err < 0) 930 goto exit; 931 932 exit: 933 mutex_unlock(&spec->chipio_mutex); 934 return err; 935 } 936 937 /* 938 * Write multiple values to the given address through the chip I/O widget. 939 * protected by the Mutex 940 */ 941 static int chipio_write_multiple(struct hda_codec *codec, 942 u32 chip_addx, 943 const u32 *data, 944 unsigned int count) 945 { 946 struct ca0132_spec *spec = codec->spec; 947 int status; 948 949 mutex_lock(&spec->chipio_mutex); 950 status = chipio_write_address(codec, chip_addx); 951 if (status < 0) 952 goto error; 953 954 status = chipio_write_data_multiple(codec, data, count); 955 error: 956 mutex_unlock(&spec->chipio_mutex); 957 958 return status; 959 } 960 961 /* 962 * Read the given address through the chip I/O widget 963 * protected by the Mutex 964 */ 965 static int chipio_read(struct hda_codec *codec, 966 unsigned int chip_addx, unsigned int *data) 967 { 968 struct ca0132_spec *spec = codec->spec; 969 int err; 970 971 mutex_lock(&spec->chipio_mutex); 972 973 /* write the address, and if successful proceed to write data */ 974 err = chipio_write_address(codec, chip_addx); 975 if (err < 0) 976 goto exit; 977 978 err = chipio_read_data(codec, data); 979 if (err < 0) 980 goto exit; 981 982 exit: 983 mutex_unlock(&spec->chipio_mutex); 984 return err; 985 } 986 987 /* 988 * Set chip control flags through the chip I/O widget. 989 */ 990 static void chipio_set_control_flag(struct hda_codec *codec, 991 enum control_flag_id flag_id, 992 bool flag_state) 993 { 994 unsigned int val; 995 unsigned int flag_bit; 996 997 flag_bit = (flag_state ? 1 : 0); 998 val = (flag_bit << 7) | (flag_id); 999 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1000 VENDOR_CHIPIO_FLAG_SET, val); 1001 } 1002 1003 /* 1004 * Set chip parameters through the chip I/O widget. 1005 */ 1006 static void chipio_set_control_param(struct hda_codec *codec, 1007 enum control_param_id param_id, int param_val) 1008 { 1009 struct ca0132_spec *spec = codec->spec; 1010 int val; 1011 1012 if ((param_id < 32) && (param_val < 8)) { 1013 val = (param_val << 5) | (param_id); 1014 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1015 VENDOR_CHIPIO_PARAM_SET, val); 1016 } else { 1017 mutex_lock(&spec->chipio_mutex); 1018 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1019 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1020 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1021 param_id); 1022 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1023 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1024 param_val); 1025 } 1026 mutex_unlock(&spec->chipio_mutex); 1027 } 1028 } 1029 1030 /* 1031 * Set sampling rate of the connection point. 1032 */ 1033 static void chipio_set_conn_rate(struct hda_codec *codec, 1034 int connid, enum ca0132_sample_rate rate) 1035 { 1036 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid); 1037 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, 1038 rate); 1039 } 1040 1041 /* 1042 * Enable clocks. 1043 */ 1044 static void chipio_enable_clocks(struct hda_codec *codec) 1045 { 1046 struct ca0132_spec *spec = codec->spec; 1047 1048 mutex_lock(&spec->chipio_mutex); 1049 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1050 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0); 1051 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1052 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); 1053 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1054 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5); 1055 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1056 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b); 1057 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1058 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6); 1059 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1060 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); 1061 mutex_unlock(&spec->chipio_mutex); 1062 } 1063 1064 /* 1065 * CA0132 DSP IO stuffs 1066 */ 1067 static int dspio_send(struct hda_codec *codec, unsigned int reg, 1068 unsigned int data) 1069 { 1070 int res; 1071 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1072 1073 /* send bits of data specified by reg to dsp */ 1074 do { 1075 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data); 1076 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY)) 1077 return res; 1078 msleep(20); 1079 } while (time_before(jiffies, timeout)); 1080 1081 return -EIO; 1082 } 1083 1084 /* 1085 * Wait for DSP to be ready for commands 1086 */ 1087 static void dspio_write_wait(struct hda_codec *codec) 1088 { 1089 int status; 1090 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1091 1092 do { 1093 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1094 VENDOR_DSPIO_STATUS, 0); 1095 if ((status == VENDOR_STATUS_DSPIO_OK) || 1096 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)) 1097 break; 1098 msleep(1); 1099 } while (time_before(jiffies, timeout)); 1100 } 1101 1102 /* 1103 * Write SCP data to DSP 1104 */ 1105 static int dspio_write(struct hda_codec *codec, unsigned int scp_data) 1106 { 1107 struct ca0132_spec *spec = codec->spec; 1108 int status; 1109 1110 dspio_write_wait(codec); 1111 1112 mutex_lock(&spec->chipio_mutex); 1113 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW, 1114 scp_data & 0xffff); 1115 if (status < 0) 1116 goto error; 1117 1118 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH, 1119 scp_data >> 16); 1120 if (status < 0) 1121 goto error; 1122 1123 /* OK, now check if the write itself has executed*/ 1124 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1125 VENDOR_DSPIO_STATUS, 0); 1126 error: 1127 mutex_unlock(&spec->chipio_mutex); 1128 1129 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ? 1130 -EIO : 0; 1131 } 1132 1133 /* 1134 * Write multiple SCP data to DSP 1135 */ 1136 static int dspio_write_multiple(struct hda_codec *codec, 1137 unsigned int *buffer, unsigned int size) 1138 { 1139 int status = 0; 1140 unsigned int count; 1141 1142 if ((buffer == NULL)) 1143 return -EINVAL; 1144 1145 count = 0; 1146 while (count < size) { 1147 status = dspio_write(codec, *buffer++); 1148 if (status != 0) 1149 break; 1150 count++; 1151 } 1152 1153 return status; 1154 } 1155 1156 static int dspio_read(struct hda_codec *codec, unsigned int *data) 1157 { 1158 int status; 1159 1160 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0); 1161 if (status == -EIO) 1162 return status; 1163 1164 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0); 1165 if (status == -EIO || 1166 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY) 1167 return -EIO; 1168 1169 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1170 VENDOR_DSPIO_SCP_READ_DATA, 0); 1171 1172 return 0; 1173 } 1174 1175 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer, 1176 unsigned int *buf_size, unsigned int size_count) 1177 { 1178 int status = 0; 1179 unsigned int size = *buf_size; 1180 unsigned int count; 1181 unsigned int skip_count; 1182 unsigned int dummy; 1183 1184 if ((buffer == NULL)) 1185 return -1; 1186 1187 count = 0; 1188 while (count < size && count < size_count) { 1189 status = dspio_read(codec, buffer++); 1190 if (status != 0) 1191 break; 1192 count++; 1193 } 1194 1195 skip_count = count; 1196 if (status == 0) { 1197 while (skip_count < size) { 1198 status = dspio_read(codec, &dummy); 1199 if (status != 0) 1200 break; 1201 skip_count++; 1202 } 1203 } 1204 *buf_size = count; 1205 1206 return status; 1207 } 1208 1209 /* 1210 * Construct the SCP header using corresponding fields 1211 */ 1212 static inline unsigned int 1213 make_scp_header(unsigned int target_id, unsigned int source_id, 1214 unsigned int get_flag, unsigned int req, 1215 unsigned int device_flag, unsigned int resp_flag, 1216 unsigned int error_flag, unsigned int data_size) 1217 { 1218 unsigned int header = 0; 1219 1220 header = (data_size & 0x1f) << 27; 1221 header |= (error_flag & 0x01) << 26; 1222 header |= (resp_flag & 0x01) << 25; 1223 header |= (device_flag & 0x01) << 24; 1224 header |= (req & 0x7f) << 17; 1225 header |= (get_flag & 0x01) << 16; 1226 header |= (source_id & 0xff) << 8; 1227 header |= target_id & 0xff; 1228 1229 return header; 1230 } 1231 1232 /* 1233 * Extract corresponding fields from SCP header 1234 */ 1235 static inline void 1236 extract_scp_header(unsigned int header, 1237 unsigned int *target_id, unsigned int *source_id, 1238 unsigned int *get_flag, unsigned int *req, 1239 unsigned int *device_flag, unsigned int *resp_flag, 1240 unsigned int *error_flag, unsigned int *data_size) 1241 { 1242 if (data_size) 1243 *data_size = (header >> 27) & 0x1f; 1244 if (error_flag) 1245 *error_flag = (header >> 26) & 0x01; 1246 if (resp_flag) 1247 *resp_flag = (header >> 25) & 0x01; 1248 if (device_flag) 1249 *device_flag = (header >> 24) & 0x01; 1250 if (req) 1251 *req = (header >> 17) & 0x7f; 1252 if (get_flag) 1253 *get_flag = (header >> 16) & 0x01; 1254 if (source_id) 1255 *source_id = (header >> 8) & 0xff; 1256 if (target_id) 1257 *target_id = header & 0xff; 1258 } 1259 1260 #define SCP_MAX_DATA_WORDS (16) 1261 1262 /* Structure to contain any SCP message */ 1263 struct scp_msg { 1264 unsigned int hdr; 1265 unsigned int data[SCP_MAX_DATA_WORDS]; 1266 }; 1267 1268 static void dspio_clear_response_queue(struct hda_codec *codec) 1269 { 1270 unsigned int dummy = 0; 1271 int status = -1; 1272 1273 /* clear all from the response queue */ 1274 do { 1275 status = dspio_read(codec, &dummy); 1276 } while (status == 0); 1277 } 1278 1279 static int dspio_get_response_data(struct hda_codec *codec) 1280 { 1281 struct ca0132_spec *spec = codec->spec; 1282 unsigned int data = 0; 1283 unsigned int count; 1284 1285 if (dspio_read(codec, &data) < 0) 1286 return -EIO; 1287 1288 if ((data & 0x00ffffff) == spec->wait_scp_header) { 1289 spec->scp_resp_header = data; 1290 spec->scp_resp_count = data >> 27; 1291 count = spec->wait_num_data; 1292 dspio_read_multiple(codec, spec->scp_resp_data, 1293 &spec->scp_resp_count, count); 1294 return 0; 1295 } 1296 1297 return -EIO; 1298 } 1299 1300 /* 1301 * Send SCP message to DSP 1302 */ 1303 static int dspio_send_scp_message(struct hda_codec *codec, 1304 unsigned char *send_buf, 1305 unsigned int send_buf_size, 1306 unsigned char *return_buf, 1307 unsigned int return_buf_size, 1308 unsigned int *bytes_returned) 1309 { 1310 struct ca0132_spec *spec = codec->spec; 1311 int status = -1; 1312 unsigned int scp_send_size = 0; 1313 unsigned int total_size; 1314 bool waiting_for_resp = false; 1315 unsigned int header; 1316 struct scp_msg *ret_msg; 1317 unsigned int resp_src_id, resp_target_id; 1318 unsigned int data_size, src_id, target_id, get_flag, device_flag; 1319 1320 if (bytes_returned) 1321 *bytes_returned = 0; 1322 1323 /* get scp header from buffer */ 1324 header = *((unsigned int *)send_buf); 1325 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL, 1326 &device_flag, NULL, NULL, &data_size); 1327 scp_send_size = data_size + 1; 1328 total_size = (scp_send_size * 4); 1329 1330 if (send_buf_size < total_size) 1331 return -EINVAL; 1332 1333 if (get_flag || device_flag) { 1334 if (!return_buf || return_buf_size < 4 || !bytes_returned) 1335 return -EINVAL; 1336 1337 spec->wait_scp_header = *((unsigned int *)send_buf); 1338 1339 /* swap source id with target id */ 1340 resp_target_id = src_id; 1341 resp_src_id = target_id; 1342 spec->wait_scp_header &= 0xffff0000; 1343 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id); 1344 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1; 1345 spec->wait_scp = 1; 1346 waiting_for_resp = true; 1347 } 1348 1349 status = dspio_write_multiple(codec, (unsigned int *)send_buf, 1350 scp_send_size); 1351 if (status < 0) { 1352 spec->wait_scp = 0; 1353 return status; 1354 } 1355 1356 if (waiting_for_resp) { 1357 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1358 memset(return_buf, 0, return_buf_size); 1359 do { 1360 msleep(20); 1361 } while (spec->wait_scp && time_before(jiffies, timeout)); 1362 waiting_for_resp = false; 1363 if (!spec->wait_scp) { 1364 ret_msg = (struct scp_msg *)return_buf; 1365 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4); 1366 memcpy(&ret_msg->data, spec->scp_resp_data, 1367 spec->wait_num_data); 1368 *bytes_returned = (spec->scp_resp_count + 1) * 4; 1369 status = 0; 1370 } else { 1371 status = -EIO; 1372 } 1373 spec->wait_scp = 0; 1374 } 1375 1376 return status; 1377 } 1378 1379 /** 1380 * Prepare and send the SCP message to DSP 1381 * @codec: the HDA codec 1382 * @mod_id: ID of the DSP module to send the command 1383 * @req: ID of request to send to the DSP module 1384 * @dir: SET or GET 1385 * @data: pointer to the data to send with the request, request specific 1386 * @len: length of the data, in bytes 1387 * @reply: point to the buffer to hold data returned for a reply 1388 * @reply_len: length of the reply buffer returned from GET 1389 * 1390 * Returns zero or a negative error code. 1391 */ 1392 static int dspio_scp(struct hda_codec *codec, 1393 int mod_id, int req, int dir, void *data, unsigned int len, 1394 void *reply, unsigned int *reply_len) 1395 { 1396 int status = 0; 1397 struct scp_msg scp_send, scp_reply; 1398 unsigned int ret_bytes, send_size, ret_size; 1399 unsigned int send_get_flag, reply_resp_flag, reply_error_flag; 1400 unsigned int reply_data_size; 1401 1402 memset(&scp_send, 0, sizeof(scp_send)); 1403 memset(&scp_reply, 0, sizeof(scp_reply)); 1404 1405 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS)) 1406 return -EINVAL; 1407 1408 if (dir == SCP_GET && reply == NULL) { 1409 codec_dbg(codec, "dspio_scp get but has no buffer\n"); 1410 return -EINVAL; 1411 } 1412 1413 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) { 1414 codec_dbg(codec, "dspio_scp bad resp buf len parms\n"); 1415 return -EINVAL; 1416 } 1417 1418 scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req, 1419 0, 0, 0, len/sizeof(unsigned int)); 1420 if (data != NULL && len > 0) { 1421 len = min((unsigned int)(sizeof(scp_send.data)), len); 1422 memcpy(scp_send.data, data, len); 1423 } 1424 1425 ret_bytes = 0; 1426 send_size = sizeof(unsigned int) + len; 1427 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send, 1428 send_size, (unsigned char *)&scp_reply, 1429 sizeof(scp_reply), &ret_bytes); 1430 1431 if (status < 0) { 1432 codec_dbg(codec, "dspio_scp: send scp msg failed\n"); 1433 return status; 1434 } 1435 1436 /* extract send and reply headers members */ 1437 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag, 1438 NULL, NULL, NULL, NULL, NULL); 1439 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL, 1440 &reply_resp_flag, &reply_error_flag, 1441 &reply_data_size); 1442 1443 if (!send_get_flag) 1444 return 0; 1445 1446 if (reply_resp_flag && !reply_error_flag) { 1447 ret_size = (ret_bytes - sizeof(scp_reply.hdr)) 1448 / sizeof(unsigned int); 1449 1450 if (*reply_len < ret_size*sizeof(unsigned int)) { 1451 codec_dbg(codec, "reply too long for buf\n"); 1452 return -EINVAL; 1453 } else if (ret_size != reply_data_size) { 1454 codec_dbg(codec, "RetLen and HdrLen .NE.\n"); 1455 return -EINVAL; 1456 } else { 1457 *reply_len = ret_size*sizeof(unsigned int); 1458 memcpy(reply, scp_reply.data, *reply_len); 1459 } 1460 } else { 1461 codec_dbg(codec, "reply ill-formed or errflag set\n"); 1462 return -EIO; 1463 } 1464 1465 return status; 1466 } 1467 1468 /* 1469 * Set DSP parameters 1470 */ 1471 static int dspio_set_param(struct hda_codec *codec, int mod_id, 1472 int req, void *data, unsigned int len) 1473 { 1474 return dspio_scp(codec, mod_id, req, SCP_SET, data, len, NULL, NULL); 1475 } 1476 1477 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id, 1478 int req, unsigned int data) 1479 { 1480 return dspio_set_param(codec, mod_id, req, &data, sizeof(unsigned int)); 1481 } 1482 1483 /* 1484 * Allocate a DSP DMA channel via an SCP message 1485 */ 1486 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan) 1487 { 1488 int status = 0; 1489 unsigned int size = sizeof(dma_chan); 1490 1491 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n"); 1492 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN, 1493 SCP_GET, NULL, 0, dma_chan, &size); 1494 1495 if (status < 0) { 1496 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n"); 1497 return status; 1498 } 1499 1500 if ((*dma_chan + 1) == 0) { 1501 codec_dbg(codec, "no free dma channels to allocate\n"); 1502 return -EBUSY; 1503 } 1504 1505 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan); 1506 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n"); 1507 1508 return status; 1509 } 1510 1511 /* 1512 * Free a DSP DMA via an SCP message 1513 */ 1514 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan) 1515 { 1516 int status = 0; 1517 unsigned int dummy = 0; 1518 1519 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n"); 1520 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan); 1521 1522 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN, 1523 SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy); 1524 1525 if (status < 0) { 1526 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n"); 1527 return status; 1528 } 1529 1530 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n"); 1531 1532 return status; 1533 } 1534 1535 /* 1536 * (Re)start the DSP 1537 */ 1538 static int dsp_set_run_state(struct hda_codec *codec) 1539 { 1540 unsigned int dbg_ctrl_reg; 1541 unsigned int halt_state; 1542 int err; 1543 1544 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg); 1545 if (err < 0) 1546 return err; 1547 1548 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >> 1549 DSP_DBGCNTL_STATE_LOBIT; 1550 1551 if (halt_state != 0) { 1552 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) & 1553 DSP_DBGCNTL_SS_MASK); 1554 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 1555 dbg_ctrl_reg); 1556 if (err < 0) 1557 return err; 1558 1559 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) & 1560 DSP_DBGCNTL_EXEC_MASK; 1561 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 1562 dbg_ctrl_reg); 1563 if (err < 0) 1564 return err; 1565 } 1566 1567 return 0; 1568 } 1569 1570 /* 1571 * Reset the DSP 1572 */ 1573 static int dsp_reset(struct hda_codec *codec) 1574 { 1575 unsigned int res; 1576 int retry = 20; 1577 1578 codec_dbg(codec, "dsp_reset\n"); 1579 do { 1580 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0); 1581 retry--; 1582 } while (res == -EIO && retry); 1583 1584 if (!retry) { 1585 codec_dbg(codec, "dsp_reset timeout\n"); 1586 return -EIO; 1587 } 1588 1589 return 0; 1590 } 1591 1592 /* 1593 * Convert chip address to DSP address 1594 */ 1595 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx, 1596 bool *code, bool *yram) 1597 { 1598 *code = *yram = false; 1599 1600 if (UC_RANGE(chip_addx, 1)) { 1601 *code = true; 1602 return UC_OFF(chip_addx); 1603 } else if (X_RANGE_ALL(chip_addx, 1)) { 1604 return X_OFF(chip_addx); 1605 } else if (Y_RANGE_ALL(chip_addx, 1)) { 1606 *yram = true; 1607 return Y_OFF(chip_addx); 1608 } 1609 1610 return INVALID_CHIP_ADDRESS; 1611 } 1612 1613 /* 1614 * Check if the DSP DMA is active 1615 */ 1616 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan) 1617 { 1618 unsigned int dma_chnlstart_reg; 1619 1620 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg); 1621 1622 return ((dma_chnlstart_reg & (1 << 1623 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0); 1624 } 1625 1626 static int dsp_dma_setup_common(struct hda_codec *codec, 1627 unsigned int chip_addx, 1628 unsigned int dma_chan, 1629 unsigned int port_map_mask, 1630 bool ovly) 1631 { 1632 int status = 0; 1633 unsigned int chnl_prop; 1634 unsigned int dsp_addx; 1635 unsigned int active; 1636 bool code, yram; 1637 1638 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n"); 1639 1640 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) { 1641 codec_dbg(codec, "dma chan num invalid\n"); 1642 return -EINVAL; 1643 } 1644 1645 if (dsp_is_dma_active(codec, dma_chan)) { 1646 codec_dbg(codec, "dma already active\n"); 1647 return -EBUSY; 1648 } 1649 1650 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 1651 1652 if (dsp_addx == INVALID_CHIP_ADDRESS) { 1653 codec_dbg(codec, "invalid chip addr\n"); 1654 return -ENXIO; 1655 } 1656 1657 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK; 1658 active = 0; 1659 1660 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n"); 1661 1662 if (ovly) { 1663 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET, 1664 &chnl_prop); 1665 1666 if (status < 0) { 1667 codec_dbg(codec, "read CHNLPROP Reg fail\n"); 1668 return status; 1669 } 1670 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n"); 1671 } 1672 1673 if (!code) 1674 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 1675 else 1676 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 1677 1678 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan)); 1679 1680 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop); 1681 if (status < 0) { 1682 codec_dbg(codec, "write CHNLPROP Reg fail\n"); 1683 return status; 1684 } 1685 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n"); 1686 1687 if (ovly) { 1688 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET, 1689 &active); 1690 1691 if (status < 0) { 1692 codec_dbg(codec, "read ACTIVE Reg fail\n"); 1693 return status; 1694 } 1695 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n"); 1696 } 1697 1698 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) & 1699 DSPDMAC_ACTIVE_AAR_MASK; 1700 1701 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active); 1702 if (status < 0) { 1703 codec_dbg(codec, "write ACTIVE Reg fail\n"); 1704 return status; 1705 } 1706 1707 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n"); 1708 1709 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan), 1710 port_map_mask); 1711 if (status < 0) { 1712 codec_dbg(codec, "write AUDCHSEL Reg fail\n"); 1713 return status; 1714 } 1715 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n"); 1716 1717 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan), 1718 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK); 1719 if (status < 0) { 1720 codec_dbg(codec, "write IRQCNT Reg fail\n"); 1721 return status; 1722 } 1723 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n"); 1724 1725 codec_dbg(codec, 1726 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, " 1727 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n", 1728 chip_addx, dsp_addx, dma_chan, 1729 port_map_mask, chnl_prop, active); 1730 1731 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n"); 1732 1733 return 0; 1734 } 1735 1736 /* 1737 * Setup the DSP DMA per-transfer-specific registers 1738 */ 1739 static int dsp_dma_setup(struct hda_codec *codec, 1740 unsigned int chip_addx, 1741 unsigned int count, 1742 unsigned int dma_chan) 1743 { 1744 int status = 0; 1745 bool code, yram; 1746 unsigned int dsp_addx; 1747 unsigned int addr_field; 1748 unsigned int incr_field; 1749 unsigned int base_cnt; 1750 unsigned int cur_cnt; 1751 unsigned int dma_cfg = 0; 1752 unsigned int adr_ofs = 0; 1753 unsigned int xfr_cnt = 0; 1754 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT - 1755 DSPDMAC_XFRCNT_BCNT_LOBIT + 1); 1756 1757 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n"); 1758 1759 if (count > max_dma_count) { 1760 codec_dbg(codec, "count too big\n"); 1761 return -EINVAL; 1762 } 1763 1764 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 1765 if (dsp_addx == INVALID_CHIP_ADDRESS) { 1766 codec_dbg(codec, "invalid chip addr\n"); 1767 return -ENXIO; 1768 } 1769 1770 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n"); 1771 1772 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT; 1773 incr_field = 0; 1774 1775 if (!code) { 1776 addr_field <<= 1; 1777 if (yram) 1778 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT); 1779 1780 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT); 1781 } 1782 1783 dma_cfg = addr_field + incr_field; 1784 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan), 1785 dma_cfg); 1786 if (status < 0) { 1787 codec_dbg(codec, "write DMACFG Reg fail\n"); 1788 return status; 1789 } 1790 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n"); 1791 1792 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT + 1793 (code ? 0 : 1)); 1794 1795 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan), 1796 adr_ofs); 1797 if (status < 0) { 1798 codec_dbg(codec, "write DSPADROFS Reg fail\n"); 1799 return status; 1800 } 1801 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n"); 1802 1803 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT; 1804 1805 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT; 1806 1807 xfr_cnt = base_cnt | cur_cnt; 1808 1809 status = chipio_write(codec, 1810 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt); 1811 if (status < 0) { 1812 codec_dbg(codec, "write XFRCNT Reg fail\n"); 1813 return status; 1814 } 1815 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n"); 1816 1817 codec_dbg(codec, 1818 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, " 1819 "ADROFS=0x%x, XFRCNT=0x%x\n", 1820 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt); 1821 1822 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n"); 1823 1824 return 0; 1825 } 1826 1827 /* 1828 * Start the DSP DMA 1829 */ 1830 static int dsp_dma_start(struct hda_codec *codec, 1831 unsigned int dma_chan, bool ovly) 1832 { 1833 unsigned int reg = 0; 1834 int status = 0; 1835 1836 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n"); 1837 1838 if (ovly) { 1839 status = chipio_read(codec, 1840 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 1841 1842 if (status < 0) { 1843 codec_dbg(codec, "read CHNLSTART reg fail\n"); 1844 return status; 1845 } 1846 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n"); 1847 1848 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 1849 DSPDMAC_CHNLSTART_DIS_MASK); 1850 } 1851 1852 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 1853 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT))); 1854 if (status < 0) { 1855 codec_dbg(codec, "write CHNLSTART reg fail\n"); 1856 return status; 1857 } 1858 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n"); 1859 1860 return status; 1861 } 1862 1863 /* 1864 * Stop the DSP DMA 1865 */ 1866 static int dsp_dma_stop(struct hda_codec *codec, 1867 unsigned int dma_chan, bool ovly) 1868 { 1869 unsigned int reg = 0; 1870 int status = 0; 1871 1872 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n"); 1873 1874 if (ovly) { 1875 status = chipio_read(codec, 1876 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 1877 1878 if (status < 0) { 1879 codec_dbg(codec, "read CHNLSTART reg fail\n"); 1880 return status; 1881 } 1882 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n"); 1883 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 1884 DSPDMAC_CHNLSTART_DIS_MASK); 1885 } 1886 1887 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 1888 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT))); 1889 if (status < 0) { 1890 codec_dbg(codec, "write CHNLSTART reg fail\n"); 1891 return status; 1892 } 1893 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n"); 1894 1895 return status; 1896 } 1897 1898 /** 1899 * Allocate router ports 1900 * 1901 * @codec: the HDA codec 1902 * @num_chans: number of channels in the stream 1903 * @ports_per_channel: number of ports per channel 1904 * @start_device: start device 1905 * @port_map: pointer to the port list to hold the allocated ports 1906 * 1907 * Returns zero or a negative error code. 1908 */ 1909 static int dsp_allocate_router_ports(struct hda_codec *codec, 1910 unsigned int num_chans, 1911 unsigned int ports_per_channel, 1912 unsigned int start_device, 1913 unsigned int *port_map) 1914 { 1915 int status = 0; 1916 int res; 1917 u8 val; 1918 1919 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 1920 if (status < 0) 1921 return status; 1922 1923 val = start_device << 6; 1924 val |= (ports_per_channel - 1) << 4; 1925 val |= num_chans - 1; 1926 1927 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1928 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET, 1929 val); 1930 1931 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1932 VENDOR_CHIPIO_PORT_ALLOC_SET, 1933 MEM_CONNID_DSP); 1934 1935 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 1936 if (status < 0) 1937 return status; 1938 1939 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1940 VENDOR_CHIPIO_PORT_ALLOC_GET, 0); 1941 1942 *port_map = res; 1943 1944 return (res < 0) ? res : 0; 1945 } 1946 1947 /* 1948 * Free router ports 1949 */ 1950 static int dsp_free_router_ports(struct hda_codec *codec) 1951 { 1952 int status = 0; 1953 1954 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 1955 if (status < 0) 1956 return status; 1957 1958 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1959 VENDOR_CHIPIO_PORT_FREE_SET, 1960 MEM_CONNID_DSP); 1961 1962 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 1963 1964 return status; 1965 } 1966 1967 /* 1968 * Allocate DSP ports for the download stream 1969 */ 1970 static int dsp_allocate_ports(struct hda_codec *codec, 1971 unsigned int num_chans, 1972 unsigned int rate_multi, unsigned int *port_map) 1973 { 1974 int status; 1975 1976 codec_dbg(codec, " dsp_allocate_ports() -- begin\n"); 1977 1978 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 1979 codec_dbg(codec, "bad rate multiple\n"); 1980 return -EINVAL; 1981 } 1982 1983 status = dsp_allocate_router_ports(codec, num_chans, 1984 rate_multi, 0, port_map); 1985 1986 codec_dbg(codec, " dsp_allocate_ports() -- complete\n"); 1987 1988 return status; 1989 } 1990 1991 static int dsp_allocate_ports_format(struct hda_codec *codec, 1992 const unsigned short fmt, 1993 unsigned int *port_map) 1994 { 1995 int status; 1996 unsigned int num_chans; 1997 1998 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1; 1999 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1; 2000 unsigned int rate_multi = sample_rate_mul / sample_rate_div; 2001 2002 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2003 codec_dbg(codec, "bad rate multiple\n"); 2004 return -EINVAL; 2005 } 2006 2007 num_chans = get_hdafmt_chs(fmt) + 1; 2008 2009 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map); 2010 2011 return status; 2012 } 2013 2014 /* 2015 * free DSP ports 2016 */ 2017 static int dsp_free_ports(struct hda_codec *codec) 2018 { 2019 int status; 2020 2021 codec_dbg(codec, " dsp_free_ports() -- begin\n"); 2022 2023 status = dsp_free_router_ports(codec); 2024 if (status < 0) { 2025 codec_dbg(codec, "free router ports fail\n"); 2026 return status; 2027 } 2028 codec_dbg(codec, " dsp_free_ports() -- complete\n"); 2029 2030 return status; 2031 } 2032 2033 /* 2034 * HDA DMA engine stuffs for DSP code download 2035 */ 2036 struct dma_engine { 2037 struct hda_codec *codec; 2038 unsigned short m_converter_format; 2039 struct snd_dma_buffer *dmab; 2040 unsigned int buf_size; 2041 }; 2042 2043 2044 enum dma_state { 2045 DMA_STATE_STOP = 0, 2046 DMA_STATE_RUN = 1 2047 }; 2048 2049 static int dma_convert_to_hda_format(struct hda_codec *codec, 2050 unsigned int sample_rate, 2051 unsigned short channels, 2052 unsigned short *hda_format) 2053 { 2054 unsigned int format_val; 2055 2056 format_val = snd_hda_calc_stream_format(codec, 2057 sample_rate, 2058 channels, 2059 SNDRV_PCM_FORMAT_S32_LE, 2060 32, 0); 2061 2062 if (hda_format) 2063 *hda_format = (unsigned short)format_val; 2064 2065 return 0; 2066 } 2067 2068 /* 2069 * Reset DMA for DSP download 2070 */ 2071 static int dma_reset(struct dma_engine *dma) 2072 { 2073 struct hda_codec *codec = dma->codec; 2074 struct ca0132_spec *spec = codec->spec; 2075 int status; 2076 2077 if (dma->dmab->area) 2078 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab); 2079 2080 status = snd_hda_codec_load_dsp_prepare(codec, 2081 dma->m_converter_format, 2082 dma->buf_size, 2083 dma->dmab); 2084 if (status < 0) 2085 return status; 2086 spec->dsp_stream_id = status; 2087 return 0; 2088 } 2089 2090 static int dma_set_state(struct dma_engine *dma, enum dma_state state) 2091 { 2092 bool cmd; 2093 2094 switch (state) { 2095 case DMA_STATE_STOP: 2096 cmd = false; 2097 break; 2098 case DMA_STATE_RUN: 2099 cmd = true; 2100 break; 2101 default: 2102 return 0; 2103 } 2104 2105 snd_hda_codec_load_dsp_trigger(dma->codec, cmd); 2106 return 0; 2107 } 2108 2109 static unsigned int dma_get_buffer_size(struct dma_engine *dma) 2110 { 2111 return dma->dmab->bytes; 2112 } 2113 2114 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma) 2115 { 2116 return dma->dmab->area; 2117 } 2118 2119 static int dma_xfer(struct dma_engine *dma, 2120 const unsigned int *data, 2121 unsigned int count) 2122 { 2123 memcpy(dma->dmab->area, data, count); 2124 return 0; 2125 } 2126 2127 static void dma_get_converter_format( 2128 struct dma_engine *dma, 2129 unsigned short *format) 2130 { 2131 if (format) 2132 *format = dma->m_converter_format; 2133 } 2134 2135 static unsigned int dma_get_stream_id(struct dma_engine *dma) 2136 { 2137 struct ca0132_spec *spec = dma->codec->spec; 2138 2139 return spec->dsp_stream_id; 2140 } 2141 2142 struct dsp_image_seg { 2143 u32 magic; 2144 u32 chip_addr; 2145 u32 count; 2146 u32 data[0]; 2147 }; 2148 2149 static const u32 g_magic_value = 0x4c46584d; 2150 static const u32 g_chip_addr_magic_value = 0xFFFFFF01; 2151 2152 static bool is_valid(const struct dsp_image_seg *p) 2153 { 2154 return p->magic == g_magic_value; 2155 } 2156 2157 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p) 2158 { 2159 return g_chip_addr_magic_value == p->chip_addr; 2160 } 2161 2162 static bool is_last(const struct dsp_image_seg *p) 2163 { 2164 return p->count == 0; 2165 } 2166 2167 static size_t dsp_sizeof(const struct dsp_image_seg *p) 2168 { 2169 return sizeof(*p) + p->count*sizeof(u32); 2170 } 2171 2172 static const struct dsp_image_seg *get_next_seg_ptr( 2173 const struct dsp_image_seg *p) 2174 { 2175 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p)); 2176 } 2177 2178 /* 2179 * CA0132 chip DSP transfer stuffs. For DSP download. 2180 */ 2181 #define INVALID_DMA_CHANNEL (~0U) 2182 2183 /* 2184 * Program a list of address/data pairs via the ChipIO widget. 2185 * The segment data is in the format of successive pairs of words. 2186 * These are repeated as indicated by the segment's count field. 2187 */ 2188 static int dspxfr_hci_write(struct hda_codec *codec, 2189 const struct dsp_image_seg *fls) 2190 { 2191 int status; 2192 const u32 *data; 2193 unsigned int count; 2194 2195 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) { 2196 codec_dbg(codec, "hci_write invalid params\n"); 2197 return -EINVAL; 2198 } 2199 2200 count = fls->count; 2201 data = (u32 *)(fls->data); 2202 while (count >= 2) { 2203 status = chipio_write(codec, data[0], data[1]); 2204 if (status < 0) { 2205 codec_dbg(codec, "hci_write chipio failed\n"); 2206 return status; 2207 } 2208 count -= 2; 2209 data += 2; 2210 } 2211 return 0; 2212 } 2213 2214 /** 2215 * Write a block of data into DSP code or data RAM using pre-allocated 2216 * DMA engine. 2217 * 2218 * @codec: the HDA codec 2219 * @fls: pointer to a fast load image 2220 * @reloc: Relocation address for loading single-segment overlays, or 0 for 2221 * no relocation 2222 * @dma_engine: pointer to DMA engine to be used for DSP download 2223 * @dma_chan: The number of DMA channels used for DSP download 2224 * @port_map_mask: port mapping 2225 * @ovly: TRUE if overlay format is required 2226 * 2227 * Returns zero or a negative error code. 2228 */ 2229 static int dspxfr_one_seg(struct hda_codec *codec, 2230 const struct dsp_image_seg *fls, 2231 unsigned int reloc, 2232 struct dma_engine *dma_engine, 2233 unsigned int dma_chan, 2234 unsigned int port_map_mask, 2235 bool ovly) 2236 { 2237 int status = 0; 2238 bool comm_dma_setup_done = false; 2239 const unsigned int *data; 2240 unsigned int chip_addx; 2241 unsigned int words_to_write; 2242 unsigned int buffer_size_words; 2243 unsigned char *buffer_addx; 2244 unsigned short hda_format; 2245 unsigned int sample_rate_div; 2246 unsigned int sample_rate_mul; 2247 unsigned int num_chans; 2248 unsigned int hda_frame_size_words; 2249 unsigned int remainder_words; 2250 const u32 *data_remainder; 2251 u32 chip_addx_remainder; 2252 unsigned int run_size_words; 2253 const struct dsp_image_seg *hci_write = NULL; 2254 unsigned long timeout; 2255 bool dma_active; 2256 2257 if (fls == NULL) 2258 return -EINVAL; 2259 if (is_hci_prog_list_seg(fls)) { 2260 hci_write = fls; 2261 fls = get_next_seg_ptr(fls); 2262 } 2263 2264 if (hci_write && (!fls || is_last(fls))) { 2265 codec_dbg(codec, "hci_write\n"); 2266 return dspxfr_hci_write(codec, hci_write); 2267 } 2268 2269 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) { 2270 codec_dbg(codec, "Invalid Params\n"); 2271 return -EINVAL; 2272 } 2273 2274 data = fls->data; 2275 chip_addx = fls->chip_addr, 2276 words_to_write = fls->count; 2277 2278 if (!words_to_write) 2279 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0; 2280 if (reloc) 2281 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2); 2282 2283 if (!UC_RANGE(chip_addx, words_to_write) && 2284 !X_RANGE_ALL(chip_addx, words_to_write) && 2285 !Y_RANGE_ALL(chip_addx, words_to_write)) { 2286 codec_dbg(codec, "Invalid chip_addx Params\n"); 2287 return -EINVAL; 2288 } 2289 2290 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) / 2291 sizeof(u32); 2292 2293 buffer_addx = dma_get_buffer_addr(dma_engine); 2294 2295 if (buffer_addx == NULL) { 2296 codec_dbg(codec, "dma_engine buffer NULL\n"); 2297 return -EINVAL; 2298 } 2299 2300 dma_get_converter_format(dma_engine, &hda_format); 2301 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1; 2302 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1; 2303 num_chans = get_hdafmt_chs(hda_format) + 1; 2304 2305 hda_frame_size_words = ((sample_rate_div == 0) ? 0 : 2306 (num_chans * sample_rate_mul / sample_rate_div)); 2307 2308 if (hda_frame_size_words == 0) { 2309 codec_dbg(codec, "frmsz zero\n"); 2310 return -EINVAL; 2311 } 2312 2313 buffer_size_words = min(buffer_size_words, 2314 (unsigned int)(UC_RANGE(chip_addx, 1) ? 2315 65536 : 32768)); 2316 buffer_size_words -= buffer_size_words % hda_frame_size_words; 2317 codec_dbg(codec, 2318 "chpadr=0x%08x frmsz=%u nchan=%u " 2319 "rate_mul=%u div=%u bufsz=%u\n", 2320 chip_addx, hda_frame_size_words, num_chans, 2321 sample_rate_mul, sample_rate_div, buffer_size_words); 2322 2323 if (buffer_size_words < hda_frame_size_words) { 2324 codec_dbg(codec, "dspxfr_one_seg:failed\n"); 2325 return -EINVAL; 2326 } 2327 2328 remainder_words = words_to_write % hda_frame_size_words; 2329 data_remainder = data; 2330 chip_addx_remainder = chip_addx; 2331 2332 data += remainder_words; 2333 chip_addx += remainder_words*sizeof(u32); 2334 words_to_write -= remainder_words; 2335 2336 while (words_to_write != 0) { 2337 run_size_words = min(buffer_size_words, words_to_write); 2338 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n", 2339 words_to_write, run_size_words, remainder_words); 2340 dma_xfer(dma_engine, data, run_size_words*sizeof(u32)); 2341 if (!comm_dma_setup_done) { 2342 status = dsp_dma_stop(codec, dma_chan, ovly); 2343 if (status < 0) 2344 return status; 2345 status = dsp_dma_setup_common(codec, chip_addx, 2346 dma_chan, port_map_mask, ovly); 2347 if (status < 0) 2348 return status; 2349 comm_dma_setup_done = true; 2350 } 2351 2352 status = dsp_dma_setup(codec, chip_addx, 2353 run_size_words, dma_chan); 2354 if (status < 0) 2355 return status; 2356 status = dsp_dma_start(codec, dma_chan, ovly); 2357 if (status < 0) 2358 return status; 2359 if (!dsp_is_dma_active(codec, dma_chan)) { 2360 codec_dbg(codec, "dspxfr:DMA did not start\n"); 2361 return -EIO; 2362 } 2363 status = dma_set_state(dma_engine, DMA_STATE_RUN); 2364 if (status < 0) 2365 return status; 2366 if (remainder_words != 0) { 2367 status = chipio_write_multiple(codec, 2368 chip_addx_remainder, 2369 data_remainder, 2370 remainder_words); 2371 if (status < 0) 2372 return status; 2373 remainder_words = 0; 2374 } 2375 if (hci_write) { 2376 status = dspxfr_hci_write(codec, hci_write); 2377 if (status < 0) 2378 return status; 2379 hci_write = NULL; 2380 } 2381 2382 timeout = jiffies + msecs_to_jiffies(2000); 2383 do { 2384 dma_active = dsp_is_dma_active(codec, dma_chan); 2385 if (!dma_active) 2386 break; 2387 msleep(20); 2388 } while (time_before(jiffies, timeout)); 2389 if (dma_active) 2390 break; 2391 2392 codec_dbg(codec, "+++++ DMA complete\n"); 2393 dma_set_state(dma_engine, DMA_STATE_STOP); 2394 status = dma_reset(dma_engine); 2395 2396 if (status < 0) 2397 return status; 2398 2399 data += run_size_words; 2400 chip_addx += run_size_words*sizeof(u32); 2401 words_to_write -= run_size_words; 2402 } 2403 2404 if (remainder_words != 0) { 2405 status = chipio_write_multiple(codec, chip_addx_remainder, 2406 data_remainder, remainder_words); 2407 } 2408 2409 return status; 2410 } 2411 2412 /** 2413 * Write the entire DSP image of a DSP code/data overlay to DSP memories 2414 * 2415 * @codec: the HDA codec 2416 * @fls_data: pointer to a fast load image 2417 * @reloc: Relocation address for loading single-segment overlays, or 0 for 2418 * no relocation 2419 * @sample_rate: sampling rate of the stream used for DSP download 2420 * @channels: channels of the stream used for DSP download 2421 * @ovly: TRUE if overlay format is required 2422 * 2423 * Returns zero or a negative error code. 2424 */ 2425 static int dspxfr_image(struct hda_codec *codec, 2426 const struct dsp_image_seg *fls_data, 2427 unsigned int reloc, 2428 unsigned int sample_rate, 2429 unsigned short channels, 2430 bool ovly) 2431 { 2432 struct ca0132_spec *spec = codec->spec; 2433 int status; 2434 unsigned short hda_format = 0; 2435 unsigned int response; 2436 unsigned char stream_id = 0; 2437 struct dma_engine *dma_engine; 2438 unsigned int dma_chan; 2439 unsigned int port_map_mask; 2440 2441 if (fls_data == NULL) 2442 return -EINVAL; 2443 2444 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL); 2445 if (!dma_engine) 2446 return -ENOMEM; 2447 2448 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL); 2449 if (!dma_engine->dmab) { 2450 kfree(dma_engine); 2451 return -ENOMEM; 2452 } 2453 2454 dma_engine->codec = codec; 2455 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format); 2456 dma_engine->m_converter_format = hda_format; 2457 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY : 2458 DSP_DMA_WRITE_BUFLEN_INIT) * 2; 2459 2460 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0; 2461 2462 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL, 2463 hda_format, &response); 2464 2465 if (status < 0) { 2466 codec_dbg(codec, "set converter format fail\n"); 2467 goto exit; 2468 } 2469 2470 status = snd_hda_codec_load_dsp_prepare(codec, 2471 dma_engine->m_converter_format, 2472 dma_engine->buf_size, 2473 dma_engine->dmab); 2474 if (status < 0) 2475 goto exit; 2476 spec->dsp_stream_id = status; 2477 2478 if (ovly) { 2479 status = dspio_alloc_dma_chan(codec, &dma_chan); 2480 if (status < 0) { 2481 codec_dbg(codec, "alloc dmachan fail\n"); 2482 dma_chan = INVALID_DMA_CHANNEL; 2483 goto exit; 2484 } 2485 } 2486 2487 port_map_mask = 0; 2488 status = dsp_allocate_ports_format(codec, hda_format, 2489 &port_map_mask); 2490 if (status < 0) { 2491 codec_dbg(codec, "alloc ports fail\n"); 2492 goto exit; 2493 } 2494 2495 stream_id = dma_get_stream_id(dma_engine); 2496 status = codec_set_converter_stream_channel(codec, 2497 WIDGET_CHIP_CTRL, stream_id, 0, &response); 2498 if (status < 0) { 2499 codec_dbg(codec, "set stream chan fail\n"); 2500 goto exit; 2501 } 2502 2503 while ((fls_data != NULL) && !is_last(fls_data)) { 2504 if (!is_valid(fls_data)) { 2505 codec_dbg(codec, "FLS check fail\n"); 2506 status = -EINVAL; 2507 goto exit; 2508 } 2509 status = dspxfr_one_seg(codec, fls_data, reloc, 2510 dma_engine, dma_chan, 2511 port_map_mask, ovly); 2512 if (status < 0) 2513 break; 2514 2515 if (is_hci_prog_list_seg(fls_data)) 2516 fls_data = get_next_seg_ptr(fls_data); 2517 2518 if ((fls_data != NULL) && !is_last(fls_data)) 2519 fls_data = get_next_seg_ptr(fls_data); 2520 } 2521 2522 if (port_map_mask != 0) 2523 status = dsp_free_ports(codec); 2524 2525 if (status < 0) 2526 goto exit; 2527 2528 status = codec_set_converter_stream_channel(codec, 2529 WIDGET_CHIP_CTRL, 0, 0, &response); 2530 2531 exit: 2532 if (ovly && (dma_chan != INVALID_DMA_CHANNEL)) 2533 dspio_free_dma_chan(codec, dma_chan); 2534 2535 if (dma_engine->dmab->area) 2536 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab); 2537 kfree(dma_engine->dmab); 2538 kfree(dma_engine); 2539 2540 return status; 2541 } 2542 2543 /* 2544 * CA0132 DSP download stuffs. 2545 */ 2546 static void dspload_post_setup(struct hda_codec *codec) 2547 { 2548 codec_dbg(codec, "---- dspload_post_setup ------\n"); 2549 2550 /*set DSP speaker to 2.0 configuration*/ 2551 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080); 2552 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000); 2553 2554 /*update write pointer*/ 2555 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002); 2556 } 2557 2558 /** 2559 * dspload_image - Download DSP from a DSP Image Fast Load structure. 2560 * 2561 * @codec: the HDA codec 2562 * @fls: pointer to a fast load image 2563 * @ovly: TRUE if overlay format is required 2564 * @reloc: Relocation address for loading single-segment overlays, or 0 for 2565 * no relocation 2566 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE 2567 * @router_chans: number of audio router channels to be allocated (0 means use 2568 * internal defaults; max is 32) 2569 * 2570 * Download DSP from a DSP Image Fast Load structure. This structure is a 2571 * linear, non-constant sized element array of structures, each of which 2572 * contain the count of the data to be loaded, the data itself, and the 2573 * corresponding starting chip address of the starting data location. 2574 * Returns zero or a negative error code. 2575 */ 2576 static int dspload_image(struct hda_codec *codec, 2577 const struct dsp_image_seg *fls, 2578 bool ovly, 2579 unsigned int reloc, 2580 bool autostart, 2581 int router_chans) 2582 { 2583 int status = 0; 2584 unsigned int sample_rate; 2585 unsigned short channels; 2586 2587 codec_dbg(codec, "---- dspload_image begin ------\n"); 2588 if (router_chans == 0) { 2589 if (!ovly) 2590 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS; 2591 else 2592 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS; 2593 } 2594 2595 sample_rate = 48000; 2596 channels = (unsigned short)router_chans; 2597 2598 while (channels > 16) { 2599 sample_rate *= 2; 2600 channels /= 2; 2601 } 2602 2603 do { 2604 codec_dbg(codec, "Ready to program DMA\n"); 2605 if (!ovly) 2606 status = dsp_reset(codec); 2607 2608 if (status < 0) 2609 break; 2610 2611 codec_dbg(codec, "dsp_reset() complete\n"); 2612 status = dspxfr_image(codec, fls, reloc, sample_rate, channels, 2613 ovly); 2614 2615 if (status < 0) 2616 break; 2617 2618 codec_dbg(codec, "dspxfr_image() complete\n"); 2619 if (autostart && !ovly) { 2620 dspload_post_setup(codec); 2621 status = dsp_set_run_state(codec); 2622 } 2623 2624 codec_dbg(codec, "LOAD FINISHED\n"); 2625 } while (0); 2626 2627 return status; 2628 } 2629 2630 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 2631 static bool dspload_is_loaded(struct hda_codec *codec) 2632 { 2633 unsigned int data = 0; 2634 int status = 0; 2635 2636 status = chipio_read(codec, 0x40004, &data); 2637 if ((status < 0) || (data != 1)) 2638 return false; 2639 2640 return true; 2641 } 2642 #else 2643 #define dspload_is_loaded(codec) false 2644 #endif 2645 2646 static bool dspload_wait_loaded(struct hda_codec *codec) 2647 { 2648 unsigned long timeout = jiffies + msecs_to_jiffies(2000); 2649 2650 do { 2651 if (dspload_is_loaded(codec)) { 2652 pr_info("ca0132 DOWNLOAD OK :-) DSP IS RUNNING.\n"); 2653 return true; 2654 } 2655 msleep(20); 2656 } while (time_before(jiffies, timeout)); 2657 2658 pr_err("ca0132 DOWNLOAD FAILED!!! DSP IS NOT RUNNING.\n"); 2659 return false; 2660 } 2661 2662 /* 2663 * PCM callbacks 2664 */ 2665 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 2666 struct hda_codec *codec, 2667 unsigned int stream_tag, 2668 unsigned int format, 2669 struct snd_pcm_substream *substream) 2670 { 2671 struct ca0132_spec *spec = codec->spec; 2672 2673 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format); 2674 2675 return 0; 2676 } 2677 2678 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 2679 struct hda_codec *codec, 2680 struct snd_pcm_substream *substream) 2681 { 2682 struct ca0132_spec *spec = codec->spec; 2683 2684 if (spec->dsp_state == DSP_DOWNLOADING) 2685 return 0; 2686 2687 /*If Playback effects are on, allow stream some time to flush 2688 *effects tail*/ 2689 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 2690 msleep(50); 2691 2692 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 2693 2694 return 0; 2695 } 2696 2697 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info, 2698 struct hda_codec *codec, 2699 struct snd_pcm_substream *substream) 2700 { 2701 struct ca0132_spec *spec = codec->spec; 2702 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY; 2703 struct snd_pcm_runtime *runtime = substream->runtime; 2704 2705 if (spec->dsp_state != DSP_DOWNLOADED) 2706 return 0; 2707 2708 /* Add latency if playback enhancement and either effect is enabled. */ 2709 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) { 2710 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) || 2711 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID])) 2712 latency += DSP_PLAY_ENHANCEMENT_LATENCY; 2713 } 2714 2715 /* Applying Speaker EQ adds latency as well. */ 2716 if (spec->cur_out_type == SPEAKER_OUT) 2717 latency += DSP_SPEAKER_OUT_LATENCY; 2718 2719 return (latency * runtime->rate) / 1000; 2720 } 2721 2722 /* 2723 * Digital out 2724 */ 2725 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo, 2726 struct hda_codec *codec, 2727 struct snd_pcm_substream *substream) 2728 { 2729 struct ca0132_spec *spec = codec->spec; 2730 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 2731 } 2732 2733 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 2734 struct hda_codec *codec, 2735 unsigned int stream_tag, 2736 unsigned int format, 2737 struct snd_pcm_substream *substream) 2738 { 2739 struct ca0132_spec *spec = codec->spec; 2740 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 2741 stream_tag, format, substream); 2742 } 2743 2744 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 2745 struct hda_codec *codec, 2746 struct snd_pcm_substream *substream) 2747 { 2748 struct ca0132_spec *spec = codec->spec; 2749 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout); 2750 } 2751 2752 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo, 2753 struct hda_codec *codec, 2754 struct snd_pcm_substream *substream) 2755 { 2756 struct ca0132_spec *spec = codec->spec; 2757 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 2758 } 2759 2760 /* 2761 * Analog capture 2762 */ 2763 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo, 2764 struct hda_codec *codec, 2765 unsigned int stream_tag, 2766 unsigned int format, 2767 struct snd_pcm_substream *substream) 2768 { 2769 snd_hda_codec_setup_stream(codec, hinfo->nid, 2770 stream_tag, 0, format); 2771 2772 return 0; 2773 } 2774 2775 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo, 2776 struct hda_codec *codec, 2777 struct snd_pcm_substream *substream) 2778 { 2779 struct ca0132_spec *spec = codec->spec; 2780 2781 if (spec->dsp_state == DSP_DOWNLOADING) 2782 return 0; 2783 2784 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 2785 return 0; 2786 } 2787 2788 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info, 2789 struct hda_codec *codec, 2790 struct snd_pcm_substream *substream) 2791 { 2792 struct ca0132_spec *spec = codec->spec; 2793 unsigned int latency = DSP_CAPTURE_INIT_LATENCY; 2794 struct snd_pcm_runtime *runtime = substream->runtime; 2795 2796 if (spec->dsp_state != DSP_DOWNLOADED) 2797 return 0; 2798 2799 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 2800 latency += DSP_CRYSTAL_VOICE_LATENCY; 2801 2802 return (latency * runtime->rate) / 1000; 2803 } 2804 2805 /* 2806 * Controls stuffs. 2807 */ 2808 2809 /* 2810 * Mixer controls helpers. 2811 */ 2812 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \ 2813 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2814 .name = xname, \ 2815 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 2816 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 2817 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 2818 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 2819 .info = ca0132_volume_info, \ 2820 .get = ca0132_volume_get, \ 2821 .put = ca0132_volume_put, \ 2822 .tlv = { .c = ca0132_volume_tlv }, \ 2823 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 2824 2825 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \ 2826 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2827 .name = xname, \ 2828 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 2829 .info = snd_hda_mixer_amp_switch_info, \ 2830 .get = ca0132_switch_get, \ 2831 .put = ca0132_switch_put, \ 2832 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 2833 2834 /* stereo */ 2835 #define CA0132_CODEC_VOL(xname, nid, dir) \ 2836 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir) 2837 #define CA0132_CODEC_MUTE(xname, nid, dir) \ 2838 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir) 2839 2840 /* The followings are for tuning of products */ 2841 #ifdef ENABLE_TUNING_CONTROLS 2842 2843 static unsigned int voice_focus_vals_lookup[] = { 2844 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000, 2845 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000, 2846 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000, 2847 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000, 2848 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000, 2849 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000, 2850 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000, 2851 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000, 2852 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000, 2853 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000, 2854 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000, 2855 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000, 2856 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000, 2857 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000, 2858 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000, 2859 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000, 2860 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000, 2861 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000, 2862 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000, 2863 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000, 2864 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000, 2865 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000, 2866 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000, 2867 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000, 2868 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000, 2869 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000, 2870 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000 2871 }; 2872 2873 static unsigned int mic_svm_vals_lookup[] = { 2874 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 2875 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 2876 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 2877 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 2878 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 2879 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 2880 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 2881 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 2882 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 2883 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 2884 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 2885 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 2886 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 2887 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 2888 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 2889 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 2890 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 2891 }; 2892 2893 static unsigned int equalizer_vals_lookup[] = { 2894 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 2895 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 2896 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 2897 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 2898 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 2899 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000, 2900 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000, 2901 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 2902 0x41C00000 2903 }; 2904 2905 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid, 2906 unsigned int *lookup, int idx) 2907 { 2908 int i = 0; 2909 2910 for (i = 0; i < TUNING_CTLS_COUNT; i++) 2911 if (nid == ca0132_tuning_ctls[i].nid) 2912 break; 2913 2914 snd_hda_power_up(codec); 2915 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 2916 ca0132_tuning_ctls[i].req, 2917 &(lookup[idx]), sizeof(unsigned int)); 2918 snd_hda_power_down(codec); 2919 2920 return 1; 2921 } 2922 2923 static int tuning_ctl_get(struct snd_kcontrol *kcontrol, 2924 struct snd_ctl_elem_value *ucontrol) 2925 { 2926 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 2927 struct ca0132_spec *spec = codec->spec; 2928 hda_nid_t nid = get_amp_nid(kcontrol); 2929 long *valp = ucontrol->value.integer.value; 2930 int idx = nid - TUNING_CTL_START_NID; 2931 2932 *valp = spec->cur_ctl_vals[idx]; 2933 return 0; 2934 } 2935 2936 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol, 2937 struct snd_ctl_elem_info *uinfo) 2938 { 2939 int chs = get_amp_channels(kcontrol); 2940 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2941 uinfo->count = chs == 3 ? 2 : 1; 2942 uinfo->value.integer.min = 20; 2943 uinfo->value.integer.max = 180; 2944 uinfo->value.integer.step = 1; 2945 2946 return 0; 2947 } 2948 2949 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol, 2950 struct snd_ctl_elem_value *ucontrol) 2951 { 2952 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 2953 struct ca0132_spec *spec = codec->spec; 2954 hda_nid_t nid = get_amp_nid(kcontrol); 2955 long *valp = ucontrol->value.integer.value; 2956 int idx; 2957 2958 idx = nid - TUNING_CTL_START_NID; 2959 /* any change? */ 2960 if (spec->cur_ctl_vals[idx] == *valp) 2961 return 0; 2962 2963 spec->cur_ctl_vals[idx] = *valp; 2964 2965 idx = *valp - 20; 2966 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx); 2967 2968 return 1; 2969 } 2970 2971 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol, 2972 struct snd_ctl_elem_info *uinfo) 2973 { 2974 int chs = get_amp_channels(kcontrol); 2975 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2976 uinfo->count = chs == 3 ? 2 : 1; 2977 uinfo->value.integer.min = 0; 2978 uinfo->value.integer.max = 100; 2979 uinfo->value.integer.step = 1; 2980 2981 return 0; 2982 } 2983 2984 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol, 2985 struct snd_ctl_elem_value *ucontrol) 2986 { 2987 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 2988 struct ca0132_spec *spec = codec->spec; 2989 hda_nid_t nid = get_amp_nid(kcontrol); 2990 long *valp = ucontrol->value.integer.value; 2991 int idx; 2992 2993 idx = nid - TUNING_CTL_START_NID; 2994 /* any change? */ 2995 if (spec->cur_ctl_vals[idx] == *valp) 2996 return 0; 2997 2998 spec->cur_ctl_vals[idx] = *valp; 2999 3000 idx = *valp; 3001 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx); 3002 3003 return 0; 3004 } 3005 3006 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol, 3007 struct snd_ctl_elem_info *uinfo) 3008 { 3009 int chs = get_amp_channels(kcontrol); 3010 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3011 uinfo->count = chs == 3 ? 2 : 1; 3012 uinfo->value.integer.min = 0; 3013 uinfo->value.integer.max = 48; 3014 uinfo->value.integer.step = 1; 3015 3016 return 0; 3017 } 3018 3019 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol, 3020 struct snd_ctl_elem_value *ucontrol) 3021 { 3022 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3023 struct ca0132_spec *spec = codec->spec; 3024 hda_nid_t nid = get_amp_nid(kcontrol); 3025 long *valp = ucontrol->value.integer.value; 3026 int idx; 3027 3028 idx = nid - TUNING_CTL_START_NID; 3029 /* any change? */ 3030 if (spec->cur_ctl_vals[idx] == *valp) 3031 return 0; 3032 3033 spec->cur_ctl_vals[idx] = *valp; 3034 3035 idx = *valp; 3036 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx); 3037 3038 return 1; 3039 } 3040 3041 static const DECLARE_TLV_DB_SCALE(voice_focus_db_scale, 2000, 100, 0); 3042 static const DECLARE_TLV_DB_SCALE(eq_db_scale, -2400, 100, 0); 3043 3044 static int add_tuning_control(struct hda_codec *codec, 3045 hda_nid_t pnid, hda_nid_t nid, 3046 const char *name, int dir) 3047 { 3048 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 3049 int type = dir ? HDA_INPUT : HDA_OUTPUT; 3050 struct snd_kcontrol_new knew = 3051 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 3052 3053 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 3054 SNDRV_CTL_ELEM_ACCESS_TLV_READ; 3055 knew.tlv.c = 0; 3056 knew.tlv.p = 0; 3057 switch (pnid) { 3058 case VOICE_FOCUS: 3059 knew.info = voice_focus_ctl_info; 3060 knew.get = tuning_ctl_get; 3061 knew.put = voice_focus_ctl_put; 3062 knew.tlv.p = voice_focus_db_scale; 3063 break; 3064 case MIC_SVM: 3065 knew.info = mic_svm_ctl_info; 3066 knew.get = tuning_ctl_get; 3067 knew.put = mic_svm_ctl_put; 3068 break; 3069 case EQUALIZER: 3070 knew.info = equalizer_ctl_info; 3071 knew.get = tuning_ctl_get; 3072 knew.put = equalizer_ctl_put; 3073 knew.tlv.p = eq_db_scale; 3074 break; 3075 default: 3076 return 0; 3077 } 3078 knew.private_value = 3079 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 3080 sprintf(namestr, "%s %s Volume", name, dirstr[dir]); 3081 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 3082 } 3083 3084 static int add_tuning_ctls(struct hda_codec *codec) 3085 { 3086 int i; 3087 int err; 3088 3089 for (i = 0; i < TUNING_CTLS_COUNT; i++) { 3090 err = add_tuning_control(codec, 3091 ca0132_tuning_ctls[i].parent_nid, 3092 ca0132_tuning_ctls[i].nid, 3093 ca0132_tuning_ctls[i].name, 3094 ca0132_tuning_ctls[i].direct); 3095 if (err < 0) 3096 return err; 3097 } 3098 3099 return 0; 3100 } 3101 3102 static void ca0132_init_tuning_defaults(struct hda_codec *codec) 3103 { 3104 struct ca0132_spec *spec = codec->spec; 3105 int i; 3106 3107 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */ 3108 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10; 3109 /* SVM level defaults to 0.74. */ 3110 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74; 3111 3112 /* EQ defaults to 0dB. */ 3113 for (i = 2; i < TUNING_CTLS_COUNT; i++) 3114 spec->cur_ctl_vals[i] = 24; 3115 } 3116 #endif /*ENABLE_TUNING_CONTROLS*/ 3117 3118 /* 3119 * Select the active output. 3120 * If autodetect is enabled, output will be selected based on jack detection. 3121 * If jack inserted, headphone will be selected, else built-in speakers 3122 * If autodetect is disabled, output will be selected based on selection. 3123 */ 3124 static int ca0132_select_out(struct hda_codec *codec) 3125 { 3126 struct ca0132_spec *spec = codec->spec; 3127 unsigned int pin_ctl; 3128 int jack_present; 3129 int auto_jack; 3130 unsigned int tmp; 3131 int err; 3132 3133 codec_dbg(codec, "ca0132_select_out\n"); 3134 3135 snd_hda_power_up(codec); 3136 3137 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 3138 3139 if (auto_jack) 3140 jack_present = snd_hda_jack_detect(codec, spec->out_pins[1]); 3141 else 3142 jack_present = 3143 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID]; 3144 3145 if (jack_present) 3146 spec->cur_out_type = HEADPHONE_OUT; 3147 else 3148 spec->cur_out_type = SPEAKER_OUT; 3149 3150 if (spec->cur_out_type == SPEAKER_OUT) { 3151 codec_dbg(codec, "ca0132_select_out speaker\n"); 3152 /*speaker out config*/ 3153 tmp = FLOAT_ONE; 3154 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 3155 if (err < 0) 3156 goto exit; 3157 /*enable speaker EQ*/ 3158 tmp = FLOAT_ONE; 3159 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 3160 if (err < 0) 3161 goto exit; 3162 3163 /* Setup EAPD */ 3164 snd_hda_codec_write(codec, spec->out_pins[1], 0, 3165 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 3166 snd_hda_codec_write(codec, spec->out_pins[0], 0, 3167 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 3168 snd_hda_codec_write(codec, spec->out_pins[0], 0, 3169 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 3170 snd_hda_codec_write(codec, spec->out_pins[0], 0, 3171 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 3172 3173 /* disable headphone node */ 3174 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 3175 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 3176 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 3177 pin_ctl & ~PIN_HP); 3178 /* enable speaker node */ 3179 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 3180 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 3181 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 3182 pin_ctl | PIN_OUT); 3183 } else { 3184 codec_dbg(codec, "ca0132_select_out hp\n"); 3185 /*headphone out config*/ 3186 tmp = FLOAT_ZERO; 3187 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 3188 if (err < 0) 3189 goto exit; 3190 /*disable speaker EQ*/ 3191 tmp = FLOAT_ZERO; 3192 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 3193 if (err < 0) 3194 goto exit; 3195 3196 /* Setup EAPD */ 3197 snd_hda_codec_write(codec, spec->out_pins[0], 0, 3198 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 3199 snd_hda_codec_write(codec, spec->out_pins[0], 0, 3200 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 3201 snd_hda_codec_write(codec, spec->out_pins[1], 0, 3202 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 3203 snd_hda_codec_write(codec, spec->out_pins[0], 0, 3204 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 3205 3206 /* disable speaker*/ 3207 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 3208 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 3209 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 3210 pin_ctl & ~PIN_HP); 3211 /* enable headphone*/ 3212 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 3213 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 3214 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 3215 pin_ctl | PIN_HP); 3216 } 3217 3218 exit: 3219 snd_hda_power_down(codec); 3220 3221 return err < 0 ? err : 0; 3222 } 3223 3224 static void ca0132_unsol_hp_delayed(struct work_struct *work) 3225 { 3226 struct ca0132_spec *spec = container_of( 3227 to_delayed_work(work), struct ca0132_spec, unsol_hp_work); 3228 struct hda_jack_tbl *jack; 3229 3230 ca0132_select_out(spec->codec); 3231 jack = snd_hda_jack_tbl_get(spec->codec, UNSOL_TAG_HP); 3232 if (jack) { 3233 jack->block_report = 0; 3234 snd_hda_jack_report_sync(spec->codec); 3235 } 3236 } 3237 3238 static void ca0132_set_dmic(struct hda_codec *codec, int enable); 3239 static int ca0132_mic_boost_set(struct hda_codec *codec, long val); 3240 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val); 3241 3242 /* 3243 * Select the active VIP source 3244 */ 3245 static int ca0132_set_vipsource(struct hda_codec *codec, int val) 3246 { 3247 struct ca0132_spec *spec = codec->spec; 3248 unsigned int tmp; 3249 3250 if (spec->dsp_state != DSP_DOWNLOADED) 3251 return 0; 3252 3253 /* if CrystalVoice if off, vipsource should be 0 */ 3254 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 3255 (val == 0)) { 3256 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 3257 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 3258 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 3259 if (spec->cur_mic_type == DIGITAL_MIC) 3260 tmp = FLOAT_TWO; 3261 else 3262 tmp = FLOAT_ONE; 3263 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 3264 tmp = FLOAT_ZERO; 3265 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 3266 } else { 3267 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 3268 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 3269 if (spec->cur_mic_type == DIGITAL_MIC) 3270 tmp = FLOAT_TWO; 3271 else 3272 tmp = FLOAT_ONE; 3273 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 3274 tmp = FLOAT_ONE; 3275 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 3276 msleep(20); 3277 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 3278 } 3279 3280 return 1; 3281 } 3282 3283 /* 3284 * Select the active microphone. 3285 * If autodetect is enabled, mic will be selected based on jack detection. 3286 * If jack inserted, ext.mic will be selected, else built-in mic 3287 * If autodetect is disabled, mic will be selected based on selection. 3288 */ 3289 static int ca0132_select_mic(struct hda_codec *codec) 3290 { 3291 struct ca0132_spec *spec = codec->spec; 3292 int jack_present; 3293 int auto_jack; 3294 3295 codec_dbg(codec, "ca0132_select_mic\n"); 3296 3297 snd_hda_power_up(codec); 3298 3299 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 3300 3301 if (auto_jack) 3302 jack_present = snd_hda_jack_detect(codec, spec->input_pins[0]); 3303 else 3304 jack_present = 3305 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID]; 3306 3307 if (jack_present) 3308 spec->cur_mic_type = LINE_MIC_IN; 3309 else 3310 spec->cur_mic_type = DIGITAL_MIC; 3311 3312 if (spec->cur_mic_type == DIGITAL_MIC) { 3313 /* enable digital Mic */ 3314 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000); 3315 ca0132_set_dmic(codec, 1); 3316 ca0132_mic_boost_set(codec, 0); 3317 /* set voice focus */ 3318 ca0132_effects_set(codec, VOICE_FOCUS, 3319 spec->effects_switch 3320 [VOICE_FOCUS - EFFECT_START_NID]); 3321 } else { 3322 /* disable digital Mic */ 3323 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000); 3324 ca0132_set_dmic(codec, 0); 3325 ca0132_mic_boost_set(codec, spec->cur_mic_boost); 3326 /* disable voice focus */ 3327 ca0132_effects_set(codec, VOICE_FOCUS, 0); 3328 } 3329 3330 snd_hda_power_down(codec); 3331 3332 return 0; 3333 } 3334 3335 /* 3336 * Check if VNODE settings take effect immediately. 3337 */ 3338 static bool ca0132_is_vnode_effective(struct hda_codec *codec, 3339 hda_nid_t vnid, 3340 hda_nid_t *shared_nid) 3341 { 3342 struct ca0132_spec *spec = codec->spec; 3343 hda_nid_t nid; 3344 3345 switch (vnid) { 3346 case VNID_SPK: 3347 nid = spec->shared_out_nid; 3348 break; 3349 case VNID_MIC: 3350 nid = spec->shared_mic_nid; 3351 break; 3352 default: 3353 return false; 3354 } 3355 3356 if (shared_nid) 3357 *shared_nid = nid; 3358 3359 return true; 3360 } 3361 3362 /* 3363 * The following functions are control change helpers. 3364 * They return 0 if no changed. Return 1 if changed. 3365 */ 3366 static int ca0132_voicefx_set(struct hda_codec *codec, int enable) 3367 { 3368 struct ca0132_spec *spec = codec->spec; 3369 unsigned int tmp; 3370 3371 /* based on CrystalVoice state to enable VoiceFX. */ 3372 if (enable) { 3373 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ? 3374 FLOAT_ONE : FLOAT_ZERO; 3375 } else { 3376 tmp = FLOAT_ZERO; 3377 } 3378 3379 dspio_set_uint_param(codec, ca0132_voicefx.mid, 3380 ca0132_voicefx.reqs[0], tmp); 3381 3382 return 1; 3383 } 3384 3385 /* 3386 * Set the effects parameters 3387 */ 3388 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val) 3389 { 3390 struct ca0132_spec *spec = codec->spec; 3391 unsigned int on; 3392 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 3393 int err = 0; 3394 int idx = nid - EFFECT_START_NID; 3395 3396 if ((idx < 0) || (idx >= num_fx)) 3397 return 0; /* no changed */ 3398 3399 /* for out effect, qualify with PE */ 3400 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) { 3401 /* if PE if off, turn off out effects. */ 3402 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 3403 val = 0; 3404 } 3405 3406 /* for in effect, qualify with CrystalVoice */ 3407 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) { 3408 /* if CrystalVoice if off, turn off in effects. */ 3409 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 3410 val = 0; 3411 3412 /* Voice Focus applies to 2-ch Mic, Digital Mic */ 3413 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC)) 3414 val = 0; 3415 } 3416 3417 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n", 3418 nid, val); 3419 3420 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE; 3421 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid, 3422 ca0132_effects[idx].reqs[0], on); 3423 3424 if (err < 0) 3425 return 0; /* no changed */ 3426 3427 return 1; 3428 } 3429 3430 /* 3431 * Turn on/off Playback Enhancements 3432 */ 3433 static int ca0132_pe_switch_set(struct hda_codec *codec) 3434 { 3435 struct ca0132_spec *spec = codec->spec; 3436 hda_nid_t nid; 3437 int i, ret = 0; 3438 3439 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n", 3440 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]); 3441 3442 i = OUT_EFFECT_START_NID - EFFECT_START_NID; 3443 nid = OUT_EFFECT_START_NID; 3444 /* PE affects all out effects */ 3445 for (; nid < OUT_EFFECT_END_NID; nid++, i++) 3446 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 3447 3448 return ret; 3449 } 3450 3451 /* Check if Mic1 is streaming, if so, stop streaming */ 3452 static int stop_mic1(struct hda_codec *codec) 3453 { 3454 struct ca0132_spec *spec = codec->spec; 3455 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0, 3456 AC_VERB_GET_CONV, 0); 3457 if (oldval != 0) 3458 snd_hda_codec_write(codec, spec->adcs[0], 0, 3459 AC_VERB_SET_CHANNEL_STREAMID, 3460 0); 3461 return oldval; 3462 } 3463 3464 /* Resume Mic1 streaming if it was stopped. */ 3465 static void resume_mic1(struct hda_codec *codec, unsigned int oldval) 3466 { 3467 struct ca0132_spec *spec = codec->spec; 3468 /* Restore the previous stream and channel */ 3469 if (oldval != 0) 3470 snd_hda_codec_write(codec, spec->adcs[0], 0, 3471 AC_VERB_SET_CHANNEL_STREAMID, 3472 oldval); 3473 } 3474 3475 /* 3476 * Turn on/off CrystalVoice 3477 */ 3478 static int ca0132_cvoice_switch_set(struct hda_codec *codec) 3479 { 3480 struct ca0132_spec *spec = codec->spec; 3481 hda_nid_t nid; 3482 int i, ret = 0; 3483 unsigned int oldval; 3484 3485 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n", 3486 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]); 3487 3488 i = IN_EFFECT_START_NID - EFFECT_START_NID; 3489 nid = IN_EFFECT_START_NID; 3490 /* CrystalVoice affects all in effects */ 3491 for (; nid < IN_EFFECT_END_NID; nid++, i++) 3492 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 3493 3494 /* including VoiceFX */ 3495 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0)); 3496 3497 /* set correct vipsource */ 3498 oldval = stop_mic1(codec); 3499 ret |= ca0132_set_vipsource(codec, 1); 3500 resume_mic1(codec, oldval); 3501 return ret; 3502 } 3503 3504 static int ca0132_mic_boost_set(struct hda_codec *codec, long val) 3505 { 3506 struct ca0132_spec *spec = codec->spec; 3507 int ret = 0; 3508 3509 if (val) /* on */ 3510 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 3511 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3); 3512 else /* off */ 3513 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 3514 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0); 3515 3516 return ret; 3517 } 3518 3519 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol, 3520 struct snd_ctl_elem_value *ucontrol) 3521 { 3522 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3523 hda_nid_t nid = get_amp_nid(kcontrol); 3524 hda_nid_t shared_nid = 0; 3525 bool effective; 3526 int ret = 0; 3527 struct ca0132_spec *spec = codec->spec; 3528 int auto_jack; 3529 3530 if (nid == VNID_HP_SEL) { 3531 auto_jack = 3532 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 3533 if (!auto_jack) 3534 ca0132_select_out(codec); 3535 return 1; 3536 } 3537 3538 if (nid == VNID_AMIC1_SEL) { 3539 auto_jack = 3540 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 3541 if (!auto_jack) 3542 ca0132_select_mic(codec); 3543 return 1; 3544 } 3545 3546 if (nid == VNID_HP_ASEL) { 3547 ca0132_select_out(codec); 3548 return 1; 3549 } 3550 3551 if (nid == VNID_AMIC1_ASEL) { 3552 ca0132_select_mic(codec); 3553 return 1; 3554 } 3555 3556 /* if effective conditions, then update hw immediately. */ 3557 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 3558 if (effective) { 3559 int dir = get_amp_direction(kcontrol); 3560 int ch = get_amp_channels(kcontrol); 3561 unsigned long pval; 3562 3563 mutex_lock(&codec->control_mutex); 3564 pval = kcontrol->private_value; 3565 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 3566 0, dir); 3567 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol); 3568 kcontrol->private_value = pval; 3569 mutex_unlock(&codec->control_mutex); 3570 } 3571 3572 return ret; 3573 } 3574 /* End of control change helpers. */ 3575 3576 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol, 3577 struct snd_ctl_elem_info *uinfo) 3578 { 3579 unsigned int items = sizeof(ca0132_voicefx_presets) 3580 / sizeof(struct ct_voicefx_preset); 3581 3582 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3583 uinfo->count = 1; 3584 uinfo->value.enumerated.items = items; 3585 if (uinfo->value.enumerated.item >= items) 3586 uinfo->value.enumerated.item = items - 1; 3587 strcpy(uinfo->value.enumerated.name, 3588 ca0132_voicefx_presets[uinfo->value.enumerated.item].name); 3589 return 0; 3590 } 3591 3592 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol, 3593 struct snd_ctl_elem_value *ucontrol) 3594 { 3595 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3596 struct ca0132_spec *spec = codec->spec; 3597 3598 ucontrol->value.enumerated.item[0] = spec->voicefx_val; 3599 return 0; 3600 } 3601 3602 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol, 3603 struct snd_ctl_elem_value *ucontrol) 3604 { 3605 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3606 struct ca0132_spec *spec = codec->spec; 3607 int i, err = 0; 3608 int sel = ucontrol->value.enumerated.item[0]; 3609 unsigned int items = sizeof(ca0132_voicefx_presets) 3610 / sizeof(struct ct_voicefx_preset); 3611 3612 if (sel >= items) 3613 return 0; 3614 3615 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n", 3616 sel, ca0132_voicefx_presets[sel].name); 3617 3618 /* 3619 * Idx 0 is default. 3620 * Default needs to qualify with CrystalVoice state. 3621 */ 3622 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) { 3623 err = dspio_set_uint_param(codec, ca0132_voicefx.mid, 3624 ca0132_voicefx.reqs[i], 3625 ca0132_voicefx_presets[sel].vals[i]); 3626 if (err < 0) 3627 break; 3628 } 3629 3630 if (err >= 0) { 3631 spec->voicefx_val = sel; 3632 /* enable voice fx */ 3633 ca0132_voicefx_set(codec, (sel ? 1 : 0)); 3634 } 3635 3636 return 1; 3637 } 3638 3639 static int ca0132_switch_get(struct snd_kcontrol *kcontrol, 3640 struct snd_ctl_elem_value *ucontrol) 3641 { 3642 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3643 struct ca0132_spec *spec = codec->spec; 3644 hda_nid_t nid = get_amp_nid(kcontrol); 3645 int ch = get_amp_channels(kcontrol); 3646 long *valp = ucontrol->value.integer.value; 3647 3648 /* vnode */ 3649 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 3650 if (ch & 1) { 3651 *valp = spec->vnode_lswitch[nid - VNODE_START_NID]; 3652 valp++; 3653 } 3654 if (ch & 2) { 3655 *valp = spec->vnode_rswitch[nid - VNODE_START_NID]; 3656 valp++; 3657 } 3658 return 0; 3659 } 3660 3661 /* effects, include PE and CrystalVoice */ 3662 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) { 3663 *valp = spec->effects_switch[nid - EFFECT_START_NID]; 3664 return 0; 3665 } 3666 3667 /* mic boost */ 3668 if (nid == spec->input_pins[0]) { 3669 *valp = spec->cur_mic_boost; 3670 return 0; 3671 } 3672 3673 return 0; 3674 } 3675 3676 static int ca0132_switch_put(struct snd_kcontrol *kcontrol, 3677 struct snd_ctl_elem_value *ucontrol) 3678 { 3679 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3680 struct ca0132_spec *spec = codec->spec; 3681 hda_nid_t nid = get_amp_nid(kcontrol); 3682 int ch = get_amp_channels(kcontrol); 3683 long *valp = ucontrol->value.integer.value; 3684 int changed = 1; 3685 3686 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n", 3687 nid, *valp); 3688 3689 snd_hda_power_up(codec); 3690 /* vnode */ 3691 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 3692 if (ch & 1) { 3693 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp; 3694 valp++; 3695 } 3696 if (ch & 2) { 3697 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp; 3698 valp++; 3699 } 3700 changed = ca0132_vnode_switch_set(kcontrol, ucontrol); 3701 goto exit; 3702 } 3703 3704 /* PE */ 3705 if (nid == PLAY_ENHANCEMENT) { 3706 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 3707 changed = ca0132_pe_switch_set(codec); 3708 goto exit; 3709 } 3710 3711 /* CrystalVoice */ 3712 if (nid == CRYSTAL_VOICE) { 3713 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 3714 changed = ca0132_cvoice_switch_set(codec); 3715 goto exit; 3716 } 3717 3718 /* out and in effects */ 3719 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) || 3720 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) { 3721 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 3722 changed = ca0132_effects_set(codec, nid, *valp); 3723 goto exit; 3724 } 3725 3726 /* mic boost */ 3727 if (nid == spec->input_pins[0]) { 3728 spec->cur_mic_boost = *valp; 3729 3730 /* Mic boost does not apply to Digital Mic */ 3731 if (spec->cur_mic_type != DIGITAL_MIC) 3732 changed = ca0132_mic_boost_set(codec, *valp); 3733 goto exit; 3734 } 3735 3736 exit: 3737 snd_hda_power_down(codec); 3738 return changed; 3739 } 3740 3741 /* 3742 * Volume related 3743 */ 3744 static int ca0132_volume_info(struct snd_kcontrol *kcontrol, 3745 struct snd_ctl_elem_info *uinfo) 3746 { 3747 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3748 struct ca0132_spec *spec = codec->spec; 3749 hda_nid_t nid = get_amp_nid(kcontrol); 3750 int ch = get_amp_channels(kcontrol); 3751 int dir = get_amp_direction(kcontrol); 3752 unsigned long pval; 3753 int err; 3754 3755 switch (nid) { 3756 case VNID_SPK: 3757 /* follow shared_out info */ 3758 nid = spec->shared_out_nid; 3759 mutex_lock(&codec->control_mutex); 3760 pval = kcontrol->private_value; 3761 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 3762 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 3763 kcontrol->private_value = pval; 3764 mutex_unlock(&codec->control_mutex); 3765 break; 3766 case VNID_MIC: 3767 /* follow shared_mic info */ 3768 nid = spec->shared_mic_nid; 3769 mutex_lock(&codec->control_mutex); 3770 pval = kcontrol->private_value; 3771 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 3772 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 3773 kcontrol->private_value = pval; 3774 mutex_unlock(&codec->control_mutex); 3775 break; 3776 default: 3777 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 3778 } 3779 return err; 3780 } 3781 3782 static int ca0132_volume_get(struct snd_kcontrol *kcontrol, 3783 struct snd_ctl_elem_value *ucontrol) 3784 { 3785 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3786 struct ca0132_spec *spec = codec->spec; 3787 hda_nid_t nid = get_amp_nid(kcontrol); 3788 int ch = get_amp_channels(kcontrol); 3789 long *valp = ucontrol->value.integer.value; 3790 3791 /* store the left and right volume */ 3792 if (ch & 1) { 3793 *valp = spec->vnode_lvol[nid - VNODE_START_NID]; 3794 valp++; 3795 } 3796 if (ch & 2) { 3797 *valp = spec->vnode_rvol[nid - VNODE_START_NID]; 3798 valp++; 3799 } 3800 return 0; 3801 } 3802 3803 static int ca0132_volume_put(struct snd_kcontrol *kcontrol, 3804 struct snd_ctl_elem_value *ucontrol) 3805 { 3806 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3807 struct ca0132_spec *spec = codec->spec; 3808 hda_nid_t nid = get_amp_nid(kcontrol); 3809 int ch = get_amp_channels(kcontrol); 3810 long *valp = ucontrol->value.integer.value; 3811 hda_nid_t shared_nid = 0; 3812 bool effective; 3813 int changed = 1; 3814 3815 /* store the left and right volume */ 3816 if (ch & 1) { 3817 spec->vnode_lvol[nid - VNODE_START_NID] = *valp; 3818 valp++; 3819 } 3820 if (ch & 2) { 3821 spec->vnode_rvol[nid - VNODE_START_NID] = *valp; 3822 valp++; 3823 } 3824 3825 /* if effective conditions, then update hw immediately. */ 3826 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 3827 if (effective) { 3828 int dir = get_amp_direction(kcontrol); 3829 unsigned long pval; 3830 3831 snd_hda_power_up(codec); 3832 mutex_lock(&codec->control_mutex); 3833 pval = kcontrol->private_value; 3834 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 3835 0, dir); 3836 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 3837 kcontrol->private_value = pval; 3838 mutex_unlock(&codec->control_mutex); 3839 snd_hda_power_down(codec); 3840 } 3841 3842 return changed; 3843 } 3844 3845 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag, 3846 unsigned int size, unsigned int __user *tlv) 3847 { 3848 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3849 struct ca0132_spec *spec = codec->spec; 3850 hda_nid_t nid = get_amp_nid(kcontrol); 3851 int ch = get_amp_channels(kcontrol); 3852 int dir = get_amp_direction(kcontrol); 3853 unsigned long pval; 3854 int err; 3855 3856 switch (nid) { 3857 case VNID_SPK: 3858 /* follow shared_out tlv */ 3859 nid = spec->shared_out_nid; 3860 mutex_lock(&codec->control_mutex); 3861 pval = kcontrol->private_value; 3862 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 3863 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 3864 kcontrol->private_value = pval; 3865 mutex_unlock(&codec->control_mutex); 3866 break; 3867 case VNID_MIC: 3868 /* follow shared_mic tlv */ 3869 nid = spec->shared_mic_nid; 3870 mutex_lock(&codec->control_mutex); 3871 pval = kcontrol->private_value; 3872 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 3873 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 3874 kcontrol->private_value = pval; 3875 mutex_unlock(&codec->control_mutex); 3876 break; 3877 default: 3878 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 3879 } 3880 return err; 3881 } 3882 3883 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid, 3884 const char *pfx, int dir) 3885 { 3886 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 3887 int type = dir ? HDA_INPUT : HDA_OUTPUT; 3888 struct snd_kcontrol_new knew = 3889 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type); 3890 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]); 3891 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 3892 } 3893 3894 static int add_voicefx(struct hda_codec *codec) 3895 { 3896 struct snd_kcontrol_new knew = 3897 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name, 3898 VOICEFX, 1, 0, HDA_INPUT); 3899 knew.info = ca0132_voicefx_info; 3900 knew.get = ca0132_voicefx_get; 3901 knew.put = ca0132_voicefx_put; 3902 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec)); 3903 } 3904 3905 /* 3906 * When changing Node IDs for Mixer Controls below, make sure to update 3907 * Node IDs in ca0132_config() as well. 3908 */ 3909 static struct snd_kcontrol_new ca0132_mixer[] = { 3910 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT), 3911 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT), 3912 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 3913 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 3914 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT), 3915 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT), 3916 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 3917 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 3918 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch", 3919 0x12, 1, HDA_INPUT), 3920 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch", 3921 VNID_HP_SEL, 1, HDA_OUTPUT), 3922 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch", 3923 VNID_AMIC1_SEL, 1, HDA_INPUT), 3924 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 3925 VNID_HP_ASEL, 1, HDA_OUTPUT), 3926 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch", 3927 VNID_AMIC1_ASEL, 1, HDA_INPUT), 3928 { } /* end */ 3929 }; 3930 3931 static int ca0132_build_controls(struct hda_codec *codec) 3932 { 3933 struct ca0132_spec *spec = codec->spec; 3934 int i, num_fx; 3935 int err = 0; 3936 3937 /* Add Mixer controls */ 3938 for (i = 0; i < spec->num_mixers; i++) { 3939 err = snd_hda_add_new_ctls(codec, spec->mixers[i]); 3940 if (err < 0) 3941 return err; 3942 } 3943 3944 /* Add in and out effects controls. 3945 * VoiceFX, PE and CrystalVoice are added separately. 3946 */ 3947 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 3948 for (i = 0; i < num_fx; i++) { 3949 err = add_fx_switch(codec, ca0132_effects[i].nid, 3950 ca0132_effects[i].name, 3951 ca0132_effects[i].direct); 3952 if (err < 0) 3953 return err; 3954 } 3955 3956 err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0); 3957 if (err < 0) 3958 return err; 3959 3960 err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1); 3961 if (err < 0) 3962 return err; 3963 3964 add_voicefx(codec); 3965 3966 #ifdef ENABLE_TUNING_CONTROLS 3967 add_tuning_ctls(codec); 3968 #endif 3969 3970 err = snd_hda_jack_add_kctls(codec, &spec->autocfg); 3971 if (err < 0) 3972 return err; 3973 3974 if (spec->dig_out) { 3975 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 3976 spec->dig_out); 3977 if (err < 0) 3978 return err; 3979 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout); 3980 if (err < 0) 3981 return err; 3982 /* spec->multiout.share_spdif = 1; */ 3983 } 3984 3985 if (spec->dig_in) { 3986 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 3987 if (err < 0) 3988 return err; 3989 } 3990 return 0; 3991 } 3992 3993 /* 3994 * PCM 3995 */ 3996 static struct hda_pcm_stream ca0132_pcm_analog_playback = { 3997 .substreams = 1, 3998 .channels_min = 2, 3999 .channels_max = 6, 4000 .ops = { 4001 .prepare = ca0132_playback_pcm_prepare, 4002 .cleanup = ca0132_playback_pcm_cleanup, 4003 .get_delay = ca0132_playback_pcm_delay, 4004 }, 4005 }; 4006 4007 static struct hda_pcm_stream ca0132_pcm_analog_capture = { 4008 .substreams = 1, 4009 .channels_min = 2, 4010 .channels_max = 2, 4011 .ops = { 4012 .prepare = ca0132_capture_pcm_prepare, 4013 .cleanup = ca0132_capture_pcm_cleanup, 4014 .get_delay = ca0132_capture_pcm_delay, 4015 }, 4016 }; 4017 4018 static struct hda_pcm_stream ca0132_pcm_digital_playback = { 4019 .substreams = 1, 4020 .channels_min = 2, 4021 .channels_max = 2, 4022 .ops = { 4023 .open = ca0132_dig_playback_pcm_open, 4024 .close = ca0132_dig_playback_pcm_close, 4025 .prepare = ca0132_dig_playback_pcm_prepare, 4026 .cleanup = ca0132_dig_playback_pcm_cleanup 4027 }, 4028 }; 4029 4030 static struct hda_pcm_stream ca0132_pcm_digital_capture = { 4031 .substreams = 1, 4032 .channels_min = 2, 4033 .channels_max = 2, 4034 }; 4035 4036 static int ca0132_build_pcms(struct hda_codec *codec) 4037 { 4038 struct ca0132_spec *spec = codec->spec; 4039 struct hda_pcm *info = spec->pcm_rec; 4040 4041 codec->pcm_info = info; 4042 codec->num_pcms = 0; 4043 4044 info->name = "CA0132 Analog"; 4045 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback; 4046 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0]; 4047 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max = 4048 spec->multiout.max_channels; 4049 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 4050 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 4051 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 4052 codec->num_pcms++; 4053 4054 info++; 4055 info->name = "CA0132 Analog Mic-In2"; 4056 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 4057 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 4058 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1]; 4059 codec->num_pcms++; 4060 4061 info++; 4062 info->name = "CA0132 What U Hear"; 4063 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 4064 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 4065 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2]; 4066 codec->num_pcms++; 4067 4068 if (!spec->dig_out && !spec->dig_in) 4069 return 0; 4070 4071 info++; 4072 info->name = "CA0132 Digital"; 4073 info->pcm_type = HDA_PCM_TYPE_SPDIF; 4074 if (spec->dig_out) { 4075 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 4076 ca0132_pcm_digital_playback; 4077 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 4078 } 4079 if (spec->dig_in) { 4080 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 4081 ca0132_pcm_digital_capture; 4082 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 4083 } 4084 codec->num_pcms++; 4085 4086 return 0; 4087 } 4088 4089 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac) 4090 { 4091 if (pin) { 4092 snd_hda_set_pin_ctl(codec, pin, PIN_HP); 4093 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 4094 snd_hda_codec_write(codec, pin, 0, 4095 AC_VERB_SET_AMP_GAIN_MUTE, 4096 AMP_OUT_UNMUTE); 4097 } 4098 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP)) 4099 snd_hda_codec_write(codec, dac, 0, 4100 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO); 4101 } 4102 4103 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc) 4104 { 4105 if (pin) { 4106 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80); 4107 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP) 4108 snd_hda_codec_write(codec, pin, 0, 4109 AC_VERB_SET_AMP_GAIN_MUTE, 4110 AMP_IN_UNMUTE(0)); 4111 } 4112 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) { 4113 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE, 4114 AMP_IN_UNMUTE(0)); 4115 4116 /* init to 0 dB and unmute. */ 4117 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 4118 HDA_AMP_VOLMASK, 0x5a); 4119 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 4120 HDA_AMP_MUTE, 0); 4121 } 4122 } 4123 4124 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir) 4125 { 4126 unsigned int caps; 4127 4128 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ? 4129 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP); 4130 snd_hda_override_amp_caps(codec, nid, dir, caps); 4131 } 4132 4133 /* 4134 * Switch between Digital built-in mic and analog mic. 4135 */ 4136 static void ca0132_set_dmic(struct hda_codec *codec, int enable) 4137 { 4138 struct ca0132_spec *spec = codec->spec; 4139 unsigned int tmp; 4140 u8 val; 4141 unsigned int oldval; 4142 4143 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable); 4144 4145 oldval = stop_mic1(codec); 4146 ca0132_set_vipsource(codec, 0); 4147 if (enable) { 4148 /* set DMic input as 2-ch */ 4149 tmp = FLOAT_TWO; 4150 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4151 4152 val = spec->dmic_ctl; 4153 val |= 0x80; 4154 snd_hda_codec_write(codec, spec->input_pins[0], 0, 4155 VENDOR_CHIPIO_DMIC_CTL_SET, val); 4156 4157 if (!(spec->dmic_ctl & 0x20)) 4158 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1); 4159 } else { 4160 /* set AMic input as mono */ 4161 tmp = FLOAT_ONE; 4162 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4163 4164 val = spec->dmic_ctl; 4165 /* clear bit7 and bit5 to disable dmic */ 4166 val &= 0x5f; 4167 snd_hda_codec_write(codec, spec->input_pins[0], 0, 4168 VENDOR_CHIPIO_DMIC_CTL_SET, val); 4169 4170 if (!(spec->dmic_ctl & 0x20)) 4171 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0); 4172 } 4173 ca0132_set_vipsource(codec, 1); 4174 resume_mic1(codec, oldval); 4175 } 4176 4177 /* 4178 * Initialization for Digital Mic. 4179 */ 4180 static void ca0132_init_dmic(struct hda_codec *codec) 4181 { 4182 struct ca0132_spec *spec = codec->spec; 4183 u8 val; 4184 4185 /* Setup Digital Mic here, but don't enable. 4186 * Enable based on jack detect. 4187 */ 4188 4189 /* MCLK uses MPIO1, set to enable. 4190 * Bit 2-0: MPIO select 4191 * Bit 3: set to disable 4192 * Bit 7-4: reserved 4193 */ 4194 val = 0x01; 4195 snd_hda_codec_write(codec, spec->input_pins[0], 0, 4196 VENDOR_CHIPIO_DMIC_MCLK_SET, val); 4197 4198 /* Data1 uses MPIO3. Data2 not use 4199 * Bit 2-0: Data1 MPIO select 4200 * Bit 3: set disable Data1 4201 * Bit 6-4: Data2 MPIO select 4202 * Bit 7: set disable Data2 4203 */ 4204 val = 0x83; 4205 snd_hda_codec_write(codec, spec->input_pins[0], 0, 4206 VENDOR_CHIPIO_DMIC_PIN_SET, val); 4207 4208 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first. 4209 * Bit 3-0: Channel mask 4210 * Bit 4: set for 48KHz, clear for 32KHz 4211 * Bit 5: mode 4212 * Bit 6: set to select Data2, clear for Data1 4213 * Bit 7: set to enable DMic, clear for AMic 4214 */ 4215 val = 0x23; 4216 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */ 4217 spec->dmic_ctl = val; 4218 snd_hda_codec_write(codec, spec->input_pins[0], 0, 4219 VENDOR_CHIPIO_DMIC_CTL_SET, val); 4220 } 4221 4222 /* 4223 * Initialization for Analog Mic 2 4224 */ 4225 static void ca0132_init_analog_mic2(struct hda_codec *codec) 4226 { 4227 struct ca0132_spec *spec = codec->spec; 4228 4229 mutex_lock(&spec->chipio_mutex); 4230 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 4231 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); 4232 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 4233 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 4234 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 4235 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 4236 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 4237 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D); 4238 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 4239 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 4240 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 4241 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 4242 mutex_unlock(&spec->chipio_mutex); 4243 } 4244 4245 static void ca0132_refresh_widget_caps(struct hda_codec *codec) 4246 { 4247 struct ca0132_spec *spec = codec->spec; 4248 int i; 4249 hda_nid_t nid; 4250 4251 codec_dbg(codec, "ca0132_refresh_widget_caps.\n"); 4252 nid = codec->start_nid; 4253 for (i = 0; i < codec->num_nodes; i++, nid++) 4254 codec->wcaps[i] = snd_hda_param_read(codec, nid, 4255 AC_PAR_AUDIO_WIDGET_CAP); 4256 4257 for (i = 0; i < spec->multiout.num_dacs; i++) 4258 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT); 4259 4260 for (i = 0; i < spec->num_outputs; i++) 4261 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT); 4262 4263 for (i = 0; i < spec->num_inputs; i++) { 4264 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT); 4265 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT); 4266 } 4267 } 4268 4269 /* 4270 * Setup default parameters for DSP 4271 */ 4272 static void ca0132_setup_defaults(struct hda_codec *codec) 4273 { 4274 struct ca0132_spec *spec = codec->spec; 4275 unsigned int tmp; 4276 int num_fx; 4277 int idx, i; 4278 4279 if (spec->dsp_state != DSP_DOWNLOADED) 4280 return; 4281 4282 /* out, in effects + voicefx */ 4283 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 4284 for (idx = 0; idx < num_fx; idx++) { 4285 for (i = 0; i <= ca0132_effects[idx].params; i++) { 4286 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 4287 ca0132_effects[idx].reqs[i], 4288 ca0132_effects[idx].def_vals[i]); 4289 } 4290 } 4291 4292 /*remove DSP headroom*/ 4293 tmp = FLOAT_ZERO; 4294 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 4295 4296 /*set speaker EQ bypass attenuation*/ 4297 dspio_set_uint_param(codec, 0x8f, 0x01, tmp); 4298 4299 /* set AMic1 and AMic2 as mono mic */ 4300 tmp = FLOAT_ONE; 4301 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4302 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 4303 4304 /* set AMic1 as CrystalVoice input */ 4305 tmp = FLOAT_ONE; 4306 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4307 4308 /* set WUH source */ 4309 tmp = FLOAT_TWO; 4310 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 4311 } 4312 4313 /* 4314 * Initialization of flags in chip 4315 */ 4316 static void ca0132_init_flags(struct hda_codec *codec) 4317 { 4318 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 4319 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0); 4320 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0); 4321 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0); 4322 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 4323 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1); 4324 } 4325 4326 /* 4327 * Initialization of parameters in chip 4328 */ 4329 static void ca0132_init_params(struct hda_codec *codec) 4330 { 4331 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6); 4332 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6); 4333 } 4334 4335 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k) 4336 { 4337 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k); 4338 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k); 4339 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k); 4340 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k); 4341 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k); 4342 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k); 4343 4344 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4345 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4346 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 4347 } 4348 4349 static bool ca0132_download_dsp_images(struct hda_codec *codec) 4350 { 4351 bool dsp_loaded = false; 4352 const struct dsp_image_seg *dsp_os_image; 4353 const struct firmware *fw_entry; 4354 4355 if (request_firmware(&fw_entry, EFX_FILE, codec->bus->card->dev) != 0) 4356 return false; 4357 4358 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data); 4359 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) { 4360 pr_err("ca0132 dspload_image failed.\n"); 4361 goto exit_download; 4362 } 4363 4364 dsp_loaded = dspload_wait_loaded(codec); 4365 4366 exit_download: 4367 release_firmware(fw_entry); 4368 4369 return dsp_loaded; 4370 } 4371 4372 static void ca0132_download_dsp(struct hda_codec *codec) 4373 { 4374 struct ca0132_spec *spec = codec->spec; 4375 4376 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP 4377 return; /* NOP */ 4378 #endif 4379 4380 if (spec->dsp_state == DSP_DOWNLOAD_FAILED) 4381 return; /* don't retry failures */ 4382 4383 chipio_enable_clocks(codec); 4384 spec->dsp_state = DSP_DOWNLOADING; 4385 if (!ca0132_download_dsp_images(codec)) 4386 spec->dsp_state = DSP_DOWNLOAD_FAILED; 4387 else 4388 spec->dsp_state = DSP_DOWNLOADED; 4389 4390 if (spec->dsp_state == DSP_DOWNLOADED) 4391 ca0132_set_dsp_msr(codec, true); 4392 } 4393 4394 static void ca0132_process_dsp_response(struct hda_codec *codec, 4395 struct hda_jack_callback *callback) 4396 { 4397 struct ca0132_spec *spec = codec->spec; 4398 4399 codec_dbg(codec, "ca0132_process_dsp_response\n"); 4400 if (spec->wait_scp) { 4401 if (dspio_get_response_data(codec) >= 0) 4402 spec->wait_scp = 0; 4403 } 4404 4405 dspio_clear_response_queue(codec); 4406 } 4407 4408 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 4409 { 4410 struct ca0132_spec *spec = codec->spec; 4411 4412 /* Delay enabling the HP amp, to let the mic-detection 4413 * state machine run. 4414 */ 4415 cancel_delayed_work_sync(&spec->unsol_hp_work); 4416 queue_delayed_work(codec->bus->workq, &spec->unsol_hp_work, 4417 msecs_to_jiffies(500)); 4418 cb->tbl->block_report = 1; 4419 } 4420 4421 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 4422 { 4423 ca0132_select_mic(codec); 4424 } 4425 4426 static void ca0132_init_unsol(struct hda_codec *codec) 4427 { 4428 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_HP, hp_callback); 4429 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_AMIC1, 4430 amic_callback); 4431 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP, 4432 ca0132_process_dsp_response); 4433 } 4434 4435 /* 4436 * Verbs tables. 4437 */ 4438 4439 /* Sends before DSP download. */ 4440 static struct hda_verb ca0132_base_init_verbs[] = { 4441 /*enable ct extension*/ 4442 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1}, 4443 {} 4444 }; 4445 4446 /* Send at exit. */ 4447 static struct hda_verb ca0132_base_exit_verbs[] = { 4448 /*set afg to D3*/ 4449 {0x01, AC_VERB_SET_POWER_STATE, 0x03}, 4450 /*disable ct extension*/ 4451 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0}, 4452 {} 4453 }; 4454 4455 /* Other verbs tables. Sends after DSP download. */ 4456 static struct hda_verb ca0132_init_verbs0[] = { 4457 /* chip init verbs */ 4458 {0x15, 0x70D, 0xF0}, 4459 {0x15, 0x70E, 0xFE}, 4460 {0x15, 0x707, 0x75}, 4461 {0x15, 0x707, 0xD3}, 4462 {0x15, 0x707, 0x09}, 4463 {0x15, 0x707, 0x53}, 4464 {0x15, 0x707, 0xD4}, 4465 {0x15, 0x707, 0xEF}, 4466 {0x15, 0x707, 0x75}, 4467 {0x15, 0x707, 0xD3}, 4468 {0x15, 0x707, 0x09}, 4469 {0x15, 0x707, 0x02}, 4470 {0x15, 0x707, 0x37}, 4471 {0x15, 0x707, 0x78}, 4472 {0x15, 0x53C, 0xCE}, 4473 {0x15, 0x575, 0xC9}, 4474 {0x15, 0x53D, 0xCE}, 4475 {0x15, 0x5B7, 0xC9}, 4476 {0x15, 0x70D, 0xE8}, 4477 {0x15, 0x70E, 0xFE}, 4478 {0x15, 0x707, 0x02}, 4479 {0x15, 0x707, 0x68}, 4480 {0x15, 0x707, 0x62}, 4481 {0x15, 0x53A, 0xCE}, 4482 {0x15, 0x546, 0xC9}, 4483 {0x15, 0x53B, 0xCE}, 4484 {0x15, 0x5E8, 0xC9}, 4485 {0x15, 0x717, 0x0D}, 4486 {0x15, 0x718, 0x20}, 4487 {} 4488 }; 4489 4490 static struct hda_verb ca0132_init_verbs1[] = { 4491 {0x10, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_HP}, 4492 {0x12, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_AMIC1}, 4493 /* config EAPD */ 4494 {0x0b, 0x78D, 0x00}, 4495 /*{0x0b, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/ 4496 /*{0x10, 0x78D, 0x02},*/ 4497 /*{0x10, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/ 4498 {} 4499 }; 4500 4501 static void ca0132_init_chip(struct hda_codec *codec) 4502 { 4503 struct ca0132_spec *spec = codec->spec; 4504 int num_fx; 4505 int i; 4506 unsigned int on; 4507 4508 mutex_init(&spec->chipio_mutex); 4509 4510 spec->cur_out_type = SPEAKER_OUT; 4511 spec->cur_mic_type = DIGITAL_MIC; 4512 spec->cur_mic_boost = 0; 4513 4514 for (i = 0; i < VNODES_COUNT; i++) { 4515 spec->vnode_lvol[i] = 0x5a; 4516 spec->vnode_rvol[i] = 0x5a; 4517 spec->vnode_lswitch[i] = 0; 4518 spec->vnode_rswitch[i] = 0; 4519 } 4520 4521 /* 4522 * Default states for effects are in ca0132_effects[]. 4523 */ 4524 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 4525 for (i = 0; i < num_fx; i++) { 4526 on = (unsigned int)ca0132_effects[i].reqs[0]; 4527 spec->effects_switch[i] = on ? 1 : 0; 4528 } 4529 4530 spec->voicefx_val = 0; 4531 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1; 4532 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0; 4533 4534 #ifdef ENABLE_TUNING_CONTROLS 4535 ca0132_init_tuning_defaults(codec); 4536 #endif 4537 } 4538 4539 static void ca0132_exit_chip(struct hda_codec *codec) 4540 { 4541 /* put any chip cleanup stuffs here. */ 4542 4543 if (dspload_is_loaded(codec)) 4544 dsp_reset(codec); 4545 } 4546 4547 static int ca0132_init(struct hda_codec *codec) 4548 { 4549 struct ca0132_spec *spec = codec->spec; 4550 struct auto_pin_cfg *cfg = &spec->autocfg; 4551 int i; 4552 4553 if (spec->dsp_state != DSP_DOWNLOAD_FAILED) 4554 spec->dsp_state = DSP_DOWNLOAD_INIT; 4555 spec->curr_chip_addx = INVALID_CHIP_ADDRESS; 4556 4557 snd_hda_power_up(codec); 4558 4559 ca0132_init_unsol(codec); 4560 4561 ca0132_init_params(codec); 4562 ca0132_init_flags(codec); 4563 snd_hda_sequence_write(codec, spec->base_init_verbs); 4564 ca0132_download_dsp(codec); 4565 ca0132_refresh_widget_caps(codec); 4566 ca0132_setup_defaults(codec); 4567 ca0132_init_analog_mic2(codec); 4568 ca0132_init_dmic(codec); 4569 4570 for (i = 0; i < spec->num_outputs; i++) 4571 init_output(codec, spec->out_pins[i], spec->dacs[0]); 4572 4573 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 4574 4575 for (i = 0; i < spec->num_inputs; i++) 4576 init_input(codec, spec->input_pins[i], spec->adcs[i]); 4577 4578 init_input(codec, cfg->dig_in_pin, spec->dig_in); 4579 4580 for (i = 0; i < spec->num_init_verbs; i++) 4581 snd_hda_sequence_write(codec, spec->init_verbs[i]); 4582 4583 ca0132_select_out(codec); 4584 ca0132_select_mic(codec); 4585 4586 snd_hda_jack_report_sync(codec); 4587 4588 snd_hda_power_down(codec); 4589 4590 return 0; 4591 } 4592 4593 static void ca0132_free(struct hda_codec *codec) 4594 { 4595 struct ca0132_spec *spec = codec->spec; 4596 4597 cancel_delayed_work_sync(&spec->unsol_hp_work); 4598 snd_hda_power_up(codec); 4599 snd_hda_sequence_write(codec, spec->base_exit_verbs); 4600 ca0132_exit_chip(codec); 4601 snd_hda_power_down(codec); 4602 kfree(codec->spec); 4603 } 4604 4605 static struct hda_codec_ops ca0132_patch_ops = { 4606 .build_controls = ca0132_build_controls, 4607 .build_pcms = ca0132_build_pcms, 4608 .init = ca0132_init, 4609 .free = ca0132_free, 4610 .unsol_event = snd_hda_jack_unsol_event, 4611 }; 4612 4613 static void ca0132_config(struct hda_codec *codec) 4614 { 4615 struct ca0132_spec *spec = codec->spec; 4616 struct auto_pin_cfg *cfg = &spec->autocfg; 4617 4618 spec->dacs[0] = 0x2; 4619 spec->dacs[1] = 0x3; 4620 spec->dacs[2] = 0x4; 4621 4622 spec->multiout.dac_nids = spec->dacs; 4623 spec->multiout.num_dacs = 3; 4624 spec->multiout.max_channels = 2; 4625 4626 spec->num_outputs = 2; 4627 spec->out_pins[0] = 0x0b; /* speaker out */ 4628 spec->out_pins[1] = 0x10; /* headphone out */ 4629 spec->shared_out_nid = 0x2; 4630 4631 spec->num_inputs = 3; 4632 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 4633 spec->adcs[1] = 0x8; /* analog mic2 */ 4634 spec->adcs[2] = 0xa; /* what u hear */ 4635 spec->shared_mic_nid = 0x7; 4636 4637 spec->input_pins[0] = 0x12; 4638 spec->input_pins[1] = 0x11; 4639 spec->input_pins[2] = 0x13; 4640 4641 /* SPDIF I/O */ 4642 spec->dig_out = 0x05; 4643 spec->multiout.dig_out_nid = spec->dig_out; 4644 cfg->dig_out_pins[0] = 0x0c; 4645 cfg->dig_outs = 1; 4646 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF; 4647 spec->dig_in = 0x09; 4648 cfg->dig_in_pin = 0x0e; 4649 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF; 4650 } 4651 4652 static int patch_ca0132(struct hda_codec *codec) 4653 { 4654 struct ca0132_spec *spec; 4655 int err; 4656 4657 codec_dbg(codec, "patch_ca0132\n"); 4658 4659 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 4660 if (!spec) 4661 return -ENOMEM; 4662 codec->spec = spec; 4663 spec->codec = codec; 4664 4665 spec->dsp_state = DSP_DOWNLOAD_INIT; 4666 spec->num_mixers = 1; 4667 spec->mixers[0] = ca0132_mixer; 4668 4669 spec->base_init_verbs = ca0132_base_init_verbs; 4670 spec->base_exit_verbs = ca0132_base_exit_verbs; 4671 spec->init_verbs[0] = ca0132_init_verbs0; 4672 spec->init_verbs[1] = ca0132_init_verbs1; 4673 spec->num_init_verbs = 2; 4674 4675 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed); 4676 4677 ca0132_init_chip(codec); 4678 4679 ca0132_config(codec); 4680 4681 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL); 4682 if (err < 0) 4683 return err; 4684 4685 codec->patch_ops = ca0132_patch_ops; 4686 codec->pcm_format_first = 1; 4687 codec->no_sticky_stream = 1; 4688 4689 return 0; 4690 } 4691 4692 /* 4693 * patch entries 4694 */ 4695 static struct hda_codec_preset snd_hda_preset_ca0132[] = { 4696 { .id = 0x11020011, .name = "CA0132", .patch = patch_ca0132 }, 4697 {} /* terminator */ 4698 }; 4699 4700 MODULE_ALIAS("snd-hda-codec-id:11020011"); 4701 4702 MODULE_LICENSE("GPL"); 4703 MODULE_DESCRIPTION("Creative Sound Core3D codec"); 4704 4705 static struct hda_codec_preset_list ca0132_list = { 4706 .preset = snd_hda_preset_ca0132, 4707 .owner = THIS_MODULE, 4708 }; 4709 4710 static int __init patch_ca0132_init(void) 4711 { 4712 return snd_hda_add_codec_preset(&ca0132_list); 4713 } 4714 4715 static void __exit patch_ca0132_exit(void) 4716 { 4717 snd_hda_delete_codec_preset(&ca0132_list); 4718 } 4719 4720 module_init(patch_ca0132_init) 4721 module_exit(patch_ca0132_exit) 4722