1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * HD audio interface patch for Creative CA0132 chip 4 * 5 * Copyright (c) 2011, Creative Technology Ltd. 6 * 7 * Based on patch_ca0110.c 8 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de> 9 */ 10 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/slab.h> 14 #include <linux/mutex.h> 15 #include <linux/module.h> 16 #include <linux/firmware.h> 17 #include <linux/kernel.h> 18 #include <linux/types.h> 19 #include <linux/io.h> 20 #include <linux/pci.h> 21 #include <asm/io.h> 22 #include <sound/core.h> 23 #include <sound/hda_codec.h> 24 #include "hda_local.h" 25 #include "hda_auto_parser.h" 26 #include "hda_jack.h" 27 28 #include "ca0132_regs.h" 29 30 /* Enable this to see controls for tuning purpose. */ 31 /*#define ENABLE_TUNING_CONTROLS*/ 32 33 #ifdef ENABLE_TUNING_CONTROLS 34 #include <sound/tlv.h> 35 #endif 36 37 #define FLOAT_ZERO 0x00000000 38 #define FLOAT_ONE 0x3f800000 39 #define FLOAT_TWO 0x40000000 40 #define FLOAT_THREE 0x40400000 41 #define FLOAT_FIVE 0x40a00000 42 #define FLOAT_SIX 0x40c00000 43 #define FLOAT_EIGHT 0x41000000 44 #define FLOAT_MINUS_5 0xc0a00000 45 46 #define UNSOL_TAG_DSP 0x16 47 48 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18) 49 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15) 50 51 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8 52 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32 53 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2 54 55 #define MASTERCONTROL 0x80 56 #define MASTERCONTROL_ALLOC_DMA_CHAN 10 57 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60 58 59 #define WIDGET_CHIP_CTRL 0x15 60 #define WIDGET_DSP_CTRL 0x16 61 62 #define MEM_CONNID_MICIN1 3 63 #define MEM_CONNID_MICIN2 5 64 #define MEM_CONNID_MICOUT1 12 65 #define MEM_CONNID_MICOUT2 14 66 #define MEM_CONNID_WUH 10 67 #define MEM_CONNID_DSP 16 68 #define MEM_CONNID_DMIC 100 69 70 #define SCP_SET 0 71 #define SCP_GET 1 72 73 #define EFX_FILE "ctefx.bin" 74 #define DESKTOP_EFX_FILE "ctefx-desktop.bin" 75 #define R3DI_EFX_FILE "ctefx-r3di.bin" 76 77 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 78 MODULE_FIRMWARE(EFX_FILE); 79 MODULE_FIRMWARE(DESKTOP_EFX_FILE); 80 MODULE_FIRMWARE(R3DI_EFX_FILE); 81 #endif 82 83 static const char *const dirstr[2] = { "Playback", "Capture" }; 84 85 #define NUM_OF_OUTPUTS 2 86 static const char *const out_type_str[2] = { "Speakers", "Headphone" }; 87 enum { 88 SPEAKER_OUT, 89 HEADPHONE_OUT, 90 }; 91 92 enum { 93 DIGITAL_MIC, 94 LINE_MIC_IN 95 }; 96 97 /* Strings for Input Source Enum Control */ 98 static const char *const in_src_str[3] = {"Rear Mic", "Line", "Front Mic" }; 99 #define IN_SRC_NUM_OF_INPUTS 3 100 enum { 101 REAR_MIC, 102 REAR_LINE_IN, 103 FRONT_MIC, 104 }; 105 106 enum { 107 #define VNODE_START_NID 0x80 108 VNID_SPK = VNODE_START_NID, /* Speaker vnid */ 109 VNID_MIC, 110 VNID_HP_SEL, 111 VNID_AMIC1_SEL, 112 VNID_HP_ASEL, 113 VNID_AMIC1_ASEL, 114 VNODE_END_NID, 115 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID) 116 117 #define EFFECT_START_NID 0x90 118 #define OUT_EFFECT_START_NID EFFECT_START_NID 119 SURROUND = OUT_EFFECT_START_NID, 120 CRYSTALIZER, 121 DIALOG_PLUS, 122 SMART_VOLUME, 123 X_BASS, 124 EQUALIZER, 125 OUT_EFFECT_END_NID, 126 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID) 127 128 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID 129 ECHO_CANCELLATION = IN_EFFECT_START_NID, 130 VOICE_FOCUS, 131 MIC_SVM, 132 NOISE_REDUCTION, 133 IN_EFFECT_END_NID, 134 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID) 135 136 VOICEFX = IN_EFFECT_END_NID, 137 PLAY_ENHANCEMENT, 138 CRYSTAL_VOICE, 139 EFFECT_END_NID, 140 OUTPUT_SOURCE_ENUM, 141 INPUT_SOURCE_ENUM, 142 XBASS_XOVER, 143 EQ_PRESET_ENUM, 144 SMART_VOLUME_ENUM, 145 MIC_BOOST_ENUM, 146 AE5_HEADPHONE_GAIN_ENUM, 147 AE5_SOUND_FILTER_ENUM, 148 ZXR_HEADPHONE_GAIN, 149 SPEAKER_CHANNEL_CFG_ENUM, 150 SPEAKER_FULL_RANGE_FRONT, 151 SPEAKER_FULL_RANGE_REAR, 152 BASS_REDIRECTION, 153 BASS_REDIRECTION_XOVER, 154 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID) 155 }; 156 157 /* Effects values size*/ 158 #define EFFECT_VALS_MAX_COUNT 12 159 160 /* 161 * Default values for the effect slider controls, they are in order of their 162 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then 163 * X-bass. 164 */ 165 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50}; 166 /* Amount of effect level sliders for ca0132_alt controls. */ 167 #define EFFECT_LEVEL_SLIDERS 5 168 169 /* Latency introduced by DSP blocks in milliseconds. */ 170 #define DSP_CAPTURE_INIT_LATENCY 0 171 #define DSP_CRYSTAL_VOICE_LATENCY 124 172 #define DSP_PLAYBACK_INIT_LATENCY 13 173 #define DSP_PLAY_ENHANCEMENT_LATENCY 30 174 #define DSP_SPEAKER_OUT_LATENCY 7 175 176 struct ct_effect { 177 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 178 hda_nid_t nid; 179 int mid; /*effect module ID*/ 180 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/ 181 int direct; /* 0:output; 1:input*/ 182 int params; /* number of default non-on/off params */ 183 /*effect default values, 1st is on/off. */ 184 unsigned int def_vals[EFFECT_VALS_MAX_COUNT]; 185 }; 186 187 #define EFX_DIR_OUT 0 188 #define EFX_DIR_IN 1 189 190 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = { 191 { .name = "Surround", 192 .nid = SURROUND, 193 .mid = 0x96, 194 .reqs = {0, 1}, 195 .direct = EFX_DIR_OUT, 196 .params = 1, 197 .def_vals = {0x3F800000, 0x3F2B851F} 198 }, 199 { .name = "Crystalizer", 200 .nid = CRYSTALIZER, 201 .mid = 0x96, 202 .reqs = {7, 8}, 203 .direct = EFX_DIR_OUT, 204 .params = 1, 205 .def_vals = {0x3F800000, 0x3F266666} 206 }, 207 { .name = "Dialog Plus", 208 .nid = DIALOG_PLUS, 209 .mid = 0x96, 210 .reqs = {2, 3}, 211 .direct = EFX_DIR_OUT, 212 .params = 1, 213 .def_vals = {0x00000000, 0x3F000000} 214 }, 215 { .name = "Smart Volume", 216 .nid = SMART_VOLUME, 217 .mid = 0x96, 218 .reqs = {4, 5, 6}, 219 .direct = EFX_DIR_OUT, 220 .params = 2, 221 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000} 222 }, 223 { .name = "X-Bass", 224 .nid = X_BASS, 225 .mid = 0x96, 226 .reqs = {24, 23, 25}, 227 .direct = EFX_DIR_OUT, 228 .params = 2, 229 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000} 230 }, 231 { .name = "Equalizer", 232 .nid = EQUALIZER, 233 .mid = 0x96, 234 .reqs = {9, 10, 11, 12, 13, 14, 235 15, 16, 17, 18, 19, 20}, 236 .direct = EFX_DIR_OUT, 237 .params = 11, 238 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000, 239 0x00000000, 0x00000000, 0x00000000, 0x00000000, 240 0x00000000, 0x00000000, 0x00000000, 0x00000000} 241 }, 242 { .name = "Echo Cancellation", 243 .nid = ECHO_CANCELLATION, 244 .mid = 0x95, 245 .reqs = {0, 1, 2, 3}, 246 .direct = EFX_DIR_IN, 247 .params = 3, 248 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000} 249 }, 250 { .name = "Voice Focus", 251 .nid = VOICE_FOCUS, 252 .mid = 0x95, 253 .reqs = {6, 7, 8, 9}, 254 .direct = EFX_DIR_IN, 255 .params = 3, 256 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000} 257 }, 258 { .name = "Mic SVM", 259 .nid = MIC_SVM, 260 .mid = 0x95, 261 .reqs = {44, 45}, 262 .direct = EFX_DIR_IN, 263 .params = 1, 264 .def_vals = {0x00000000, 0x3F3D70A4} 265 }, 266 { .name = "Noise Reduction", 267 .nid = NOISE_REDUCTION, 268 .mid = 0x95, 269 .reqs = {4, 5}, 270 .direct = EFX_DIR_IN, 271 .params = 1, 272 .def_vals = {0x3F800000, 0x3F000000} 273 }, 274 { .name = "VoiceFX", 275 .nid = VOICEFX, 276 .mid = 0x95, 277 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}, 278 .direct = EFX_DIR_IN, 279 .params = 8, 280 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000, 281 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000, 282 0x00000000} 283 } 284 }; 285 286 /* Tuning controls */ 287 #ifdef ENABLE_TUNING_CONTROLS 288 289 enum { 290 #define TUNING_CTL_START_NID 0xC0 291 WEDGE_ANGLE = TUNING_CTL_START_NID, 292 SVM_LEVEL, 293 EQUALIZER_BAND_0, 294 EQUALIZER_BAND_1, 295 EQUALIZER_BAND_2, 296 EQUALIZER_BAND_3, 297 EQUALIZER_BAND_4, 298 EQUALIZER_BAND_5, 299 EQUALIZER_BAND_6, 300 EQUALIZER_BAND_7, 301 EQUALIZER_BAND_8, 302 EQUALIZER_BAND_9, 303 TUNING_CTL_END_NID 304 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID) 305 }; 306 307 struct ct_tuning_ctl { 308 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 309 hda_nid_t parent_nid; 310 hda_nid_t nid; 311 int mid; /*effect module ID*/ 312 int req; /*effect module request*/ 313 int direct; /* 0:output; 1:input*/ 314 unsigned int def_val;/*effect default values*/ 315 }; 316 317 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = { 318 { .name = "Wedge Angle", 319 .parent_nid = VOICE_FOCUS, 320 .nid = WEDGE_ANGLE, 321 .mid = 0x95, 322 .req = 8, 323 .direct = EFX_DIR_IN, 324 .def_val = 0x41F00000 325 }, 326 { .name = "SVM Level", 327 .parent_nid = MIC_SVM, 328 .nid = SVM_LEVEL, 329 .mid = 0x95, 330 .req = 45, 331 .direct = EFX_DIR_IN, 332 .def_val = 0x3F3D70A4 333 }, 334 { .name = "EQ Band0", 335 .parent_nid = EQUALIZER, 336 .nid = EQUALIZER_BAND_0, 337 .mid = 0x96, 338 .req = 11, 339 .direct = EFX_DIR_OUT, 340 .def_val = 0x00000000 341 }, 342 { .name = "EQ Band1", 343 .parent_nid = EQUALIZER, 344 .nid = EQUALIZER_BAND_1, 345 .mid = 0x96, 346 .req = 12, 347 .direct = EFX_DIR_OUT, 348 .def_val = 0x00000000 349 }, 350 { .name = "EQ Band2", 351 .parent_nid = EQUALIZER, 352 .nid = EQUALIZER_BAND_2, 353 .mid = 0x96, 354 .req = 13, 355 .direct = EFX_DIR_OUT, 356 .def_val = 0x00000000 357 }, 358 { .name = "EQ Band3", 359 .parent_nid = EQUALIZER, 360 .nid = EQUALIZER_BAND_3, 361 .mid = 0x96, 362 .req = 14, 363 .direct = EFX_DIR_OUT, 364 .def_val = 0x00000000 365 }, 366 { .name = "EQ Band4", 367 .parent_nid = EQUALIZER, 368 .nid = EQUALIZER_BAND_4, 369 .mid = 0x96, 370 .req = 15, 371 .direct = EFX_DIR_OUT, 372 .def_val = 0x00000000 373 }, 374 { .name = "EQ Band5", 375 .parent_nid = EQUALIZER, 376 .nid = EQUALIZER_BAND_5, 377 .mid = 0x96, 378 .req = 16, 379 .direct = EFX_DIR_OUT, 380 .def_val = 0x00000000 381 }, 382 { .name = "EQ Band6", 383 .parent_nid = EQUALIZER, 384 .nid = EQUALIZER_BAND_6, 385 .mid = 0x96, 386 .req = 17, 387 .direct = EFX_DIR_OUT, 388 .def_val = 0x00000000 389 }, 390 { .name = "EQ Band7", 391 .parent_nid = EQUALIZER, 392 .nid = EQUALIZER_BAND_7, 393 .mid = 0x96, 394 .req = 18, 395 .direct = EFX_DIR_OUT, 396 .def_val = 0x00000000 397 }, 398 { .name = "EQ Band8", 399 .parent_nid = EQUALIZER, 400 .nid = EQUALIZER_BAND_8, 401 .mid = 0x96, 402 .req = 19, 403 .direct = EFX_DIR_OUT, 404 .def_val = 0x00000000 405 }, 406 { .name = "EQ Band9", 407 .parent_nid = EQUALIZER, 408 .nid = EQUALIZER_BAND_9, 409 .mid = 0x96, 410 .req = 20, 411 .direct = EFX_DIR_OUT, 412 .def_val = 0x00000000 413 } 414 }; 415 #endif 416 417 /* Voice FX Presets */ 418 #define VOICEFX_MAX_PARAM_COUNT 9 419 420 struct ct_voicefx { 421 char *name; 422 hda_nid_t nid; 423 int mid; 424 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/ 425 }; 426 427 struct ct_voicefx_preset { 428 char *name; /*preset name*/ 429 unsigned int vals[VOICEFX_MAX_PARAM_COUNT]; 430 }; 431 432 static const struct ct_voicefx ca0132_voicefx = { 433 .name = "VoiceFX Capture Switch", 434 .nid = VOICEFX, 435 .mid = 0x95, 436 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18} 437 }; 438 439 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = { 440 { .name = "Neutral", 441 .vals = { 0x00000000, 0x43C80000, 0x44AF0000, 442 0x44FA0000, 0x3F800000, 0x3F800000, 443 0x3F800000, 0x00000000, 0x00000000 } 444 }, 445 { .name = "Female2Male", 446 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 447 0x44FA0000, 0x3F19999A, 0x3F866666, 448 0x3F800000, 0x00000000, 0x00000000 } 449 }, 450 { .name = "Male2Female", 451 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 452 0x450AC000, 0x4017AE14, 0x3F6B851F, 453 0x3F800000, 0x00000000, 0x00000000 } 454 }, 455 { .name = "ScrappyKid", 456 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 457 0x44FA0000, 0x40400000, 0x3F28F5C3, 458 0x3F800000, 0x00000000, 0x00000000 } 459 }, 460 { .name = "Elderly", 461 .vals = { 0x3F800000, 0x44324000, 0x44BB8000, 462 0x44E10000, 0x3FB33333, 0x3FB9999A, 463 0x3F800000, 0x3E3A2E43, 0x00000000 } 464 }, 465 { .name = "Orc", 466 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000, 467 0x45098000, 0x3F266666, 0x3FC00000, 468 0x3F800000, 0x00000000, 0x00000000 } 469 }, 470 { .name = "Elf", 471 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000, 472 0x45193000, 0x3F8E147B, 0x3F75C28F, 473 0x3F800000, 0x00000000, 0x00000000 } 474 }, 475 { .name = "Dwarf", 476 .vals = { 0x3F800000, 0x43930000, 0x44BEE000, 477 0x45007000, 0x3F451EB8, 0x3F7851EC, 478 0x3F800000, 0x00000000, 0x00000000 } 479 }, 480 { .name = "AlienBrute", 481 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF, 482 0x451F6000, 0x3F266666, 0x3FA7D945, 483 0x3F800000, 0x3CF5C28F, 0x00000000 } 484 }, 485 { .name = "Robot", 486 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 487 0x44FA0000, 0x3FB2718B, 0x3F800000, 488 0xBC07010E, 0x00000000, 0x00000000 } 489 }, 490 { .name = "Marine", 491 .vals = { 0x3F800000, 0x43C20000, 0x44906000, 492 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71, 493 0x3F0A3D71, 0x00000000, 0x00000000 } 494 }, 495 { .name = "Emo", 496 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 497 0x44FA0000, 0x3F800000, 0x3F800000, 498 0x3E4CCCCD, 0x00000000, 0x00000000 } 499 }, 500 { .name = "DeepVoice", 501 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF, 502 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA, 503 0x3F800000, 0x00000000, 0x00000000 } 504 }, 505 { .name = "Munchkin", 506 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 507 0x44FA0000, 0x3F800000, 0x3F1A043C, 508 0x3F800000, 0x00000000, 0x00000000 } 509 } 510 }; 511 512 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */ 513 514 #define EQ_PRESET_MAX_PARAM_COUNT 11 515 516 struct ct_eq { 517 char *name; 518 hda_nid_t nid; 519 int mid; 520 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/ 521 }; 522 523 struct ct_eq_preset { 524 char *name; /*preset name*/ 525 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT]; 526 }; 527 528 static const struct ct_eq ca0132_alt_eq_enum = { 529 .name = "FX: Equalizer Preset Switch", 530 .nid = EQ_PRESET_ENUM, 531 .mid = 0x96, 532 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20} 533 }; 534 535 536 static const struct ct_eq_preset ca0132_alt_eq_presets[] = { 537 { .name = "Flat", 538 .vals = { 0x00000000, 0x00000000, 0x00000000, 539 0x00000000, 0x00000000, 0x00000000, 540 0x00000000, 0x00000000, 0x00000000, 541 0x00000000, 0x00000000 } 542 }, 543 { .name = "Acoustic", 544 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD, 545 0x40000000, 0x00000000, 0x00000000, 546 0x00000000, 0x00000000, 0x40000000, 547 0x40000000, 0x40000000 } 548 }, 549 { .name = "Classical", 550 .vals = { 0x00000000, 0x00000000, 0x40C00000, 551 0x40C00000, 0x40466666, 0x00000000, 552 0x00000000, 0x00000000, 0x00000000, 553 0x40466666, 0x40466666 } 554 }, 555 { .name = "Country", 556 .vals = { 0x00000000, 0xBF99999A, 0x00000000, 557 0x3FA66666, 0x3FA66666, 0x3F8CCCCD, 558 0x00000000, 0x00000000, 0x40000000, 559 0x40466666, 0x40800000 } 560 }, 561 { .name = "Dance", 562 .vals = { 0x00000000, 0xBF99999A, 0x40000000, 563 0x40466666, 0x40866666, 0xBF99999A, 564 0xBF99999A, 0x00000000, 0x00000000, 565 0x40800000, 0x40800000 } 566 }, 567 { .name = "Jazz", 568 .vals = { 0x00000000, 0x00000000, 0x00000000, 569 0x3F8CCCCD, 0x40800000, 0x40800000, 570 0x40800000, 0x00000000, 0x3F8CCCCD, 571 0x40466666, 0x40466666 } 572 }, 573 { .name = "New Age", 574 .vals = { 0x00000000, 0x00000000, 0x40000000, 575 0x40000000, 0x00000000, 0x00000000, 576 0x00000000, 0x3F8CCCCD, 0x40000000, 577 0x40000000, 0x40000000 } 578 }, 579 { .name = "Pop", 580 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000, 581 0x40000000, 0x40000000, 0x00000000, 582 0xBF99999A, 0xBF99999A, 0x00000000, 583 0x40466666, 0x40C00000 } 584 }, 585 { .name = "Rock", 586 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A, 587 0x3F8CCCCD, 0x40000000, 0xBF99999A, 588 0xBF99999A, 0x00000000, 0x00000000, 589 0x40800000, 0x40800000 } 590 }, 591 { .name = "Vocal", 592 .vals = { 0x00000000, 0xC0000000, 0xBF99999A, 593 0xBF99999A, 0x00000000, 0x40466666, 594 0x40800000, 0x40466666, 0x00000000, 595 0x00000000, 0x3F8CCCCD } 596 } 597 }; 598 599 /* 600 * DSP reqs for handling full-range speakers/bass redirection. If a speaker is 601 * set as not being full range, and bass redirection is enabled, all 602 * frequencies below the crossover frequency are redirected to the LFE 603 * channel. If the surround configuration has no LFE channel, this can't be 604 * enabled. X-Bass must be disabled when using these. 605 */ 606 enum speaker_range_reqs { 607 SPEAKER_BASS_REDIRECT = 0x15, 608 SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16, 609 /* Between 0x16-0x1a are the X-Bass reqs. */ 610 SPEAKER_FULL_RANGE_FRONT_L_R = 0x1a, 611 SPEAKER_FULL_RANGE_CENTER_LFE = 0x1b, 612 SPEAKER_FULL_RANGE_REAR_L_R = 0x1c, 613 SPEAKER_FULL_RANGE_SURROUND_L_R = 0x1d, 614 SPEAKER_BASS_REDIRECT_SUB_GAIN = 0x1e, 615 }; 616 617 /* 618 * Definitions for the DSP req's to handle speaker tuning. These all belong to 619 * module ID 0x96, the output effects module. 620 */ 621 enum speaker_tuning_reqs { 622 /* 623 * Currently, this value is always set to 0.0f. However, on Windows, 624 * when selecting certain headphone profiles on the new Sound Blaster 625 * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is 626 * sent. This gets the speaker EQ address area, which is then used to 627 * send over (presumably) an equalizer profile for the specific 628 * headphone setup. It is sent using the same method the DSP 629 * firmware is uploaded with, which I believe is why the 'ctspeq.bin' 630 * file exists in linux firmware tree but goes unused. It would also 631 * explain why the QUERY_SPEAKER_EQ_ADDRESS req is defined but unused. 632 * Once this profile is sent over, SPEAKER_TUNING_USE_SPEAKER_EQ is 633 * set to 1.0f. 634 */ 635 SPEAKER_TUNING_USE_SPEAKER_EQ = 0x1f, 636 SPEAKER_TUNING_ENABLE_CENTER_EQ = 0x20, 637 SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL = 0x21, 638 SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL = 0x22, 639 SPEAKER_TUNING_CENTER_VOL_LEVEL = 0x23, 640 SPEAKER_TUNING_LFE_VOL_LEVEL = 0x24, 641 SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL = 0x25, 642 SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL = 0x26, 643 SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL = 0x27, 644 SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28, 645 /* 646 * Inversion is used when setting headphone virtualization to line 647 * out. Not sure why this is, but it's the only place it's ever used. 648 */ 649 SPEAKER_TUNING_FRONT_LEFT_INVERT = 0x29, 650 SPEAKER_TUNING_FRONT_RIGHT_INVERT = 0x2a, 651 SPEAKER_TUNING_CENTER_INVERT = 0x2b, 652 SPEAKER_TUNING_LFE_INVERT = 0x2c, 653 SPEAKER_TUNING_REAR_LEFT_INVERT = 0x2d, 654 SPEAKER_TUNING_REAR_RIGHT_INVERT = 0x2e, 655 SPEAKER_TUNING_SURROUND_LEFT_INVERT = 0x2f, 656 SPEAKER_TUNING_SURROUND_RIGHT_INVERT = 0x30, 657 /* Delay is used when setting surround speaker distance in Windows. */ 658 SPEAKER_TUNING_FRONT_LEFT_DELAY = 0x31, 659 SPEAKER_TUNING_FRONT_RIGHT_DELAY = 0x32, 660 SPEAKER_TUNING_CENTER_DELAY = 0x33, 661 SPEAKER_TUNING_LFE_DELAY = 0x34, 662 SPEAKER_TUNING_REAR_LEFT_DELAY = 0x35, 663 SPEAKER_TUNING_REAR_RIGHT_DELAY = 0x36, 664 SPEAKER_TUNING_SURROUND_LEFT_DELAY = 0x37, 665 SPEAKER_TUNING_SURROUND_RIGHT_DELAY = 0x38, 666 /* Of these two, only mute seems to ever be used. */ 667 SPEAKER_TUNING_MAIN_VOLUME = 0x39, 668 SPEAKER_TUNING_MUTE = 0x3a, 669 }; 670 671 /* Surround output channel count configuration structures. */ 672 #define SPEAKER_CHANNEL_CFG_COUNT 5 673 enum { 674 SPEAKER_CHANNELS_2_0, 675 SPEAKER_CHANNELS_2_1, 676 SPEAKER_CHANNELS_4_0, 677 SPEAKER_CHANNELS_4_1, 678 SPEAKER_CHANNELS_5_1, 679 }; 680 681 struct ca0132_alt_speaker_channel_cfg { 682 char *name; 683 unsigned int val; 684 }; 685 686 static const struct ca0132_alt_speaker_channel_cfg speaker_channel_cfgs[] = { 687 { .name = "2.0", 688 .val = FLOAT_ONE 689 }, 690 { .name = "2.1", 691 .val = FLOAT_TWO 692 }, 693 { .name = "4.0", 694 .val = FLOAT_FIVE 695 }, 696 { .name = "4.1", 697 .val = FLOAT_SIX 698 }, 699 { .name = "5.1", 700 .val = FLOAT_EIGHT 701 } 702 }; 703 704 /* 705 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume, 706 * and I don't know what the third req is, but it's always zero. I assume it's 707 * some sort of update or set command to tell the DSP there's new volume info. 708 */ 709 #define DSP_VOL_OUT 0 710 #define DSP_VOL_IN 1 711 712 struct ct_dsp_volume_ctl { 713 hda_nid_t vnid; 714 int mid; /* module ID*/ 715 unsigned int reqs[3]; /* scp req ID */ 716 }; 717 718 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = { 719 { .vnid = VNID_SPK, 720 .mid = 0x32, 721 .reqs = {3, 4, 2} 722 }, 723 { .vnid = VNID_MIC, 724 .mid = 0x37, 725 .reqs = {2, 3, 1} 726 } 727 }; 728 729 /* Values for ca0113_mmio_command_set for selecting output. */ 730 #define AE_CA0113_OUT_SET_COMMANDS 6 731 struct ae_ca0113_output_set { 732 unsigned int group[AE_CA0113_OUT_SET_COMMANDS]; 733 unsigned int target[AE_CA0113_OUT_SET_COMMANDS]; 734 unsigned int vals[NUM_OF_OUTPUTS][AE_CA0113_OUT_SET_COMMANDS]; 735 }; 736 737 static const struct ae_ca0113_output_set ae5_ca0113_output_presets = { 738 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 739 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 740 /* Speakers. */ 741 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }, 742 /* Headphones. */ 743 { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } }, 744 }; 745 746 static const struct ae_ca0113_output_set ae7_ca0113_output_presets = { 747 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 748 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 749 /* Speakers. */ 750 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }, 751 /* Headphones. */ 752 { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } }, 753 }; 754 755 /* ae5 ca0113 command sequences to set headphone gain levels. */ 756 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4 757 struct ae5_headphone_gain_set { 758 char *name; 759 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS]; 760 }; 761 762 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = { 763 { .name = "Low (16-31", 764 .vals = { 0xff, 0x2c, 0xf5, 0x32 } 765 }, 766 { .name = "Medium (32-149", 767 .vals = { 0x38, 0xa8, 0x3e, 0x4c } 768 }, 769 { .name = "High (150-600", 770 .vals = { 0xff, 0xff, 0xff, 0x7f } 771 } 772 }; 773 774 struct ae5_filter_set { 775 char *name; 776 unsigned int val; 777 }; 778 779 static const struct ae5_filter_set ae5_filter_presets[] = { 780 { .name = "Slow Roll Off", 781 .val = 0xa0 782 }, 783 { .name = "Minimum Phase", 784 .val = 0xc0 785 }, 786 { .name = "Fast Roll Off", 787 .val = 0x80 788 } 789 }; 790 791 enum hda_cmd_vendor_io { 792 /* for DspIO node */ 793 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000, 794 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100, 795 796 VENDOR_DSPIO_STATUS = 0xF01, 797 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702, 798 VENDOR_DSPIO_SCP_READ_DATA = 0xF02, 799 VENDOR_DSPIO_DSP_INIT = 0x703, 800 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704, 801 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04, 802 803 /* for ChipIO node */ 804 VENDOR_CHIPIO_ADDRESS_LOW = 0x000, 805 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100, 806 VENDOR_CHIPIO_STREAM_FORMAT = 0x200, 807 VENDOR_CHIPIO_DATA_LOW = 0x300, 808 VENDOR_CHIPIO_DATA_HIGH = 0x400, 809 810 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500, 811 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00, 812 813 VENDOR_CHIPIO_GET_PARAMETER = 0xF00, 814 VENDOR_CHIPIO_STATUS = 0xF01, 815 VENDOR_CHIPIO_HIC_POST_READ = 0x702, 816 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03, 817 818 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707, 819 VENDOR_CHIPIO_8051_DATA_READ = 0xF07, 820 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08, 821 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709, 822 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09, 823 824 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A, 825 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A, 826 827 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C, 828 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C, 829 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D, 830 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E, 831 VENDOR_CHIPIO_FLAG_SET = 0x70F, 832 VENDOR_CHIPIO_FLAGS_GET = 0xF0F, 833 VENDOR_CHIPIO_PARAM_SET = 0x710, 834 VENDOR_CHIPIO_PARAM_GET = 0xF10, 835 836 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711, 837 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712, 838 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12, 839 VENDOR_CHIPIO_PORT_FREE_SET = 0x713, 840 841 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17, 842 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717, 843 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18, 844 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718, 845 846 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788, 847 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88, 848 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789, 849 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89, 850 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A, 851 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A, 852 853 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D 854 }; 855 856 /* 857 * Control flag IDs 858 */ 859 enum control_flag_id { 860 /* Connection manager stream setup is bypassed/enabled */ 861 CONTROL_FLAG_C_MGR = 0, 862 /* DSP DMA is bypassed/enabled */ 863 CONTROL_FLAG_DMA = 1, 864 /* 8051 'idle' mode is disabled/enabled */ 865 CONTROL_FLAG_IDLE_ENABLE = 2, 866 /* Tracker for the SPDIF-in path is bypassed/enabled */ 867 CONTROL_FLAG_TRACKER = 3, 868 /* DigitalOut to Spdif2Out connection is disabled/enabled */ 869 CONTROL_FLAG_SPDIF2OUT = 4, 870 /* Digital Microphone is disabled/enabled */ 871 CONTROL_FLAG_DMIC = 5, 872 /* ADC_B rate is 48 kHz/96 kHz */ 873 CONTROL_FLAG_ADC_B_96KHZ = 6, 874 /* ADC_C rate is 48 kHz/96 kHz */ 875 CONTROL_FLAG_ADC_C_96KHZ = 7, 876 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */ 877 CONTROL_FLAG_DAC_96KHZ = 8, 878 /* DSP rate is 48 kHz/96 kHz */ 879 CONTROL_FLAG_DSP_96KHZ = 9, 880 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */ 881 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10, 882 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */ 883 CONTROL_FLAG_SRC_RATE_96KHZ = 11, 884 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */ 885 CONTROL_FLAG_DECODE_LOOP = 12, 886 /* De-emphasis filter on DAC-1 disabled/enabled */ 887 CONTROL_FLAG_DAC1_DEEMPHASIS = 13, 888 /* De-emphasis filter on DAC-2 disabled/enabled */ 889 CONTROL_FLAG_DAC2_DEEMPHASIS = 14, 890 /* De-emphasis filter on DAC-3 disabled/enabled */ 891 CONTROL_FLAG_DAC3_DEEMPHASIS = 15, 892 /* High-pass filter on ADC_B disabled/enabled */ 893 CONTROL_FLAG_ADC_B_HIGH_PASS = 16, 894 /* High-pass filter on ADC_C disabled/enabled */ 895 CONTROL_FLAG_ADC_C_HIGH_PASS = 17, 896 /* Common mode on Port_A disabled/enabled */ 897 CONTROL_FLAG_PORT_A_COMMON_MODE = 18, 898 /* Common mode on Port_D disabled/enabled */ 899 CONTROL_FLAG_PORT_D_COMMON_MODE = 19, 900 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */ 901 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20, 902 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */ 903 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21, 904 /* ASI rate is 48kHz/96kHz */ 905 CONTROL_FLAG_ASI_96KHZ = 22, 906 /* DAC power settings able to control attached ports no/yes */ 907 CONTROL_FLAG_DACS_CONTROL_PORTS = 23, 908 /* Clock Stop OK reporting is disabled/enabled */ 909 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24, 910 /* Number of control flags */ 911 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1) 912 }; 913 914 /* 915 * Control parameter IDs 916 */ 917 enum control_param_id { 918 /* 0: None, 1: Mic1In*/ 919 CONTROL_PARAM_VIP_SOURCE = 1, 920 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */ 921 CONTROL_PARAM_SPDIF1_SOURCE = 2, 922 /* Port A output stage gain setting to use when 16 Ohm output 923 * impedance is selected*/ 924 CONTROL_PARAM_PORTA_160OHM_GAIN = 8, 925 /* Port D output stage gain setting to use when 16 Ohm output 926 * impedance is selected*/ 927 CONTROL_PARAM_PORTD_160OHM_GAIN = 10, 928 929 /* 930 * This control param name was found in the 8051 memory, and makes 931 * sense given the fact the AE-5 uses it and has the ASI flag set. 932 */ 933 CONTROL_PARAM_ASI = 23, 934 935 /* Stream Control */ 936 937 /* Select stream with the given ID */ 938 CONTROL_PARAM_STREAM_ID = 24, 939 /* Source connection point for the selected stream */ 940 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25, 941 /* Destination connection point for the selected stream */ 942 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26, 943 /* Number of audio channels in the selected stream */ 944 CONTROL_PARAM_STREAMS_CHANNELS = 27, 945 /*Enable control for the selected stream */ 946 CONTROL_PARAM_STREAM_CONTROL = 28, 947 948 /* Connection Point Control */ 949 950 /* Select connection point with the given ID */ 951 CONTROL_PARAM_CONN_POINT_ID = 29, 952 /* Connection point sample rate */ 953 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30, 954 955 /* Node Control */ 956 957 /* Select HDA node with the given ID */ 958 CONTROL_PARAM_NODE_ID = 31 959 }; 960 961 /* 962 * Dsp Io Status codes 963 */ 964 enum hda_vendor_status_dspio { 965 /* Success */ 966 VENDOR_STATUS_DSPIO_OK = 0x00, 967 /* Busy, unable to accept new command, the host must retry */ 968 VENDOR_STATUS_DSPIO_BUSY = 0x01, 969 /* SCP command queue is full */ 970 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02, 971 /* SCP response queue is empty */ 972 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03 973 }; 974 975 /* 976 * Chip Io Status codes 977 */ 978 enum hda_vendor_status_chipio { 979 /* Success */ 980 VENDOR_STATUS_CHIPIO_OK = 0x00, 981 /* Busy, unable to accept new command, the host must retry */ 982 VENDOR_STATUS_CHIPIO_BUSY = 0x01 983 }; 984 985 /* 986 * CA0132 sample rate 987 */ 988 enum ca0132_sample_rate { 989 SR_6_000 = 0x00, 990 SR_8_000 = 0x01, 991 SR_9_600 = 0x02, 992 SR_11_025 = 0x03, 993 SR_16_000 = 0x04, 994 SR_22_050 = 0x05, 995 SR_24_000 = 0x06, 996 SR_32_000 = 0x07, 997 SR_44_100 = 0x08, 998 SR_48_000 = 0x09, 999 SR_88_200 = 0x0A, 1000 SR_96_000 = 0x0B, 1001 SR_144_000 = 0x0C, 1002 SR_176_400 = 0x0D, 1003 SR_192_000 = 0x0E, 1004 SR_384_000 = 0x0F, 1005 1006 SR_COUNT = 0x10, 1007 1008 SR_RATE_UNKNOWN = 0x1F 1009 }; 1010 1011 enum dsp_download_state { 1012 DSP_DOWNLOAD_FAILED = -1, 1013 DSP_DOWNLOAD_INIT = 0, 1014 DSP_DOWNLOADING = 1, 1015 DSP_DOWNLOADED = 2 1016 }; 1017 1018 /* retrieve parameters from hda format */ 1019 #define get_hdafmt_chs(fmt) (fmt & 0xf) 1020 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7) 1021 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f) 1022 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1) 1023 1024 /* 1025 * CA0132 specific 1026 */ 1027 1028 struct ca0132_spec { 1029 const struct snd_kcontrol_new *mixers[5]; 1030 unsigned int num_mixers; 1031 const struct hda_verb *base_init_verbs; 1032 const struct hda_verb *base_exit_verbs; 1033 const struct hda_verb *chip_init_verbs; 1034 const struct hda_verb *desktop_init_verbs; 1035 struct hda_verb *spec_init_verbs; 1036 struct auto_pin_cfg autocfg; 1037 1038 /* Nodes configurations */ 1039 struct hda_multi_out multiout; 1040 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS]; 1041 hda_nid_t dacs[AUTO_CFG_MAX_OUTS]; 1042 unsigned int num_outputs; 1043 hda_nid_t input_pins[AUTO_PIN_LAST]; 1044 hda_nid_t adcs[AUTO_PIN_LAST]; 1045 hda_nid_t dig_out; 1046 hda_nid_t dig_in; 1047 unsigned int num_inputs; 1048 hda_nid_t shared_mic_nid; 1049 hda_nid_t shared_out_nid; 1050 hda_nid_t unsol_tag_hp; 1051 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */ 1052 hda_nid_t unsol_tag_amic1; 1053 1054 /* chip access */ 1055 struct mutex chipio_mutex; /* chip access mutex */ 1056 u32 curr_chip_addx; 1057 1058 /* DSP download related */ 1059 enum dsp_download_state dsp_state; 1060 unsigned int dsp_stream_id; 1061 unsigned int wait_scp; 1062 unsigned int wait_scp_header; 1063 unsigned int wait_num_data; 1064 unsigned int scp_resp_header; 1065 unsigned int scp_resp_data[4]; 1066 unsigned int scp_resp_count; 1067 bool startup_check_entered; 1068 bool dsp_reload; 1069 1070 /* mixer and effects related */ 1071 unsigned char dmic_ctl; 1072 int cur_out_type; 1073 int cur_mic_type; 1074 long vnode_lvol[VNODES_COUNT]; 1075 long vnode_rvol[VNODES_COUNT]; 1076 long vnode_lswitch[VNODES_COUNT]; 1077 long vnode_rswitch[VNODES_COUNT]; 1078 long effects_switch[EFFECTS_COUNT]; 1079 long voicefx_val; 1080 long cur_mic_boost; 1081 /* ca0132_alt control related values */ 1082 unsigned char in_enum_val; 1083 unsigned char out_enum_val; 1084 unsigned char channel_cfg_val; 1085 unsigned char speaker_range_val[2]; 1086 unsigned char mic_boost_enum_val; 1087 unsigned char smart_volume_setting; 1088 unsigned char bass_redirection_val; 1089 long bass_redirect_xover_freq; 1090 long fx_ctl_val[EFFECT_LEVEL_SLIDERS]; 1091 long xbass_xover_freq; 1092 long eq_preset_val; 1093 unsigned int tlv[4]; 1094 struct hda_vmaster_mute_hook vmaster_mute; 1095 /* AE-5 Control values */ 1096 unsigned char ae5_headphone_gain_val; 1097 unsigned char ae5_filter_val; 1098 /* ZxR Control Values */ 1099 unsigned char zxr_gain_set; 1100 1101 struct hda_codec *codec; 1102 struct delayed_work unsol_hp_work; 1103 int quirk; 1104 1105 #ifdef ENABLE_TUNING_CONTROLS 1106 long cur_ctl_vals[TUNING_CTLS_COUNT]; 1107 #endif 1108 /* 1109 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster 1110 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown 1111 * things. 1112 */ 1113 bool use_pci_mmio; 1114 void __iomem *mem_base; 1115 1116 /* 1117 * Whether or not to use the alt functions like alt_select_out, 1118 * alt_select_in, etc. Only used on desktop codecs for now, because of 1119 * surround sound support. 1120 */ 1121 bool use_alt_functions; 1122 1123 /* 1124 * Whether or not to use alt controls: volume effect sliders, EQ 1125 * presets, smart volume presets, and new control names with FX prefix. 1126 * Renames PlayEnhancement and CrystalVoice too. 1127 */ 1128 bool use_alt_controls; 1129 }; 1130 1131 /* 1132 * CA0132 quirks table 1133 */ 1134 enum { 1135 QUIRK_NONE, 1136 QUIRK_ALIENWARE, 1137 QUIRK_ALIENWARE_M17XR4, 1138 QUIRK_SBZ, 1139 QUIRK_ZXR, 1140 QUIRK_ZXR_DBPRO, 1141 QUIRK_R3DI, 1142 QUIRK_R3D, 1143 QUIRK_AE5, 1144 QUIRK_AE7, 1145 }; 1146 1147 #ifdef CONFIG_PCI 1148 #define ca0132_quirk(spec) ((spec)->quirk) 1149 #define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio) 1150 #define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions) 1151 #define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls) 1152 #else 1153 #define ca0132_quirk(spec) ({ (void)(spec); QUIRK_NONE; }) 1154 #define ca0132_use_alt_functions(spec) ({ (void)(spec); false; }) 1155 #define ca0132_use_pci_mmio(spec) ({ (void)(spec); false; }) 1156 #define ca0132_use_alt_controls(spec) ({ (void)(spec); false; }) 1157 #endif 1158 1159 static const struct hda_pintbl alienware_pincfgs[] = { 1160 { 0x0b, 0x90170110 }, /* Builtin Speaker */ 1161 { 0x0c, 0x411111f0 }, /* N/A */ 1162 { 0x0d, 0x411111f0 }, /* N/A */ 1163 { 0x0e, 0x411111f0 }, /* N/A */ 1164 { 0x0f, 0x0321101f }, /* HP */ 1165 { 0x10, 0x411111f0 }, /* Headset? disabled for now */ 1166 { 0x11, 0x03a11021 }, /* Mic */ 1167 { 0x12, 0xd5a30140 }, /* Builtin Mic */ 1168 { 0x13, 0x411111f0 }, /* N/A */ 1169 { 0x18, 0x411111f0 }, /* N/A */ 1170 {} 1171 }; 1172 1173 /* Sound Blaster Z pin configs taken from Windows Driver */ 1174 static const struct hda_pintbl sbz_pincfgs[] = { 1175 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1176 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1177 { 0x0d, 0x014510f0 }, /* Digital Out */ 1178 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1179 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */ 1180 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1181 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1182 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1183 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1184 { 0x18, 0x50d000f0 }, /* N/A */ 1185 {} 1186 }; 1187 1188 /* Sound Blaster ZxR pin configs taken from Windows Driver */ 1189 static const struct hda_pintbl zxr_pincfgs[] = { 1190 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */ 1191 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/ 1192 { 0x0d, 0x014510f0 }, /* Digital Out */ 1193 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/ 1194 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */ 1195 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */ 1196 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */ 1197 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */ 1198 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1199 { 0x18, 0x50d000f0 }, /* N/A */ 1200 {} 1201 }; 1202 1203 /* Recon3D pin configs taken from Windows Driver */ 1204 static const struct hda_pintbl r3d_pincfgs[] = { 1205 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1206 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1207 { 0x0d, 0x014510f0 }, /* Digital Out */ 1208 { 0x0e, 0x01c520f0 }, /* SPDIF In */ 1209 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1210 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1211 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1212 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1213 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1214 { 0x18, 0x50d000f0 }, /* N/A */ 1215 {} 1216 }; 1217 1218 /* Sound Blaster AE-5 pin configs taken from Windows Driver */ 1219 static const struct hda_pintbl ae5_pincfgs[] = { 1220 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1221 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1222 { 0x0d, 0x014510f0 }, /* Digital Out */ 1223 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1224 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */ 1225 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1226 { 0x11, 0x01a170ff }, /* Port B -- LineMicIn2 / Rear Headphone */ 1227 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1228 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1229 { 0x18, 0x50d000f0 }, /* N/A */ 1230 {} 1231 }; 1232 1233 /* Recon3D integrated pin configs taken from Windows Driver */ 1234 static const struct hda_pintbl r3di_pincfgs[] = { 1235 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1236 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1237 { 0x0d, 0x014510f0 }, /* Digital Out */ 1238 { 0x0e, 0x41c520f0 }, /* SPDIF In */ 1239 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1240 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1241 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1242 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1243 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1244 { 0x18, 0x500000f0 }, /* N/A */ 1245 {} 1246 }; 1247 1248 static const struct hda_pintbl ae7_pincfgs[] = { 1249 { 0x0b, 0x01017010 }, 1250 { 0x0c, 0x014510f0 }, 1251 { 0x0d, 0x414510f0 }, 1252 { 0x0e, 0x01c520f0 }, 1253 { 0x0f, 0x01017114 }, 1254 { 0x10, 0x01017011 }, 1255 { 0x11, 0x018170ff }, 1256 { 0x12, 0x01a170f0 }, 1257 { 0x13, 0x908700f0 }, 1258 { 0x18, 0x500000f0 }, 1259 {} 1260 }; 1261 1262 static const struct snd_pci_quirk ca0132_quirks[] = { 1263 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4), 1264 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE), 1265 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE), 1266 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE), 1267 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ), 1268 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ), 1269 SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ), 1270 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ), 1271 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI), 1272 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI), 1273 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI), 1274 SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI), 1275 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D), 1276 SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D), 1277 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5), 1278 SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7), 1279 {} 1280 }; 1281 1282 /* Output selection quirk info structures. */ 1283 #define MAX_QUIRK_MMIO_GPIO_SET_VALS 3 1284 #define MAX_QUIRK_SCP_SET_VALS 2 1285 struct ca0132_alt_out_set_info { 1286 unsigned int dac2port; /* ParamID 0x0d value. */ 1287 1288 bool has_hda_gpio; 1289 char hda_gpio_pin; 1290 char hda_gpio_set; 1291 1292 unsigned int mmio_gpio_count; 1293 char mmio_gpio_pin[MAX_QUIRK_MMIO_GPIO_SET_VALS]; 1294 char mmio_gpio_set[MAX_QUIRK_MMIO_GPIO_SET_VALS]; 1295 1296 unsigned int scp_cmds_count; 1297 unsigned int scp_cmd_mid[MAX_QUIRK_SCP_SET_VALS]; 1298 unsigned int scp_cmd_req[MAX_QUIRK_SCP_SET_VALS]; 1299 unsigned int scp_cmd_val[MAX_QUIRK_SCP_SET_VALS]; 1300 1301 bool has_chipio_write; 1302 unsigned int chipio_write_addr; 1303 unsigned int chipio_write_data; 1304 }; 1305 1306 struct ca0132_alt_out_set_quirk_data { 1307 int quirk_id; 1308 1309 bool has_headphone_gain; 1310 bool is_ae_series; 1311 1312 struct ca0132_alt_out_set_info out_set_info[NUM_OF_OUTPUTS]; 1313 }; 1314 1315 static const struct ca0132_alt_out_set_quirk_data quirk_out_set_data[] = { 1316 { .quirk_id = QUIRK_R3DI, 1317 .has_headphone_gain = false, 1318 .is_ae_series = false, 1319 .out_set_info = { 1320 /* Speakers. */ 1321 { .dac2port = 0x24, 1322 .has_hda_gpio = true, 1323 .hda_gpio_pin = 2, 1324 .hda_gpio_set = 1, 1325 .mmio_gpio_count = 0, 1326 .scp_cmds_count = 0, 1327 .has_chipio_write = false, 1328 }, 1329 /* Headphones. */ 1330 { .dac2port = 0x21, 1331 .has_hda_gpio = true, 1332 .hda_gpio_pin = 2, 1333 .hda_gpio_set = 0, 1334 .mmio_gpio_count = 0, 1335 .scp_cmds_count = 0, 1336 .has_chipio_write = false, 1337 } }, 1338 }, 1339 { .quirk_id = QUIRK_R3D, 1340 .has_headphone_gain = false, 1341 .is_ae_series = false, 1342 .out_set_info = { 1343 /* Speakers. */ 1344 { .dac2port = 0x24, 1345 .has_hda_gpio = false, 1346 .mmio_gpio_count = 1, 1347 .mmio_gpio_pin = { 1 }, 1348 .mmio_gpio_set = { 1 }, 1349 .scp_cmds_count = 0, 1350 .has_chipio_write = false, 1351 }, 1352 /* Headphones. */ 1353 { .dac2port = 0x21, 1354 .has_hda_gpio = false, 1355 .mmio_gpio_count = 1, 1356 .mmio_gpio_pin = { 1 }, 1357 .mmio_gpio_set = { 0 }, 1358 .scp_cmds_count = 0, 1359 .has_chipio_write = false, 1360 } }, 1361 }, 1362 { .quirk_id = QUIRK_SBZ, 1363 .has_headphone_gain = false, 1364 .is_ae_series = false, 1365 .out_set_info = { 1366 /* Speakers. */ 1367 { .dac2port = 0x18, 1368 .has_hda_gpio = false, 1369 .mmio_gpio_count = 3, 1370 .mmio_gpio_pin = { 7, 4, 1 }, 1371 .mmio_gpio_set = { 0, 1, 1 }, 1372 .scp_cmds_count = 0, 1373 .has_chipio_write = false, }, 1374 /* Headphones. */ 1375 { .dac2port = 0x12, 1376 .has_hda_gpio = false, 1377 .mmio_gpio_count = 3, 1378 .mmio_gpio_pin = { 7, 4, 1 }, 1379 .mmio_gpio_set = { 1, 1, 0 }, 1380 .scp_cmds_count = 0, 1381 .has_chipio_write = false, 1382 } }, 1383 }, 1384 { .quirk_id = QUIRK_ZXR, 1385 .has_headphone_gain = true, 1386 .is_ae_series = false, 1387 .out_set_info = { 1388 /* Speakers. */ 1389 { .dac2port = 0x24, 1390 .has_hda_gpio = false, 1391 .mmio_gpio_count = 3, 1392 .mmio_gpio_pin = { 2, 3, 5 }, 1393 .mmio_gpio_set = { 1, 1, 0 }, 1394 .scp_cmds_count = 0, 1395 .has_chipio_write = false, 1396 }, 1397 /* Headphones. */ 1398 { .dac2port = 0x21, 1399 .has_hda_gpio = false, 1400 .mmio_gpio_count = 3, 1401 .mmio_gpio_pin = { 2, 3, 5 }, 1402 .mmio_gpio_set = { 0, 1, 1 }, 1403 .scp_cmds_count = 0, 1404 .has_chipio_write = false, 1405 } }, 1406 }, 1407 { .quirk_id = QUIRK_AE5, 1408 .has_headphone_gain = true, 1409 .is_ae_series = true, 1410 .out_set_info = { 1411 /* Speakers. */ 1412 { .dac2port = 0xa4, 1413 .has_hda_gpio = false, 1414 .mmio_gpio_count = 0, 1415 .scp_cmds_count = 2, 1416 .scp_cmd_mid = { 0x96, 0x96 }, 1417 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1418 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1419 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO }, 1420 .has_chipio_write = true, 1421 .chipio_write_addr = 0x0018b03c, 1422 .chipio_write_data = 0x00000012 1423 }, 1424 /* Headphones. */ 1425 { .dac2port = 0xa1, 1426 .has_hda_gpio = false, 1427 .mmio_gpio_count = 0, 1428 .scp_cmds_count = 2, 1429 .scp_cmd_mid = { 0x96, 0x96 }, 1430 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1431 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1432 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE }, 1433 .has_chipio_write = true, 1434 .chipio_write_addr = 0x0018b03c, 1435 .chipio_write_data = 0x00000012 1436 } }, 1437 }, 1438 { .quirk_id = QUIRK_AE7, 1439 .has_headphone_gain = true, 1440 .is_ae_series = true, 1441 .out_set_info = { 1442 /* Speakers. */ 1443 { .dac2port = 0x58, 1444 .has_hda_gpio = false, 1445 .mmio_gpio_count = 1, 1446 .mmio_gpio_pin = { 0 }, 1447 .mmio_gpio_set = { 1 }, 1448 .scp_cmds_count = 2, 1449 .scp_cmd_mid = { 0x96, 0x96 }, 1450 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1451 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1452 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO }, 1453 .has_chipio_write = true, 1454 .chipio_write_addr = 0x0018b03c, 1455 .chipio_write_data = 0x00000000 1456 }, 1457 /* Headphones. */ 1458 { .dac2port = 0x58, 1459 .has_hda_gpio = false, 1460 .mmio_gpio_count = 1, 1461 .mmio_gpio_pin = { 0 }, 1462 .mmio_gpio_set = { 1 }, 1463 .scp_cmds_count = 2, 1464 .scp_cmd_mid = { 0x96, 0x96 }, 1465 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1466 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1467 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE }, 1468 .has_chipio_write = true, 1469 .chipio_write_addr = 0x0018b03c, 1470 .chipio_write_data = 0x00000010 1471 } }, 1472 } 1473 }; 1474 1475 /* 1476 * CA0132 codec access 1477 */ 1478 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid, 1479 unsigned int verb, unsigned int parm, unsigned int *res) 1480 { 1481 unsigned int response; 1482 response = snd_hda_codec_read(codec, nid, 0, verb, parm); 1483 *res = response; 1484 1485 return ((response == -1) ? -1 : 0); 1486 } 1487 1488 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid, 1489 unsigned short converter_format, unsigned int *res) 1490 { 1491 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT, 1492 converter_format & 0xffff, res); 1493 } 1494 1495 static int codec_set_converter_stream_channel(struct hda_codec *codec, 1496 hda_nid_t nid, unsigned char stream, 1497 unsigned char channel, unsigned int *res) 1498 { 1499 unsigned char converter_stream_channel = 0; 1500 1501 converter_stream_channel = (stream << 4) | (channel & 0x0f); 1502 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID, 1503 converter_stream_channel, res); 1504 } 1505 1506 /* Chip access helper function */ 1507 static int chipio_send(struct hda_codec *codec, 1508 unsigned int reg, 1509 unsigned int data) 1510 { 1511 unsigned int res; 1512 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1513 1514 /* send bits of data specified by reg */ 1515 do { 1516 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1517 reg, data); 1518 if (res == VENDOR_STATUS_CHIPIO_OK) 1519 return 0; 1520 msleep(20); 1521 } while (time_before(jiffies, timeout)); 1522 1523 return -EIO; 1524 } 1525 1526 /* 1527 * Write chip address through the vendor widget -- NOT protected by the Mutex! 1528 */ 1529 static int chipio_write_address(struct hda_codec *codec, 1530 unsigned int chip_addx) 1531 { 1532 struct ca0132_spec *spec = codec->spec; 1533 int res; 1534 1535 if (spec->curr_chip_addx == chip_addx) 1536 return 0; 1537 1538 /* send low 16 bits of the address */ 1539 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW, 1540 chip_addx & 0xffff); 1541 1542 if (res != -EIO) { 1543 /* send high 16 bits of the address */ 1544 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH, 1545 chip_addx >> 16); 1546 } 1547 1548 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx; 1549 1550 return res; 1551 } 1552 1553 /* 1554 * Write data through the vendor widget -- NOT protected by the Mutex! 1555 */ 1556 static int chipio_write_data(struct hda_codec *codec, unsigned int data) 1557 { 1558 struct ca0132_spec *spec = codec->spec; 1559 int res; 1560 1561 /* send low 16 bits of the data */ 1562 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff); 1563 1564 if (res != -EIO) { 1565 /* send high 16 bits of the data */ 1566 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH, 1567 data >> 16); 1568 } 1569 1570 /*If no error encountered, automatically increment the address 1571 as per chip behaviour*/ 1572 spec->curr_chip_addx = (res != -EIO) ? 1573 (spec->curr_chip_addx + 4) : ~0U; 1574 return res; 1575 } 1576 1577 /* 1578 * Write multiple data through the vendor widget -- NOT protected by the Mutex! 1579 */ 1580 static int chipio_write_data_multiple(struct hda_codec *codec, 1581 const u32 *data, 1582 unsigned int count) 1583 { 1584 int status = 0; 1585 1586 if (data == NULL) { 1587 codec_dbg(codec, "chipio_write_data null ptr\n"); 1588 return -EINVAL; 1589 } 1590 1591 while ((count-- != 0) && (status == 0)) 1592 status = chipio_write_data(codec, *data++); 1593 1594 return status; 1595 } 1596 1597 1598 /* 1599 * Read data through the vendor widget -- NOT protected by the Mutex! 1600 */ 1601 static int chipio_read_data(struct hda_codec *codec, unsigned int *data) 1602 { 1603 struct ca0132_spec *spec = codec->spec; 1604 int res; 1605 1606 /* post read */ 1607 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0); 1608 1609 if (res != -EIO) { 1610 /* read status */ 1611 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 1612 } 1613 1614 if (res != -EIO) { 1615 /* read data */ 1616 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1617 VENDOR_CHIPIO_HIC_READ_DATA, 1618 0); 1619 } 1620 1621 /*If no error encountered, automatically increment the address 1622 as per chip behaviour*/ 1623 spec->curr_chip_addx = (res != -EIO) ? 1624 (spec->curr_chip_addx + 4) : ~0U; 1625 return res; 1626 } 1627 1628 /* 1629 * Write given value to the given address through the chip I/O widget. 1630 * protected by the Mutex 1631 */ 1632 static int chipio_write(struct hda_codec *codec, 1633 unsigned int chip_addx, const unsigned int data) 1634 { 1635 struct ca0132_spec *spec = codec->spec; 1636 int err; 1637 1638 mutex_lock(&spec->chipio_mutex); 1639 1640 /* write the address, and if successful proceed to write data */ 1641 err = chipio_write_address(codec, chip_addx); 1642 if (err < 0) 1643 goto exit; 1644 1645 err = chipio_write_data(codec, data); 1646 if (err < 0) 1647 goto exit; 1648 1649 exit: 1650 mutex_unlock(&spec->chipio_mutex); 1651 return err; 1652 } 1653 1654 /* 1655 * Write given value to the given address through the chip I/O widget. 1656 * not protected by the Mutex 1657 */ 1658 static int chipio_write_no_mutex(struct hda_codec *codec, 1659 unsigned int chip_addx, const unsigned int data) 1660 { 1661 int err; 1662 1663 1664 /* write the address, and if successful proceed to write data */ 1665 err = chipio_write_address(codec, chip_addx); 1666 if (err < 0) 1667 goto exit; 1668 1669 err = chipio_write_data(codec, data); 1670 if (err < 0) 1671 goto exit; 1672 1673 exit: 1674 return err; 1675 } 1676 1677 /* 1678 * Write multiple values to the given address through the chip I/O widget. 1679 * protected by the Mutex 1680 */ 1681 static int chipio_write_multiple(struct hda_codec *codec, 1682 u32 chip_addx, 1683 const u32 *data, 1684 unsigned int count) 1685 { 1686 struct ca0132_spec *spec = codec->spec; 1687 int status; 1688 1689 mutex_lock(&spec->chipio_mutex); 1690 status = chipio_write_address(codec, chip_addx); 1691 if (status < 0) 1692 goto error; 1693 1694 status = chipio_write_data_multiple(codec, data, count); 1695 error: 1696 mutex_unlock(&spec->chipio_mutex); 1697 1698 return status; 1699 } 1700 1701 /* 1702 * Read the given address through the chip I/O widget 1703 * protected by the Mutex 1704 */ 1705 static int chipio_read(struct hda_codec *codec, 1706 unsigned int chip_addx, unsigned int *data) 1707 { 1708 struct ca0132_spec *spec = codec->spec; 1709 int err; 1710 1711 mutex_lock(&spec->chipio_mutex); 1712 1713 /* write the address, and if successful proceed to write data */ 1714 err = chipio_write_address(codec, chip_addx); 1715 if (err < 0) 1716 goto exit; 1717 1718 err = chipio_read_data(codec, data); 1719 if (err < 0) 1720 goto exit; 1721 1722 exit: 1723 mutex_unlock(&spec->chipio_mutex); 1724 return err; 1725 } 1726 1727 /* 1728 * Set chip control flags through the chip I/O widget. 1729 */ 1730 static void chipio_set_control_flag(struct hda_codec *codec, 1731 enum control_flag_id flag_id, 1732 bool flag_state) 1733 { 1734 unsigned int val; 1735 unsigned int flag_bit; 1736 1737 flag_bit = (flag_state ? 1 : 0); 1738 val = (flag_bit << 7) | (flag_id); 1739 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1740 VENDOR_CHIPIO_FLAG_SET, val); 1741 } 1742 1743 /* 1744 * Set chip parameters through the chip I/O widget. 1745 */ 1746 static void chipio_set_control_param(struct hda_codec *codec, 1747 enum control_param_id param_id, int param_val) 1748 { 1749 struct ca0132_spec *spec = codec->spec; 1750 int val; 1751 1752 if ((param_id < 32) && (param_val < 8)) { 1753 val = (param_val << 5) | (param_id); 1754 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1755 VENDOR_CHIPIO_PARAM_SET, val); 1756 } else { 1757 mutex_lock(&spec->chipio_mutex); 1758 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1759 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1760 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1761 param_id); 1762 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1763 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1764 param_val); 1765 } 1766 mutex_unlock(&spec->chipio_mutex); 1767 } 1768 } 1769 1770 /* 1771 * Set chip parameters through the chip I/O widget. NO MUTEX. 1772 */ 1773 static void chipio_set_control_param_no_mutex(struct hda_codec *codec, 1774 enum control_param_id param_id, int param_val) 1775 { 1776 int val; 1777 1778 if ((param_id < 32) && (param_val < 8)) { 1779 val = (param_val << 5) | (param_id); 1780 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1781 VENDOR_CHIPIO_PARAM_SET, val); 1782 } else { 1783 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1784 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1785 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1786 param_id); 1787 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1788 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1789 param_val); 1790 } 1791 } 1792 } 1793 /* 1794 * Connect stream to a source point, and then connect 1795 * that source point to a destination point. 1796 */ 1797 static void chipio_set_stream_source_dest(struct hda_codec *codec, 1798 int streamid, int source_point, int dest_point) 1799 { 1800 chipio_set_control_param_no_mutex(codec, 1801 CONTROL_PARAM_STREAM_ID, streamid); 1802 chipio_set_control_param_no_mutex(codec, 1803 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point); 1804 chipio_set_control_param_no_mutex(codec, 1805 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point); 1806 } 1807 1808 /* 1809 * Set number of channels in the selected stream. 1810 */ 1811 static void chipio_set_stream_channels(struct hda_codec *codec, 1812 int streamid, unsigned int channels) 1813 { 1814 chipio_set_control_param_no_mutex(codec, 1815 CONTROL_PARAM_STREAM_ID, streamid); 1816 chipio_set_control_param_no_mutex(codec, 1817 CONTROL_PARAM_STREAMS_CHANNELS, channels); 1818 } 1819 1820 /* 1821 * Enable/Disable audio stream. 1822 */ 1823 static void chipio_set_stream_control(struct hda_codec *codec, 1824 int streamid, int enable) 1825 { 1826 chipio_set_control_param_no_mutex(codec, 1827 CONTROL_PARAM_STREAM_ID, streamid); 1828 chipio_set_control_param_no_mutex(codec, 1829 CONTROL_PARAM_STREAM_CONTROL, enable); 1830 } 1831 1832 1833 /* 1834 * Set sampling rate of the connection point. NO MUTEX. 1835 */ 1836 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec, 1837 int connid, enum ca0132_sample_rate rate) 1838 { 1839 chipio_set_control_param_no_mutex(codec, 1840 CONTROL_PARAM_CONN_POINT_ID, connid); 1841 chipio_set_control_param_no_mutex(codec, 1842 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate); 1843 } 1844 1845 /* 1846 * Set sampling rate of the connection point. 1847 */ 1848 static void chipio_set_conn_rate(struct hda_codec *codec, 1849 int connid, enum ca0132_sample_rate rate) 1850 { 1851 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid); 1852 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, 1853 rate); 1854 } 1855 1856 /* 1857 * Writes to the 8051's internal address space directly instead of indirectly, 1858 * giving access to the special function registers located at addresses 1859 * 0x80-0xFF. 1860 */ 1861 static void chipio_8051_write_direct(struct hda_codec *codec, 1862 unsigned int addr, unsigned int data) 1863 { 1864 unsigned int verb; 1865 1866 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data; 1867 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr); 1868 } 1869 1870 /* 1871 * Enable clocks. 1872 */ 1873 static void chipio_enable_clocks(struct hda_codec *codec) 1874 { 1875 struct ca0132_spec *spec = codec->spec; 1876 1877 mutex_lock(&spec->chipio_mutex); 1878 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1879 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0); 1880 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1881 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); 1882 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1883 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5); 1884 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1885 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b); 1886 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1887 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6); 1888 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1889 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); 1890 mutex_unlock(&spec->chipio_mutex); 1891 } 1892 1893 /* 1894 * CA0132 DSP IO stuffs 1895 */ 1896 static int dspio_send(struct hda_codec *codec, unsigned int reg, 1897 unsigned int data) 1898 { 1899 int res; 1900 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1901 1902 /* send bits of data specified by reg to dsp */ 1903 do { 1904 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data); 1905 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY)) 1906 return res; 1907 msleep(20); 1908 } while (time_before(jiffies, timeout)); 1909 1910 return -EIO; 1911 } 1912 1913 /* 1914 * Wait for DSP to be ready for commands 1915 */ 1916 static void dspio_write_wait(struct hda_codec *codec) 1917 { 1918 int status; 1919 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1920 1921 do { 1922 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1923 VENDOR_DSPIO_STATUS, 0); 1924 if ((status == VENDOR_STATUS_DSPIO_OK) || 1925 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)) 1926 break; 1927 msleep(1); 1928 } while (time_before(jiffies, timeout)); 1929 } 1930 1931 /* 1932 * Write SCP data to DSP 1933 */ 1934 static int dspio_write(struct hda_codec *codec, unsigned int scp_data) 1935 { 1936 struct ca0132_spec *spec = codec->spec; 1937 int status; 1938 1939 dspio_write_wait(codec); 1940 1941 mutex_lock(&spec->chipio_mutex); 1942 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW, 1943 scp_data & 0xffff); 1944 if (status < 0) 1945 goto error; 1946 1947 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH, 1948 scp_data >> 16); 1949 if (status < 0) 1950 goto error; 1951 1952 /* OK, now check if the write itself has executed*/ 1953 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1954 VENDOR_DSPIO_STATUS, 0); 1955 error: 1956 mutex_unlock(&spec->chipio_mutex); 1957 1958 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ? 1959 -EIO : 0; 1960 } 1961 1962 /* 1963 * Write multiple SCP data to DSP 1964 */ 1965 static int dspio_write_multiple(struct hda_codec *codec, 1966 unsigned int *buffer, unsigned int size) 1967 { 1968 int status = 0; 1969 unsigned int count; 1970 1971 if (buffer == NULL) 1972 return -EINVAL; 1973 1974 count = 0; 1975 while (count < size) { 1976 status = dspio_write(codec, *buffer++); 1977 if (status != 0) 1978 break; 1979 count++; 1980 } 1981 1982 return status; 1983 } 1984 1985 static int dspio_read(struct hda_codec *codec, unsigned int *data) 1986 { 1987 int status; 1988 1989 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0); 1990 if (status == -EIO) 1991 return status; 1992 1993 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0); 1994 if (status == -EIO || 1995 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY) 1996 return -EIO; 1997 1998 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1999 VENDOR_DSPIO_SCP_READ_DATA, 0); 2000 2001 return 0; 2002 } 2003 2004 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer, 2005 unsigned int *buf_size, unsigned int size_count) 2006 { 2007 int status = 0; 2008 unsigned int size = *buf_size; 2009 unsigned int count; 2010 unsigned int skip_count; 2011 unsigned int dummy; 2012 2013 if (buffer == NULL) 2014 return -1; 2015 2016 count = 0; 2017 while (count < size && count < size_count) { 2018 status = dspio_read(codec, buffer++); 2019 if (status != 0) 2020 break; 2021 count++; 2022 } 2023 2024 skip_count = count; 2025 if (status == 0) { 2026 while (skip_count < size) { 2027 status = dspio_read(codec, &dummy); 2028 if (status != 0) 2029 break; 2030 skip_count++; 2031 } 2032 } 2033 *buf_size = count; 2034 2035 return status; 2036 } 2037 2038 /* 2039 * Construct the SCP header using corresponding fields 2040 */ 2041 static inline unsigned int 2042 make_scp_header(unsigned int target_id, unsigned int source_id, 2043 unsigned int get_flag, unsigned int req, 2044 unsigned int device_flag, unsigned int resp_flag, 2045 unsigned int error_flag, unsigned int data_size) 2046 { 2047 unsigned int header = 0; 2048 2049 header = (data_size & 0x1f) << 27; 2050 header |= (error_flag & 0x01) << 26; 2051 header |= (resp_flag & 0x01) << 25; 2052 header |= (device_flag & 0x01) << 24; 2053 header |= (req & 0x7f) << 17; 2054 header |= (get_flag & 0x01) << 16; 2055 header |= (source_id & 0xff) << 8; 2056 header |= target_id & 0xff; 2057 2058 return header; 2059 } 2060 2061 /* 2062 * Extract corresponding fields from SCP header 2063 */ 2064 static inline void 2065 extract_scp_header(unsigned int header, 2066 unsigned int *target_id, unsigned int *source_id, 2067 unsigned int *get_flag, unsigned int *req, 2068 unsigned int *device_flag, unsigned int *resp_flag, 2069 unsigned int *error_flag, unsigned int *data_size) 2070 { 2071 if (data_size) 2072 *data_size = (header >> 27) & 0x1f; 2073 if (error_flag) 2074 *error_flag = (header >> 26) & 0x01; 2075 if (resp_flag) 2076 *resp_flag = (header >> 25) & 0x01; 2077 if (device_flag) 2078 *device_flag = (header >> 24) & 0x01; 2079 if (req) 2080 *req = (header >> 17) & 0x7f; 2081 if (get_flag) 2082 *get_flag = (header >> 16) & 0x01; 2083 if (source_id) 2084 *source_id = (header >> 8) & 0xff; 2085 if (target_id) 2086 *target_id = header & 0xff; 2087 } 2088 2089 #define SCP_MAX_DATA_WORDS (16) 2090 2091 /* Structure to contain any SCP message */ 2092 struct scp_msg { 2093 unsigned int hdr; 2094 unsigned int data[SCP_MAX_DATA_WORDS]; 2095 }; 2096 2097 static void dspio_clear_response_queue(struct hda_codec *codec) 2098 { 2099 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2100 unsigned int dummy = 0; 2101 int status; 2102 2103 /* clear all from the response queue */ 2104 do { 2105 status = dspio_read(codec, &dummy); 2106 } while (status == 0 && time_before(jiffies, timeout)); 2107 } 2108 2109 static int dspio_get_response_data(struct hda_codec *codec) 2110 { 2111 struct ca0132_spec *spec = codec->spec; 2112 unsigned int data = 0; 2113 unsigned int count; 2114 2115 if (dspio_read(codec, &data) < 0) 2116 return -EIO; 2117 2118 if ((data & 0x00ffffff) == spec->wait_scp_header) { 2119 spec->scp_resp_header = data; 2120 spec->scp_resp_count = data >> 27; 2121 count = spec->wait_num_data; 2122 dspio_read_multiple(codec, spec->scp_resp_data, 2123 &spec->scp_resp_count, count); 2124 return 0; 2125 } 2126 2127 return -EIO; 2128 } 2129 2130 /* 2131 * Send SCP message to DSP 2132 */ 2133 static int dspio_send_scp_message(struct hda_codec *codec, 2134 unsigned char *send_buf, 2135 unsigned int send_buf_size, 2136 unsigned char *return_buf, 2137 unsigned int return_buf_size, 2138 unsigned int *bytes_returned) 2139 { 2140 struct ca0132_spec *spec = codec->spec; 2141 int status = -1; 2142 unsigned int scp_send_size = 0; 2143 unsigned int total_size; 2144 bool waiting_for_resp = false; 2145 unsigned int header; 2146 struct scp_msg *ret_msg; 2147 unsigned int resp_src_id, resp_target_id; 2148 unsigned int data_size, src_id, target_id, get_flag, device_flag; 2149 2150 if (bytes_returned) 2151 *bytes_returned = 0; 2152 2153 /* get scp header from buffer */ 2154 header = *((unsigned int *)send_buf); 2155 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL, 2156 &device_flag, NULL, NULL, &data_size); 2157 scp_send_size = data_size + 1; 2158 total_size = (scp_send_size * 4); 2159 2160 if (send_buf_size < total_size) 2161 return -EINVAL; 2162 2163 if (get_flag || device_flag) { 2164 if (!return_buf || return_buf_size < 4 || !bytes_returned) 2165 return -EINVAL; 2166 2167 spec->wait_scp_header = *((unsigned int *)send_buf); 2168 2169 /* swap source id with target id */ 2170 resp_target_id = src_id; 2171 resp_src_id = target_id; 2172 spec->wait_scp_header &= 0xffff0000; 2173 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id); 2174 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1; 2175 spec->wait_scp = 1; 2176 waiting_for_resp = true; 2177 } 2178 2179 status = dspio_write_multiple(codec, (unsigned int *)send_buf, 2180 scp_send_size); 2181 if (status < 0) { 2182 spec->wait_scp = 0; 2183 return status; 2184 } 2185 2186 if (waiting_for_resp) { 2187 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2188 memset(return_buf, 0, return_buf_size); 2189 do { 2190 msleep(20); 2191 } while (spec->wait_scp && time_before(jiffies, timeout)); 2192 waiting_for_resp = false; 2193 if (!spec->wait_scp) { 2194 ret_msg = (struct scp_msg *)return_buf; 2195 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4); 2196 memcpy(&ret_msg->data, spec->scp_resp_data, 2197 spec->wait_num_data); 2198 *bytes_returned = (spec->scp_resp_count + 1) * 4; 2199 status = 0; 2200 } else { 2201 status = -EIO; 2202 } 2203 spec->wait_scp = 0; 2204 } 2205 2206 return status; 2207 } 2208 2209 /** 2210 * Prepare and send the SCP message to DSP 2211 * @codec: the HDA codec 2212 * @mod_id: ID of the DSP module to send the command 2213 * @src_id: ID of the source 2214 * @req: ID of request to send to the DSP module 2215 * @dir: SET or GET 2216 * @data: pointer to the data to send with the request, request specific 2217 * @len: length of the data, in bytes 2218 * @reply: point to the buffer to hold data returned for a reply 2219 * @reply_len: length of the reply buffer returned from GET 2220 * 2221 * Returns zero or a negative error code. 2222 */ 2223 static int dspio_scp(struct hda_codec *codec, 2224 int mod_id, int src_id, int req, int dir, const void *data, 2225 unsigned int len, void *reply, unsigned int *reply_len) 2226 { 2227 int status = 0; 2228 struct scp_msg scp_send, scp_reply; 2229 unsigned int ret_bytes, send_size, ret_size; 2230 unsigned int send_get_flag, reply_resp_flag, reply_error_flag; 2231 unsigned int reply_data_size; 2232 2233 memset(&scp_send, 0, sizeof(scp_send)); 2234 memset(&scp_reply, 0, sizeof(scp_reply)); 2235 2236 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS)) 2237 return -EINVAL; 2238 2239 if (dir == SCP_GET && reply == NULL) { 2240 codec_dbg(codec, "dspio_scp get but has no buffer\n"); 2241 return -EINVAL; 2242 } 2243 2244 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) { 2245 codec_dbg(codec, "dspio_scp bad resp buf len parms\n"); 2246 return -EINVAL; 2247 } 2248 2249 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req, 2250 0, 0, 0, len/sizeof(unsigned int)); 2251 if (data != NULL && len > 0) { 2252 len = min((unsigned int)(sizeof(scp_send.data)), len); 2253 memcpy(scp_send.data, data, len); 2254 } 2255 2256 ret_bytes = 0; 2257 send_size = sizeof(unsigned int) + len; 2258 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send, 2259 send_size, (unsigned char *)&scp_reply, 2260 sizeof(scp_reply), &ret_bytes); 2261 2262 if (status < 0) { 2263 codec_dbg(codec, "dspio_scp: send scp msg failed\n"); 2264 return status; 2265 } 2266 2267 /* extract send and reply headers members */ 2268 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag, 2269 NULL, NULL, NULL, NULL, NULL); 2270 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL, 2271 &reply_resp_flag, &reply_error_flag, 2272 &reply_data_size); 2273 2274 if (!send_get_flag) 2275 return 0; 2276 2277 if (reply_resp_flag && !reply_error_flag) { 2278 ret_size = (ret_bytes - sizeof(scp_reply.hdr)) 2279 / sizeof(unsigned int); 2280 2281 if (*reply_len < ret_size*sizeof(unsigned int)) { 2282 codec_dbg(codec, "reply too long for buf\n"); 2283 return -EINVAL; 2284 } else if (ret_size != reply_data_size) { 2285 codec_dbg(codec, "RetLen and HdrLen .NE.\n"); 2286 return -EINVAL; 2287 } else if (!reply) { 2288 codec_dbg(codec, "NULL reply\n"); 2289 return -EINVAL; 2290 } else { 2291 *reply_len = ret_size*sizeof(unsigned int); 2292 memcpy(reply, scp_reply.data, *reply_len); 2293 } 2294 } else { 2295 codec_dbg(codec, "reply ill-formed or errflag set\n"); 2296 return -EIO; 2297 } 2298 2299 return status; 2300 } 2301 2302 /* 2303 * Set DSP parameters 2304 */ 2305 static int dspio_set_param(struct hda_codec *codec, int mod_id, 2306 int src_id, int req, const void *data, unsigned int len) 2307 { 2308 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL, 2309 NULL); 2310 } 2311 2312 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id, 2313 int req, const unsigned int data) 2314 { 2315 return dspio_set_param(codec, mod_id, 0x20, req, &data, 2316 sizeof(unsigned int)); 2317 } 2318 2319 static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id, 2320 int req, const unsigned int data) 2321 { 2322 return dspio_set_param(codec, mod_id, 0x00, req, &data, 2323 sizeof(unsigned int)); 2324 } 2325 2326 /* 2327 * Allocate a DSP DMA channel via an SCP message 2328 */ 2329 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan) 2330 { 2331 int status = 0; 2332 unsigned int size = sizeof(dma_chan); 2333 2334 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n"); 2335 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2336 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0, 2337 dma_chan, &size); 2338 2339 if (status < 0) { 2340 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n"); 2341 return status; 2342 } 2343 2344 if ((*dma_chan + 1) == 0) { 2345 codec_dbg(codec, "no free dma channels to allocate\n"); 2346 return -EBUSY; 2347 } 2348 2349 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan); 2350 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n"); 2351 2352 return status; 2353 } 2354 2355 /* 2356 * Free a DSP DMA via an SCP message 2357 */ 2358 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan) 2359 { 2360 int status = 0; 2361 unsigned int dummy = 0; 2362 2363 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n"); 2364 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan); 2365 2366 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2367 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan, 2368 sizeof(dma_chan), NULL, &dummy); 2369 2370 if (status < 0) { 2371 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n"); 2372 return status; 2373 } 2374 2375 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n"); 2376 2377 return status; 2378 } 2379 2380 /* 2381 * (Re)start the DSP 2382 */ 2383 static int dsp_set_run_state(struct hda_codec *codec) 2384 { 2385 unsigned int dbg_ctrl_reg; 2386 unsigned int halt_state; 2387 int err; 2388 2389 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg); 2390 if (err < 0) 2391 return err; 2392 2393 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >> 2394 DSP_DBGCNTL_STATE_LOBIT; 2395 2396 if (halt_state != 0) { 2397 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) & 2398 DSP_DBGCNTL_SS_MASK); 2399 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2400 dbg_ctrl_reg); 2401 if (err < 0) 2402 return err; 2403 2404 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) & 2405 DSP_DBGCNTL_EXEC_MASK; 2406 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2407 dbg_ctrl_reg); 2408 if (err < 0) 2409 return err; 2410 } 2411 2412 return 0; 2413 } 2414 2415 /* 2416 * Reset the DSP 2417 */ 2418 static int dsp_reset(struct hda_codec *codec) 2419 { 2420 unsigned int res; 2421 int retry = 20; 2422 2423 codec_dbg(codec, "dsp_reset\n"); 2424 do { 2425 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0); 2426 retry--; 2427 } while (res == -EIO && retry); 2428 2429 if (!retry) { 2430 codec_dbg(codec, "dsp_reset timeout\n"); 2431 return -EIO; 2432 } 2433 2434 return 0; 2435 } 2436 2437 /* 2438 * Convert chip address to DSP address 2439 */ 2440 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx, 2441 bool *code, bool *yram) 2442 { 2443 *code = *yram = false; 2444 2445 if (UC_RANGE(chip_addx, 1)) { 2446 *code = true; 2447 return UC_OFF(chip_addx); 2448 } else if (X_RANGE_ALL(chip_addx, 1)) { 2449 return X_OFF(chip_addx); 2450 } else if (Y_RANGE_ALL(chip_addx, 1)) { 2451 *yram = true; 2452 return Y_OFF(chip_addx); 2453 } 2454 2455 return INVALID_CHIP_ADDRESS; 2456 } 2457 2458 /* 2459 * Check if the DSP DMA is active 2460 */ 2461 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan) 2462 { 2463 unsigned int dma_chnlstart_reg; 2464 2465 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg); 2466 2467 return ((dma_chnlstart_reg & (1 << 2468 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0); 2469 } 2470 2471 static int dsp_dma_setup_common(struct hda_codec *codec, 2472 unsigned int chip_addx, 2473 unsigned int dma_chan, 2474 unsigned int port_map_mask, 2475 bool ovly) 2476 { 2477 int status = 0; 2478 unsigned int chnl_prop; 2479 unsigned int dsp_addx; 2480 unsigned int active; 2481 bool code, yram; 2482 2483 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n"); 2484 2485 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) { 2486 codec_dbg(codec, "dma chan num invalid\n"); 2487 return -EINVAL; 2488 } 2489 2490 if (dsp_is_dma_active(codec, dma_chan)) { 2491 codec_dbg(codec, "dma already active\n"); 2492 return -EBUSY; 2493 } 2494 2495 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2496 2497 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2498 codec_dbg(codec, "invalid chip addr\n"); 2499 return -ENXIO; 2500 } 2501 2502 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK; 2503 active = 0; 2504 2505 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n"); 2506 2507 if (ovly) { 2508 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET, 2509 &chnl_prop); 2510 2511 if (status < 0) { 2512 codec_dbg(codec, "read CHNLPROP Reg fail\n"); 2513 return status; 2514 } 2515 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n"); 2516 } 2517 2518 if (!code) 2519 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2520 else 2521 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2522 2523 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan)); 2524 2525 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop); 2526 if (status < 0) { 2527 codec_dbg(codec, "write CHNLPROP Reg fail\n"); 2528 return status; 2529 } 2530 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n"); 2531 2532 if (ovly) { 2533 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET, 2534 &active); 2535 2536 if (status < 0) { 2537 codec_dbg(codec, "read ACTIVE Reg fail\n"); 2538 return status; 2539 } 2540 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n"); 2541 } 2542 2543 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) & 2544 DSPDMAC_ACTIVE_AAR_MASK; 2545 2546 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active); 2547 if (status < 0) { 2548 codec_dbg(codec, "write ACTIVE Reg fail\n"); 2549 return status; 2550 } 2551 2552 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n"); 2553 2554 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan), 2555 port_map_mask); 2556 if (status < 0) { 2557 codec_dbg(codec, "write AUDCHSEL Reg fail\n"); 2558 return status; 2559 } 2560 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n"); 2561 2562 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan), 2563 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK); 2564 if (status < 0) { 2565 codec_dbg(codec, "write IRQCNT Reg fail\n"); 2566 return status; 2567 } 2568 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n"); 2569 2570 codec_dbg(codec, 2571 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, " 2572 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n", 2573 chip_addx, dsp_addx, dma_chan, 2574 port_map_mask, chnl_prop, active); 2575 2576 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n"); 2577 2578 return 0; 2579 } 2580 2581 /* 2582 * Setup the DSP DMA per-transfer-specific registers 2583 */ 2584 static int dsp_dma_setup(struct hda_codec *codec, 2585 unsigned int chip_addx, 2586 unsigned int count, 2587 unsigned int dma_chan) 2588 { 2589 int status = 0; 2590 bool code, yram; 2591 unsigned int dsp_addx; 2592 unsigned int addr_field; 2593 unsigned int incr_field; 2594 unsigned int base_cnt; 2595 unsigned int cur_cnt; 2596 unsigned int dma_cfg = 0; 2597 unsigned int adr_ofs = 0; 2598 unsigned int xfr_cnt = 0; 2599 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT - 2600 DSPDMAC_XFRCNT_BCNT_LOBIT + 1); 2601 2602 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n"); 2603 2604 if (count > max_dma_count) { 2605 codec_dbg(codec, "count too big\n"); 2606 return -EINVAL; 2607 } 2608 2609 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2610 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2611 codec_dbg(codec, "invalid chip addr\n"); 2612 return -ENXIO; 2613 } 2614 2615 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n"); 2616 2617 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT; 2618 incr_field = 0; 2619 2620 if (!code) { 2621 addr_field <<= 1; 2622 if (yram) 2623 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT); 2624 2625 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT); 2626 } 2627 2628 dma_cfg = addr_field + incr_field; 2629 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan), 2630 dma_cfg); 2631 if (status < 0) { 2632 codec_dbg(codec, "write DMACFG Reg fail\n"); 2633 return status; 2634 } 2635 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n"); 2636 2637 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT + 2638 (code ? 0 : 1)); 2639 2640 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan), 2641 adr_ofs); 2642 if (status < 0) { 2643 codec_dbg(codec, "write DSPADROFS Reg fail\n"); 2644 return status; 2645 } 2646 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n"); 2647 2648 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT; 2649 2650 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT; 2651 2652 xfr_cnt = base_cnt | cur_cnt; 2653 2654 status = chipio_write(codec, 2655 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt); 2656 if (status < 0) { 2657 codec_dbg(codec, "write XFRCNT Reg fail\n"); 2658 return status; 2659 } 2660 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n"); 2661 2662 codec_dbg(codec, 2663 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, " 2664 "ADROFS=0x%x, XFRCNT=0x%x\n", 2665 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt); 2666 2667 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n"); 2668 2669 return 0; 2670 } 2671 2672 /* 2673 * Start the DSP DMA 2674 */ 2675 static int dsp_dma_start(struct hda_codec *codec, 2676 unsigned int dma_chan, bool ovly) 2677 { 2678 unsigned int reg = 0; 2679 int status = 0; 2680 2681 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n"); 2682 2683 if (ovly) { 2684 status = chipio_read(codec, 2685 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2686 2687 if (status < 0) { 2688 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2689 return status; 2690 } 2691 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n"); 2692 2693 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2694 DSPDMAC_CHNLSTART_DIS_MASK); 2695 } 2696 2697 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2698 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT))); 2699 if (status < 0) { 2700 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2701 return status; 2702 } 2703 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n"); 2704 2705 return status; 2706 } 2707 2708 /* 2709 * Stop the DSP DMA 2710 */ 2711 static int dsp_dma_stop(struct hda_codec *codec, 2712 unsigned int dma_chan, bool ovly) 2713 { 2714 unsigned int reg = 0; 2715 int status = 0; 2716 2717 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n"); 2718 2719 if (ovly) { 2720 status = chipio_read(codec, 2721 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2722 2723 if (status < 0) { 2724 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2725 return status; 2726 } 2727 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n"); 2728 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2729 DSPDMAC_CHNLSTART_DIS_MASK); 2730 } 2731 2732 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2733 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT))); 2734 if (status < 0) { 2735 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2736 return status; 2737 } 2738 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n"); 2739 2740 return status; 2741 } 2742 2743 /** 2744 * Allocate router ports 2745 * 2746 * @codec: the HDA codec 2747 * @num_chans: number of channels in the stream 2748 * @ports_per_channel: number of ports per channel 2749 * @start_device: start device 2750 * @port_map: pointer to the port list to hold the allocated ports 2751 * 2752 * Returns zero or a negative error code. 2753 */ 2754 static int dsp_allocate_router_ports(struct hda_codec *codec, 2755 unsigned int num_chans, 2756 unsigned int ports_per_channel, 2757 unsigned int start_device, 2758 unsigned int *port_map) 2759 { 2760 int status = 0; 2761 int res; 2762 u8 val; 2763 2764 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2765 if (status < 0) 2766 return status; 2767 2768 val = start_device << 6; 2769 val |= (ports_per_channel - 1) << 4; 2770 val |= num_chans - 1; 2771 2772 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2773 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET, 2774 val); 2775 2776 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2777 VENDOR_CHIPIO_PORT_ALLOC_SET, 2778 MEM_CONNID_DSP); 2779 2780 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2781 if (status < 0) 2782 return status; 2783 2784 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 2785 VENDOR_CHIPIO_PORT_ALLOC_GET, 0); 2786 2787 *port_map = res; 2788 2789 return (res < 0) ? res : 0; 2790 } 2791 2792 /* 2793 * Free router ports 2794 */ 2795 static int dsp_free_router_ports(struct hda_codec *codec) 2796 { 2797 int status = 0; 2798 2799 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2800 if (status < 0) 2801 return status; 2802 2803 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2804 VENDOR_CHIPIO_PORT_FREE_SET, 2805 MEM_CONNID_DSP); 2806 2807 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2808 2809 return status; 2810 } 2811 2812 /* 2813 * Allocate DSP ports for the download stream 2814 */ 2815 static int dsp_allocate_ports(struct hda_codec *codec, 2816 unsigned int num_chans, 2817 unsigned int rate_multi, unsigned int *port_map) 2818 { 2819 int status; 2820 2821 codec_dbg(codec, " dsp_allocate_ports() -- begin\n"); 2822 2823 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2824 codec_dbg(codec, "bad rate multiple\n"); 2825 return -EINVAL; 2826 } 2827 2828 status = dsp_allocate_router_ports(codec, num_chans, 2829 rate_multi, 0, port_map); 2830 2831 codec_dbg(codec, " dsp_allocate_ports() -- complete\n"); 2832 2833 return status; 2834 } 2835 2836 static int dsp_allocate_ports_format(struct hda_codec *codec, 2837 const unsigned short fmt, 2838 unsigned int *port_map) 2839 { 2840 int status; 2841 unsigned int num_chans; 2842 2843 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1; 2844 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1; 2845 unsigned int rate_multi = sample_rate_mul / sample_rate_div; 2846 2847 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2848 codec_dbg(codec, "bad rate multiple\n"); 2849 return -EINVAL; 2850 } 2851 2852 num_chans = get_hdafmt_chs(fmt) + 1; 2853 2854 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map); 2855 2856 return status; 2857 } 2858 2859 /* 2860 * free DSP ports 2861 */ 2862 static int dsp_free_ports(struct hda_codec *codec) 2863 { 2864 int status; 2865 2866 codec_dbg(codec, " dsp_free_ports() -- begin\n"); 2867 2868 status = dsp_free_router_ports(codec); 2869 if (status < 0) { 2870 codec_dbg(codec, "free router ports fail\n"); 2871 return status; 2872 } 2873 codec_dbg(codec, " dsp_free_ports() -- complete\n"); 2874 2875 return status; 2876 } 2877 2878 /* 2879 * HDA DMA engine stuffs for DSP code download 2880 */ 2881 struct dma_engine { 2882 struct hda_codec *codec; 2883 unsigned short m_converter_format; 2884 struct snd_dma_buffer *dmab; 2885 unsigned int buf_size; 2886 }; 2887 2888 2889 enum dma_state { 2890 DMA_STATE_STOP = 0, 2891 DMA_STATE_RUN = 1 2892 }; 2893 2894 static int dma_convert_to_hda_format(struct hda_codec *codec, 2895 unsigned int sample_rate, 2896 unsigned short channels, 2897 unsigned short *hda_format) 2898 { 2899 unsigned int format_val; 2900 2901 format_val = snd_hdac_calc_stream_format(sample_rate, 2902 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0); 2903 2904 if (hda_format) 2905 *hda_format = (unsigned short)format_val; 2906 2907 return 0; 2908 } 2909 2910 /* 2911 * Reset DMA for DSP download 2912 */ 2913 static int dma_reset(struct dma_engine *dma) 2914 { 2915 struct hda_codec *codec = dma->codec; 2916 struct ca0132_spec *spec = codec->spec; 2917 int status; 2918 2919 if (dma->dmab->area) 2920 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab); 2921 2922 status = snd_hda_codec_load_dsp_prepare(codec, 2923 dma->m_converter_format, 2924 dma->buf_size, 2925 dma->dmab); 2926 if (status < 0) 2927 return status; 2928 spec->dsp_stream_id = status; 2929 return 0; 2930 } 2931 2932 static int dma_set_state(struct dma_engine *dma, enum dma_state state) 2933 { 2934 bool cmd; 2935 2936 switch (state) { 2937 case DMA_STATE_STOP: 2938 cmd = false; 2939 break; 2940 case DMA_STATE_RUN: 2941 cmd = true; 2942 break; 2943 default: 2944 return 0; 2945 } 2946 2947 snd_hda_codec_load_dsp_trigger(dma->codec, cmd); 2948 return 0; 2949 } 2950 2951 static unsigned int dma_get_buffer_size(struct dma_engine *dma) 2952 { 2953 return dma->dmab->bytes; 2954 } 2955 2956 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma) 2957 { 2958 return dma->dmab->area; 2959 } 2960 2961 static int dma_xfer(struct dma_engine *dma, 2962 const unsigned int *data, 2963 unsigned int count) 2964 { 2965 memcpy(dma->dmab->area, data, count); 2966 return 0; 2967 } 2968 2969 static void dma_get_converter_format( 2970 struct dma_engine *dma, 2971 unsigned short *format) 2972 { 2973 if (format) 2974 *format = dma->m_converter_format; 2975 } 2976 2977 static unsigned int dma_get_stream_id(struct dma_engine *dma) 2978 { 2979 struct ca0132_spec *spec = dma->codec->spec; 2980 2981 return spec->dsp_stream_id; 2982 } 2983 2984 struct dsp_image_seg { 2985 u32 magic; 2986 u32 chip_addr; 2987 u32 count; 2988 u32 data[]; 2989 }; 2990 2991 static const u32 g_magic_value = 0x4c46584d; 2992 static const u32 g_chip_addr_magic_value = 0xFFFFFF01; 2993 2994 static bool is_valid(const struct dsp_image_seg *p) 2995 { 2996 return p->magic == g_magic_value; 2997 } 2998 2999 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p) 3000 { 3001 return g_chip_addr_magic_value == p->chip_addr; 3002 } 3003 3004 static bool is_last(const struct dsp_image_seg *p) 3005 { 3006 return p->count == 0; 3007 } 3008 3009 static size_t dsp_sizeof(const struct dsp_image_seg *p) 3010 { 3011 return struct_size(p, data, p->count); 3012 } 3013 3014 static const struct dsp_image_seg *get_next_seg_ptr( 3015 const struct dsp_image_seg *p) 3016 { 3017 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p)); 3018 } 3019 3020 /* 3021 * CA0132 chip DSP transfer stuffs. For DSP download. 3022 */ 3023 #define INVALID_DMA_CHANNEL (~0U) 3024 3025 /* 3026 * Program a list of address/data pairs via the ChipIO widget. 3027 * The segment data is in the format of successive pairs of words. 3028 * These are repeated as indicated by the segment's count field. 3029 */ 3030 static int dspxfr_hci_write(struct hda_codec *codec, 3031 const struct dsp_image_seg *fls) 3032 { 3033 int status; 3034 const u32 *data; 3035 unsigned int count; 3036 3037 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) { 3038 codec_dbg(codec, "hci_write invalid params\n"); 3039 return -EINVAL; 3040 } 3041 3042 count = fls->count; 3043 data = (u32 *)(fls->data); 3044 while (count >= 2) { 3045 status = chipio_write(codec, data[0], data[1]); 3046 if (status < 0) { 3047 codec_dbg(codec, "hci_write chipio failed\n"); 3048 return status; 3049 } 3050 count -= 2; 3051 data += 2; 3052 } 3053 return 0; 3054 } 3055 3056 /** 3057 * Write a block of data into DSP code or data RAM using pre-allocated 3058 * DMA engine. 3059 * 3060 * @codec: the HDA codec 3061 * @fls: pointer to a fast load image 3062 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3063 * no relocation 3064 * @dma_engine: pointer to DMA engine to be used for DSP download 3065 * @dma_chan: The number of DMA channels used for DSP download 3066 * @port_map_mask: port mapping 3067 * @ovly: TRUE if overlay format is required 3068 * 3069 * Returns zero or a negative error code. 3070 */ 3071 static int dspxfr_one_seg(struct hda_codec *codec, 3072 const struct dsp_image_seg *fls, 3073 unsigned int reloc, 3074 struct dma_engine *dma_engine, 3075 unsigned int dma_chan, 3076 unsigned int port_map_mask, 3077 bool ovly) 3078 { 3079 int status = 0; 3080 bool comm_dma_setup_done = false; 3081 const unsigned int *data; 3082 unsigned int chip_addx; 3083 unsigned int words_to_write; 3084 unsigned int buffer_size_words; 3085 unsigned char *buffer_addx; 3086 unsigned short hda_format; 3087 unsigned int sample_rate_div; 3088 unsigned int sample_rate_mul; 3089 unsigned int num_chans; 3090 unsigned int hda_frame_size_words; 3091 unsigned int remainder_words; 3092 const u32 *data_remainder; 3093 u32 chip_addx_remainder; 3094 unsigned int run_size_words; 3095 const struct dsp_image_seg *hci_write = NULL; 3096 unsigned long timeout; 3097 bool dma_active; 3098 3099 if (fls == NULL) 3100 return -EINVAL; 3101 if (is_hci_prog_list_seg(fls)) { 3102 hci_write = fls; 3103 fls = get_next_seg_ptr(fls); 3104 } 3105 3106 if (hci_write && (!fls || is_last(fls))) { 3107 codec_dbg(codec, "hci_write\n"); 3108 return dspxfr_hci_write(codec, hci_write); 3109 } 3110 3111 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) { 3112 codec_dbg(codec, "Invalid Params\n"); 3113 return -EINVAL; 3114 } 3115 3116 data = fls->data; 3117 chip_addx = fls->chip_addr; 3118 words_to_write = fls->count; 3119 3120 if (!words_to_write) 3121 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0; 3122 if (reloc) 3123 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2); 3124 3125 if (!UC_RANGE(chip_addx, words_to_write) && 3126 !X_RANGE_ALL(chip_addx, words_to_write) && 3127 !Y_RANGE_ALL(chip_addx, words_to_write)) { 3128 codec_dbg(codec, "Invalid chip_addx Params\n"); 3129 return -EINVAL; 3130 } 3131 3132 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) / 3133 sizeof(u32); 3134 3135 buffer_addx = dma_get_buffer_addr(dma_engine); 3136 3137 if (buffer_addx == NULL) { 3138 codec_dbg(codec, "dma_engine buffer NULL\n"); 3139 return -EINVAL; 3140 } 3141 3142 dma_get_converter_format(dma_engine, &hda_format); 3143 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1; 3144 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1; 3145 num_chans = get_hdafmt_chs(hda_format) + 1; 3146 3147 hda_frame_size_words = ((sample_rate_div == 0) ? 0 : 3148 (num_chans * sample_rate_mul / sample_rate_div)); 3149 3150 if (hda_frame_size_words == 0) { 3151 codec_dbg(codec, "frmsz zero\n"); 3152 return -EINVAL; 3153 } 3154 3155 buffer_size_words = min(buffer_size_words, 3156 (unsigned int)(UC_RANGE(chip_addx, 1) ? 3157 65536 : 32768)); 3158 buffer_size_words -= buffer_size_words % hda_frame_size_words; 3159 codec_dbg(codec, 3160 "chpadr=0x%08x frmsz=%u nchan=%u " 3161 "rate_mul=%u div=%u bufsz=%u\n", 3162 chip_addx, hda_frame_size_words, num_chans, 3163 sample_rate_mul, sample_rate_div, buffer_size_words); 3164 3165 if (buffer_size_words < hda_frame_size_words) { 3166 codec_dbg(codec, "dspxfr_one_seg:failed\n"); 3167 return -EINVAL; 3168 } 3169 3170 remainder_words = words_to_write % hda_frame_size_words; 3171 data_remainder = data; 3172 chip_addx_remainder = chip_addx; 3173 3174 data += remainder_words; 3175 chip_addx += remainder_words*sizeof(u32); 3176 words_to_write -= remainder_words; 3177 3178 while (words_to_write != 0) { 3179 run_size_words = min(buffer_size_words, words_to_write); 3180 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n", 3181 words_to_write, run_size_words, remainder_words); 3182 dma_xfer(dma_engine, data, run_size_words*sizeof(u32)); 3183 if (!comm_dma_setup_done) { 3184 status = dsp_dma_stop(codec, dma_chan, ovly); 3185 if (status < 0) 3186 return status; 3187 status = dsp_dma_setup_common(codec, chip_addx, 3188 dma_chan, port_map_mask, ovly); 3189 if (status < 0) 3190 return status; 3191 comm_dma_setup_done = true; 3192 } 3193 3194 status = dsp_dma_setup(codec, chip_addx, 3195 run_size_words, dma_chan); 3196 if (status < 0) 3197 return status; 3198 status = dsp_dma_start(codec, dma_chan, ovly); 3199 if (status < 0) 3200 return status; 3201 if (!dsp_is_dma_active(codec, dma_chan)) { 3202 codec_dbg(codec, "dspxfr:DMA did not start\n"); 3203 return -EIO; 3204 } 3205 status = dma_set_state(dma_engine, DMA_STATE_RUN); 3206 if (status < 0) 3207 return status; 3208 if (remainder_words != 0) { 3209 status = chipio_write_multiple(codec, 3210 chip_addx_remainder, 3211 data_remainder, 3212 remainder_words); 3213 if (status < 0) 3214 return status; 3215 remainder_words = 0; 3216 } 3217 if (hci_write) { 3218 status = dspxfr_hci_write(codec, hci_write); 3219 if (status < 0) 3220 return status; 3221 hci_write = NULL; 3222 } 3223 3224 timeout = jiffies + msecs_to_jiffies(2000); 3225 do { 3226 dma_active = dsp_is_dma_active(codec, dma_chan); 3227 if (!dma_active) 3228 break; 3229 msleep(20); 3230 } while (time_before(jiffies, timeout)); 3231 if (dma_active) 3232 break; 3233 3234 codec_dbg(codec, "+++++ DMA complete\n"); 3235 dma_set_state(dma_engine, DMA_STATE_STOP); 3236 status = dma_reset(dma_engine); 3237 3238 if (status < 0) 3239 return status; 3240 3241 data += run_size_words; 3242 chip_addx += run_size_words*sizeof(u32); 3243 words_to_write -= run_size_words; 3244 } 3245 3246 if (remainder_words != 0) { 3247 status = chipio_write_multiple(codec, chip_addx_remainder, 3248 data_remainder, remainder_words); 3249 } 3250 3251 return status; 3252 } 3253 3254 /** 3255 * Write the entire DSP image of a DSP code/data overlay to DSP memories 3256 * 3257 * @codec: the HDA codec 3258 * @fls_data: pointer to a fast load image 3259 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3260 * no relocation 3261 * @sample_rate: sampling rate of the stream used for DSP download 3262 * @channels: channels of the stream used for DSP download 3263 * @ovly: TRUE if overlay format is required 3264 * 3265 * Returns zero or a negative error code. 3266 */ 3267 static int dspxfr_image(struct hda_codec *codec, 3268 const struct dsp_image_seg *fls_data, 3269 unsigned int reloc, 3270 unsigned int sample_rate, 3271 unsigned short channels, 3272 bool ovly) 3273 { 3274 struct ca0132_spec *spec = codec->spec; 3275 int status; 3276 unsigned short hda_format = 0; 3277 unsigned int response; 3278 unsigned char stream_id = 0; 3279 struct dma_engine *dma_engine; 3280 unsigned int dma_chan; 3281 unsigned int port_map_mask; 3282 3283 if (fls_data == NULL) 3284 return -EINVAL; 3285 3286 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL); 3287 if (!dma_engine) 3288 return -ENOMEM; 3289 3290 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL); 3291 if (!dma_engine->dmab) { 3292 kfree(dma_engine); 3293 return -ENOMEM; 3294 } 3295 3296 dma_engine->codec = codec; 3297 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format); 3298 dma_engine->m_converter_format = hda_format; 3299 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY : 3300 DSP_DMA_WRITE_BUFLEN_INIT) * 2; 3301 3302 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0; 3303 3304 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL, 3305 hda_format, &response); 3306 3307 if (status < 0) { 3308 codec_dbg(codec, "set converter format fail\n"); 3309 goto exit; 3310 } 3311 3312 status = snd_hda_codec_load_dsp_prepare(codec, 3313 dma_engine->m_converter_format, 3314 dma_engine->buf_size, 3315 dma_engine->dmab); 3316 if (status < 0) 3317 goto exit; 3318 spec->dsp_stream_id = status; 3319 3320 if (ovly) { 3321 status = dspio_alloc_dma_chan(codec, &dma_chan); 3322 if (status < 0) { 3323 codec_dbg(codec, "alloc dmachan fail\n"); 3324 dma_chan = INVALID_DMA_CHANNEL; 3325 goto exit; 3326 } 3327 } 3328 3329 port_map_mask = 0; 3330 status = dsp_allocate_ports_format(codec, hda_format, 3331 &port_map_mask); 3332 if (status < 0) { 3333 codec_dbg(codec, "alloc ports fail\n"); 3334 goto exit; 3335 } 3336 3337 stream_id = dma_get_stream_id(dma_engine); 3338 status = codec_set_converter_stream_channel(codec, 3339 WIDGET_CHIP_CTRL, stream_id, 0, &response); 3340 if (status < 0) { 3341 codec_dbg(codec, "set stream chan fail\n"); 3342 goto exit; 3343 } 3344 3345 while ((fls_data != NULL) && !is_last(fls_data)) { 3346 if (!is_valid(fls_data)) { 3347 codec_dbg(codec, "FLS check fail\n"); 3348 status = -EINVAL; 3349 goto exit; 3350 } 3351 status = dspxfr_one_seg(codec, fls_data, reloc, 3352 dma_engine, dma_chan, 3353 port_map_mask, ovly); 3354 if (status < 0) 3355 break; 3356 3357 if (is_hci_prog_list_seg(fls_data)) 3358 fls_data = get_next_seg_ptr(fls_data); 3359 3360 if ((fls_data != NULL) && !is_last(fls_data)) 3361 fls_data = get_next_seg_ptr(fls_data); 3362 } 3363 3364 if (port_map_mask != 0) 3365 status = dsp_free_ports(codec); 3366 3367 if (status < 0) 3368 goto exit; 3369 3370 status = codec_set_converter_stream_channel(codec, 3371 WIDGET_CHIP_CTRL, 0, 0, &response); 3372 3373 exit: 3374 if (ovly && (dma_chan != INVALID_DMA_CHANNEL)) 3375 dspio_free_dma_chan(codec, dma_chan); 3376 3377 if (dma_engine->dmab->area) 3378 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab); 3379 kfree(dma_engine->dmab); 3380 kfree(dma_engine); 3381 3382 return status; 3383 } 3384 3385 /* 3386 * CA0132 DSP download stuffs. 3387 */ 3388 static void dspload_post_setup(struct hda_codec *codec) 3389 { 3390 struct ca0132_spec *spec = codec->spec; 3391 codec_dbg(codec, "---- dspload_post_setup ------\n"); 3392 if (!ca0132_use_alt_functions(spec)) { 3393 /*set DSP speaker to 2.0 configuration*/ 3394 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080); 3395 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000); 3396 3397 /*update write pointer*/ 3398 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002); 3399 } 3400 } 3401 3402 /** 3403 * dspload_image - Download DSP from a DSP Image Fast Load structure. 3404 * 3405 * @codec: the HDA codec 3406 * @fls: pointer to a fast load image 3407 * @ovly: TRUE if overlay format is required 3408 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3409 * no relocation 3410 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE 3411 * @router_chans: number of audio router channels to be allocated (0 means use 3412 * internal defaults; max is 32) 3413 * 3414 * Download DSP from a DSP Image Fast Load structure. This structure is a 3415 * linear, non-constant sized element array of structures, each of which 3416 * contain the count of the data to be loaded, the data itself, and the 3417 * corresponding starting chip address of the starting data location. 3418 * Returns zero or a negative error code. 3419 */ 3420 static int dspload_image(struct hda_codec *codec, 3421 const struct dsp_image_seg *fls, 3422 bool ovly, 3423 unsigned int reloc, 3424 bool autostart, 3425 int router_chans) 3426 { 3427 int status = 0; 3428 unsigned int sample_rate; 3429 unsigned short channels; 3430 3431 codec_dbg(codec, "---- dspload_image begin ------\n"); 3432 if (router_chans == 0) { 3433 if (!ovly) 3434 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS; 3435 else 3436 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS; 3437 } 3438 3439 sample_rate = 48000; 3440 channels = (unsigned short)router_chans; 3441 3442 while (channels > 16) { 3443 sample_rate *= 2; 3444 channels /= 2; 3445 } 3446 3447 do { 3448 codec_dbg(codec, "Ready to program DMA\n"); 3449 if (!ovly) 3450 status = dsp_reset(codec); 3451 3452 if (status < 0) 3453 break; 3454 3455 codec_dbg(codec, "dsp_reset() complete\n"); 3456 status = dspxfr_image(codec, fls, reloc, sample_rate, channels, 3457 ovly); 3458 3459 if (status < 0) 3460 break; 3461 3462 codec_dbg(codec, "dspxfr_image() complete\n"); 3463 if (autostart && !ovly) { 3464 dspload_post_setup(codec); 3465 status = dsp_set_run_state(codec); 3466 } 3467 3468 codec_dbg(codec, "LOAD FINISHED\n"); 3469 } while (0); 3470 3471 return status; 3472 } 3473 3474 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 3475 static bool dspload_is_loaded(struct hda_codec *codec) 3476 { 3477 unsigned int data = 0; 3478 int status = 0; 3479 3480 status = chipio_read(codec, 0x40004, &data); 3481 if ((status < 0) || (data != 1)) 3482 return false; 3483 3484 return true; 3485 } 3486 #else 3487 #define dspload_is_loaded(codec) false 3488 #endif 3489 3490 static bool dspload_wait_loaded(struct hda_codec *codec) 3491 { 3492 unsigned long timeout = jiffies + msecs_to_jiffies(2000); 3493 3494 do { 3495 if (dspload_is_loaded(codec)) { 3496 codec_info(codec, "ca0132 DSP downloaded and running\n"); 3497 return true; 3498 } 3499 msleep(20); 3500 } while (time_before(jiffies, timeout)); 3501 3502 codec_err(codec, "ca0132 failed to download DSP\n"); 3503 return false; 3504 } 3505 3506 /* 3507 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e 3508 * based cards, and has a second mmio region, region2, that's used for special 3509 * commands. 3510 */ 3511 3512 /* 3513 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5) 3514 * the mmio address 0x320 is used to set GPIO pins. The format for the data 3515 * The first eight bits are just the number of the pin. So far, I've only seen 3516 * this number go to 7. 3517 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value 3518 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and 3519 * then off to send that bit. 3520 */ 3521 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin, 3522 bool enable) 3523 { 3524 struct ca0132_spec *spec = codec->spec; 3525 unsigned short gpio_data; 3526 3527 gpio_data = gpio_pin & 0xF; 3528 gpio_data |= ((enable << 8) & 0x100); 3529 3530 writew(gpio_data, spec->mem_base + 0x320); 3531 } 3532 3533 /* 3534 * Special pci region2 commands that are only used by the AE-5. They follow 3535 * a set format, and require reads at certain points to seemingly 'clear' 3536 * the response data. My first tests didn't do these reads, and would cause 3537 * the card to get locked up until the memory was read. These commands 3538 * seem to work with three distinct values that I've taken to calling group, 3539 * target-id, and value. 3540 */ 3541 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group, 3542 unsigned int target, unsigned int value) 3543 { 3544 struct ca0132_spec *spec = codec->spec; 3545 unsigned int write_val; 3546 3547 writel(0x0000007e, spec->mem_base + 0x210); 3548 readl(spec->mem_base + 0x210); 3549 writel(0x0000005a, spec->mem_base + 0x210); 3550 readl(spec->mem_base + 0x210); 3551 readl(spec->mem_base + 0x210); 3552 3553 writel(0x00800005, spec->mem_base + 0x20c); 3554 writel(group, spec->mem_base + 0x804); 3555 3556 writel(0x00800005, spec->mem_base + 0x20c); 3557 write_val = (target & 0xff); 3558 write_val |= (value << 8); 3559 3560 3561 writel(write_val, spec->mem_base + 0x204); 3562 /* 3563 * Need delay here or else it goes too fast and works inconsistently. 3564 */ 3565 msleep(20); 3566 3567 readl(spec->mem_base + 0x860); 3568 readl(spec->mem_base + 0x854); 3569 readl(spec->mem_base + 0x840); 3570 3571 writel(0x00800004, spec->mem_base + 0x20c); 3572 writel(0x00000000, spec->mem_base + 0x210); 3573 readl(spec->mem_base + 0x210); 3574 readl(spec->mem_base + 0x210); 3575 } 3576 3577 /* 3578 * This second type of command is used for setting the sound filter type. 3579 */ 3580 static void ca0113_mmio_command_set_type2(struct hda_codec *codec, 3581 unsigned int group, unsigned int target, unsigned int value) 3582 { 3583 struct ca0132_spec *spec = codec->spec; 3584 unsigned int write_val; 3585 3586 writel(0x0000007e, spec->mem_base + 0x210); 3587 readl(spec->mem_base + 0x210); 3588 writel(0x0000005a, spec->mem_base + 0x210); 3589 readl(spec->mem_base + 0x210); 3590 readl(spec->mem_base + 0x210); 3591 3592 writel(0x00800003, spec->mem_base + 0x20c); 3593 writel(group, spec->mem_base + 0x804); 3594 3595 writel(0x00800005, spec->mem_base + 0x20c); 3596 write_val = (target & 0xff); 3597 write_val |= (value << 8); 3598 3599 3600 writel(write_val, spec->mem_base + 0x204); 3601 msleep(20); 3602 readl(spec->mem_base + 0x860); 3603 readl(spec->mem_base + 0x854); 3604 readl(spec->mem_base + 0x840); 3605 3606 writel(0x00800004, spec->mem_base + 0x20c); 3607 writel(0x00000000, spec->mem_base + 0x210); 3608 readl(spec->mem_base + 0x210); 3609 readl(spec->mem_base + 0x210); 3610 } 3611 3612 /* 3613 * Setup GPIO for the other variants of Core3D. 3614 */ 3615 3616 /* 3617 * Sets up the GPIO pins so that they are discoverable. If this isn't done, 3618 * the card shows as having no GPIO pins. 3619 */ 3620 static void ca0132_gpio_init(struct hda_codec *codec) 3621 { 3622 struct ca0132_spec *spec = codec->spec; 3623 3624 switch (ca0132_quirk(spec)) { 3625 case QUIRK_SBZ: 3626 case QUIRK_AE5: 3627 case QUIRK_AE7: 3628 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3629 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 3630 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23); 3631 break; 3632 case QUIRK_R3DI: 3633 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3634 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B); 3635 break; 3636 default: 3637 break; 3638 } 3639 3640 } 3641 3642 /* Sets the GPIO for audio output. */ 3643 static void ca0132_gpio_setup(struct hda_codec *codec) 3644 { 3645 struct ca0132_spec *spec = codec->spec; 3646 3647 switch (ca0132_quirk(spec)) { 3648 case QUIRK_SBZ: 3649 snd_hda_codec_write(codec, 0x01, 0, 3650 AC_VERB_SET_GPIO_DIRECTION, 0x07); 3651 snd_hda_codec_write(codec, 0x01, 0, 3652 AC_VERB_SET_GPIO_MASK, 0x07); 3653 snd_hda_codec_write(codec, 0x01, 0, 3654 AC_VERB_SET_GPIO_DATA, 0x04); 3655 snd_hda_codec_write(codec, 0x01, 0, 3656 AC_VERB_SET_GPIO_DATA, 0x06); 3657 break; 3658 case QUIRK_R3DI: 3659 snd_hda_codec_write(codec, 0x01, 0, 3660 AC_VERB_SET_GPIO_DIRECTION, 0x1E); 3661 snd_hda_codec_write(codec, 0x01, 0, 3662 AC_VERB_SET_GPIO_MASK, 0x1F); 3663 snd_hda_codec_write(codec, 0x01, 0, 3664 AC_VERB_SET_GPIO_DATA, 0x0C); 3665 break; 3666 default: 3667 break; 3668 } 3669 } 3670 3671 /* 3672 * GPIO control functions for the Recon3D integrated. 3673 */ 3674 3675 enum r3di_gpio_bit { 3676 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */ 3677 R3DI_MIC_SELECT_BIT = 1, 3678 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */ 3679 R3DI_OUT_SELECT_BIT = 2, 3680 /* 3681 * I dunno what this actually does, but it stays on until the dsp 3682 * is downloaded. 3683 */ 3684 R3DI_GPIO_DSP_DOWNLOADING = 3, 3685 /* 3686 * Same as above, no clue what it does, but it comes on after the dsp 3687 * is downloaded. 3688 */ 3689 R3DI_GPIO_DSP_DOWNLOADED = 4 3690 }; 3691 3692 enum r3di_mic_select { 3693 /* Set GPIO bit 1 to 0 for rear mic */ 3694 R3DI_REAR_MIC = 0, 3695 /* Set GPIO bit 1 to 1 for front microphone*/ 3696 R3DI_FRONT_MIC = 1 3697 }; 3698 3699 enum r3di_out_select { 3700 /* Set GPIO bit 2 to 0 for headphone */ 3701 R3DI_HEADPHONE_OUT = 0, 3702 /* Set GPIO bit 2 to 1 for speaker */ 3703 R3DI_LINE_OUT = 1 3704 }; 3705 enum r3di_dsp_status { 3706 /* Set GPIO bit 3 to 1 until DSP is downloaded */ 3707 R3DI_DSP_DOWNLOADING = 0, 3708 /* Set GPIO bit 4 to 1 once DSP is downloaded */ 3709 R3DI_DSP_DOWNLOADED = 1 3710 }; 3711 3712 3713 static void r3di_gpio_mic_set(struct hda_codec *codec, 3714 enum r3di_mic_select cur_mic) 3715 { 3716 unsigned int cur_gpio; 3717 3718 /* Get the current GPIO Data setup */ 3719 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3720 3721 switch (cur_mic) { 3722 case R3DI_REAR_MIC: 3723 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT); 3724 break; 3725 case R3DI_FRONT_MIC: 3726 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT); 3727 break; 3728 } 3729 snd_hda_codec_write(codec, codec->core.afg, 0, 3730 AC_VERB_SET_GPIO_DATA, cur_gpio); 3731 } 3732 3733 static void r3di_gpio_dsp_status_set(struct hda_codec *codec, 3734 enum r3di_dsp_status dsp_status) 3735 { 3736 unsigned int cur_gpio; 3737 3738 /* Get the current GPIO Data setup */ 3739 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3740 3741 switch (dsp_status) { 3742 case R3DI_DSP_DOWNLOADING: 3743 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING); 3744 snd_hda_codec_write(codec, codec->core.afg, 0, 3745 AC_VERB_SET_GPIO_DATA, cur_gpio); 3746 break; 3747 case R3DI_DSP_DOWNLOADED: 3748 /* Set DOWNLOADING bit to 0. */ 3749 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING); 3750 3751 snd_hda_codec_write(codec, codec->core.afg, 0, 3752 AC_VERB_SET_GPIO_DATA, cur_gpio); 3753 3754 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED); 3755 break; 3756 } 3757 3758 snd_hda_codec_write(codec, codec->core.afg, 0, 3759 AC_VERB_SET_GPIO_DATA, cur_gpio); 3760 } 3761 3762 /* 3763 * PCM callbacks 3764 */ 3765 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3766 struct hda_codec *codec, 3767 unsigned int stream_tag, 3768 unsigned int format, 3769 struct snd_pcm_substream *substream) 3770 { 3771 struct ca0132_spec *spec = codec->spec; 3772 3773 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format); 3774 3775 return 0; 3776 } 3777 3778 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3779 struct hda_codec *codec, 3780 struct snd_pcm_substream *substream) 3781 { 3782 struct ca0132_spec *spec = codec->spec; 3783 3784 if (spec->dsp_state == DSP_DOWNLOADING) 3785 return 0; 3786 3787 /*If Playback effects are on, allow stream some time to flush 3788 *effects tail*/ 3789 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 3790 msleep(50); 3791 3792 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 3793 3794 return 0; 3795 } 3796 3797 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info, 3798 struct hda_codec *codec, 3799 struct snd_pcm_substream *substream) 3800 { 3801 struct ca0132_spec *spec = codec->spec; 3802 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY; 3803 struct snd_pcm_runtime *runtime = substream->runtime; 3804 3805 if (spec->dsp_state != DSP_DOWNLOADED) 3806 return 0; 3807 3808 /* Add latency if playback enhancement and either effect is enabled. */ 3809 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) { 3810 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) || 3811 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID])) 3812 latency += DSP_PLAY_ENHANCEMENT_LATENCY; 3813 } 3814 3815 /* Applying Speaker EQ adds latency as well. */ 3816 if (spec->cur_out_type == SPEAKER_OUT) 3817 latency += DSP_SPEAKER_OUT_LATENCY; 3818 3819 return (latency * runtime->rate) / 1000; 3820 } 3821 3822 /* 3823 * Digital out 3824 */ 3825 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo, 3826 struct hda_codec *codec, 3827 struct snd_pcm_substream *substream) 3828 { 3829 struct ca0132_spec *spec = codec->spec; 3830 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3831 } 3832 3833 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3834 struct hda_codec *codec, 3835 unsigned int stream_tag, 3836 unsigned int format, 3837 struct snd_pcm_substream *substream) 3838 { 3839 struct ca0132_spec *spec = codec->spec; 3840 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3841 stream_tag, format, substream); 3842 } 3843 3844 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3845 struct hda_codec *codec, 3846 struct snd_pcm_substream *substream) 3847 { 3848 struct ca0132_spec *spec = codec->spec; 3849 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout); 3850 } 3851 3852 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo, 3853 struct hda_codec *codec, 3854 struct snd_pcm_substream *substream) 3855 { 3856 struct ca0132_spec *spec = codec->spec; 3857 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3858 } 3859 3860 /* 3861 * Analog capture 3862 */ 3863 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo, 3864 struct hda_codec *codec, 3865 unsigned int stream_tag, 3866 unsigned int format, 3867 struct snd_pcm_substream *substream) 3868 { 3869 snd_hda_codec_setup_stream(codec, hinfo->nid, 3870 stream_tag, 0, format); 3871 3872 return 0; 3873 } 3874 3875 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo, 3876 struct hda_codec *codec, 3877 struct snd_pcm_substream *substream) 3878 { 3879 struct ca0132_spec *spec = codec->spec; 3880 3881 if (spec->dsp_state == DSP_DOWNLOADING) 3882 return 0; 3883 3884 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 3885 return 0; 3886 } 3887 3888 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info, 3889 struct hda_codec *codec, 3890 struct snd_pcm_substream *substream) 3891 { 3892 struct ca0132_spec *spec = codec->spec; 3893 unsigned int latency = DSP_CAPTURE_INIT_LATENCY; 3894 struct snd_pcm_runtime *runtime = substream->runtime; 3895 3896 if (spec->dsp_state != DSP_DOWNLOADED) 3897 return 0; 3898 3899 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 3900 latency += DSP_CRYSTAL_VOICE_LATENCY; 3901 3902 return (latency * runtime->rate) / 1000; 3903 } 3904 3905 /* 3906 * Controls stuffs. 3907 */ 3908 3909 /* 3910 * Mixer controls helpers. 3911 */ 3912 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \ 3913 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3914 .name = xname, \ 3915 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3916 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3917 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 3918 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 3919 .info = ca0132_volume_info, \ 3920 .get = ca0132_volume_get, \ 3921 .put = ca0132_volume_put, \ 3922 .tlv = { .c = ca0132_volume_tlv }, \ 3923 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3924 3925 /* 3926 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the 3927 * volume put, which is used for setting the DSP volume. This was done because 3928 * the ca0132 functions were taking too much time and causing lag. 3929 */ 3930 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \ 3931 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3932 .name = xname, \ 3933 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3934 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3935 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 3936 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 3937 .info = snd_hda_mixer_amp_volume_info, \ 3938 .get = snd_hda_mixer_amp_volume_get, \ 3939 .put = ca0132_alt_volume_put, \ 3940 .tlv = { .c = snd_hda_mixer_amp_tlv }, \ 3941 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3942 3943 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \ 3944 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3945 .name = xname, \ 3946 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3947 .info = snd_hda_mixer_amp_switch_info, \ 3948 .get = ca0132_switch_get, \ 3949 .put = ca0132_switch_put, \ 3950 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3951 3952 /* stereo */ 3953 #define CA0132_CODEC_VOL(xname, nid, dir) \ 3954 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir) 3955 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \ 3956 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir) 3957 #define CA0132_CODEC_MUTE(xname, nid, dir) \ 3958 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir) 3959 3960 /* lookup tables */ 3961 /* 3962 * Lookup table with decibel values for the DSP. When volume is changed in 3963 * Windows, the DSP is also sent the dB value in floating point. In Windows, 3964 * these values have decimal points, probably because the Windows driver 3965 * actually uses floating point. We can't here, so I made a lookup table of 3966 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the 3967 * DAC's, and 9 is the maximum. 3968 */ 3969 static const unsigned int float_vol_db_lookup[] = { 3970 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000, 3971 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000, 3972 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000, 3973 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000, 3974 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000, 3975 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000, 3976 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000, 3977 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000, 3978 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000, 3979 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000, 3980 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000, 3981 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 3982 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 3983 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 3984 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 3985 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 3986 0x40C00000, 0x40E00000, 0x41000000, 0x41100000 3987 }; 3988 3989 /* 3990 * This table counts from float 0 to 1 in increments of .01, which is 3991 * useful for a few different sliders. 3992 */ 3993 static const unsigned int float_zero_to_one_lookup[] = { 3994 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 3995 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 3996 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 3997 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 3998 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 3999 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 4000 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 4001 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 4002 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 4003 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 4004 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 4005 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 4006 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 4007 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 4008 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 4009 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 4010 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 4011 }; 4012 4013 /* 4014 * This table counts from float 10 to 1000, which is the range of the x-bass 4015 * crossover slider in Windows. 4016 */ 4017 static const unsigned int float_xbass_xover_lookup[] = { 4018 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000, 4019 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000, 4020 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000, 4021 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000, 4022 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000, 4023 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000, 4024 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000, 4025 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000, 4026 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000, 4027 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000, 4028 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000, 4029 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000, 4030 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000, 4031 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000, 4032 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000, 4033 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000, 4034 0x44728000, 0x44750000, 0x44778000, 0x447A0000 4035 }; 4036 4037 /* The following are for tuning of products */ 4038 #ifdef ENABLE_TUNING_CONTROLS 4039 4040 static const unsigned int voice_focus_vals_lookup[] = { 4041 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000, 4042 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000, 4043 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000, 4044 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000, 4045 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000, 4046 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000, 4047 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000, 4048 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000, 4049 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000, 4050 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000, 4051 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000, 4052 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000, 4053 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000, 4054 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000, 4055 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000, 4056 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000, 4057 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000, 4058 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000, 4059 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000, 4060 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000, 4061 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000, 4062 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000, 4063 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000, 4064 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000, 4065 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000, 4066 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000, 4067 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000 4068 }; 4069 4070 static const unsigned int mic_svm_vals_lookup[] = { 4071 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 4072 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 4073 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 4074 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 4075 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 4076 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 4077 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 4078 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 4079 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 4080 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 4081 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 4082 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 4083 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 4084 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 4085 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 4086 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 4087 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 4088 }; 4089 4090 static const unsigned int equalizer_vals_lookup[] = { 4091 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 4092 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 4093 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 4094 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 4095 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 4096 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000, 4097 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000, 4098 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 4099 0x41C00000 4100 }; 4101 4102 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid, 4103 const unsigned int *lookup, int idx) 4104 { 4105 int i = 0; 4106 4107 for (i = 0; i < TUNING_CTLS_COUNT; i++) 4108 if (nid == ca0132_tuning_ctls[i].nid) 4109 break; 4110 4111 snd_hda_power_up(codec); 4112 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20, 4113 ca0132_tuning_ctls[i].req, 4114 &(lookup[idx]), sizeof(unsigned int)); 4115 snd_hda_power_down(codec); 4116 4117 return 1; 4118 } 4119 4120 static int tuning_ctl_get(struct snd_kcontrol *kcontrol, 4121 struct snd_ctl_elem_value *ucontrol) 4122 { 4123 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4124 struct ca0132_spec *spec = codec->spec; 4125 hda_nid_t nid = get_amp_nid(kcontrol); 4126 long *valp = ucontrol->value.integer.value; 4127 int idx = nid - TUNING_CTL_START_NID; 4128 4129 *valp = spec->cur_ctl_vals[idx]; 4130 return 0; 4131 } 4132 4133 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol, 4134 struct snd_ctl_elem_info *uinfo) 4135 { 4136 int chs = get_amp_channels(kcontrol); 4137 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4138 uinfo->count = chs == 3 ? 2 : 1; 4139 uinfo->value.integer.min = 20; 4140 uinfo->value.integer.max = 180; 4141 uinfo->value.integer.step = 1; 4142 4143 return 0; 4144 } 4145 4146 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol, 4147 struct snd_ctl_elem_value *ucontrol) 4148 { 4149 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4150 struct ca0132_spec *spec = codec->spec; 4151 hda_nid_t nid = get_amp_nid(kcontrol); 4152 long *valp = ucontrol->value.integer.value; 4153 int idx; 4154 4155 idx = nid - TUNING_CTL_START_NID; 4156 /* any change? */ 4157 if (spec->cur_ctl_vals[idx] == *valp) 4158 return 0; 4159 4160 spec->cur_ctl_vals[idx] = *valp; 4161 4162 idx = *valp - 20; 4163 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx); 4164 4165 return 1; 4166 } 4167 4168 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol, 4169 struct snd_ctl_elem_info *uinfo) 4170 { 4171 int chs = get_amp_channels(kcontrol); 4172 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4173 uinfo->count = chs == 3 ? 2 : 1; 4174 uinfo->value.integer.min = 0; 4175 uinfo->value.integer.max = 100; 4176 uinfo->value.integer.step = 1; 4177 4178 return 0; 4179 } 4180 4181 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol, 4182 struct snd_ctl_elem_value *ucontrol) 4183 { 4184 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4185 struct ca0132_spec *spec = codec->spec; 4186 hda_nid_t nid = get_amp_nid(kcontrol); 4187 long *valp = ucontrol->value.integer.value; 4188 int idx; 4189 4190 idx = nid - TUNING_CTL_START_NID; 4191 /* any change? */ 4192 if (spec->cur_ctl_vals[idx] == *valp) 4193 return 0; 4194 4195 spec->cur_ctl_vals[idx] = *valp; 4196 4197 idx = *valp; 4198 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx); 4199 4200 return 0; 4201 } 4202 4203 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol, 4204 struct snd_ctl_elem_info *uinfo) 4205 { 4206 int chs = get_amp_channels(kcontrol); 4207 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4208 uinfo->count = chs == 3 ? 2 : 1; 4209 uinfo->value.integer.min = 0; 4210 uinfo->value.integer.max = 48; 4211 uinfo->value.integer.step = 1; 4212 4213 return 0; 4214 } 4215 4216 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol, 4217 struct snd_ctl_elem_value *ucontrol) 4218 { 4219 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4220 struct ca0132_spec *spec = codec->spec; 4221 hda_nid_t nid = get_amp_nid(kcontrol); 4222 long *valp = ucontrol->value.integer.value; 4223 int idx; 4224 4225 idx = nid - TUNING_CTL_START_NID; 4226 /* any change? */ 4227 if (spec->cur_ctl_vals[idx] == *valp) 4228 return 0; 4229 4230 spec->cur_ctl_vals[idx] = *valp; 4231 4232 idx = *valp; 4233 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx); 4234 4235 return 1; 4236 } 4237 4238 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0); 4239 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0); 4240 4241 static int add_tuning_control(struct hda_codec *codec, 4242 hda_nid_t pnid, hda_nid_t nid, 4243 const char *name, int dir) 4244 { 4245 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 4246 int type = dir ? HDA_INPUT : HDA_OUTPUT; 4247 struct snd_kcontrol_new knew = 4248 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 4249 4250 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 4251 SNDRV_CTL_ELEM_ACCESS_TLV_READ; 4252 knew.tlv.c = 0; 4253 knew.tlv.p = 0; 4254 switch (pnid) { 4255 case VOICE_FOCUS: 4256 knew.info = voice_focus_ctl_info; 4257 knew.get = tuning_ctl_get; 4258 knew.put = voice_focus_ctl_put; 4259 knew.tlv.p = voice_focus_db_scale; 4260 break; 4261 case MIC_SVM: 4262 knew.info = mic_svm_ctl_info; 4263 knew.get = tuning_ctl_get; 4264 knew.put = mic_svm_ctl_put; 4265 break; 4266 case EQUALIZER: 4267 knew.info = equalizer_ctl_info; 4268 knew.get = tuning_ctl_get; 4269 knew.put = equalizer_ctl_put; 4270 knew.tlv.p = eq_db_scale; 4271 break; 4272 default: 4273 return 0; 4274 } 4275 knew.private_value = 4276 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 4277 sprintf(namestr, "%s %s Volume", name, dirstr[dir]); 4278 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 4279 } 4280 4281 static int add_tuning_ctls(struct hda_codec *codec) 4282 { 4283 int i; 4284 int err; 4285 4286 for (i = 0; i < TUNING_CTLS_COUNT; i++) { 4287 err = add_tuning_control(codec, 4288 ca0132_tuning_ctls[i].parent_nid, 4289 ca0132_tuning_ctls[i].nid, 4290 ca0132_tuning_ctls[i].name, 4291 ca0132_tuning_ctls[i].direct); 4292 if (err < 0) 4293 return err; 4294 } 4295 4296 return 0; 4297 } 4298 4299 static void ca0132_init_tuning_defaults(struct hda_codec *codec) 4300 { 4301 struct ca0132_spec *spec = codec->spec; 4302 int i; 4303 4304 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */ 4305 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10; 4306 /* SVM level defaults to 0.74. */ 4307 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74; 4308 4309 /* EQ defaults to 0dB. */ 4310 for (i = 2; i < TUNING_CTLS_COUNT; i++) 4311 spec->cur_ctl_vals[i] = 24; 4312 } 4313 #endif /*ENABLE_TUNING_CONTROLS*/ 4314 4315 /* 4316 * Select the active output. 4317 * If autodetect is enabled, output will be selected based on jack detection. 4318 * If jack inserted, headphone will be selected, else built-in speakers 4319 * If autodetect is disabled, output will be selected based on selection. 4320 */ 4321 static int ca0132_select_out(struct hda_codec *codec) 4322 { 4323 struct ca0132_spec *spec = codec->spec; 4324 unsigned int pin_ctl; 4325 int jack_present; 4326 int auto_jack; 4327 unsigned int tmp; 4328 int err; 4329 4330 codec_dbg(codec, "ca0132_select_out\n"); 4331 4332 snd_hda_power_up_pm(codec); 4333 4334 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4335 4336 if (auto_jack) 4337 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp); 4338 else 4339 jack_present = 4340 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID]; 4341 4342 if (jack_present) 4343 spec->cur_out_type = HEADPHONE_OUT; 4344 else 4345 spec->cur_out_type = SPEAKER_OUT; 4346 4347 if (spec->cur_out_type == SPEAKER_OUT) { 4348 codec_dbg(codec, "ca0132_select_out speaker\n"); 4349 /*speaker out config*/ 4350 tmp = FLOAT_ONE; 4351 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4352 if (err < 0) 4353 goto exit; 4354 /*enable speaker EQ*/ 4355 tmp = FLOAT_ONE; 4356 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4357 if (err < 0) 4358 goto exit; 4359 4360 /* Setup EAPD */ 4361 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4362 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4363 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4364 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4365 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4366 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4367 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4368 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4369 4370 /* disable headphone node */ 4371 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4372 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4373 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4374 pin_ctl & ~PIN_HP); 4375 /* enable speaker node */ 4376 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4377 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4378 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4379 pin_ctl | PIN_OUT); 4380 } else { 4381 codec_dbg(codec, "ca0132_select_out hp\n"); 4382 /*headphone out config*/ 4383 tmp = FLOAT_ZERO; 4384 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4385 if (err < 0) 4386 goto exit; 4387 /*disable speaker EQ*/ 4388 tmp = FLOAT_ZERO; 4389 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4390 if (err < 0) 4391 goto exit; 4392 4393 /* Setup EAPD */ 4394 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4395 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4396 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4397 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4398 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4399 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4400 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4401 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4402 4403 /* disable speaker*/ 4404 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4405 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4406 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4407 pin_ctl & ~PIN_HP); 4408 /* enable headphone*/ 4409 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4410 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4411 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4412 pin_ctl | PIN_HP); 4413 } 4414 4415 exit: 4416 snd_hda_power_down_pm(codec); 4417 4418 return err < 0 ? err : 0; 4419 } 4420 4421 static int ae5_headphone_gain_set(struct hda_codec *codec, long val); 4422 static int zxr_headphone_gain_set(struct hda_codec *codec, long val); 4423 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val); 4424 4425 static void ae5_mmio_select_out(struct hda_codec *codec) 4426 { 4427 struct ca0132_spec *spec = codec->spec; 4428 const struct ae_ca0113_output_set *out_cmds; 4429 unsigned int i; 4430 4431 if (ca0132_quirk(spec) == QUIRK_AE5) 4432 out_cmds = &ae5_ca0113_output_presets; 4433 else 4434 out_cmds = &ae7_ca0113_output_presets; 4435 4436 for (i = 0; i < AE_CA0113_OUT_SET_COMMANDS; i++) 4437 ca0113_mmio_command_set(codec, out_cmds->group[i], 4438 out_cmds->target[i], 4439 out_cmds->vals[spec->cur_out_type][i]); 4440 } 4441 4442 static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec) 4443 { 4444 struct ca0132_spec *spec = codec->spec; 4445 int quirk = ca0132_quirk(spec); 4446 unsigned int tmp; 4447 int err; 4448 4449 /* 2.0/4.0 setup has no LFE channel, so setting full-range does nothing. */ 4450 if (spec->channel_cfg_val == SPEAKER_CHANNELS_4_0 4451 || spec->channel_cfg_val == SPEAKER_CHANNELS_2_0) 4452 return 0; 4453 4454 /* Set front L/R full range. Zero for full-range, one for redirection. */ 4455 tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE; 4456 err = dspio_set_uint_param(codec, 0x96, 4457 SPEAKER_FULL_RANGE_FRONT_L_R, tmp); 4458 if (err < 0) 4459 return err; 4460 4461 /* When setting full-range rear, both rear and center/lfe are set. */ 4462 tmp = spec->speaker_range_val[1] ? FLOAT_ZERO : FLOAT_ONE; 4463 err = dspio_set_uint_param(codec, 0x96, 4464 SPEAKER_FULL_RANGE_CENTER_LFE, tmp); 4465 if (err < 0) 4466 return err; 4467 4468 err = dspio_set_uint_param(codec, 0x96, 4469 SPEAKER_FULL_RANGE_REAR_L_R, tmp); 4470 if (err < 0) 4471 return err; 4472 4473 /* 4474 * Only the AE series cards set this value when setting full-range, 4475 * and it's always 1.0f. 4476 */ 4477 if (quirk == QUIRK_AE5 || quirk == QUIRK_AE7) { 4478 err = dspio_set_uint_param(codec, 0x96, 4479 SPEAKER_FULL_RANGE_SURROUND_L_R, FLOAT_ONE); 4480 if (err < 0) 4481 return err; 4482 } 4483 4484 return 0; 4485 } 4486 4487 static int ca0132_alt_surround_set_bass_redirection(struct hda_codec *codec, 4488 bool val) 4489 { 4490 struct ca0132_spec *spec = codec->spec; 4491 unsigned int tmp; 4492 int err; 4493 4494 if (val && spec->channel_cfg_val != SPEAKER_CHANNELS_4_0 && 4495 spec->channel_cfg_val != SPEAKER_CHANNELS_2_0) 4496 tmp = FLOAT_ONE; 4497 else 4498 tmp = FLOAT_ZERO; 4499 4500 err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp); 4501 if (err < 0) 4502 return err; 4503 4504 /* If it is enabled, make sure to set the crossover frequency. */ 4505 if (tmp) { 4506 tmp = float_xbass_xover_lookup[spec->xbass_xover_freq]; 4507 err = dspio_set_uint_param(codec, 0x96, 4508 SPEAKER_BASS_REDIRECT_XOVER_FREQ, tmp); 4509 if (err < 0) 4510 return err; 4511 } 4512 4513 return 0; 4514 } 4515 4516 /* 4517 * These are the commands needed to setup output on each of the different card 4518 * types. 4519 */ 4520 static void ca0132_alt_select_out_get_quirk_data(struct hda_codec *codec, 4521 const struct ca0132_alt_out_set_quirk_data **quirk_data) 4522 { 4523 struct ca0132_spec *spec = codec->spec; 4524 int quirk = ca0132_quirk(spec); 4525 unsigned int i; 4526 4527 *quirk_data = NULL; 4528 for (i = 0; i < ARRAY_SIZE(quirk_out_set_data); i++) { 4529 if (quirk_out_set_data[i].quirk_id == quirk) { 4530 *quirk_data = &quirk_out_set_data[i]; 4531 return; 4532 } 4533 } 4534 } 4535 4536 static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec) 4537 { 4538 const struct ca0132_alt_out_set_quirk_data *quirk_data; 4539 const struct ca0132_alt_out_set_info *out_info; 4540 struct ca0132_spec *spec = codec->spec; 4541 unsigned int i, gpio_data; 4542 int err; 4543 4544 ca0132_alt_select_out_get_quirk_data(codec, &quirk_data); 4545 if (!quirk_data) 4546 return 0; 4547 4548 out_info = &quirk_data->out_set_info[spec->cur_out_type]; 4549 if (quirk_data->is_ae_series) 4550 ae5_mmio_select_out(codec); 4551 4552 if (out_info->has_hda_gpio) { 4553 gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0, 4554 AC_VERB_GET_GPIO_DATA, 0); 4555 4556 if (out_info->hda_gpio_set) 4557 gpio_data |= (1 << out_info->hda_gpio_pin); 4558 else 4559 gpio_data &= ~(1 << out_info->hda_gpio_pin); 4560 4561 snd_hda_codec_write(codec, codec->core.afg, 0, 4562 AC_VERB_SET_GPIO_DATA, gpio_data); 4563 } 4564 4565 if (out_info->mmio_gpio_count) { 4566 for (i = 0; i < out_info->mmio_gpio_count; i++) { 4567 ca0113_mmio_gpio_set(codec, out_info->mmio_gpio_pin[i], 4568 out_info->mmio_gpio_set[i]); 4569 } 4570 } 4571 4572 if (out_info->scp_cmds_count) { 4573 for (i = 0; i < out_info->scp_cmds_count; i++) { 4574 err = dspio_set_uint_param(codec, 4575 out_info->scp_cmd_mid[i], 4576 out_info->scp_cmd_req[i], 4577 out_info->scp_cmd_val[i]); 4578 if (err < 0) 4579 return err; 4580 } 4581 } 4582 4583 chipio_set_control_param(codec, 0x0d, out_info->dac2port); 4584 4585 if (out_info->has_chipio_write) { 4586 chipio_write(codec, out_info->chipio_write_addr, 4587 out_info->chipio_write_data); 4588 } 4589 4590 if (quirk_data->has_headphone_gain) { 4591 if (spec->cur_out_type != HEADPHONE_OUT) { 4592 if (quirk_data->is_ae_series) 4593 ae5_headphone_gain_set(codec, 2); 4594 else 4595 zxr_headphone_gain_set(codec, 0); 4596 } else { 4597 if (quirk_data->is_ae_series) 4598 ae5_headphone_gain_set(codec, 4599 spec->ae5_headphone_gain_val); 4600 else 4601 zxr_headphone_gain_set(codec, 4602 spec->zxr_gain_set); 4603 } 4604 } 4605 4606 return 0; 4607 } 4608 4609 static void ca0132_set_out_node_pincfg(struct hda_codec *codec, hda_nid_t nid, 4610 bool out_enable, bool hp_enable) 4611 { 4612 unsigned int pin_ctl; 4613 4614 pin_ctl = snd_hda_codec_read(codec, nid, 0, 4615 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4616 4617 pin_ctl = hp_enable ? pin_ctl | PIN_HP_AMP : pin_ctl & ~PIN_HP_AMP; 4618 pin_ctl = out_enable ? pin_ctl | PIN_OUT : pin_ctl & ~PIN_OUT; 4619 snd_hda_set_pin_ctl(codec, nid, pin_ctl); 4620 } 4621 4622 /* 4623 * This function behaves similarly to the ca0132_select_out funciton above, 4624 * except with a few differences. It adds the ability to select the current 4625 * output with an enumerated control "output source" if the auto detect 4626 * mute switch is set to off. If the auto detect mute switch is enabled, it 4627 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection. 4628 * It also adds the ability to auto-detect the front headphone port. 4629 */ 4630 static int ca0132_alt_select_out(struct hda_codec *codec) 4631 { 4632 struct ca0132_spec *spec = codec->spec; 4633 unsigned int tmp, outfx_set; 4634 int jack_present; 4635 int auto_jack; 4636 int err; 4637 /* Default Headphone is rear headphone */ 4638 hda_nid_t headphone_nid = spec->out_pins[1]; 4639 4640 codec_dbg(codec, "%s\n", __func__); 4641 4642 snd_hda_power_up_pm(codec); 4643 4644 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4645 4646 /* 4647 * If headphone rear or front is plugged in, set to headphone. 4648 * If neither is plugged in, set to rear line out. Only if 4649 * hp/speaker auto detect is enabled. 4650 */ 4651 if (auto_jack) { 4652 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) || 4653 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp); 4654 4655 if (jack_present) 4656 spec->cur_out_type = HEADPHONE_OUT; 4657 else 4658 spec->cur_out_type = SPEAKER_OUT; 4659 } else 4660 spec->cur_out_type = spec->out_enum_val; 4661 4662 outfx_set = spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]; 4663 4664 /* Begin DSP output switch, mute DSP volume. */ 4665 err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE); 4666 if (err < 0) 4667 goto exit; 4668 4669 if (ca0132_alt_select_out_quirk_set(codec) < 0) 4670 goto exit; 4671 4672 switch (spec->cur_out_type) { 4673 case SPEAKER_OUT: 4674 codec_dbg(codec, "%s speaker\n", __func__); 4675 4676 /* Enable EAPD */ 4677 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4678 AC_VERB_SET_EAPD_BTLENABLE, 0x01); 4679 4680 /* Disable headphone node. */ 4681 ca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0); 4682 /* Set front L-R to output. */ 4683 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0); 4684 /* Set Center/LFE to output. */ 4685 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0); 4686 /* Set rear surround to output. */ 4687 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0); 4688 4689 /* 4690 * Without PlayEnhancement being enabled, if we've got a 2.0 4691 * setup, set it to floating point eight to disable any DSP 4692 * processing effects. 4693 */ 4694 if (!outfx_set && spec->channel_cfg_val == SPEAKER_CHANNELS_2_0) 4695 tmp = FLOAT_EIGHT; 4696 else 4697 tmp = speaker_channel_cfgs[spec->channel_cfg_val].val; 4698 4699 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4700 if (err < 0) 4701 goto exit; 4702 4703 break; 4704 case HEADPHONE_OUT: 4705 codec_dbg(codec, "%s hp\n", __func__); 4706 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4707 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4708 4709 /* Disable all speaker nodes. */ 4710 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0); 4711 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0); 4712 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0); 4713 4714 /* enable headphone, either front or rear */ 4715 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp)) 4716 headphone_nid = spec->out_pins[2]; 4717 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp)) 4718 headphone_nid = spec->out_pins[1]; 4719 4720 ca0132_set_out_node_pincfg(codec, headphone_nid, 1, 1); 4721 4722 if (outfx_set) 4723 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE); 4724 else 4725 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO); 4726 4727 if (err < 0) 4728 goto exit; 4729 break; 4730 } 4731 /* 4732 * If output effects are enabled, set the X-Bass effect value again to 4733 * make sure that it's properly enabled/disabled for speaker 4734 * configurations with an LFE channel. 4735 */ 4736 if (outfx_set) 4737 ca0132_effects_set(codec, X_BASS, 4738 spec->effects_switch[X_BASS - EFFECT_START_NID]); 4739 4740 /* Set speaker EQ bypass attenuation to 0. */ 4741 err = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO); 4742 if (err < 0) 4743 goto exit; 4744 4745 /* 4746 * Although unused on all cards but the AE series, this is always set 4747 * to zero when setting the output. 4748 */ 4749 err = dspio_set_uint_param(codec, 0x96, 4750 SPEAKER_TUNING_USE_SPEAKER_EQ, FLOAT_ZERO); 4751 if (err < 0) 4752 goto exit; 4753 4754 if (spec->cur_out_type == SPEAKER_OUT) 4755 err = ca0132_alt_surround_set_bass_redirection(codec, 4756 spec->bass_redirection_val); 4757 else 4758 err = ca0132_alt_surround_set_bass_redirection(codec, 0); 4759 4760 /* Unmute DSP now that we're done with output selection. */ 4761 err = dspio_set_uint_param(codec, 0x96, 4762 SPEAKER_TUNING_MUTE, FLOAT_ZERO); 4763 if (err < 0) 4764 goto exit; 4765 4766 if (spec->cur_out_type == SPEAKER_OUT) { 4767 err = ca0132_alt_set_full_range_speaker(codec); 4768 if (err < 0) 4769 goto exit; 4770 } 4771 4772 exit: 4773 snd_hda_power_down_pm(codec); 4774 4775 return err < 0 ? err : 0; 4776 } 4777 4778 static void ca0132_unsol_hp_delayed(struct work_struct *work) 4779 { 4780 struct ca0132_spec *spec = container_of( 4781 to_delayed_work(work), struct ca0132_spec, unsol_hp_work); 4782 struct hda_jack_tbl *jack; 4783 4784 if (ca0132_use_alt_functions(spec)) 4785 ca0132_alt_select_out(spec->codec); 4786 else 4787 ca0132_select_out(spec->codec); 4788 4789 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp); 4790 if (jack) { 4791 jack->block_report = 0; 4792 snd_hda_jack_report_sync(spec->codec); 4793 } 4794 } 4795 4796 static void ca0132_set_dmic(struct hda_codec *codec, int enable); 4797 static int ca0132_mic_boost_set(struct hda_codec *codec, long val); 4798 static void resume_mic1(struct hda_codec *codec, unsigned int oldval); 4799 static int stop_mic1(struct hda_codec *codec); 4800 static int ca0132_cvoice_switch_set(struct hda_codec *codec); 4801 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val); 4802 4803 /* 4804 * Select the active VIP source 4805 */ 4806 static int ca0132_set_vipsource(struct hda_codec *codec, int val) 4807 { 4808 struct ca0132_spec *spec = codec->spec; 4809 unsigned int tmp; 4810 4811 if (spec->dsp_state != DSP_DOWNLOADED) 4812 return 0; 4813 4814 /* if CrystalVoice if off, vipsource should be 0 */ 4815 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4816 (val == 0)) { 4817 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4818 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4819 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4820 if (spec->cur_mic_type == DIGITAL_MIC) 4821 tmp = FLOAT_TWO; 4822 else 4823 tmp = FLOAT_ONE; 4824 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4825 tmp = FLOAT_ZERO; 4826 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4827 } else { 4828 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4829 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4830 if (spec->cur_mic_type == DIGITAL_MIC) 4831 tmp = FLOAT_TWO; 4832 else 4833 tmp = FLOAT_ONE; 4834 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4835 tmp = FLOAT_ONE; 4836 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4837 msleep(20); 4838 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4839 } 4840 4841 return 1; 4842 } 4843 4844 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val) 4845 { 4846 struct ca0132_spec *spec = codec->spec; 4847 unsigned int tmp; 4848 4849 if (spec->dsp_state != DSP_DOWNLOADED) 4850 return 0; 4851 4852 codec_dbg(codec, "%s\n", __func__); 4853 4854 chipio_set_stream_control(codec, 0x03, 0); 4855 chipio_set_stream_control(codec, 0x04, 0); 4856 4857 /* if CrystalVoice is off, vipsource should be 0 */ 4858 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4859 (val == 0) || spec->in_enum_val == REAR_LINE_IN) { 4860 codec_dbg(codec, "%s: off.", __func__); 4861 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4862 4863 tmp = FLOAT_ZERO; 4864 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4865 4866 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4867 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4868 if (ca0132_quirk(spec) == QUIRK_R3DI) 4869 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4870 4871 4872 if (spec->in_enum_val == REAR_LINE_IN) 4873 tmp = FLOAT_ZERO; 4874 else { 4875 if (ca0132_quirk(spec) == QUIRK_SBZ) 4876 tmp = FLOAT_THREE; 4877 else 4878 tmp = FLOAT_ONE; 4879 } 4880 4881 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4882 4883 } else { 4884 codec_dbg(codec, "%s: on.", __func__); 4885 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4886 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4887 if (ca0132_quirk(spec) == QUIRK_R3DI) 4888 chipio_set_conn_rate(codec, 0x0F, SR_16_000); 4889 4890 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID]) 4891 tmp = FLOAT_TWO; 4892 else 4893 tmp = FLOAT_ONE; 4894 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4895 4896 tmp = FLOAT_ONE; 4897 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4898 4899 msleep(20); 4900 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4901 } 4902 4903 chipio_set_stream_control(codec, 0x03, 1); 4904 chipio_set_stream_control(codec, 0x04, 1); 4905 4906 return 1; 4907 } 4908 4909 /* 4910 * Select the active microphone. 4911 * If autodetect is enabled, mic will be selected based on jack detection. 4912 * If jack inserted, ext.mic will be selected, else built-in mic 4913 * If autodetect is disabled, mic will be selected based on selection. 4914 */ 4915 static int ca0132_select_mic(struct hda_codec *codec) 4916 { 4917 struct ca0132_spec *spec = codec->spec; 4918 int jack_present; 4919 int auto_jack; 4920 4921 codec_dbg(codec, "ca0132_select_mic\n"); 4922 4923 snd_hda_power_up_pm(codec); 4924 4925 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 4926 4927 if (auto_jack) 4928 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1); 4929 else 4930 jack_present = 4931 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID]; 4932 4933 if (jack_present) 4934 spec->cur_mic_type = LINE_MIC_IN; 4935 else 4936 spec->cur_mic_type = DIGITAL_MIC; 4937 4938 if (spec->cur_mic_type == DIGITAL_MIC) { 4939 /* enable digital Mic */ 4940 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000); 4941 ca0132_set_dmic(codec, 1); 4942 ca0132_mic_boost_set(codec, 0); 4943 /* set voice focus */ 4944 ca0132_effects_set(codec, VOICE_FOCUS, 4945 spec->effects_switch 4946 [VOICE_FOCUS - EFFECT_START_NID]); 4947 } else { 4948 /* disable digital Mic */ 4949 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000); 4950 ca0132_set_dmic(codec, 0); 4951 ca0132_mic_boost_set(codec, spec->cur_mic_boost); 4952 /* disable voice focus */ 4953 ca0132_effects_set(codec, VOICE_FOCUS, 0); 4954 } 4955 4956 snd_hda_power_down_pm(codec); 4957 4958 return 0; 4959 } 4960 4961 /* 4962 * Select the active input. 4963 * Mic detection isn't used, because it's kind of pointless on the SBZ. 4964 * The front mic has no jack-detection, so the only way to switch to it 4965 * is to do it manually in alsamixer. 4966 */ 4967 static int ca0132_alt_select_in(struct hda_codec *codec) 4968 { 4969 struct ca0132_spec *spec = codec->spec; 4970 unsigned int tmp; 4971 4972 codec_dbg(codec, "%s\n", __func__); 4973 4974 snd_hda_power_up_pm(codec); 4975 4976 chipio_set_stream_control(codec, 0x03, 0); 4977 chipio_set_stream_control(codec, 0x04, 0); 4978 4979 spec->cur_mic_type = spec->in_enum_val; 4980 4981 switch (spec->cur_mic_type) { 4982 case REAR_MIC: 4983 switch (ca0132_quirk(spec)) { 4984 case QUIRK_SBZ: 4985 case QUIRK_R3D: 4986 ca0113_mmio_gpio_set(codec, 0, false); 4987 tmp = FLOAT_THREE; 4988 break; 4989 case QUIRK_ZXR: 4990 tmp = FLOAT_THREE; 4991 break; 4992 case QUIRK_R3DI: 4993 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 4994 tmp = FLOAT_ONE; 4995 break; 4996 case QUIRK_AE5: 4997 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 4998 tmp = FLOAT_THREE; 4999 break; 5000 case QUIRK_AE7: 5001 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5002 tmp = FLOAT_THREE; 5003 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, 5004 SR_96_000); 5005 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, 5006 SR_96_000); 5007 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO); 5008 break; 5009 default: 5010 tmp = FLOAT_ONE; 5011 break; 5012 } 5013 5014 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5015 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5016 if (ca0132_quirk(spec) == QUIRK_R3DI) 5017 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5018 5019 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5020 5021 chipio_set_stream_control(codec, 0x03, 1); 5022 chipio_set_stream_control(codec, 0x04, 1); 5023 switch (ca0132_quirk(spec)) { 5024 case QUIRK_SBZ: 5025 chipio_write(codec, 0x18B098, 0x0000000C); 5026 chipio_write(codec, 0x18B09C, 0x0000000C); 5027 break; 5028 case QUIRK_ZXR: 5029 chipio_write(codec, 0x18B098, 0x0000000C); 5030 chipio_write(codec, 0x18B09C, 0x000000CC); 5031 break; 5032 case QUIRK_AE5: 5033 chipio_write(codec, 0x18B098, 0x0000000C); 5034 chipio_write(codec, 0x18B09C, 0x0000004C); 5035 break; 5036 default: 5037 break; 5038 } 5039 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5040 break; 5041 case REAR_LINE_IN: 5042 ca0132_mic_boost_set(codec, 0); 5043 switch (ca0132_quirk(spec)) { 5044 case QUIRK_SBZ: 5045 case QUIRK_R3D: 5046 ca0113_mmio_gpio_set(codec, 0, false); 5047 break; 5048 case QUIRK_R3DI: 5049 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 5050 break; 5051 case QUIRK_AE5: 5052 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5053 break; 5054 case QUIRK_AE7: 5055 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f); 5056 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, 5057 SR_96_000); 5058 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, 5059 SR_96_000); 5060 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO); 5061 break; 5062 default: 5063 break; 5064 } 5065 5066 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5067 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5068 if (ca0132_quirk(spec) == QUIRK_R3DI) 5069 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5070 5071 if (ca0132_quirk(spec) == QUIRK_AE7) 5072 tmp = FLOAT_THREE; 5073 else 5074 tmp = FLOAT_ZERO; 5075 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5076 5077 switch (ca0132_quirk(spec)) { 5078 case QUIRK_SBZ: 5079 case QUIRK_AE5: 5080 chipio_write(codec, 0x18B098, 0x00000000); 5081 chipio_write(codec, 0x18B09C, 0x00000000); 5082 break; 5083 default: 5084 break; 5085 } 5086 chipio_set_stream_control(codec, 0x03, 1); 5087 chipio_set_stream_control(codec, 0x04, 1); 5088 break; 5089 case FRONT_MIC: 5090 switch (ca0132_quirk(spec)) { 5091 case QUIRK_SBZ: 5092 case QUIRK_R3D: 5093 ca0113_mmio_gpio_set(codec, 0, true); 5094 ca0113_mmio_gpio_set(codec, 5, false); 5095 tmp = FLOAT_THREE; 5096 break; 5097 case QUIRK_R3DI: 5098 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC); 5099 tmp = FLOAT_ONE; 5100 break; 5101 case QUIRK_AE5: 5102 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f); 5103 tmp = FLOAT_THREE; 5104 break; 5105 default: 5106 tmp = FLOAT_ONE; 5107 break; 5108 } 5109 5110 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5111 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5112 if (ca0132_quirk(spec) == QUIRK_R3DI) 5113 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5114 5115 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5116 5117 chipio_set_stream_control(codec, 0x03, 1); 5118 chipio_set_stream_control(codec, 0x04, 1); 5119 5120 switch (ca0132_quirk(spec)) { 5121 case QUIRK_SBZ: 5122 chipio_write(codec, 0x18B098, 0x0000000C); 5123 chipio_write(codec, 0x18B09C, 0x000000CC); 5124 break; 5125 case QUIRK_AE5: 5126 chipio_write(codec, 0x18B098, 0x0000000C); 5127 chipio_write(codec, 0x18B09C, 0x0000004C); 5128 break; 5129 default: 5130 break; 5131 } 5132 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5133 break; 5134 } 5135 ca0132_cvoice_switch_set(codec); 5136 5137 snd_hda_power_down_pm(codec); 5138 return 0; 5139 } 5140 5141 /* 5142 * Check if VNODE settings take effect immediately. 5143 */ 5144 static bool ca0132_is_vnode_effective(struct hda_codec *codec, 5145 hda_nid_t vnid, 5146 hda_nid_t *shared_nid) 5147 { 5148 struct ca0132_spec *spec = codec->spec; 5149 hda_nid_t nid; 5150 5151 switch (vnid) { 5152 case VNID_SPK: 5153 nid = spec->shared_out_nid; 5154 break; 5155 case VNID_MIC: 5156 nid = spec->shared_mic_nid; 5157 break; 5158 default: 5159 return false; 5160 } 5161 5162 if (shared_nid) 5163 *shared_nid = nid; 5164 5165 return true; 5166 } 5167 5168 /* 5169 * The following functions are control change helpers. 5170 * They return 0 if no changed. Return 1 if changed. 5171 */ 5172 static int ca0132_voicefx_set(struct hda_codec *codec, int enable) 5173 { 5174 struct ca0132_spec *spec = codec->spec; 5175 unsigned int tmp; 5176 5177 /* based on CrystalVoice state to enable VoiceFX. */ 5178 if (enable) { 5179 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ? 5180 FLOAT_ONE : FLOAT_ZERO; 5181 } else { 5182 tmp = FLOAT_ZERO; 5183 } 5184 5185 dspio_set_uint_param(codec, ca0132_voicefx.mid, 5186 ca0132_voicefx.reqs[0], tmp); 5187 5188 return 1; 5189 } 5190 5191 /* 5192 * Set the effects parameters 5193 */ 5194 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val) 5195 { 5196 struct ca0132_spec *spec = codec->spec; 5197 unsigned int on, tmp, channel_cfg; 5198 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 5199 int err = 0; 5200 int idx = nid - EFFECT_START_NID; 5201 5202 if ((idx < 0) || (idx >= num_fx)) 5203 return 0; /* no changed */ 5204 5205 /* for out effect, qualify with PE */ 5206 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) { 5207 /* if PE if off, turn off out effects. */ 5208 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 5209 val = 0; 5210 if (spec->cur_out_type == SPEAKER_OUT && nid == X_BASS) { 5211 channel_cfg = spec->channel_cfg_val; 5212 if (channel_cfg != SPEAKER_CHANNELS_2_0 && 5213 channel_cfg != SPEAKER_CHANNELS_4_0) 5214 val = 0; 5215 } 5216 } 5217 5218 /* for in effect, qualify with CrystalVoice */ 5219 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) { 5220 /* if CrystalVoice if off, turn off in effects. */ 5221 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 5222 val = 0; 5223 5224 /* Voice Focus applies to 2-ch Mic, Digital Mic */ 5225 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC)) 5226 val = 0; 5227 5228 /* If Voice Focus on SBZ, set to two channel. */ 5229 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec) 5230 && (spec->cur_mic_type != REAR_LINE_IN)) { 5231 if (spec->effects_switch[CRYSTAL_VOICE - 5232 EFFECT_START_NID]) { 5233 5234 if (spec->effects_switch[VOICE_FOCUS - 5235 EFFECT_START_NID]) { 5236 tmp = FLOAT_TWO; 5237 val = 1; 5238 } else 5239 tmp = FLOAT_ONE; 5240 5241 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5242 } 5243 } 5244 /* 5245 * For SBZ noise reduction, there's an extra command 5246 * to module ID 0x47. No clue why. 5247 */ 5248 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec) 5249 && (spec->cur_mic_type != REAR_LINE_IN)) { 5250 if (spec->effects_switch[CRYSTAL_VOICE - 5251 EFFECT_START_NID]) { 5252 if (spec->effects_switch[NOISE_REDUCTION - 5253 EFFECT_START_NID]) 5254 tmp = FLOAT_ONE; 5255 else 5256 tmp = FLOAT_ZERO; 5257 } else 5258 tmp = FLOAT_ZERO; 5259 5260 dspio_set_uint_param(codec, 0x47, 0x00, tmp); 5261 } 5262 5263 /* If rear line in disable effects. */ 5264 if (ca0132_use_alt_functions(spec) && 5265 spec->in_enum_val == REAR_LINE_IN) 5266 val = 0; 5267 } 5268 5269 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n", 5270 nid, val); 5271 5272 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE; 5273 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid, 5274 ca0132_effects[idx].reqs[0], on); 5275 5276 if (err < 0) 5277 return 0; /* no changed */ 5278 5279 return 1; 5280 } 5281 5282 /* 5283 * Turn on/off Playback Enhancements 5284 */ 5285 static int ca0132_pe_switch_set(struct hda_codec *codec) 5286 { 5287 struct ca0132_spec *spec = codec->spec; 5288 hda_nid_t nid; 5289 int i, ret = 0; 5290 5291 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n", 5292 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]); 5293 5294 if (ca0132_use_alt_functions(spec)) 5295 ca0132_alt_select_out(codec); 5296 5297 i = OUT_EFFECT_START_NID - EFFECT_START_NID; 5298 nid = OUT_EFFECT_START_NID; 5299 /* PE affects all out effects */ 5300 for (; nid < OUT_EFFECT_END_NID; nid++, i++) 5301 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 5302 5303 return ret; 5304 } 5305 5306 /* Check if Mic1 is streaming, if so, stop streaming */ 5307 static int stop_mic1(struct hda_codec *codec) 5308 { 5309 struct ca0132_spec *spec = codec->spec; 5310 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0, 5311 AC_VERB_GET_CONV, 0); 5312 if (oldval != 0) 5313 snd_hda_codec_write(codec, spec->adcs[0], 0, 5314 AC_VERB_SET_CHANNEL_STREAMID, 5315 0); 5316 return oldval; 5317 } 5318 5319 /* Resume Mic1 streaming if it was stopped. */ 5320 static void resume_mic1(struct hda_codec *codec, unsigned int oldval) 5321 { 5322 struct ca0132_spec *spec = codec->spec; 5323 /* Restore the previous stream and channel */ 5324 if (oldval != 0) 5325 snd_hda_codec_write(codec, spec->adcs[0], 0, 5326 AC_VERB_SET_CHANNEL_STREAMID, 5327 oldval); 5328 } 5329 5330 /* 5331 * Turn on/off CrystalVoice 5332 */ 5333 static int ca0132_cvoice_switch_set(struct hda_codec *codec) 5334 { 5335 struct ca0132_spec *spec = codec->spec; 5336 hda_nid_t nid; 5337 int i, ret = 0; 5338 unsigned int oldval; 5339 5340 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n", 5341 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]); 5342 5343 i = IN_EFFECT_START_NID - EFFECT_START_NID; 5344 nid = IN_EFFECT_START_NID; 5345 /* CrystalVoice affects all in effects */ 5346 for (; nid < IN_EFFECT_END_NID; nid++, i++) 5347 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 5348 5349 /* including VoiceFX */ 5350 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0)); 5351 5352 /* set correct vipsource */ 5353 oldval = stop_mic1(codec); 5354 if (ca0132_use_alt_functions(spec)) 5355 ret |= ca0132_alt_set_vipsource(codec, 1); 5356 else 5357 ret |= ca0132_set_vipsource(codec, 1); 5358 resume_mic1(codec, oldval); 5359 return ret; 5360 } 5361 5362 static int ca0132_mic_boost_set(struct hda_codec *codec, long val) 5363 { 5364 struct ca0132_spec *spec = codec->spec; 5365 int ret = 0; 5366 5367 if (val) /* on */ 5368 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5369 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3); 5370 else /* off */ 5371 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5372 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0); 5373 5374 return ret; 5375 } 5376 5377 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val) 5378 { 5379 struct ca0132_spec *spec = codec->spec; 5380 int ret = 0; 5381 5382 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5383 HDA_INPUT, 0, HDA_AMP_VOLMASK, val); 5384 return ret; 5385 } 5386 5387 static int ae5_headphone_gain_set(struct hda_codec *codec, long val) 5388 { 5389 unsigned int i; 5390 5391 for (i = 0; i < 4; i++) 5392 ca0113_mmio_command_set(codec, 0x48, 0x11 + i, 5393 ae5_headphone_gain_presets[val].vals[i]); 5394 return 0; 5395 } 5396 5397 /* 5398 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone 5399 * amplifier to handle a 600 ohm load. 5400 */ 5401 static int zxr_headphone_gain_set(struct hda_codec *codec, long val) 5402 { 5403 ca0113_mmio_gpio_set(codec, 1, val); 5404 5405 return 0; 5406 } 5407 5408 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol, 5409 struct snd_ctl_elem_value *ucontrol) 5410 { 5411 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5412 hda_nid_t nid = get_amp_nid(kcontrol); 5413 hda_nid_t shared_nid = 0; 5414 bool effective; 5415 int ret = 0; 5416 struct ca0132_spec *spec = codec->spec; 5417 int auto_jack; 5418 5419 if (nid == VNID_HP_SEL) { 5420 auto_jack = 5421 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 5422 if (!auto_jack) { 5423 if (ca0132_use_alt_functions(spec)) 5424 ca0132_alt_select_out(codec); 5425 else 5426 ca0132_select_out(codec); 5427 } 5428 return 1; 5429 } 5430 5431 if (nid == VNID_AMIC1_SEL) { 5432 auto_jack = 5433 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 5434 if (!auto_jack) 5435 ca0132_select_mic(codec); 5436 return 1; 5437 } 5438 5439 if (nid == VNID_HP_ASEL) { 5440 if (ca0132_use_alt_functions(spec)) 5441 ca0132_alt_select_out(codec); 5442 else 5443 ca0132_select_out(codec); 5444 return 1; 5445 } 5446 5447 if (nid == VNID_AMIC1_ASEL) { 5448 ca0132_select_mic(codec); 5449 return 1; 5450 } 5451 5452 /* if effective conditions, then update hw immediately. */ 5453 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 5454 if (effective) { 5455 int dir = get_amp_direction(kcontrol); 5456 int ch = get_amp_channels(kcontrol); 5457 unsigned long pval; 5458 5459 mutex_lock(&codec->control_mutex); 5460 pval = kcontrol->private_value; 5461 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 5462 0, dir); 5463 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol); 5464 kcontrol->private_value = pval; 5465 mutex_unlock(&codec->control_mutex); 5466 } 5467 5468 return ret; 5469 } 5470 /* End of control change helpers. */ 5471 5472 static void ca0132_alt_bass_redirection_xover_set(struct hda_codec *codec, 5473 long idx) 5474 { 5475 snd_hda_power_up(codec); 5476 5477 dspio_set_param(codec, 0x96, 0x20, SPEAKER_BASS_REDIRECT_XOVER_FREQ, 5478 &(float_xbass_xover_lookup[idx]), sizeof(unsigned int)); 5479 5480 snd_hda_power_down(codec); 5481 } 5482 5483 /* 5484 * Below I've added controls to mess with the effect levels, I've only enabled 5485 * them on the Sound Blaster Z, but they would probably also work on the 5486 * Chromebook. I figured they were probably tuned specifically for it, and left 5487 * out for a reason. 5488 */ 5489 5490 /* Sets DSP effect level from the sliders above the controls */ 5491 5492 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid, 5493 const unsigned int *lookup, int idx) 5494 { 5495 int i = 0; 5496 unsigned int y; 5497 /* 5498 * For X_BASS, req 2 is actually crossover freq instead of 5499 * effect level 5500 */ 5501 if (nid == X_BASS) 5502 y = 2; 5503 else 5504 y = 1; 5505 5506 snd_hda_power_up(codec); 5507 if (nid == XBASS_XOVER) { 5508 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5509 if (ca0132_effects[i].nid == X_BASS) 5510 break; 5511 5512 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5513 ca0132_effects[i].reqs[1], 5514 &(lookup[idx - 1]), sizeof(unsigned int)); 5515 } else { 5516 /* Find the actual effect structure */ 5517 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5518 if (nid == ca0132_effects[i].nid) 5519 break; 5520 5521 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5522 ca0132_effects[i].reqs[y], 5523 &(lookup[idx]), sizeof(unsigned int)); 5524 } 5525 5526 snd_hda_power_down(codec); 5527 5528 return 0; 5529 } 5530 5531 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol, 5532 struct snd_ctl_elem_value *ucontrol) 5533 { 5534 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5535 struct ca0132_spec *spec = codec->spec; 5536 long *valp = ucontrol->value.integer.value; 5537 hda_nid_t nid = get_amp_nid(kcontrol); 5538 5539 if (nid == BASS_REDIRECTION_XOVER) 5540 *valp = spec->bass_redirect_xover_freq; 5541 else 5542 *valp = spec->xbass_xover_freq; 5543 5544 return 0; 5545 } 5546 5547 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol, 5548 struct snd_ctl_elem_value *ucontrol) 5549 { 5550 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5551 struct ca0132_spec *spec = codec->spec; 5552 hda_nid_t nid = get_amp_nid(kcontrol); 5553 long *valp = ucontrol->value.integer.value; 5554 int idx = nid - OUT_EFFECT_START_NID; 5555 5556 *valp = spec->fx_ctl_val[idx]; 5557 return 0; 5558 } 5559 5560 /* 5561 * The X-bass crossover starts at 10hz, so the min is 1. The 5562 * frequency is set in multiples of 10. 5563 */ 5564 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol, 5565 struct snd_ctl_elem_info *uinfo) 5566 { 5567 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5568 uinfo->count = 1; 5569 uinfo->value.integer.min = 1; 5570 uinfo->value.integer.max = 100; 5571 uinfo->value.integer.step = 1; 5572 5573 return 0; 5574 } 5575 5576 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol, 5577 struct snd_ctl_elem_info *uinfo) 5578 { 5579 int chs = get_amp_channels(kcontrol); 5580 5581 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5582 uinfo->count = chs == 3 ? 2 : 1; 5583 uinfo->value.integer.min = 0; 5584 uinfo->value.integer.max = 100; 5585 uinfo->value.integer.step = 1; 5586 5587 return 0; 5588 } 5589 5590 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol, 5591 struct snd_ctl_elem_value *ucontrol) 5592 { 5593 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5594 struct ca0132_spec *spec = codec->spec; 5595 hda_nid_t nid = get_amp_nid(kcontrol); 5596 long *valp = ucontrol->value.integer.value; 5597 long *cur_val; 5598 int idx; 5599 5600 if (nid == BASS_REDIRECTION_XOVER) 5601 cur_val = &spec->bass_redirect_xover_freq; 5602 else 5603 cur_val = &spec->xbass_xover_freq; 5604 5605 /* any change? */ 5606 if (*cur_val == *valp) 5607 return 0; 5608 5609 *cur_val = *valp; 5610 5611 idx = *valp; 5612 if (nid == BASS_REDIRECTION_XOVER) 5613 ca0132_alt_bass_redirection_xover_set(codec, *cur_val); 5614 else 5615 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx); 5616 5617 return 0; 5618 } 5619 5620 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol, 5621 struct snd_ctl_elem_value *ucontrol) 5622 { 5623 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5624 struct ca0132_spec *spec = codec->spec; 5625 hda_nid_t nid = get_amp_nid(kcontrol); 5626 long *valp = ucontrol->value.integer.value; 5627 int idx; 5628 5629 idx = nid - EFFECT_START_NID; 5630 /* any change? */ 5631 if (spec->fx_ctl_val[idx] == *valp) 5632 return 0; 5633 5634 spec->fx_ctl_val[idx] = *valp; 5635 5636 idx = *valp; 5637 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx); 5638 5639 return 0; 5640 } 5641 5642 5643 /* 5644 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original 5645 * only has off or full 30 dB, and didn't like making a volume slider that has 5646 * traditional 0-100 in alsamixer that goes in big steps. I like enum better. 5647 */ 5648 #define MIC_BOOST_NUM_OF_STEPS 4 5649 #define MIC_BOOST_ENUM_MAX_STRLEN 10 5650 5651 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol, 5652 struct snd_ctl_elem_info *uinfo) 5653 { 5654 char *sfx = "dB"; 5655 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5656 5657 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5658 uinfo->count = 1; 5659 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS; 5660 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS) 5661 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1; 5662 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx); 5663 strcpy(uinfo->value.enumerated.name, namestr); 5664 return 0; 5665 } 5666 5667 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol, 5668 struct snd_ctl_elem_value *ucontrol) 5669 { 5670 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5671 struct ca0132_spec *spec = codec->spec; 5672 5673 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val; 5674 return 0; 5675 } 5676 5677 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol, 5678 struct snd_ctl_elem_value *ucontrol) 5679 { 5680 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5681 struct ca0132_spec *spec = codec->spec; 5682 int sel = ucontrol->value.enumerated.item[0]; 5683 unsigned int items = MIC_BOOST_NUM_OF_STEPS; 5684 5685 if (sel >= items) 5686 return 0; 5687 5688 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n", 5689 sel); 5690 5691 spec->mic_boost_enum_val = sel; 5692 5693 if (spec->in_enum_val != REAR_LINE_IN) 5694 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5695 5696 return 1; 5697 } 5698 5699 /* 5700 * Sound BlasterX AE-5 Headphone Gain Controls. 5701 */ 5702 #define AE5_HEADPHONE_GAIN_MAX 3 5703 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol, 5704 struct snd_ctl_elem_info *uinfo) 5705 { 5706 char *sfx = " Ohms)"; 5707 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5708 5709 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5710 uinfo->count = 1; 5711 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX; 5712 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX) 5713 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1; 5714 sprintf(namestr, "%s %s", 5715 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name, 5716 sfx); 5717 strcpy(uinfo->value.enumerated.name, namestr); 5718 return 0; 5719 } 5720 5721 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol, 5722 struct snd_ctl_elem_value *ucontrol) 5723 { 5724 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5725 struct ca0132_spec *spec = codec->spec; 5726 5727 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val; 5728 return 0; 5729 } 5730 5731 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol, 5732 struct snd_ctl_elem_value *ucontrol) 5733 { 5734 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5735 struct ca0132_spec *spec = codec->spec; 5736 int sel = ucontrol->value.enumerated.item[0]; 5737 unsigned int items = AE5_HEADPHONE_GAIN_MAX; 5738 5739 if (sel >= items) 5740 return 0; 5741 5742 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n", 5743 sel); 5744 5745 spec->ae5_headphone_gain_val = sel; 5746 5747 if (spec->out_enum_val == HEADPHONE_OUT) 5748 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val); 5749 5750 return 1; 5751 } 5752 5753 /* 5754 * Sound BlasterX AE-5 sound filter enumerated control. 5755 */ 5756 #define AE5_SOUND_FILTER_MAX 3 5757 5758 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol, 5759 struct snd_ctl_elem_info *uinfo) 5760 { 5761 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5762 5763 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5764 uinfo->count = 1; 5765 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX; 5766 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX) 5767 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1; 5768 sprintf(namestr, "%s", 5769 ae5_filter_presets[uinfo->value.enumerated.item].name); 5770 strcpy(uinfo->value.enumerated.name, namestr); 5771 return 0; 5772 } 5773 5774 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol, 5775 struct snd_ctl_elem_value *ucontrol) 5776 { 5777 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5778 struct ca0132_spec *spec = codec->spec; 5779 5780 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val; 5781 return 0; 5782 } 5783 5784 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol, 5785 struct snd_ctl_elem_value *ucontrol) 5786 { 5787 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5788 struct ca0132_spec *spec = codec->spec; 5789 int sel = ucontrol->value.enumerated.item[0]; 5790 unsigned int items = AE5_SOUND_FILTER_MAX; 5791 5792 if (sel >= items) 5793 return 0; 5794 5795 codec_dbg(codec, "ae5_sound_filter: %s\n", 5796 ae5_filter_presets[sel].name); 5797 5798 spec->ae5_filter_val = sel; 5799 5800 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 5801 ae5_filter_presets[sel].val); 5802 5803 return 1; 5804 } 5805 5806 /* 5807 * Input Select Control for alternative ca0132 codecs. This exists because 5808 * front microphone has no auto-detect, and we need a way to set the rear 5809 * as line-in 5810 */ 5811 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol, 5812 struct snd_ctl_elem_info *uinfo) 5813 { 5814 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5815 uinfo->count = 1; 5816 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS; 5817 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS) 5818 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1; 5819 strcpy(uinfo->value.enumerated.name, 5820 in_src_str[uinfo->value.enumerated.item]); 5821 return 0; 5822 } 5823 5824 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol, 5825 struct snd_ctl_elem_value *ucontrol) 5826 { 5827 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5828 struct ca0132_spec *spec = codec->spec; 5829 5830 ucontrol->value.enumerated.item[0] = spec->in_enum_val; 5831 return 0; 5832 } 5833 5834 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol, 5835 struct snd_ctl_elem_value *ucontrol) 5836 { 5837 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5838 struct ca0132_spec *spec = codec->spec; 5839 int sel = ucontrol->value.enumerated.item[0]; 5840 unsigned int items = IN_SRC_NUM_OF_INPUTS; 5841 5842 /* 5843 * The AE-7 has no front microphone, so limit items to 2: rear mic and 5844 * line-in. 5845 */ 5846 if (ca0132_quirk(spec) == QUIRK_AE7) 5847 items = 2; 5848 5849 if (sel >= items) 5850 return 0; 5851 5852 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n", 5853 sel, in_src_str[sel]); 5854 5855 spec->in_enum_val = sel; 5856 5857 ca0132_alt_select_in(codec); 5858 5859 return 1; 5860 } 5861 5862 /* Sound Blaster Z Output Select Control */ 5863 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol, 5864 struct snd_ctl_elem_info *uinfo) 5865 { 5866 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5867 uinfo->count = 1; 5868 uinfo->value.enumerated.items = NUM_OF_OUTPUTS; 5869 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS) 5870 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1; 5871 strcpy(uinfo->value.enumerated.name, 5872 out_type_str[uinfo->value.enumerated.item]); 5873 return 0; 5874 } 5875 5876 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol, 5877 struct snd_ctl_elem_value *ucontrol) 5878 { 5879 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5880 struct ca0132_spec *spec = codec->spec; 5881 5882 ucontrol->value.enumerated.item[0] = spec->out_enum_val; 5883 return 0; 5884 } 5885 5886 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol, 5887 struct snd_ctl_elem_value *ucontrol) 5888 { 5889 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5890 struct ca0132_spec *spec = codec->spec; 5891 int sel = ucontrol->value.enumerated.item[0]; 5892 unsigned int items = NUM_OF_OUTPUTS; 5893 unsigned int auto_jack; 5894 5895 if (sel >= items) 5896 return 0; 5897 5898 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n", 5899 sel, out_type_str[sel]); 5900 5901 spec->out_enum_val = sel; 5902 5903 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 5904 5905 if (!auto_jack) 5906 ca0132_alt_select_out(codec); 5907 5908 return 1; 5909 } 5910 5911 /* Select surround output type: 2.1, 4.0, 4.1, or 5.1. */ 5912 static int ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol *kcontrol, 5913 struct snd_ctl_elem_info *uinfo) 5914 { 5915 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT; 5916 5917 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5918 uinfo->count = 1; 5919 uinfo->value.enumerated.items = items; 5920 if (uinfo->value.enumerated.item >= items) 5921 uinfo->value.enumerated.item = items - 1; 5922 strcpy(uinfo->value.enumerated.name, 5923 speaker_channel_cfgs[uinfo->value.enumerated.item].name); 5924 return 0; 5925 } 5926 5927 static int ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol *kcontrol, 5928 struct snd_ctl_elem_value *ucontrol) 5929 { 5930 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5931 struct ca0132_spec *spec = codec->spec; 5932 5933 ucontrol->value.enumerated.item[0] = spec->channel_cfg_val; 5934 return 0; 5935 } 5936 5937 static int ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol *kcontrol, 5938 struct snd_ctl_elem_value *ucontrol) 5939 { 5940 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5941 struct ca0132_spec *spec = codec->spec; 5942 int sel = ucontrol->value.enumerated.item[0]; 5943 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT; 5944 5945 if (sel >= items) 5946 return 0; 5947 5948 codec_dbg(codec, "ca0132_alt_speaker_channels: sel=%d, channels=%s\n", 5949 sel, speaker_channel_cfgs[sel].name); 5950 5951 spec->channel_cfg_val = sel; 5952 5953 if (spec->out_enum_val == SPEAKER_OUT) 5954 ca0132_alt_select_out(codec); 5955 5956 return 1; 5957 } 5958 5959 /* 5960 * Smart Volume output setting control. Three different settings, Normal, 5961 * which takes the value from the smart volume slider. The two others, loud 5962 * and night, disregard the slider value and have uneditable values. 5963 */ 5964 #define NUM_OF_SVM_SETTINGS 3 5965 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" }; 5966 5967 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol, 5968 struct snd_ctl_elem_info *uinfo) 5969 { 5970 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5971 uinfo->count = 1; 5972 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS; 5973 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS) 5974 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1; 5975 strcpy(uinfo->value.enumerated.name, 5976 out_svm_set_enum_str[uinfo->value.enumerated.item]); 5977 return 0; 5978 } 5979 5980 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol, 5981 struct snd_ctl_elem_value *ucontrol) 5982 { 5983 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5984 struct ca0132_spec *spec = codec->spec; 5985 5986 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting; 5987 return 0; 5988 } 5989 5990 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol, 5991 struct snd_ctl_elem_value *ucontrol) 5992 { 5993 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5994 struct ca0132_spec *spec = codec->spec; 5995 int sel = ucontrol->value.enumerated.item[0]; 5996 unsigned int items = NUM_OF_SVM_SETTINGS; 5997 unsigned int idx = SMART_VOLUME - EFFECT_START_NID; 5998 unsigned int tmp; 5999 6000 if (sel >= items) 6001 return 0; 6002 6003 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n", 6004 sel, out_svm_set_enum_str[sel]); 6005 6006 spec->smart_volume_setting = sel; 6007 6008 switch (sel) { 6009 case 0: 6010 tmp = FLOAT_ZERO; 6011 break; 6012 case 1: 6013 tmp = FLOAT_ONE; 6014 break; 6015 case 2: 6016 tmp = FLOAT_TWO; 6017 break; 6018 default: 6019 tmp = FLOAT_ZERO; 6020 break; 6021 } 6022 /* Req 2 is the Smart Volume Setting req. */ 6023 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 6024 ca0132_effects[idx].reqs[2], tmp); 6025 return 1; 6026 } 6027 6028 /* Sound Blaster Z EQ preset controls */ 6029 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol, 6030 struct snd_ctl_elem_info *uinfo) 6031 { 6032 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 6033 6034 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6035 uinfo->count = 1; 6036 uinfo->value.enumerated.items = items; 6037 if (uinfo->value.enumerated.item >= items) 6038 uinfo->value.enumerated.item = items - 1; 6039 strcpy(uinfo->value.enumerated.name, 6040 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name); 6041 return 0; 6042 } 6043 6044 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol, 6045 struct snd_ctl_elem_value *ucontrol) 6046 { 6047 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6048 struct ca0132_spec *spec = codec->spec; 6049 6050 ucontrol->value.enumerated.item[0] = spec->eq_preset_val; 6051 return 0; 6052 } 6053 6054 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol, 6055 struct snd_ctl_elem_value *ucontrol) 6056 { 6057 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6058 struct ca0132_spec *spec = codec->spec; 6059 int i, err = 0; 6060 int sel = ucontrol->value.enumerated.item[0]; 6061 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 6062 6063 if (sel >= items) 6064 return 0; 6065 6066 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel, 6067 ca0132_alt_eq_presets[sel].name); 6068 /* 6069 * Idx 0 is default. 6070 * Default needs to qualify with CrystalVoice state. 6071 */ 6072 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) { 6073 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid, 6074 ca0132_alt_eq_enum.reqs[i], 6075 ca0132_alt_eq_presets[sel].vals[i]); 6076 if (err < 0) 6077 break; 6078 } 6079 6080 if (err >= 0) 6081 spec->eq_preset_val = sel; 6082 6083 return 1; 6084 } 6085 6086 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol, 6087 struct snd_ctl_elem_info *uinfo) 6088 { 6089 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets); 6090 6091 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6092 uinfo->count = 1; 6093 uinfo->value.enumerated.items = items; 6094 if (uinfo->value.enumerated.item >= items) 6095 uinfo->value.enumerated.item = items - 1; 6096 strcpy(uinfo->value.enumerated.name, 6097 ca0132_voicefx_presets[uinfo->value.enumerated.item].name); 6098 return 0; 6099 } 6100 6101 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol, 6102 struct snd_ctl_elem_value *ucontrol) 6103 { 6104 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6105 struct ca0132_spec *spec = codec->spec; 6106 6107 ucontrol->value.enumerated.item[0] = spec->voicefx_val; 6108 return 0; 6109 } 6110 6111 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol, 6112 struct snd_ctl_elem_value *ucontrol) 6113 { 6114 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6115 struct ca0132_spec *spec = codec->spec; 6116 int i, err = 0; 6117 int sel = ucontrol->value.enumerated.item[0]; 6118 6119 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets)) 6120 return 0; 6121 6122 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n", 6123 sel, ca0132_voicefx_presets[sel].name); 6124 6125 /* 6126 * Idx 0 is default. 6127 * Default needs to qualify with CrystalVoice state. 6128 */ 6129 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) { 6130 err = dspio_set_uint_param(codec, ca0132_voicefx.mid, 6131 ca0132_voicefx.reqs[i], 6132 ca0132_voicefx_presets[sel].vals[i]); 6133 if (err < 0) 6134 break; 6135 } 6136 6137 if (err >= 0) { 6138 spec->voicefx_val = sel; 6139 /* enable voice fx */ 6140 ca0132_voicefx_set(codec, (sel ? 1 : 0)); 6141 } 6142 6143 return 1; 6144 } 6145 6146 static int ca0132_switch_get(struct snd_kcontrol *kcontrol, 6147 struct snd_ctl_elem_value *ucontrol) 6148 { 6149 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6150 struct ca0132_spec *spec = codec->spec; 6151 hda_nid_t nid = get_amp_nid(kcontrol); 6152 int ch = get_amp_channels(kcontrol); 6153 long *valp = ucontrol->value.integer.value; 6154 6155 /* vnode */ 6156 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 6157 if (ch & 1) { 6158 *valp = spec->vnode_lswitch[nid - VNODE_START_NID]; 6159 valp++; 6160 } 6161 if (ch & 2) { 6162 *valp = spec->vnode_rswitch[nid - VNODE_START_NID]; 6163 valp++; 6164 } 6165 return 0; 6166 } 6167 6168 /* effects, include PE and CrystalVoice */ 6169 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) { 6170 *valp = spec->effects_switch[nid - EFFECT_START_NID]; 6171 return 0; 6172 } 6173 6174 /* mic boost */ 6175 if (nid == spec->input_pins[0]) { 6176 *valp = spec->cur_mic_boost; 6177 return 0; 6178 } 6179 6180 if (nid == ZXR_HEADPHONE_GAIN) { 6181 *valp = spec->zxr_gain_set; 6182 return 0; 6183 } 6184 6185 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) { 6186 *valp = spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT]; 6187 return 0; 6188 } 6189 6190 if (nid == BASS_REDIRECTION) { 6191 *valp = spec->bass_redirection_val; 6192 return 0; 6193 } 6194 6195 return 0; 6196 } 6197 6198 static int ca0132_switch_put(struct snd_kcontrol *kcontrol, 6199 struct snd_ctl_elem_value *ucontrol) 6200 { 6201 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6202 struct ca0132_spec *spec = codec->spec; 6203 hda_nid_t nid = get_amp_nid(kcontrol); 6204 int ch = get_amp_channels(kcontrol); 6205 long *valp = ucontrol->value.integer.value; 6206 int changed = 1; 6207 6208 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n", 6209 nid, *valp); 6210 6211 snd_hda_power_up(codec); 6212 /* vnode */ 6213 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 6214 if (ch & 1) { 6215 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp; 6216 valp++; 6217 } 6218 if (ch & 2) { 6219 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp; 6220 valp++; 6221 } 6222 changed = ca0132_vnode_switch_set(kcontrol, ucontrol); 6223 goto exit; 6224 } 6225 6226 /* PE */ 6227 if (nid == PLAY_ENHANCEMENT) { 6228 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6229 changed = ca0132_pe_switch_set(codec); 6230 goto exit; 6231 } 6232 6233 /* CrystalVoice */ 6234 if (nid == CRYSTAL_VOICE) { 6235 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6236 changed = ca0132_cvoice_switch_set(codec); 6237 goto exit; 6238 } 6239 6240 /* out and in effects */ 6241 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) || 6242 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) { 6243 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6244 changed = ca0132_effects_set(codec, nid, *valp); 6245 goto exit; 6246 } 6247 6248 /* mic boost */ 6249 if (nid == spec->input_pins[0]) { 6250 spec->cur_mic_boost = *valp; 6251 if (ca0132_use_alt_functions(spec)) { 6252 if (spec->in_enum_val != REAR_LINE_IN) 6253 changed = ca0132_mic_boost_set(codec, *valp); 6254 } else { 6255 /* Mic boost does not apply to Digital Mic */ 6256 if (spec->cur_mic_type != DIGITAL_MIC) 6257 changed = ca0132_mic_boost_set(codec, *valp); 6258 } 6259 6260 goto exit; 6261 } 6262 6263 if (nid == ZXR_HEADPHONE_GAIN) { 6264 spec->zxr_gain_set = *valp; 6265 if (spec->cur_out_type == HEADPHONE_OUT) 6266 changed = zxr_headphone_gain_set(codec, *valp); 6267 else 6268 changed = 0; 6269 6270 goto exit; 6271 } 6272 6273 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) { 6274 spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT] = *valp; 6275 if (spec->cur_out_type == SPEAKER_OUT) 6276 ca0132_alt_set_full_range_speaker(codec); 6277 6278 changed = 0; 6279 } 6280 6281 if (nid == BASS_REDIRECTION) { 6282 spec->bass_redirection_val = *valp; 6283 if (spec->cur_out_type == SPEAKER_OUT) 6284 ca0132_alt_surround_set_bass_redirection(codec, *valp); 6285 6286 changed = 0; 6287 } 6288 6289 exit: 6290 snd_hda_power_down(codec); 6291 return changed; 6292 } 6293 6294 /* 6295 * Volume related 6296 */ 6297 /* 6298 * Sets the internal DSP decibel level to match the DAC for output, and the 6299 * ADC for input. Currently only the SBZ sets dsp capture volume level, and 6300 * all alternative codecs set DSP playback volume. 6301 */ 6302 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid) 6303 { 6304 struct ca0132_spec *spec = codec->spec; 6305 unsigned int dsp_dir; 6306 unsigned int lookup_val; 6307 6308 if (nid == VNID_SPK) 6309 dsp_dir = DSP_VOL_OUT; 6310 else 6311 dsp_dir = DSP_VOL_IN; 6312 6313 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID]; 6314 6315 dspio_set_uint_param(codec, 6316 ca0132_alt_vol_ctls[dsp_dir].mid, 6317 ca0132_alt_vol_ctls[dsp_dir].reqs[0], 6318 float_vol_db_lookup[lookup_val]); 6319 6320 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID]; 6321 6322 dspio_set_uint_param(codec, 6323 ca0132_alt_vol_ctls[dsp_dir].mid, 6324 ca0132_alt_vol_ctls[dsp_dir].reqs[1], 6325 float_vol_db_lookup[lookup_val]); 6326 6327 dspio_set_uint_param(codec, 6328 ca0132_alt_vol_ctls[dsp_dir].mid, 6329 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO); 6330 } 6331 6332 static int ca0132_volume_info(struct snd_kcontrol *kcontrol, 6333 struct snd_ctl_elem_info *uinfo) 6334 { 6335 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6336 struct ca0132_spec *spec = codec->spec; 6337 hda_nid_t nid = get_amp_nid(kcontrol); 6338 int ch = get_amp_channels(kcontrol); 6339 int dir = get_amp_direction(kcontrol); 6340 unsigned long pval; 6341 int err; 6342 6343 switch (nid) { 6344 case VNID_SPK: 6345 /* follow shared_out info */ 6346 nid = spec->shared_out_nid; 6347 mutex_lock(&codec->control_mutex); 6348 pval = kcontrol->private_value; 6349 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6350 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6351 kcontrol->private_value = pval; 6352 mutex_unlock(&codec->control_mutex); 6353 break; 6354 case VNID_MIC: 6355 /* follow shared_mic info */ 6356 nid = spec->shared_mic_nid; 6357 mutex_lock(&codec->control_mutex); 6358 pval = kcontrol->private_value; 6359 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6360 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6361 kcontrol->private_value = pval; 6362 mutex_unlock(&codec->control_mutex); 6363 break; 6364 default: 6365 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6366 } 6367 return err; 6368 } 6369 6370 static int ca0132_volume_get(struct snd_kcontrol *kcontrol, 6371 struct snd_ctl_elem_value *ucontrol) 6372 { 6373 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6374 struct ca0132_spec *spec = codec->spec; 6375 hda_nid_t nid = get_amp_nid(kcontrol); 6376 int ch = get_amp_channels(kcontrol); 6377 long *valp = ucontrol->value.integer.value; 6378 6379 /* store the left and right volume */ 6380 if (ch & 1) { 6381 *valp = spec->vnode_lvol[nid - VNODE_START_NID]; 6382 valp++; 6383 } 6384 if (ch & 2) { 6385 *valp = spec->vnode_rvol[nid - VNODE_START_NID]; 6386 valp++; 6387 } 6388 return 0; 6389 } 6390 6391 static int ca0132_volume_put(struct snd_kcontrol *kcontrol, 6392 struct snd_ctl_elem_value *ucontrol) 6393 { 6394 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6395 struct ca0132_spec *spec = codec->spec; 6396 hda_nid_t nid = get_amp_nid(kcontrol); 6397 int ch = get_amp_channels(kcontrol); 6398 long *valp = ucontrol->value.integer.value; 6399 hda_nid_t shared_nid = 0; 6400 bool effective; 6401 int changed = 1; 6402 6403 /* store the left and right volume */ 6404 if (ch & 1) { 6405 spec->vnode_lvol[nid - VNODE_START_NID] = *valp; 6406 valp++; 6407 } 6408 if (ch & 2) { 6409 spec->vnode_rvol[nid - VNODE_START_NID] = *valp; 6410 valp++; 6411 } 6412 6413 /* if effective conditions, then update hw immediately. */ 6414 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 6415 if (effective) { 6416 int dir = get_amp_direction(kcontrol); 6417 unsigned long pval; 6418 6419 snd_hda_power_up(codec); 6420 mutex_lock(&codec->control_mutex); 6421 pval = kcontrol->private_value; 6422 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 6423 0, dir); 6424 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 6425 kcontrol->private_value = pval; 6426 mutex_unlock(&codec->control_mutex); 6427 snd_hda_power_down(codec); 6428 } 6429 6430 return changed; 6431 } 6432 6433 /* 6434 * This function is the same as the one above, because using an if statement 6435 * inside of the above volume control for the DSP volume would cause too much 6436 * lag. This is a lot more smooth. 6437 */ 6438 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol, 6439 struct snd_ctl_elem_value *ucontrol) 6440 { 6441 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6442 struct ca0132_spec *spec = codec->spec; 6443 hda_nid_t nid = get_amp_nid(kcontrol); 6444 int ch = get_amp_channels(kcontrol); 6445 long *valp = ucontrol->value.integer.value; 6446 hda_nid_t vnid = 0; 6447 int changed; 6448 6449 switch (nid) { 6450 case 0x02: 6451 vnid = VNID_SPK; 6452 break; 6453 case 0x07: 6454 vnid = VNID_MIC; 6455 break; 6456 } 6457 6458 /* store the left and right volume */ 6459 if (ch & 1) { 6460 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp; 6461 valp++; 6462 } 6463 if (ch & 2) { 6464 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp; 6465 valp++; 6466 } 6467 6468 snd_hda_power_up(codec); 6469 ca0132_alt_dsp_volume_put(codec, vnid); 6470 mutex_lock(&codec->control_mutex); 6471 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 6472 mutex_unlock(&codec->control_mutex); 6473 snd_hda_power_down(codec); 6474 6475 return changed; 6476 } 6477 6478 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag, 6479 unsigned int size, unsigned int __user *tlv) 6480 { 6481 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6482 struct ca0132_spec *spec = codec->spec; 6483 hda_nid_t nid = get_amp_nid(kcontrol); 6484 int ch = get_amp_channels(kcontrol); 6485 int dir = get_amp_direction(kcontrol); 6486 unsigned long pval; 6487 int err; 6488 6489 switch (nid) { 6490 case VNID_SPK: 6491 /* follow shared_out tlv */ 6492 nid = spec->shared_out_nid; 6493 mutex_lock(&codec->control_mutex); 6494 pval = kcontrol->private_value; 6495 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6496 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6497 kcontrol->private_value = pval; 6498 mutex_unlock(&codec->control_mutex); 6499 break; 6500 case VNID_MIC: 6501 /* follow shared_mic tlv */ 6502 nid = spec->shared_mic_nid; 6503 mutex_lock(&codec->control_mutex); 6504 pval = kcontrol->private_value; 6505 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6506 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6507 kcontrol->private_value = pval; 6508 mutex_unlock(&codec->control_mutex); 6509 break; 6510 default: 6511 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6512 } 6513 return err; 6514 } 6515 6516 /* Add volume slider control for effect level */ 6517 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid, 6518 const char *pfx, int dir) 6519 { 6520 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6521 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6522 struct snd_kcontrol_new knew = 6523 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 6524 6525 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]); 6526 6527 knew.tlv.c = NULL; 6528 6529 switch (nid) { 6530 case XBASS_XOVER: 6531 knew.info = ca0132_alt_xbass_xover_slider_info; 6532 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 6533 knew.put = ca0132_alt_xbass_xover_slider_put; 6534 break; 6535 default: 6536 knew.info = ca0132_alt_effect_slider_info; 6537 knew.get = ca0132_alt_slider_ctl_get; 6538 knew.put = ca0132_alt_effect_slider_put; 6539 knew.private_value = 6540 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 6541 break; 6542 } 6543 6544 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6545 } 6546 6547 /* 6548 * Added FX: prefix for the alternative codecs, because otherwise the surround 6549 * effect would conflict with the Surround sound volume control. Also seems more 6550 * clear as to what the switches do. Left alone for others. 6551 */ 6552 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid, 6553 const char *pfx, int dir) 6554 { 6555 struct ca0132_spec *spec = codec->spec; 6556 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6557 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6558 struct snd_kcontrol_new knew = 6559 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type); 6560 /* If using alt_controls, add FX: prefix. But, don't add FX: 6561 * prefix to OutFX or InFX enable controls. 6562 */ 6563 if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID)) 6564 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]); 6565 else 6566 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]); 6567 6568 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6569 } 6570 6571 static int add_voicefx(struct hda_codec *codec) 6572 { 6573 struct snd_kcontrol_new knew = 6574 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name, 6575 VOICEFX, 1, 0, HDA_INPUT); 6576 knew.info = ca0132_voicefx_info; 6577 knew.get = ca0132_voicefx_get; 6578 knew.put = ca0132_voicefx_put; 6579 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec)); 6580 } 6581 6582 /* Create the EQ Preset control */ 6583 static int add_ca0132_alt_eq_presets(struct hda_codec *codec) 6584 { 6585 struct snd_kcontrol_new knew = 6586 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name, 6587 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT); 6588 knew.info = ca0132_alt_eq_preset_info; 6589 knew.get = ca0132_alt_eq_preset_get; 6590 knew.put = ca0132_alt_eq_preset_put; 6591 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM, 6592 snd_ctl_new1(&knew, codec)); 6593 } 6594 6595 /* 6596 * Add enumerated control for the three different settings of the smart volume 6597 * output effect. Normal just uses the slider value, and loud and night are 6598 * their own things that ignore that value. 6599 */ 6600 static int ca0132_alt_add_svm_enum(struct hda_codec *codec) 6601 { 6602 struct snd_kcontrol_new knew = 6603 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting", 6604 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT); 6605 knew.info = ca0132_alt_svm_setting_info; 6606 knew.get = ca0132_alt_svm_setting_get; 6607 knew.put = ca0132_alt_svm_setting_put; 6608 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM, 6609 snd_ctl_new1(&knew, codec)); 6610 6611 } 6612 6613 /* 6614 * Create an Output Select enumerated control for codecs with surround 6615 * out capabilities. 6616 */ 6617 static int ca0132_alt_add_output_enum(struct hda_codec *codec) 6618 { 6619 struct snd_kcontrol_new knew = 6620 HDA_CODEC_MUTE_MONO("Output Select", 6621 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT); 6622 knew.info = ca0132_alt_output_select_get_info; 6623 knew.get = ca0132_alt_output_select_get; 6624 knew.put = ca0132_alt_output_select_put; 6625 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM, 6626 snd_ctl_new1(&knew, codec)); 6627 } 6628 6629 /* 6630 * Add a control for selecting channel count on speaker output. Setting this 6631 * allows the DSP to do bass redirection and channel upmixing on surround 6632 * configurations. 6633 */ 6634 static int ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec *codec) 6635 { 6636 struct snd_kcontrol_new knew = 6637 HDA_CODEC_MUTE_MONO("Surround Channel Config", 6638 SPEAKER_CHANNEL_CFG_ENUM, 1, 0, HDA_OUTPUT); 6639 knew.info = ca0132_alt_speaker_channel_cfg_get_info; 6640 knew.get = ca0132_alt_speaker_channel_cfg_get; 6641 knew.put = ca0132_alt_speaker_channel_cfg_put; 6642 return snd_hda_ctl_add(codec, SPEAKER_CHANNEL_CFG_ENUM, 6643 snd_ctl_new1(&knew, codec)); 6644 } 6645 6646 /* 6647 * Full range front stereo and rear surround switches. When these are set to 6648 * full range, the lower frequencies from these channels are no longer 6649 * redirected to the LFE channel. 6650 */ 6651 static int ca0132_alt_add_front_full_range_switch(struct hda_codec *codec) 6652 { 6653 struct snd_kcontrol_new knew = 6654 CA0132_CODEC_MUTE_MONO("Full-Range Front Speakers", 6655 SPEAKER_FULL_RANGE_FRONT, 1, HDA_OUTPUT); 6656 6657 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_FRONT, 6658 snd_ctl_new1(&knew, codec)); 6659 } 6660 6661 static int ca0132_alt_add_rear_full_range_switch(struct hda_codec *codec) 6662 { 6663 struct snd_kcontrol_new knew = 6664 CA0132_CODEC_MUTE_MONO("Full-Range Rear Speakers", 6665 SPEAKER_FULL_RANGE_REAR, 1, HDA_OUTPUT); 6666 6667 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_REAR, 6668 snd_ctl_new1(&knew, codec)); 6669 } 6670 6671 /* 6672 * Bass redirection redirects audio below the crossover frequency to the LFE 6673 * channel on speakers that are set as not being full-range. On configurations 6674 * without an LFE channel, it does nothing. Bass redirection seems to be the 6675 * replacement for X-Bass on configurations with an LFE channel. 6676 */ 6677 static int ca0132_alt_add_bass_redirection_crossover(struct hda_codec *codec) 6678 { 6679 const char *namestr = "Bass Redirection Crossover"; 6680 struct snd_kcontrol_new knew = 6681 HDA_CODEC_VOLUME_MONO(namestr, BASS_REDIRECTION_XOVER, 1, 0, 6682 HDA_OUTPUT); 6683 6684 knew.tlv.c = NULL; 6685 knew.info = ca0132_alt_xbass_xover_slider_info; 6686 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 6687 knew.put = ca0132_alt_xbass_xover_slider_put; 6688 6689 return snd_hda_ctl_add(codec, BASS_REDIRECTION_XOVER, 6690 snd_ctl_new1(&knew, codec)); 6691 } 6692 6693 static int ca0132_alt_add_bass_redirection_switch(struct hda_codec *codec) 6694 { 6695 const char *namestr = "Bass Redirection"; 6696 struct snd_kcontrol_new knew = 6697 CA0132_CODEC_MUTE_MONO(namestr, BASS_REDIRECTION, 1, 6698 HDA_OUTPUT); 6699 6700 return snd_hda_ctl_add(codec, BASS_REDIRECTION, 6701 snd_ctl_new1(&knew, codec)); 6702 } 6703 6704 /* 6705 * Create an Input Source enumerated control for the alternate ca0132 codecs 6706 * because the front microphone has no auto-detect, and Line-in has to be set 6707 * somehow. 6708 */ 6709 static int ca0132_alt_add_input_enum(struct hda_codec *codec) 6710 { 6711 struct snd_kcontrol_new knew = 6712 HDA_CODEC_MUTE_MONO("Input Source", 6713 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT); 6714 knew.info = ca0132_alt_input_source_info; 6715 knew.get = ca0132_alt_input_source_get; 6716 knew.put = ca0132_alt_input_source_put; 6717 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM, 6718 snd_ctl_new1(&knew, codec)); 6719 } 6720 6721 /* 6722 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds 6723 * more control than the original mic boost, which is either full 30dB or off. 6724 */ 6725 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec) 6726 { 6727 struct snd_kcontrol_new knew = 6728 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch", 6729 MIC_BOOST_ENUM, 1, 0, HDA_INPUT); 6730 knew.info = ca0132_alt_mic_boost_info; 6731 knew.get = ca0132_alt_mic_boost_get; 6732 knew.put = ca0132_alt_mic_boost_put; 6733 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM, 6734 snd_ctl_new1(&knew, codec)); 6735 6736 } 6737 6738 /* 6739 * Add headphone gain enumerated control for the AE-5. This switches between 6740 * three modes, low, medium, and high. When non-headphone outputs are selected, 6741 * it is automatically set to high. This is the same behavior as Windows. 6742 */ 6743 static int ae5_add_headphone_gain_enum(struct hda_codec *codec) 6744 { 6745 struct snd_kcontrol_new knew = 6746 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain", 6747 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT); 6748 knew.info = ae5_headphone_gain_info; 6749 knew.get = ae5_headphone_gain_get; 6750 knew.put = ae5_headphone_gain_put; 6751 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM, 6752 snd_ctl_new1(&knew, codec)); 6753 } 6754 6755 /* 6756 * Add sound filter enumerated control for the AE-5. This adds three different 6757 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've 6758 * read into it, it changes the DAC's interpolation filter. 6759 */ 6760 static int ae5_add_sound_filter_enum(struct hda_codec *codec) 6761 { 6762 struct snd_kcontrol_new knew = 6763 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter", 6764 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT); 6765 knew.info = ae5_sound_filter_info; 6766 knew.get = ae5_sound_filter_get; 6767 knew.put = ae5_sound_filter_put; 6768 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM, 6769 snd_ctl_new1(&knew, codec)); 6770 } 6771 6772 static int zxr_add_headphone_gain_switch(struct hda_codec *codec) 6773 { 6774 struct snd_kcontrol_new knew = 6775 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain", 6776 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT); 6777 6778 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN, 6779 snd_ctl_new1(&knew, codec)); 6780 } 6781 6782 /* 6783 * Need to create follower controls for the alternate codecs that have surround 6784 * capabilities. 6785 */ 6786 static const char * const ca0132_alt_follower_pfxs[] = { 6787 "Front", "Surround", "Center", "LFE", NULL, 6788 }; 6789 6790 /* 6791 * Also need special channel map, because the default one is incorrect. 6792 * I think this has to do with the pin for rear surround being 0x11, 6793 * and the center/lfe being 0x10. Usually the pin order is the opposite. 6794 */ 6795 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = { 6796 { .channels = 2, 6797 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } }, 6798 { .channels = 4, 6799 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6800 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6801 { .channels = 6, 6802 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6803 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE, 6804 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6805 { } 6806 }; 6807 6808 /* Add the correct chmap for streams with 6 channels. */ 6809 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec) 6810 { 6811 int err = 0; 6812 struct hda_pcm *pcm; 6813 6814 list_for_each_entry(pcm, &codec->pcm_list_head, list) { 6815 struct hda_pcm_stream *hinfo = 6816 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 6817 struct snd_pcm_chmap *chmap; 6818 const struct snd_pcm_chmap_elem *elem; 6819 6820 elem = ca0132_alt_chmaps; 6821 if (hinfo->channels_max == 6) { 6822 err = snd_pcm_add_chmap_ctls(pcm->pcm, 6823 SNDRV_PCM_STREAM_PLAYBACK, 6824 elem, hinfo->channels_max, 0, &chmap); 6825 if (err < 0) 6826 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!"); 6827 } 6828 } 6829 } 6830 6831 /* 6832 * When changing Node IDs for Mixer Controls below, make sure to update 6833 * Node IDs in ca0132_config() as well. 6834 */ 6835 static const struct snd_kcontrol_new ca0132_mixer[] = { 6836 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT), 6837 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT), 6838 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 6839 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6840 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT), 6841 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT), 6842 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6843 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6844 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch", 6845 0x12, 1, HDA_INPUT), 6846 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch", 6847 VNID_HP_SEL, 1, HDA_OUTPUT), 6848 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch", 6849 VNID_AMIC1_SEL, 1, HDA_INPUT), 6850 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6851 VNID_HP_ASEL, 1, HDA_OUTPUT), 6852 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch", 6853 VNID_AMIC1_ASEL, 1, HDA_INPUT), 6854 { } /* end */ 6855 }; 6856 6857 /* 6858 * Desktop specific control mixer. Removes auto-detect for mic, and adds 6859 * surround controls. Also sets both the Front Playback and Capture Volume 6860 * controls to alt so they set the DSP's decibel level. 6861 */ 6862 static const struct snd_kcontrol_new desktop_mixer[] = { 6863 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 6864 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 6865 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 6866 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 6867 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 6868 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 6869 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 6870 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 6871 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT), 6872 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6873 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6874 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6875 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6876 VNID_HP_ASEL, 1, HDA_OUTPUT), 6877 { } /* end */ 6878 }; 6879 6880 /* 6881 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture 6882 * because it doesn't set decibel levels for the DSP for capture. 6883 */ 6884 static const struct snd_kcontrol_new r3di_mixer[] = { 6885 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 6886 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 6887 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 6888 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 6889 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 6890 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 6891 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 6892 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 6893 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 6894 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6895 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6896 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6897 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6898 VNID_HP_ASEL, 1, HDA_OUTPUT), 6899 { } /* end */ 6900 }; 6901 6902 static int ca0132_build_controls(struct hda_codec *codec) 6903 { 6904 struct ca0132_spec *spec = codec->spec; 6905 int i, num_fx, num_sliders; 6906 int err = 0; 6907 6908 /* Add Mixer controls */ 6909 for (i = 0; i < spec->num_mixers; i++) { 6910 err = snd_hda_add_new_ctls(codec, spec->mixers[i]); 6911 if (err < 0) 6912 return err; 6913 } 6914 /* Setup vmaster with surround followers for desktop ca0132 devices */ 6915 if (ca0132_use_alt_functions(spec)) { 6916 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT, 6917 spec->tlv); 6918 snd_hda_add_vmaster(codec, "Master Playback Volume", 6919 spec->tlv, ca0132_alt_follower_pfxs, 6920 "Playback Volume"); 6921 err = __snd_hda_add_vmaster(codec, "Master Playback Switch", 6922 NULL, ca0132_alt_follower_pfxs, 6923 "Playback Switch", 6924 true, &spec->vmaster_mute.sw_kctl); 6925 if (err < 0) 6926 return err; 6927 } 6928 6929 /* Add in and out effects controls. 6930 * VoiceFX, PE and CrystalVoice are added separately. 6931 */ 6932 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 6933 for (i = 0; i < num_fx; i++) { 6934 /* Desktop cards break if Echo Cancellation is used. */ 6935 if (ca0132_use_pci_mmio(spec)) { 6936 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID + 6937 OUT_EFFECTS_COUNT)) 6938 continue; 6939 } 6940 6941 err = add_fx_switch(codec, ca0132_effects[i].nid, 6942 ca0132_effects[i].name, 6943 ca0132_effects[i].direct); 6944 if (err < 0) 6945 return err; 6946 } 6947 /* 6948 * If codec has use_alt_controls set to true, add effect level sliders, 6949 * EQ presets, and Smart Volume presets. Also, change names to add FX 6950 * prefix, and change PlayEnhancement and CrystalVoice to match. 6951 */ 6952 if (ca0132_use_alt_controls(spec)) { 6953 err = ca0132_alt_add_svm_enum(codec); 6954 if (err < 0) 6955 return err; 6956 6957 err = add_ca0132_alt_eq_presets(codec); 6958 if (err < 0) 6959 return err; 6960 6961 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 6962 "Enable OutFX", 0); 6963 if (err < 0) 6964 return err; 6965 6966 err = add_fx_switch(codec, CRYSTAL_VOICE, 6967 "Enable InFX", 1); 6968 if (err < 0) 6969 return err; 6970 6971 num_sliders = OUT_EFFECTS_COUNT - 1; 6972 for (i = 0; i < num_sliders; i++) { 6973 err = ca0132_alt_add_effect_slider(codec, 6974 ca0132_effects[i].nid, 6975 ca0132_effects[i].name, 6976 ca0132_effects[i].direct); 6977 if (err < 0) 6978 return err; 6979 } 6980 6981 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER, 6982 "X-Bass Crossover", EFX_DIR_OUT); 6983 6984 if (err < 0) 6985 return err; 6986 } else { 6987 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 6988 "PlayEnhancement", 0); 6989 if (err < 0) 6990 return err; 6991 6992 err = add_fx_switch(codec, CRYSTAL_VOICE, 6993 "CrystalVoice", 1); 6994 if (err < 0) 6995 return err; 6996 } 6997 err = add_voicefx(codec); 6998 if (err < 0) 6999 return err; 7000 7001 /* 7002 * If the codec uses alt_functions, you need the enumerated controls 7003 * to select the new outputs and inputs, plus add the new mic boost 7004 * setting control. 7005 */ 7006 if (ca0132_use_alt_functions(spec)) { 7007 err = ca0132_alt_add_output_enum(codec); 7008 if (err < 0) 7009 return err; 7010 err = ca0132_alt_add_speaker_channel_cfg_enum(codec); 7011 if (err < 0) 7012 return err; 7013 err = ca0132_alt_add_front_full_range_switch(codec); 7014 if (err < 0) 7015 return err; 7016 err = ca0132_alt_add_rear_full_range_switch(codec); 7017 if (err < 0) 7018 return err; 7019 err = ca0132_alt_add_bass_redirection_crossover(codec); 7020 if (err < 0) 7021 return err; 7022 err = ca0132_alt_add_bass_redirection_switch(codec); 7023 if (err < 0) 7024 return err; 7025 err = ca0132_alt_add_mic_boost_enum(codec); 7026 if (err < 0) 7027 return err; 7028 /* 7029 * ZxR only has microphone input, there is no front panel 7030 * header on the card, and aux-in is handled by the DBPro board. 7031 */ 7032 if (ca0132_quirk(spec) != QUIRK_ZXR) { 7033 err = ca0132_alt_add_input_enum(codec); 7034 if (err < 0) 7035 return err; 7036 } 7037 } 7038 7039 switch (ca0132_quirk(spec)) { 7040 case QUIRK_AE5: 7041 case QUIRK_AE7: 7042 err = ae5_add_headphone_gain_enum(codec); 7043 if (err < 0) 7044 return err; 7045 err = ae5_add_sound_filter_enum(codec); 7046 if (err < 0) 7047 return err; 7048 break; 7049 case QUIRK_ZXR: 7050 err = zxr_add_headphone_gain_switch(codec); 7051 if (err < 0) 7052 return err; 7053 break; 7054 default: 7055 break; 7056 } 7057 7058 #ifdef ENABLE_TUNING_CONTROLS 7059 add_tuning_ctls(codec); 7060 #endif 7061 7062 err = snd_hda_jack_add_kctls(codec, &spec->autocfg); 7063 if (err < 0) 7064 return err; 7065 7066 if (spec->dig_out) { 7067 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 7068 spec->dig_out); 7069 if (err < 0) 7070 return err; 7071 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout); 7072 if (err < 0) 7073 return err; 7074 /* spec->multiout.share_spdif = 1; */ 7075 } 7076 7077 if (spec->dig_in) { 7078 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 7079 if (err < 0) 7080 return err; 7081 } 7082 7083 if (ca0132_use_alt_functions(spec)) 7084 ca0132_alt_add_chmap_ctls(codec); 7085 7086 return 0; 7087 } 7088 7089 static int dbpro_build_controls(struct hda_codec *codec) 7090 { 7091 struct ca0132_spec *spec = codec->spec; 7092 int err = 0; 7093 7094 if (spec->dig_out) { 7095 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 7096 spec->dig_out); 7097 if (err < 0) 7098 return err; 7099 } 7100 7101 if (spec->dig_in) { 7102 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 7103 if (err < 0) 7104 return err; 7105 } 7106 7107 return 0; 7108 } 7109 7110 /* 7111 * PCM 7112 */ 7113 static const struct hda_pcm_stream ca0132_pcm_analog_playback = { 7114 .substreams = 1, 7115 .channels_min = 2, 7116 .channels_max = 6, 7117 .ops = { 7118 .prepare = ca0132_playback_pcm_prepare, 7119 .cleanup = ca0132_playback_pcm_cleanup, 7120 .get_delay = ca0132_playback_pcm_delay, 7121 }, 7122 }; 7123 7124 static const struct hda_pcm_stream ca0132_pcm_analog_capture = { 7125 .substreams = 1, 7126 .channels_min = 2, 7127 .channels_max = 2, 7128 .ops = { 7129 .prepare = ca0132_capture_pcm_prepare, 7130 .cleanup = ca0132_capture_pcm_cleanup, 7131 .get_delay = ca0132_capture_pcm_delay, 7132 }, 7133 }; 7134 7135 static const struct hda_pcm_stream ca0132_pcm_digital_playback = { 7136 .substreams = 1, 7137 .channels_min = 2, 7138 .channels_max = 2, 7139 .ops = { 7140 .open = ca0132_dig_playback_pcm_open, 7141 .close = ca0132_dig_playback_pcm_close, 7142 .prepare = ca0132_dig_playback_pcm_prepare, 7143 .cleanup = ca0132_dig_playback_pcm_cleanup 7144 }, 7145 }; 7146 7147 static const struct hda_pcm_stream ca0132_pcm_digital_capture = { 7148 .substreams = 1, 7149 .channels_min = 2, 7150 .channels_max = 2, 7151 }; 7152 7153 static int ca0132_build_pcms(struct hda_codec *codec) 7154 { 7155 struct ca0132_spec *spec = codec->spec; 7156 struct hda_pcm *info; 7157 7158 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog"); 7159 if (!info) 7160 return -ENOMEM; 7161 if (ca0132_use_alt_functions(spec)) { 7162 info->own_chmap = true; 7163 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap 7164 = ca0132_alt_chmaps; 7165 } 7166 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback; 7167 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0]; 7168 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max = 7169 spec->multiout.max_channels; 7170 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7171 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7172 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 7173 7174 /* With the DSP enabled, desktops don't use this ADC. */ 7175 if (!ca0132_use_alt_functions(spec)) { 7176 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2"); 7177 if (!info) 7178 return -ENOMEM; 7179 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7180 ca0132_pcm_analog_capture; 7181 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7182 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1]; 7183 } 7184 7185 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear"); 7186 if (!info) 7187 return -ENOMEM; 7188 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7189 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7190 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2]; 7191 7192 if (!spec->dig_out && !spec->dig_in) 7193 return 0; 7194 7195 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 7196 if (!info) 7197 return -ENOMEM; 7198 info->pcm_type = HDA_PCM_TYPE_SPDIF; 7199 if (spec->dig_out) { 7200 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 7201 ca0132_pcm_digital_playback; 7202 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 7203 } 7204 if (spec->dig_in) { 7205 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7206 ca0132_pcm_digital_capture; 7207 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 7208 } 7209 7210 return 0; 7211 } 7212 7213 static int dbpro_build_pcms(struct hda_codec *codec) 7214 { 7215 struct ca0132_spec *spec = codec->spec; 7216 struct hda_pcm *info; 7217 7218 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog"); 7219 if (!info) 7220 return -ENOMEM; 7221 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7222 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7223 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 7224 7225 7226 if (!spec->dig_out && !spec->dig_in) 7227 return 0; 7228 7229 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 7230 if (!info) 7231 return -ENOMEM; 7232 info->pcm_type = HDA_PCM_TYPE_SPDIF; 7233 if (spec->dig_out) { 7234 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 7235 ca0132_pcm_digital_playback; 7236 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 7237 } 7238 if (spec->dig_in) { 7239 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7240 ca0132_pcm_digital_capture; 7241 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 7242 } 7243 7244 return 0; 7245 } 7246 7247 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac) 7248 { 7249 if (pin) { 7250 snd_hda_set_pin_ctl(codec, pin, PIN_HP); 7251 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 7252 snd_hda_codec_write(codec, pin, 0, 7253 AC_VERB_SET_AMP_GAIN_MUTE, 7254 AMP_OUT_UNMUTE); 7255 } 7256 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP)) 7257 snd_hda_codec_write(codec, dac, 0, 7258 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO); 7259 } 7260 7261 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc) 7262 { 7263 if (pin) { 7264 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80); 7265 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP) 7266 snd_hda_codec_write(codec, pin, 0, 7267 AC_VERB_SET_AMP_GAIN_MUTE, 7268 AMP_IN_UNMUTE(0)); 7269 } 7270 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) { 7271 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE, 7272 AMP_IN_UNMUTE(0)); 7273 7274 /* init to 0 dB and unmute. */ 7275 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 7276 HDA_AMP_VOLMASK, 0x5a); 7277 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 7278 HDA_AMP_MUTE, 0); 7279 } 7280 } 7281 7282 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir) 7283 { 7284 unsigned int caps; 7285 7286 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ? 7287 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP); 7288 snd_hda_override_amp_caps(codec, nid, dir, caps); 7289 } 7290 7291 /* 7292 * Switch between Digital built-in mic and analog mic. 7293 */ 7294 static void ca0132_set_dmic(struct hda_codec *codec, int enable) 7295 { 7296 struct ca0132_spec *spec = codec->spec; 7297 unsigned int tmp; 7298 u8 val; 7299 unsigned int oldval; 7300 7301 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable); 7302 7303 oldval = stop_mic1(codec); 7304 ca0132_set_vipsource(codec, 0); 7305 if (enable) { 7306 /* set DMic input as 2-ch */ 7307 tmp = FLOAT_TWO; 7308 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7309 7310 val = spec->dmic_ctl; 7311 val |= 0x80; 7312 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7313 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7314 7315 if (!(spec->dmic_ctl & 0x20)) 7316 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1); 7317 } else { 7318 /* set AMic input as mono */ 7319 tmp = FLOAT_ONE; 7320 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7321 7322 val = spec->dmic_ctl; 7323 /* clear bit7 and bit5 to disable dmic */ 7324 val &= 0x5f; 7325 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7326 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7327 7328 if (!(spec->dmic_ctl & 0x20)) 7329 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0); 7330 } 7331 ca0132_set_vipsource(codec, 1); 7332 resume_mic1(codec, oldval); 7333 } 7334 7335 /* 7336 * Initialization for Digital Mic. 7337 */ 7338 static void ca0132_init_dmic(struct hda_codec *codec) 7339 { 7340 struct ca0132_spec *spec = codec->spec; 7341 u8 val; 7342 7343 /* Setup Digital Mic here, but don't enable. 7344 * Enable based on jack detect. 7345 */ 7346 7347 /* MCLK uses MPIO1, set to enable. 7348 * Bit 2-0: MPIO select 7349 * Bit 3: set to disable 7350 * Bit 7-4: reserved 7351 */ 7352 val = 0x01; 7353 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7354 VENDOR_CHIPIO_DMIC_MCLK_SET, val); 7355 7356 /* Data1 uses MPIO3. Data2 not use 7357 * Bit 2-0: Data1 MPIO select 7358 * Bit 3: set disable Data1 7359 * Bit 6-4: Data2 MPIO select 7360 * Bit 7: set disable Data2 7361 */ 7362 val = 0x83; 7363 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7364 VENDOR_CHIPIO_DMIC_PIN_SET, val); 7365 7366 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first. 7367 * Bit 3-0: Channel mask 7368 * Bit 4: set for 48KHz, clear for 32KHz 7369 * Bit 5: mode 7370 * Bit 6: set to select Data2, clear for Data1 7371 * Bit 7: set to enable DMic, clear for AMic 7372 */ 7373 if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4) 7374 val = 0x33; 7375 else 7376 val = 0x23; 7377 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */ 7378 spec->dmic_ctl = val; 7379 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7380 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7381 } 7382 7383 /* 7384 * Initialization for Analog Mic 2 7385 */ 7386 static void ca0132_init_analog_mic2(struct hda_codec *codec) 7387 { 7388 struct ca0132_spec *spec = codec->spec; 7389 7390 mutex_lock(&spec->chipio_mutex); 7391 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7392 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); 7393 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7394 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 7395 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7396 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 7397 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7398 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D); 7399 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7400 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 7401 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7402 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 7403 mutex_unlock(&spec->chipio_mutex); 7404 } 7405 7406 static void ca0132_refresh_widget_caps(struct hda_codec *codec) 7407 { 7408 struct ca0132_spec *spec = codec->spec; 7409 int i; 7410 7411 codec_dbg(codec, "ca0132_refresh_widget_caps.\n"); 7412 snd_hda_codec_update_widgets(codec); 7413 7414 for (i = 0; i < spec->multiout.num_dacs; i++) 7415 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT); 7416 7417 for (i = 0; i < spec->num_outputs; i++) 7418 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT); 7419 7420 for (i = 0; i < spec->num_inputs; i++) { 7421 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT); 7422 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT); 7423 } 7424 } 7425 7426 /* 7427 * Default speaker tuning values setup for alternative codecs. 7428 */ 7429 static const unsigned int sbz_default_delay_values[] = { 7430 /* Non-zero values are floating point 0.000198. */ 7431 0x394f9e38, 0x394f9e38, 0x00000000, 0x00000000, 0x00000000, 0x00000000 7432 }; 7433 7434 static const unsigned int zxr_default_delay_values[] = { 7435 /* Non-zero values are floating point 0.000220. */ 7436 0x00000000, 0x00000000, 0x3966afcd, 0x3966afcd, 0x3966afcd, 0x3966afcd 7437 }; 7438 7439 static const unsigned int ae5_default_delay_values[] = { 7440 /* Non-zero values are floating point 0.000100. */ 7441 0x00000000, 0x00000000, 0x38d1b717, 0x38d1b717, 0x38d1b717, 0x38d1b717 7442 }; 7443 7444 /* 7445 * If we never change these, probably only need them on initialization. 7446 */ 7447 static void ca0132_alt_init_speaker_tuning(struct hda_codec *codec) 7448 { 7449 struct ca0132_spec *spec = codec->spec; 7450 unsigned int i, tmp, start_req, end_req; 7451 const unsigned int *values; 7452 7453 switch (ca0132_quirk(spec)) { 7454 case QUIRK_SBZ: 7455 values = sbz_default_delay_values; 7456 break; 7457 case QUIRK_ZXR: 7458 values = zxr_default_delay_values; 7459 break; 7460 case QUIRK_AE5: 7461 case QUIRK_AE7: 7462 values = ae5_default_delay_values; 7463 break; 7464 default: 7465 values = sbz_default_delay_values; 7466 break; 7467 } 7468 7469 tmp = FLOAT_ZERO; 7470 dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_ENABLE_CENTER_EQ, tmp); 7471 7472 start_req = SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL; 7473 end_req = SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL; 7474 for (i = start_req; i < end_req + 1; i++) 7475 dspio_set_uint_param(codec, 0x96, i, tmp); 7476 7477 start_req = SPEAKER_TUNING_FRONT_LEFT_INVERT; 7478 end_req = SPEAKER_TUNING_REAR_RIGHT_INVERT; 7479 for (i = start_req; i < end_req + 1; i++) 7480 dspio_set_uint_param(codec, 0x96, i, tmp); 7481 7482 7483 for (i = 0; i < 6; i++) 7484 dspio_set_uint_param(codec, 0x96, 7485 SPEAKER_TUNING_FRONT_LEFT_DELAY + i, values[i]); 7486 } 7487 7488 /* 7489 * Creates a dummy stream to bind the output to. This seems to have to be done 7490 * after changing the main outputs source and destination streams. 7491 */ 7492 static void ca0132_alt_create_dummy_stream(struct hda_codec *codec) 7493 { 7494 struct ca0132_spec *spec = codec->spec; 7495 unsigned int stream_format; 7496 7497 stream_format = snd_hdac_calc_stream_format(48000, 2, 7498 SNDRV_PCM_FORMAT_S32_LE, 32, 0); 7499 7500 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id, 7501 0, stream_format); 7502 7503 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 7504 } 7505 7506 /* 7507 * Initialize mic for non-chromebook ca0132 implementations. 7508 */ 7509 static void ca0132_alt_init_analog_mics(struct hda_codec *codec) 7510 { 7511 struct ca0132_spec *spec = codec->spec; 7512 unsigned int tmp; 7513 7514 /* Mic 1 Setup */ 7515 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7516 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7517 if (ca0132_quirk(spec) == QUIRK_R3DI) { 7518 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 7519 tmp = FLOAT_ONE; 7520 } else 7521 tmp = FLOAT_THREE; 7522 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7523 7524 /* Mic 2 setup (not present on desktop cards) */ 7525 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000); 7526 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000); 7527 if (ca0132_quirk(spec) == QUIRK_R3DI) 7528 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 7529 tmp = FLOAT_ZERO; 7530 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 7531 } 7532 7533 /* 7534 * Sets the source of stream 0x14 to connpointID 0x48, and the destination 7535 * connpointID to 0x91. If this isn't done, the destination is 0x71, and 7536 * you get no sound. I'm guessing this has to do with the Sound Blaster Z 7537 * having an updated DAC, which changes the destination to that DAC. 7538 */ 7539 static void sbz_connect_streams(struct hda_codec *codec) 7540 { 7541 struct ca0132_spec *spec = codec->spec; 7542 7543 mutex_lock(&spec->chipio_mutex); 7544 7545 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n"); 7546 7547 chipio_set_stream_channels(codec, 0x0C, 6); 7548 chipio_set_stream_control(codec, 0x0C, 1); 7549 7550 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */ 7551 chipio_write_no_mutex(codec, 0x18a020, 0x00000043); 7552 7553 /* Setup stream 0x14 with it's source and destination points */ 7554 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91); 7555 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000); 7556 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000); 7557 chipio_set_stream_channels(codec, 0x14, 2); 7558 chipio_set_stream_control(codec, 0x14, 1); 7559 7560 codec_dbg(codec, "Connect Streams exited, mutex released.\n"); 7561 7562 mutex_unlock(&spec->chipio_mutex); 7563 } 7564 7565 /* 7566 * Write data through ChipIO to setup proper stream destinations. 7567 * Not sure how it exactly works, but it seems to direct data 7568 * to different destinations. Example is f8 to c0, e0 to c0. 7569 * All I know is, if you don't set these, you get no sound. 7570 */ 7571 static void sbz_chipio_startup_data(struct hda_codec *codec) 7572 { 7573 struct ca0132_spec *spec = codec->spec; 7574 7575 mutex_lock(&spec->chipio_mutex); 7576 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n"); 7577 7578 /* These control audio output */ 7579 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0); 7580 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1); 7581 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6); 7582 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7); 7583 /* Signal to update I think */ 7584 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 7585 7586 chipio_set_stream_channels(codec, 0x0C, 6); 7587 chipio_set_stream_control(codec, 0x0C, 1); 7588 /* No clue what these control */ 7589 if (ca0132_quirk(spec) == QUIRK_SBZ) { 7590 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0); 7591 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1); 7592 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2); 7593 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3); 7594 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4); 7595 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5); 7596 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6); 7597 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7); 7598 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8); 7599 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9); 7600 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca); 7601 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb); 7602 } else if (ca0132_quirk(spec) == QUIRK_ZXR) { 7603 chipio_write_no_mutex(codec, 0x190038, 0x000140c2); 7604 chipio_write_no_mutex(codec, 0x19003c, 0x000141c3); 7605 chipio_write_no_mutex(codec, 0x190040, 0x000150c4); 7606 chipio_write_no_mutex(codec, 0x190044, 0x000151c5); 7607 chipio_write_no_mutex(codec, 0x190050, 0x000142c8); 7608 chipio_write_no_mutex(codec, 0x190054, 0x000143c9); 7609 chipio_write_no_mutex(codec, 0x190058, 0x000152ca); 7610 chipio_write_no_mutex(codec, 0x19005c, 0x000153cb); 7611 } 7612 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 7613 7614 codec_dbg(codec, "Startup Data exited, mutex released.\n"); 7615 mutex_unlock(&spec->chipio_mutex); 7616 } 7617 7618 /* 7619 * Custom DSP SCP commands where the src value is 0x00 instead of 0x20. This is 7620 * done after the DSP is loaded. 7621 */ 7622 static void ca0132_alt_dsp_scp_startup(struct hda_codec *codec) 7623 { 7624 struct ca0132_spec *spec = codec->spec; 7625 unsigned int tmp, i; 7626 7627 /* 7628 * Gotta run these twice, or else mic works inconsistently. Not clear 7629 * why this is, but multiple tests have confirmed it. 7630 */ 7631 for (i = 0; i < 2; i++) { 7632 switch (ca0132_quirk(spec)) { 7633 case QUIRK_SBZ: 7634 case QUIRK_AE5: 7635 case QUIRK_AE7: 7636 tmp = 0x00000003; 7637 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7638 tmp = 0x00000000; 7639 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp); 7640 tmp = 0x00000001; 7641 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp); 7642 tmp = 0x00000004; 7643 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7644 tmp = 0x00000005; 7645 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7646 tmp = 0x00000000; 7647 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7648 break; 7649 case QUIRK_R3D: 7650 case QUIRK_R3DI: 7651 tmp = 0x00000000; 7652 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp); 7653 tmp = 0x00000001; 7654 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp); 7655 tmp = 0x00000004; 7656 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7657 tmp = 0x00000005; 7658 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7659 tmp = 0x00000000; 7660 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7661 break; 7662 default: 7663 break; 7664 } 7665 msleep(100); 7666 } 7667 } 7668 7669 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec) 7670 { 7671 struct ca0132_spec *spec = codec->spec; 7672 unsigned int tmp; 7673 7674 chipio_set_stream_control(codec, 0x03, 0); 7675 chipio_set_stream_control(codec, 0x04, 0); 7676 7677 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7678 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7679 7680 tmp = FLOAT_THREE; 7681 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7682 7683 chipio_set_stream_control(codec, 0x03, 1); 7684 chipio_set_stream_control(codec, 0x04, 1); 7685 7686 switch (ca0132_quirk(spec)) { 7687 case QUIRK_SBZ: 7688 chipio_write(codec, 0x18b098, 0x0000000c); 7689 chipio_write(codec, 0x18b09C, 0x0000000c); 7690 break; 7691 case QUIRK_AE5: 7692 chipio_write(codec, 0x18b098, 0x0000000c); 7693 chipio_write(codec, 0x18b09c, 0x0000004c); 7694 break; 7695 default: 7696 break; 7697 } 7698 } 7699 7700 static void ae5_post_dsp_register_set(struct hda_codec *codec) 7701 { 7702 struct ca0132_spec *spec = codec->spec; 7703 7704 chipio_8051_write_direct(codec, 0x93, 0x10); 7705 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7706 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44); 7707 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7708 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2); 7709 7710 writeb(0xff, spec->mem_base + 0x304); 7711 writeb(0xff, spec->mem_base + 0x304); 7712 writeb(0xff, spec->mem_base + 0x304); 7713 writeb(0xff, spec->mem_base + 0x304); 7714 writeb(0x00, spec->mem_base + 0x100); 7715 writeb(0xff, spec->mem_base + 0x304); 7716 writeb(0x00, spec->mem_base + 0x100); 7717 writeb(0xff, spec->mem_base + 0x304); 7718 writeb(0x00, spec->mem_base + 0x100); 7719 writeb(0xff, spec->mem_base + 0x304); 7720 writeb(0x00, spec->mem_base + 0x100); 7721 writeb(0xff, spec->mem_base + 0x304); 7722 7723 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f); 7724 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 7725 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7726 } 7727 7728 static void ae5_post_dsp_param_setup(struct hda_codec *codec) 7729 { 7730 /* 7731 * Param3 in the 8051's memory is represented by the ascii string 'mch' 7732 * which seems to be 'multichannel'. This is also mentioned in the 7733 * AE-5's registry values in Windows. 7734 */ 7735 chipio_set_control_param(codec, 3, 0); 7736 /* 7737 * I believe ASI is 'audio serial interface' and that it's used to 7738 * change colors on the external LED strip connected to the AE-5. 7739 */ 7740 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); 7741 7742 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); 7743 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 7744 7745 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7746 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92); 7747 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7748 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa); 7749 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7750 VENDOR_CHIPIO_8051_DATA_WRITE, 0x22); 7751 } 7752 7753 static void ae5_post_dsp_pll_setup(struct hda_codec *codec) 7754 { 7755 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7756 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41); 7757 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7758 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8); 7759 7760 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7761 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x45); 7762 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7763 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcc); 7764 7765 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7766 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x40); 7767 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7768 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcb); 7769 7770 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7771 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43); 7772 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7773 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7); 7774 7775 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7776 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x51); 7777 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7778 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x8d); 7779 } 7780 7781 static void ae5_post_dsp_stream_setup(struct hda_codec *codec) 7782 { 7783 struct ca0132_spec *spec = codec->spec; 7784 7785 mutex_lock(&spec->chipio_mutex); 7786 7787 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); 7788 7789 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); 7790 7791 chipio_set_stream_channels(codec, 0x0C, 6); 7792 chipio_set_stream_control(codec, 0x0C, 1); 7793 7794 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0); 7795 7796 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0); 7797 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 7798 chipio_set_stream_channels(codec, 0x18, 6); 7799 chipio_set_stream_control(codec, 0x18, 1); 7800 7801 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); 7802 7803 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7804 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43); 7805 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7806 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7); 7807 7808 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80); 7809 7810 mutex_unlock(&spec->chipio_mutex); 7811 } 7812 7813 static void ae5_post_dsp_startup_data(struct hda_codec *codec) 7814 { 7815 struct ca0132_spec *spec = codec->spec; 7816 7817 mutex_lock(&spec->chipio_mutex); 7818 7819 chipio_write_no_mutex(codec, 0x189000, 0x0001f101); 7820 chipio_write_no_mutex(codec, 0x189004, 0x0001f101); 7821 chipio_write_no_mutex(codec, 0x189024, 0x00014004); 7822 chipio_write_no_mutex(codec, 0x189028, 0x0002000f); 7823 7824 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 7825 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 7826 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12); 7827 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00); 7828 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48); 7829 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 7830 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7831 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 7832 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 7833 ca0113_mmio_gpio_set(codec, 0, true); 7834 ca0113_mmio_gpio_set(codec, 1, true); 7835 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80); 7836 7837 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012); 7838 7839 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 7840 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 7841 7842 mutex_unlock(&spec->chipio_mutex); 7843 } 7844 7845 static const unsigned int ae7_port_set_data[] = { 7846 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3, 0x0001e2c4, 0x0001e3c5, 7847 0x0001e8c6, 0x0001e9c7, 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb 7848 }; 7849 7850 static void ae7_post_dsp_setup_ports(struct hda_codec *codec) 7851 { 7852 struct ca0132_spec *spec = codec->spec; 7853 unsigned int i, count, addr; 7854 7855 mutex_lock(&spec->chipio_mutex); 7856 7857 chipio_set_stream_channels(codec, 0x0c, 6); 7858 chipio_set_stream_control(codec, 0x0c, 1); 7859 7860 count = ARRAY_SIZE(ae7_port_set_data); 7861 addr = 0x190030; 7862 for (i = 0; i < count; i++) { 7863 chipio_write_no_mutex(codec, addr, ae7_port_set_data[i]); 7864 7865 /* Addresses are incremented by 4-bytes. */ 7866 addr += 0x04; 7867 } 7868 7869 /* 7870 * Port setting always ends with a write of 0x1 to address 0x19042c. 7871 */ 7872 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 7873 7874 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 7875 ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40); 7876 ca0113_mmio_command_set(codec, 0x48, 0x17, 0x00); 7877 ca0113_mmio_command_set(codec, 0x48, 0x19, 0x00); 7878 ca0113_mmio_command_set(codec, 0x48, 0x11, 0xff); 7879 ca0113_mmio_command_set(codec, 0x48, 0x12, 0xff); 7880 ca0113_mmio_command_set(codec, 0x48, 0x13, 0xff); 7881 ca0113_mmio_command_set(codec, 0x48, 0x14, 0x7f); 7882 7883 mutex_unlock(&spec->chipio_mutex); 7884 } 7885 7886 static void ae7_post_dsp_asi_stream_setup(struct hda_codec *codec) 7887 { 7888 struct ca0132_spec *spec = codec->spec; 7889 7890 mutex_lock(&spec->chipio_mutex); 7891 7892 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); 7893 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 7894 7895 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); 7896 chipio_set_stream_channels(codec, 0x0c, 6); 7897 chipio_set_stream_control(codec, 0x0c, 1); 7898 7899 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00); 7900 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0); 7901 7902 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 7903 chipio_set_stream_channels(codec, 0x18, 6); 7904 chipio_set_stream_control(codec, 0x18, 1); 7905 7906 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); 7907 7908 mutex_unlock(&spec->chipio_mutex); 7909 } 7910 7911 static void ae7_post_dsp_pll_setup(struct hda_codec *codec) 7912 { 7913 static const unsigned int addr[] = { 7914 0x41, 0x45, 0x40, 0x43, 0x51 7915 }; 7916 static const unsigned int data[] = { 7917 0xc8, 0xcc, 0xcb, 0xc7, 0x8d 7918 }; 7919 unsigned int i; 7920 7921 for (i = 0; i < ARRAY_SIZE(addr); i++) { 7922 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7923 VENDOR_CHIPIO_8051_ADDRESS_LOW, addr[i]); 7924 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7925 VENDOR_CHIPIO_PLL_PMU_WRITE, data[i]); 7926 } 7927 } 7928 7929 static void ae7_post_dsp_asi_setup_ports(struct hda_codec *codec) 7930 { 7931 struct ca0132_spec *spec = codec->spec; 7932 static const unsigned int target[] = { 7933 0x0b, 0x04, 0x06, 0x0a, 0x0c, 0x11, 0x12, 0x13, 0x14 7934 }; 7935 static const unsigned int data[] = { 7936 0x12, 0x00, 0x48, 0x05, 0x5f, 0xff, 0xff, 0xff, 0x7f 7937 }; 7938 unsigned int i; 7939 7940 mutex_lock(&spec->chipio_mutex); 7941 7942 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7943 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43); 7944 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7945 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7); 7946 7947 chipio_write_no_mutex(codec, 0x189000, 0x0001f101); 7948 chipio_write_no_mutex(codec, 0x189004, 0x0001f101); 7949 chipio_write_no_mutex(codec, 0x189024, 0x00014004); 7950 chipio_write_no_mutex(codec, 0x189028, 0x0002000f); 7951 7952 ae7_post_dsp_pll_setup(codec); 7953 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 7954 7955 for (i = 0; i < ARRAY_SIZE(target); i++) 7956 ca0113_mmio_command_set(codec, 0x48, target[i], data[i]); 7957 7958 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 7959 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 7960 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 7961 7962 chipio_set_stream_source_dest(codec, 0x21, 0x64, 0x56); 7963 chipio_set_stream_channels(codec, 0x21, 2); 7964 chipio_set_conn_rate_no_mutex(codec, 0x56, SR_8_000); 7965 7966 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_NODE_ID, 0x09); 7967 /* 7968 * In the 8051's memory, this param is referred to as 'n2sid', which I 7969 * believe is 'node to streamID'. It seems to be a way to assign a 7970 * stream to a given HDA node. 7971 */ 7972 chipio_set_control_param_no_mutex(codec, 0x20, 0x21); 7973 7974 chipio_write_no_mutex(codec, 0x18b038, 0x00000088); 7975 7976 /* 7977 * Now, at this point on Windows, an actual stream is setup and 7978 * seemingly sends data to the HDA node 0x09, which is the digital 7979 * audio input node. This is left out here, because obviously I don't 7980 * know what data is being sent. Interestingly, the AE-5 seems to go 7981 * through the motions of getting here and never actually takes this 7982 * step, but the AE-7 does. 7983 */ 7984 7985 ca0113_mmio_gpio_set(codec, 0, 1); 7986 ca0113_mmio_gpio_set(codec, 1, 1); 7987 7988 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 7989 chipio_write_no_mutex(codec, 0x18b03c, 0x00000000); 7990 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 7991 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 7992 7993 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00); 7994 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0); 7995 7996 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 7997 chipio_set_stream_channels(codec, 0x18, 6); 7998 7999 /* 8000 * Runs again, this has been repeated a few times, but I'm just 8001 * following what the Windows driver does. 8002 */ 8003 ae7_post_dsp_pll_setup(codec); 8004 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 8005 8006 mutex_unlock(&spec->chipio_mutex); 8007 } 8008 8009 /* 8010 * The Windows driver has commands that seem to setup ASI, which I believe to 8011 * be some sort of audio serial interface. My current speculation is that it's 8012 * related to communicating with the new DAC. 8013 */ 8014 static void ae7_post_dsp_asi_setup(struct hda_codec *codec) 8015 { 8016 chipio_8051_write_direct(codec, 0x93, 0x10); 8017 8018 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8019 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44); 8020 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8021 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2); 8022 8023 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8024 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8025 8026 chipio_set_control_param(codec, 3, 3); 8027 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); 8028 8029 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); 8030 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 8031 snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00); 8032 8033 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8034 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92); 8035 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8036 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa); 8037 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8038 VENDOR_CHIPIO_8051_DATA_WRITE, 0x22); 8039 8040 ae7_post_dsp_pll_setup(codec); 8041 ae7_post_dsp_asi_stream_setup(codec); 8042 8043 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8044 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43); 8045 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8046 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7); 8047 8048 ae7_post_dsp_asi_setup_ports(codec); 8049 } 8050 8051 /* 8052 * Setup default parameters for DSP 8053 */ 8054 static void ca0132_setup_defaults(struct hda_codec *codec) 8055 { 8056 struct ca0132_spec *spec = codec->spec; 8057 unsigned int tmp; 8058 int num_fx; 8059 int idx, i; 8060 8061 if (spec->dsp_state != DSP_DOWNLOADED) 8062 return; 8063 8064 /* out, in effects + voicefx */ 8065 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8066 for (idx = 0; idx < num_fx; idx++) { 8067 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8068 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 8069 ca0132_effects[idx].reqs[i], 8070 ca0132_effects[idx].def_vals[i]); 8071 } 8072 } 8073 8074 /*remove DSP headroom*/ 8075 tmp = FLOAT_ZERO; 8076 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8077 8078 /*set speaker EQ bypass attenuation*/ 8079 dspio_set_uint_param(codec, 0x8f, 0x01, tmp); 8080 8081 /* set AMic1 and AMic2 as mono mic */ 8082 tmp = FLOAT_ONE; 8083 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 8084 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 8085 8086 /* set AMic1 as CrystalVoice input */ 8087 tmp = FLOAT_ONE; 8088 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 8089 8090 /* set WUH source */ 8091 tmp = FLOAT_TWO; 8092 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8093 } 8094 8095 /* 8096 * Setup default parameters for Recon3D/Recon3Di DSP. 8097 */ 8098 8099 static void r3d_setup_defaults(struct hda_codec *codec) 8100 { 8101 struct ca0132_spec *spec = codec->spec; 8102 unsigned int tmp; 8103 int num_fx; 8104 int idx, i; 8105 8106 if (spec->dsp_state != DSP_DOWNLOADED) 8107 return; 8108 8109 ca0132_alt_dsp_scp_startup(codec); 8110 ca0132_alt_init_analog_mics(codec); 8111 8112 /*remove DSP headroom*/ 8113 tmp = FLOAT_ZERO; 8114 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8115 8116 /* set WUH source */ 8117 tmp = FLOAT_TWO; 8118 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8119 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8120 8121 /* Set speaker source? */ 8122 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8123 8124 if (ca0132_quirk(spec) == QUIRK_R3DI) 8125 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED); 8126 8127 /* Disable mute on Center/LFE. */ 8128 if (ca0132_quirk(spec) == QUIRK_R3D) { 8129 ca0113_mmio_gpio_set(codec, 2, false); 8130 ca0113_mmio_gpio_set(codec, 4, true); 8131 } 8132 8133 /* Setup effect defaults */ 8134 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8135 for (idx = 0; idx < num_fx; idx++) { 8136 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8137 dspio_set_uint_param(codec, 8138 ca0132_effects[idx].mid, 8139 ca0132_effects[idx].reqs[i], 8140 ca0132_effects[idx].def_vals[i]); 8141 } 8142 } 8143 } 8144 8145 /* 8146 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on 8147 * than the Chromebook setup. 8148 */ 8149 static void sbz_setup_defaults(struct hda_codec *codec) 8150 { 8151 struct ca0132_spec *spec = codec->spec; 8152 unsigned int tmp; 8153 int num_fx; 8154 int idx, i; 8155 8156 if (spec->dsp_state != DSP_DOWNLOADED) 8157 return; 8158 8159 ca0132_alt_dsp_scp_startup(codec); 8160 ca0132_alt_init_analog_mics(codec); 8161 sbz_connect_streams(codec); 8162 sbz_chipio_startup_data(codec); 8163 8164 chipio_set_stream_control(codec, 0x03, 1); 8165 chipio_set_stream_control(codec, 0x04, 1); 8166 8167 /* 8168 * Sets internal input loopback to off, used to have a switch to 8169 * enable input loopback, but turned out to be way too buggy. 8170 */ 8171 tmp = FLOAT_ONE; 8172 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8173 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8174 8175 /*remove DSP headroom*/ 8176 tmp = FLOAT_ZERO; 8177 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8178 8179 /* set WUH source */ 8180 tmp = FLOAT_TWO; 8181 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8182 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8183 8184 /* Set speaker source? */ 8185 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8186 8187 ca0132_alt_dsp_initial_mic_setup(codec); 8188 8189 /* out, in effects + voicefx */ 8190 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8191 for (idx = 0; idx < num_fx; idx++) { 8192 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8193 dspio_set_uint_param(codec, 8194 ca0132_effects[idx].mid, 8195 ca0132_effects[idx].reqs[i], 8196 ca0132_effects[idx].def_vals[i]); 8197 } 8198 } 8199 8200 ca0132_alt_init_speaker_tuning(codec); 8201 8202 ca0132_alt_create_dummy_stream(codec); 8203 } 8204 8205 /* 8206 * Setup default parameters for the Sound BlasterX AE-5 DSP. 8207 */ 8208 static void ae5_setup_defaults(struct hda_codec *codec) 8209 { 8210 struct ca0132_spec *spec = codec->spec; 8211 unsigned int tmp; 8212 int num_fx; 8213 int idx, i; 8214 8215 if (spec->dsp_state != DSP_DOWNLOADED) 8216 return; 8217 8218 ca0132_alt_dsp_scp_startup(codec); 8219 ca0132_alt_init_analog_mics(codec); 8220 chipio_set_stream_control(codec, 0x03, 1); 8221 chipio_set_stream_control(codec, 0x04, 1); 8222 8223 /* New, unknown SCP req's */ 8224 tmp = FLOAT_ZERO; 8225 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 8226 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 8227 dspio_set_uint_param(codec, 0x80, 0x0d, tmp); 8228 dspio_set_uint_param(codec, 0x80, 0x0e, tmp); 8229 8230 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8231 ca0113_mmio_gpio_set(codec, 0, false); 8232 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 8233 8234 /* Internal loopback off */ 8235 tmp = FLOAT_ONE; 8236 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8237 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8238 8239 /*remove DSP headroom*/ 8240 tmp = FLOAT_ZERO; 8241 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8242 8243 /* set WUH source */ 8244 tmp = FLOAT_TWO; 8245 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8246 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8247 8248 /* Set speaker source? */ 8249 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8250 8251 ca0132_alt_dsp_initial_mic_setup(codec); 8252 ae5_post_dsp_register_set(codec); 8253 ae5_post_dsp_param_setup(codec); 8254 ae5_post_dsp_pll_setup(codec); 8255 ae5_post_dsp_stream_setup(codec); 8256 ae5_post_dsp_startup_data(codec); 8257 8258 /* out, in effects + voicefx */ 8259 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8260 for (idx = 0; idx < num_fx; idx++) { 8261 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8262 dspio_set_uint_param(codec, 8263 ca0132_effects[idx].mid, 8264 ca0132_effects[idx].reqs[i], 8265 ca0132_effects[idx].def_vals[i]); 8266 } 8267 } 8268 8269 ca0132_alt_init_speaker_tuning(codec); 8270 8271 ca0132_alt_create_dummy_stream(codec); 8272 } 8273 8274 /* 8275 * Setup default parameters for the Sound Blaster AE-7 DSP. 8276 */ 8277 static void ae7_setup_defaults(struct hda_codec *codec) 8278 { 8279 struct ca0132_spec *spec = codec->spec; 8280 unsigned int tmp; 8281 int num_fx; 8282 int idx, i; 8283 8284 if (spec->dsp_state != DSP_DOWNLOADED) 8285 return; 8286 8287 ca0132_alt_dsp_scp_startup(codec); 8288 ca0132_alt_init_analog_mics(codec); 8289 ae7_post_dsp_setup_ports(codec); 8290 8291 tmp = FLOAT_ZERO; 8292 dspio_set_uint_param(codec, 0x96, 8293 SPEAKER_TUNING_FRONT_LEFT_INVERT, tmp); 8294 dspio_set_uint_param(codec, 0x96, 8295 SPEAKER_TUNING_FRONT_RIGHT_INVERT, tmp); 8296 8297 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8298 8299 /* New, unknown SCP req's */ 8300 dspio_set_uint_param(codec, 0x80, 0x0d, tmp); 8301 dspio_set_uint_param(codec, 0x80, 0x0e, tmp); 8302 8303 ca0113_mmio_gpio_set(codec, 0, false); 8304 8305 /* Internal loopback off */ 8306 tmp = FLOAT_ONE; 8307 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8308 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8309 8310 /*remove DSP headroom*/ 8311 tmp = FLOAT_ZERO; 8312 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8313 8314 /* set WUH source */ 8315 tmp = FLOAT_TWO; 8316 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8317 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8318 8319 /* Set speaker source? */ 8320 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8321 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 8322 8323 /* 8324 * This is the second time we've called this, but this is seemingly 8325 * what Windows does. 8326 */ 8327 ca0132_alt_init_analog_mics(codec); 8328 8329 ae7_post_dsp_asi_setup(codec); 8330 8331 /* 8332 * Not sure why, but these are both set to 1. They're only set to 0 8333 * upon shutdown. 8334 */ 8335 ca0113_mmio_gpio_set(codec, 0, true); 8336 ca0113_mmio_gpio_set(codec, 1, true); 8337 8338 /* Volume control related. */ 8339 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x04); 8340 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x04); 8341 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x80); 8342 8343 /* out, in effects + voicefx */ 8344 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8345 for (idx = 0; idx < num_fx; idx++) { 8346 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8347 dspio_set_uint_param(codec, 8348 ca0132_effects[idx].mid, 8349 ca0132_effects[idx].reqs[i], 8350 ca0132_effects[idx].def_vals[i]); 8351 } 8352 } 8353 8354 ca0132_alt_init_speaker_tuning(codec); 8355 8356 ca0132_alt_create_dummy_stream(codec); 8357 } 8358 8359 /* 8360 * Initialization of flags in chip 8361 */ 8362 static void ca0132_init_flags(struct hda_codec *codec) 8363 { 8364 struct ca0132_spec *spec = codec->spec; 8365 8366 if (ca0132_use_alt_functions(spec)) { 8367 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1); 8368 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1); 8369 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1); 8370 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1); 8371 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1); 8372 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8373 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0); 8374 chipio_set_control_flag(codec, 8375 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 8376 chipio_set_control_flag(codec, 8377 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1); 8378 } else { 8379 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8380 chipio_set_control_flag(codec, 8381 CONTROL_FLAG_PORT_A_COMMON_MODE, 0); 8382 chipio_set_control_flag(codec, 8383 CONTROL_FLAG_PORT_D_COMMON_MODE, 0); 8384 chipio_set_control_flag(codec, 8385 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0); 8386 chipio_set_control_flag(codec, 8387 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 8388 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1); 8389 } 8390 } 8391 8392 /* 8393 * Initialization of parameters in chip 8394 */ 8395 static void ca0132_init_params(struct hda_codec *codec) 8396 { 8397 struct ca0132_spec *spec = codec->spec; 8398 8399 if (ca0132_use_alt_functions(spec)) { 8400 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8401 chipio_set_conn_rate(codec, 0x0B, SR_48_000); 8402 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0); 8403 chipio_set_control_param(codec, 0, 0); 8404 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 8405 } 8406 8407 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6); 8408 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6); 8409 } 8410 8411 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k) 8412 { 8413 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k); 8414 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k); 8415 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k); 8416 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k); 8417 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k); 8418 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k); 8419 8420 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 8421 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 8422 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8423 } 8424 8425 static bool ca0132_download_dsp_images(struct hda_codec *codec) 8426 { 8427 bool dsp_loaded = false; 8428 struct ca0132_spec *spec = codec->spec; 8429 const struct dsp_image_seg *dsp_os_image; 8430 const struct firmware *fw_entry = NULL; 8431 /* 8432 * Alternate firmwares for different variants. The Recon3Di apparently 8433 * can use the default firmware, but I'll leave the option in case 8434 * it needs it again. 8435 */ 8436 switch (ca0132_quirk(spec)) { 8437 case QUIRK_SBZ: 8438 case QUIRK_R3D: 8439 case QUIRK_AE5: 8440 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE, 8441 codec->card->dev) != 0) 8442 codec_dbg(codec, "Desktop firmware not found."); 8443 else 8444 codec_dbg(codec, "Desktop firmware selected."); 8445 break; 8446 case QUIRK_R3DI: 8447 if (request_firmware(&fw_entry, R3DI_EFX_FILE, 8448 codec->card->dev) != 0) 8449 codec_dbg(codec, "Recon3Di alt firmware not detected."); 8450 else 8451 codec_dbg(codec, "Recon3Di firmware selected."); 8452 break; 8453 default: 8454 break; 8455 } 8456 /* 8457 * Use default ctefx.bin if no alt firmware is detected, or if none 8458 * exists for your particular codec. 8459 */ 8460 if (!fw_entry) { 8461 codec_dbg(codec, "Default firmware selected."); 8462 if (request_firmware(&fw_entry, EFX_FILE, 8463 codec->card->dev) != 0) 8464 return false; 8465 } 8466 8467 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data); 8468 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) { 8469 codec_err(codec, "ca0132 DSP load image failed\n"); 8470 goto exit_download; 8471 } 8472 8473 dsp_loaded = dspload_wait_loaded(codec); 8474 8475 exit_download: 8476 release_firmware(fw_entry); 8477 8478 return dsp_loaded; 8479 } 8480 8481 static void ca0132_download_dsp(struct hda_codec *codec) 8482 { 8483 struct ca0132_spec *spec = codec->spec; 8484 8485 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP 8486 return; /* NOP */ 8487 #endif 8488 8489 if (spec->dsp_state == DSP_DOWNLOAD_FAILED) 8490 return; /* don't retry failures */ 8491 8492 chipio_enable_clocks(codec); 8493 if (spec->dsp_state != DSP_DOWNLOADED) { 8494 spec->dsp_state = DSP_DOWNLOADING; 8495 8496 if (!ca0132_download_dsp_images(codec)) 8497 spec->dsp_state = DSP_DOWNLOAD_FAILED; 8498 else 8499 spec->dsp_state = DSP_DOWNLOADED; 8500 } 8501 8502 /* For codecs using alt functions, this is already done earlier */ 8503 if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec)) 8504 ca0132_set_dsp_msr(codec, true); 8505 } 8506 8507 static void ca0132_process_dsp_response(struct hda_codec *codec, 8508 struct hda_jack_callback *callback) 8509 { 8510 struct ca0132_spec *spec = codec->spec; 8511 8512 codec_dbg(codec, "ca0132_process_dsp_response\n"); 8513 snd_hda_power_up_pm(codec); 8514 if (spec->wait_scp) { 8515 if (dspio_get_response_data(codec) >= 0) 8516 spec->wait_scp = 0; 8517 } 8518 8519 dspio_clear_response_queue(codec); 8520 snd_hda_power_down_pm(codec); 8521 } 8522 8523 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 8524 { 8525 struct ca0132_spec *spec = codec->spec; 8526 struct hda_jack_tbl *tbl; 8527 8528 /* Delay enabling the HP amp, to let the mic-detection 8529 * state machine run. 8530 */ 8531 tbl = snd_hda_jack_tbl_get(codec, cb->nid); 8532 if (tbl) 8533 tbl->block_report = 1; 8534 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500)); 8535 } 8536 8537 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 8538 { 8539 struct ca0132_spec *spec = codec->spec; 8540 8541 if (ca0132_use_alt_functions(spec)) 8542 ca0132_alt_select_in(codec); 8543 else 8544 ca0132_select_mic(codec); 8545 } 8546 8547 static void ca0132_init_unsol(struct hda_codec *codec) 8548 { 8549 struct ca0132_spec *spec = codec->spec; 8550 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback); 8551 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1, 8552 amic_callback); 8553 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP, 8554 ca0132_process_dsp_response); 8555 /* Front headphone jack detection */ 8556 if (ca0132_use_alt_functions(spec)) 8557 snd_hda_jack_detect_enable_callback(codec, 8558 spec->unsol_tag_front_hp, hp_callback); 8559 } 8560 8561 /* 8562 * Verbs tables. 8563 */ 8564 8565 /* Sends before DSP download. */ 8566 static const struct hda_verb ca0132_base_init_verbs[] = { 8567 /*enable ct extension*/ 8568 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1}, 8569 {} 8570 }; 8571 8572 /* Send at exit. */ 8573 static const struct hda_verb ca0132_base_exit_verbs[] = { 8574 /*set afg to D3*/ 8575 {0x01, AC_VERB_SET_POWER_STATE, 0x03}, 8576 /*disable ct extension*/ 8577 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0}, 8578 {} 8579 }; 8580 8581 /* Other verbs tables. Sends after DSP download. */ 8582 8583 static const struct hda_verb ca0132_init_verbs0[] = { 8584 /* chip init verbs */ 8585 {0x15, 0x70D, 0xF0}, 8586 {0x15, 0x70E, 0xFE}, 8587 {0x15, 0x707, 0x75}, 8588 {0x15, 0x707, 0xD3}, 8589 {0x15, 0x707, 0x09}, 8590 {0x15, 0x707, 0x53}, 8591 {0x15, 0x707, 0xD4}, 8592 {0x15, 0x707, 0xEF}, 8593 {0x15, 0x707, 0x75}, 8594 {0x15, 0x707, 0xD3}, 8595 {0x15, 0x707, 0x09}, 8596 {0x15, 0x707, 0x02}, 8597 {0x15, 0x707, 0x37}, 8598 {0x15, 0x707, 0x78}, 8599 {0x15, 0x53C, 0xCE}, 8600 {0x15, 0x575, 0xC9}, 8601 {0x15, 0x53D, 0xCE}, 8602 {0x15, 0x5B7, 0xC9}, 8603 {0x15, 0x70D, 0xE8}, 8604 {0x15, 0x70E, 0xFE}, 8605 {0x15, 0x707, 0x02}, 8606 {0x15, 0x707, 0x68}, 8607 {0x15, 0x707, 0x62}, 8608 {0x15, 0x53A, 0xCE}, 8609 {0x15, 0x546, 0xC9}, 8610 {0x15, 0x53B, 0xCE}, 8611 {0x15, 0x5E8, 0xC9}, 8612 {} 8613 }; 8614 8615 /* Extra init verbs for desktop cards. */ 8616 static const struct hda_verb ca0132_init_verbs1[] = { 8617 {0x15, 0x70D, 0x20}, 8618 {0x15, 0x70E, 0x19}, 8619 {0x15, 0x707, 0x00}, 8620 {0x15, 0x539, 0xCE}, 8621 {0x15, 0x546, 0xC9}, 8622 {0x15, 0x70D, 0xB7}, 8623 {0x15, 0x70E, 0x09}, 8624 {0x15, 0x707, 0x10}, 8625 {0x15, 0x70D, 0xAF}, 8626 {0x15, 0x70E, 0x09}, 8627 {0x15, 0x707, 0x01}, 8628 {0x15, 0x707, 0x05}, 8629 {0x15, 0x70D, 0x73}, 8630 {0x15, 0x70E, 0x09}, 8631 {0x15, 0x707, 0x14}, 8632 {0x15, 0x6FF, 0xC4}, 8633 {} 8634 }; 8635 8636 static void ca0132_init_chip(struct hda_codec *codec) 8637 { 8638 struct ca0132_spec *spec = codec->spec; 8639 int num_fx; 8640 int i; 8641 unsigned int on; 8642 8643 mutex_init(&spec->chipio_mutex); 8644 8645 spec->cur_out_type = SPEAKER_OUT; 8646 if (!ca0132_use_alt_functions(spec)) 8647 spec->cur_mic_type = DIGITAL_MIC; 8648 else 8649 spec->cur_mic_type = REAR_MIC; 8650 8651 spec->cur_mic_boost = 0; 8652 8653 for (i = 0; i < VNODES_COUNT; i++) { 8654 spec->vnode_lvol[i] = 0x5a; 8655 spec->vnode_rvol[i] = 0x5a; 8656 spec->vnode_lswitch[i] = 0; 8657 spec->vnode_rswitch[i] = 0; 8658 } 8659 8660 /* 8661 * Default states for effects are in ca0132_effects[]. 8662 */ 8663 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 8664 for (i = 0; i < num_fx; i++) { 8665 on = (unsigned int)ca0132_effects[i].reqs[0]; 8666 spec->effects_switch[i] = on ? 1 : 0; 8667 } 8668 /* 8669 * Sets defaults for the effect slider controls, only for alternative 8670 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz. 8671 */ 8672 if (ca0132_use_alt_controls(spec)) { 8673 /* Set speakers to default to full range. */ 8674 spec->speaker_range_val[0] = 1; 8675 spec->speaker_range_val[1] = 1; 8676 8677 spec->xbass_xover_freq = 8; 8678 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++) 8679 spec->fx_ctl_val[i] = effect_slider_defaults[i]; 8680 8681 spec->bass_redirect_xover_freq = 8; 8682 } 8683 8684 spec->voicefx_val = 0; 8685 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1; 8686 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0; 8687 8688 /* 8689 * The ZxR doesn't have a front panel header, and it's line-in is on 8690 * the daughter board. So, there is no input enum control, and we need 8691 * to make sure that spec->in_enum_val is set properly. 8692 */ 8693 if (ca0132_quirk(spec) == QUIRK_ZXR) 8694 spec->in_enum_val = REAR_MIC; 8695 8696 #ifdef ENABLE_TUNING_CONTROLS 8697 ca0132_init_tuning_defaults(codec); 8698 #endif 8699 } 8700 8701 /* 8702 * Recon3Di exit specific commands. 8703 */ 8704 /* prevents popping noise on shutdown */ 8705 static void r3di_gpio_shutdown(struct hda_codec *codec) 8706 { 8707 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00); 8708 } 8709 8710 /* 8711 * Sound Blaster Z exit specific commands. 8712 */ 8713 static void sbz_region2_exit(struct hda_codec *codec) 8714 { 8715 struct ca0132_spec *spec = codec->spec; 8716 unsigned int i; 8717 8718 for (i = 0; i < 4; i++) 8719 writeb(0x0, spec->mem_base + 0x100); 8720 for (i = 0; i < 8; i++) 8721 writeb(0xb3, spec->mem_base + 0x304); 8722 8723 ca0113_mmio_gpio_set(codec, 0, false); 8724 ca0113_mmio_gpio_set(codec, 1, false); 8725 ca0113_mmio_gpio_set(codec, 4, true); 8726 ca0113_mmio_gpio_set(codec, 5, false); 8727 ca0113_mmio_gpio_set(codec, 7, false); 8728 } 8729 8730 static void sbz_set_pin_ctl_default(struct hda_codec *codec) 8731 { 8732 static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13}; 8733 unsigned int i; 8734 8735 snd_hda_codec_write(codec, 0x11, 0, 8736 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40); 8737 8738 for (i = 0; i < ARRAY_SIZE(pins); i++) 8739 snd_hda_codec_write(codec, pins[i], 0, 8740 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00); 8741 } 8742 8743 static void ca0132_clear_unsolicited(struct hda_codec *codec) 8744 { 8745 static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13}; 8746 unsigned int i; 8747 8748 for (i = 0; i < ARRAY_SIZE(pins); i++) { 8749 snd_hda_codec_write(codec, pins[i], 0, 8750 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00); 8751 } 8752 } 8753 8754 /* On shutdown, sends commands in sets of three */ 8755 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir, 8756 int mask, int data) 8757 { 8758 if (dir >= 0) 8759 snd_hda_codec_write(codec, 0x01, 0, 8760 AC_VERB_SET_GPIO_DIRECTION, dir); 8761 if (mask >= 0) 8762 snd_hda_codec_write(codec, 0x01, 0, 8763 AC_VERB_SET_GPIO_MASK, mask); 8764 8765 if (data >= 0) 8766 snd_hda_codec_write(codec, 0x01, 0, 8767 AC_VERB_SET_GPIO_DATA, data); 8768 } 8769 8770 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec) 8771 { 8772 static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01}; 8773 unsigned int i; 8774 8775 for (i = 0; i < ARRAY_SIZE(pins); i++) 8776 snd_hda_codec_write(codec, pins[i], 0, 8777 AC_VERB_SET_POWER_STATE, 0x03); 8778 } 8779 8780 static void sbz_exit_chip(struct hda_codec *codec) 8781 { 8782 chipio_set_stream_control(codec, 0x03, 0); 8783 chipio_set_stream_control(codec, 0x04, 0); 8784 8785 /* Mess with GPIO */ 8786 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1); 8787 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05); 8788 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01); 8789 8790 chipio_set_stream_control(codec, 0x14, 0); 8791 chipio_set_stream_control(codec, 0x0C, 0); 8792 8793 chipio_set_conn_rate(codec, 0x41, SR_192_000); 8794 chipio_set_conn_rate(codec, 0x91, SR_192_000); 8795 8796 chipio_write(codec, 0x18a020, 0x00000083); 8797 8798 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03); 8799 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07); 8800 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06); 8801 8802 chipio_set_stream_control(codec, 0x0C, 0); 8803 8804 chipio_set_control_param(codec, 0x0D, 0x24); 8805 8806 ca0132_clear_unsolicited(codec); 8807 sbz_set_pin_ctl_default(codec); 8808 8809 snd_hda_codec_write(codec, 0x0B, 0, 8810 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 8811 8812 sbz_region2_exit(codec); 8813 } 8814 8815 static void r3d_exit_chip(struct hda_codec *codec) 8816 { 8817 ca0132_clear_unsolicited(codec); 8818 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 8819 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b); 8820 } 8821 8822 static void ae5_exit_chip(struct hda_codec *codec) 8823 { 8824 chipio_set_stream_control(codec, 0x03, 0); 8825 chipio_set_stream_control(codec, 0x04, 0); 8826 8827 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 8828 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8829 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8830 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 8831 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 8832 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00); 8833 ca0113_mmio_gpio_set(codec, 0, false); 8834 ca0113_mmio_gpio_set(codec, 1, false); 8835 8836 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 8837 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 8838 8839 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 8840 8841 chipio_set_stream_control(codec, 0x18, 0); 8842 chipio_set_stream_control(codec, 0x0c, 0); 8843 8844 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83); 8845 } 8846 8847 static void ae7_exit_chip(struct hda_codec *codec) 8848 { 8849 chipio_set_stream_control(codec, 0x18, 0); 8850 chipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8); 8851 chipio_set_stream_channels(codec, 0x21, 0); 8852 chipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09); 8853 chipio_set_control_param(codec, 0x20, 0x01); 8854 8855 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 8856 8857 chipio_set_stream_control(codec, 0x18, 0); 8858 chipio_set_stream_control(codec, 0x0c, 0); 8859 8860 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 8861 snd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83); 8862 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8863 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 8864 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00); 8865 ca0113_mmio_gpio_set(codec, 0, false); 8866 ca0113_mmio_gpio_set(codec, 1, false); 8867 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 8868 8869 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 8870 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 8871 } 8872 8873 static void zxr_exit_chip(struct hda_codec *codec) 8874 { 8875 chipio_set_stream_control(codec, 0x03, 0); 8876 chipio_set_stream_control(codec, 0x04, 0); 8877 chipio_set_stream_control(codec, 0x14, 0); 8878 chipio_set_stream_control(codec, 0x0C, 0); 8879 8880 chipio_set_conn_rate(codec, 0x41, SR_192_000); 8881 chipio_set_conn_rate(codec, 0x91, SR_192_000); 8882 8883 chipio_write(codec, 0x18a020, 0x00000083); 8884 8885 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 8886 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 8887 8888 ca0132_clear_unsolicited(codec); 8889 sbz_set_pin_ctl_default(codec); 8890 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00); 8891 8892 ca0113_mmio_gpio_set(codec, 5, false); 8893 ca0113_mmio_gpio_set(codec, 2, false); 8894 ca0113_mmio_gpio_set(codec, 3, false); 8895 ca0113_mmio_gpio_set(codec, 0, false); 8896 ca0113_mmio_gpio_set(codec, 4, true); 8897 ca0113_mmio_gpio_set(codec, 0, true); 8898 ca0113_mmio_gpio_set(codec, 5, true); 8899 ca0113_mmio_gpio_set(codec, 2, false); 8900 ca0113_mmio_gpio_set(codec, 3, false); 8901 } 8902 8903 static void ca0132_exit_chip(struct hda_codec *codec) 8904 { 8905 /* put any chip cleanup stuffs here. */ 8906 8907 if (dspload_is_loaded(codec)) 8908 dsp_reset(codec); 8909 } 8910 8911 /* 8912 * This fixes a problem that was hard to reproduce. Very rarely, I would 8913 * boot up, and there would be no sound, but the DSP indicated it had loaded 8914 * properly. I did a few memory dumps to see if anything was different, and 8915 * there were a few areas of memory uninitialized with a1a2a3a4. This function 8916 * checks if those areas are uninitialized, and if they are, it'll attempt to 8917 * reload the card 3 times. Usually it fixes by the second. 8918 */ 8919 static void sbz_dsp_startup_check(struct hda_codec *codec) 8920 { 8921 struct ca0132_spec *spec = codec->spec; 8922 unsigned int dsp_data_check[4]; 8923 unsigned int cur_address = 0x390; 8924 unsigned int i; 8925 unsigned int failure = 0; 8926 unsigned int reload = 3; 8927 8928 if (spec->startup_check_entered) 8929 return; 8930 8931 spec->startup_check_entered = true; 8932 8933 for (i = 0; i < 4; i++) { 8934 chipio_read(codec, cur_address, &dsp_data_check[i]); 8935 cur_address += 0x4; 8936 } 8937 for (i = 0; i < 4; i++) { 8938 if (dsp_data_check[i] == 0xa1a2a3a4) 8939 failure = 1; 8940 } 8941 8942 codec_dbg(codec, "Startup Check: %d ", failure); 8943 if (failure) 8944 codec_info(codec, "DSP not initialized properly. Attempting to fix."); 8945 /* 8946 * While the failure condition is true, and we haven't reached our 8947 * three reload limit, continue trying to reload the driver and 8948 * fix the issue. 8949 */ 8950 while (failure && (reload != 0)) { 8951 codec_info(codec, "Reloading... Tries left: %d", reload); 8952 sbz_exit_chip(codec); 8953 spec->dsp_state = DSP_DOWNLOAD_INIT; 8954 codec->patch_ops.init(codec); 8955 failure = 0; 8956 for (i = 0; i < 4; i++) { 8957 chipio_read(codec, cur_address, &dsp_data_check[i]); 8958 cur_address += 0x4; 8959 } 8960 for (i = 0; i < 4; i++) { 8961 if (dsp_data_check[i] == 0xa1a2a3a4) 8962 failure = 1; 8963 } 8964 reload--; 8965 } 8966 8967 if (!failure && reload < 3) 8968 codec_info(codec, "DSP fixed."); 8969 8970 if (!failure) 8971 return; 8972 8973 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory."); 8974 } 8975 8976 /* 8977 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add 8978 * extra precision for decibel values. If you had the dB value in floating point 8979 * you would take the value after the decimal point, multiply by 64, and divide 8980 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to 8981 * implement fixed point or floating point dB volumes. For now, I'll set them 8982 * to 0 just incase a value has lingered from a boot into Windows. 8983 */ 8984 static void ca0132_alt_vol_setup(struct hda_codec *codec) 8985 { 8986 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00); 8987 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00); 8988 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00); 8989 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00); 8990 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00); 8991 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00); 8992 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00); 8993 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00); 8994 } 8995 8996 /* 8997 * Extra commands that don't really fit anywhere else. 8998 */ 8999 static void sbz_pre_dsp_setup(struct hda_codec *codec) 9000 { 9001 struct ca0132_spec *spec = codec->spec; 9002 9003 writel(0x00820680, spec->mem_base + 0x01C); 9004 writel(0x00820680, spec->mem_base + 0x01C); 9005 9006 chipio_write(codec, 0x18b0a4, 0x000000c2); 9007 9008 snd_hda_codec_write(codec, 0x11, 0, 9009 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 9010 } 9011 9012 static void r3d_pre_dsp_setup(struct hda_codec *codec) 9013 { 9014 chipio_write(codec, 0x18b0a4, 0x000000c2); 9015 9016 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9017 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E); 9018 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9019 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C); 9020 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9021 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B); 9022 9023 snd_hda_codec_write(codec, 0x11, 0, 9024 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 9025 } 9026 9027 static void r3di_pre_dsp_setup(struct hda_codec *codec) 9028 { 9029 chipio_write(codec, 0x18b0a4, 0x000000c2); 9030 9031 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9032 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E); 9033 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9034 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C); 9035 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9036 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B); 9037 9038 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9039 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); 9040 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9041 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 9042 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9043 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 9044 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9045 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40); 9046 9047 snd_hda_codec_write(codec, 0x11, 0, 9048 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04); 9049 } 9050 9051 /* 9052 * These are sent before the DSP is downloaded. Not sure 9053 * what they do, or if they're necessary. Could possibly 9054 * be removed. Figure they're better to leave in. 9055 */ 9056 static const unsigned int ca0113_mmio_init_address_sbz[] = { 9057 0x400, 0x408, 0x40c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 9058 0xc0c, 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04 9059 }; 9060 9061 static const unsigned int ca0113_mmio_init_data_sbz[] = { 9062 0x00000030, 0x00000000, 0x00000003, 0x00000003, 0x00000003, 9063 0x00000003, 0x000000c1, 0x000000f1, 0x00000001, 0x000000c7, 9064 0x000000c1, 0x00000080 9065 }; 9066 9067 static const unsigned int ca0113_mmio_init_data_zxr[] = { 9068 0x00000030, 0x00000000, 0x00000000, 0x00000003, 0x00000003, 9069 0x00000003, 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 9070 0x000000c1, 0x00000080 9071 }; 9072 9073 static const unsigned int ca0113_mmio_init_address_ae5[] = { 9074 0x400, 0x42c, 0x46c, 0x4ac, 0x4ec, 0x43c, 0x47c, 0x4bc, 0x4fc, 0x408, 9075 0x100, 0x410, 0x40c, 0x100, 0x100, 0x830, 0x86c, 0x800, 0x86c, 0x800, 9076 0x804, 0x20c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 0xc0c, 9077 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04, 0x01c 9078 }; 9079 9080 static const unsigned int ca0113_mmio_init_data_ae5[] = { 9081 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 9082 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 9083 0x00000600, 0x00000014, 0x00000001, 0x0000060f, 0x0000070f, 9084 0x00000aff, 0x00000000, 0x0000006b, 0x00000001, 0x0000006b, 9085 0x00000057, 0x00800000, 0x00880680, 0x00000080, 0x00000030, 9086 0x00000000, 0x00000000, 0x00000003, 0x00000003, 0x00000003, 9087 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1, 9088 0x00000080, 0x00880680 9089 }; 9090 9091 static void ca0132_mmio_init_sbz(struct hda_codec *codec) 9092 { 9093 struct ca0132_spec *spec = codec->spec; 9094 unsigned int tmp[2], i, count, cur_addr; 9095 const unsigned int *addr, *data; 9096 9097 addr = ca0113_mmio_init_address_sbz; 9098 for (i = 0; i < 3; i++) 9099 writel(0x00000000, spec->mem_base + addr[i]); 9100 9101 cur_addr = i; 9102 switch (ca0132_quirk(spec)) { 9103 case QUIRK_ZXR: 9104 tmp[0] = 0x00880480; 9105 tmp[1] = 0x00000080; 9106 break; 9107 case QUIRK_SBZ: 9108 tmp[0] = 0x00820680; 9109 tmp[1] = 0x00000083; 9110 break; 9111 case QUIRK_R3D: 9112 tmp[0] = 0x00880680; 9113 tmp[1] = 0x00000083; 9114 break; 9115 default: 9116 tmp[0] = 0x00000000; 9117 tmp[1] = 0x00000000; 9118 break; 9119 } 9120 9121 for (i = 0; i < 2; i++) 9122 writel(tmp[i], spec->mem_base + addr[cur_addr + i]); 9123 9124 cur_addr += i; 9125 9126 switch (ca0132_quirk(spec)) { 9127 case QUIRK_ZXR: 9128 count = ARRAY_SIZE(ca0113_mmio_init_data_zxr); 9129 data = ca0113_mmio_init_data_zxr; 9130 break; 9131 default: 9132 count = ARRAY_SIZE(ca0113_mmio_init_data_sbz); 9133 data = ca0113_mmio_init_data_sbz; 9134 break; 9135 } 9136 9137 for (i = 0; i < count; i++) 9138 writel(data[i], spec->mem_base + addr[cur_addr + i]); 9139 } 9140 9141 static void ca0132_mmio_init_ae5(struct hda_codec *codec) 9142 { 9143 struct ca0132_spec *spec = codec->spec; 9144 const unsigned int *addr, *data; 9145 unsigned int i, count; 9146 9147 addr = ca0113_mmio_init_address_ae5; 9148 data = ca0113_mmio_init_data_ae5; 9149 count = ARRAY_SIZE(ca0113_mmio_init_data_ae5); 9150 9151 if (ca0132_quirk(spec) == QUIRK_AE7) { 9152 writel(0x00000680, spec->mem_base + 0x1c); 9153 writel(0x00880680, spec->mem_base + 0x1c); 9154 } 9155 9156 for (i = 0; i < count; i++) { 9157 /* 9158 * AE-7 shares all writes with the AE-5, except that it writes 9159 * a different value to 0x20c. 9160 */ 9161 if (i == 21 && ca0132_quirk(spec) == QUIRK_AE7) { 9162 writel(0x00800001, spec->mem_base + addr[i]); 9163 continue; 9164 } 9165 9166 writel(data[i], spec->mem_base + addr[i]); 9167 } 9168 9169 if (ca0132_quirk(spec) == QUIRK_AE5) 9170 writel(0x00880680, spec->mem_base + 0x1c); 9171 } 9172 9173 static void ca0132_mmio_init(struct hda_codec *codec) 9174 { 9175 struct ca0132_spec *spec = codec->spec; 9176 9177 switch (ca0132_quirk(spec)) { 9178 case QUIRK_R3D: 9179 case QUIRK_SBZ: 9180 case QUIRK_ZXR: 9181 ca0132_mmio_init_sbz(codec); 9182 break; 9183 case QUIRK_AE5: 9184 ca0132_mmio_init_ae5(codec); 9185 break; 9186 } 9187 } 9188 9189 static const unsigned int ca0132_ae5_register_set_addresses[] = { 9190 0x304, 0x304, 0x304, 0x304, 0x100, 0x304, 0x100, 0x304, 0x100, 0x304, 9191 0x100, 0x304, 0x86c, 0x800, 0x86c, 0x800, 0x804 9192 }; 9193 9194 static const unsigned char ca0132_ae5_register_set_data[] = { 9195 0x0f, 0x0e, 0x1f, 0x0c, 0x3f, 0x08, 0x7f, 0x00, 0xff, 0x00, 0x6b, 9196 0x01, 0x6b, 0x57 9197 }; 9198 9199 /* 9200 * This function writes to some SFR's, does some region2 writes, and then 9201 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does 9202 * what it does. 9203 */ 9204 static void ae5_register_set(struct hda_codec *codec) 9205 { 9206 struct ca0132_spec *spec = codec->spec; 9207 unsigned int count = ARRAY_SIZE(ca0132_ae5_register_set_addresses); 9208 const unsigned int *addr = ca0132_ae5_register_set_addresses; 9209 const unsigned char *data = ca0132_ae5_register_set_data; 9210 unsigned int i, cur_addr; 9211 unsigned char tmp[3]; 9212 9213 if (ca0132_quirk(spec) == QUIRK_AE7) { 9214 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9215 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41); 9216 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9217 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8); 9218 } 9219 9220 chipio_8051_write_direct(codec, 0x93, 0x10); 9221 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9222 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44); 9223 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9224 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2); 9225 9226 if (ca0132_quirk(spec) == QUIRK_AE7) { 9227 tmp[0] = 0x03; 9228 tmp[1] = 0x03; 9229 tmp[2] = 0x07; 9230 } else { 9231 tmp[0] = 0x0f; 9232 tmp[1] = 0x0f; 9233 tmp[2] = 0x0f; 9234 } 9235 9236 for (i = cur_addr = 0; i < 3; i++, cur_addr++) 9237 writeb(tmp[i], spec->mem_base + addr[cur_addr]); 9238 9239 /* 9240 * First writes are in single bytes, final are in 4 bytes. So, we use 9241 * writeb, then writel. 9242 */ 9243 for (i = 0; cur_addr < 12; i++, cur_addr++) 9244 writeb(data[i], spec->mem_base + addr[cur_addr]); 9245 9246 for (; cur_addr < count; i++, cur_addr++) 9247 writel(data[i], spec->mem_base + addr[cur_addr]); 9248 9249 writel(0x00800001, spec->mem_base + 0x20c); 9250 9251 if (ca0132_quirk(spec) == QUIRK_AE7) { 9252 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 9253 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 9254 } else { 9255 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 9256 } 9257 9258 chipio_8051_write_direct(codec, 0x90, 0x00); 9259 chipio_8051_write_direct(codec, 0x90, 0x10); 9260 9261 if (ca0132_quirk(spec) == QUIRK_AE5) 9262 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 9263 9264 chipio_write(codec, 0x18b0a4, 0x000000c2); 9265 9266 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00); 9267 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00); 9268 } 9269 9270 /* 9271 * Extra init functions for alternative ca0132 codecs. Done 9272 * here so they don't clutter up the main ca0132_init function 9273 * anymore than they have to. 9274 */ 9275 static void ca0132_alt_init(struct hda_codec *codec) 9276 { 9277 struct ca0132_spec *spec = codec->spec; 9278 9279 ca0132_alt_vol_setup(codec); 9280 9281 switch (ca0132_quirk(spec)) { 9282 case QUIRK_SBZ: 9283 codec_dbg(codec, "SBZ alt_init"); 9284 ca0132_gpio_init(codec); 9285 sbz_pre_dsp_setup(codec); 9286 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9287 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9288 break; 9289 case QUIRK_R3DI: 9290 codec_dbg(codec, "R3DI alt_init"); 9291 ca0132_gpio_init(codec); 9292 ca0132_gpio_setup(codec); 9293 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING); 9294 r3di_pre_dsp_setup(codec); 9295 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9296 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4); 9297 break; 9298 case QUIRK_R3D: 9299 r3d_pre_dsp_setup(codec); 9300 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9301 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9302 break; 9303 case QUIRK_AE5: 9304 ca0132_gpio_init(codec); 9305 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9306 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49); 9307 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9308 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88); 9309 chipio_write(codec, 0x18b030, 0x00000020); 9310 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9311 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9312 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9313 break; 9314 case QUIRK_AE7: 9315 ca0132_gpio_init(codec); 9316 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9317 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49); 9318 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9319 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88); 9320 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9321 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9322 chipio_write(codec, 0x18b008, 0x000000f8); 9323 chipio_write(codec, 0x18b008, 0x000000f0); 9324 chipio_write(codec, 0x18b030, 0x00000020); 9325 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9326 break; 9327 case QUIRK_ZXR: 9328 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9329 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9330 break; 9331 default: 9332 break; 9333 } 9334 } 9335 9336 static int ca0132_init(struct hda_codec *codec) 9337 { 9338 struct ca0132_spec *spec = codec->spec; 9339 struct auto_pin_cfg *cfg = &spec->autocfg; 9340 int i; 9341 bool dsp_loaded; 9342 9343 /* 9344 * If the DSP is already downloaded, and init has been entered again, 9345 * there's only two reasons for it. One, the codec has awaken from a 9346 * suspended state, and in that case dspload_is_loaded will return 9347 * false, and the init will be ran again. The other reason it gets 9348 * re entered is on startup for some reason it triggers a suspend and 9349 * resume state. In this case, it will check if the DSP is downloaded, 9350 * and not run the init function again. For codecs using alt_functions, 9351 * it will check if the DSP is loaded properly. 9352 */ 9353 if (spec->dsp_state == DSP_DOWNLOADED) { 9354 dsp_loaded = dspload_is_loaded(codec); 9355 if (!dsp_loaded) { 9356 spec->dsp_reload = true; 9357 spec->dsp_state = DSP_DOWNLOAD_INIT; 9358 } else { 9359 if (ca0132_quirk(spec) == QUIRK_SBZ) 9360 sbz_dsp_startup_check(codec); 9361 return 0; 9362 } 9363 } 9364 9365 if (spec->dsp_state != DSP_DOWNLOAD_FAILED) 9366 spec->dsp_state = DSP_DOWNLOAD_INIT; 9367 spec->curr_chip_addx = INVALID_CHIP_ADDRESS; 9368 9369 if (ca0132_use_pci_mmio(spec)) 9370 ca0132_mmio_init(codec); 9371 9372 snd_hda_power_up_pm(codec); 9373 9374 if (ca0132_quirk(spec) == QUIRK_AE5 || ca0132_quirk(spec) == QUIRK_AE7) 9375 ae5_register_set(codec); 9376 9377 ca0132_init_unsol(codec); 9378 ca0132_init_params(codec); 9379 ca0132_init_flags(codec); 9380 9381 snd_hda_sequence_write(codec, spec->base_init_verbs); 9382 9383 if (ca0132_use_alt_functions(spec)) 9384 ca0132_alt_init(codec); 9385 9386 ca0132_download_dsp(codec); 9387 9388 ca0132_refresh_widget_caps(codec); 9389 9390 switch (ca0132_quirk(spec)) { 9391 case QUIRK_R3DI: 9392 case QUIRK_R3D: 9393 r3d_setup_defaults(codec); 9394 break; 9395 case QUIRK_SBZ: 9396 case QUIRK_ZXR: 9397 sbz_setup_defaults(codec); 9398 break; 9399 case QUIRK_AE5: 9400 ae5_setup_defaults(codec); 9401 break; 9402 case QUIRK_AE7: 9403 ae7_setup_defaults(codec); 9404 break; 9405 default: 9406 ca0132_setup_defaults(codec); 9407 ca0132_init_analog_mic2(codec); 9408 ca0132_init_dmic(codec); 9409 break; 9410 } 9411 9412 for (i = 0; i < spec->num_outputs; i++) 9413 init_output(codec, spec->out_pins[i], spec->dacs[0]); 9414 9415 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 9416 9417 for (i = 0; i < spec->num_inputs; i++) 9418 init_input(codec, spec->input_pins[i], spec->adcs[i]); 9419 9420 init_input(codec, cfg->dig_in_pin, spec->dig_in); 9421 9422 if (!ca0132_use_alt_functions(spec)) { 9423 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9424 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9425 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D); 9426 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9427 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20); 9428 } 9429 9430 if (ca0132_quirk(spec) == QUIRK_SBZ) 9431 ca0132_gpio_setup(codec); 9432 9433 snd_hda_sequence_write(codec, spec->spec_init_verbs); 9434 if (ca0132_use_alt_functions(spec)) { 9435 ca0132_alt_select_out(codec); 9436 ca0132_alt_select_in(codec); 9437 } else { 9438 ca0132_select_out(codec); 9439 ca0132_select_mic(codec); 9440 } 9441 9442 snd_hda_jack_report_sync(codec); 9443 9444 /* 9445 * Re set the PlayEnhancement switch on a resume event, because the 9446 * controls will not be reloaded. 9447 */ 9448 if (spec->dsp_reload) { 9449 spec->dsp_reload = false; 9450 ca0132_pe_switch_set(codec); 9451 } 9452 9453 snd_hda_power_down_pm(codec); 9454 9455 return 0; 9456 } 9457 9458 static int dbpro_init(struct hda_codec *codec) 9459 { 9460 struct ca0132_spec *spec = codec->spec; 9461 struct auto_pin_cfg *cfg = &spec->autocfg; 9462 unsigned int i; 9463 9464 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 9465 init_input(codec, cfg->dig_in_pin, spec->dig_in); 9466 9467 for (i = 0; i < spec->num_inputs; i++) 9468 init_input(codec, spec->input_pins[i], spec->adcs[i]); 9469 9470 return 0; 9471 } 9472 9473 static void ca0132_free(struct hda_codec *codec) 9474 { 9475 struct ca0132_spec *spec = codec->spec; 9476 9477 cancel_delayed_work_sync(&spec->unsol_hp_work); 9478 snd_hda_power_up(codec); 9479 switch (ca0132_quirk(spec)) { 9480 case QUIRK_SBZ: 9481 sbz_exit_chip(codec); 9482 break; 9483 case QUIRK_ZXR: 9484 zxr_exit_chip(codec); 9485 break; 9486 case QUIRK_R3D: 9487 r3d_exit_chip(codec); 9488 break; 9489 case QUIRK_AE5: 9490 ae5_exit_chip(codec); 9491 break; 9492 case QUIRK_AE7: 9493 ae7_exit_chip(codec); 9494 break; 9495 case QUIRK_R3DI: 9496 r3di_gpio_shutdown(codec); 9497 break; 9498 default: 9499 break; 9500 } 9501 9502 snd_hda_sequence_write(codec, spec->base_exit_verbs); 9503 ca0132_exit_chip(codec); 9504 9505 snd_hda_power_down(codec); 9506 #ifdef CONFIG_PCI 9507 if (spec->mem_base) 9508 pci_iounmap(codec->bus->pci, spec->mem_base); 9509 #endif 9510 kfree(spec->spec_init_verbs); 9511 kfree(codec->spec); 9512 } 9513 9514 static void dbpro_free(struct hda_codec *codec) 9515 { 9516 struct ca0132_spec *spec = codec->spec; 9517 9518 zxr_dbpro_power_state_shutdown(codec); 9519 9520 kfree(spec->spec_init_verbs); 9521 kfree(codec->spec); 9522 } 9523 9524 static void ca0132_reboot_notify(struct hda_codec *codec) 9525 { 9526 codec->patch_ops.free(codec); 9527 } 9528 9529 #ifdef CONFIG_PM 9530 static int ca0132_suspend(struct hda_codec *codec) 9531 { 9532 struct ca0132_spec *spec = codec->spec; 9533 9534 cancel_delayed_work_sync(&spec->unsol_hp_work); 9535 return 0; 9536 } 9537 #endif 9538 9539 static const struct hda_codec_ops ca0132_patch_ops = { 9540 .build_controls = ca0132_build_controls, 9541 .build_pcms = ca0132_build_pcms, 9542 .init = ca0132_init, 9543 .free = ca0132_free, 9544 .unsol_event = snd_hda_jack_unsol_event, 9545 #ifdef CONFIG_PM 9546 .suspend = ca0132_suspend, 9547 #endif 9548 .reboot_notify = ca0132_reboot_notify, 9549 }; 9550 9551 static const struct hda_codec_ops dbpro_patch_ops = { 9552 .build_controls = dbpro_build_controls, 9553 .build_pcms = dbpro_build_pcms, 9554 .init = dbpro_init, 9555 .free = dbpro_free, 9556 }; 9557 9558 static void ca0132_config(struct hda_codec *codec) 9559 { 9560 struct ca0132_spec *spec = codec->spec; 9561 9562 spec->dacs[0] = 0x2; 9563 spec->dacs[1] = 0x3; 9564 spec->dacs[2] = 0x4; 9565 9566 spec->multiout.dac_nids = spec->dacs; 9567 spec->multiout.num_dacs = 3; 9568 9569 if (!ca0132_use_alt_functions(spec)) 9570 spec->multiout.max_channels = 2; 9571 else 9572 spec->multiout.max_channels = 6; 9573 9574 switch (ca0132_quirk(spec)) { 9575 case QUIRK_ALIENWARE: 9576 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__); 9577 snd_hda_apply_pincfgs(codec, alienware_pincfgs); 9578 break; 9579 case QUIRK_SBZ: 9580 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__); 9581 snd_hda_apply_pincfgs(codec, sbz_pincfgs); 9582 break; 9583 case QUIRK_ZXR: 9584 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__); 9585 snd_hda_apply_pincfgs(codec, zxr_pincfgs); 9586 break; 9587 case QUIRK_R3D: 9588 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__); 9589 snd_hda_apply_pincfgs(codec, r3d_pincfgs); 9590 break; 9591 case QUIRK_R3DI: 9592 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__); 9593 snd_hda_apply_pincfgs(codec, r3di_pincfgs); 9594 break; 9595 case QUIRK_AE5: 9596 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__); 9597 snd_hda_apply_pincfgs(codec, ae5_pincfgs); 9598 break; 9599 case QUIRK_AE7: 9600 codec_dbg(codec, "%s: QUIRK_AE7 applied.\n", __func__); 9601 snd_hda_apply_pincfgs(codec, ae7_pincfgs); 9602 break; 9603 default: 9604 break; 9605 } 9606 9607 switch (ca0132_quirk(spec)) { 9608 case QUIRK_ALIENWARE: 9609 spec->num_outputs = 2; 9610 spec->out_pins[0] = 0x0b; /* speaker out */ 9611 spec->out_pins[1] = 0x0f; 9612 spec->shared_out_nid = 0x2; 9613 spec->unsol_tag_hp = 0x0f; 9614 9615 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 9616 spec->adcs[1] = 0x8; /* analog mic2 */ 9617 spec->adcs[2] = 0xa; /* what u hear */ 9618 9619 spec->num_inputs = 3; 9620 spec->input_pins[0] = 0x12; 9621 spec->input_pins[1] = 0x11; 9622 spec->input_pins[2] = 0x13; 9623 spec->shared_mic_nid = 0x7; 9624 spec->unsol_tag_amic1 = 0x11; 9625 break; 9626 case QUIRK_SBZ: 9627 case QUIRK_R3D: 9628 spec->num_outputs = 2; 9629 spec->out_pins[0] = 0x0B; /* Line out */ 9630 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9631 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9632 spec->out_pins[3] = 0x11; /* Rear surround */ 9633 spec->shared_out_nid = 0x2; 9634 spec->unsol_tag_hp = spec->out_pins[1]; 9635 spec->unsol_tag_front_hp = spec->out_pins[2]; 9636 9637 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9638 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 9639 spec->adcs[2] = 0xa; /* what u hear */ 9640 9641 spec->num_inputs = 2; 9642 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9643 spec->input_pins[1] = 0x13; /* What U Hear */ 9644 spec->shared_mic_nid = 0x7; 9645 spec->unsol_tag_amic1 = spec->input_pins[0]; 9646 9647 /* SPDIF I/O */ 9648 spec->dig_out = 0x05; 9649 spec->multiout.dig_out_nid = spec->dig_out; 9650 spec->dig_in = 0x09; 9651 break; 9652 case QUIRK_ZXR: 9653 spec->num_outputs = 2; 9654 spec->out_pins[0] = 0x0B; /* Line out */ 9655 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9656 spec->out_pins[2] = 0x10; /* Center/LFE */ 9657 spec->out_pins[3] = 0x11; /* Rear surround */ 9658 spec->shared_out_nid = 0x2; 9659 spec->unsol_tag_hp = spec->out_pins[1]; 9660 spec->unsol_tag_front_hp = spec->out_pins[2]; 9661 9662 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9663 spec->adcs[1] = 0x8; /* Not connected, no front mic */ 9664 spec->adcs[2] = 0xa; /* what u hear */ 9665 9666 spec->num_inputs = 2; 9667 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9668 spec->input_pins[1] = 0x13; /* What U Hear */ 9669 spec->shared_mic_nid = 0x7; 9670 spec->unsol_tag_amic1 = spec->input_pins[0]; 9671 break; 9672 case QUIRK_ZXR_DBPRO: 9673 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */ 9674 9675 spec->num_inputs = 1; 9676 spec->input_pins[0] = 0x11; /* RCA Line-in */ 9677 9678 spec->dig_out = 0x05; 9679 spec->multiout.dig_out_nid = spec->dig_out; 9680 9681 spec->dig_in = 0x09; 9682 break; 9683 case QUIRK_AE5: 9684 case QUIRK_AE7: 9685 spec->num_outputs = 2; 9686 spec->out_pins[0] = 0x0B; /* Line out */ 9687 spec->out_pins[1] = 0x11; /* Rear headphone out */ 9688 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9689 spec->out_pins[3] = 0x0F; /* Rear surround */ 9690 spec->shared_out_nid = 0x2; 9691 spec->unsol_tag_hp = spec->out_pins[1]; 9692 spec->unsol_tag_front_hp = spec->out_pins[2]; 9693 9694 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9695 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 9696 spec->adcs[2] = 0xa; /* what u hear */ 9697 9698 spec->num_inputs = 2; 9699 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9700 spec->input_pins[1] = 0x13; /* What U Hear */ 9701 spec->shared_mic_nid = 0x7; 9702 spec->unsol_tag_amic1 = spec->input_pins[0]; 9703 9704 /* SPDIF I/O */ 9705 spec->dig_out = 0x05; 9706 spec->multiout.dig_out_nid = spec->dig_out; 9707 break; 9708 case QUIRK_R3DI: 9709 spec->num_outputs = 2; 9710 spec->out_pins[0] = 0x0B; /* Line out */ 9711 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9712 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9713 spec->out_pins[3] = 0x11; /* Rear surround */ 9714 spec->shared_out_nid = 0x2; 9715 spec->unsol_tag_hp = spec->out_pins[1]; 9716 spec->unsol_tag_front_hp = spec->out_pins[2]; 9717 9718 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */ 9719 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */ 9720 spec->adcs[2] = 0x0a; /* what u hear */ 9721 9722 spec->num_inputs = 2; 9723 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9724 spec->input_pins[1] = 0x13; /* What U Hear */ 9725 spec->shared_mic_nid = 0x7; 9726 spec->unsol_tag_amic1 = spec->input_pins[0]; 9727 9728 /* SPDIF I/O */ 9729 spec->dig_out = 0x05; 9730 spec->multiout.dig_out_nid = spec->dig_out; 9731 break; 9732 default: 9733 spec->num_outputs = 2; 9734 spec->out_pins[0] = 0x0b; /* speaker out */ 9735 spec->out_pins[1] = 0x10; /* headphone out */ 9736 spec->shared_out_nid = 0x2; 9737 spec->unsol_tag_hp = spec->out_pins[1]; 9738 9739 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 9740 spec->adcs[1] = 0x8; /* analog mic2 */ 9741 spec->adcs[2] = 0xa; /* what u hear */ 9742 9743 spec->num_inputs = 3; 9744 spec->input_pins[0] = 0x12; 9745 spec->input_pins[1] = 0x11; 9746 spec->input_pins[2] = 0x13; 9747 spec->shared_mic_nid = 0x7; 9748 spec->unsol_tag_amic1 = spec->input_pins[0]; 9749 9750 /* SPDIF I/O */ 9751 spec->dig_out = 0x05; 9752 spec->multiout.dig_out_nid = spec->dig_out; 9753 spec->dig_in = 0x09; 9754 break; 9755 } 9756 } 9757 9758 static int ca0132_prepare_verbs(struct hda_codec *codec) 9759 { 9760 /* Verbs + terminator (an empty element) */ 9761 #define NUM_SPEC_VERBS 2 9762 struct ca0132_spec *spec = codec->spec; 9763 9764 spec->chip_init_verbs = ca0132_init_verbs0; 9765 /* 9766 * Since desktop cards use pci_mmio, this can be used to determine 9767 * whether or not to use these verbs instead of a separate bool. 9768 */ 9769 if (ca0132_use_pci_mmio(spec)) 9770 spec->desktop_init_verbs = ca0132_init_verbs1; 9771 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS, 9772 sizeof(struct hda_verb), 9773 GFP_KERNEL); 9774 if (!spec->spec_init_verbs) 9775 return -ENOMEM; 9776 9777 /* config EAPD */ 9778 spec->spec_init_verbs[0].nid = 0x0b; 9779 spec->spec_init_verbs[0].param = 0x78D; 9780 spec->spec_init_verbs[0].verb = 0x00; 9781 9782 /* Previously commented configuration */ 9783 /* 9784 spec->spec_init_verbs[2].nid = 0x0b; 9785 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE; 9786 spec->spec_init_verbs[2].verb = 0x02; 9787 9788 spec->spec_init_verbs[3].nid = 0x10; 9789 spec->spec_init_verbs[3].param = 0x78D; 9790 spec->spec_init_verbs[3].verb = 0x02; 9791 9792 spec->spec_init_verbs[4].nid = 0x10; 9793 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE; 9794 spec->spec_init_verbs[4].verb = 0x02; 9795 */ 9796 9797 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */ 9798 return 0; 9799 } 9800 9801 /* 9802 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular 9803 * Sound Blaster Z cards. However, they have different HDA codec subsystem 9804 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro 9805 * daughter boards ID. 9806 */ 9807 static void sbz_detect_quirk(struct hda_codec *codec) 9808 { 9809 struct ca0132_spec *spec = codec->spec; 9810 9811 switch (codec->core.subsystem_id) { 9812 case 0x11020033: 9813 spec->quirk = QUIRK_ZXR; 9814 break; 9815 case 0x1102003f: 9816 spec->quirk = QUIRK_ZXR_DBPRO; 9817 break; 9818 default: 9819 spec->quirk = QUIRK_SBZ; 9820 break; 9821 } 9822 } 9823 9824 static int patch_ca0132(struct hda_codec *codec) 9825 { 9826 struct ca0132_spec *spec; 9827 int err; 9828 const struct snd_pci_quirk *quirk; 9829 9830 codec_dbg(codec, "patch_ca0132\n"); 9831 9832 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 9833 if (!spec) 9834 return -ENOMEM; 9835 codec->spec = spec; 9836 spec->codec = codec; 9837 9838 /* Detect codec quirk */ 9839 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks); 9840 if (quirk) 9841 spec->quirk = quirk->value; 9842 else 9843 spec->quirk = QUIRK_NONE; 9844 if (ca0132_quirk(spec) == QUIRK_SBZ) 9845 sbz_detect_quirk(codec); 9846 9847 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO) 9848 codec->patch_ops = dbpro_patch_ops; 9849 else 9850 codec->patch_ops = ca0132_patch_ops; 9851 9852 codec->pcm_format_first = 1; 9853 codec->no_sticky_stream = 1; 9854 9855 9856 spec->dsp_state = DSP_DOWNLOAD_INIT; 9857 spec->num_mixers = 1; 9858 9859 /* Set which mixers each quirk uses. */ 9860 switch (ca0132_quirk(spec)) { 9861 case QUIRK_SBZ: 9862 spec->mixers[0] = desktop_mixer; 9863 snd_hda_codec_set_name(codec, "Sound Blaster Z"); 9864 break; 9865 case QUIRK_ZXR: 9866 spec->mixers[0] = desktop_mixer; 9867 snd_hda_codec_set_name(codec, "Sound Blaster ZxR"); 9868 break; 9869 case QUIRK_ZXR_DBPRO: 9870 break; 9871 case QUIRK_R3D: 9872 spec->mixers[0] = desktop_mixer; 9873 snd_hda_codec_set_name(codec, "Recon3D"); 9874 break; 9875 case QUIRK_R3DI: 9876 spec->mixers[0] = r3di_mixer; 9877 snd_hda_codec_set_name(codec, "Recon3Di"); 9878 break; 9879 case QUIRK_AE5: 9880 spec->mixers[0] = desktop_mixer; 9881 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5"); 9882 break; 9883 case QUIRK_AE7: 9884 spec->mixers[0] = desktop_mixer; 9885 snd_hda_codec_set_name(codec, "Sound Blaster AE-7"); 9886 break; 9887 default: 9888 spec->mixers[0] = ca0132_mixer; 9889 break; 9890 } 9891 9892 /* Setup whether or not to use alt functions/controls/pci_mmio */ 9893 switch (ca0132_quirk(spec)) { 9894 case QUIRK_SBZ: 9895 case QUIRK_R3D: 9896 case QUIRK_AE5: 9897 case QUIRK_AE7: 9898 case QUIRK_ZXR: 9899 spec->use_alt_controls = true; 9900 spec->use_alt_functions = true; 9901 spec->use_pci_mmio = true; 9902 break; 9903 case QUIRK_R3DI: 9904 spec->use_alt_controls = true; 9905 spec->use_alt_functions = true; 9906 spec->use_pci_mmio = false; 9907 break; 9908 default: 9909 spec->use_alt_controls = false; 9910 spec->use_alt_functions = false; 9911 spec->use_pci_mmio = false; 9912 break; 9913 } 9914 9915 #ifdef CONFIG_PCI 9916 if (spec->use_pci_mmio) { 9917 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20); 9918 if (spec->mem_base == NULL) { 9919 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE."); 9920 spec->quirk = QUIRK_NONE; 9921 } 9922 } 9923 #endif 9924 9925 spec->base_init_verbs = ca0132_base_init_verbs; 9926 spec->base_exit_verbs = ca0132_base_exit_verbs; 9927 9928 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed); 9929 9930 ca0132_init_chip(codec); 9931 9932 ca0132_config(codec); 9933 9934 err = ca0132_prepare_verbs(codec); 9935 if (err < 0) 9936 goto error; 9937 9938 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL); 9939 if (err < 0) 9940 goto error; 9941 9942 return 0; 9943 9944 error: 9945 ca0132_free(codec); 9946 return err; 9947 } 9948 9949 /* 9950 * patch entries 9951 */ 9952 static const struct hda_device_id snd_hda_id_ca0132[] = { 9953 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132), 9954 {} /* terminator */ 9955 }; 9956 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132); 9957 9958 MODULE_LICENSE("GPL"); 9959 MODULE_DESCRIPTION("Creative Sound Core3D codec"); 9960 9961 static struct hda_codec_driver ca0132_driver = { 9962 .id = snd_hda_id_ca0132, 9963 }; 9964 9965 module_hda_codec_driver(ca0132_driver); 9966