1 /* 2 * HD audio interface patch for Creative CA0132 chip 3 * 4 * Copyright (c) 2011, Creative Technology Ltd. 5 * 6 * Based on patch_ca0110.c 7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de> 8 * 9 * This driver is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This driver is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 */ 23 24 #include <linux/init.h> 25 #include <linux/delay.h> 26 #include <linux/slab.h> 27 #include <linux/mutex.h> 28 #include <linux/module.h> 29 #include <linux/firmware.h> 30 #include <linux/kernel.h> 31 #include <linux/types.h> 32 #include <linux/io.h> 33 #include <linux/pci.h> 34 #include <sound/core.h> 35 #include "hda_codec.h" 36 #include "hda_local.h" 37 #include "hda_auto_parser.h" 38 #include "hda_jack.h" 39 40 #include "ca0132_regs.h" 41 42 /* Enable this to see controls for tuning purpose. */ 43 /*#define ENABLE_TUNING_CONTROLS*/ 44 45 #ifdef ENABLE_TUNING_CONTROLS 46 #include <sound/tlv.h> 47 #endif 48 49 #define FLOAT_ZERO 0x00000000 50 #define FLOAT_ONE 0x3f800000 51 #define FLOAT_TWO 0x40000000 52 #define FLOAT_THREE 0x40400000 53 #define FLOAT_EIGHT 0x41000000 54 #define FLOAT_MINUS_5 0xc0a00000 55 56 #define UNSOL_TAG_DSP 0x16 57 58 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18) 59 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15) 60 61 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8 62 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32 63 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2 64 65 #define MASTERCONTROL 0x80 66 #define MASTERCONTROL_ALLOC_DMA_CHAN 10 67 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60 68 69 #define WIDGET_CHIP_CTRL 0x15 70 #define WIDGET_DSP_CTRL 0x16 71 72 #define MEM_CONNID_MICIN1 3 73 #define MEM_CONNID_MICIN2 5 74 #define MEM_CONNID_MICOUT1 12 75 #define MEM_CONNID_MICOUT2 14 76 #define MEM_CONNID_WUH 10 77 #define MEM_CONNID_DSP 16 78 #define MEM_CONNID_DMIC 100 79 80 #define SCP_SET 0 81 #define SCP_GET 1 82 83 #define EFX_FILE "ctefx.bin" 84 #define SBZ_EFX_FILE "ctefx-sbz.bin" 85 #define R3DI_EFX_FILE "ctefx-r3di.bin" 86 87 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 88 MODULE_FIRMWARE(EFX_FILE); 89 MODULE_FIRMWARE(SBZ_EFX_FILE); 90 MODULE_FIRMWARE(R3DI_EFX_FILE); 91 #endif 92 93 static const char *const dirstr[2] = { "Playback", "Capture" }; 94 95 #define NUM_OF_OUTPUTS 3 96 enum { 97 SPEAKER_OUT, 98 HEADPHONE_OUT, 99 SURROUND_OUT 100 }; 101 102 enum { 103 DIGITAL_MIC, 104 LINE_MIC_IN 105 }; 106 107 /* Strings for Input Source Enum Control */ 108 static const char *const in_src_str[3] = {"Rear Mic", "Line", "Front Mic" }; 109 #define IN_SRC_NUM_OF_INPUTS 3 110 enum { 111 REAR_MIC, 112 REAR_LINE_IN, 113 FRONT_MIC, 114 }; 115 116 enum { 117 #define VNODE_START_NID 0x80 118 VNID_SPK = VNODE_START_NID, /* Speaker vnid */ 119 VNID_MIC, 120 VNID_HP_SEL, 121 VNID_AMIC1_SEL, 122 VNID_HP_ASEL, 123 VNID_AMIC1_ASEL, 124 VNODE_END_NID, 125 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID) 126 127 #define EFFECT_START_NID 0x90 128 #define OUT_EFFECT_START_NID EFFECT_START_NID 129 SURROUND = OUT_EFFECT_START_NID, 130 CRYSTALIZER, 131 DIALOG_PLUS, 132 SMART_VOLUME, 133 X_BASS, 134 EQUALIZER, 135 OUT_EFFECT_END_NID, 136 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID) 137 138 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID 139 ECHO_CANCELLATION = IN_EFFECT_START_NID, 140 VOICE_FOCUS, 141 MIC_SVM, 142 NOISE_REDUCTION, 143 IN_EFFECT_END_NID, 144 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID) 145 146 VOICEFX = IN_EFFECT_END_NID, 147 PLAY_ENHANCEMENT, 148 CRYSTAL_VOICE, 149 EFFECT_END_NID, 150 OUTPUT_SOURCE_ENUM, 151 INPUT_SOURCE_ENUM, 152 XBASS_XOVER, 153 EQ_PRESET_ENUM, 154 SMART_VOLUME_ENUM, 155 MIC_BOOST_ENUM 156 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID) 157 }; 158 159 /* Effects values size*/ 160 #define EFFECT_VALS_MAX_COUNT 12 161 162 /* 163 * Default values for the effect slider controls, they are in order of their 164 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then 165 * X-bass. 166 */ 167 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50}; 168 /* Amount of effect level sliders for ca0132_alt controls. */ 169 #define EFFECT_LEVEL_SLIDERS 5 170 171 /* Latency introduced by DSP blocks in milliseconds. */ 172 #define DSP_CAPTURE_INIT_LATENCY 0 173 #define DSP_CRYSTAL_VOICE_LATENCY 124 174 #define DSP_PLAYBACK_INIT_LATENCY 13 175 #define DSP_PLAY_ENHANCEMENT_LATENCY 30 176 #define DSP_SPEAKER_OUT_LATENCY 7 177 178 struct ct_effect { 179 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 180 hda_nid_t nid; 181 int mid; /*effect module ID*/ 182 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/ 183 int direct; /* 0:output; 1:input*/ 184 int params; /* number of default non-on/off params */ 185 /*effect default values, 1st is on/off. */ 186 unsigned int def_vals[EFFECT_VALS_MAX_COUNT]; 187 }; 188 189 #define EFX_DIR_OUT 0 190 #define EFX_DIR_IN 1 191 192 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = { 193 { .name = "Surround", 194 .nid = SURROUND, 195 .mid = 0x96, 196 .reqs = {0, 1}, 197 .direct = EFX_DIR_OUT, 198 .params = 1, 199 .def_vals = {0x3F800000, 0x3F2B851F} 200 }, 201 { .name = "Crystalizer", 202 .nid = CRYSTALIZER, 203 .mid = 0x96, 204 .reqs = {7, 8}, 205 .direct = EFX_DIR_OUT, 206 .params = 1, 207 .def_vals = {0x3F800000, 0x3F266666} 208 }, 209 { .name = "Dialog Plus", 210 .nid = DIALOG_PLUS, 211 .mid = 0x96, 212 .reqs = {2, 3}, 213 .direct = EFX_DIR_OUT, 214 .params = 1, 215 .def_vals = {0x00000000, 0x3F000000} 216 }, 217 { .name = "Smart Volume", 218 .nid = SMART_VOLUME, 219 .mid = 0x96, 220 .reqs = {4, 5, 6}, 221 .direct = EFX_DIR_OUT, 222 .params = 2, 223 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000} 224 }, 225 { .name = "X-Bass", 226 .nid = X_BASS, 227 .mid = 0x96, 228 .reqs = {24, 23, 25}, 229 .direct = EFX_DIR_OUT, 230 .params = 2, 231 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000} 232 }, 233 { .name = "Equalizer", 234 .nid = EQUALIZER, 235 .mid = 0x96, 236 .reqs = {9, 10, 11, 12, 13, 14, 237 15, 16, 17, 18, 19, 20}, 238 .direct = EFX_DIR_OUT, 239 .params = 11, 240 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000, 241 0x00000000, 0x00000000, 0x00000000, 0x00000000, 242 0x00000000, 0x00000000, 0x00000000, 0x00000000} 243 }, 244 { .name = "Echo Cancellation", 245 .nid = ECHO_CANCELLATION, 246 .mid = 0x95, 247 .reqs = {0, 1, 2, 3}, 248 .direct = EFX_DIR_IN, 249 .params = 3, 250 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000} 251 }, 252 { .name = "Voice Focus", 253 .nid = VOICE_FOCUS, 254 .mid = 0x95, 255 .reqs = {6, 7, 8, 9}, 256 .direct = EFX_DIR_IN, 257 .params = 3, 258 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000} 259 }, 260 { .name = "Mic SVM", 261 .nid = MIC_SVM, 262 .mid = 0x95, 263 .reqs = {44, 45}, 264 .direct = EFX_DIR_IN, 265 .params = 1, 266 .def_vals = {0x00000000, 0x3F3D70A4} 267 }, 268 { .name = "Noise Reduction", 269 .nid = NOISE_REDUCTION, 270 .mid = 0x95, 271 .reqs = {4, 5}, 272 .direct = EFX_DIR_IN, 273 .params = 1, 274 .def_vals = {0x3F800000, 0x3F000000} 275 }, 276 { .name = "VoiceFX", 277 .nid = VOICEFX, 278 .mid = 0x95, 279 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}, 280 .direct = EFX_DIR_IN, 281 .params = 8, 282 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000, 283 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000, 284 0x00000000} 285 } 286 }; 287 288 /* Tuning controls */ 289 #ifdef ENABLE_TUNING_CONTROLS 290 291 enum { 292 #define TUNING_CTL_START_NID 0xC0 293 WEDGE_ANGLE = TUNING_CTL_START_NID, 294 SVM_LEVEL, 295 EQUALIZER_BAND_0, 296 EQUALIZER_BAND_1, 297 EQUALIZER_BAND_2, 298 EQUALIZER_BAND_3, 299 EQUALIZER_BAND_4, 300 EQUALIZER_BAND_5, 301 EQUALIZER_BAND_6, 302 EQUALIZER_BAND_7, 303 EQUALIZER_BAND_8, 304 EQUALIZER_BAND_9, 305 TUNING_CTL_END_NID 306 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID) 307 }; 308 309 struct ct_tuning_ctl { 310 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 311 hda_nid_t parent_nid; 312 hda_nid_t nid; 313 int mid; /*effect module ID*/ 314 int req; /*effect module request*/ 315 int direct; /* 0:output; 1:input*/ 316 unsigned int def_val;/*effect default values*/ 317 }; 318 319 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = { 320 { .name = "Wedge Angle", 321 .parent_nid = VOICE_FOCUS, 322 .nid = WEDGE_ANGLE, 323 .mid = 0x95, 324 .req = 8, 325 .direct = EFX_DIR_IN, 326 .def_val = 0x41F00000 327 }, 328 { .name = "SVM Level", 329 .parent_nid = MIC_SVM, 330 .nid = SVM_LEVEL, 331 .mid = 0x95, 332 .req = 45, 333 .direct = EFX_DIR_IN, 334 .def_val = 0x3F3D70A4 335 }, 336 { .name = "EQ Band0", 337 .parent_nid = EQUALIZER, 338 .nid = EQUALIZER_BAND_0, 339 .mid = 0x96, 340 .req = 11, 341 .direct = EFX_DIR_OUT, 342 .def_val = 0x00000000 343 }, 344 { .name = "EQ Band1", 345 .parent_nid = EQUALIZER, 346 .nid = EQUALIZER_BAND_1, 347 .mid = 0x96, 348 .req = 12, 349 .direct = EFX_DIR_OUT, 350 .def_val = 0x00000000 351 }, 352 { .name = "EQ Band2", 353 .parent_nid = EQUALIZER, 354 .nid = EQUALIZER_BAND_2, 355 .mid = 0x96, 356 .req = 13, 357 .direct = EFX_DIR_OUT, 358 .def_val = 0x00000000 359 }, 360 { .name = "EQ Band3", 361 .parent_nid = EQUALIZER, 362 .nid = EQUALIZER_BAND_3, 363 .mid = 0x96, 364 .req = 14, 365 .direct = EFX_DIR_OUT, 366 .def_val = 0x00000000 367 }, 368 { .name = "EQ Band4", 369 .parent_nid = EQUALIZER, 370 .nid = EQUALIZER_BAND_4, 371 .mid = 0x96, 372 .req = 15, 373 .direct = EFX_DIR_OUT, 374 .def_val = 0x00000000 375 }, 376 { .name = "EQ Band5", 377 .parent_nid = EQUALIZER, 378 .nid = EQUALIZER_BAND_5, 379 .mid = 0x96, 380 .req = 16, 381 .direct = EFX_DIR_OUT, 382 .def_val = 0x00000000 383 }, 384 { .name = "EQ Band6", 385 .parent_nid = EQUALIZER, 386 .nid = EQUALIZER_BAND_6, 387 .mid = 0x96, 388 .req = 17, 389 .direct = EFX_DIR_OUT, 390 .def_val = 0x00000000 391 }, 392 { .name = "EQ Band7", 393 .parent_nid = EQUALIZER, 394 .nid = EQUALIZER_BAND_7, 395 .mid = 0x96, 396 .req = 18, 397 .direct = EFX_DIR_OUT, 398 .def_val = 0x00000000 399 }, 400 { .name = "EQ Band8", 401 .parent_nid = EQUALIZER, 402 .nid = EQUALIZER_BAND_8, 403 .mid = 0x96, 404 .req = 19, 405 .direct = EFX_DIR_OUT, 406 .def_val = 0x00000000 407 }, 408 { .name = "EQ Band9", 409 .parent_nid = EQUALIZER, 410 .nid = EQUALIZER_BAND_9, 411 .mid = 0x96, 412 .req = 20, 413 .direct = EFX_DIR_OUT, 414 .def_val = 0x00000000 415 } 416 }; 417 #endif 418 419 /* Voice FX Presets */ 420 #define VOICEFX_MAX_PARAM_COUNT 9 421 422 struct ct_voicefx { 423 char *name; 424 hda_nid_t nid; 425 int mid; 426 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/ 427 }; 428 429 struct ct_voicefx_preset { 430 char *name; /*preset name*/ 431 unsigned int vals[VOICEFX_MAX_PARAM_COUNT]; 432 }; 433 434 static const struct ct_voicefx ca0132_voicefx = { 435 .name = "VoiceFX Capture Switch", 436 .nid = VOICEFX, 437 .mid = 0x95, 438 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18} 439 }; 440 441 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = { 442 { .name = "Neutral", 443 .vals = { 0x00000000, 0x43C80000, 0x44AF0000, 444 0x44FA0000, 0x3F800000, 0x3F800000, 445 0x3F800000, 0x00000000, 0x00000000 } 446 }, 447 { .name = "Female2Male", 448 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 449 0x44FA0000, 0x3F19999A, 0x3F866666, 450 0x3F800000, 0x00000000, 0x00000000 } 451 }, 452 { .name = "Male2Female", 453 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 454 0x450AC000, 0x4017AE14, 0x3F6B851F, 455 0x3F800000, 0x00000000, 0x00000000 } 456 }, 457 { .name = "ScrappyKid", 458 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 459 0x44FA0000, 0x40400000, 0x3F28F5C3, 460 0x3F800000, 0x00000000, 0x00000000 } 461 }, 462 { .name = "Elderly", 463 .vals = { 0x3F800000, 0x44324000, 0x44BB8000, 464 0x44E10000, 0x3FB33333, 0x3FB9999A, 465 0x3F800000, 0x3E3A2E43, 0x00000000 } 466 }, 467 { .name = "Orc", 468 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000, 469 0x45098000, 0x3F266666, 0x3FC00000, 470 0x3F800000, 0x00000000, 0x00000000 } 471 }, 472 { .name = "Elf", 473 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000, 474 0x45193000, 0x3F8E147B, 0x3F75C28F, 475 0x3F800000, 0x00000000, 0x00000000 } 476 }, 477 { .name = "Dwarf", 478 .vals = { 0x3F800000, 0x43930000, 0x44BEE000, 479 0x45007000, 0x3F451EB8, 0x3F7851EC, 480 0x3F800000, 0x00000000, 0x00000000 } 481 }, 482 { .name = "AlienBrute", 483 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF, 484 0x451F6000, 0x3F266666, 0x3FA7D945, 485 0x3F800000, 0x3CF5C28F, 0x00000000 } 486 }, 487 { .name = "Robot", 488 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 489 0x44FA0000, 0x3FB2718B, 0x3F800000, 490 0xBC07010E, 0x00000000, 0x00000000 } 491 }, 492 { .name = "Marine", 493 .vals = { 0x3F800000, 0x43C20000, 0x44906000, 494 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71, 495 0x3F0A3D71, 0x00000000, 0x00000000 } 496 }, 497 { .name = "Emo", 498 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 499 0x44FA0000, 0x3F800000, 0x3F800000, 500 0x3E4CCCCD, 0x00000000, 0x00000000 } 501 }, 502 { .name = "DeepVoice", 503 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF, 504 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA, 505 0x3F800000, 0x00000000, 0x00000000 } 506 }, 507 { .name = "Munchkin", 508 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 509 0x44FA0000, 0x3F800000, 0x3F1A043C, 510 0x3F800000, 0x00000000, 0x00000000 } 511 } 512 }; 513 514 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */ 515 516 #define EQ_PRESET_MAX_PARAM_COUNT 11 517 518 struct ct_eq { 519 char *name; 520 hda_nid_t nid; 521 int mid; 522 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/ 523 }; 524 525 struct ct_eq_preset { 526 char *name; /*preset name*/ 527 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT]; 528 }; 529 530 static const struct ct_eq ca0132_alt_eq_enum = { 531 .name = "FX: Equalizer Preset Switch", 532 .nid = EQ_PRESET_ENUM, 533 .mid = 0x96, 534 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20} 535 }; 536 537 538 static const struct ct_eq_preset ca0132_alt_eq_presets[] = { 539 { .name = "Flat", 540 .vals = { 0x00000000, 0x00000000, 0x00000000, 541 0x00000000, 0x00000000, 0x00000000, 542 0x00000000, 0x00000000, 0x00000000, 543 0x00000000, 0x00000000 } 544 }, 545 { .name = "Acoustic", 546 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD, 547 0x40000000, 0x00000000, 0x00000000, 548 0x00000000, 0x00000000, 0x40000000, 549 0x40000000, 0x40000000 } 550 }, 551 { .name = "Classical", 552 .vals = { 0x00000000, 0x00000000, 0x40C00000, 553 0x40C00000, 0x40466666, 0x00000000, 554 0x00000000, 0x00000000, 0x00000000, 555 0x40466666, 0x40466666 } 556 }, 557 { .name = "Country", 558 .vals = { 0x00000000, 0xBF99999A, 0x00000000, 559 0x3FA66666, 0x3FA66666, 0x3F8CCCCD, 560 0x00000000, 0x00000000, 0x40000000, 561 0x40466666, 0x40800000 } 562 }, 563 { .name = "Dance", 564 .vals = { 0x00000000, 0xBF99999A, 0x40000000, 565 0x40466666, 0x40866666, 0xBF99999A, 566 0xBF99999A, 0x00000000, 0x00000000, 567 0x40800000, 0x40800000 } 568 }, 569 { .name = "Jazz", 570 .vals = { 0x00000000, 0x00000000, 0x00000000, 571 0x3F8CCCCD, 0x40800000, 0x40800000, 572 0x40800000, 0x00000000, 0x3F8CCCCD, 573 0x40466666, 0x40466666 } 574 }, 575 { .name = "New Age", 576 .vals = { 0x00000000, 0x00000000, 0x40000000, 577 0x40000000, 0x00000000, 0x00000000, 578 0x00000000, 0x3F8CCCCD, 0x40000000, 579 0x40000000, 0x40000000 } 580 }, 581 { .name = "Pop", 582 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000, 583 0x40000000, 0x40000000, 0x00000000, 584 0xBF99999A, 0xBF99999A, 0x00000000, 585 0x40466666, 0x40C00000 } 586 }, 587 { .name = "Rock", 588 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A, 589 0x3F8CCCCD, 0x40000000, 0xBF99999A, 590 0xBF99999A, 0x00000000, 0x00000000, 591 0x40800000, 0x40800000 } 592 }, 593 { .name = "Vocal", 594 .vals = { 0x00000000, 0xC0000000, 0xBF99999A, 595 0xBF99999A, 0x00000000, 0x40466666, 596 0x40800000, 0x40466666, 0x00000000, 597 0x00000000, 0x3F8CCCCD } 598 } 599 }; 600 601 /* DSP command sequences for ca0132_alt_select_out */ 602 #define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */ 603 struct ca0132_alt_out_set { 604 char *name; /*preset name*/ 605 unsigned char commands; 606 unsigned int mids[ALT_OUT_SET_MAX_COMMANDS]; 607 unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS]; 608 unsigned int vals[ALT_OUT_SET_MAX_COMMANDS]; 609 }; 610 611 static const struct ca0132_alt_out_set alt_out_presets[] = { 612 { .name = "Line Out", 613 .commands = 7, 614 .mids = { 0x96, 0x96, 0x96, 0x8F, 615 0x96, 0x96, 0x96 }, 616 .reqs = { 0x19, 0x17, 0x18, 0x01, 617 0x1F, 0x15, 0x3A }, 618 .vals = { 0x3F000000, 0x42A00000, 0x00000000, 619 0x00000000, 0x00000000, 0x00000000, 620 0x00000000 } 621 }, 622 { .name = "Headphone", 623 .commands = 7, 624 .mids = { 0x96, 0x96, 0x96, 0x8F, 625 0x96, 0x96, 0x96 }, 626 .reqs = { 0x19, 0x17, 0x18, 0x01, 627 0x1F, 0x15, 0x3A }, 628 .vals = { 0x3F000000, 0x42A00000, 0x00000000, 629 0x00000000, 0x00000000, 0x00000000, 630 0x00000000 } 631 }, 632 { .name = "Surround", 633 .commands = 8, 634 .mids = { 0x96, 0x8F, 0x96, 0x96, 635 0x96, 0x96, 0x96, 0x96 }, 636 .reqs = { 0x18, 0x01, 0x1F, 0x15, 637 0x3A, 0x1A, 0x1B, 0x1C }, 638 .vals = { 0x00000000, 0x00000000, 0x00000000, 639 0x00000000, 0x00000000, 0x00000000, 640 0x00000000, 0x00000000 } 641 } 642 }; 643 644 /* 645 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume, 646 * and I don't know what the third req is, but it's always zero. I assume it's 647 * some sort of update or set command to tell the DSP there's new volume info. 648 */ 649 #define DSP_VOL_OUT 0 650 #define DSP_VOL_IN 1 651 652 struct ct_dsp_volume_ctl { 653 hda_nid_t vnid; 654 int mid; /* module ID*/ 655 unsigned int reqs[3]; /* scp req ID */ 656 }; 657 658 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = { 659 { .vnid = VNID_SPK, 660 .mid = 0x32, 661 .reqs = {3, 4, 2} 662 }, 663 { .vnid = VNID_MIC, 664 .mid = 0x37, 665 .reqs = {2, 3, 1} 666 } 667 }; 668 669 enum hda_cmd_vendor_io { 670 /* for DspIO node */ 671 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000, 672 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100, 673 674 VENDOR_DSPIO_STATUS = 0xF01, 675 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702, 676 VENDOR_DSPIO_SCP_READ_DATA = 0xF02, 677 VENDOR_DSPIO_DSP_INIT = 0x703, 678 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704, 679 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04, 680 681 /* for ChipIO node */ 682 VENDOR_CHIPIO_ADDRESS_LOW = 0x000, 683 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100, 684 VENDOR_CHIPIO_STREAM_FORMAT = 0x200, 685 VENDOR_CHIPIO_DATA_LOW = 0x300, 686 VENDOR_CHIPIO_DATA_HIGH = 0x400, 687 688 VENDOR_CHIPIO_GET_PARAMETER = 0xF00, 689 VENDOR_CHIPIO_STATUS = 0xF01, 690 VENDOR_CHIPIO_HIC_POST_READ = 0x702, 691 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03, 692 693 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707, 694 VENDOR_CHIPIO_8051_DATA_READ = 0xF07, 695 696 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A, 697 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A, 698 699 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C, 700 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C, 701 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D, 702 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E, 703 VENDOR_CHIPIO_FLAG_SET = 0x70F, 704 VENDOR_CHIPIO_FLAGS_GET = 0xF0F, 705 VENDOR_CHIPIO_PARAM_SET = 0x710, 706 VENDOR_CHIPIO_PARAM_GET = 0xF10, 707 708 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711, 709 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712, 710 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12, 711 VENDOR_CHIPIO_PORT_FREE_SET = 0x713, 712 713 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17, 714 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717, 715 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18, 716 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718, 717 718 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788, 719 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88, 720 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789, 721 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89, 722 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A, 723 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A, 724 725 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D 726 }; 727 728 /* 729 * Control flag IDs 730 */ 731 enum control_flag_id { 732 /* Connection manager stream setup is bypassed/enabled */ 733 CONTROL_FLAG_C_MGR = 0, 734 /* DSP DMA is bypassed/enabled */ 735 CONTROL_FLAG_DMA = 1, 736 /* 8051 'idle' mode is disabled/enabled */ 737 CONTROL_FLAG_IDLE_ENABLE = 2, 738 /* Tracker for the SPDIF-in path is bypassed/enabled */ 739 CONTROL_FLAG_TRACKER = 3, 740 /* DigitalOut to Spdif2Out connection is disabled/enabled */ 741 CONTROL_FLAG_SPDIF2OUT = 4, 742 /* Digital Microphone is disabled/enabled */ 743 CONTROL_FLAG_DMIC = 5, 744 /* ADC_B rate is 48 kHz/96 kHz */ 745 CONTROL_FLAG_ADC_B_96KHZ = 6, 746 /* ADC_C rate is 48 kHz/96 kHz */ 747 CONTROL_FLAG_ADC_C_96KHZ = 7, 748 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */ 749 CONTROL_FLAG_DAC_96KHZ = 8, 750 /* DSP rate is 48 kHz/96 kHz */ 751 CONTROL_FLAG_DSP_96KHZ = 9, 752 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */ 753 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10, 754 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */ 755 CONTROL_FLAG_SRC_RATE_96KHZ = 11, 756 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */ 757 CONTROL_FLAG_DECODE_LOOP = 12, 758 /* De-emphasis filter on DAC-1 disabled/enabled */ 759 CONTROL_FLAG_DAC1_DEEMPHASIS = 13, 760 /* De-emphasis filter on DAC-2 disabled/enabled */ 761 CONTROL_FLAG_DAC2_DEEMPHASIS = 14, 762 /* De-emphasis filter on DAC-3 disabled/enabled */ 763 CONTROL_FLAG_DAC3_DEEMPHASIS = 15, 764 /* High-pass filter on ADC_B disabled/enabled */ 765 CONTROL_FLAG_ADC_B_HIGH_PASS = 16, 766 /* High-pass filter on ADC_C disabled/enabled */ 767 CONTROL_FLAG_ADC_C_HIGH_PASS = 17, 768 /* Common mode on Port_A disabled/enabled */ 769 CONTROL_FLAG_PORT_A_COMMON_MODE = 18, 770 /* Common mode on Port_D disabled/enabled */ 771 CONTROL_FLAG_PORT_D_COMMON_MODE = 19, 772 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */ 773 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20, 774 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */ 775 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21, 776 /* ASI rate is 48kHz/96kHz */ 777 CONTROL_FLAG_ASI_96KHZ = 22, 778 /* DAC power settings able to control attached ports no/yes */ 779 CONTROL_FLAG_DACS_CONTROL_PORTS = 23, 780 /* Clock Stop OK reporting is disabled/enabled */ 781 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24, 782 /* Number of control flags */ 783 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1) 784 }; 785 786 /* 787 * Control parameter IDs 788 */ 789 enum control_param_id { 790 /* 0: None, 1: Mic1In*/ 791 CONTROL_PARAM_VIP_SOURCE = 1, 792 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */ 793 CONTROL_PARAM_SPDIF1_SOURCE = 2, 794 /* Port A output stage gain setting to use when 16 Ohm output 795 * impedance is selected*/ 796 CONTROL_PARAM_PORTA_160OHM_GAIN = 8, 797 /* Port D output stage gain setting to use when 16 Ohm output 798 * impedance is selected*/ 799 CONTROL_PARAM_PORTD_160OHM_GAIN = 10, 800 801 /* Stream Control */ 802 803 /* Select stream with the given ID */ 804 CONTROL_PARAM_STREAM_ID = 24, 805 /* Source connection point for the selected stream */ 806 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25, 807 /* Destination connection point for the selected stream */ 808 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26, 809 /* Number of audio channels in the selected stream */ 810 CONTROL_PARAM_STREAMS_CHANNELS = 27, 811 /*Enable control for the selected stream */ 812 CONTROL_PARAM_STREAM_CONTROL = 28, 813 814 /* Connection Point Control */ 815 816 /* Select connection point with the given ID */ 817 CONTROL_PARAM_CONN_POINT_ID = 29, 818 /* Connection point sample rate */ 819 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30, 820 821 /* Node Control */ 822 823 /* Select HDA node with the given ID */ 824 CONTROL_PARAM_NODE_ID = 31 825 }; 826 827 /* 828 * Dsp Io Status codes 829 */ 830 enum hda_vendor_status_dspio { 831 /* Success */ 832 VENDOR_STATUS_DSPIO_OK = 0x00, 833 /* Busy, unable to accept new command, the host must retry */ 834 VENDOR_STATUS_DSPIO_BUSY = 0x01, 835 /* SCP command queue is full */ 836 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02, 837 /* SCP response queue is empty */ 838 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03 839 }; 840 841 /* 842 * Chip Io Status codes 843 */ 844 enum hda_vendor_status_chipio { 845 /* Success */ 846 VENDOR_STATUS_CHIPIO_OK = 0x00, 847 /* Busy, unable to accept new command, the host must retry */ 848 VENDOR_STATUS_CHIPIO_BUSY = 0x01 849 }; 850 851 /* 852 * CA0132 sample rate 853 */ 854 enum ca0132_sample_rate { 855 SR_6_000 = 0x00, 856 SR_8_000 = 0x01, 857 SR_9_600 = 0x02, 858 SR_11_025 = 0x03, 859 SR_16_000 = 0x04, 860 SR_22_050 = 0x05, 861 SR_24_000 = 0x06, 862 SR_32_000 = 0x07, 863 SR_44_100 = 0x08, 864 SR_48_000 = 0x09, 865 SR_88_200 = 0x0A, 866 SR_96_000 = 0x0B, 867 SR_144_000 = 0x0C, 868 SR_176_400 = 0x0D, 869 SR_192_000 = 0x0E, 870 SR_384_000 = 0x0F, 871 872 SR_COUNT = 0x10, 873 874 SR_RATE_UNKNOWN = 0x1F 875 }; 876 877 enum dsp_download_state { 878 DSP_DOWNLOAD_FAILED = -1, 879 DSP_DOWNLOAD_INIT = 0, 880 DSP_DOWNLOADING = 1, 881 DSP_DOWNLOADED = 2 882 }; 883 884 /* retrieve parameters from hda format */ 885 #define get_hdafmt_chs(fmt) (fmt & 0xf) 886 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7) 887 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f) 888 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1) 889 890 /* 891 * CA0132 specific 892 */ 893 894 struct ca0132_spec { 895 const struct snd_kcontrol_new *mixers[5]; 896 unsigned int num_mixers; 897 const struct hda_verb *base_init_verbs; 898 const struct hda_verb *base_exit_verbs; 899 const struct hda_verb *chip_init_verbs; 900 const struct hda_verb *sbz_init_verbs; 901 struct hda_verb *spec_init_verbs; 902 struct auto_pin_cfg autocfg; 903 904 /* Nodes configurations */ 905 struct hda_multi_out multiout; 906 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS]; 907 hda_nid_t dacs[AUTO_CFG_MAX_OUTS]; 908 unsigned int num_outputs; 909 hda_nid_t input_pins[AUTO_PIN_LAST]; 910 hda_nid_t adcs[AUTO_PIN_LAST]; 911 hda_nid_t dig_out; 912 hda_nid_t dig_in; 913 unsigned int num_inputs; 914 hda_nid_t shared_mic_nid; 915 hda_nid_t shared_out_nid; 916 hda_nid_t unsol_tag_hp; 917 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */ 918 hda_nid_t unsol_tag_amic1; 919 920 /* chip access */ 921 struct mutex chipio_mutex; /* chip access mutex */ 922 u32 curr_chip_addx; 923 924 /* DSP download related */ 925 enum dsp_download_state dsp_state; 926 unsigned int dsp_stream_id; 927 unsigned int wait_scp; 928 unsigned int wait_scp_header; 929 unsigned int wait_num_data; 930 unsigned int scp_resp_header; 931 unsigned int scp_resp_data[4]; 932 unsigned int scp_resp_count; 933 bool alt_firmware_present; 934 bool startup_check_entered; 935 bool dsp_reload; 936 937 /* mixer and effects related */ 938 unsigned char dmic_ctl; 939 int cur_out_type; 940 int cur_mic_type; 941 long vnode_lvol[VNODES_COUNT]; 942 long vnode_rvol[VNODES_COUNT]; 943 long vnode_lswitch[VNODES_COUNT]; 944 long vnode_rswitch[VNODES_COUNT]; 945 long effects_switch[EFFECTS_COUNT]; 946 long voicefx_val; 947 long cur_mic_boost; 948 /* ca0132_alt control related values */ 949 unsigned char in_enum_val; 950 unsigned char out_enum_val; 951 unsigned char mic_boost_enum_val; 952 unsigned char smart_volume_setting; 953 long fx_ctl_val[EFFECT_LEVEL_SLIDERS]; 954 long xbass_xover_freq; 955 long eq_preset_val; 956 unsigned int tlv[4]; 957 struct hda_vmaster_mute_hook vmaster_mute; 958 959 960 struct hda_codec *codec; 961 struct delayed_work unsol_hp_work; 962 int quirk; 963 964 #ifdef ENABLE_TUNING_CONTROLS 965 long cur_ctl_vals[TUNING_CTLS_COUNT]; 966 #endif 967 /* 968 * Sound Blaster Z PCI region 2 iomem, used for input and output 969 * switching, and other unknown commands. 970 */ 971 void __iomem *mem_base; 972 973 /* 974 * Whether or not to use the alt functions like alt_select_out, 975 * alt_select_in, etc. Only used on desktop codecs for now, because of 976 * surround sound support. 977 */ 978 bool use_alt_functions; 979 980 /* 981 * Whether or not to use alt controls: volume effect sliders, EQ 982 * presets, smart volume presets, and new control names with FX prefix. 983 * Renames PlayEnhancement and CrystalVoice too. 984 */ 985 bool use_alt_controls; 986 }; 987 988 /* 989 * CA0132 quirks table 990 */ 991 enum { 992 QUIRK_NONE, 993 QUIRK_ALIENWARE, 994 QUIRK_ALIENWARE_M17XR4, 995 QUIRK_SBZ, 996 QUIRK_R3DI, 997 }; 998 999 static const struct hda_pintbl alienware_pincfgs[] = { 1000 { 0x0b, 0x90170110 }, /* Builtin Speaker */ 1001 { 0x0c, 0x411111f0 }, /* N/A */ 1002 { 0x0d, 0x411111f0 }, /* N/A */ 1003 { 0x0e, 0x411111f0 }, /* N/A */ 1004 { 0x0f, 0x0321101f }, /* HP */ 1005 { 0x10, 0x411111f0 }, /* Headset? disabled for now */ 1006 { 0x11, 0x03a11021 }, /* Mic */ 1007 { 0x12, 0xd5a30140 }, /* Builtin Mic */ 1008 { 0x13, 0x411111f0 }, /* N/A */ 1009 { 0x18, 0x411111f0 }, /* N/A */ 1010 {} 1011 }; 1012 1013 /* Sound Blaster Z pin configs taken from Windows Driver */ 1014 static const struct hda_pintbl sbz_pincfgs[] = { 1015 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1016 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1017 { 0x0d, 0x014510f0 }, /* Digital Out */ 1018 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1019 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */ 1020 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1021 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1022 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1023 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1024 { 0x18, 0x50d000f0 }, /* N/A */ 1025 {} 1026 }; 1027 1028 /* Recon3D integrated pin configs taken from Windows Driver */ 1029 static const struct hda_pintbl r3di_pincfgs[] = { 1030 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1031 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1032 { 0x0d, 0x014510f0 }, /* Digital Out */ 1033 { 0x0e, 0x41c520f0 }, /* SPDIF In */ 1034 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1035 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1036 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1037 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1038 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1039 { 0x18, 0x500000f0 }, /* N/A */ 1040 {} 1041 }; 1042 1043 static const struct snd_pci_quirk ca0132_quirks[] = { 1044 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4), 1045 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE), 1046 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE), 1047 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE), 1048 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ), 1049 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ), 1050 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI), 1051 SND_PCI_QUIRK(0x1458, 0xA036, "Recon3Di", QUIRK_R3DI), 1052 {} 1053 }; 1054 1055 /* 1056 * CA0132 codec access 1057 */ 1058 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid, 1059 unsigned int verb, unsigned int parm, unsigned int *res) 1060 { 1061 unsigned int response; 1062 response = snd_hda_codec_read(codec, nid, 0, verb, parm); 1063 *res = response; 1064 1065 return ((response == -1) ? -1 : 0); 1066 } 1067 1068 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid, 1069 unsigned short converter_format, unsigned int *res) 1070 { 1071 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT, 1072 converter_format & 0xffff, res); 1073 } 1074 1075 static int codec_set_converter_stream_channel(struct hda_codec *codec, 1076 hda_nid_t nid, unsigned char stream, 1077 unsigned char channel, unsigned int *res) 1078 { 1079 unsigned char converter_stream_channel = 0; 1080 1081 converter_stream_channel = (stream << 4) | (channel & 0x0f); 1082 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID, 1083 converter_stream_channel, res); 1084 } 1085 1086 /* Chip access helper function */ 1087 static int chipio_send(struct hda_codec *codec, 1088 unsigned int reg, 1089 unsigned int data) 1090 { 1091 unsigned int res; 1092 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1093 1094 /* send bits of data specified by reg */ 1095 do { 1096 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1097 reg, data); 1098 if (res == VENDOR_STATUS_CHIPIO_OK) 1099 return 0; 1100 msleep(20); 1101 } while (time_before(jiffies, timeout)); 1102 1103 return -EIO; 1104 } 1105 1106 /* 1107 * Write chip address through the vendor widget -- NOT protected by the Mutex! 1108 */ 1109 static int chipio_write_address(struct hda_codec *codec, 1110 unsigned int chip_addx) 1111 { 1112 struct ca0132_spec *spec = codec->spec; 1113 int res; 1114 1115 if (spec->curr_chip_addx == chip_addx) 1116 return 0; 1117 1118 /* send low 16 bits of the address */ 1119 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW, 1120 chip_addx & 0xffff); 1121 1122 if (res != -EIO) { 1123 /* send high 16 bits of the address */ 1124 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH, 1125 chip_addx >> 16); 1126 } 1127 1128 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx; 1129 1130 return res; 1131 } 1132 1133 /* 1134 * Write data through the vendor widget -- NOT protected by the Mutex! 1135 */ 1136 static int chipio_write_data(struct hda_codec *codec, unsigned int data) 1137 { 1138 struct ca0132_spec *spec = codec->spec; 1139 int res; 1140 1141 /* send low 16 bits of the data */ 1142 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff); 1143 1144 if (res != -EIO) { 1145 /* send high 16 bits of the data */ 1146 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH, 1147 data >> 16); 1148 } 1149 1150 /*If no error encountered, automatically increment the address 1151 as per chip behaviour*/ 1152 spec->curr_chip_addx = (res != -EIO) ? 1153 (spec->curr_chip_addx + 4) : ~0U; 1154 return res; 1155 } 1156 1157 /* 1158 * Write multiple data through the vendor widget -- NOT protected by the Mutex! 1159 */ 1160 static int chipio_write_data_multiple(struct hda_codec *codec, 1161 const u32 *data, 1162 unsigned int count) 1163 { 1164 int status = 0; 1165 1166 if (data == NULL) { 1167 codec_dbg(codec, "chipio_write_data null ptr\n"); 1168 return -EINVAL; 1169 } 1170 1171 while ((count-- != 0) && (status == 0)) 1172 status = chipio_write_data(codec, *data++); 1173 1174 return status; 1175 } 1176 1177 1178 /* 1179 * Read data through the vendor widget -- NOT protected by the Mutex! 1180 */ 1181 static int chipio_read_data(struct hda_codec *codec, unsigned int *data) 1182 { 1183 struct ca0132_spec *spec = codec->spec; 1184 int res; 1185 1186 /* post read */ 1187 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0); 1188 1189 if (res != -EIO) { 1190 /* read status */ 1191 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 1192 } 1193 1194 if (res != -EIO) { 1195 /* read data */ 1196 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1197 VENDOR_CHIPIO_HIC_READ_DATA, 1198 0); 1199 } 1200 1201 /*If no error encountered, automatically increment the address 1202 as per chip behaviour*/ 1203 spec->curr_chip_addx = (res != -EIO) ? 1204 (spec->curr_chip_addx + 4) : ~0U; 1205 return res; 1206 } 1207 1208 /* 1209 * Write given value to the given address through the chip I/O widget. 1210 * protected by the Mutex 1211 */ 1212 static int chipio_write(struct hda_codec *codec, 1213 unsigned int chip_addx, const unsigned int data) 1214 { 1215 struct ca0132_spec *spec = codec->spec; 1216 int err; 1217 1218 mutex_lock(&spec->chipio_mutex); 1219 1220 /* write the address, and if successful proceed to write data */ 1221 err = chipio_write_address(codec, chip_addx); 1222 if (err < 0) 1223 goto exit; 1224 1225 err = chipio_write_data(codec, data); 1226 if (err < 0) 1227 goto exit; 1228 1229 exit: 1230 mutex_unlock(&spec->chipio_mutex); 1231 return err; 1232 } 1233 1234 /* 1235 * Write given value to the given address through the chip I/O widget. 1236 * not protected by the Mutex 1237 */ 1238 static int chipio_write_no_mutex(struct hda_codec *codec, 1239 unsigned int chip_addx, const unsigned int data) 1240 { 1241 int err; 1242 1243 1244 /* write the address, and if successful proceed to write data */ 1245 err = chipio_write_address(codec, chip_addx); 1246 if (err < 0) 1247 goto exit; 1248 1249 err = chipio_write_data(codec, data); 1250 if (err < 0) 1251 goto exit; 1252 1253 exit: 1254 return err; 1255 } 1256 1257 /* 1258 * Write multiple values to the given address through the chip I/O widget. 1259 * protected by the Mutex 1260 */ 1261 static int chipio_write_multiple(struct hda_codec *codec, 1262 u32 chip_addx, 1263 const u32 *data, 1264 unsigned int count) 1265 { 1266 struct ca0132_spec *spec = codec->spec; 1267 int status; 1268 1269 mutex_lock(&spec->chipio_mutex); 1270 status = chipio_write_address(codec, chip_addx); 1271 if (status < 0) 1272 goto error; 1273 1274 status = chipio_write_data_multiple(codec, data, count); 1275 error: 1276 mutex_unlock(&spec->chipio_mutex); 1277 1278 return status; 1279 } 1280 1281 /* 1282 * Read the given address through the chip I/O widget 1283 * protected by the Mutex 1284 */ 1285 static int chipio_read(struct hda_codec *codec, 1286 unsigned int chip_addx, unsigned int *data) 1287 { 1288 struct ca0132_spec *spec = codec->spec; 1289 int err; 1290 1291 mutex_lock(&spec->chipio_mutex); 1292 1293 /* write the address, and if successful proceed to write data */ 1294 err = chipio_write_address(codec, chip_addx); 1295 if (err < 0) 1296 goto exit; 1297 1298 err = chipio_read_data(codec, data); 1299 if (err < 0) 1300 goto exit; 1301 1302 exit: 1303 mutex_unlock(&spec->chipio_mutex); 1304 return err; 1305 } 1306 1307 /* 1308 * Set chip control flags through the chip I/O widget. 1309 */ 1310 static void chipio_set_control_flag(struct hda_codec *codec, 1311 enum control_flag_id flag_id, 1312 bool flag_state) 1313 { 1314 unsigned int val; 1315 unsigned int flag_bit; 1316 1317 flag_bit = (flag_state ? 1 : 0); 1318 val = (flag_bit << 7) | (flag_id); 1319 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1320 VENDOR_CHIPIO_FLAG_SET, val); 1321 } 1322 1323 /* 1324 * Set chip parameters through the chip I/O widget. 1325 */ 1326 static void chipio_set_control_param(struct hda_codec *codec, 1327 enum control_param_id param_id, int param_val) 1328 { 1329 struct ca0132_spec *spec = codec->spec; 1330 int val; 1331 1332 if ((param_id < 32) && (param_val < 8)) { 1333 val = (param_val << 5) | (param_id); 1334 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1335 VENDOR_CHIPIO_PARAM_SET, val); 1336 } else { 1337 mutex_lock(&spec->chipio_mutex); 1338 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1339 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1340 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1341 param_id); 1342 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1343 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1344 param_val); 1345 } 1346 mutex_unlock(&spec->chipio_mutex); 1347 } 1348 } 1349 1350 /* 1351 * Set chip parameters through the chip I/O widget. NO MUTEX. 1352 */ 1353 static void chipio_set_control_param_no_mutex(struct hda_codec *codec, 1354 enum control_param_id param_id, int param_val) 1355 { 1356 int val; 1357 1358 if ((param_id < 32) && (param_val < 8)) { 1359 val = (param_val << 5) | (param_id); 1360 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1361 VENDOR_CHIPIO_PARAM_SET, val); 1362 } else { 1363 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1364 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1365 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1366 param_id); 1367 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1368 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1369 param_val); 1370 } 1371 } 1372 } 1373 /* 1374 * Connect stream to a source point, and then connect 1375 * that source point to a destination point. 1376 */ 1377 static void chipio_set_stream_source_dest(struct hda_codec *codec, 1378 int streamid, int source_point, int dest_point) 1379 { 1380 chipio_set_control_param_no_mutex(codec, 1381 CONTROL_PARAM_STREAM_ID, streamid); 1382 chipio_set_control_param_no_mutex(codec, 1383 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point); 1384 chipio_set_control_param_no_mutex(codec, 1385 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point); 1386 } 1387 1388 /* 1389 * Set number of channels in the selected stream. 1390 */ 1391 static void chipio_set_stream_channels(struct hda_codec *codec, 1392 int streamid, unsigned int channels) 1393 { 1394 chipio_set_control_param_no_mutex(codec, 1395 CONTROL_PARAM_STREAM_ID, streamid); 1396 chipio_set_control_param_no_mutex(codec, 1397 CONTROL_PARAM_STREAMS_CHANNELS, channels); 1398 } 1399 1400 /* 1401 * Enable/Disable audio stream. 1402 */ 1403 static void chipio_set_stream_control(struct hda_codec *codec, 1404 int streamid, int enable) 1405 { 1406 chipio_set_control_param_no_mutex(codec, 1407 CONTROL_PARAM_STREAM_ID, streamid); 1408 chipio_set_control_param_no_mutex(codec, 1409 CONTROL_PARAM_STREAM_CONTROL, enable); 1410 } 1411 1412 1413 /* 1414 * Set sampling rate of the connection point. NO MUTEX. 1415 */ 1416 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec, 1417 int connid, enum ca0132_sample_rate rate) 1418 { 1419 chipio_set_control_param_no_mutex(codec, 1420 CONTROL_PARAM_CONN_POINT_ID, connid); 1421 chipio_set_control_param_no_mutex(codec, 1422 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate); 1423 } 1424 1425 /* 1426 * Set sampling rate of the connection point. 1427 */ 1428 static void chipio_set_conn_rate(struct hda_codec *codec, 1429 int connid, enum ca0132_sample_rate rate) 1430 { 1431 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid); 1432 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, 1433 rate); 1434 } 1435 1436 /* 1437 * Enable clocks. 1438 */ 1439 static void chipio_enable_clocks(struct hda_codec *codec) 1440 { 1441 struct ca0132_spec *spec = codec->spec; 1442 1443 mutex_lock(&spec->chipio_mutex); 1444 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1445 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0); 1446 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1447 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); 1448 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1449 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5); 1450 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1451 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b); 1452 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1453 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6); 1454 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1455 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); 1456 mutex_unlock(&spec->chipio_mutex); 1457 } 1458 1459 /* 1460 * CA0132 DSP IO stuffs 1461 */ 1462 static int dspio_send(struct hda_codec *codec, unsigned int reg, 1463 unsigned int data) 1464 { 1465 int res; 1466 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1467 1468 /* send bits of data specified by reg to dsp */ 1469 do { 1470 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data); 1471 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY)) 1472 return res; 1473 msleep(20); 1474 } while (time_before(jiffies, timeout)); 1475 1476 return -EIO; 1477 } 1478 1479 /* 1480 * Wait for DSP to be ready for commands 1481 */ 1482 static void dspio_write_wait(struct hda_codec *codec) 1483 { 1484 int status; 1485 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1486 1487 do { 1488 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1489 VENDOR_DSPIO_STATUS, 0); 1490 if ((status == VENDOR_STATUS_DSPIO_OK) || 1491 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)) 1492 break; 1493 msleep(1); 1494 } while (time_before(jiffies, timeout)); 1495 } 1496 1497 /* 1498 * Write SCP data to DSP 1499 */ 1500 static int dspio_write(struct hda_codec *codec, unsigned int scp_data) 1501 { 1502 struct ca0132_spec *spec = codec->spec; 1503 int status; 1504 1505 dspio_write_wait(codec); 1506 1507 mutex_lock(&spec->chipio_mutex); 1508 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW, 1509 scp_data & 0xffff); 1510 if (status < 0) 1511 goto error; 1512 1513 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH, 1514 scp_data >> 16); 1515 if (status < 0) 1516 goto error; 1517 1518 /* OK, now check if the write itself has executed*/ 1519 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1520 VENDOR_DSPIO_STATUS, 0); 1521 error: 1522 mutex_unlock(&spec->chipio_mutex); 1523 1524 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ? 1525 -EIO : 0; 1526 } 1527 1528 /* 1529 * Write multiple SCP data to DSP 1530 */ 1531 static int dspio_write_multiple(struct hda_codec *codec, 1532 unsigned int *buffer, unsigned int size) 1533 { 1534 int status = 0; 1535 unsigned int count; 1536 1537 if (buffer == NULL) 1538 return -EINVAL; 1539 1540 count = 0; 1541 while (count < size) { 1542 status = dspio_write(codec, *buffer++); 1543 if (status != 0) 1544 break; 1545 count++; 1546 } 1547 1548 return status; 1549 } 1550 1551 static int dspio_read(struct hda_codec *codec, unsigned int *data) 1552 { 1553 int status; 1554 1555 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0); 1556 if (status == -EIO) 1557 return status; 1558 1559 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0); 1560 if (status == -EIO || 1561 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY) 1562 return -EIO; 1563 1564 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1565 VENDOR_DSPIO_SCP_READ_DATA, 0); 1566 1567 return 0; 1568 } 1569 1570 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer, 1571 unsigned int *buf_size, unsigned int size_count) 1572 { 1573 int status = 0; 1574 unsigned int size = *buf_size; 1575 unsigned int count; 1576 unsigned int skip_count; 1577 unsigned int dummy; 1578 1579 if (buffer == NULL) 1580 return -1; 1581 1582 count = 0; 1583 while (count < size && count < size_count) { 1584 status = dspio_read(codec, buffer++); 1585 if (status != 0) 1586 break; 1587 count++; 1588 } 1589 1590 skip_count = count; 1591 if (status == 0) { 1592 while (skip_count < size) { 1593 status = dspio_read(codec, &dummy); 1594 if (status != 0) 1595 break; 1596 skip_count++; 1597 } 1598 } 1599 *buf_size = count; 1600 1601 return status; 1602 } 1603 1604 /* 1605 * Construct the SCP header using corresponding fields 1606 */ 1607 static inline unsigned int 1608 make_scp_header(unsigned int target_id, unsigned int source_id, 1609 unsigned int get_flag, unsigned int req, 1610 unsigned int device_flag, unsigned int resp_flag, 1611 unsigned int error_flag, unsigned int data_size) 1612 { 1613 unsigned int header = 0; 1614 1615 header = (data_size & 0x1f) << 27; 1616 header |= (error_flag & 0x01) << 26; 1617 header |= (resp_flag & 0x01) << 25; 1618 header |= (device_flag & 0x01) << 24; 1619 header |= (req & 0x7f) << 17; 1620 header |= (get_flag & 0x01) << 16; 1621 header |= (source_id & 0xff) << 8; 1622 header |= target_id & 0xff; 1623 1624 return header; 1625 } 1626 1627 /* 1628 * Extract corresponding fields from SCP header 1629 */ 1630 static inline void 1631 extract_scp_header(unsigned int header, 1632 unsigned int *target_id, unsigned int *source_id, 1633 unsigned int *get_flag, unsigned int *req, 1634 unsigned int *device_flag, unsigned int *resp_flag, 1635 unsigned int *error_flag, unsigned int *data_size) 1636 { 1637 if (data_size) 1638 *data_size = (header >> 27) & 0x1f; 1639 if (error_flag) 1640 *error_flag = (header >> 26) & 0x01; 1641 if (resp_flag) 1642 *resp_flag = (header >> 25) & 0x01; 1643 if (device_flag) 1644 *device_flag = (header >> 24) & 0x01; 1645 if (req) 1646 *req = (header >> 17) & 0x7f; 1647 if (get_flag) 1648 *get_flag = (header >> 16) & 0x01; 1649 if (source_id) 1650 *source_id = (header >> 8) & 0xff; 1651 if (target_id) 1652 *target_id = header & 0xff; 1653 } 1654 1655 #define SCP_MAX_DATA_WORDS (16) 1656 1657 /* Structure to contain any SCP message */ 1658 struct scp_msg { 1659 unsigned int hdr; 1660 unsigned int data[SCP_MAX_DATA_WORDS]; 1661 }; 1662 1663 static void dspio_clear_response_queue(struct hda_codec *codec) 1664 { 1665 unsigned int dummy = 0; 1666 int status = -1; 1667 1668 /* clear all from the response queue */ 1669 do { 1670 status = dspio_read(codec, &dummy); 1671 } while (status == 0); 1672 } 1673 1674 static int dspio_get_response_data(struct hda_codec *codec) 1675 { 1676 struct ca0132_spec *spec = codec->spec; 1677 unsigned int data = 0; 1678 unsigned int count; 1679 1680 if (dspio_read(codec, &data) < 0) 1681 return -EIO; 1682 1683 if ((data & 0x00ffffff) == spec->wait_scp_header) { 1684 spec->scp_resp_header = data; 1685 spec->scp_resp_count = data >> 27; 1686 count = spec->wait_num_data; 1687 dspio_read_multiple(codec, spec->scp_resp_data, 1688 &spec->scp_resp_count, count); 1689 return 0; 1690 } 1691 1692 return -EIO; 1693 } 1694 1695 /* 1696 * Send SCP message to DSP 1697 */ 1698 static int dspio_send_scp_message(struct hda_codec *codec, 1699 unsigned char *send_buf, 1700 unsigned int send_buf_size, 1701 unsigned char *return_buf, 1702 unsigned int return_buf_size, 1703 unsigned int *bytes_returned) 1704 { 1705 struct ca0132_spec *spec = codec->spec; 1706 int status = -1; 1707 unsigned int scp_send_size = 0; 1708 unsigned int total_size; 1709 bool waiting_for_resp = false; 1710 unsigned int header; 1711 struct scp_msg *ret_msg; 1712 unsigned int resp_src_id, resp_target_id; 1713 unsigned int data_size, src_id, target_id, get_flag, device_flag; 1714 1715 if (bytes_returned) 1716 *bytes_returned = 0; 1717 1718 /* get scp header from buffer */ 1719 header = *((unsigned int *)send_buf); 1720 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL, 1721 &device_flag, NULL, NULL, &data_size); 1722 scp_send_size = data_size + 1; 1723 total_size = (scp_send_size * 4); 1724 1725 if (send_buf_size < total_size) 1726 return -EINVAL; 1727 1728 if (get_flag || device_flag) { 1729 if (!return_buf || return_buf_size < 4 || !bytes_returned) 1730 return -EINVAL; 1731 1732 spec->wait_scp_header = *((unsigned int *)send_buf); 1733 1734 /* swap source id with target id */ 1735 resp_target_id = src_id; 1736 resp_src_id = target_id; 1737 spec->wait_scp_header &= 0xffff0000; 1738 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id); 1739 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1; 1740 spec->wait_scp = 1; 1741 waiting_for_resp = true; 1742 } 1743 1744 status = dspio_write_multiple(codec, (unsigned int *)send_buf, 1745 scp_send_size); 1746 if (status < 0) { 1747 spec->wait_scp = 0; 1748 return status; 1749 } 1750 1751 if (waiting_for_resp) { 1752 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1753 memset(return_buf, 0, return_buf_size); 1754 do { 1755 msleep(20); 1756 } while (spec->wait_scp && time_before(jiffies, timeout)); 1757 waiting_for_resp = false; 1758 if (!spec->wait_scp) { 1759 ret_msg = (struct scp_msg *)return_buf; 1760 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4); 1761 memcpy(&ret_msg->data, spec->scp_resp_data, 1762 spec->wait_num_data); 1763 *bytes_returned = (spec->scp_resp_count + 1) * 4; 1764 status = 0; 1765 } else { 1766 status = -EIO; 1767 } 1768 spec->wait_scp = 0; 1769 } 1770 1771 return status; 1772 } 1773 1774 /** 1775 * Prepare and send the SCP message to DSP 1776 * @codec: the HDA codec 1777 * @mod_id: ID of the DSP module to send the command 1778 * @req: ID of request to send to the DSP module 1779 * @dir: SET or GET 1780 * @data: pointer to the data to send with the request, request specific 1781 * @len: length of the data, in bytes 1782 * @reply: point to the buffer to hold data returned for a reply 1783 * @reply_len: length of the reply buffer returned from GET 1784 * 1785 * Returns zero or a negative error code. 1786 */ 1787 static int dspio_scp(struct hda_codec *codec, 1788 int mod_id, int src_id, int req, int dir, const void *data, 1789 unsigned int len, void *reply, unsigned int *reply_len) 1790 { 1791 int status = 0; 1792 struct scp_msg scp_send, scp_reply; 1793 unsigned int ret_bytes, send_size, ret_size; 1794 unsigned int send_get_flag, reply_resp_flag, reply_error_flag; 1795 unsigned int reply_data_size; 1796 1797 memset(&scp_send, 0, sizeof(scp_send)); 1798 memset(&scp_reply, 0, sizeof(scp_reply)); 1799 1800 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS)) 1801 return -EINVAL; 1802 1803 if (dir == SCP_GET && reply == NULL) { 1804 codec_dbg(codec, "dspio_scp get but has no buffer\n"); 1805 return -EINVAL; 1806 } 1807 1808 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) { 1809 codec_dbg(codec, "dspio_scp bad resp buf len parms\n"); 1810 return -EINVAL; 1811 } 1812 1813 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req, 1814 0, 0, 0, len/sizeof(unsigned int)); 1815 if (data != NULL && len > 0) { 1816 len = min((unsigned int)(sizeof(scp_send.data)), len); 1817 memcpy(scp_send.data, data, len); 1818 } 1819 1820 ret_bytes = 0; 1821 send_size = sizeof(unsigned int) + len; 1822 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send, 1823 send_size, (unsigned char *)&scp_reply, 1824 sizeof(scp_reply), &ret_bytes); 1825 1826 if (status < 0) { 1827 codec_dbg(codec, "dspio_scp: send scp msg failed\n"); 1828 return status; 1829 } 1830 1831 /* extract send and reply headers members */ 1832 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag, 1833 NULL, NULL, NULL, NULL, NULL); 1834 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL, 1835 &reply_resp_flag, &reply_error_flag, 1836 &reply_data_size); 1837 1838 if (!send_get_flag) 1839 return 0; 1840 1841 if (reply_resp_flag && !reply_error_flag) { 1842 ret_size = (ret_bytes - sizeof(scp_reply.hdr)) 1843 / sizeof(unsigned int); 1844 1845 if (*reply_len < ret_size*sizeof(unsigned int)) { 1846 codec_dbg(codec, "reply too long for buf\n"); 1847 return -EINVAL; 1848 } else if (ret_size != reply_data_size) { 1849 codec_dbg(codec, "RetLen and HdrLen .NE.\n"); 1850 return -EINVAL; 1851 } else if (!reply) { 1852 codec_dbg(codec, "NULL reply\n"); 1853 return -EINVAL; 1854 } else { 1855 *reply_len = ret_size*sizeof(unsigned int); 1856 memcpy(reply, scp_reply.data, *reply_len); 1857 } 1858 } else { 1859 codec_dbg(codec, "reply ill-formed or errflag set\n"); 1860 return -EIO; 1861 } 1862 1863 return status; 1864 } 1865 1866 /* 1867 * Set DSP parameters 1868 */ 1869 static int dspio_set_param(struct hda_codec *codec, int mod_id, 1870 int src_id, int req, const void *data, unsigned int len) 1871 { 1872 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL, 1873 NULL); 1874 } 1875 1876 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id, 1877 int req, const unsigned int data) 1878 { 1879 return dspio_set_param(codec, mod_id, 0x20, req, &data, 1880 sizeof(unsigned int)); 1881 } 1882 1883 static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id, 1884 int req, const unsigned int data) 1885 { 1886 return dspio_set_param(codec, mod_id, 0x00, req, &data, 1887 sizeof(unsigned int)); 1888 } 1889 1890 /* 1891 * Allocate a DSP DMA channel via an SCP message 1892 */ 1893 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan) 1894 { 1895 int status = 0; 1896 unsigned int size = sizeof(dma_chan); 1897 1898 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n"); 1899 status = dspio_scp(codec, MASTERCONTROL, 0x20, 1900 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0, 1901 dma_chan, &size); 1902 1903 if (status < 0) { 1904 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n"); 1905 return status; 1906 } 1907 1908 if ((*dma_chan + 1) == 0) { 1909 codec_dbg(codec, "no free dma channels to allocate\n"); 1910 return -EBUSY; 1911 } 1912 1913 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan); 1914 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n"); 1915 1916 return status; 1917 } 1918 1919 /* 1920 * Free a DSP DMA via an SCP message 1921 */ 1922 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan) 1923 { 1924 int status = 0; 1925 unsigned int dummy = 0; 1926 1927 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n"); 1928 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan); 1929 1930 status = dspio_scp(codec, MASTERCONTROL, 0x20, 1931 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan, 1932 sizeof(dma_chan), NULL, &dummy); 1933 1934 if (status < 0) { 1935 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n"); 1936 return status; 1937 } 1938 1939 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n"); 1940 1941 return status; 1942 } 1943 1944 /* 1945 * (Re)start the DSP 1946 */ 1947 static int dsp_set_run_state(struct hda_codec *codec) 1948 { 1949 unsigned int dbg_ctrl_reg; 1950 unsigned int halt_state; 1951 int err; 1952 1953 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg); 1954 if (err < 0) 1955 return err; 1956 1957 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >> 1958 DSP_DBGCNTL_STATE_LOBIT; 1959 1960 if (halt_state != 0) { 1961 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) & 1962 DSP_DBGCNTL_SS_MASK); 1963 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 1964 dbg_ctrl_reg); 1965 if (err < 0) 1966 return err; 1967 1968 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) & 1969 DSP_DBGCNTL_EXEC_MASK; 1970 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 1971 dbg_ctrl_reg); 1972 if (err < 0) 1973 return err; 1974 } 1975 1976 return 0; 1977 } 1978 1979 /* 1980 * Reset the DSP 1981 */ 1982 static int dsp_reset(struct hda_codec *codec) 1983 { 1984 unsigned int res; 1985 int retry = 20; 1986 1987 codec_dbg(codec, "dsp_reset\n"); 1988 do { 1989 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0); 1990 retry--; 1991 } while (res == -EIO && retry); 1992 1993 if (!retry) { 1994 codec_dbg(codec, "dsp_reset timeout\n"); 1995 return -EIO; 1996 } 1997 1998 return 0; 1999 } 2000 2001 /* 2002 * Convert chip address to DSP address 2003 */ 2004 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx, 2005 bool *code, bool *yram) 2006 { 2007 *code = *yram = false; 2008 2009 if (UC_RANGE(chip_addx, 1)) { 2010 *code = true; 2011 return UC_OFF(chip_addx); 2012 } else if (X_RANGE_ALL(chip_addx, 1)) { 2013 return X_OFF(chip_addx); 2014 } else if (Y_RANGE_ALL(chip_addx, 1)) { 2015 *yram = true; 2016 return Y_OFF(chip_addx); 2017 } 2018 2019 return INVALID_CHIP_ADDRESS; 2020 } 2021 2022 /* 2023 * Check if the DSP DMA is active 2024 */ 2025 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan) 2026 { 2027 unsigned int dma_chnlstart_reg; 2028 2029 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg); 2030 2031 return ((dma_chnlstart_reg & (1 << 2032 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0); 2033 } 2034 2035 static int dsp_dma_setup_common(struct hda_codec *codec, 2036 unsigned int chip_addx, 2037 unsigned int dma_chan, 2038 unsigned int port_map_mask, 2039 bool ovly) 2040 { 2041 int status = 0; 2042 unsigned int chnl_prop; 2043 unsigned int dsp_addx; 2044 unsigned int active; 2045 bool code, yram; 2046 2047 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n"); 2048 2049 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) { 2050 codec_dbg(codec, "dma chan num invalid\n"); 2051 return -EINVAL; 2052 } 2053 2054 if (dsp_is_dma_active(codec, dma_chan)) { 2055 codec_dbg(codec, "dma already active\n"); 2056 return -EBUSY; 2057 } 2058 2059 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2060 2061 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2062 codec_dbg(codec, "invalid chip addr\n"); 2063 return -ENXIO; 2064 } 2065 2066 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK; 2067 active = 0; 2068 2069 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n"); 2070 2071 if (ovly) { 2072 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET, 2073 &chnl_prop); 2074 2075 if (status < 0) { 2076 codec_dbg(codec, "read CHNLPROP Reg fail\n"); 2077 return status; 2078 } 2079 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n"); 2080 } 2081 2082 if (!code) 2083 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2084 else 2085 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2086 2087 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan)); 2088 2089 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop); 2090 if (status < 0) { 2091 codec_dbg(codec, "write CHNLPROP Reg fail\n"); 2092 return status; 2093 } 2094 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n"); 2095 2096 if (ovly) { 2097 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET, 2098 &active); 2099 2100 if (status < 0) { 2101 codec_dbg(codec, "read ACTIVE Reg fail\n"); 2102 return status; 2103 } 2104 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n"); 2105 } 2106 2107 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) & 2108 DSPDMAC_ACTIVE_AAR_MASK; 2109 2110 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active); 2111 if (status < 0) { 2112 codec_dbg(codec, "write ACTIVE Reg fail\n"); 2113 return status; 2114 } 2115 2116 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n"); 2117 2118 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan), 2119 port_map_mask); 2120 if (status < 0) { 2121 codec_dbg(codec, "write AUDCHSEL Reg fail\n"); 2122 return status; 2123 } 2124 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n"); 2125 2126 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan), 2127 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK); 2128 if (status < 0) { 2129 codec_dbg(codec, "write IRQCNT Reg fail\n"); 2130 return status; 2131 } 2132 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n"); 2133 2134 codec_dbg(codec, 2135 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, " 2136 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n", 2137 chip_addx, dsp_addx, dma_chan, 2138 port_map_mask, chnl_prop, active); 2139 2140 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n"); 2141 2142 return 0; 2143 } 2144 2145 /* 2146 * Setup the DSP DMA per-transfer-specific registers 2147 */ 2148 static int dsp_dma_setup(struct hda_codec *codec, 2149 unsigned int chip_addx, 2150 unsigned int count, 2151 unsigned int dma_chan) 2152 { 2153 int status = 0; 2154 bool code, yram; 2155 unsigned int dsp_addx; 2156 unsigned int addr_field; 2157 unsigned int incr_field; 2158 unsigned int base_cnt; 2159 unsigned int cur_cnt; 2160 unsigned int dma_cfg = 0; 2161 unsigned int adr_ofs = 0; 2162 unsigned int xfr_cnt = 0; 2163 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT - 2164 DSPDMAC_XFRCNT_BCNT_LOBIT + 1); 2165 2166 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n"); 2167 2168 if (count > max_dma_count) { 2169 codec_dbg(codec, "count too big\n"); 2170 return -EINVAL; 2171 } 2172 2173 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2174 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2175 codec_dbg(codec, "invalid chip addr\n"); 2176 return -ENXIO; 2177 } 2178 2179 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n"); 2180 2181 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT; 2182 incr_field = 0; 2183 2184 if (!code) { 2185 addr_field <<= 1; 2186 if (yram) 2187 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT); 2188 2189 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT); 2190 } 2191 2192 dma_cfg = addr_field + incr_field; 2193 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan), 2194 dma_cfg); 2195 if (status < 0) { 2196 codec_dbg(codec, "write DMACFG Reg fail\n"); 2197 return status; 2198 } 2199 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n"); 2200 2201 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT + 2202 (code ? 0 : 1)); 2203 2204 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan), 2205 adr_ofs); 2206 if (status < 0) { 2207 codec_dbg(codec, "write DSPADROFS Reg fail\n"); 2208 return status; 2209 } 2210 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n"); 2211 2212 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT; 2213 2214 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT; 2215 2216 xfr_cnt = base_cnt | cur_cnt; 2217 2218 status = chipio_write(codec, 2219 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt); 2220 if (status < 0) { 2221 codec_dbg(codec, "write XFRCNT Reg fail\n"); 2222 return status; 2223 } 2224 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n"); 2225 2226 codec_dbg(codec, 2227 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, " 2228 "ADROFS=0x%x, XFRCNT=0x%x\n", 2229 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt); 2230 2231 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n"); 2232 2233 return 0; 2234 } 2235 2236 /* 2237 * Start the DSP DMA 2238 */ 2239 static int dsp_dma_start(struct hda_codec *codec, 2240 unsigned int dma_chan, bool ovly) 2241 { 2242 unsigned int reg = 0; 2243 int status = 0; 2244 2245 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n"); 2246 2247 if (ovly) { 2248 status = chipio_read(codec, 2249 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2250 2251 if (status < 0) { 2252 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2253 return status; 2254 } 2255 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n"); 2256 2257 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2258 DSPDMAC_CHNLSTART_DIS_MASK); 2259 } 2260 2261 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2262 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT))); 2263 if (status < 0) { 2264 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2265 return status; 2266 } 2267 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n"); 2268 2269 return status; 2270 } 2271 2272 /* 2273 * Stop the DSP DMA 2274 */ 2275 static int dsp_dma_stop(struct hda_codec *codec, 2276 unsigned int dma_chan, bool ovly) 2277 { 2278 unsigned int reg = 0; 2279 int status = 0; 2280 2281 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n"); 2282 2283 if (ovly) { 2284 status = chipio_read(codec, 2285 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2286 2287 if (status < 0) { 2288 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2289 return status; 2290 } 2291 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n"); 2292 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2293 DSPDMAC_CHNLSTART_DIS_MASK); 2294 } 2295 2296 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2297 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT))); 2298 if (status < 0) { 2299 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2300 return status; 2301 } 2302 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n"); 2303 2304 return status; 2305 } 2306 2307 /** 2308 * Allocate router ports 2309 * 2310 * @codec: the HDA codec 2311 * @num_chans: number of channels in the stream 2312 * @ports_per_channel: number of ports per channel 2313 * @start_device: start device 2314 * @port_map: pointer to the port list to hold the allocated ports 2315 * 2316 * Returns zero or a negative error code. 2317 */ 2318 static int dsp_allocate_router_ports(struct hda_codec *codec, 2319 unsigned int num_chans, 2320 unsigned int ports_per_channel, 2321 unsigned int start_device, 2322 unsigned int *port_map) 2323 { 2324 int status = 0; 2325 int res; 2326 u8 val; 2327 2328 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2329 if (status < 0) 2330 return status; 2331 2332 val = start_device << 6; 2333 val |= (ports_per_channel - 1) << 4; 2334 val |= num_chans - 1; 2335 2336 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2337 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET, 2338 val); 2339 2340 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2341 VENDOR_CHIPIO_PORT_ALLOC_SET, 2342 MEM_CONNID_DSP); 2343 2344 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2345 if (status < 0) 2346 return status; 2347 2348 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 2349 VENDOR_CHIPIO_PORT_ALLOC_GET, 0); 2350 2351 *port_map = res; 2352 2353 return (res < 0) ? res : 0; 2354 } 2355 2356 /* 2357 * Free router ports 2358 */ 2359 static int dsp_free_router_ports(struct hda_codec *codec) 2360 { 2361 int status = 0; 2362 2363 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2364 if (status < 0) 2365 return status; 2366 2367 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2368 VENDOR_CHIPIO_PORT_FREE_SET, 2369 MEM_CONNID_DSP); 2370 2371 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2372 2373 return status; 2374 } 2375 2376 /* 2377 * Allocate DSP ports for the download stream 2378 */ 2379 static int dsp_allocate_ports(struct hda_codec *codec, 2380 unsigned int num_chans, 2381 unsigned int rate_multi, unsigned int *port_map) 2382 { 2383 int status; 2384 2385 codec_dbg(codec, " dsp_allocate_ports() -- begin\n"); 2386 2387 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2388 codec_dbg(codec, "bad rate multiple\n"); 2389 return -EINVAL; 2390 } 2391 2392 status = dsp_allocate_router_ports(codec, num_chans, 2393 rate_multi, 0, port_map); 2394 2395 codec_dbg(codec, " dsp_allocate_ports() -- complete\n"); 2396 2397 return status; 2398 } 2399 2400 static int dsp_allocate_ports_format(struct hda_codec *codec, 2401 const unsigned short fmt, 2402 unsigned int *port_map) 2403 { 2404 int status; 2405 unsigned int num_chans; 2406 2407 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1; 2408 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1; 2409 unsigned int rate_multi = sample_rate_mul / sample_rate_div; 2410 2411 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2412 codec_dbg(codec, "bad rate multiple\n"); 2413 return -EINVAL; 2414 } 2415 2416 num_chans = get_hdafmt_chs(fmt) + 1; 2417 2418 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map); 2419 2420 return status; 2421 } 2422 2423 /* 2424 * free DSP ports 2425 */ 2426 static int dsp_free_ports(struct hda_codec *codec) 2427 { 2428 int status; 2429 2430 codec_dbg(codec, " dsp_free_ports() -- begin\n"); 2431 2432 status = dsp_free_router_ports(codec); 2433 if (status < 0) { 2434 codec_dbg(codec, "free router ports fail\n"); 2435 return status; 2436 } 2437 codec_dbg(codec, " dsp_free_ports() -- complete\n"); 2438 2439 return status; 2440 } 2441 2442 /* 2443 * HDA DMA engine stuffs for DSP code download 2444 */ 2445 struct dma_engine { 2446 struct hda_codec *codec; 2447 unsigned short m_converter_format; 2448 struct snd_dma_buffer *dmab; 2449 unsigned int buf_size; 2450 }; 2451 2452 2453 enum dma_state { 2454 DMA_STATE_STOP = 0, 2455 DMA_STATE_RUN = 1 2456 }; 2457 2458 static int dma_convert_to_hda_format(struct hda_codec *codec, 2459 unsigned int sample_rate, 2460 unsigned short channels, 2461 unsigned short *hda_format) 2462 { 2463 unsigned int format_val; 2464 2465 format_val = snd_hdac_calc_stream_format(sample_rate, 2466 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0); 2467 2468 if (hda_format) 2469 *hda_format = (unsigned short)format_val; 2470 2471 return 0; 2472 } 2473 2474 /* 2475 * Reset DMA for DSP download 2476 */ 2477 static int dma_reset(struct dma_engine *dma) 2478 { 2479 struct hda_codec *codec = dma->codec; 2480 struct ca0132_spec *spec = codec->spec; 2481 int status; 2482 2483 if (dma->dmab->area) 2484 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab); 2485 2486 status = snd_hda_codec_load_dsp_prepare(codec, 2487 dma->m_converter_format, 2488 dma->buf_size, 2489 dma->dmab); 2490 if (status < 0) 2491 return status; 2492 spec->dsp_stream_id = status; 2493 return 0; 2494 } 2495 2496 static int dma_set_state(struct dma_engine *dma, enum dma_state state) 2497 { 2498 bool cmd; 2499 2500 switch (state) { 2501 case DMA_STATE_STOP: 2502 cmd = false; 2503 break; 2504 case DMA_STATE_RUN: 2505 cmd = true; 2506 break; 2507 default: 2508 return 0; 2509 } 2510 2511 snd_hda_codec_load_dsp_trigger(dma->codec, cmd); 2512 return 0; 2513 } 2514 2515 static unsigned int dma_get_buffer_size(struct dma_engine *dma) 2516 { 2517 return dma->dmab->bytes; 2518 } 2519 2520 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma) 2521 { 2522 return dma->dmab->area; 2523 } 2524 2525 static int dma_xfer(struct dma_engine *dma, 2526 const unsigned int *data, 2527 unsigned int count) 2528 { 2529 memcpy(dma->dmab->area, data, count); 2530 return 0; 2531 } 2532 2533 static void dma_get_converter_format( 2534 struct dma_engine *dma, 2535 unsigned short *format) 2536 { 2537 if (format) 2538 *format = dma->m_converter_format; 2539 } 2540 2541 static unsigned int dma_get_stream_id(struct dma_engine *dma) 2542 { 2543 struct ca0132_spec *spec = dma->codec->spec; 2544 2545 return spec->dsp_stream_id; 2546 } 2547 2548 struct dsp_image_seg { 2549 u32 magic; 2550 u32 chip_addr; 2551 u32 count; 2552 u32 data[0]; 2553 }; 2554 2555 static const u32 g_magic_value = 0x4c46584d; 2556 static const u32 g_chip_addr_magic_value = 0xFFFFFF01; 2557 2558 static bool is_valid(const struct dsp_image_seg *p) 2559 { 2560 return p->magic == g_magic_value; 2561 } 2562 2563 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p) 2564 { 2565 return g_chip_addr_magic_value == p->chip_addr; 2566 } 2567 2568 static bool is_last(const struct dsp_image_seg *p) 2569 { 2570 return p->count == 0; 2571 } 2572 2573 static size_t dsp_sizeof(const struct dsp_image_seg *p) 2574 { 2575 return sizeof(*p) + p->count*sizeof(u32); 2576 } 2577 2578 static const struct dsp_image_seg *get_next_seg_ptr( 2579 const struct dsp_image_seg *p) 2580 { 2581 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p)); 2582 } 2583 2584 /* 2585 * CA0132 chip DSP transfer stuffs. For DSP download. 2586 */ 2587 #define INVALID_DMA_CHANNEL (~0U) 2588 2589 /* 2590 * Program a list of address/data pairs via the ChipIO widget. 2591 * The segment data is in the format of successive pairs of words. 2592 * These are repeated as indicated by the segment's count field. 2593 */ 2594 static int dspxfr_hci_write(struct hda_codec *codec, 2595 const struct dsp_image_seg *fls) 2596 { 2597 int status; 2598 const u32 *data; 2599 unsigned int count; 2600 2601 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) { 2602 codec_dbg(codec, "hci_write invalid params\n"); 2603 return -EINVAL; 2604 } 2605 2606 count = fls->count; 2607 data = (u32 *)(fls->data); 2608 while (count >= 2) { 2609 status = chipio_write(codec, data[0], data[1]); 2610 if (status < 0) { 2611 codec_dbg(codec, "hci_write chipio failed\n"); 2612 return status; 2613 } 2614 count -= 2; 2615 data += 2; 2616 } 2617 return 0; 2618 } 2619 2620 /** 2621 * Write a block of data into DSP code or data RAM using pre-allocated 2622 * DMA engine. 2623 * 2624 * @codec: the HDA codec 2625 * @fls: pointer to a fast load image 2626 * @reloc: Relocation address for loading single-segment overlays, or 0 for 2627 * no relocation 2628 * @dma_engine: pointer to DMA engine to be used for DSP download 2629 * @dma_chan: The number of DMA channels used for DSP download 2630 * @port_map_mask: port mapping 2631 * @ovly: TRUE if overlay format is required 2632 * 2633 * Returns zero or a negative error code. 2634 */ 2635 static int dspxfr_one_seg(struct hda_codec *codec, 2636 const struct dsp_image_seg *fls, 2637 unsigned int reloc, 2638 struct dma_engine *dma_engine, 2639 unsigned int dma_chan, 2640 unsigned int port_map_mask, 2641 bool ovly) 2642 { 2643 int status = 0; 2644 bool comm_dma_setup_done = false; 2645 const unsigned int *data; 2646 unsigned int chip_addx; 2647 unsigned int words_to_write; 2648 unsigned int buffer_size_words; 2649 unsigned char *buffer_addx; 2650 unsigned short hda_format; 2651 unsigned int sample_rate_div; 2652 unsigned int sample_rate_mul; 2653 unsigned int num_chans; 2654 unsigned int hda_frame_size_words; 2655 unsigned int remainder_words; 2656 const u32 *data_remainder; 2657 u32 chip_addx_remainder; 2658 unsigned int run_size_words; 2659 const struct dsp_image_seg *hci_write = NULL; 2660 unsigned long timeout; 2661 bool dma_active; 2662 2663 if (fls == NULL) 2664 return -EINVAL; 2665 if (is_hci_prog_list_seg(fls)) { 2666 hci_write = fls; 2667 fls = get_next_seg_ptr(fls); 2668 } 2669 2670 if (hci_write && (!fls || is_last(fls))) { 2671 codec_dbg(codec, "hci_write\n"); 2672 return dspxfr_hci_write(codec, hci_write); 2673 } 2674 2675 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) { 2676 codec_dbg(codec, "Invalid Params\n"); 2677 return -EINVAL; 2678 } 2679 2680 data = fls->data; 2681 chip_addx = fls->chip_addr, 2682 words_to_write = fls->count; 2683 2684 if (!words_to_write) 2685 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0; 2686 if (reloc) 2687 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2); 2688 2689 if (!UC_RANGE(chip_addx, words_to_write) && 2690 !X_RANGE_ALL(chip_addx, words_to_write) && 2691 !Y_RANGE_ALL(chip_addx, words_to_write)) { 2692 codec_dbg(codec, "Invalid chip_addx Params\n"); 2693 return -EINVAL; 2694 } 2695 2696 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) / 2697 sizeof(u32); 2698 2699 buffer_addx = dma_get_buffer_addr(dma_engine); 2700 2701 if (buffer_addx == NULL) { 2702 codec_dbg(codec, "dma_engine buffer NULL\n"); 2703 return -EINVAL; 2704 } 2705 2706 dma_get_converter_format(dma_engine, &hda_format); 2707 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1; 2708 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1; 2709 num_chans = get_hdafmt_chs(hda_format) + 1; 2710 2711 hda_frame_size_words = ((sample_rate_div == 0) ? 0 : 2712 (num_chans * sample_rate_mul / sample_rate_div)); 2713 2714 if (hda_frame_size_words == 0) { 2715 codec_dbg(codec, "frmsz zero\n"); 2716 return -EINVAL; 2717 } 2718 2719 buffer_size_words = min(buffer_size_words, 2720 (unsigned int)(UC_RANGE(chip_addx, 1) ? 2721 65536 : 32768)); 2722 buffer_size_words -= buffer_size_words % hda_frame_size_words; 2723 codec_dbg(codec, 2724 "chpadr=0x%08x frmsz=%u nchan=%u " 2725 "rate_mul=%u div=%u bufsz=%u\n", 2726 chip_addx, hda_frame_size_words, num_chans, 2727 sample_rate_mul, sample_rate_div, buffer_size_words); 2728 2729 if (buffer_size_words < hda_frame_size_words) { 2730 codec_dbg(codec, "dspxfr_one_seg:failed\n"); 2731 return -EINVAL; 2732 } 2733 2734 remainder_words = words_to_write % hda_frame_size_words; 2735 data_remainder = data; 2736 chip_addx_remainder = chip_addx; 2737 2738 data += remainder_words; 2739 chip_addx += remainder_words*sizeof(u32); 2740 words_to_write -= remainder_words; 2741 2742 while (words_to_write != 0) { 2743 run_size_words = min(buffer_size_words, words_to_write); 2744 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n", 2745 words_to_write, run_size_words, remainder_words); 2746 dma_xfer(dma_engine, data, run_size_words*sizeof(u32)); 2747 if (!comm_dma_setup_done) { 2748 status = dsp_dma_stop(codec, dma_chan, ovly); 2749 if (status < 0) 2750 return status; 2751 status = dsp_dma_setup_common(codec, chip_addx, 2752 dma_chan, port_map_mask, ovly); 2753 if (status < 0) 2754 return status; 2755 comm_dma_setup_done = true; 2756 } 2757 2758 status = dsp_dma_setup(codec, chip_addx, 2759 run_size_words, dma_chan); 2760 if (status < 0) 2761 return status; 2762 status = dsp_dma_start(codec, dma_chan, ovly); 2763 if (status < 0) 2764 return status; 2765 if (!dsp_is_dma_active(codec, dma_chan)) { 2766 codec_dbg(codec, "dspxfr:DMA did not start\n"); 2767 return -EIO; 2768 } 2769 status = dma_set_state(dma_engine, DMA_STATE_RUN); 2770 if (status < 0) 2771 return status; 2772 if (remainder_words != 0) { 2773 status = chipio_write_multiple(codec, 2774 chip_addx_remainder, 2775 data_remainder, 2776 remainder_words); 2777 if (status < 0) 2778 return status; 2779 remainder_words = 0; 2780 } 2781 if (hci_write) { 2782 status = dspxfr_hci_write(codec, hci_write); 2783 if (status < 0) 2784 return status; 2785 hci_write = NULL; 2786 } 2787 2788 timeout = jiffies + msecs_to_jiffies(2000); 2789 do { 2790 dma_active = dsp_is_dma_active(codec, dma_chan); 2791 if (!dma_active) 2792 break; 2793 msleep(20); 2794 } while (time_before(jiffies, timeout)); 2795 if (dma_active) 2796 break; 2797 2798 codec_dbg(codec, "+++++ DMA complete\n"); 2799 dma_set_state(dma_engine, DMA_STATE_STOP); 2800 status = dma_reset(dma_engine); 2801 2802 if (status < 0) 2803 return status; 2804 2805 data += run_size_words; 2806 chip_addx += run_size_words*sizeof(u32); 2807 words_to_write -= run_size_words; 2808 } 2809 2810 if (remainder_words != 0) { 2811 status = chipio_write_multiple(codec, chip_addx_remainder, 2812 data_remainder, remainder_words); 2813 } 2814 2815 return status; 2816 } 2817 2818 /** 2819 * Write the entire DSP image of a DSP code/data overlay to DSP memories 2820 * 2821 * @codec: the HDA codec 2822 * @fls_data: pointer to a fast load image 2823 * @reloc: Relocation address for loading single-segment overlays, or 0 for 2824 * no relocation 2825 * @sample_rate: sampling rate of the stream used for DSP download 2826 * @channels: channels of the stream used for DSP download 2827 * @ovly: TRUE if overlay format is required 2828 * 2829 * Returns zero or a negative error code. 2830 */ 2831 static int dspxfr_image(struct hda_codec *codec, 2832 const struct dsp_image_seg *fls_data, 2833 unsigned int reloc, 2834 unsigned int sample_rate, 2835 unsigned short channels, 2836 bool ovly) 2837 { 2838 struct ca0132_spec *spec = codec->spec; 2839 int status; 2840 unsigned short hda_format = 0; 2841 unsigned int response; 2842 unsigned char stream_id = 0; 2843 struct dma_engine *dma_engine; 2844 unsigned int dma_chan; 2845 unsigned int port_map_mask; 2846 2847 if (fls_data == NULL) 2848 return -EINVAL; 2849 2850 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL); 2851 if (!dma_engine) 2852 return -ENOMEM; 2853 2854 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL); 2855 if (!dma_engine->dmab) { 2856 kfree(dma_engine); 2857 return -ENOMEM; 2858 } 2859 2860 dma_engine->codec = codec; 2861 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format); 2862 dma_engine->m_converter_format = hda_format; 2863 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY : 2864 DSP_DMA_WRITE_BUFLEN_INIT) * 2; 2865 2866 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0; 2867 2868 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL, 2869 hda_format, &response); 2870 2871 if (status < 0) { 2872 codec_dbg(codec, "set converter format fail\n"); 2873 goto exit; 2874 } 2875 2876 status = snd_hda_codec_load_dsp_prepare(codec, 2877 dma_engine->m_converter_format, 2878 dma_engine->buf_size, 2879 dma_engine->dmab); 2880 if (status < 0) 2881 goto exit; 2882 spec->dsp_stream_id = status; 2883 2884 if (ovly) { 2885 status = dspio_alloc_dma_chan(codec, &dma_chan); 2886 if (status < 0) { 2887 codec_dbg(codec, "alloc dmachan fail\n"); 2888 dma_chan = INVALID_DMA_CHANNEL; 2889 goto exit; 2890 } 2891 } 2892 2893 port_map_mask = 0; 2894 status = dsp_allocate_ports_format(codec, hda_format, 2895 &port_map_mask); 2896 if (status < 0) { 2897 codec_dbg(codec, "alloc ports fail\n"); 2898 goto exit; 2899 } 2900 2901 stream_id = dma_get_stream_id(dma_engine); 2902 status = codec_set_converter_stream_channel(codec, 2903 WIDGET_CHIP_CTRL, stream_id, 0, &response); 2904 if (status < 0) { 2905 codec_dbg(codec, "set stream chan fail\n"); 2906 goto exit; 2907 } 2908 2909 while ((fls_data != NULL) && !is_last(fls_data)) { 2910 if (!is_valid(fls_data)) { 2911 codec_dbg(codec, "FLS check fail\n"); 2912 status = -EINVAL; 2913 goto exit; 2914 } 2915 status = dspxfr_one_seg(codec, fls_data, reloc, 2916 dma_engine, dma_chan, 2917 port_map_mask, ovly); 2918 if (status < 0) 2919 break; 2920 2921 if (is_hci_prog_list_seg(fls_data)) 2922 fls_data = get_next_seg_ptr(fls_data); 2923 2924 if ((fls_data != NULL) && !is_last(fls_data)) 2925 fls_data = get_next_seg_ptr(fls_data); 2926 } 2927 2928 if (port_map_mask != 0) 2929 status = dsp_free_ports(codec); 2930 2931 if (status < 0) 2932 goto exit; 2933 2934 status = codec_set_converter_stream_channel(codec, 2935 WIDGET_CHIP_CTRL, 0, 0, &response); 2936 2937 exit: 2938 if (ovly && (dma_chan != INVALID_DMA_CHANNEL)) 2939 dspio_free_dma_chan(codec, dma_chan); 2940 2941 if (dma_engine->dmab->area) 2942 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab); 2943 kfree(dma_engine->dmab); 2944 kfree(dma_engine); 2945 2946 return status; 2947 } 2948 2949 /* 2950 * CA0132 DSP download stuffs. 2951 */ 2952 static void dspload_post_setup(struct hda_codec *codec) 2953 { 2954 struct ca0132_spec *spec = codec->spec; 2955 codec_dbg(codec, "---- dspload_post_setup ------\n"); 2956 if (!spec->use_alt_functions) { 2957 /*set DSP speaker to 2.0 configuration*/ 2958 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080); 2959 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000); 2960 2961 /*update write pointer*/ 2962 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002); 2963 } 2964 } 2965 2966 /** 2967 * dspload_image - Download DSP from a DSP Image Fast Load structure. 2968 * 2969 * @codec: the HDA codec 2970 * @fls: pointer to a fast load image 2971 * @ovly: TRUE if overlay format is required 2972 * @reloc: Relocation address for loading single-segment overlays, or 0 for 2973 * no relocation 2974 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE 2975 * @router_chans: number of audio router channels to be allocated (0 means use 2976 * internal defaults; max is 32) 2977 * 2978 * Download DSP from a DSP Image Fast Load structure. This structure is a 2979 * linear, non-constant sized element array of structures, each of which 2980 * contain the count of the data to be loaded, the data itself, and the 2981 * corresponding starting chip address of the starting data location. 2982 * Returns zero or a negative error code. 2983 */ 2984 static int dspload_image(struct hda_codec *codec, 2985 const struct dsp_image_seg *fls, 2986 bool ovly, 2987 unsigned int reloc, 2988 bool autostart, 2989 int router_chans) 2990 { 2991 int status = 0; 2992 unsigned int sample_rate; 2993 unsigned short channels; 2994 2995 codec_dbg(codec, "---- dspload_image begin ------\n"); 2996 if (router_chans == 0) { 2997 if (!ovly) 2998 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS; 2999 else 3000 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS; 3001 } 3002 3003 sample_rate = 48000; 3004 channels = (unsigned short)router_chans; 3005 3006 while (channels > 16) { 3007 sample_rate *= 2; 3008 channels /= 2; 3009 } 3010 3011 do { 3012 codec_dbg(codec, "Ready to program DMA\n"); 3013 if (!ovly) 3014 status = dsp_reset(codec); 3015 3016 if (status < 0) 3017 break; 3018 3019 codec_dbg(codec, "dsp_reset() complete\n"); 3020 status = dspxfr_image(codec, fls, reloc, sample_rate, channels, 3021 ovly); 3022 3023 if (status < 0) 3024 break; 3025 3026 codec_dbg(codec, "dspxfr_image() complete\n"); 3027 if (autostart && !ovly) { 3028 dspload_post_setup(codec); 3029 status = dsp_set_run_state(codec); 3030 } 3031 3032 codec_dbg(codec, "LOAD FINISHED\n"); 3033 } while (0); 3034 3035 return status; 3036 } 3037 3038 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 3039 static bool dspload_is_loaded(struct hda_codec *codec) 3040 { 3041 unsigned int data = 0; 3042 int status = 0; 3043 3044 status = chipio_read(codec, 0x40004, &data); 3045 if ((status < 0) || (data != 1)) 3046 return false; 3047 3048 return true; 3049 } 3050 #else 3051 #define dspload_is_loaded(codec) false 3052 #endif 3053 3054 static bool dspload_wait_loaded(struct hda_codec *codec) 3055 { 3056 unsigned long timeout = jiffies + msecs_to_jiffies(2000); 3057 3058 do { 3059 if (dspload_is_loaded(codec)) { 3060 codec_info(codec, "ca0132 DSP downloaded and running\n"); 3061 return true; 3062 } 3063 msleep(20); 3064 } while (time_before(jiffies, timeout)); 3065 3066 codec_err(codec, "ca0132 failed to download DSP\n"); 3067 return false; 3068 } 3069 3070 /* 3071 * Setup GPIO for the other variants of Core3D. 3072 */ 3073 3074 /* 3075 * Sets up the GPIO pins so that they are discoverable. If this isn't done, 3076 * the card shows as having no GPIO pins. 3077 */ 3078 static void ca0132_gpio_init(struct hda_codec *codec) 3079 { 3080 struct ca0132_spec *spec = codec->spec; 3081 3082 switch (spec->quirk) { 3083 case QUIRK_SBZ: 3084 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3085 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 3086 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23); 3087 break; 3088 case QUIRK_R3DI: 3089 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3090 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B); 3091 break; 3092 } 3093 3094 } 3095 3096 /* Sets the GPIO for audio output. */ 3097 static void ca0132_gpio_setup(struct hda_codec *codec) 3098 { 3099 struct ca0132_spec *spec = codec->spec; 3100 3101 switch (spec->quirk) { 3102 case QUIRK_SBZ: 3103 snd_hda_codec_write(codec, 0x01, 0, 3104 AC_VERB_SET_GPIO_DIRECTION, 0x07); 3105 snd_hda_codec_write(codec, 0x01, 0, 3106 AC_VERB_SET_GPIO_MASK, 0x07); 3107 snd_hda_codec_write(codec, 0x01, 0, 3108 AC_VERB_SET_GPIO_DATA, 0x04); 3109 snd_hda_codec_write(codec, 0x01, 0, 3110 AC_VERB_SET_GPIO_DATA, 0x06); 3111 break; 3112 case QUIRK_R3DI: 3113 snd_hda_codec_write(codec, 0x01, 0, 3114 AC_VERB_SET_GPIO_DIRECTION, 0x1E); 3115 snd_hda_codec_write(codec, 0x01, 0, 3116 AC_VERB_SET_GPIO_MASK, 0x1F); 3117 snd_hda_codec_write(codec, 0x01, 0, 3118 AC_VERB_SET_GPIO_DATA, 0x0C); 3119 break; 3120 } 3121 } 3122 3123 /* 3124 * GPIO control functions for the Recon3D integrated. 3125 */ 3126 3127 enum r3di_gpio_bit { 3128 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */ 3129 R3DI_MIC_SELECT_BIT = 1, 3130 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */ 3131 R3DI_OUT_SELECT_BIT = 2, 3132 /* 3133 * I dunno what this actually does, but it stays on until the dsp 3134 * is downloaded. 3135 */ 3136 R3DI_GPIO_DSP_DOWNLOADING = 3, 3137 /* 3138 * Same as above, no clue what it does, but it comes on after the dsp 3139 * is downloaded. 3140 */ 3141 R3DI_GPIO_DSP_DOWNLOADED = 4 3142 }; 3143 3144 enum r3di_mic_select { 3145 /* Set GPIO bit 1 to 0 for rear mic */ 3146 R3DI_REAR_MIC = 0, 3147 /* Set GPIO bit 1 to 1 for front microphone*/ 3148 R3DI_FRONT_MIC = 1 3149 }; 3150 3151 enum r3di_out_select { 3152 /* Set GPIO bit 2 to 0 for headphone */ 3153 R3DI_HEADPHONE_OUT = 0, 3154 /* Set GPIO bit 2 to 1 for speaker */ 3155 R3DI_LINE_OUT = 1 3156 }; 3157 enum r3di_dsp_status { 3158 /* Set GPIO bit 3 to 1 until DSP is downloaded */ 3159 R3DI_DSP_DOWNLOADING = 0, 3160 /* Set GPIO bit 4 to 1 once DSP is downloaded */ 3161 R3DI_DSP_DOWNLOADED = 1 3162 }; 3163 3164 3165 static void r3di_gpio_mic_set(struct hda_codec *codec, 3166 enum r3di_mic_select cur_mic) 3167 { 3168 unsigned int cur_gpio; 3169 3170 /* Get the current GPIO Data setup */ 3171 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3172 3173 switch (cur_mic) { 3174 case R3DI_REAR_MIC: 3175 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT); 3176 break; 3177 case R3DI_FRONT_MIC: 3178 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT); 3179 break; 3180 } 3181 snd_hda_codec_write(codec, codec->core.afg, 0, 3182 AC_VERB_SET_GPIO_DATA, cur_gpio); 3183 } 3184 3185 static void r3di_gpio_out_set(struct hda_codec *codec, 3186 enum r3di_out_select cur_out) 3187 { 3188 unsigned int cur_gpio; 3189 3190 /* Get the current GPIO Data setup */ 3191 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3192 3193 switch (cur_out) { 3194 case R3DI_HEADPHONE_OUT: 3195 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT); 3196 break; 3197 case R3DI_LINE_OUT: 3198 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT); 3199 break; 3200 } 3201 snd_hda_codec_write(codec, codec->core.afg, 0, 3202 AC_VERB_SET_GPIO_DATA, cur_gpio); 3203 } 3204 3205 static void r3di_gpio_dsp_status_set(struct hda_codec *codec, 3206 enum r3di_dsp_status dsp_status) 3207 { 3208 unsigned int cur_gpio; 3209 3210 /* Get the current GPIO Data setup */ 3211 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3212 3213 switch (dsp_status) { 3214 case R3DI_DSP_DOWNLOADING: 3215 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING); 3216 snd_hda_codec_write(codec, codec->core.afg, 0, 3217 AC_VERB_SET_GPIO_DATA, cur_gpio); 3218 break; 3219 case R3DI_DSP_DOWNLOADED: 3220 /* Set DOWNLOADING bit to 0. */ 3221 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING); 3222 3223 snd_hda_codec_write(codec, codec->core.afg, 0, 3224 AC_VERB_SET_GPIO_DATA, cur_gpio); 3225 3226 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED); 3227 break; 3228 } 3229 3230 snd_hda_codec_write(codec, codec->core.afg, 0, 3231 AC_VERB_SET_GPIO_DATA, cur_gpio); 3232 } 3233 3234 /* 3235 * PCM callbacks 3236 */ 3237 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3238 struct hda_codec *codec, 3239 unsigned int stream_tag, 3240 unsigned int format, 3241 struct snd_pcm_substream *substream) 3242 { 3243 struct ca0132_spec *spec = codec->spec; 3244 3245 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format); 3246 3247 return 0; 3248 } 3249 3250 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3251 struct hda_codec *codec, 3252 struct snd_pcm_substream *substream) 3253 { 3254 struct ca0132_spec *spec = codec->spec; 3255 3256 if (spec->dsp_state == DSP_DOWNLOADING) 3257 return 0; 3258 3259 /*If Playback effects are on, allow stream some time to flush 3260 *effects tail*/ 3261 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 3262 msleep(50); 3263 3264 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 3265 3266 return 0; 3267 } 3268 3269 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info, 3270 struct hda_codec *codec, 3271 struct snd_pcm_substream *substream) 3272 { 3273 struct ca0132_spec *spec = codec->spec; 3274 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY; 3275 struct snd_pcm_runtime *runtime = substream->runtime; 3276 3277 if (spec->dsp_state != DSP_DOWNLOADED) 3278 return 0; 3279 3280 /* Add latency if playback enhancement and either effect is enabled. */ 3281 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) { 3282 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) || 3283 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID])) 3284 latency += DSP_PLAY_ENHANCEMENT_LATENCY; 3285 } 3286 3287 /* Applying Speaker EQ adds latency as well. */ 3288 if (spec->cur_out_type == SPEAKER_OUT) 3289 latency += DSP_SPEAKER_OUT_LATENCY; 3290 3291 return (latency * runtime->rate) / 1000; 3292 } 3293 3294 /* 3295 * Digital out 3296 */ 3297 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo, 3298 struct hda_codec *codec, 3299 struct snd_pcm_substream *substream) 3300 { 3301 struct ca0132_spec *spec = codec->spec; 3302 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3303 } 3304 3305 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3306 struct hda_codec *codec, 3307 unsigned int stream_tag, 3308 unsigned int format, 3309 struct snd_pcm_substream *substream) 3310 { 3311 struct ca0132_spec *spec = codec->spec; 3312 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3313 stream_tag, format, substream); 3314 } 3315 3316 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3317 struct hda_codec *codec, 3318 struct snd_pcm_substream *substream) 3319 { 3320 struct ca0132_spec *spec = codec->spec; 3321 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout); 3322 } 3323 3324 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo, 3325 struct hda_codec *codec, 3326 struct snd_pcm_substream *substream) 3327 { 3328 struct ca0132_spec *spec = codec->spec; 3329 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3330 } 3331 3332 /* 3333 * Analog capture 3334 */ 3335 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo, 3336 struct hda_codec *codec, 3337 unsigned int stream_tag, 3338 unsigned int format, 3339 struct snd_pcm_substream *substream) 3340 { 3341 snd_hda_codec_setup_stream(codec, hinfo->nid, 3342 stream_tag, 0, format); 3343 3344 return 0; 3345 } 3346 3347 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo, 3348 struct hda_codec *codec, 3349 struct snd_pcm_substream *substream) 3350 { 3351 struct ca0132_spec *spec = codec->spec; 3352 3353 if (spec->dsp_state == DSP_DOWNLOADING) 3354 return 0; 3355 3356 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 3357 return 0; 3358 } 3359 3360 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info, 3361 struct hda_codec *codec, 3362 struct snd_pcm_substream *substream) 3363 { 3364 struct ca0132_spec *spec = codec->spec; 3365 unsigned int latency = DSP_CAPTURE_INIT_LATENCY; 3366 struct snd_pcm_runtime *runtime = substream->runtime; 3367 3368 if (spec->dsp_state != DSP_DOWNLOADED) 3369 return 0; 3370 3371 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 3372 latency += DSP_CRYSTAL_VOICE_LATENCY; 3373 3374 return (latency * runtime->rate) / 1000; 3375 } 3376 3377 /* 3378 * Controls stuffs. 3379 */ 3380 3381 /* 3382 * Mixer controls helpers. 3383 */ 3384 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \ 3385 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3386 .name = xname, \ 3387 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3388 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3389 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 3390 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 3391 .info = ca0132_volume_info, \ 3392 .get = ca0132_volume_get, \ 3393 .put = ca0132_volume_put, \ 3394 .tlv = { .c = ca0132_volume_tlv }, \ 3395 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3396 3397 /* 3398 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the 3399 * volume put, which is used for setting the DSP volume. This was done because 3400 * the ca0132 functions were taking too much time and causing lag. 3401 */ 3402 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \ 3403 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3404 .name = xname, \ 3405 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3406 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3407 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 3408 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 3409 .info = snd_hda_mixer_amp_volume_info, \ 3410 .get = snd_hda_mixer_amp_volume_get, \ 3411 .put = ca0132_alt_volume_put, \ 3412 .tlv = { .c = snd_hda_mixer_amp_tlv }, \ 3413 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3414 3415 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \ 3416 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3417 .name = xname, \ 3418 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3419 .info = snd_hda_mixer_amp_switch_info, \ 3420 .get = ca0132_switch_get, \ 3421 .put = ca0132_switch_put, \ 3422 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3423 3424 /* stereo */ 3425 #define CA0132_CODEC_VOL(xname, nid, dir) \ 3426 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir) 3427 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \ 3428 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir) 3429 #define CA0132_CODEC_MUTE(xname, nid, dir) \ 3430 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir) 3431 3432 /* lookup tables */ 3433 /* 3434 * Lookup table with decibel values for the DSP. When volume is changed in 3435 * Windows, the DSP is also sent the dB value in floating point. In Windows, 3436 * these values have decimal points, probably because the Windows driver 3437 * actually uses floating point. We can't here, so I made a lookup table of 3438 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the 3439 * DAC's, and 9 is the maximum. 3440 */ 3441 static const unsigned int float_vol_db_lookup[] = { 3442 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000, 3443 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000, 3444 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000, 3445 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000, 3446 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000, 3447 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000, 3448 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000, 3449 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000, 3450 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000, 3451 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000, 3452 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000, 3453 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 3454 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 3455 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 3456 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 3457 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 3458 0x40C00000, 0x40E00000, 0x41000000, 0x41100000 3459 }; 3460 3461 /* 3462 * This table counts from float 0 to 1 in increments of .01, which is 3463 * useful for a few different sliders. 3464 */ 3465 static const unsigned int float_zero_to_one_lookup[] = { 3466 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 3467 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 3468 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 3469 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 3470 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 3471 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 3472 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 3473 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 3474 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 3475 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 3476 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 3477 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 3478 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 3479 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 3480 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 3481 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 3482 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 3483 }; 3484 3485 /* 3486 * This table counts from float 10 to 1000, which is the range of the x-bass 3487 * crossover slider in Windows. 3488 */ 3489 static const unsigned int float_xbass_xover_lookup[] = { 3490 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000, 3491 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000, 3492 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000, 3493 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000, 3494 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000, 3495 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000, 3496 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000, 3497 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000, 3498 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000, 3499 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000, 3500 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000, 3501 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000, 3502 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000, 3503 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000, 3504 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000, 3505 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000, 3506 0x44728000, 0x44750000, 0x44778000, 0x447A0000 3507 }; 3508 3509 /* The following are for tuning of products */ 3510 #ifdef ENABLE_TUNING_CONTROLS 3511 3512 static unsigned int voice_focus_vals_lookup[] = { 3513 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000, 3514 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000, 3515 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000, 3516 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000, 3517 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000, 3518 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000, 3519 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000, 3520 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000, 3521 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000, 3522 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000, 3523 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000, 3524 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000, 3525 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000, 3526 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000, 3527 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000, 3528 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000, 3529 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000, 3530 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000, 3531 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000, 3532 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000, 3533 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000, 3534 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000, 3535 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000, 3536 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000, 3537 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000, 3538 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000, 3539 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000 3540 }; 3541 3542 static unsigned int mic_svm_vals_lookup[] = { 3543 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 3544 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 3545 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 3546 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 3547 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 3548 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 3549 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 3550 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 3551 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 3552 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 3553 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 3554 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 3555 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 3556 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 3557 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 3558 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 3559 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 3560 }; 3561 3562 static unsigned int equalizer_vals_lookup[] = { 3563 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 3564 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 3565 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 3566 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 3567 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 3568 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000, 3569 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000, 3570 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 3571 0x41C00000 3572 }; 3573 3574 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid, 3575 unsigned int *lookup, int idx) 3576 { 3577 int i = 0; 3578 3579 for (i = 0; i < TUNING_CTLS_COUNT; i++) 3580 if (nid == ca0132_tuning_ctls[i].nid) 3581 break; 3582 3583 snd_hda_power_up(codec); 3584 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20, 3585 ca0132_tuning_ctls[i].req, 3586 &(lookup[idx]), sizeof(unsigned int)); 3587 snd_hda_power_down(codec); 3588 3589 return 1; 3590 } 3591 3592 static int tuning_ctl_get(struct snd_kcontrol *kcontrol, 3593 struct snd_ctl_elem_value *ucontrol) 3594 { 3595 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3596 struct ca0132_spec *spec = codec->spec; 3597 hda_nid_t nid = get_amp_nid(kcontrol); 3598 long *valp = ucontrol->value.integer.value; 3599 int idx = nid - TUNING_CTL_START_NID; 3600 3601 *valp = spec->cur_ctl_vals[idx]; 3602 return 0; 3603 } 3604 3605 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol, 3606 struct snd_ctl_elem_info *uinfo) 3607 { 3608 int chs = get_amp_channels(kcontrol); 3609 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3610 uinfo->count = chs == 3 ? 2 : 1; 3611 uinfo->value.integer.min = 20; 3612 uinfo->value.integer.max = 180; 3613 uinfo->value.integer.step = 1; 3614 3615 return 0; 3616 } 3617 3618 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol, 3619 struct snd_ctl_elem_value *ucontrol) 3620 { 3621 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3622 struct ca0132_spec *spec = codec->spec; 3623 hda_nid_t nid = get_amp_nid(kcontrol); 3624 long *valp = ucontrol->value.integer.value; 3625 int idx; 3626 3627 idx = nid - TUNING_CTL_START_NID; 3628 /* any change? */ 3629 if (spec->cur_ctl_vals[idx] == *valp) 3630 return 0; 3631 3632 spec->cur_ctl_vals[idx] = *valp; 3633 3634 idx = *valp - 20; 3635 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx); 3636 3637 return 1; 3638 } 3639 3640 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol, 3641 struct snd_ctl_elem_info *uinfo) 3642 { 3643 int chs = get_amp_channels(kcontrol); 3644 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3645 uinfo->count = chs == 3 ? 2 : 1; 3646 uinfo->value.integer.min = 0; 3647 uinfo->value.integer.max = 100; 3648 uinfo->value.integer.step = 1; 3649 3650 return 0; 3651 } 3652 3653 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol, 3654 struct snd_ctl_elem_value *ucontrol) 3655 { 3656 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3657 struct ca0132_spec *spec = codec->spec; 3658 hda_nid_t nid = get_amp_nid(kcontrol); 3659 long *valp = ucontrol->value.integer.value; 3660 int idx; 3661 3662 idx = nid - TUNING_CTL_START_NID; 3663 /* any change? */ 3664 if (spec->cur_ctl_vals[idx] == *valp) 3665 return 0; 3666 3667 spec->cur_ctl_vals[idx] = *valp; 3668 3669 idx = *valp; 3670 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx); 3671 3672 return 0; 3673 } 3674 3675 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol, 3676 struct snd_ctl_elem_info *uinfo) 3677 { 3678 int chs = get_amp_channels(kcontrol); 3679 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3680 uinfo->count = chs == 3 ? 2 : 1; 3681 uinfo->value.integer.min = 0; 3682 uinfo->value.integer.max = 48; 3683 uinfo->value.integer.step = 1; 3684 3685 return 0; 3686 } 3687 3688 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol, 3689 struct snd_ctl_elem_value *ucontrol) 3690 { 3691 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3692 struct ca0132_spec *spec = codec->spec; 3693 hda_nid_t nid = get_amp_nid(kcontrol); 3694 long *valp = ucontrol->value.integer.value; 3695 int idx; 3696 3697 idx = nid - TUNING_CTL_START_NID; 3698 /* any change? */ 3699 if (spec->cur_ctl_vals[idx] == *valp) 3700 return 0; 3701 3702 spec->cur_ctl_vals[idx] = *valp; 3703 3704 idx = *valp; 3705 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx); 3706 3707 return 1; 3708 } 3709 3710 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0); 3711 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0); 3712 3713 static int add_tuning_control(struct hda_codec *codec, 3714 hda_nid_t pnid, hda_nid_t nid, 3715 const char *name, int dir) 3716 { 3717 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 3718 int type = dir ? HDA_INPUT : HDA_OUTPUT; 3719 struct snd_kcontrol_new knew = 3720 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 3721 3722 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 3723 SNDRV_CTL_ELEM_ACCESS_TLV_READ; 3724 knew.tlv.c = 0; 3725 knew.tlv.p = 0; 3726 switch (pnid) { 3727 case VOICE_FOCUS: 3728 knew.info = voice_focus_ctl_info; 3729 knew.get = tuning_ctl_get; 3730 knew.put = voice_focus_ctl_put; 3731 knew.tlv.p = voice_focus_db_scale; 3732 break; 3733 case MIC_SVM: 3734 knew.info = mic_svm_ctl_info; 3735 knew.get = tuning_ctl_get; 3736 knew.put = mic_svm_ctl_put; 3737 break; 3738 case EQUALIZER: 3739 knew.info = equalizer_ctl_info; 3740 knew.get = tuning_ctl_get; 3741 knew.put = equalizer_ctl_put; 3742 knew.tlv.p = eq_db_scale; 3743 break; 3744 default: 3745 return 0; 3746 } 3747 knew.private_value = 3748 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 3749 sprintf(namestr, "%s %s Volume", name, dirstr[dir]); 3750 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 3751 } 3752 3753 static int add_tuning_ctls(struct hda_codec *codec) 3754 { 3755 int i; 3756 int err; 3757 3758 for (i = 0; i < TUNING_CTLS_COUNT; i++) { 3759 err = add_tuning_control(codec, 3760 ca0132_tuning_ctls[i].parent_nid, 3761 ca0132_tuning_ctls[i].nid, 3762 ca0132_tuning_ctls[i].name, 3763 ca0132_tuning_ctls[i].direct); 3764 if (err < 0) 3765 return err; 3766 } 3767 3768 return 0; 3769 } 3770 3771 static void ca0132_init_tuning_defaults(struct hda_codec *codec) 3772 { 3773 struct ca0132_spec *spec = codec->spec; 3774 int i; 3775 3776 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */ 3777 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10; 3778 /* SVM level defaults to 0.74. */ 3779 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74; 3780 3781 /* EQ defaults to 0dB. */ 3782 for (i = 2; i < TUNING_CTLS_COUNT; i++) 3783 spec->cur_ctl_vals[i] = 24; 3784 } 3785 #endif /*ENABLE_TUNING_CONTROLS*/ 3786 3787 /* 3788 * Select the active output. 3789 * If autodetect is enabled, output will be selected based on jack detection. 3790 * If jack inserted, headphone will be selected, else built-in speakers 3791 * If autodetect is disabled, output will be selected based on selection. 3792 */ 3793 static int ca0132_select_out(struct hda_codec *codec) 3794 { 3795 struct ca0132_spec *spec = codec->spec; 3796 unsigned int pin_ctl; 3797 int jack_present; 3798 int auto_jack; 3799 unsigned int tmp; 3800 int err; 3801 3802 codec_dbg(codec, "ca0132_select_out\n"); 3803 3804 snd_hda_power_up_pm(codec); 3805 3806 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 3807 3808 if (auto_jack) 3809 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp); 3810 else 3811 jack_present = 3812 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID]; 3813 3814 if (jack_present) 3815 spec->cur_out_type = HEADPHONE_OUT; 3816 else 3817 spec->cur_out_type = SPEAKER_OUT; 3818 3819 if (spec->cur_out_type == SPEAKER_OUT) { 3820 codec_dbg(codec, "ca0132_select_out speaker\n"); 3821 /*speaker out config*/ 3822 tmp = FLOAT_ONE; 3823 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 3824 if (err < 0) 3825 goto exit; 3826 /*enable speaker EQ*/ 3827 tmp = FLOAT_ONE; 3828 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 3829 if (err < 0) 3830 goto exit; 3831 3832 /* Setup EAPD */ 3833 snd_hda_codec_write(codec, spec->out_pins[1], 0, 3834 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 3835 snd_hda_codec_write(codec, spec->out_pins[0], 0, 3836 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 3837 snd_hda_codec_write(codec, spec->out_pins[0], 0, 3838 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 3839 snd_hda_codec_write(codec, spec->out_pins[0], 0, 3840 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 3841 3842 /* disable headphone node */ 3843 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 3844 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 3845 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 3846 pin_ctl & ~PIN_HP); 3847 /* enable speaker node */ 3848 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 3849 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 3850 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 3851 pin_ctl | PIN_OUT); 3852 } else { 3853 codec_dbg(codec, "ca0132_select_out hp\n"); 3854 /*headphone out config*/ 3855 tmp = FLOAT_ZERO; 3856 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 3857 if (err < 0) 3858 goto exit; 3859 /*disable speaker EQ*/ 3860 tmp = FLOAT_ZERO; 3861 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 3862 if (err < 0) 3863 goto exit; 3864 3865 /* Setup EAPD */ 3866 snd_hda_codec_write(codec, spec->out_pins[0], 0, 3867 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 3868 snd_hda_codec_write(codec, spec->out_pins[0], 0, 3869 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 3870 snd_hda_codec_write(codec, spec->out_pins[1], 0, 3871 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 3872 snd_hda_codec_write(codec, spec->out_pins[0], 0, 3873 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 3874 3875 /* disable speaker*/ 3876 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 3877 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 3878 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 3879 pin_ctl & ~PIN_HP); 3880 /* enable headphone*/ 3881 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 3882 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 3883 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 3884 pin_ctl | PIN_HP); 3885 } 3886 3887 exit: 3888 snd_hda_power_down_pm(codec); 3889 3890 return err < 0 ? err : 0; 3891 } 3892 3893 /* 3894 * This function behaves similarly to the ca0132_select_out funciton above, 3895 * except with a few differences. It adds the ability to select the current 3896 * output with an enumerated control "output source" if the auto detect 3897 * mute switch is set to off. If the auto detect mute switch is enabled, it 3898 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection. 3899 * It also adds the ability to auto-detect the front headphone port. The only 3900 * way to select surround is to disable auto detect, and set Surround with the 3901 * enumerated control. 3902 */ 3903 static int ca0132_alt_select_out(struct hda_codec *codec) 3904 { 3905 struct ca0132_spec *spec = codec->spec; 3906 unsigned int pin_ctl; 3907 int jack_present; 3908 int auto_jack; 3909 unsigned int i; 3910 unsigned int tmp; 3911 int err; 3912 /* Default Headphone is rear headphone */ 3913 hda_nid_t headphone_nid = spec->out_pins[1]; 3914 3915 codec_dbg(codec, "%s\n", __func__); 3916 3917 snd_hda_power_up_pm(codec); 3918 3919 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 3920 3921 /* 3922 * If headphone rear or front is plugged in, set to headphone. 3923 * If neither is plugged in, set to rear line out. Only if 3924 * hp/speaker auto detect is enabled. 3925 */ 3926 if (auto_jack) { 3927 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) || 3928 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp); 3929 3930 if (jack_present) 3931 spec->cur_out_type = HEADPHONE_OUT; 3932 else 3933 spec->cur_out_type = SPEAKER_OUT; 3934 } else 3935 spec->cur_out_type = spec->out_enum_val; 3936 3937 /* Begin DSP output switch */ 3938 tmp = FLOAT_ONE; 3939 err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp); 3940 if (err < 0) 3941 goto exit; 3942 3943 switch (spec->cur_out_type) { 3944 case SPEAKER_OUT: 3945 codec_dbg(codec, "%s speaker\n", __func__); 3946 /*speaker out config*/ 3947 switch (spec->quirk) { 3948 case QUIRK_SBZ: 3949 writew(0x0007, spec->mem_base + 0x320); 3950 writew(0x0104, spec->mem_base + 0x320); 3951 writew(0x0101, spec->mem_base + 0x320); 3952 chipio_set_control_param(codec, 0x0D, 0x18); 3953 break; 3954 case QUIRK_R3DI: 3955 chipio_set_control_param(codec, 0x0D, 0x24); 3956 r3di_gpio_out_set(codec, R3DI_LINE_OUT); 3957 break; 3958 } 3959 3960 /* disable headphone node */ 3961 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 3962 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 3963 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 3964 pin_ctl & ~PIN_HP); 3965 /* enable line-out node */ 3966 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 3967 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 3968 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 3969 pin_ctl | PIN_OUT); 3970 /* Enable EAPD */ 3971 snd_hda_codec_write(codec, spec->out_pins[0], 0, 3972 AC_VERB_SET_EAPD_BTLENABLE, 0x01); 3973 3974 /* If PlayEnhancement is enabled, set different source */ 3975 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 3976 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE); 3977 else 3978 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT); 3979 break; 3980 case HEADPHONE_OUT: 3981 codec_dbg(codec, "%s hp\n", __func__); 3982 /* Headphone out config*/ 3983 switch (spec->quirk) { 3984 case QUIRK_SBZ: 3985 writew(0x0107, spec->mem_base + 0x320); 3986 writew(0x0104, spec->mem_base + 0x320); 3987 writew(0x0001, spec->mem_base + 0x320); 3988 chipio_set_control_param(codec, 0x0D, 0x12); 3989 break; 3990 case QUIRK_R3DI: 3991 chipio_set_control_param(codec, 0x0D, 0x21); 3992 r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT); 3993 break; 3994 } 3995 3996 snd_hda_codec_write(codec, spec->out_pins[0], 0, 3997 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 3998 3999 /* disable speaker*/ 4000 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4001 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4002 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4003 pin_ctl & ~PIN_HP); 4004 4005 /* enable headphone, either front or rear */ 4006 4007 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp)) 4008 headphone_nid = spec->out_pins[2]; 4009 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp)) 4010 headphone_nid = spec->out_pins[1]; 4011 4012 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0, 4013 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4014 snd_hda_set_pin_ctl(codec, headphone_nid, 4015 pin_ctl | PIN_HP); 4016 4017 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4018 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE); 4019 else 4020 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO); 4021 break; 4022 case SURROUND_OUT: 4023 codec_dbg(codec, "%s surround\n", __func__); 4024 /* Surround out config*/ 4025 switch (spec->quirk) { 4026 case QUIRK_SBZ: 4027 writew(0x0007, spec->mem_base + 0x320); 4028 writew(0x0104, spec->mem_base + 0x320); 4029 writew(0x0101, spec->mem_base + 0x320); 4030 chipio_set_control_param(codec, 0x0D, 0x18); 4031 break; 4032 case QUIRK_R3DI: 4033 chipio_set_control_param(codec, 0x0D, 0x24); 4034 r3di_gpio_out_set(codec, R3DI_LINE_OUT); 4035 break; 4036 } 4037 /* enable line out node */ 4038 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4039 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4040 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4041 pin_ctl | PIN_OUT); 4042 /* Disable headphone out */ 4043 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4044 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4045 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4046 pin_ctl & ~PIN_HP); 4047 /* Enable EAPD on line out */ 4048 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4049 AC_VERB_SET_EAPD_BTLENABLE, 0x01); 4050 /* enable center/lfe out node */ 4051 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0, 4052 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4053 snd_hda_set_pin_ctl(codec, spec->out_pins[2], 4054 pin_ctl | PIN_OUT); 4055 /* Now set rear surround node as out. */ 4056 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0, 4057 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4058 snd_hda_set_pin_ctl(codec, spec->out_pins[3], 4059 pin_ctl | PIN_OUT); 4060 4061 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4062 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE); 4063 else 4064 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT); 4065 break; 4066 } 4067 4068 /* run through the output dsp commands for line-out */ 4069 for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) { 4070 err = dspio_set_uint_param(codec, 4071 alt_out_presets[spec->cur_out_type].mids[i], 4072 alt_out_presets[spec->cur_out_type].reqs[i], 4073 alt_out_presets[spec->cur_out_type].vals[i]); 4074 4075 if (err < 0) 4076 goto exit; 4077 } 4078 4079 exit: 4080 snd_hda_power_down_pm(codec); 4081 4082 return err < 0 ? err : 0; 4083 } 4084 4085 static void ca0132_unsol_hp_delayed(struct work_struct *work) 4086 { 4087 struct ca0132_spec *spec = container_of( 4088 to_delayed_work(work), struct ca0132_spec, unsol_hp_work); 4089 struct hda_jack_tbl *jack; 4090 4091 if (spec->use_alt_functions) 4092 ca0132_alt_select_out(spec->codec); 4093 else 4094 ca0132_select_out(spec->codec); 4095 4096 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp); 4097 if (jack) { 4098 jack->block_report = 0; 4099 snd_hda_jack_report_sync(spec->codec); 4100 } 4101 } 4102 4103 static void ca0132_set_dmic(struct hda_codec *codec, int enable); 4104 static int ca0132_mic_boost_set(struct hda_codec *codec, long val); 4105 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val); 4106 static void resume_mic1(struct hda_codec *codec, unsigned int oldval); 4107 static int stop_mic1(struct hda_codec *codec); 4108 static int ca0132_cvoice_switch_set(struct hda_codec *codec); 4109 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val); 4110 4111 /* 4112 * Select the active VIP source 4113 */ 4114 static int ca0132_set_vipsource(struct hda_codec *codec, int val) 4115 { 4116 struct ca0132_spec *spec = codec->spec; 4117 unsigned int tmp; 4118 4119 if (spec->dsp_state != DSP_DOWNLOADED) 4120 return 0; 4121 4122 /* if CrystalVoice if off, vipsource should be 0 */ 4123 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4124 (val == 0)) { 4125 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4126 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4127 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4128 if (spec->cur_mic_type == DIGITAL_MIC) 4129 tmp = FLOAT_TWO; 4130 else 4131 tmp = FLOAT_ONE; 4132 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4133 tmp = FLOAT_ZERO; 4134 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4135 } else { 4136 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4137 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4138 if (spec->cur_mic_type == DIGITAL_MIC) 4139 tmp = FLOAT_TWO; 4140 else 4141 tmp = FLOAT_ONE; 4142 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4143 tmp = FLOAT_ONE; 4144 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4145 msleep(20); 4146 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4147 } 4148 4149 return 1; 4150 } 4151 4152 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val) 4153 { 4154 struct ca0132_spec *spec = codec->spec; 4155 unsigned int tmp; 4156 4157 if (spec->dsp_state != DSP_DOWNLOADED) 4158 return 0; 4159 4160 codec_dbg(codec, "%s\n", __func__); 4161 4162 chipio_set_stream_control(codec, 0x03, 0); 4163 chipio_set_stream_control(codec, 0x04, 0); 4164 4165 /* if CrystalVoice is off, vipsource should be 0 */ 4166 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4167 (val == 0) || spec->in_enum_val == REAR_LINE_IN) { 4168 codec_dbg(codec, "%s: off.", __func__); 4169 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4170 4171 tmp = FLOAT_ZERO; 4172 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4173 4174 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4175 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4176 if (spec->quirk == QUIRK_R3DI) 4177 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4178 4179 4180 if (spec->in_enum_val == REAR_LINE_IN) 4181 tmp = FLOAT_ZERO; 4182 else { 4183 if (spec->quirk == QUIRK_SBZ) 4184 tmp = FLOAT_THREE; 4185 else 4186 tmp = FLOAT_ONE; 4187 } 4188 4189 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4190 4191 } else { 4192 codec_dbg(codec, "%s: on.", __func__); 4193 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4194 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4195 if (spec->quirk == QUIRK_R3DI) 4196 chipio_set_conn_rate(codec, 0x0F, SR_16_000); 4197 4198 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID]) 4199 tmp = FLOAT_TWO; 4200 else 4201 tmp = FLOAT_ONE; 4202 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4203 4204 tmp = FLOAT_ONE; 4205 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4206 4207 msleep(20); 4208 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4209 } 4210 4211 chipio_set_stream_control(codec, 0x03, 1); 4212 chipio_set_stream_control(codec, 0x04, 1); 4213 4214 return 1; 4215 } 4216 4217 /* 4218 * Select the active microphone. 4219 * If autodetect is enabled, mic will be selected based on jack detection. 4220 * If jack inserted, ext.mic will be selected, else built-in mic 4221 * If autodetect is disabled, mic will be selected based on selection. 4222 */ 4223 static int ca0132_select_mic(struct hda_codec *codec) 4224 { 4225 struct ca0132_spec *spec = codec->spec; 4226 int jack_present; 4227 int auto_jack; 4228 4229 codec_dbg(codec, "ca0132_select_mic\n"); 4230 4231 snd_hda_power_up_pm(codec); 4232 4233 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 4234 4235 if (auto_jack) 4236 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1); 4237 else 4238 jack_present = 4239 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID]; 4240 4241 if (jack_present) 4242 spec->cur_mic_type = LINE_MIC_IN; 4243 else 4244 spec->cur_mic_type = DIGITAL_MIC; 4245 4246 if (spec->cur_mic_type == DIGITAL_MIC) { 4247 /* enable digital Mic */ 4248 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000); 4249 ca0132_set_dmic(codec, 1); 4250 ca0132_mic_boost_set(codec, 0); 4251 /* set voice focus */ 4252 ca0132_effects_set(codec, VOICE_FOCUS, 4253 spec->effects_switch 4254 [VOICE_FOCUS - EFFECT_START_NID]); 4255 } else { 4256 /* disable digital Mic */ 4257 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000); 4258 ca0132_set_dmic(codec, 0); 4259 ca0132_mic_boost_set(codec, spec->cur_mic_boost); 4260 /* disable voice focus */ 4261 ca0132_effects_set(codec, VOICE_FOCUS, 0); 4262 } 4263 4264 snd_hda_power_down_pm(codec); 4265 4266 return 0; 4267 } 4268 4269 /* 4270 * Select the active input. 4271 * Mic detection isn't used, because it's kind of pointless on the SBZ. 4272 * The front mic has no jack-detection, so the only way to switch to it 4273 * is to do it manually in alsamixer. 4274 */ 4275 static int ca0132_alt_select_in(struct hda_codec *codec) 4276 { 4277 struct ca0132_spec *spec = codec->spec; 4278 unsigned int tmp; 4279 4280 codec_dbg(codec, "%s\n", __func__); 4281 4282 snd_hda_power_up_pm(codec); 4283 4284 chipio_set_stream_control(codec, 0x03, 0); 4285 chipio_set_stream_control(codec, 0x04, 0); 4286 4287 spec->cur_mic_type = spec->in_enum_val; 4288 4289 switch (spec->cur_mic_type) { 4290 case REAR_MIC: 4291 switch (spec->quirk) { 4292 case QUIRK_SBZ: 4293 writew(0x0000, spec->mem_base + 0x320); 4294 tmp = FLOAT_THREE; 4295 break; 4296 case QUIRK_R3DI: 4297 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 4298 tmp = FLOAT_ONE; 4299 break; 4300 default: 4301 tmp = FLOAT_ONE; 4302 break; 4303 } 4304 4305 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4306 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4307 if (spec->quirk == QUIRK_R3DI) 4308 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4309 4310 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4311 4312 chipio_set_stream_control(codec, 0x03, 1); 4313 chipio_set_stream_control(codec, 0x04, 1); 4314 4315 if (spec->quirk == QUIRK_SBZ) { 4316 chipio_write(codec, 0x18B098, 0x0000000C); 4317 chipio_write(codec, 0x18B09C, 0x0000000C); 4318 } 4319 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 4320 break; 4321 case REAR_LINE_IN: 4322 ca0132_mic_boost_set(codec, 0); 4323 switch (spec->quirk) { 4324 case QUIRK_SBZ: 4325 writew(0x0000, spec->mem_base + 0x320); 4326 break; 4327 case QUIRK_R3DI: 4328 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 4329 break; 4330 } 4331 4332 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4333 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4334 if (spec->quirk == QUIRK_R3DI) 4335 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4336 4337 tmp = FLOAT_ZERO; 4338 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4339 4340 if (spec->quirk == QUIRK_SBZ) { 4341 chipio_write(codec, 0x18B098, 0x00000000); 4342 chipio_write(codec, 0x18B09C, 0x00000000); 4343 } 4344 4345 chipio_set_stream_control(codec, 0x03, 1); 4346 chipio_set_stream_control(codec, 0x04, 1); 4347 break; 4348 case FRONT_MIC: 4349 switch (spec->quirk) { 4350 case QUIRK_SBZ: 4351 writew(0x0100, spec->mem_base + 0x320); 4352 writew(0x0005, spec->mem_base + 0x320); 4353 tmp = FLOAT_THREE; 4354 break; 4355 case QUIRK_R3DI: 4356 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC); 4357 tmp = FLOAT_ONE; 4358 break; 4359 default: 4360 tmp = FLOAT_ONE; 4361 break; 4362 } 4363 4364 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4365 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4366 if (spec->quirk == QUIRK_R3DI) 4367 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4368 4369 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4370 4371 chipio_set_stream_control(codec, 0x03, 1); 4372 chipio_set_stream_control(codec, 0x04, 1); 4373 4374 if (spec->quirk == QUIRK_SBZ) { 4375 chipio_write(codec, 0x18B098, 0x0000000C); 4376 chipio_write(codec, 0x18B09C, 0x000000CC); 4377 } 4378 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 4379 break; 4380 } 4381 ca0132_cvoice_switch_set(codec); 4382 4383 snd_hda_power_down_pm(codec); 4384 return 0; 4385 4386 } 4387 4388 /* 4389 * Check if VNODE settings take effect immediately. 4390 */ 4391 static bool ca0132_is_vnode_effective(struct hda_codec *codec, 4392 hda_nid_t vnid, 4393 hda_nid_t *shared_nid) 4394 { 4395 struct ca0132_spec *spec = codec->spec; 4396 hda_nid_t nid; 4397 4398 switch (vnid) { 4399 case VNID_SPK: 4400 nid = spec->shared_out_nid; 4401 break; 4402 case VNID_MIC: 4403 nid = spec->shared_mic_nid; 4404 break; 4405 default: 4406 return false; 4407 } 4408 4409 if (shared_nid) 4410 *shared_nid = nid; 4411 4412 return true; 4413 } 4414 4415 /* 4416 * The following functions are control change helpers. 4417 * They return 0 if no changed. Return 1 if changed. 4418 */ 4419 static int ca0132_voicefx_set(struct hda_codec *codec, int enable) 4420 { 4421 struct ca0132_spec *spec = codec->spec; 4422 unsigned int tmp; 4423 4424 /* based on CrystalVoice state to enable VoiceFX. */ 4425 if (enable) { 4426 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ? 4427 FLOAT_ONE : FLOAT_ZERO; 4428 } else { 4429 tmp = FLOAT_ZERO; 4430 } 4431 4432 dspio_set_uint_param(codec, ca0132_voicefx.mid, 4433 ca0132_voicefx.reqs[0], tmp); 4434 4435 return 1; 4436 } 4437 4438 /* 4439 * Set the effects parameters 4440 */ 4441 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val) 4442 { 4443 struct ca0132_spec *spec = codec->spec; 4444 unsigned int on, tmp; 4445 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 4446 int err = 0; 4447 int idx = nid - EFFECT_START_NID; 4448 4449 if ((idx < 0) || (idx >= num_fx)) 4450 return 0; /* no changed */ 4451 4452 /* for out effect, qualify with PE */ 4453 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) { 4454 /* if PE if off, turn off out effects. */ 4455 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4456 val = 0; 4457 } 4458 4459 /* for in effect, qualify with CrystalVoice */ 4460 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) { 4461 /* if CrystalVoice if off, turn off in effects. */ 4462 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 4463 val = 0; 4464 4465 /* Voice Focus applies to 2-ch Mic, Digital Mic */ 4466 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC)) 4467 val = 0; 4468 4469 /* If Voice Focus on SBZ, set to two channel. */ 4470 if ((nid == VOICE_FOCUS) && (spec->quirk == QUIRK_SBZ) 4471 && (spec->cur_mic_type != REAR_LINE_IN)) { 4472 if (spec->effects_switch[CRYSTAL_VOICE - 4473 EFFECT_START_NID]) { 4474 4475 if (spec->effects_switch[VOICE_FOCUS - 4476 EFFECT_START_NID]) { 4477 tmp = FLOAT_TWO; 4478 val = 1; 4479 } else 4480 tmp = FLOAT_ONE; 4481 4482 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4483 } 4484 } 4485 /* 4486 * For SBZ noise reduction, there's an extra command 4487 * to module ID 0x47. No clue why. 4488 */ 4489 if ((nid == NOISE_REDUCTION) && (spec->quirk == QUIRK_SBZ) 4490 && (spec->cur_mic_type != REAR_LINE_IN)) { 4491 if (spec->effects_switch[CRYSTAL_VOICE - 4492 EFFECT_START_NID]) { 4493 if (spec->effects_switch[NOISE_REDUCTION - 4494 EFFECT_START_NID]) 4495 tmp = FLOAT_ONE; 4496 else 4497 tmp = FLOAT_ZERO; 4498 } else 4499 tmp = FLOAT_ZERO; 4500 4501 dspio_set_uint_param(codec, 0x47, 0x00, tmp); 4502 } 4503 4504 /* If rear line in disable effects. */ 4505 if (spec->use_alt_functions && 4506 spec->in_enum_val == REAR_LINE_IN) 4507 val = 0; 4508 } 4509 4510 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n", 4511 nid, val); 4512 4513 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE; 4514 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid, 4515 ca0132_effects[idx].reqs[0], on); 4516 4517 if (err < 0) 4518 return 0; /* no changed */ 4519 4520 return 1; 4521 } 4522 4523 /* 4524 * Turn on/off Playback Enhancements 4525 */ 4526 static int ca0132_pe_switch_set(struct hda_codec *codec) 4527 { 4528 struct ca0132_spec *spec = codec->spec; 4529 hda_nid_t nid; 4530 int i, ret = 0; 4531 4532 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n", 4533 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]); 4534 4535 if (spec->use_alt_functions) 4536 ca0132_alt_select_out(codec); 4537 4538 i = OUT_EFFECT_START_NID - EFFECT_START_NID; 4539 nid = OUT_EFFECT_START_NID; 4540 /* PE affects all out effects */ 4541 for (; nid < OUT_EFFECT_END_NID; nid++, i++) 4542 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 4543 4544 return ret; 4545 } 4546 4547 /* Check if Mic1 is streaming, if so, stop streaming */ 4548 static int stop_mic1(struct hda_codec *codec) 4549 { 4550 struct ca0132_spec *spec = codec->spec; 4551 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0, 4552 AC_VERB_GET_CONV, 0); 4553 if (oldval != 0) 4554 snd_hda_codec_write(codec, spec->adcs[0], 0, 4555 AC_VERB_SET_CHANNEL_STREAMID, 4556 0); 4557 return oldval; 4558 } 4559 4560 /* Resume Mic1 streaming if it was stopped. */ 4561 static void resume_mic1(struct hda_codec *codec, unsigned int oldval) 4562 { 4563 struct ca0132_spec *spec = codec->spec; 4564 /* Restore the previous stream and channel */ 4565 if (oldval != 0) 4566 snd_hda_codec_write(codec, spec->adcs[0], 0, 4567 AC_VERB_SET_CHANNEL_STREAMID, 4568 oldval); 4569 } 4570 4571 /* 4572 * Turn on/off CrystalVoice 4573 */ 4574 static int ca0132_cvoice_switch_set(struct hda_codec *codec) 4575 { 4576 struct ca0132_spec *spec = codec->spec; 4577 hda_nid_t nid; 4578 int i, ret = 0; 4579 unsigned int oldval; 4580 4581 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n", 4582 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]); 4583 4584 i = IN_EFFECT_START_NID - EFFECT_START_NID; 4585 nid = IN_EFFECT_START_NID; 4586 /* CrystalVoice affects all in effects */ 4587 for (; nid < IN_EFFECT_END_NID; nid++, i++) 4588 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 4589 4590 /* including VoiceFX */ 4591 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0)); 4592 4593 /* set correct vipsource */ 4594 oldval = stop_mic1(codec); 4595 if (spec->use_alt_functions) 4596 ret |= ca0132_alt_set_vipsource(codec, 1); 4597 else 4598 ret |= ca0132_set_vipsource(codec, 1); 4599 resume_mic1(codec, oldval); 4600 return ret; 4601 } 4602 4603 static int ca0132_mic_boost_set(struct hda_codec *codec, long val) 4604 { 4605 struct ca0132_spec *spec = codec->spec; 4606 int ret = 0; 4607 4608 if (val) /* on */ 4609 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 4610 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3); 4611 else /* off */ 4612 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 4613 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0); 4614 4615 return ret; 4616 } 4617 4618 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val) 4619 { 4620 struct ca0132_spec *spec = codec->spec; 4621 int ret = 0; 4622 4623 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 4624 HDA_INPUT, 0, HDA_AMP_VOLMASK, val); 4625 return ret; 4626 } 4627 4628 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol, 4629 struct snd_ctl_elem_value *ucontrol) 4630 { 4631 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4632 hda_nid_t nid = get_amp_nid(kcontrol); 4633 hda_nid_t shared_nid = 0; 4634 bool effective; 4635 int ret = 0; 4636 struct ca0132_spec *spec = codec->spec; 4637 int auto_jack; 4638 4639 if (nid == VNID_HP_SEL) { 4640 auto_jack = 4641 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4642 if (!auto_jack) { 4643 if (spec->use_alt_functions) 4644 ca0132_alt_select_out(codec); 4645 else 4646 ca0132_select_out(codec); 4647 } 4648 return 1; 4649 } 4650 4651 if (nid == VNID_AMIC1_SEL) { 4652 auto_jack = 4653 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 4654 if (!auto_jack) 4655 ca0132_select_mic(codec); 4656 return 1; 4657 } 4658 4659 if (nid == VNID_HP_ASEL) { 4660 if (spec->use_alt_functions) 4661 ca0132_alt_select_out(codec); 4662 else 4663 ca0132_select_out(codec); 4664 return 1; 4665 } 4666 4667 if (nid == VNID_AMIC1_ASEL) { 4668 ca0132_select_mic(codec); 4669 return 1; 4670 } 4671 4672 /* if effective conditions, then update hw immediately. */ 4673 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 4674 if (effective) { 4675 int dir = get_amp_direction(kcontrol); 4676 int ch = get_amp_channels(kcontrol); 4677 unsigned long pval; 4678 4679 mutex_lock(&codec->control_mutex); 4680 pval = kcontrol->private_value; 4681 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 4682 0, dir); 4683 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol); 4684 kcontrol->private_value = pval; 4685 mutex_unlock(&codec->control_mutex); 4686 } 4687 4688 return ret; 4689 } 4690 /* End of control change helpers. */ 4691 /* 4692 * Below I've added controls to mess with the effect levels, I've only enabled 4693 * them on the Sound Blaster Z, but they would probably also work on the 4694 * Chromebook. I figured they were probably tuned specifically for it, and left 4695 * out for a reason. 4696 */ 4697 4698 /* Sets DSP effect level from the sliders above the controls */ 4699 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid, 4700 const unsigned int *lookup, int idx) 4701 { 4702 int i = 0; 4703 unsigned int y; 4704 /* 4705 * For X_BASS, req 2 is actually crossover freq instead of 4706 * effect level 4707 */ 4708 if (nid == X_BASS) 4709 y = 2; 4710 else 4711 y = 1; 4712 4713 snd_hda_power_up(codec); 4714 if (nid == XBASS_XOVER) { 4715 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 4716 if (ca0132_effects[i].nid == X_BASS) 4717 break; 4718 4719 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 4720 ca0132_effects[i].reqs[1], 4721 &(lookup[idx - 1]), sizeof(unsigned int)); 4722 } else { 4723 /* Find the actual effect structure */ 4724 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 4725 if (nid == ca0132_effects[i].nid) 4726 break; 4727 4728 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 4729 ca0132_effects[i].reqs[y], 4730 &(lookup[idx]), sizeof(unsigned int)); 4731 } 4732 4733 snd_hda_power_down(codec); 4734 4735 return 0; 4736 } 4737 4738 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol, 4739 struct snd_ctl_elem_value *ucontrol) 4740 { 4741 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4742 struct ca0132_spec *spec = codec->spec; 4743 long *valp = ucontrol->value.integer.value; 4744 4745 *valp = spec->xbass_xover_freq; 4746 return 0; 4747 } 4748 4749 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol, 4750 struct snd_ctl_elem_value *ucontrol) 4751 { 4752 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4753 struct ca0132_spec *spec = codec->spec; 4754 hda_nid_t nid = get_amp_nid(kcontrol); 4755 long *valp = ucontrol->value.integer.value; 4756 int idx = nid - OUT_EFFECT_START_NID; 4757 4758 *valp = spec->fx_ctl_val[idx]; 4759 return 0; 4760 } 4761 4762 /* 4763 * The X-bass crossover starts at 10hz, so the min is 1. The 4764 * frequency is set in multiples of 10. 4765 */ 4766 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol, 4767 struct snd_ctl_elem_info *uinfo) 4768 { 4769 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4770 uinfo->count = 1; 4771 uinfo->value.integer.min = 1; 4772 uinfo->value.integer.max = 100; 4773 uinfo->value.integer.step = 1; 4774 4775 return 0; 4776 } 4777 4778 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol, 4779 struct snd_ctl_elem_info *uinfo) 4780 { 4781 int chs = get_amp_channels(kcontrol); 4782 4783 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4784 uinfo->count = chs == 3 ? 2 : 1; 4785 uinfo->value.integer.min = 0; 4786 uinfo->value.integer.max = 100; 4787 uinfo->value.integer.step = 1; 4788 4789 return 0; 4790 } 4791 4792 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol, 4793 struct snd_ctl_elem_value *ucontrol) 4794 { 4795 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4796 struct ca0132_spec *spec = codec->spec; 4797 hda_nid_t nid = get_amp_nid(kcontrol); 4798 long *valp = ucontrol->value.integer.value; 4799 int idx; 4800 4801 /* any change? */ 4802 if (spec->xbass_xover_freq == *valp) 4803 return 0; 4804 4805 spec->xbass_xover_freq = *valp; 4806 4807 idx = *valp; 4808 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx); 4809 4810 return 0; 4811 } 4812 4813 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol, 4814 struct snd_ctl_elem_value *ucontrol) 4815 { 4816 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4817 struct ca0132_spec *spec = codec->spec; 4818 hda_nid_t nid = get_amp_nid(kcontrol); 4819 long *valp = ucontrol->value.integer.value; 4820 int idx; 4821 4822 idx = nid - EFFECT_START_NID; 4823 /* any change? */ 4824 if (spec->fx_ctl_val[idx] == *valp) 4825 return 0; 4826 4827 spec->fx_ctl_val[idx] = *valp; 4828 4829 idx = *valp; 4830 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx); 4831 4832 return 0; 4833 } 4834 4835 4836 /* 4837 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original 4838 * only has off or full 30 dB, and didn't like making a volume slider that has 4839 * traditional 0-100 in alsamixer that goes in big steps. I like enum better. 4840 */ 4841 #define MIC_BOOST_NUM_OF_STEPS 4 4842 #define MIC_BOOST_ENUM_MAX_STRLEN 10 4843 4844 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol, 4845 struct snd_ctl_elem_info *uinfo) 4846 { 4847 char *sfx = "dB"; 4848 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 4849 4850 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 4851 uinfo->count = 1; 4852 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS; 4853 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS) 4854 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1; 4855 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx); 4856 strcpy(uinfo->value.enumerated.name, namestr); 4857 return 0; 4858 } 4859 4860 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol, 4861 struct snd_ctl_elem_value *ucontrol) 4862 { 4863 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4864 struct ca0132_spec *spec = codec->spec; 4865 4866 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val; 4867 return 0; 4868 } 4869 4870 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol, 4871 struct snd_ctl_elem_value *ucontrol) 4872 { 4873 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4874 struct ca0132_spec *spec = codec->spec; 4875 int sel = ucontrol->value.enumerated.item[0]; 4876 unsigned int items = MIC_BOOST_NUM_OF_STEPS; 4877 4878 if (sel >= items) 4879 return 0; 4880 4881 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n", 4882 sel); 4883 4884 spec->mic_boost_enum_val = sel; 4885 4886 if (spec->in_enum_val != REAR_LINE_IN) 4887 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 4888 4889 return 1; 4890 } 4891 4892 4893 /* 4894 * Input Select Control for alternative ca0132 codecs. This exists because 4895 * front microphone has no auto-detect, and we need a way to set the rear 4896 * as line-in 4897 */ 4898 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol, 4899 struct snd_ctl_elem_info *uinfo) 4900 { 4901 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 4902 uinfo->count = 1; 4903 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS; 4904 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS) 4905 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1; 4906 strcpy(uinfo->value.enumerated.name, 4907 in_src_str[uinfo->value.enumerated.item]); 4908 return 0; 4909 } 4910 4911 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol, 4912 struct snd_ctl_elem_value *ucontrol) 4913 { 4914 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4915 struct ca0132_spec *spec = codec->spec; 4916 4917 ucontrol->value.enumerated.item[0] = spec->in_enum_val; 4918 return 0; 4919 } 4920 4921 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol, 4922 struct snd_ctl_elem_value *ucontrol) 4923 { 4924 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4925 struct ca0132_spec *spec = codec->spec; 4926 int sel = ucontrol->value.enumerated.item[0]; 4927 unsigned int items = IN_SRC_NUM_OF_INPUTS; 4928 4929 if (sel >= items) 4930 return 0; 4931 4932 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n", 4933 sel, in_src_str[sel]); 4934 4935 spec->in_enum_val = sel; 4936 4937 ca0132_alt_select_in(codec); 4938 4939 return 1; 4940 } 4941 4942 /* Sound Blaster Z Output Select Control */ 4943 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol, 4944 struct snd_ctl_elem_info *uinfo) 4945 { 4946 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 4947 uinfo->count = 1; 4948 uinfo->value.enumerated.items = NUM_OF_OUTPUTS; 4949 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS) 4950 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1; 4951 strcpy(uinfo->value.enumerated.name, 4952 alt_out_presets[uinfo->value.enumerated.item].name); 4953 return 0; 4954 } 4955 4956 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol, 4957 struct snd_ctl_elem_value *ucontrol) 4958 { 4959 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4960 struct ca0132_spec *spec = codec->spec; 4961 4962 ucontrol->value.enumerated.item[0] = spec->out_enum_val; 4963 return 0; 4964 } 4965 4966 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol, 4967 struct snd_ctl_elem_value *ucontrol) 4968 { 4969 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4970 struct ca0132_spec *spec = codec->spec; 4971 int sel = ucontrol->value.enumerated.item[0]; 4972 unsigned int items = NUM_OF_OUTPUTS; 4973 unsigned int auto_jack; 4974 4975 if (sel >= items) 4976 return 0; 4977 4978 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n", 4979 sel, alt_out_presets[sel].name); 4980 4981 spec->out_enum_val = sel; 4982 4983 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4984 4985 if (!auto_jack) 4986 ca0132_alt_select_out(codec); 4987 4988 return 1; 4989 } 4990 4991 /* 4992 * Smart Volume output setting control. Three different settings, Normal, 4993 * which takes the value from the smart volume slider. The two others, loud 4994 * and night, disregard the slider value and have uneditable values. 4995 */ 4996 #define NUM_OF_SVM_SETTINGS 3 4997 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" }; 4998 4999 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol, 5000 struct snd_ctl_elem_info *uinfo) 5001 { 5002 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5003 uinfo->count = 1; 5004 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS; 5005 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS) 5006 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1; 5007 strcpy(uinfo->value.enumerated.name, 5008 out_svm_set_enum_str[uinfo->value.enumerated.item]); 5009 return 0; 5010 } 5011 5012 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol, 5013 struct snd_ctl_elem_value *ucontrol) 5014 { 5015 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5016 struct ca0132_spec *spec = codec->spec; 5017 5018 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting; 5019 return 0; 5020 } 5021 5022 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol, 5023 struct snd_ctl_elem_value *ucontrol) 5024 { 5025 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5026 struct ca0132_spec *spec = codec->spec; 5027 int sel = ucontrol->value.enumerated.item[0]; 5028 unsigned int items = NUM_OF_SVM_SETTINGS; 5029 unsigned int idx = SMART_VOLUME - EFFECT_START_NID; 5030 unsigned int tmp; 5031 5032 if (sel >= items) 5033 return 0; 5034 5035 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n", 5036 sel, out_svm_set_enum_str[sel]); 5037 5038 spec->smart_volume_setting = sel; 5039 5040 switch (sel) { 5041 case 0: 5042 tmp = FLOAT_ZERO; 5043 break; 5044 case 1: 5045 tmp = FLOAT_ONE; 5046 break; 5047 case 2: 5048 tmp = FLOAT_TWO; 5049 break; 5050 default: 5051 tmp = FLOAT_ZERO; 5052 break; 5053 } 5054 /* Req 2 is the Smart Volume Setting req. */ 5055 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 5056 ca0132_effects[idx].reqs[2], tmp); 5057 return 1; 5058 } 5059 5060 /* Sound Blaster Z EQ preset controls */ 5061 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol, 5062 struct snd_ctl_elem_info *uinfo) 5063 { 5064 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 5065 5066 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5067 uinfo->count = 1; 5068 uinfo->value.enumerated.items = items; 5069 if (uinfo->value.enumerated.item >= items) 5070 uinfo->value.enumerated.item = items - 1; 5071 strcpy(uinfo->value.enumerated.name, 5072 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name); 5073 return 0; 5074 } 5075 5076 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol, 5077 struct snd_ctl_elem_value *ucontrol) 5078 { 5079 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5080 struct ca0132_spec *spec = codec->spec; 5081 5082 ucontrol->value.enumerated.item[0] = spec->eq_preset_val; 5083 return 0; 5084 } 5085 5086 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol, 5087 struct snd_ctl_elem_value *ucontrol) 5088 { 5089 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5090 struct ca0132_spec *spec = codec->spec; 5091 int i, err = 0; 5092 int sel = ucontrol->value.enumerated.item[0]; 5093 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 5094 5095 if (sel >= items) 5096 return 0; 5097 5098 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel, 5099 ca0132_alt_eq_presets[sel].name); 5100 /* 5101 * Idx 0 is default. 5102 * Default needs to qualify with CrystalVoice state. 5103 */ 5104 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) { 5105 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid, 5106 ca0132_alt_eq_enum.reqs[i], 5107 ca0132_alt_eq_presets[sel].vals[i]); 5108 if (err < 0) 5109 break; 5110 } 5111 5112 if (err >= 0) 5113 spec->eq_preset_val = sel; 5114 5115 return 1; 5116 } 5117 5118 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol, 5119 struct snd_ctl_elem_info *uinfo) 5120 { 5121 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets); 5122 5123 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5124 uinfo->count = 1; 5125 uinfo->value.enumerated.items = items; 5126 if (uinfo->value.enumerated.item >= items) 5127 uinfo->value.enumerated.item = items - 1; 5128 strcpy(uinfo->value.enumerated.name, 5129 ca0132_voicefx_presets[uinfo->value.enumerated.item].name); 5130 return 0; 5131 } 5132 5133 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol, 5134 struct snd_ctl_elem_value *ucontrol) 5135 { 5136 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5137 struct ca0132_spec *spec = codec->spec; 5138 5139 ucontrol->value.enumerated.item[0] = spec->voicefx_val; 5140 return 0; 5141 } 5142 5143 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol, 5144 struct snd_ctl_elem_value *ucontrol) 5145 { 5146 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5147 struct ca0132_spec *spec = codec->spec; 5148 int i, err = 0; 5149 int sel = ucontrol->value.enumerated.item[0]; 5150 5151 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets)) 5152 return 0; 5153 5154 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n", 5155 sel, ca0132_voicefx_presets[sel].name); 5156 5157 /* 5158 * Idx 0 is default. 5159 * Default needs to qualify with CrystalVoice state. 5160 */ 5161 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) { 5162 err = dspio_set_uint_param(codec, ca0132_voicefx.mid, 5163 ca0132_voicefx.reqs[i], 5164 ca0132_voicefx_presets[sel].vals[i]); 5165 if (err < 0) 5166 break; 5167 } 5168 5169 if (err >= 0) { 5170 spec->voicefx_val = sel; 5171 /* enable voice fx */ 5172 ca0132_voicefx_set(codec, (sel ? 1 : 0)); 5173 } 5174 5175 return 1; 5176 } 5177 5178 static int ca0132_switch_get(struct snd_kcontrol *kcontrol, 5179 struct snd_ctl_elem_value *ucontrol) 5180 { 5181 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5182 struct ca0132_spec *spec = codec->spec; 5183 hda_nid_t nid = get_amp_nid(kcontrol); 5184 int ch = get_amp_channels(kcontrol); 5185 long *valp = ucontrol->value.integer.value; 5186 5187 /* vnode */ 5188 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 5189 if (ch & 1) { 5190 *valp = spec->vnode_lswitch[nid - VNODE_START_NID]; 5191 valp++; 5192 } 5193 if (ch & 2) { 5194 *valp = spec->vnode_rswitch[nid - VNODE_START_NID]; 5195 valp++; 5196 } 5197 return 0; 5198 } 5199 5200 /* effects, include PE and CrystalVoice */ 5201 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) { 5202 *valp = spec->effects_switch[nid - EFFECT_START_NID]; 5203 return 0; 5204 } 5205 5206 /* mic boost */ 5207 if (nid == spec->input_pins[0]) { 5208 *valp = spec->cur_mic_boost; 5209 return 0; 5210 } 5211 5212 return 0; 5213 } 5214 5215 static int ca0132_switch_put(struct snd_kcontrol *kcontrol, 5216 struct snd_ctl_elem_value *ucontrol) 5217 { 5218 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5219 struct ca0132_spec *spec = codec->spec; 5220 hda_nid_t nid = get_amp_nid(kcontrol); 5221 int ch = get_amp_channels(kcontrol); 5222 long *valp = ucontrol->value.integer.value; 5223 int changed = 1; 5224 5225 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n", 5226 nid, *valp); 5227 5228 snd_hda_power_up(codec); 5229 /* vnode */ 5230 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 5231 if (ch & 1) { 5232 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp; 5233 valp++; 5234 } 5235 if (ch & 2) { 5236 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp; 5237 valp++; 5238 } 5239 changed = ca0132_vnode_switch_set(kcontrol, ucontrol); 5240 goto exit; 5241 } 5242 5243 /* PE */ 5244 if (nid == PLAY_ENHANCEMENT) { 5245 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 5246 changed = ca0132_pe_switch_set(codec); 5247 goto exit; 5248 } 5249 5250 /* CrystalVoice */ 5251 if (nid == CRYSTAL_VOICE) { 5252 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 5253 changed = ca0132_cvoice_switch_set(codec); 5254 goto exit; 5255 } 5256 5257 /* out and in effects */ 5258 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) || 5259 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) { 5260 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 5261 changed = ca0132_effects_set(codec, nid, *valp); 5262 goto exit; 5263 } 5264 5265 /* mic boost */ 5266 if (nid == spec->input_pins[0]) { 5267 spec->cur_mic_boost = *valp; 5268 if (spec->use_alt_functions) { 5269 if (spec->in_enum_val != REAR_LINE_IN) 5270 changed = ca0132_mic_boost_set(codec, *valp); 5271 } else { 5272 /* Mic boost does not apply to Digital Mic */ 5273 if (spec->cur_mic_type != DIGITAL_MIC) 5274 changed = ca0132_mic_boost_set(codec, *valp); 5275 } 5276 5277 goto exit; 5278 } 5279 5280 exit: 5281 snd_hda_power_down(codec); 5282 return changed; 5283 } 5284 5285 /* 5286 * Volume related 5287 */ 5288 /* 5289 * Sets the internal DSP decibel level to match the DAC for output, and the 5290 * ADC for input. Currently only the SBZ sets dsp capture volume level, and 5291 * all alternative codecs set DSP playback volume. 5292 */ 5293 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid) 5294 { 5295 struct ca0132_spec *spec = codec->spec; 5296 unsigned int dsp_dir; 5297 unsigned int lookup_val; 5298 5299 if (nid == VNID_SPK) 5300 dsp_dir = DSP_VOL_OUT; 5301 else 5302 dsp_dir = DSP_VOL_IN; 5303 5304 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID]; 5305 5306 dspio_set_uint_param(codec, 5307 ca0132_alt_vol_ctls[dsp_dir].mid, 5308 ca0132_alt_vol_ctls[dsp_dir].reqs[0], 5309 float_vol_db_lookup[lookup_val]); 5310 5311 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID]; 5312 5313 dspio_set_uint_param(codec, 5314 ca0132_alt_vol_ctls[dsp_dir].mid, 5315 ca0132_alt_vol_ctls[dsp_dir].reqs[1], 5316 float_vol_db_lookup[lookup_val]); 5317 5318 dspio_set_uint_param(codec, 5319 ca0132_alt_vol_ctls[dsp_dir].mid, 5320 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO); 5321 } 5322 5323 static int ca0132_volume_info(struct snd_kcontrol *kcontrol, 5324 struct snd_ctl_elem_info *uinfo) 5325 { 5326 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5327 struct ca0132_spec *spec = codec->spec; 5328 hda_nid_t nid = get_amp_nid(kcontrol); 5329 int ch = get_amp_channels(kcontrol); 5330 int dir = get_amp_direction(kcontrol); 5331 unsigned long pval; 5332 int err; 5333 5334 switch (nid) { 5335 case VNID_SPK: 5336 /* follow shared_out info */ 5337 nid = spec->shared_out_nid; 5338 mutex_lock(&codec->control_mutex); 5339 pval = kcontrol->private_value; 5340 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 5341 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 5342 kcontrol->private_value = pval; 5343 mutex_unlock(&codec->control_mutex); 5344 break; 5345 case VNID_MIC: 5346 /* follow shared_mic info */ 5347 nid = spec->shared_mic_nid; 5348 mutex_lock(&codec->control_mutex); 5349 pval = kcontrol->private_value; 5350 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 5351 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 5352 kcontrol->private_value = pval; 5353 mutex_unlock(&codec->control_mutex); 5354 break; 5355 default: 5356 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 5357 } 5358 return err; 5359 } 5360 5361 static int ca0132_volume_get(struct snd_kcontrol *kcontrol, 5362 struct snd_ctl_elem_value *ucontrol) 5363 { 5364 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5365 struct ca0132_spec *spec = codec->spec; 5366 hda_nid_t nid = get_amp_nid(kcontrol); 5367 int ch = get_amp_channels(kcontrol); 5368 long *valp = ucontrol->value.integer.value; 5369 5370 /* store the left and right volume */ 5371 if (ch & 1) { 5372 *valp = spec->vnode_lvol[nid - VNODE_START_NID]; 5373 valp++; 5374 } 5375 if (ch & 2) { 5376 *valp = spec->vnode_rvol[nid - VNODE_START_NID]; 5377 valp++; 5378 } 5379 return 0; 5380 } 5381 5382 static int ca0132_volume_put(struct snd_kcontrol *kcontrol, 5383 struct snd_ctl_elem_value *ucontrol) 5384 { 5385 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5386 struct ca0132_spec *spec = codec->spec; 5387 hda_nid_t nid = get_amp_nid(kcontrol); 5388 int ch = get_amp_channels(kcontrol); 5389 long *valp = ucontrol->value.integer.value; 5390 hda_nid_t shared_nid = 0; 5391 bool effective; 5392 int changed = 1; 5393 5394 /* store the left and right volume */ 5395 if (ch & 1) { 5396 spec->vnode_lvol[nid - VNODE_START_NID] = *valp; 5397 valp++; 5398 } 5399 if (ch & 2) { 5400 spec->vnode_rvol[nid - VNODE_START_NID] = *valp; 5401 valp++; 5402 } 5403 5404 /* if effective conditions, then update hw immediately. */ 5405 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 5406 if (effective) { 5407 int dir = get_amp_direction(kcontrol); 5408 unsigned long pval; 5409 5410 snd_hda_power_up(codec); 5411 mutex_lock(&codec->control_mutex); 5412 pval = kcontrol->private_value; 5413 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 5414 0, dir); 5415 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 5416 kcontrol->private_value = pval; 5417 mutex_unlock(&codec->control_mutex); 5418 snd_hda_power_down(codec); 5419 } 5420 5421 return changed; 5422 } 5423 5424 /* 5425 * This function is the same as the one above, because using an if statement 5426 * inside of the above volume control for the DSP volume would cause too much 5427 * lag. This is a lot more smooth. 5428 */ 5429 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol, 5430 struct snd_ctl_elem_value *ucontrol) 5431 { 5432 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5433 struct ca0132_spec *spec = codec->spec; 5434 hda_nid_t nid = get_amp_nid(kcontrol); 5435 int ch = get_amp_channels(kcontrol); 5436 long *valp = ucontrol->value.integer.value; 5437 hda_nid_t vnid = 0; 5438 int changed = 1; 5439 5440 switch (nid) { 5441 case 0x02: 5442 vnid = VNID_SPK; 5443 break; 5444 case 0x07: 5445 vnid = VNID_MIC; 5446 break; 5447 } 5448 5449 /* store the left and right volume */ 5450 if (ch & 1) { 5451 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp; 5452 valp++; 5453 } 5454 if (ch & 2) { 5455 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp; 5456 valp++; 5457 } 5458 5459 snd_hda_power_up(codec); 5460 ca0132_alt_dsp_volume_put(codec, vnid); 5461 mutex_lock(&codec->control_mutex); 5462 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 5463 mutex_unlock(&codec->control_mutex); 5464 snd_hda_power_down(codec); 5465 5466 return changed; 5467 } 5468 5469 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag, 5470 unsigned int size, unsigned int __user *tlv) 5471 { 5472 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5473 struct ca0132_spec *spec = codec->spec; 5474 hda_nid_t nid = get_amp_nid(kcontrol); 5475 int ch = get_amp_channels(kcontrol); 5476 int dir = get_amp_direction(kcontrol); 5477 unsigned long pval; 5478 int err; 5479 5480 switch (nid) { 5481 case VNID_SPK: 5482 /* follow shared_out tlv */ 5483 nid = spec->shared_out_nid; 5484 mutex_lock(&codec->control_mutex); 5485 pval = kcontrol->private_value; 5486 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 5487 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 5488 kcontrol->private_value = pval; 5489 mutex_unlock(&codec->control_mutex); 5490 break; 5491 case VNID_MIC: 5492 /* follow shared_mic tlv */ 5493 nid = spec->shared_mic_nid; 5494 mutex_lock(&codec->control_mutex); 5495 pval = kcontrol->private_value; 5496 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 5497 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 5498 kcontrol->private_value = pval; 5499 mutex_unlock(&codec->control_mutex); 5500 break; 5501 default: 5502 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 5503 } 5504 return err; 5505 } 5506 5507 /* Add volume slider control for effect level */ 5508 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid, 5509 const char *pfx, int dir) 5510 { 5511 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5512 int type = dir ? HDA_INPUT : HDA_OUTPUT; 5513 struct snd_kcontrol_new knew = 5514 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 5515 5516 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]); 5517 5518 knew.tlv.c = 0; 5519 knew.tlv.p = 0; 5520 5521 switch (nid) { 5522 case XBASS_XOVER: 5523 knew.info = ca0132_alt_xbass_xover_slider_info; 5524 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 5525 knew.put = ca0132_alt_xbass_xover_slider_put; 5526 break; 5527 default: 5528 knew.info = ca0132_alt_effect_slider_info; 5529 knew.get = ca0132_alt_slider_ctl_get; 5530 knew.put = ca0132_alt_effect_slider_put; 5531 knew.private_value = 5532 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 5533 break; 5534 } 5535 5536 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 5537 } 5538 5539 /* 5540 * Added FX: prefix for the alternative codecs, because otherwise the surround 5541 * effect would conflict with the Surround sound volume control. Also seems more 5542 * clear as to what the switches do. Left alone for others. 5543 */ 5544 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid, 5545 const char *pfx, int dir) 5546 { 5547 struct ca0132_spec *spec = codec->spec; 5548 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5549 int type = dir ? HDA_INPUT : HDA_OUTPUT; 5550 struct snd_kcontrol_new knew = 5551 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type); 5552 /* If using alt_controls, add FX: prefix. But, don't add FX: 5553 * prefix to OutFX or InFX enable controls. 5554 */ 5555 if ((spec->use_alt_controls) && (nid <= IN_EFFECT_END_NID)) 5556 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]); 5557 else 5558 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]); 5559 5560 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 5561 } 5562 5563 static int add_voicefx(struct hda_codec *codec) 5564 { 5565 struct snd_kcontrol_new knew = 5566 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name, 5567 VOICEFX, 1, 0, HDA_INPUT); 5568 knew.info = ca0132_voicefx_info; 5569 knew.get = ca0132_voicefx_get; 5570 knew.put = ca0132_voicefx_put; 5571 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec)); 5572 } 5573 5574 /* Create the EQ Preset control */ 5575 static int add_ca0132_alt_eq_presets(struct hda_codec *codec) 5576 { 5577 struct snd_kcontrol_new knew = 5578 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name, 5579 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT); 5580 knew.info = ca0132_alt_eq_preset_info; 5581 knew.get = ca0132_alt_eq_preset_get; 5582 knew.put = ca0132_alt_eq_preset_put; 5583 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM, 5584 snd_ctl_new1(&knew, codec)); 5585 } 5586 5587 /* 5588 * Add enumerated control for the three different settings of the smart volume 5589 * output effect. Normal just uses the slider value, and loud and night are 5590 * their own things that ignore that value. 5591 */ 5592 static int ca0132_alt_add_svm_enum(struct hda_codec *codec) 5593 { 5594 struct snd_kcontrol_new knew = 5595 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting", 5596 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT); 5597 knew.info = ca0132_alt_svm_setting_info; 5598 knew.get = ca0132_alt_svm_setting_get; 5599 knew.put = ca0132_alt_svm_setting_put; 5600 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM, 5601 snd_ctl_new1(&knew, codec)); 5602 5603 } 5604 5605 /* 5606 * Create an Output Select enumerated control for codecs with surround 5607 * out capabilities. 5608 */ 5609 static int ca0132_alt_add_output_enum(struct hda_codec *codec) 5610 { 5611 struct snd_kcontrol_new knew = 5612 HDA_CODEC_MUTE_MONO("Output Select", 5613 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT); 5614 knew.info = ca0132_alt_output_select_get_info; 5615 knew.get = ca0132_alt_output_select_get; 5616 knew.put = ca0132_alt_output_select_put; 5617 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM, 5618 snd_ctl_new1(&knew, codec)); 5619 } 5620 5621 /* 5622 * Create an Input Source enumerated control for the alternate ca0132 codecs 5623 * because the front microphone has no auto-detect, and Line-in has to be set 5624 * somehow. 5625 */ 5626 static int ca0132_alt_add_input_enum(struct hda_codec *codec) 5627 { 5628 struct snd_kcontrol_new knew = 5629 HDA_CODEC_MUTE_MONO("Input Source", 5630 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT); 5631 knew.info = ca0132_alt_input_source_info; 5632 knew.get = ca0132_alt_input_source_get; 5633 knew.put = ca0132_alt_input_source_put; 5634 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM, 5635 snd_ctl_new1(&knew, codec)); 5636 } 5637 5638 /* 5639 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds 5640 * more control than the original mic boost, which is either full 30dB or off. 5641 */ 5642 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec) 5643 { 5644 struct snd_kcontrol_new knew = 5645 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch", 5646 MIC_BOOST_ENUM, 1, 0, HDA_INPUT); 5647 knew.info = ca0132_alt_mic_boost_info; 5648 knew.get = ca0132_alt_mic_boost_get; 5649 knew.put = ca0132_alt_mic_boost_put; 5650 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM, 5651 snd_ctl_new1(&knew, codec)); 5652 5653 } 5654 5655 /* 5656 * Need to create slave controls for the alternate codecs that have surround 5657 * capabilities. 5658 */ 5659 static const char * const ca0132_alt_slave_pfxs[] = { 5660 "Front", "Surround", "Center", "LFE", NULL, 5661 }; 5662 5663 /* 5664 * Also need special channel map, because the default one is incorrect. 5665 * I think this has to do with the pin for rear surround being 0x11, 5666 * and the center/lfe being 0x10. Usually the pin order is the opposite. 5667 */ 5668 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = { 5669 { .channels = 2, 5670 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } }, 5671 { .channels = 4, 5672 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 5673 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 5674 { .channels = 6, 5675 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 5676 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE, 5677 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 5678 { } 5679 }; 5680 5681 /* Add the correct chmap for streams with 6 channels. */ 5682 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec) 5683 { 5684 int err = 0; 5685 struct hda_pcm *pcm; 5686 5687 list_for_each_entry(pcm, &codec->pcm_list_head, list) { 5688 struct hda_pcm_stream *hinfo = 5689 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 5690 struct snd_pcm_chmap *chmap; 5691 const struct snd_pcm_chmap_elem *elem; 5692 5693 elem = ca0132_alt_chmaps; 5694 if (hinfo->channels_max == 6) { 5695 err = snd_pcm_add_chmap_ctls(pcm->pcm, 5696 SNDRV_PCM_STREAM_PLAYBACK, 5697 elem, hinfo->channels_max, 0, &chmap); 5698 if (err < 0) 5699 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!"); 5700 } 5701 } 5702 } 5703 5704 /* 5705 * When changing Node IDs for Mixer Controls below, make sure to update 5706 * Node IDs in ca0132_config() as well. 5707 */ 5708 static const struct snd_kcontrol_new ca0132_mixer[] = { 5709 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT), 5710 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT), 5711 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 5712 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 5713 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT), 5714 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT), 5715 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 5716 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 5717 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch", 5718 0x12, 1, HDA_INPUT), 5719 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch", 5720 VNID_HP_SEL, 1, HDA_OUTPUT), 5721 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch", 5722 VNID_AMIC1_SEL, 1, HDA_INPUT), 5723 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 5724 VNID_HP_ASEL, 1, HDA_OUTPUT), 5725 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch", 5726 VNID_AMIC1_ASEL, 1, HDA_INPUT), 5727 { } /* end */ 5728 }; 5729 5730 /* 5731 * SBZ specific control mixer. Removes auto-detect for mic, and adds surround 5732 * controls. Also sets both the Front Playback and Capture Volume controls to 5733 * alt so they set the DSP's decibel level. 5734 */ 5735 static const struct snd_kcontrol_new sbz_mixer[] = { 5736 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 5737 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 5738 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 5739 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 5740 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 5741 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 5742 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 5743 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 5744 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT), 5745 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 5746 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 5747 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 5748 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 5749 VNID_HP_ASEL, 1, HDA_OUTPUT), 5750 { } /* end */ 5751 }; 5752 5753 /* 5754 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture 5755 * because it doesn't set decibel levels for the DSP for capture. 5756 */ 5757 static const struct snd_kcontrol_new r3di_mixer[] = { 5758 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 5759 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 5760 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 5761 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 5762 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 5763 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 5764 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 5765 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 5766 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 5767 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 5768 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 5769 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 5770 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 5771 VNID_HP_ASEL, 1, HDA_OUTPUT), 5772 { } /* end */ 5773 }; 5774 5775 static int ca0132_build_controls(struct hda_codec *codec) 5776 { 5777 struct ca0132_spec *spec = codec->spec; 5778 int i, num_fx, num_sliders; 5779 int err = 0; 5780 5781 /* Add Mixer controls */ 5782 for (i = 0; i < spec->num_mixers; i++) { 5783 err = snd_hda_add_new_ctls(codec, spec->mixers[i]); 5784 if (err < 0) 5785 return err; 5786 } 5787 /* Setup vmaster with surround slaves for desktop ca0132 devices */ 5788 if (spec->use_alt_functions) { 5789 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT, 5790 spec->tlv); 5791 snd_hda_add_vmaster(codec, "Master Playback Volume", 5792 spec->tlv, ca0132_alt_slave_pfxs, 5793 "Playback Volume"); 5794 err = __snd_hda_add_vmaster(codec, "Master Playback Switch", 5795 NULL, ca0132_alt_slave_pfxs, 5796 "Playback Switch", 5797 true, &spec->vmaster_mute.sw_kctl); 5798 5799 } 5800 5801 /* Add in and out effects controls. 5802 * VoiceFX, PE and CrystalVoice are added separately. 5803 */ 5804 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 5805 for (i = 0; i < num_fx; i++) { 5806 /* SBZ breaks if Echo Cancellation is used */ 5807 if (spec->quirk == QUIRK_SBZ) { 5808 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID + 5809 OUT_EFFECTS_COUNT)) 5810 continue; 5811 } 5812 5813 err = add_fx_switch(codec, ca0132_effects[i].nid, 5814 ca0132_effects[i].name, 5815 ca0132_effects[i].direct); 5816 if (err < 0) 5817 return err; 5818 } 5819 /* 5820 * If codec has use_alt_controls set to true, add effect level sliders, 5821 * EQ presets, and Smart Volume presets. Also, change names to add FX 5822 * prefix, and change PlayEnhancement and CrystalVoice to match. 5823 */ 5824 if (spec->use_alt_controls) { 5825 ca0132_alt_add_svm_enum(codec); 5826 add_ca0132_alt_eq_presets(codec); 5827 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 5828 "Enable OutFX", 0); 5829 if (err < 0) 5830 return err; 5831 5832 err = add_fx_switch(codec, CRYSTAL_VOICE, 5833 "Enable InFX", 1); 5834 if (err < 0) 5835 return err; 5836 5837 num_sliders = OUT_EFFECTS_COUNT - 1; 5838 for (i = 0; i < num_sliders; i++) { 5839 err = ca0132_alt_add_effect_slider(codec, 5840 ca0132_effects[i].nid, 5841 ca0132_effects[i].name, 5842 ca0132_effects[i].direct); 5843 if (err < 0) 5844 return err; 5845 } 5846 5847 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER, 5848 "X-Bass Crossover", EFX_DIR_OUT); 5849 5850 if (err < 0) 5851 return err; 5852 } else { 5853 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 5854 "PlayEnhancement", 0); 5855 if (err < 0) 5856 return err; 5857 5858 err = add_fx_switch(codec, CRYSTAL_VOICE, 5859 "CrystalVoice", 1); 5860 if (err < 0) 5861 return err; 5862 } 5863 add_voicefx(codec); 5864 5865 /* 5866 * If the codec uses alt_functions, you need the enumerated controls 5867 * to select the new outputs and inputs, plus add the new mic boost 5868 * setting control. 5869 */ 5870 if (spec->use_alt_functions) { 5871 ca0132_alt_add_output_enum(codec); 5872 ca0132_alt_add_input_enum(codec); 5873 ca0132_alt_add_mic_boost_enum(codec); 5874 } 5875 #ifdef ENABLE_TUNING_CONTROLS 5876 add_tuning_ctls(codec); 5877 #endif 5878 5879 err = snd_hda_jack_add_kctls(codec, &spec->autocfg); 5880 if (err < 0) 5881 return err; 5882 5883 if (spec->dig_out) { 5884 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 5885 spec->dig_out); 5886 if (err < 0) 5887 return err; 5888 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout); 5889 if (err < 0) 5890 return err; 5891 /* spec->multiout.share_spdif = 1; */ 5892 } 5893 5894 if (spec->dig_in) { 5895 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 5896 if (err < 0) 5897 return err; 5898 } 5899 5900 if (spec->use_alt_functions) 5901 ca0132_alt_add_chmap_ctls(codec); 5902 5903 return 0; 5904 } 5905 5906 /* 5907 * PCM 5908 */ 5909 static const struct hda_pcm_stream ca0132_pcm_analog_playback = { 5910 .substreams = 1, 5911 .channels_min = 2, 5912 .channels_max = 6, 5913 .ops = { 5914 .prepare = ca0132_playback_pcm_prepare, 5915 .cleanup = ca0132_playback_pcm_cleanup, 5916 .get_delay = ca0132_playback_pcm_delay, 5917 }, 5918 }; 5919 5920 static const struct hda_pcm_stream ca0132_pcm_analog_capture = { 5921 .substreams = 1, 5922 .channels_min = 2, 5923 .channels_max = 2, 5924 .ops = { 5925 .prepare = ca0132_capture_pcm_prepare, 5926 .cleanup = ca0132_capture_pcm_cleanup, 5927 .get_delay = ca0132_capture_pcm_delay, 5928 }, 5929 }; 5930 5931 static const struct hda_pcm_stream ca0132_pcm_digital_playback = { 5932 .substreams = 1, 5933 .channels_min = 2, 5934 .channels_max = 2, 5935 .ops = { 5936 .open = ca0132_dig_playback_pcm_open, 5937 .close = ca0132_dig_playback_pcm_close, 5938 .prepare = ca0132_dig_playback_pcm_prepare, 5939 .cleanup = ca0132_dig_playback_pcm_cleanup 5940 }, 5941 }; 5942 5943 static const struct hda_pcm_stream ca0132_pcm_digital_capture = { 5944 .substreams = 1, 5945 .channels_min = 2, 5946 .channels_max = 2, 5947 }; 5948 5949 static int ca0132_build_pcms(struct hda_codec *codec) 5950 { 5951 struct ca0132_spec *spec = codec->spec; 5952 struct hda_pcm *info; 5953 5954 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog"); 5955 if (!info) 5956 return -ENOMEM; 5957 if (spec->use_alt_functions) { 5958 info->own_chmap = true; 5959 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap 5960 = ca0132_alt_chmaps; 5961 } 5962 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback; 5963 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0]; 5964 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max = 5965 spec->multiout.max_channels; 5966 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 5967 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 5968 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 5969 5970 /* With the DSP enabled, desktops don't use this ADC. */ 5971 if (!spec->use_alt_functions) { 5972 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2"); 5973 if (!info) 5974 return -ENOMEM; 5975 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 5976 ca0132_pcm_analog_capture; 5977 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 5978 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1]; 5979 } 5980 5981 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear"); 5982 if (!info) 5983 return -ENOMEM; 5984 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 5985 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 5986 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2]; 5987 5988 if (!spec->dig_out && !spec->dig_in) 5989 return 0; 5990 5991 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 5992 if (!info) 5993 return -ENOMEM; 5994 info->pcm_type = HDA_PCM_TYPE_SPDIF; 5995 if (spec->dig_out) { 5996 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 5997 ca0132_pcm_digital_playback; 5998 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 5999 } 6000 if (spec->dig_in) { 6001 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 6002 ca0132_pcm_digital_capture; 6003 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 6004 } 6005 6006 return 0; 6007 } 6008 6009 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac) 6010 { 6011 if (pin) { 6012 snd_hda_set_pin_ctl(codec, pin, PIN_HP); 6013 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 6014 snd_hda_codec_write(codec, pin, 0, 6015 AC_VERB_SET_AMP_GAIN_MUTE, 6016 AMP_OUT_UNMUTE); 6017 } 6018 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP)) 6019 snd_hda_codec_write(codec, dac, 0, 6020 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO); 6021 } 6022 6023 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc) 6024 { 6025 if (pin) { 6026 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80); 6027 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP) 6028 snd_hda_codec_write(codec, pin, 0, 6029 AC_VERB_SET_AMP_GAIN_MUTE, 6030 AMP_IN_UNMUTE(0)); 6031 } 6032 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) { 6033 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE, 6034 AMP_IN_UNMUTE(0)); 6035 6036 /* init to 0 dB and unmute. */ 6037 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 6038 HDA_AMP_VOLMASK, 0x5a); 6039 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 6040 HDA_AMP_MUTE, 0); 6041 } 6042 } 6043 6044 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir) 6045 { 6046 unsigned int caps; 6047 6048 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ? 6049 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP); 6050 snd_hda_override_amp_caps(codec, nid, dir, caps); 6051 } 6052 6053 /* 6054 * Switch between Digital built-in mic and analog mic. 6055 */ 6056 static void ca0132_set_dmic(struct hda_codec *codec, int enable) 6057 { 6058 struct ca0132_spec *spec = codec->spec; 6059 unsigned int tmp; 6060 u8 val; 6061 unsigned int oldval; 6062 6063 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable); 6064 6065 oldval = stop_mic1(codec); 6066 ca0132_set_vipsource(codec, 0); 6067 if (enable) { 6068 /* set DMic input as 2-ch */ 6069 tmp = FLOAT_TWO; 6070 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 6071 6072 val = spec->dmic_ctl; 6073 val |= 0x80; 6074 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6075 VENDOR_CHIPIO_DMIC_CTL_SET, val); 6076 6077 if (!(spec->dmic_ctl & 0x20)) 6078 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1); 6079 } else { 6080 /* set AMic input as mono */ 6081 tmp = FLOAT_ONE; 6082 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 6083 6084 val = spec->dmic_ctl; 6085 /* clear bit7 and bit5 to disable dmic */ 6086 val &= 0x5f; 6087 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6088 VENDOR_CHIPIO_DMIC_CTL_SET, val); 6089 6090 if (!(spec->dmic_ctl & 0x20)) 6091 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0); 6092 } 6093 ca0132_set_vipsource(codec, 1); 6094 resume_mic1(codec, oldval); 6095 } 6096 6097 /* 6098 * Initialization for Digital Mic. 6099 */ 6100 static void ca0132_init_dmic(struct hda_codec *codec) 6101 { 6102 struct ca0132_spec *spec = codec->spec; 6103 u8 val; 6104 6105 /* Setup Digital Mic here, but don't enable. 6106 * Enable based on jack detect. 6107 */ 6108 6109 /* MCLK uses MPIO1, set to enable. 6110 * Bit 2-0: MPIO select 6111 * Bit 3: set to disable 6112 * Bit 7-4: reserved 6113 */ 6114 val = 0x01; 6115 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6116 VENDOR_CHIPIO_DMIC_MCLK_SET, val); 6117 6118 /* Data1 uses MPIO3. Data2 not use 6119 * Bit 2-0: Data1 MPIO select 6120 * Bit 3: set disable Data1 6121 * Bit 6-4: Data2 MPIO select 6122 * Bit 7: set disable Data2 6123 */ 6124 val = 0x83; 6125 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6126 VENDOR_CHIPIO_DMIC_PIN_SET, val); 6127 6128 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first. 6129 * Bit 3-0: Channel mask 6130 * Bit 4: set for 48KHz, clear for 32KHz 6131 * Bit 5: mode 6132 * Bit 6: set to select Data2, clear for Data1 6133 * Bit 7: set to enable DMic, clear for AMic 6134 */ 6135 if (spec->quirk == QUIRK_ALIENWARE_M17XR4) 6136 val = 0x33; 6137 else 6138 val = 0x23; 6139 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */ 6140 spec->dmic_ctl = val; 6141 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6142 VENDOR_CHIPIO_DMIC_CTL_SET, val); 6143 } 6144 6145 /* 6146 * Initialization for Analog Mic 2 6147 */ 6148 static void ca0132_init_analog_mic2(struct hda_codec *codec) 6149 { 6150 struct ca0132_spec *spec = codec->spec; 6151 6152 mutex_lock(&spec->chipio_mutex); 6153 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6154 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); 6155 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6156 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 6157 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6158 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 6159 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6160 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D); 6161 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6162 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 6163 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6164 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 6165 mutex_unlock(&spec->chipio_mutex); 6166 } 6167 6168 static void ca0132_refresh_widget_caps(struct hda_codec *codec) 6169 { 6170 struct ca0132_spec *spec = codec->spec; 6171 int i; 6172 6173 codec_dbg(codec, "ca0132_refresh_widget_caps.\n"); 6174 snd_hda_codec_update_widgets(codec); 6175 6176 for (i = 0; i < spec->multiout.num_dacs; i++) 6177 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT); 6178 6179 for (i = 0; i < spec->num_outputs; i++) 6180 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT); 6181 6182 for (i = 0; i < spec->num_inputs; i++) { 6183 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT); 6184 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT); 6185 } 6186 } 6187 6188 /* 6189 * Recon3Di r3di_setup_defaults sub functions. 6190 */ 6191 6192 static void r3di_dsp_scp_startup(struct hda_codec *codec) 6193 { 6194 unsigned int tmp; 6195 6196 tmp = 0x00000000; 6197 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp); 6198 6199 tmp = 0x00000001; 6200 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp); 6201 6202 tmp = 0x00000004; 6203 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 6204 6205 tmp = 0x00000005; 6206 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 6207 6208 tmp = 0x00000000; 6209 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 6210 6211 } 6212 6213 static void r3di_dsp_initial_mic_setup(struct hda_codec *codec) 6214 { 6215 unsigned int tmp; 6216 6217 /* Mic 1 Setup */ 6218 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 6219 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 6220 /* This ConnPointID is unique to Recon3Di. Haven't seen it elsewhere */ 6221 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 6222 tmp = FLOAT_ONE; 6223 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 6224 6225 /* Mic 2 Setup, even though it isn't connected on SBZ */ 6226 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000); 6227 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000); 6228 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 6229 tmp = FLOAT_ZERO; 6230 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 6231 } 6232 6233 /* 6234 * Initialize Sound Blaster Z analog microphones. 6235 */ 6236 static void sbz_init_analog_mics(struct hda_codec *codec) 6237 { 6238 unsigned int tmp; 6239 6240 /* Mic 1 Setup */ 6241 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 6242 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 6243 tmp = FLOAT_THREE; 6244 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 6245 6246 /* Mic 2 Setup, even though it isn't connected on SBZ */ 6247 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000); 6248 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000); 6249 tmp = FLOAT_ZERO; 6250 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 6251 6252 } 6253 6254 /* 6255 * Sets the source of stream 0x14 to connpointID 0x48, and the destination 6256 * connpointID to 0x91. If this isn't done, the destination is 0x71, and 6257 * you get no sound. I'm guessing this has to do with the Sound Blaster Z 6258 * having an updated DAC, which changes the destination to that DAC. 6259 */ 6260 static void sbz_connect_streams(struct hda_codec *codec) 6261 { 6262 struct ca0132_spec *spec = codec->spec; 6263 6264 mutex_lock(&spec->chipio_mutex); 6265 6266 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n"); 6267 6268 chipio_set_stream_channels(codec, 0x0C, 6); 6269 chipio_set_stream_control(codec, 0x0C, 1); 6270 6271 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */ 6272 chipio_write_no_mutex(codec, 0x18a020, 0x00000043); 6273 6274 /* Setup stream 0x14 with it's source and destination points */ 6275 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91); 6276 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000); 6277 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000); 6278 chipio_set_stream_channels(codec, 0x14, 2); 6279 chipio_set_stream_control(codec, 0x14, 1); 6280 6281 codec_dbg(codec, "Connect Streams exited, mutex released.\n"); 6282 6283 mutex_unlock(&spec->chipio_mutex); 6284 6285 } 6286 6287 /* 6288 * Write data through ChipIO to setup proper stream destinations. 6289 * Not sure how it exactly works, but it seems to direct data 6290 * to different destinations. Example is f8 to c0, e0 to c0. 6291 * All I know is, if you don't set these, you get no sound. 6292 */ 6293 static void sbz_chipio_startup_data(struct hda_codec *codec) 6294 { 6295 struct ca0132_spec *spec = codec->spec; 6296 6297 mutex_lock(&spec->chipio_mutex); 6298 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n"); 6299 6300 /* These control audio output */ 6301 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0); 6302 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1); 6303 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6); 6304 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7); 6305 /* Signal to update I think */ 6306 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 6307 6308 chipio_set_stream_channels(codec, 0x0C, 6); 6309 chipio_set_stream_control(codec, 0x0C, 1); 6310 /* No clue what these control */ 6311 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0); 6312 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1); 6313 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2); 6314 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3); 6315 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4); 6316 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5); 6317 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6); 6318 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7); 6319 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8); 6320 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9); 6321 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca); 6322 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb); 6323 6324 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 6325 6326 codec_dbg(codec, "Startup Data exited, mutex released.\n"); 6327 mutex_unlock(&spec->chipio_mutex); 6328 } 6329 6330 /* 6331 * Sound Blaster Z uses these after DSP is loaded. Weird SCP commands 6332 * without a 0x20 source like normal. 6333 */ 6334 static void sbz_dsp_scp_startup(struct hda_codec *codec) 6335 { 6336 unsigned int tmp; 6337 6338 tmp = 0x00000003; 6339 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 6340 6341 tmp = 0x00000000; 6342 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp); 6343 6344 tmp = 0x00000001; 6345 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp); 6346 6347 tmp = 0x00000004; 6348 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 6349 6350 tmp = 0x00000005; 6351 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 6352 6353 tmp = 0x00000000; 6354 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 6355 6356 } 6357 6358 static void sbz_dsp_initial_mic_setup(struct hda_codec *codec) 6359 { 6360 unsigned int tmp; 6361 6362 chipio_set_stream_control(codec, 0x03, 0); 6363 chipio_set_stream_control(codec, 0x04, 0); 6364 6365 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 6366 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 6367 6368 tmp = FLOAT_THREE; 6369 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 6370 6371 chipio_set_stream_control(codec, 0x03, 1); 6372 chipio_set_stream_control(codec, 0x04, 1); 6373 6374 chipio_write(codec, 0x18b098, 0x0000000c); 6375 chipio_write(codec, 0x18b09C, 0x0000000c); 6376 } 6377 6378 /* 6379 * Setup default parameters for DSP 6380 */ 6381 static void ca0132_setup_defaults(struct hda_codec *codec) 6382 { 6383 struct ca0132_spec *spec = codec->spec; 6384 unsigned int tmp; 6385 int num_fx; 6386 int idx, i; 6387 6388 if (spec->dsp_state != DSP_DOWNLOADED) 6389 return; 6390 6391 /* out, in effects + voicefx */ 6392 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 6393 for (idx = 0; idx < num_fx; idx++) { 6394 for (i = 0; i <= ca0132_effects[idx].params; i++) { 6395 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 6396 ca0132_effects[idx].reqs[i], 6397 ca0132_effects[idx].def_vals[i]); 6398 } 6399 } 6400 6401 /*remove DSP headroom*/ 6402 tmp = FLOAT_ZERO; 6403 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 6404 6405 /*set speaker EQ bypass attenuation*/ 6406 dspio_set_uint_param(codec, 0x8f, 0x01, tmp); 6407 6408 /* set AMic1 and AMic2 as mono mic */ 6409 tmp = FLOAT_ONE; 6410 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 6411 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 6412 6413 /* set AMic1 as CrystalVoice input */ 6414 tmp = FLOAT_ONE; 6415 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 6416 6417 /* set WUH source */ 6418 tmp = FLOAT_TWO; 6419 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 6420 } 6421 6422 /* 6423 * Setup default parameters for Recon3Di DSP. 6424 */ 6425 6426 static void r3di_setup_defaults(struct hda_codec *codec) 6427 { 6428 struct ca0132_spec *spec = codec->spec; 6429 unsigned int tmp; 6430 int num_fx; 6431 int idx, i; 6432 6433 if (spec->dsp_state != DSP_DOWNLOADED) 6434 return; 6435 6436 r3di_dsp_scp_startup(codec); 6437 6438 r3di_dsp_initial_mic_setup(codec); 6439 6440 /*remove DSP headroom*/ 6441 tmp = FLOAT_ZERO; 6442 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 6443 6444 /* set WUH source */ 6445 tmp = FLOAT_TWO; 6446 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 6447 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 6448 6449 /* Set speaker source? */ 6450 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 6451 6452 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED); 6453 6454 /* Setup effect defaults */ 6455 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 6456 for (idx = 0; idx < num_fx; idx++) { 6457 for (i = 0; i <= ca0132_effects[idx].params; i++) { 6458 dspio_set_uint_param(codec, 6459 ca0132_effects[idx].mid, 6460 ca0132_effects[idx].reqs[i], 6461 ca0132_effects[idx].def_vals[i]); 6462 } 6463 } 6464 6465 } 6466 6467 /* 6468 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on 6469 * than the Chromebook setup. 6470 */ 6471 static void sbz_setup_defaults(struct hda_codec *codec) 6472 { 6473 struct ca0132_spec *spec = codec->spec; 6474 unsigned int tmp, stream_format; 6475 int num_fx; 6476 int idx, i; 6477 6478 if (spec->dsp_state != DSP_DOWNLOADED) 6479 return; 6480 6481 sbz_dsp_scp_startup(codec); 6482 6483 sbz_init_analog_mics(codec); 6484 6485 sbz_connect_streams(codec); 6486 6487 sbz_chipio_startup_data(codec); 6488 6489 chipio_set_stream_control(codec, 0x03, 1); 6490 chipio_set_stream_control(codec, 0x04, 1); 6491 6492 /* 6493 * Sets internal input loopback to off, used to have a switch to 6494 * enable input loopback, but turned out to be way too buggy. 6495 */ 6496 tmp = FLOAT_ONE; 6497 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 6498 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 6499 6500 /*remove DSP headroom*/ 6501 tmp = FLOAT_ZERO; 6502 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 6503 6504 /* set WUH source */ 6505 tmp = FLOAT_TWO; 6506 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 6507 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 6508 6509 /* Set speaker source? */ 6510 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 6511 6512 sbz_dsp_initial_mic_setup(codec); 6513 6514 6515 /* out, in effects + voicefx */ 6516 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 6517 for (idx = 0; idx < num_fx; idx++) { 6518 for (i = 0; i <= ca0132_effects[idx].params; i++) { 6519 dspio_set_uint_param(codec, 6520 ca0132_effects[idx].mid, 6521 ca0132_effects[idx].reqs[i], 6522 ca0132_effects[idx].def_vals[i]); 6523 } 6524 } 6525 6526 /* 6527 * Have to make a stream to bind the sound output to, otherwise 6528 * you'll get dead audio. Before I did this, it would bind to an 6529 * audio input, and would never work 6530 */ 6531 stream_format = snd_hdac_calc_stream_format(48000, 2, 6532 SNDRV_PCM_FORMAT_S32_LE, 32, 0); 6533 6534 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id, 6535 0, stream_format); 6536 6537 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 6538 6539 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id, 6540 0, stream_format); 6541 6542 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 6543 } 6544 6545 /* 6546 * Initialization of flags in chip 6547 */ 6548 static void ca0132_init_flags(struct hda_codec *codec) 6549 { 6550 struct ca0132_spec *spec = codec->spec; 6551 6552 if (spec->use_alt_functions) { 6553 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1); 6554 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1); 6555 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1); 6556 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1); 6557 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1); 6558 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 6559 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0); 6560 chipio_set_control_flag(codec, 6561 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 6562 chipio_set_control_flag(codec, 6563 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1); 6564 } else { 6565 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 6566 chipio_set_control_flag(codec, 6567 CONTROL_FLAG_PORT_A_COMMON_MODE, 0); 6568 chipio_set_control_flag(codec, 6569 CONTROL_FLAG_PORT_D_COMMON_MODE, 0); 6570 chipio_set_control_flag(codec, 6571 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0); 6572 chipio_set_control_flag(codec, 6573 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 6574 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1); 6575 } 6576 } 6577 6578 /* 6579 * Initialization of parameters in chip 6580 */ 6581 static void ca0132_init_params(struct hda_codec *codec) 6582 { 6583 struct ca0132_spec *spec = codec->spec; 6584 6585 if (spec->use_alt_functions) { 6586 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 6587 chipio_set_conn_rate(codec, 0x0B, SR_48_000); 6588 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0); 6589 chipio_set_control_param(codec, 0, 0); 6590 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 6591 } 6592 6593 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6); 6594 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6); 6595 } 6596 6597 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k) 6598 { 6599 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k); 6600 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k); 6601 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k); 6602 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k); 6603 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k); 6604 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k); 6605 6606 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 6607 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 6608 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 6609 } 6610 6611 static bool ca0132_download_dsp_images(struct hda_codec *codec) 6612 { 6613 bool dsp_loaded = false; 6614 struct ca0132_spec *spec = codec->spec; 6615 const struct dsp_image_seg *dsp_os_image; 6616 const struct firmware *fw_entry; 6617 /* 6618 * Alternate firmwares for different variants. The Recon3Di apparently 6619 * can use the default firmware, but I'll leave the option in case 6620 * it needs it again. 6621 */ 6622 switch (spec->quirk) { 6623 case QUIRK_SBZ: 6624 if (request_firmware(&fw_entry, SBZ_EFX_FILE, 6625 codec->card->dev) != 0) { 6626 codec_dbg(codec, "SBZ alt firmware not detected. "); 6627 spec->alt_firmware_present = false; 6628 } else { 6629 codec_dbg(codec, "Sound Blaster Z firmware selected."); 6630 spec->alt_firmware_present = true; 6631 } 6632 break; 6633 case QUIRK_R3DI: 6634 if (request_firmware(&fw_entry, R3DI_EFX_FILE, 6635 codec->card->dev) != 0) { 6636 codec_dbg(codec, "Recon3Di alt firmware not detected."); 6637 spec->alt_firmware_present = false; 6638 } else { 6639 codec_dbg(codec, "Recon3Di firmware selected."); 6640 spec->alt_firmware_present = true; 6641 } 6642 break; 6643 default: 6644 spec->alt_firmware_present = false; 6645 break; 6646 } 6647 /* 6648 * Use default ctefx.bin if no alt firmware is detected, or if none 6649 * exists for your particular codec. 6650 */ 6651 if (!spec->alt_firmware_present) { 6652 codec_dbg(codec, "Default firmware selected."); 6653 if (request_firmware(&fw_entry, EFX_FILE, 6654 codec->card->dev) != 0) 6655 return false; 6656 } 6657 6658 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data); 6659 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) { 6660 codec_err(codec, "ca0132 DSP load image failed\n"); 6661 goto exit_download; 6662 } 6663 6664 dsp_loaded = dspload_wait_loaded(codec); 6665 6666 exit_download: 6667 release_firmware(fw_entry); 6668 6669 return dsp_loaded; 6670 } 6671 6672 static void ca0132_download_dsp(struct hda_codec *codec) 6673 { 6674 struct ca0132_spec *spec = codec->spec; 6675 6676 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP 6677 return; /* NOP */ 6678 #endif 6679 6680 if (spec->dsp_state == DSP_DOWNLOAD_FAILED) 6681 return; /* don't retry failures */ 6682 6683 chipio_enable_clocks(codec); 6684 if (spec->dsp_state != DSP_DOWNLOADED) { 6685 spec->dsp_state = DSP_DOWNLOADING; 6686 6687 if (!ca0132_download_dsp_images(codec)) 6688 spec->dsp_state = DSP_DOWNLOAD_FAILED; 6689 else 6690 spec->dsp_state = DSP_DOWNLOADED; 6691 } 6692 6693 /* For codecs using alt functions, this is already done earlier */ 6694 if (spec->dsp_state == DSP_DOWNLOADED && (!spec->use_alt_functions)) 6695 ca0132_set_dsp_msr(codec, true); 6696 } 6697 6698 static void ca0132_process_dsp_response(struct hda_codec *codec, 6699 struct hda_jack_callback *callback) 6700 { 6701 struct ca0132_spec *spec = codec->spec; 6702 6703 codec_dbg(codec, "ca0132_process_dsp_response\n"); 6704 if (spec->wait_scp) { 6705 if (dspio_get_response_data(codec) >= 0) 6706 spec->wait_scp = 0; 6707 } 6708 6709 dspio_clear_response_queue(codec); 6710 } 6711 6712 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 6713 { 6714 struct ca0132_spec *spec = codec->spec; 6715 struct hda_jack_tbl *tbl; 6716 6717 /* Delay enabling the HP amp, to let the mic-detection 6718 * state machine run. 6719 */ 6720 cancel_delayed_work_sync(&spec->unsol_hp_work); 6721 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500)); 6722 tbl = snd_hda_jack_tbl_get(codec, cb->nid); 6723 if (tbl) 6724 tbl->block_report = 1; 6725 } 6726 6727 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 6728 { 6729 ca0132_select_mic(codec); 6730 } 6731 6732 static void ca0132_init_unsol(struct hda_codec *codec) 6733 { 6734 struct ca0132_spec *spec = codec->spec; 6735 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback); 6736 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1, 6737 amic_callback); 6738 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP, 6739 ca0132_process_dsp_response); 6740 /* Front headphone jack detection */ 6741 if (spec->use_alt_functions) 6742 snd_hda_jack_detect_enable_callback(codec, 6743 spec->unsol_tag_front_hp, hp_callback); 6744 } 6745 6746 /* 6747 * Verbs tables. 6748 */ 6749 6750 /* Sends before DSP download. */ 6751 static struct hda_verb ca0132_base_init_verbs[] = { 6752 /*enable ct extension*/ 6753 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1}, 6754 {} 6755 }; 6756 6757 /* Send at exit. */ 6758 static struct hda_verb ca0132_base_exit_verbs[] = { 6759 /*set afg to D3*/ 6760 {0x01, AC_VERB_SET_POWER_STATE, 0x03}, 6761 /*disable ct extension*/ 6762 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0}, 6763 {} 6764 }; 6765 6766 /* Other verbs tables. Sends after DSP download. */ 6767 6768 static struct hda_verb ca0132_init_verbs0[] = { 6769 /* chip init verbs */ 6770 {0x15, 0x70D, 0xF0}, 6771 {0x15, 0x70E, 0xFE}, 6772 {0x15, 0x707, 0x75}, 6773 {0x15, 0x707, 0xD3}, 6774 {0x15, 0x707, 0x09}, 6775 {0x15, 0x707, 0x53}, 6776 {0x15, 0x707, 0xD4}, 6777 {0x15, 0x707, 0xEF}, 6778 {0x15, 0x707, 0x75}, 6779 {0x15, 0x707, 0xD3}, 6780 {0x15, 0x707, 0x09}, 6781 {0x15, 0x707, 0x02}, 6782 {0x15, 0x707, 0x37}, 6783 {0x15, 0x707, 0x78}, 6784 {0x15, 0x53C, 0xCE}, 6785 {0x15, 0x575, 0xC9}, 6786 {0x15, 0x53D, 0xCE}, 6787 {0x15, 0x5B7, 0xC9}, 6788 {0x15, 0x70D, 0xE8}, 6789 {0x15, 0x70E, 0xFE}, 6790 {0x15, 0x707, 0x02}, 6791 {0x15, 0x707, 0x68}, 6792 {0x15, 0x707, 0x62}, 6793 {0x15, 0x53A, 0xCE}, 6794 {0x15, 0x546, 0xC9}, 6795 {0x15, 0x53B, 0xCE}, 6796 {0x15, 0x5E8, 0xC9}, 6797 {} 6798 }; 6799 6800 /* Extra init verbs for SBZ */ 6801 static struct hda_verb sbz_init_verbs[] = { 6802 {0x15, 0x70D, 0x20}, 6803 {0x15, 0x70E, 0x19}, 6804 {0x15, 0x707, 0x00}, 6805 {0x15, 0x539, 0xCE}, 6806 {0x15, 0x546, 0xC9}, 6807 {0x15, 0x70D, 0xB7}, 6808 {0x15, 0x70E, 0x09}, 6809 {0x15, 0x707, 0x10}, 6810 {0x15, 0x70D, 0xAF}, 6811 {0x15, 0x70E, 0x09}, 6812 {0x15, 0x707, 0x01}, 6813 {0x15, 0x707, 0x05}, 6814 {0x15, 0x70D, 0x73}, 6815 {0x15, 0x70E, 0x09}, 6816 {0x15, 0x707, 0x14}, 6817 {0x15, 0x6FF, 0xC4}, 6818 {} 6819 }; 6820 6821 static void ca0132_init_chip(struct hda_codec *codec) 6822 { 6823 struct ca0132_spec *spec = codec->spec; 6824 int num_fx; 6825 int i; 6826 unsigned int on; 6827 6828 mutex_init(&spec->chipio_mutex); 6829 6830 spec->cur_out_type = SPEAKER_OUT; 6831 if (!spec->use_alt_functions) 6832 spec->cur_mic_type = DIGITAL_MIC; 6833 else 6834 spec->cur_mic_type = REAR_MIC; 6835 6836 spec->cur_mic_boost = 0; 6837 6838 for (i = 0; i < VNODES_COUNT; i++) { 6839 spec->vnode_lvol[i] = 0x5a; 6840 spec->vnode_rvol[i] = 0x5a; 6841 spec->vnode_lswitch[i] = 0; 6842 spec->vnode_rswitch[i] = 0; 6843 } 6844 6845 /* 6846 * Default states for effects are in ca0132_effects[]. 6847 */ 6848 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 6849 for (i = 0; i < num_fx; i++) { 6850 on = (unsigned int)ca0132_effects[i].reqs[0]; 6851 spec->effects_switch[i] = on ? 1 : 0; 6852 } 6853 /* 6854 * Sets defaults for the effect slider controls, only for alternative 6855 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz. 6856 */ 6857 if (spec->use_alt_controls) { 6858 spec->xbass_xover_freq = 8; 6859 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++) 6860 spec->fx_ctl_val[i] = effect_slider_defaults[i]; 6861 } 6862 6863 spec->voicefx_val = 0; 6864 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1; 6865 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0; 6866 6867 #ifdef ENABLE_TUNING_CONTROLS 6868 ca0132_init_tuning_defaults(codec); 6869 #endif 6870 } 6871 6872 /* 6873 * Recon3Di exit specific commands. 6874 */ 6875 /* prevents popping noise on shutdown */ 6876 static void r3di_gpio_shutdown(struct hda_codec *codec) 6877 { 6878 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00); 6879 } 6880 6881 /* 6882 * Sound Blaster Z exit specific commands. 6883 */ 6884 static void sbz_region2_exit(struct hda_codec *codec) 6885 { 6886 struct ca0132_spec *spec = codec->spec; 6887 unsigned int i; 6888 6889 for (i = 0; i < 4; i++) 6890 writeb(0x0, spec->mem_base + 0x100); 6891 for (i = 0; i < 8; i++) 6892 writeb(0xb3, spec->mem_base + 0x304); 6893 /* 6894 * I believe these are GPIO, with the right most hex digit being the 6895 * gpio pin, and the second digit being on or off. We see this more in 6896 * the input/output select functions. 6897 */ 6898 writew(0x0000, spec->mem_base + 0x320); 6899 writew(0x0001, spec->mem_base + 0x320); 6900 writew(0x0104, spec->mem_base + 0x320); 6901 writew(0x0005, spec->mem_base + 0x320); 6902 writew(0x0007, spec->mem_base + 0x320); 6903 } 6904 6905 static void sbz_set_pin_ctl_default(struct hda_codec *codec) 6906 { 6907 hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13}; 6908 unsigned int i; 6909 6910 snd_hda_codec_write(codec, 0x11, 0, 6911 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40); 6912 6913 for (i = 0; i < 5; i++) 6914 snd_hda_codec_write(codec, pins[i], 0, 6915 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00); 6916 } 6917 6918 static void sbz_clear_unsolicited(struct hda_codec *codec) 6919 { 6920 hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13}; 6921 unsigned int i; 6922 6923 for (i = 0; i < 7; i++) { 6924 snd_hda_codec_write(codec, pins[i], 0, 6925 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00); 6926 } 6927 } 6928 6929 /* On shutdown, sends commands in sets of three */ 6930 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir, 6931 int mask, int data) 6932 { 6933 if (dir >= 0) 6934 snd_hda_codec_write(codec, 0x01, 0, 6935 AC_VERB_SET_GPIO_DIRECTION, dir); 6936 if (mask >= 0) 6937 snd_hda_codec_write(codec, 0x01, 0, 6938 AC_VERB_SET_GPIO_MASK, mask); 6939 6940 if (data >= 0) 6941 snd_hda_codec_write(codec, 0x01, 0, 6942 AC_VERB_SET_GPIO_DATA, data); 6943 } 6944 6945 static void sbz_exit_chip(struct hda_codec *codec) 6946 { 6947 chipio_set_stream_control(codec, 0x03, 0); 6948 chipio_set_stream_control(codec, 0x04, 0); 6949 6950 /* Mess with GPIO */ 6951 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1); 6952 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05); 6953 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01); 6954 6955 chipio_set_stream_control(codec, 0x14, 0); 6956 chipio_set_stream_control(codec, 0x0C, 0); 6957 6958 chipio_set_conn_rate(codec, 0x41, SR_192_000); 6959 chipio_set_conn_rate(codec, 0x91, SR_192_000); 6960 6961 chipio_write(codec, 0x18a020, 0x00000083); 6962 6963 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03); 6964 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07); 6965 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06); 6966 6967 chipio_set_stream_control(codec, 0x0C, 0); 6968 6969 chipio_set_control_param(codec, 0x0D, 0x24); 6970 6971 sbz_clear_unsolicited(codec); 6972 sbz_set_pin_ctl_default(codec); 6973 6974 snd_hda_codec_write(codec, 0x0B, 0, 6975 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 6976 6977 if (dspload_is_loaded(codec)) 6978 dsp_reset(codec); 6979 6980 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6981 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x00); 6982 6983 sbz_region2_exit(codec); 6984 } 6985 6986 static void ca0132_exit_chip(struct hda_codec *codec) 6987 { 6988 /* put any chip cleanup stuffs here. */ 6989 6990 if (dspload_is_loaded(codec)) 6991 dsp_reset(codec); 6992 } 6993 6994 /* 6995 * This fixes a problem that was hard to reproduce. Very rarely, I would 6996 * boot up, and there would be no sound, but the DSP indicated it had loaded 6997 * properly. I did a few memory dumps to see if anything was different, and 6998 * there were a few areas of memory uninitialized with a1a2a3a4. This function 6999 * checks if those areas are uninitialized, and if they are, it'll attempt to 7000 * reload the card 3 times. Usually it fixes by the second. 7001 */ 7002 static void sbz_dsp_startup_check(struct hda_codec *codec) 7003 { 7004 struct ca0132_spec *spec = codec->spec; 7005 unsigned int dsp_data_check[4]; 7006 unsigned int cur_address = 0x390; 7007 unsigned int i; 7008 unsigned int failure = 0; 7009 unsigned int reload = 3; 7010 7011 if (spec->startup_check_entered) 7012 return; 7013 7014 spec->startup_check_entered = true; 7015 7016 for (i = 0; i < 4; i++) { 7017 chipio_read(codec, cur_address, &dsp_data_check[i]); 7018 cur_address += 0x4; 7019 } 7020 for (i = 0; i < 4; i++) { 7021 if (dsp_data_check[i] == 0xa1a2a3a4) 7022 failure = 1; 7023 } 7024 7025 codec_dbg(codec, "Startup Check: %d ", failure); 7026 if (failure) 7027 codec_info(codec, "DSP not initialized properly. Attempting to fix."); 7028 /* 7029 * While the failure condition is true, and we haven't reached our 7030 * three reload limit, continue trying to reload the driver and 7031 * fix the issue. 7032 */ 7033 while (failure && (reload != 0)) { 7034 codec_info(codec, "Reloading... Tries left: %d", reload); 7035 sbz_exit_chip(codec); 7036 spec->dsp_state = DSP_DOWNLOAD_INIT; 7037 codec->patch_ops.init(codec); 7038 failure = 0; 7039 for (i = 0; i < 4; i++) { 7040 chipio_read(codec, cur_address, &dsp_data_check[i]); 7041 cur_address += 0x4; 7042 } 7043 for (i = 0; i < 4; i++) { 7044 if (dsp_data_check[i] == 0xa1a2a3a4) 7045 failure = 1; 7046 } 7047 reload--; 7048 } 7049 7050 if (!failure && reload < 3) 7051 codec_info(codec, "DSP fixed."); 7052 7053 if (!failure) 7054 return; 7055 7056 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory."); 7057 } 7058 7059 /* 7060 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add 7061 * extra precision for decibel values. If you had the dB value in floating point 7062 * you would take the value after the decimal point, multiply by 64, and divide 7063 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to 7064 * implement fixed point or floating point dB volumes. For now, I'll set them 7065 * to 0 just incase a value has lingered from a boot into Windows. 7066 */ 7067 static void ca0132_alt_vol_setup(struct hda_codec *codec) 7068 { 7069 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00); 7070 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00); 7071 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00); 7072 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00); 7073 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00); 7074 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00); 7075 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00); 7076 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00); 7077 } 7078 7079 /* 7080 * Extra commands that don't really fit anywhere else. 7081 */ 7082 static void sbz_pre_dsp_setup(struct hda_codec *codec) 7083 { 7084 struct ca0132_spec *spec = codec->spec; 7085 7086 writel(0x00820680, spec->mem_base + 0x01C); 7087 writel(0x00820680, spec->mem_base + 0x01C); 7088 7089 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfc); 7090 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfd); 7091 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfe); 7092 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xff); 7093 7094 chipio_write(codec, 0x18b0a4, 0x000000c2); 7095 7096 snd_hda_codec_write(codec, 0x11, 0, 7097 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 7098 } 7099 7100 /* 7101 * Extra commands that don't really fit anywhere else. 7102 */ 7103 static void r3di_pre_dsp_setup(struct hda_codec *codec) 7104 { 7105 chipio_write(codec, 0x18b0a4, 0x000000c2); 7106 7107 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7108 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E); 7109 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7110 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C); 7111 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7112 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B); 7113 7114 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7115 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); 7116 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7117 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 7118 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7119 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 7120 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7121 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40); 7122 7123 snd_hda_codec_write(codec, 0x11, 0, 7124 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04); 7125 } 7126 7127 7128 /* 7129 * These are sent before the DSP is downloaded. Not sure 7130 * what they do, or if they're necessary. Could possibly 7131 * be removed. Figure they're better to leave in. 7132 */ 7133 static void sbz_region2_startup(struct hda_codec *codec) 7134 { 7135 struct ca0132_spec *spec = codec->spec; 7136 7137 writel(0x00000000, spec->mem_base + 0x400); 7138 writel(0x00000000, spec->mem_base + 0x408); 7139 writel(0x00000000, spec->mem_base + 0x40C); 7140 writel(0x00880680, spec->mem_base + 0x01C); 7141 writel(0x00000083, spec->mem_base + 0xC0C); 7142 writel(0x00000030, spec->mem_base + 0xC00); 7143 writel(0x00000000, spec->mem_base + 0xC04); 7144 writel(0x00000003, spec->mem_base + 0xC0C); 7145 writel(0x00000003, spec->mem_base + 0xC0C); 7146 writel(0x00000003, spec->mem_base + 0xC0C); 7147 writel(0x00000003, spec->mem_base + 0xC0C); 7148 writel(0x000000C1, spec->mem_base + 0xC08); 7149 writel(0x000000F1, spec->mem_base + 0xC08); 7150 writel(0x00000001, spec->mem_base + 0xC08); 7151 writel(0x000000C7, spec->mem_base + 0xC08); 7152 writel(0x000000C1, spec->mem_base + 0xC08); 7153 writel(0x00000080, spec->mem_base + 0xC04); 7154 } 7155 7156 /* 7157 * Extra init functions for alternative ca0132 codecs. Done 7158 * here so they don't clutter up the main ca0132_init function 7159 * anymore than they have to. 7160 */ 7161 static void ca0132_alt_init(struct hda_codec *codec) 7162 { 7163 struct ca0132_spec *spec = codec->spec; 7164 7165 ca0132_alt_vol_setup(codec); 7166 7167 switch (spec->quirk) { 7168 case QUIRK_SBZ: 7169 codec_dbg(codec, "SBZ alt_init"); 7170 ca0132_gpio_init(codec); 7171 sbz_pre_dsp_setup(codec); 7172 snd_hda_sequence_write(codec, spec->chip_init_verbs); 7173 snd_hda_sequence_write(codec, spec->sbz_init_verbs); 7174 break; 7175 case QUIRK_R3DI: 7176 codec_dbg(codec, "R3DI alt_init"); 7177 ca0132_gpio_init(codec); 7178 ca0132_gpio_setup(codec); 7179 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING); 7180 r3di_pre_dsp_setup(codec); 7181 snd_hda_sequence_write(codec, spec->chip_init_verbs); 7182 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4); 7183 break; 7184 } 7185 } 7186 7187 static int ca0132_init(struct hda_codec *codec) 7188 { 7189 struct ca0132_spec *spec = codec->spec; 7190 struct auto_pin_cfg *cfg = &spec->autocfg; 7191 int i; 7192 bool dsp_loaded; 7193 7194 /* 7195 * If the DSP is already downloaded, and init has been entered again, 7196 * there's only two reasons for it. One, the codec has awaken from a 7197 * suspended state, and in that case dspload_is_loaded will return 7198 * false, and the init will be ran again. The other reason it gets 7199 * re entered is on startup for some reason it triggers a suspend and 7200 * resume state. In this case, it will check if the DSP is downloaded, 7201 * and not run the init function again. For codecs using alt_functions, 7202 * it will check if the DSP is loaded properly. 7203 */ 7204 if (spec->dsp_state == DSP_DOWNLOADED) { 7205 dsp_loaded = dspload_is_loaded(codec); 7206 if (!dsp_loaded) { 7207 spec->dsp_reload = true; 7208 spec->dsp_state = DSP_DOWNLOAD_INIT; 7209 } else { 7210 if (spec->quirk == QUIRK_SBZ) 7211 sbz_dsp_startup_check(codec); 7212 return 0; 7213 } 7214 } 7215 7216 if (spec->dsp_state != DSP_DOWNLOAD_FAILED) 7217 spec->dsp_state = DSP_DOWNLOAD_INIT; 7218 spec->curr_chip_addx = INVALID_CHIP_ADDRESS; 7219 7220 if (spec->quirk == QUIRK_SBZ) 7221 sbz_region2_startup(codec); 7222 7223 snd_hda_power_up_pm(codec); 7224 7225 ca0132_init_unsol(codec); 7226 ca0132_init_params(codec); 7227 ca0132_init_flags(codec); 7228 7229 snd_hda_sequence_write(codec, spec->base_init_verbs); 7230 7231 if (spec->use_alt_functions) 7232 ca0132_alt_init(codec); 7233 7234 ca0132_download_dsp(codec); 7235 7236 ca0132_refresh_widget_caps(codec); 7237 7238 if (spec->quirk == QUIRK_SBZ) 7239 writew(0x0107, spec->mem_base + 0x320); 7240 7241 switch (spec->quirk) { 7242 case QUIRK_R3DI: 7243 r3di_setup_defaults(codec); 7244 break; 7245 case QUIRK_SBZ: 7246 break; 7247 default: 7248 ca0132_setup_defaults(codec); 7249 ca0132_init_analog_mic2(codec); 7250 ca0132_init_dmic(codec); 7251 break; 7252 } 7253 7254 for (i = 0; i < spec->num_outputs; i++) 7255 init_output(codec, spec->out_pins[i], spec->dacs[0]); 7256 7257 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 7258 7259 for (i = 0; i < spec->num_inputs; i++) 7260 init_input(codec, spec->input_pins[i], spec->adcs[i]); 7261 7262 init_input(codec, cfg->dig_in_pin, spec->dig_in); 7263 7264 if (!spec->use_alt_functions) { 7265 snd_hda_sequence_write(codec, spec->chip_init_verbs); 7266 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7267 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D); 7268 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7269 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20); 7270 } 7271 7272 if (spec->quirk == QUIRK_SBZ) 7273 ca0132_gpio_setup(codec); 7274 7275 snd_hda_sequence_write(codec, spec->spec_init_verbs); 7276 switch (spec->quirk) { 7277 case QUIRK_SBZ: 7278 sbz_setup_defaults(codec); 7279 ca0132_alt_select_out(codec); 7280 ca0132_alt_select_in(codec); 7281 break; 7282 case QUIRK_R3DI: 7283 ca0132_alt_select_out(codec); 7284 ca0132_alt_select_in(codec); 7285 break; 7286 default: 7287 ca0132_select_out(codec); 7288 ca0132_select_mic(codec); 7289 break; 7290 } 7291 7292 snd_hda_jack_report_sync(codec); 7293 7294 /* 7295 * Re set the PlayEnhancement switch on a resume event, because the 7296 * controls will not be reloaded. 7297 */ 7298 if (spec->dsp_reload) { 7299 spec->dsp_reload = false; 7300 ca0132_pe_switch_set(codec); 7301 } 7302 7303 snd_hda_power_down_pm(codec); 7304 7305 return 0; 7306 } 7307 7308 static void ca0132_free(struct hda_codec *codec) 7309 { 7310 struct ca0132_spec *spec = codec->spec; 7311 7312 cancel_delayed_work_sync(&spec->unsol_hp_work); 7313 snd_hda_power_up(codec); 7314 switch (spec->quirk) { 7315 case QUIRK_SBZ: 7316 sbz_exit_chip(codec); 7317 break; 7318 case QUIRK_R3DI: 7319 r3di_gpio_shutdown(codec); 7320 snd_hda_sequence_write(codec, spec->base_exit_verbs); 7321 ca0132_exit_chip(codec); 7322 break; 7323 default: 7324 snd_hda_sequence_write(codec, spec->base_exit_verbs); 7325 ca0132_exit_chip(codec); 7326 break; 7327 } 7328 snd_hda_power_down(codec); 7329 if (spec->mem_base) 7330 iounmap(spec->mem_base); 7331 kfree(spec->spec_init_verbs); 7332 kfree(codec->spec); 7333 } 7334 7335 static void ca0132_reboot_notify(struct hda_codec *codec) 7336 { 7337 codec->patch_ops.free(codec); 7338 } 7339 7340 static const struct hda_codec_ops ca0132_patch_ops = { 7341 .build_controls = ca0132_build_controls, 7342 .build_pcms = ca0132_build_pcms, 7343 .init = ca0132_init, 7344 .free = ca0132_free, 7345 .unsol_event = snd_hda_jack_unsol_event, 7346 .reboot_notify = ca0132_reboot_notify, 7347 }; 7348 7349 static void ca0132_config(struct hda_codec *codec) 7350 { 7351 struct ca0132_spec *spec = codec->spec; 7352 7353 spec->dacs[0] = 0x2; 7354 spec->dacs[1] = 0x3; 7355 spec->dacs[2] = 0x4; 7356 7357 spec->multiout.dac_nids = spec->dacs; 7358 spec->multiout.num_dacs = 3; 7359 7360 if (!spec->use_alt_functions) 7361 spec->multiout.max_channels = 2; 7362 else 7363 spec->multiout.max_channels = 6; 7364 7365 switch (spec->quirk) { 7366 case QUIRK_ALIENWARE: 7367 codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n"); 7368 snd_hda_apply_pincfgs(codec, alienware_pincfgs); 7369 7370 spec->num_outputs = 2; 7371 spec->out_pins[0] = 0x0b; /* speaker out */ 7372 spec->out_pins[1] = 0x0f; 7373 spec->shared_out_nid = 0x2; 7374 spec->unsol_tag_hp = 0x0f; 7375 7376 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 7377 spec->adcs[1] = 0x8; /* analog mic2 */ 7378 spec->adcs[2] = 0xa; /* what u hear */ 7379 7380 spec->num_inputs = 3; 7381 spec->input_pins[0] = 0x12; 7382 spec->input_pins[1] = 0x11; 7383 spec->input_pins[2] = 0x13; 7384 spec->shared_mic_nid = 0x7; 7385 spec->unsol_tag_amic1 = 0x11; 7386 break; 7387 case QUIRK_SBZ: 7388 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__); 7389 snd_hda_apply_pincfgs(codec, sbz_pincfgs); 7390 7391 spec->num_outputs = 2; 7392 spec->out_pins[0] = 0x0B; /* Line out */ 7393 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 7394 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 7395 spec->out_pins[3] = 0x11; /* Rear surround */ 7396 spec->shared_out_nid = 0x2; 7397 spec->unsol_tag_hp = spec->out_pins[1]; 7398 spec->unsol_tag_front_hp = spec->out_pins[2]; 7399 7400 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 7401 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 7402 spec->adcs[2] = 0xa; /* what u hear */ 7403 7404 spec->num_inputs = 2; 7405 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 7406 spec->input_pins[1] = 0x13; /* What U Hear */ 7407 spec->shared_mic_nid = 0x7; 7408 spec->unsol_tag_amic1 = spec->input_pins[0]; 7409 7410 /* SPDIF I/O */ 7411 spec->dig_out = 0x05; 7412 spec->multiout.dig_out_nid = spec->dig_out; 7413 spec->dig_in = 0x09; 7414 break; 7415 case QUIRK_R3DI: 7416 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__); 7417 snd_hda_apply_pincfgs(codec, r3di_pincfgs); 7418 7419 spec->num_outputs = 2; 7420 spec->out_pins[0] = 0x0B; /* Line out */ 7421 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 7422 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 7423 spec->out_pins[3] = 0x11; /* Rear surround */ 7424 spec->shared_out_nid = 0x2; 7425 spec->unsol_tag_hp = spec->out_pins[1]; 7426 spec->unsol_tag_front_hp = spec->out_pins[2]; 7427 7428 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */ 7429 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */ 7430 spec->adcs[2] = 0x0a; /* what u hear */ 7431 7432 spec->num_inputs = 2; 7433 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 7434 spec->input_pins[1] = 0x13; /* What U Hear */ 7435 spec->shared_mic_nid = 0x7; 7436 spec->unsol_tag_amic1 = spec->input_pins[0]; 7437 7438 /* SPDIF I/O */ 7439 spec->dig_out = 0x05; 7440 spec->multiout.dig_out_nid = spec->dig_out; 7441 break; 7442 default: 7443 spec->num_outputs = 2; 7444 spec->out_pins[0] = 0x0b; /* speaker out */ 7445 spec->out_pins[1] = 0x10; /* headphone out */ 7446 spec->shared_out_nid = 0x2; 7447 spec->unsol_tag_hp = spec->out_pins[1]; 7448 7449 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 7450 spec->adcs[1] = 0x8; /* analog mic2 */ 7451 spec->adcs[2] = 0xa; /* what u hear */ 7452 7453 spec->num_inputs = 3; 7454 spec->input_pins[0] = 0x12; 7455 spec->input_pins[1] = 0x11; 7456 spec->input_pins[2] = 0x13; 7457 spec->shared_mic_nid = 0x7; 7458 spec->unsol_tag_amic1 = spec->input_pins[0]; 7459 7460 /* SPDIF I/O */ 7461 spec->dig_out = 0x05; 7462 spec->multiout.dig_out_nid = spec->dig_out; 7463 spec->dig_in = 0x09; 7464 break; 7465 } 7466 } 7467 7468 static int ca0132_prepare_verbs(struct hda_codec *codec) 7469 { 7470 /* Verbs + terminator (an empty element) */ 7471 #define NUM_SPEC_VERBS 2 7472 struct ca0132_spec *spec = codec->spec; 7473 7474 spec->chip_init_verbs = ca0132_init_verbs0; 7475 if (spec->quirk == QUIRK_SBZ) 7476 spec->sbz_init_verbs = sbz_init_verbs; 7477 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS, 7478 sizeof(struct hda_verb), 7479 GFP_KERNEL); 7480 if (!spec->spec_init_verbs) 7481 return -ENOMEM; 7482 7483 /* config EAPD */ 7484 spec->spec_init_verbs[0].nid = 0x0b; 7485 spec->spec_init_verbs[0].param = 0x78D; 7486 spec->spec_init_verbs[0].verb = 0x00; 7487 7488 /* Previously commented configuration */ 7489 /* 7490 spec->spec_init_verbs[2].nid = 0x0b; 7491 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE; 7492 spec->spec_init_verbs[2].verb = 0x02; 7493 7494 spec->spec_init_verbs[3].nid = 0x10; 7495 spec->spec_init_verbs[3].param = 0x78D; 7496 spec->spec_init_verbs[3].verb = 0x02; 7497 7498 spec->spec_init_verbs[4].nid = 0x10; 7499 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE; 7500 spec->spec_init_verbs[4].verb = 0x02; 7501 */ 7502 7503 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */ 7504 return 0; 7505 } 7506 7507 static int patch_ca0132(struct hda_codec *codec) 7508 { 7509 struct ca0132_spec *spec; 7510 int err; 7511 const struct snd_pci_quirk *quirk; 7512 7513 codec_dbg(codec, "patch_ca0132\n"); 7514 7515 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 7516 if (!spec) 7517 return -ENOMEM; 7518 codec->spec = spec; 7519 spec->codec = codec; 7520 7521 codec->patch_ops = ca0132_patch_ops; 7522 codec->pcm_format_first = 1; 7523 codec->no_sticky_stream = 1; 7524 7525 /* Detect codec quirk */ 7526 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks); 7527 if (quirk) 7528 spec->quirk = quirk->value; 7529 else 7530 spec->quirk = QUIRK_NONE; 7531 7532 /* Setup BAR Region 2 for Sound Blaster Z */ 7533 if (spec->quirk == QUIRK_SBZ) { 7534 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20); 7535 if (spec->mem_base == NULL) { 7536 codec_warn(codec, "pci_iomap failed!"); 7537 codec_info(codec, "perhaps this is not an SBZ?"); 7538 spec->quirk = QUIRK_NONE; 7539 } 7540 } 7541 7542 spec->dsp_state = DSP_DOWNLOAD_INIT; 7543 spec->num_mixers = 1; 7544 7545 /* Set which mixers each quirk uses. */ 7546 switch (spec->quirk) { 7547 case QUIRK_SBZ: 7548 spec->mixers[0] = sbz_mixer; 7549 snd_hda_codec_set_name(codec, "Sound Blaster Z"); 7550 break; 7551 case QUIRK_R3DI: 7552 spec->mixers[0] = r3di_mixer; 7553 snd_hda_codec_set_name(codec, "Recon3Di"); 7554 break; 7555 default: 7556 spec->mixers[0] = ca0132_mixer; 7557 break; 7558 } 7559 7560 /* Setup whether or not to use alt functions/controls */ 7561 switch (spec->quirk) { 7562 case QUIRK_SBZ: 7563 case QUIRK_R3DI: 7564 spec->use_alt_controls = true; 7565 spec->use_alt_functions = true; 7566 break; 7567 default: 7568 spec->use_alt_controls = false; 7569 spec->use_alt_functions = false; 7570 break; 7571 } 7572 7573 spec->base_init_verbs = ca0132_base_init_verbs; 7574 spec->base_exit_verbs = ca0132_base_exit_verbs; 7575 7576 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed); 7577 7578 ca0132_init_chip(codec); 7579 7580 ca0132_config(codec); 7581 7582 err = ca0132_prepare_verbs(codec); 7583 if (err < 0) 7584 goto error; 7585 7586 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL); 7587 if (err < 0) 7588 goto error; 7589 7590 return 0; 7591 7592 error: 7593 ca0132_free(codec); 7594 return err; 7595 } 7596 7597 /* 7598 * patch entries 7599 */ 7600 static struct hda_device_id snd_hda_id_ca0132[] = { 7601 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132), 7602 {} /* terminator */ 7603 }; 7604 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132); 7605 7606 MODULE_LICENSE("GPL"); 7607 MODULE_DESCRIPTION("Creative Sound Core3D codec"); 7608 7609 static struct hda_codec_driver ca0132_driver = { 7610 .id = snd_hda_id_ca0132, 7611 }; 7612 7613 module_hda_codec_driver(ca0132_driver); 7614