1 /* 2 * HD audio interface patch for Creative CA0132 chip 3 * 4 * Copyright (c) 2011, Creative Technology Ltd. 5 * 6 * Based on patch_ca0110.c 7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de> 8 * 9 * This driver is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This driver is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 */ 23 24 #include <linux/init.h> 25 #include <linux/delay.h> 26 #include <linux/slab.h> 27 #include <linux/pci.h> 28 #include <linux/mutex.h> 29 #include <linux/module.h> 30 #include <linux/firmware.h> 31 #include <sound/core.h> 32 #include "hda_codec.h" 33 #include "hda_local.h" 34 #include "hda_auto_parser.h" 35 #include "hda_jack.h" 36 37 #include "ca0132_regs.h" 38 39 /* Enable this to see controls for tuning purpose. */ 40 /*#define ENABLE_TUNING_CONTROLS*/ 41 42 #define FLOAT_ZERO 0x00000000 43 #define FLOAT_ONE 0x3f800000 44 #define FLOAT_TWO 0x40000000 45 #define FLOAT_MINUS_5 0xc0a00000 46 47 #define UNSOL_TAG_HP 0x10 48 #define UNSOL_TAG_AMIC1 0x12 49 #define UNSOL_TAG_DSP 0x16 50 51 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18) 52 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15) 53 54 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8 55 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32 56 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2 57 58 #define MASTERCONTROL 0x80 59 #define MASTERCONTROL_ALLOC_DMA_CHAN 10 60 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60 61 62 #define WIDGET_CHIP_CTRL 0x15 63 #define WIDGET_DSP_CTRL 0x16 64 65 #define MEM_CONNID_MICIN1 3 66 #define MEM_CONNID_MICIN2 5 67 #define MEM_CONNID_MICOUT1 12 68 #define MEM_CONNID_MICOUT2 14 69 #define MEM_CONNID_WUH 10 70 #define MEM_CONNID_DSP 16 71 #define MEM_CONNID_DMIC 100 72 73 #define SCP_SET 0 74 #define SCP_GET 1 75 76 #define EFX_FILE "ctefx.bin" 77 78 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 79 MODULE_FIRMWARE(EFX_FILE); 80 #endif 81 82 static char *dirstr[2] = { "Playback", "Capture" }; 83 84 enum { 85 SPEAKER_OUT, 86 HEADPHONE_OUT 87 }; 88 89 enum { 90 DIGITAL_MIC, 91 LINE_MIC_IN 92 }; 93 94 enum { 95 #define VNODE_START_NID 0x80 96 VNID_SPK = VNODE_START_NID, /* Speaker vnid */ 97 VNID_MIC, 98 VNID_HP_SEL, 99 VNID_AMIC1_SEL, 100 VNID_HP_ASEL, 101 VNID_AMIC1_ASEL, 102 VNODE_END_NID, 103 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID) 104 105 #define EFFECT_START_NID 0x90 106 #define OUT_EFFECT_START_NID EFFECT_START_NID 107 SURROUND = OUT_EFFECT_START_NID, 108 CRYSTALIZER, 109 DIALOG_PLUS, 110 SMART_VOLUME, 111 X_BASS, 112 EQUALIZER, 113 OUT_EFFECT_END_NID, 114 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID) 115 116 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID 117 ECHO_CANCELLATION = IN_EFFECT_START_NID, 118 VOICE_FOCUS, 119 MIC_SVM, 120 NOISE_REDUCTION, 121 IN_EFFECT_END_NID, 122 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID) 123 124 VOICEFX = IN_EFFECT_END_NID, 125 PLAY_ENHANCEMENT, 126 CRYSTAL_VOICE, 127 EFFECT_END_NID 128 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID) 129 }; 130 131 /* Effects values size*/ 132 #define EFFECT_VALS_MAX_COUNT 12 133 134 struct ct_effect { 135 char name[44]; 136 hda_nid_t nid; 137 int mid; /*effect module ID*/ 138 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/ 139 int direct; /* 0:output; 1:input*/ 140 int params; /* number of default non-on/off params */ 141 /*effect default values, 1st is on/off. */ 142 unsigned int def_vals[EFFECT_VALS_MAX_COUNT]; 143 }; 144 145 #define EFX_DIR_OUT 0 146 #define EFX_DIR_IN 1 147 148 static struct ct_effect ca0132_effects[EFFECTS_COUNT] = { 149 { .name = "Surround", 150 .nid = SURROUND, 151 .mid = 0x96, 152 .reqs = {0, 1}, 153 .direct = EFX_DIR_OUT, 154 .params = 1, 155 .def_vals = {0x3F800000, 0x3F2B851F} 156 }, 157 { .name = "Crystalizer", 158 .nid = CRYSTALIZER, 159 .mid = 0x96, 160 .reqs = {7, 8}, 161 .direct = EFX_DIR_OUT, 162 .params = 1, 163 .def_vals = {0x3F800000, 0x3F266666} 164 }, 165 { .name = "Dialog Plus", 166 .nid = DIALOG_PLUS, 167 .mid = 0x96, 168 .reqs = {2, 3}, 169 .direct = EFX_DIR_OUT, 170 .params = 1, 171 .def_vals = {0x00000000, 0x3F000000} 172 }, 173 { .name = "Smart Volume", 174 .nid = SMART_VOLUME, 175 .mid = 0x96, 176 .reqs = {4, 5, 6}, 177 .direct = EFX_DIR_OUT, 178 .params = 2, 179 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000} 180 }, 181 { .name = "X-Bass", 182 .nid = X_BASS, 183 .mid = 0x96, 184 .reqs = {24, 23, 25}, 185 .direct = EFX_DIR_OUT, 186 .params = 2, 187 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000} 188 }, 189 { .name = "Equalizer", 190 .nid = EQUALIZER, 191 .mid = 0x96, 192 .reqs = {9, 10, 11, 12, 13, 14, 193 15, 16, 17, 18, 19, 20}, 194 .direct = EFX_DIR_OUT, 195 .params = 11, 196 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000, 197 0x00000000, 0x00000000, 0x00000000, 0x00000000, 198 0x00000000, 0x00000000, 0x00000000, 0x00000000} 199 }, 200 { .name = "Echo Cancellation", 201 .nid = ECHO_CANCELLATION, 202 .mid = 0x95, 203 .reqs = {0, 1, 2, 3}, 204 .direct = EFX_DIR_IN, 205 .params = 3, 206 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000} 207 }, 208 { .name = "Voice Focus", 209 .nid = VOICE_FOCUS, 210 .mid = 0x95, 211 .reqs = {6, 7, 8, 9}, 212 .direct = EFX_DIR_IN, 213 .params = 3, 214 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000} 215 }, 216 { .name = "Mic SVM", 217 .nid = MIC_SVM, 218 .mid = 0x95, 219 .reqs = {44, 45}, 220 .direct = EFX_DIR_IN, 221 .params = 1, 222 .def_vals = {0x00000000, 0x3F3D70A4} 223 }, 224 { .name = "Noise Reduction", 225 .nid = NOISE_REDUCTION, 226 .mid = 0x95, 227 .reqs = {4, 5}, 228 .direct = EFX_DIR_IN, 229 .params = 1, 230 .def_vals = {0x3F800000, 0x3F000000} 231 }, 232 { .name = "VoiceFX", 233 .nid = VOICEFX, 234 .mid = 0x95, 235 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}, 236 .direct = EFX_DIR_IN, 237 .params = 8, 238 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000, 239 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000, 240 0x00000000} 241 } 242 }; 243 244 /* Tuning controls */ 245 #ifdef ENABLE_TUNING_CONTROLS 246 247 enum { 248 #define TUNING_CTL_START_NID 0xC0 249 WEDGE_ANGLE = TUNING_CTL_START_NID, 250 SVM_LEVEL, 251 EQUALIZER_BAND_0, 252 EQUALIZER_BAND_1, 253 EQUALIZER_BAND_2, 254 EQUALIZER_BAND_3, 255 EQUALIZER_BAND_4, 256 EQUALIZER_BAND_5, 257 EQUALIZER_BAND_6, 258 EQUALIZER_BAND_7, 259 EQUALIZER_BAND_8, 260 EQUALIZER_BAND_9, 261 TUNING_CTL_END_NID 262 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID) 263 }; 264 265 struct ct_tuning_ctl { 266 char name[44]; 267 hda_nid_t parent_nid; 268 hda_nid_t nid; 269 int mid; /*effect module ID*/ 270 int req; /*effect module request*/ 271 int direct; /* 0:output; 1:input*/ 272 unsigned int def_val;/*effect default values*/ 273 }; 274 275 static struct ct_tuning_ctl ca0132_tuning_ctls[] = { 276 { .name = "Wedge Angle", 277 .parent_nid = VOICE_FOCUS, 278 .nid = WEDGE_ANGLE, 279 .mid = 0x95, 280 .req = 8, 281 .direct = EFX_DIR_IN, 282 .def_val = 0x41F00000 283 }, 284 { .name = "SVM Level", 285 .parent_nid = MIC_SVM, 286 .nid = SVM_LEVEL, 287 .mid = 0x95, 288 .req = 45, 289 .direct = EFX_DIR_IN, 290 .def_val = 0x3F3D70A4 291 }, 292 { .name = "EQ Band0", 293 .parent_nid = EQUALIZER, 294 .nid = EQUALIZER_BAND_0, 295 .mid = 0x96, 296 .req = 11, 297 .direct = EFX_DIR_OUT, 298 .def_val = 0x00000000 299 }, 300 { .name = "EQ Band1", 301 .parent_nid = EQUALIZER, 302 .nid = EQUALIZER_BAND_1, 303 .mid = 0x96, 304 .req = 12, 305 .direct = EFX_DIR_OUT, 306 .def_val = 0x00000000 307 }, 308 { .name = "EQ Band2", 309 .parent_nid = EQUALIZER, 310 .nid = EQUALIZER_BAND_2, 311 .mid = 0x96, 312 .req = 13, 313 .direct = EFX_DIR_OUT, 314 .def_val = 0x00000000 315 }, 316 { .name = "EQ Band3", 317 .parent_nid = EQUALIZER, 318 .nid = EQUALIZER_BAND_3, 319 .mid = 0x96, 320 .req = 14, 321 .direct = EFX_DIR_OUT, 322 .def_val = 0x00000000 323 }, 324 { .name = "EQ Band4", 325 .parent_nid = EQUALIZER, 326 .nid = EQUALIZER_BAND_4, 327 .mid = 0x96, 328 .req = 15, 329 .direct = EFX_DIR_OUT, 330 .def_val = 0x00000000 331 }, 332 { .name = "EQ Band5", 333 .parent_nid = EQUALIZER, 334 .nid = EQUALIZER_BAND_5, 335 .mid = 0x96, 336 .req = 16, 337 .direct = EFX_DIR_OUT, 338 .def_val = 0x00000000 339 }, 340 { .name = "EQ Band6", 341 .parent_nid = EQUALIZER, 342 .nid = EQUALIZER_BAND_6, 343 .mid = 0x96, 344 .req = 17, 345 .direct = EFX_DIR_OUT, 346 .def_val = 0x00000000 347 }, 348 { .name = "EQ Band7", 349 .parent_nid = EQUALIZER, 350 .nid = EQUALIZER_BAND_7, 351 .mid = 0x96, 352 .req = 18, 353 .direct = EFX_DIR_OUT, 354 .def_val = 0x00000000 355 }, 356 { .name = "EQ Band8", 357 .parent_nid = EQUALIZER, 358 .nid = EQUALIZER_BAND_8, 359 .mid = 0x96, 360 .req = 19, 361 .direct = EFX_DIR_OUT, 362 .def_val = 0x00000000 363 }, 364 { .name = "EQ Band9", 365 .parent_nid = EQUALIZER, 366 .nid = EQUALIZER_BAND_9, 367 .mid = 0x96, 368 .req = 20, 369 .direct = EFX_DIR_OUT, 370 .def_val = 0x00000000 371 } 372 }; 373 #endif 374 375 /* Voice FX Presets */ 376 #define VOICEFX_MAX_PARAM_COUNT 9 377 378 struct ct_voicefx { 379 char *name; 380 hda_nid_t nid; 381 int mid; 382 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/ 383 }; 384 385 struct ct_voicefx_preset { 386 char *name; /*preset name*/ 387 unsigned int vals[VOICEFX_MAX_PARAM_COUNT]; 388 }; 389 390 static struct ct_voicefx ca0132_voicefx = { 391 .name = "VoiceFX Capture Switch", 392 .nid = VOICEFX, 393 .mid = 0x95, 394 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18} 395 }; 396 397 static struct ct_voicefx_preset ca0132_voicefx_presets[] = { 398 { .name = "Neutral", 399 .vals = { 0x00000000, 0x43C80000, 0x44AF0000, 400 0x44FA0000, 0x3F800000, 0x3F800000, 401 0x3F800000, 0x00000000, 0x00000000 } 402 }, 403 { .name = "Female2Male", 404 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 405 0x44FA0000, 0x3F19999A, 0x3F866666, 406 0x3F800000, 0x00000000, 0x00000000 } 407 }, 408 { .name = "Male2Female", 409 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 410 0x450AC000, 0x4017AE14, 0x3F6B851F, 411 0x3F800000, 0x00000000, 0x00000000 } 412 }, 413 { .name = "ScrappyKid", 414 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 415 0x44FA0000, 0x40400000, 0x3F28F5C3, 416 0x3F800000, 0x00000000, 0x00000000 } 417 }, 418 { .name = "Elderly", 419 .vals = { 0x3F800000, 0x44324000, 0x44BB8000, 420 0x44E10000, 0x3FB33333, 0x3FB9999A, 421 0x3F800000, 0x3E3A2E43, 0x00000000 } 422 }, 423 { .name = "Orc", 424 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000, 425 0x45098000, 0x3F266666, 0x3FC00000, 426 0x3F800000, 0x00000000, 0x00000000 } 427 }, 428 { .name = "Elf", 429 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000, 430 0x45193000, 0x3F8E147B, 0x3F75C28F, 431 0x3F800000, 0x00000000, 0x00000000 } 432 }, 433 { .name = "Dwarf", 434 .vals = { 0x3F800000, 0x43930000, 0x44BEE000, 435 0x45007000, 0x3F451EB8, 0x3F7851EC, 436 0x3F800000, 0x00000000, 0x00000000 } 437 }, 438 { .name = "AlienBrute", 439 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF, 440 0x451F6000, 0x3F266666, 0x3FA7D945, 441 0x3F800000, 0x3CF5C28F, 0x00000000 } 442 }, 443 { .name = "Robot", 444 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 445 0x44FA0000, 0x3FB2718B, 0x3F800000, 446 0xBC07010E, 0x00000000, 0x00000000 } 447 }, 448 { .name = "Marine", 449 .vals = { 0x3F800000, 0x43C20000, 0x44906000, 450 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71, 451 0x3F0A3D71, 0x00000000, 0x00000000 } 452 }, 453 { .name = "Emo", 454 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 455 0x44FA0000, 0x3F800000, 0x3F800000, 456 0x3E4CCCCD, 0x00000000, 0x00000000 } 457 }, 458 { .name = "DeepVoice", 459 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF, 460 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA, 461 0x3F800000, 0x00000000, 0x00000000 } 462 }, 463 { .name = "Munchkin", 464 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 465 0x44FA0000, 0x3F800000, 0x3F1A043C, 466 0x3F800000, 0x00000000, 0x00000000 } 467 } 468 }; 469 470 enum hda_cmd_vendor_io { 471 /* for DspIO node */ 472 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000, 473 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100, 474 475 VENDOR_DSPIO_STATUS = 0xF01, 476 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702, 477 VENDOR_DSPIO_SCP_READ_DATA = 0xF02, 478 VENDOR_DSPIO_DSP_INIT = 0x703, 479 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704, 480 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04, 481 482 /* for ChipIO node */ 483 VENDOR_CHIPIO_ADDRESS_LOW = 0x000, 484 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100, 485 VENDOR_CHIPIO_STREAM_FORMAT = 0x200, 486 VENDOR_CHIPIO_DATA_LOW = 0x300, 487 VENDOR_CHIPIO_DATA_HIGH = 0x400, 488 489 VENDOR_CHIPIO_GET_PARAMETER = 0xF00, 490 VENDOR_CHIPIO_STATUS = 0xF01, 491 VENDOR_CHIPIO_HIC_POST_READ = 0x702, 492 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03, 493 494 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707, 495 VENDOR_CHIPIO_8051_DATA_READ = 0xF07, 496 497 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A, 498 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A, 499 500 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C, 501 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C, 502 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D, 503 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E, 504 VENDOR_CHIPIO_FLAG_SET = 0x70F, 505 VENDOR_CHIPIO_FLAGS_GET = 0xF0F, 506 VENDOR_CHIPIO_PARAM_SET = 0x710, 507 VENDOR_CHIPIO_PARAM_GET = 0xF10, 508 509 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711, 510 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712, 511 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12, 512 VENDOR_CHIPIO_PORT_FREE_SET = 0x713, 513 514 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17, 515 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717, 516 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18, 517 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718, 518 519 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788, 520 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88, 521 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789, 522 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89, 523 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A, 524 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A, 525 526 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D 527 }; 528 529 /* 530 * Control flag IDs 531 */ 532 enum control_flag_id { 533 /* Connection manager stream setup is bypassed/enabled */ 534 CONTROL_FLAG_C_MGR = 0, 535 /* DSP DMA is bypassed/enabled */ 536 CONTROL_FLAG_DMA = 1, 537 /* 8051 'idle' mode is disabled/enabled */ 538 CONTROL_FLAG_IDLE_ENABLE = 2, 539 /* Tracker for the SPDIF-in path is bypassed/enabled */ 540 CONTROL_FLAG_TRACKER = 3, 541 /* DigitalOut to Spdif2Out connection is disabled/enabled */ 542 CONTROL_FLAG_SPDIF2OUT = 4, 543 /* Digital Microphone is disabled/enabled */ 544 CONTROL_FLAG_DMIC = 5, 545 /* ADC_B rate is 48 kHz/96 kHz */ 546 CONTROL_FLAG_ADC_B_96KHZ = 6, 547 /* ADC_C rate is 48 kHz/96 kHz */ 548 CONTROL_FLAG_ADC_C_96KHZ = 7, 549 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */ 550 CONTROL_FLAG_DAC_96KHZ = 8, 551 /* DSP rate is 48 kHz/96 kHz */ 552 CONTROL_FLAG_DSP_96KHZ = 9, 553 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */ 554 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10, 555 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */ 556 CONTROL_FLAG_SRC_RATE_96KHZ = 11, 557 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */ 558 CONTROL_FLAG_DECODE_LOOP = 12, 559 /* De-emphasis filter on DAC-1 disabled/enabled */ 560 CONTROL_FLAG_DAC1_DEEMPHASIS = 13, 561 /* De-emphasis filter on DAC-2 disabled/enabled */ 562 CONTROL_FLAG_DAC2_DEEMPHASIS = 14, 563 /* De-emphasis filter on DAC-3 disabled/enabled */ 564 CONTROL_FLAG_DAC3_DEEMPHASIS = 15, 565 /* High-pass filter on ADC_B disabled/enabled */ 566 CONTROL_FLAG_ADC_B_HIGH_PASS = 16, 567 /* High-pass filter on ADC_C disabled/enabled */ 568 CONTROL_FLAG_ADC_C_HIGH_PASS = 17, 569 /* Common mode on Port_A disabled/enabled */ 570 CONTROL_FLAG_PORT_A_COMMON_MODE = 18, 571 /* Common mode on Port_D disabled/enabled */ 572 CONTROL_FLAG_PORT_D_COMMON_MODE = 19, 573 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */ 574 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20, 575 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */ 576 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21, 577 /* ASI rate is 48kHz/96kHz */ 578 CONTROL_FLAG_ASI_96KHZ = 22, 579 /* DAC power settings able to control attached ports no/yes */ 580 CONTROL_FLAG_DACS_CONTROL_PORTS = 23, 581 /* Clock Stop OK reporting is disabled/enabled */ 582 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24, 583 /* Number of control flags */ 584 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1) 585 }; 586 587 /* 588 * Control parameter IDs 589 */ 590 enum control_param_id { 591 /* 0: None, 1: Mic1In*/ 592 CONTROL_PARAM_VIP_SOURCE = 1, 593 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */ 594 CONTROL_PARAM_SPDIF1_SOURCE = 2, 595 /* Port A output stage gain setting to use when 16 Ohm output 596 * impedance is selected*/ 597 CONTROL_PARAM_PORTA_160OHM_GAIN = 8, 598 /* Port D output stage gain setting to use when 16 Ohm output 599 * impedance is selected*/ 600 CONTROL_PARAM_PORTD_160OHM_GAIN = 10, 601 602 /* Stream Control */ 603 604 /* Select stream with the given ID */ 605 CONTROL_PARAM_STREAM_ID = 24, 606 /* Source connection point for the selected stream */ 607 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25, 608 /* Destination connection point for the selected stream */ 609 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26, 610 /* Number of audio channels in the selected stream */ 611 CONTROL_PARAM_STREAMS_CHANNELS = 27, 612 /*Enable control for the selected stream */ 613 CONTROL_PARAM_STREAM_CONTROL = 28, 614 615 /* Connection Point Control */ 616 617 /* Select connection point with the given ID */ 618 CONTROL_PARAM_CONN_POINT_ID = 29, 619 /* Connection point sample rate */ 620 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30, 621 622 /* Node Control */ 623 624 /* Select HDA node with the given ID */ 625 CONTROL_PARAM_NODE_ID = 31 626 }; 627 628 /* 629 * Dsp Io Status codes 630 */ 631 enum hda_vendor_status_dspio { 632 /* Success */ 633 VENDOR_STATUS_DSPIO_OK = 0x00, 634 /* Busy, unable to accept new command, the host must retry */ 635 VENDOR_STATUS_DSPIO_BUSY = 0x01, 636 /* SCP command queue is full */ 637 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02, 638 /* SCP response queue is empty */ 639 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03 640 }; 641 642 /* 643 * Chip Io Status codes 644 */ 645 enum hda_vendor_status_chipio { 646 /* Success */ 647 VENDOR_STATUS_CHIPIO_OK = 0x00, 648 /* Busy, unable to accept new command, the host must retry */ 649 VENDOR_STATUS_CHIPIO_BUSY = 0x01 650 }; 651 652 /* 653 * CA0132 sample rate 654 */ 655 enum ca0132_sample_rate { 656 SR_6_000 = 0x00, 657 SR_8_000 = 0x01, 658 SR_9_600 = 0x02, 659 SR_11_025 = 0x03, 660 SR_16_000 = 0x04, 661 SR_22_050 = 0x05, 662 SR_24_000 = 0x06, 663 SR_32_000 = 0x07, 664 SR_44_100 = 0x08, 665 SR_48_000 = 0x09, 666 SR_88_200 = 0x0A, 667 SR_96_000 = 0x0B, 668 SR_144_000 = 0x0C, 669 SR_176_400 = 0x0D, 670 SR_192_000 = 0x0E, 671 SR_384_000 = 0x0F, 672 673 SR_COUNT = 0x10, 674 675 SR_RATE_UNKNOWN = 0x1F 676 }; 677 678 enum dsp_download_state { 679 DSP_DOWNLOAD_FAILED = -1, 680 DSP_DOWNLOAD_INIT = 0, 681 DSP_DOWNLOADING = 1, 682 DSP_DOWNLOADED = 2 683 }; 684 685 /* retrieve parameters from hda format */ 686 #define get_hdafmt_chs(fmt) (fmt & 0xf) 687 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7) 688 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f) 689 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1) 690 691 /* 692 * CA0132 specific 693 */ 694 695 struct ca0132_spec { 696 struct snd_kcontrol_new *mixers[5]; 697 unsigned int num_mixers; 698 const struct hda_verb *base_init_verbs; 699 const struct hda_verb *base_exit_verbs; 700 const struct hda_verb *init_verbs[5]; 701 unsigned int num_init_verbs; /* exclude base init verbs */ 702 struct auto_pin_cfg autocfg; 703 704 /* Nodes configurations */ 705 struct hda_multi_out multiout; 706 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS]; 707 hda_nid_t dacs[AUTO_CFG_MAX_OUTS]; 708 unsigned int num_outputs; 709 hda_nid_t input_pins[AUTO_PIN_LAST]; 710 hda_nid_t adcs[AUTO_PIN_LAST]; 711 hda_nid_t dig_out; 712 hda_nid_t dig_in; 713 unsigned int num_inputs; 714 hda_nid_t shared_mic_nid; 715 hda_nid_t shared_out_nid; 716 struct hda_pcm pcm_rec[5]; /* PCM information */ 717 718 /* chip access */ 719 struct mutex chipio_mutex; /* chip access mutex */ 720 u32 curr_chip_addx; 721 722 /* DSP download related */ 723 enum dsp_download_state dsp_state; 724 unsigned int dsp_stream_id; 725 unsigned int wait_scp; 726 unsigned int wait_scp_header; 727 unsigned int wait_num_data; 728 unsigned int scp_resp_header; 729 unsigned int scp_resp_data[4]; 730 unsigned int scp_resp_count; 731 732 /* mixer and effects related */ 733 unsigned char dmic_ctl; 734 int cur_out_type; 735 int cur_mic_type; 736 long vnode_lvol[VNODES_COUNT]; 737 long vnode_rvol[VNODES_COUNT]; 738 long vnode_lswitch[VNODES_COUNT]; 739 long vnode_rswitch[VNODES_COUNT]; 740 long effects_switch[EFFECTS_COUNT]; 741 long voicefx_val; 742 long cur_mic_boost; 743 744 #ifdef ENABLE_TUNING_CONTROLS 745 long cur_ctl_vals[TUNING_CTLS_COUNT]; 746 #endif 747 }; 748 749 /* 750 * CA0132 codec access 751 */ 752 unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid, 753 unsigned int verb, unsigned int parm, unsigned int *res) 754 { 755 unsigned int response; 756 response = snd_hda_codec_read(codec, nid, 0, verb, parm); 757 *res = response; 758 759 return ((response == -1) ? -1 : 0); 760 } 761 762 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid, 763 unsigned short converter_format, unsigned int *res) 764 { 765 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT, 766 converter_format & 0xffff, res); 767 } 768 769 static int codec_set_converter_stream_channel(struct hda_codec *codec, 770 hda_nid_t nid, unsigned char stream, 771 unsigned char channel, unsigned int *res) 772 { 773 unsigned char converter_stream_channel = 0; 774 775 converter_stream_channel = (stream << 4) | (channel & 0x0f); 776 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID, 777 converter_stream_channel, res); 778 } 779 780 /* Chip access helper function */ 781 static int chipio_send(struct hda_codec *codec, 782 unsigned int reg, 783 unsigned int data) 784 { 785 unsigned int res; 786 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 787 788 /* send bits of data specified by reg */ 789 do { 790 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 791 reg, data); 792 if (res == VENDOR_STATUS_CHIPIO_OK) 793 return 0; 794 msleep(20); 795 } while (time_before(jiffies, timeout)); 796 797 return -EIO; 798 } 799 800 /* 801 * Write chip address through the vendor widget -- NOT protected by the Mutex! 802 */ 803 static int chipio_write_address(struct hda_codec *codec, 804 unsigned int chip_addx) 805 { 806 struct ca0132_spec *spec = codec->spec; 807 int res; 808 809 if (spec->curr_chip_addx == chip_addx) 810 return 0; 811 812 /* send low 16 bits of the address */ 813 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW, 814 chip_addx & 0xffff); 815 816 if (res != -EIO) { 817 /* send high 16 bits of the address */ 818 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH, 819 chip_addx >> 16); 820 } 821 822 spec->curr_chip_addx = (res < 0) ? ~0UL : chip_addx; 823 824 return res; 825 } 826 827 /* 828 * Write data through the vendor widget -- NOT protected by the Mutex! 829 */ 830 static int chipio_write_data(struct hda_codec *codec, unsigned int data) 831 { 832 struct ca0132_spec *spec = codec->spec; 833 int res; 834 835 /* send low 16 bits of the data */ 836 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff); 837 838 if (res != -EIO) { 839 /* send high 16 bits of the data */ 840 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH, 841 data >> 16); 842 } 843 844 /*If no error encountered, automatically increment the address 845 as per chip behaviour*/ 846 spec->curr_chip_addx = (res != -EIO) ? 847 (spec->curr_chip_addx + 4) : ~0UL; 848 return res; 849 } 850 851 /* 852 * Write multiple data through the vendor widget -- NOT protected by the Mutex! 853 */ 854 static int chipio_write_data_multiple(struct hda_codec *codec, 855 const u32 *data, 856 unsigned int count) 857 { 858 int status = 0; 859 860 if (data == NULL) { 861 snd_printdd(KERN_ERR "chipio_write_data null ptr\n"); 862 return -EINVAL; 863 } 864 865 while ((count-- != 0) && (status == 0)) 866 status = chipio_write_data(codec, *data++); 867 868 return status; 869 } 870 871 872 /* 873 * Read data through the vendor widget -- NOT protected by the Mutex! 874 */ 875 static int chipio_read_data(struct hda_codec *codec, unsigned int *data) 876 { 877 struct ca0132_spec *spec = codec->spec; 878 int res; 879 880 /* post read */ 881 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0); 882 883 if (res != -EIO) { 884 /* read status */ 885 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 886 } 887 888 if (res != -EIO) { 889 /* read data */ 890 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 891 VENDOR_CHIPIO_HIC_READ_DATA, 892 0); 893 } 894 895 /*If no error encountered, automatically increment the address 896 as per chip behaviour*/ 897 spec->curr_chip_addx = (res != -EIO) ? 898 (spec->curr_chip_addx + 4) : ~0UL; 899 return res; 900 } 901 902 /* 903 * Write given value to the given address through the chip I/O widget. 904 * protected by the Mutex 905 */ 906 static int chipio_write(struct hda_codec *codec, 907 unsigned int chip_addx, const unsigned int data) 908 { 909 struct ca0132_spec *spec = codec->spec; 910 int err; 911 912 mutex_lock(&spec->chipio_mutex); 913 914 /* write the address, and if successful proceed to write data */ 915 err = chipio_write_address(codec, chip_addx); 916 if (err < 0) 917 goto exit; 918 919 err = chipio_write_data(codec, data); 920 if (err < 0) 921 goto exit; 922 923 exit: 924 mutex_unlock(&spec->chipio_mutex); 925 return err; 926 } 927 928 /* 929 * Write multiple values to the given address through the chip I/O widget. 930 * protected by the Mutex 931 */ 932 static int chipio_write_multiple(struct hda_codec *codec, 933 u32 chip_addx, 934 const u32 *data, 935 unsigned int count) 936 { 937 struct ca0132_spec *spec = codec->spec; 938 int status; 939 940 mutex_lock(&spec->chipio_mutex); 941 status = chipio_write_address(codec, chip_addx); 942 if (status < 0) 943 goto error; 944 945 status = chipio_write_data_multiple(codec, data, count); 946 error: 947 mutex_unlock(&spec->chipio_mutex); 948 949 return status; 950 } 951 952 /* 953 * Read the given address through the chip I/O widget 954 * protected by the Mutex 955 */ 956 static int chipio_read(struct hda_codec *codec, 957 unsigned int chip_addx, unsigned int *data) 958 { 959 struct ca0132_spec *spec = codec->spec; 960 int err; 961 962 mutex_lock(&spec->chipio_mutex); 963 964 /* write the address, and if successful proceed to write data */ 965 err = chipio_write_address(codec, chip_addx); 966 if (err < 0) 967 goto exit; 968 969 err = chipio_read_data(codec, data); 970 if (err < 0) 971 goto exit; 972 973 exit: 974 mutex_unlock(&spec->chipio_mutex); 975 return err; 976 } 977 978 /* 979 * Set chip control flags through the chip I/O widget. 980 */ 981 static void chipio_set_control_flag(struct hda_codec *codec, 982 enum control_flag_id flag_id, 983 bool flag_state) 984 { 985 unsigned int val; 986 unsigned int flag_bit; 987 988 flag_bit = (flag_state ? 1 : 0); 989 val = (flag_bit << 7) | (flag_id); 990 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 991 VENDOR_CHIPIO_FLAG_SET, val); 992 } 993 994 /* 995 * Set chip parameters through the chip I/O widget. 996 */ 997 static void chipio_set_control_param(struct hda_codec *codec, 998 enum control_param_id param_id, int param_val) 999 { 1000 struct ca0132_spec *spec = codec->spec; 1001 int val; 1002 1003 if ((param_id < 32) && (param_val < 8)) { 1004 val = (param_val << 5) | (param_id); 1005 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1006 VENDOR_CHIPIO_PARAM_SET, val); 1007 } else { 1008 mutex_lock(&spec->chipio_mutex); 1009 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1010 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1011 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1012 param_id); 1013 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1014 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1015 param_val); 1016 } 1017 mutex_unlock(&spec->chipio_mutex); 1018 } 1019 } 1020 1021 /* 1022 * Set sampling rate of the connection point. 1023 */ 1024 static void chipio_set_conn_rate(struct hda_codec *codec, 1025 int connid, enum ca0132_sample_rate rate) 1026 { 1027 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid); 1028 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, 1029 rate); 1030 } 1031 1032 /* 1033 * Enable clocks. 1034 */ 1035 static void chipio_enable_clocks(struct hda_codec *codec) 1036 { 1037 struct ca0132_spec *spec = codec->spec; 1038 1039 mutex_lock(&spec->chipio_mutex); 1040 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1041 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0); 1042 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1043 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); 1044 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1045 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5); 1046 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1047 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b); 1048 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1049 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6); 1050 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1051 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); 1052 mutex_unlock(&spec->chipio_mutex); 1053 } 1054 1055 /* 1056 * CA0132 DSP IO stuffs 1057 */ 1058 static int dspio_send(struct hda_codec *codec, unsigned int reg, 1059 unsigned int data) 1060 { 1061 int res; 1062 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1063 1064 /* send bits of data specified by reg to dsp */ 1065 do { 1066 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data); 1067 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY)) 1068 return res; 1069 msleep(20); 1070 } while (time_before(jiffies, timeout)); 1071 1072 return -EIO; 1073 } 1074 1075 /* 1076 * Wait for DSP to be ready for commands 1077 */ 1078 static void dspio_write_wait(struct hda_codec *codec) 1079 { 1080 int status; 1081 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1082 1083 do { 1084 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1085 VENDOR_DSPIO_STATUS, 0); 1086 if ((status == VENDOR_STATUS_DSPIO_OK) || 1087 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)) 1088 break; 1089 msleep(1); 1090 } while (time_before(jiffies, timeout)); 1091 } 1092 1093 /* 1094 * Write SCP data to DSP 1095 */ 1096 static int dspio_write(struct hda_codec *codec, unsigned int scp_data) 1097 { 1098 struct ca0132_spec *spec = codec->spec; 1099 int status; 1100 1101 dspio_write_wait(codec); 1102 1103 mutex_lock(&spec->chipio_mutex); 1104 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW, 1105 scp_data & 0xffff); 1106 if (status < 0) 1107 goto error; 1108 1109 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH, 1110 scp_data >> 16); 1111 if (status < 0) 1112 goto error; 1113 1114 /* OK, now check if the write itself has executed*/ 1115 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1116 VENDOR_DSPIO_STATUS, 0); 1117 error: 1118 mutex_unlock(&spec->chipio_mutex); 1119 1120 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ? 1121 -EIO : 0; 1122 } 1123 1124 /* 1125 * Write multiple SCP data to DSP 1126 */ 1127 static int dspio_write_multiple(struct hda_codec *codec, 1128 unsigned int *buffer, unsigned int size) 1129 { 1130 int status = 0; 1131 unsigned int count; 1132 1133 if ((buffer == NULL)) 1134 return -EINVAL; 1135 1136 count = 0; 1137 while (count < size) { 1138 status = dspio_write(codec, *buffer++); 1139 if (status != 0) 1140 break; 1141 count++; 1142 } 1143 1144 return status; 1145 } 1146 1147 static int dspio_read(struct hda_codec *codec, unsigned int *data) 1148 { 1149 int status; 1150 1151 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0); 1152 if (status == -EIO) 1153 return status; 1154 1155 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0); 1156 if (status == -EIO || 1157 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY) 1158 return -EIO; 1159 1160 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1161 VENDOR_DSPIO_SCP_READ_DATA, 0); 1162 1163 return 0; 1164 } 1165 1166 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer, 1167 unsigned int *buf_size, unsigned int size_count) 1168 { 1169 int status = 0; 1170 unsigned int size = *buf_size; 1171 unsigned int count; 1172 unsigned int skip_count; 1173 unsigned int dummy; 1174 1175 if ((buffer == NULL)) 1176 return -1; 1177 1178 count = 0; 1179 while (count < size && count < size_count) { 1180 status = dspio_read(codec, buffer++); 1181 if (status != 0) 1182 break; 1183 count++; 1184 } 1185 1186 skip_count = count; 1187 if (status == 0) { 1188 while (skip_count < size) { 1189 status = dspio_read(codec, &dummy); 1190 if (status != 0) 1191 break; 1192 skip_count++; 1193 } 1194 } 1195 *buf_size = count; 1196 1197 return status; 1198 } 1199 1200 /* 1201 * Construct the SCP header using corresponding fields 1202 */ 1203 static inline unsigned int 1204 make_scp_header(unsigned int target_id, unsigned int source_id, 1205 unsigned int get_flag, unsigned int req, 1206 unsigned int device_flag, unsigned int resp_flag, 1207 unsigned int error_flag, unsigned int data_size) 1208 { 1209 unsigned int header = 0; 1210 1211 header = (data_size & 0x1f) << 27; 1212 header |= (error_flag & 0x01) << 26; 1213 header |= (resp_flag & 0x01) << 25; 1214 header |= (device_flag & 0x01) << 24; 1215 header |= (req & 0x7f) << 17; 1216 header |= (get_flag & 0x01) << 16; 1217 header |= (source_id & 0xff) << 8; 1218 header |= target_id & 0xff; 1219 1220 return header; 1221 } 1222 1223 /* 1224 * Extract corresponding fields from SCP header 1225 */ 1226 static inline void 1227 extract_scp_header(unsigned int header, 1228 unsigned int *target_id, unsigned int *source_id, 1229 unsigned int *get_flag, unsigned int *req, 1230 unsigned int *device_flag, unsigned int *resp_flag, 1231 unsigned int *error_flag, unsigned int *data_size) 1232 { 1233 if (data_size) 1234 *data_size = (header >> 27) & 0x1f; 1235 if (error_flag) 1236 *error_flag = (header >> 26) & 0x01; 1237 if (resp_flag) 1238 *resp_flag = (header >> 25) & 0x01; 1239 if (device_flag) 1240 *device_flag = (header >> 24) & 0x01; 1241 if (req) 1242 *req = (header >> 17) & 0x7f; 1243 if (get_flag) 1244 *get_flag = (header >> 16) & 0x01; 1245 if (source_id) 1246 *source_id = (header >> 8) & 0xff; 1247 if (target_id) 1248 *target_id = header & 0xff; 1249 } 1250 1251 #define SCP_MAX_DATA_WORDS (16) 1252 1253 /* Structure to contain any SCP message */ 1254 struct scp_msg { 1255 unsigned int hdr; 1256 unsigned int data[SCP_MAX_DATA_WORDS]; 1257 }; 1258 1259 static void dspio_clear_response_queue(struct hda_codec *codec) 1260 { 1261 unsigned int dummy = 0; 1262 int status = -1; 1263 1264 /* clear all from the response queue */ 1265 do { 1266 status = dspio_read(codec, &dummy); 1267 } while (status == 0); 1268 } 1269 1270 static int dspio_get_response_data(struct hda_codec *codec) 1271 { 1272 struct ca0132_spec *spec = codec->spec; 1273 unsigned int data = 0; 1274 unsigned int count; 1275 1276 if (dspio_read(codec, &data) < 0) 1277 return -EIO; 1278 1279 if ((data & 0x00ffffff) == spec->wait_scp_header) { 1280 spec->scp_resp_header = data; 1281 spec->scp_resp_count = data >> 27; 1282 count = spec->wait_num_data; 1283 dspio_read_multiple(codec, spec->scp_resp_data, 1284 &spec->scp_resp_count, count); 1285 return 0; 1286 } 1287 1288 return -EIO; 1289 } 1290 1291 /* 1292 * Send SCP message to DSP 1293 */ 1294 static int dspio_send_scp_message(struct hda_codec *codec, 1295 unsigned char *send_buf, 1296 unsigned int send_buf_size, 1297 unsigned char *return_buf, 1298 unsigned int return_buf_size, 1299 unsigned int *bytes_returned) 1300 { 1301 struct ca0132_spec *spec = codec->spec; 1302 int status = -1; 1303 unsigned int scp_send_size = 0; 1304 unsigned int total_size; 1305 bool waiting_for_resp = false; 1306 unsigned int header; 1307 struct scp_msg *ret_msg; 1308 unsigned int resp_src_id, resp_target_id; 1309 unsigned int data_size, src_id, target_id, get_flag, device_flag; 1310 1311 if (bytes_returned) 1312 *bytes_returned = 0; 1313 1314 /* get scp header from buffer */ 1315 header = *((unsigned int *)send_buf); 1316 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL, 1317 &device_flag, NULL, NULL, &data_size); 1318 scp_send_size = data_size + 1; 1319 total_size = (scp_send_size * 4); 1320 1321 if (send_buf_size < total_size) 1322 return -EINVAL; 1323 1324 if (get_flag || device_flag) { 1325 if (!return_buf || return_buf_size < 4 || !bytes_returned) 1326 return -EINVAL; 1327 1328 spec->wait_scp_header = *((unsigned int *)send_buf); 1329 1330 /* swap source id with target id */ 1331 resp_target_id = src_id; 1332 resp_src_id = target_id; 1333 spec->wait_scp_header &= 0xffff0000; 1334 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id); 1335 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1; 1336 spec->wait_scp = 1; 1337 waiting_for_resp = true; 1338 } 1339 1340 status = dspio_write_multiple(codec, (unsigned int *)send_buf, 1341 scp_send_size); 1342 if (status < 0) { 1343 spec->wait_scp = 0; 1344 return status; 1345 } 1346 1347 if (waiting_for_resp) { 1348 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1349 memset(return_buf, 0, return_buf_size); 1350 do { 1351 msleep(20); 1352 } while (spec->wait_scp && time_before(jiffies, timeout)); 1353 waiting_for_resp = false; 1354 if (!spec->wait_scp) { 1355 ret_msg = (struct scp_msg *)return_buf; 1356 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4); 1357 memcpy(&ret_msg->data, spec->scp_resp_data, 1358 spec->wait_num_data); 1359 *bytes_returned = (spec->scp_resp_count + 1) * 4; 1360 status = 0; 1361 } else { 1362 status = -EIO; 1363 } 1364 spec->wait_scp = 0; 1365 } 1366 1367 return status; 1368 } 1369 1370 /** 1371 * Prepare and send the SCP message to DSP 1372 * @codec: the HDA codec 1373 * @mod_id: ID of the DSP module to send the command 1374 * @req: ID of request to send to the DSP module 1375 * @dir: SET or GET 1376 * @data: pointer to the data to send with the request, request specific 1377 * @len: length of the data, in bytes 1378 * @reply: point to the buffer to hold data returned for a reply 1379 * @reply_len: length of the reply buffer returned from GET 1380 * 1381 * Returns zero or a negative error code. 1382 */ 1383 static int dspio_scp(struct hda_codec *codec, 1384 int mod_id, int req, int dir, void *data, unsigned int len, 1385 void *reply, unsigned int *reply_len) 1386 { 1387 int status = 0; 1388 struct scp_msg scp_send, scp_reply; 1389 unsigned int ret_bytes, send_size, ret_size; 1390 unsigned int send_get_flag, reply_resp_flag, reply_error_flag; 1391 unsigned int reply_data_size; 1392 1393 memset(&scp_send, 0, sizeof(scp_send)); 1394 memset(&scp_reply, 0, sizeof(scp_reply)); 1395 1396 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS)) 1397 return -EINVAL; 1398 1399 if (dir == SCP_GET && reply == NULL) { 1400 snd_printdd(KERN_ERR "dspio_scp get but has no buffer\n"); 1401 return -EINVAL; 1402 } 1403 1404 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) { 1405 snd_printdd(KERN_ERR "dspio_scp bad resp buf len parms\n"); 1406 return -EINVAL; 1407 } 1408 1409 scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req, 1410 0, 0, 0, len/sizeof(unsigned int)); 1411 if (data != NULL && len > 0) { 1412 len = min((unsigned int)(sizeof(scp_send.data)), len); 1413 memcpy(scp_send.data, data, len); 1414 } 1415 1416 ret_bytes = 0; 1417 send_size = sizeof(unsigned int) + len; 1418 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send, 1419 send_size, (unsigned char *)&scp_reply, 1420 sizeof(scp_reply), &ret_bytes); 1421 1422 if (status < 0) { 1423 snd_printdd(KERN_ERR "dspio_scp: send scp msg failed\n"); 1424 return status; 1425 } 1426 1427 /* extract send and reply headers members */ 1428 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag, 1429 NULL, NULL, NULL, NULL, NULL); 1430 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL, 1431 &reply_resp_flag, &reply_error_flag, 1432 &reply_data_size); 1433 1434 if (!send_get_flag) 1435 return 0; 1436 1437 if (reply_resp_flag && !reply_error_flag) { 1438 ret_size = (ret_bytes - sizeof(scp_reply.hdr)) 1439 / sizeof(unsigned int); 1440 1441 if (*reply_len < ret_size*sizeof(unsigned int)) { 1442 snd_printdd(KERN_ERR "reply too long for buf\n"); 1443 return -EINVAL; 1444 } else if (ret_size != reply_data_size) { 1445 snd_printdd(KERN_ERR "RetLen and HdrLen .NE.\n"); 1446 return -EINVAL; 1447 } else { 1448 *reply_len = ret_size*sizeof(unsigned int); 1449 memcpy(reply, scp_reply.data, *reply_len); 1450 } 1451 } else { 1452 snd_printdd(KERN_ERR "reply ill-formed or errflag set\n"); 1453 return -EIO; 1454 } 1455 1456 return status; 1457 } 1458 1459 /* 1460 * Set DSP parameters 1461 */ 1462 static int dspio_set_param(struct hda_codec *codec, int mod_id, 1463 int req, void *data, unsigned int len) 1464 { 1465 return dspio_scp(codec, mod_id, req, SCP_SET, data, len, NULL, NULL); 1466 } 1467 1468 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id, 1469 int req, unsigned int data) 1470 { 1471 return dspio_set_param(codec, mod_id, req, &data, sizeof(unsigned int)); 1472 } 1473 1474 /* 1475 * Allocate a DSP DMA channel via an SCP message 1476 */ 1477 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan) 1478 { 1479 int status = 0; 1480 unsigned int size = sizeof(dma_chan); 1481 1482 snd_printdd(KERN_INFO " dspio_alloc_dma_chan() -- begin\n"); 1483 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN, 1484 SCP_GET, NULL, 0, dma_chan, &size); 1485 1486 if (status < 0) { 1487 snd_printdd(KERN_INFO "dspio_alloc_dma_chan: SCP Failed\n"); 1488 return status; 1489 } 1490 1491 if ((*dma_chan + 1) == 0) { 1492 snd_printdd(KERN_INFO "no free dma channels to allocate\n"); 1493 return -EBUSY; 1494 } 1495 1496 snd_printdd("dspio_alloc_dma_chan: chan=%d\n", *dma_chan); 1497 snd_printdd(KERN_INFO " dspio_alloc_dma_chan() -- complete\n"); 1498 1499 return status; 1500 } 1501 1502 /* 1503 * Free a DSP DMA via an SCP message 1504 */ 1505 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan) 1506 { 1507 int status = 0; 1508 unsigned int dummy = 0; 1509 1510 snd_printdd(KERN_INFO " dspio_free_dma_chan() -- begin\n"); 1511 snd_printdd("dspio_free_dma_chan: chan=%d\n", dma_chan); 1512 1513 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN, 1514 SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy); 1515 1516 if (status < 0) { 1517 snd_printdd(KERN_INFO "dspio_free_dma_chan: SCP Failed\n"); 1518 return status; 1519 } 1520 1521 snd_printdd(KERN_INFO " dspio_free_dma_chan() -- complete\n"); 1522 1523 return status; 1524 } 1525 1526 /* 1527 * (Re)start the DSP 1528 */ 1529 static int dsp_set_run_state(struct hda_codec *codec) 1530 { 1531 unsigned int dbg_ctrl_reg; 1532 unsigned int halt_state; 1533 int err; 1534 1535 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg); 1536 if (err < 0) 1537 return err; 1538 1539 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >> 1540 DSP_DBGCNTL_STATE_LOBIT; 1541 1542 if (halt_state != 0) { 1543 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) & 1544 DSP_DBGCNTL_SS_MASK); 1545 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 1546 dbg_ctrl_reg); 1547 if (err < 0) 1548 return err; 1549 1550 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) & 1551 DSP_DBGCNTL_EXEC_MASK; 1552 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 1553 dbg_ctrl_reg); 1554 if (err < 0) 1555 return err; 1556 } 1557 1558 return 0; 1559 } 1560 1561 /* 1562 * Reset the DSP 1563 */ 1564 static int dsp_reset(struct hda_codec *codec) 1565 { 1566 unsigned int res; 1567 int retry = 20; 1568 1569 snd_printdd("dsp_reset\n"); 1570 do { 1571 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0); 1572 retry--; 1573 } while (res == -EIO && retry); 1574 1575 if (!retry) { 1576 snd_printdd("dsp_reset timeout\n"); 1577 return -EIO; 1578 } 1579 1580 return 0; 1581 } 1582 1583 /* 1584 * Convert chip address to DSP address 1585 */ 1586 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx, 1587 bool *code, bool *yram) 1588 { 1589 *code = *yram = false; 1590 1591 if (UC_RANGE(chip_addx, 1)) { 1592 *code = true; 1593 return UC_OFF(chip_addx); 1594 } else if (X_RANGE_ALL(chip_addx, 1)) { 1595 return X_OFF(chip_addx); 1596 } else if (Y_RANGE_ALL(chip_addx, 1)) { 1597 *yram = true; 1598 return Y_OFF(chip_addx); 1599 } 1600 1601 return INVALID_CHIP_ADDRESS; 1602 } 1603 1604 /* 1605 * Check if the DSP DMA is active 1606 */ 1607 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan) 1608 { 1609 unsigned int dma_chnlstart_reg; 1610 1611 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg); 1612 1613 return ((dma_chnlstart_reg & (1 << 1614 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0); 1615 } 1616 1617 static int dsp_dma_setup_common(struct hda_codec *codec, 1618 unsigned int chip_addx, 1619 unsigned int dma_chan, 1620 unsigned int port_map_mask, 1621 bool ovly) 1622 { 1623 int status = 0; 1624 unsigned int chnl_prop; 1625 unsigned int dsp_addx; 1626 unsigned int active; 1627 bool code, yram; 1628 1629 snd_printdd(KERN_INFO "-- dsp_dma_setup_common() -- Begin ---------\n"); 1630 1631 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) { 1632 snd_printdd(KERN_ERR "dma chan num invalid\n"); 1633 return -EINVAL; 1634 } 1635 1636 if (dsp_is_dma_active(codec, dma_chan)) { 1637 snd_printdd(KERN_ERR "dma already active\n"); 1638 return -EBUSY; 1639 } 1640 1641 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 1642 1643 if (dsp_addx == INVALID_CHIP_ADDRESS) { 1644 snd_printdd(KERN_ERR "invalid chip addr\n"); 1645 return -ENXIO; 1646 } 1647 1648 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK; 1649 active = 0; 1650 1651 snd_printdd(KERN_INFO " dsp_dma_setup_common() start reg pgm\n"); 1652 1653 if (ovly) { 1654 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET, 1655 &chnl_prop); 1656 1657 if (status < 0) { 1658 snd_printdd(KERN_ERR "read CHNLPROP Reg fail\n"); 1659 return status; 1660 } 1661 snd_printdd(KERN_INFO "dsp_dma_setup_common() Read CHNLPROP\n"); 1662 } 1663 1664 if (!code) 1665 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 1666 else 1667 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 1668 1669 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan)); 1670 1671 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop); 1672 if (status < 0) { 1673 snd_printdd(KERN_ERR "write CHNLPROP Reg fail\n"); 1674 return status; 1675 } 1676 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write CHNLPROP\n"); 1677 1678 if (ovly) { 1679 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET, 1680 &active); 1681 1682 if (status < 0) { 1683 snd_printdd(KERN_ERR "read ACTIVE Reg fail\n"); 1684 return status; 1685 } 1686 snd_printdd(KERN_INFO "dsp_dma_setup_common() Read ACTIVE\n"); 1687 } 1688 1689 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) & 1690 DSPDMAC_ACTIVE_AAR_MASK; 1691 1692 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active); 1693 if (status < 0) { 1694 snd_printdd(KERN_ERR "write ACTIVE Reg fail\n"); 1695 return status; 1696 } 1697 1698 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write ACTIVE\n"); 1699 1700 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan), 1701 port_map_mask); 1702 if (status < 0) { 1703 snd_printdd(KERN_ERR "write AUDCHSEL Reg fail\n"); 1704 return status; 1705 } 1706 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write AUDCHSEL\n"); 1707 1708 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan), 1709 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK); 1710 if (status < 0) { 1711 snd_printdd(KERN_ERR "write IRQCNT Reg fail\n"); 1712 return status; 1713 } 1714 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write IRQCNT\n"); 1715 1716 snd_printdd( 1717 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, " 1718 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n", 1719 chip_addx, dsp_addx, dma_chan, 1720 port_map_mask, chnl_prop, active); 1721 1722 snd_printdd(KERN_INFO "-- dsp_dma_setup_common() -- Complete ------\n"); 1723 1724 return 0; 1725 } 1726 1727 /* 1728 * Setup the DSP DMA per-transfer-specific registers 1729 */ 1730 static int dsp_dma_setup(struct hda_codec *codec, 1731 unsigned int chip_addx, 1732 unsigned int count, 1733 unsigned int dma_chan) 1734 { 1735 int status = 0; 1736 bool code, yram; 1737 unsigned int dsp_addx; 1738 unsigned int addr_field; 1739 unsigned int incr_field; 1740 unsigned int base_cnt; 1741 unsigned int cur_cnt; 1742 unsigned int dma_cfg = 0; 1743 unsigned int adr_ofs = 0; 1744 unsigned int xfr_cnt = 0; 1745 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT - 1746 DSPDMAC_XFRCNT_BCNT_LOBIT + 1); 1747 1748 snd_printdd(KERN_INFO "-- dsp_dma_setup() -- Begin ---------\n"); 1749 1750 if (count > max_dma_count) { 1751 snd_printdd(KERN_ERR "count too big\n"); 1752 return -EINVAL; 1753 } 1754 1755 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 1756 if (dsp_addx == INVALID_CHIP_ADDRESS) { 1757 snd_printdd(KERN_ERR "invalid chip addr\n"); 1758 return -ENXIO; 1759 } 1760 1761 snd_printdd(KERN_INFO " dsp_dma_setup() start reg pgm\n"); 1762 1763 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT; 1764 incr_field = 0; 1765 1766 if (!code) { 1767 addr_field <<= 1; 1768 if (yram) 1769 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT); 1770 1771 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT); 1772 } 1773 1774 dma_cfg = addr_field + incr_field; 1775 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan), 1776 dma_cfg); 1777 if (status < 0) { 1778 snd_printdd(KERN_ERR "write DMACFG Reg fail\n"); 1779 return status; 1780 } 1781 snd_printdd(KERN_INFO " dsp_dma_setup() Write DMACFG\n"); 1782 1783 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT + 1784 (code ? 0 : 1)); 1785 1786 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan), 1787 adr_ofs); 1788 if (status < 0) { 1789 snd_printdd(KERN_ERR "write DSPADROFS Reg fail\n"); 1790 return status; 1791 } 1792 snd_printdd(KERN_INFO " dsp_dma_setup() Write DSPADROFS\n"); 1793 1794 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT; 1795 1796 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT; 1797 1798 xfr_cnt = base_cnt | cur_cnt; 1799 1800 status = chipio_write(codec, 1801 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt); 1802 if (status < 0) { 1803 snd_printdd(KERN_ERR "write XFRCNT Reg fail\n"); 1804 return status; 1805 } 1806 snd_printdd(KERN_INFO " dsp_dma_setup() Write XFRCNT\n"); 1807 1808 snd_printdd( 1809 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, " 1810 "ADROFS=0x%x, XFRCNT=0x%x\n", 1811 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt); 1812 1813 snd_printdd(KERN_INFO "-- dsp_dma_setup() -- Complete ---------\n"); 1814 1815 return 0; 1816 } 1817 1818 /* 1819 * Start the DSP DMA 1820 */ 1821 static int dsp_dma_start(struct hda_codec *codec, 1822 unsigned int dma_chan, bool ovly) 1823 { 1824 unsigned int reg = 0; 1825 int status = 0; 1826 1827 snd_printdd(KERN_INFO "-- dsp_dma_start() -- Begin ---------\n"); 1828 1829 if (ovly) { 1830 status = chipio_read(codec, 1831 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 1832 1833 if (status < 0) { 1834 snd_printdd(KERN_ERR "read CHNLSTART reg fail\n"); 1835 return status; 1836 } 1837 snd_printdd(KERN_INFO "-- dsp_dma_start() Read CHNLSTART\n"); 1838 1839 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 1840 DSPDMAC_CHNLSTART_DIS_MASK); 1841 } 1842 1843 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 1844 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT))); 1845 if (status < 0) { 1846 snd_printdd(KERN_ERR "write CHNLSTART reg fail\n"); 1847 return status; 1848 } 1849 snd_printdd(KERN_INFO "-- dsp_dma_start() -- Complete ---------\n"); 1850 1851 return status; 1852 } 1853 1854 /* 1855 * Stop the DSP DMA 1856 */ 1857 static int dsp_dma_stop(struct hda_codec *codec, 1858 unsigned int dma_chan, bool ovly) 1859 { 1860 unsigned int reg = 0; 1861 int status = 0; 1862 1863 snd_printdd(KERN_INFO "-- dsp_dma_stop() -- Begin ---------\n"); 1864 1865 if (ovly) { 1866 status = chipio_read(codec, 1867 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 1868 1869 if (status < 0) { 1870 snd_printdd(KERN_ERR "read CHNLSTART reg fail\n"); 1871 return status; 1872 } 1873 snd_printdd(KERN_INFO "-- dsp_dma_stop() Read CHNLSTART\n"); 1874 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 1875 DSPDMAC_CHNLSTART_DIS_MASK); 1876 } 1877 1878 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 1879 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT))); 1880 if (status < 0) { 1881 snd_printdd(KERN_ERR "write CHNLSTART reg fail\n"); 1882 return status; 1883 } 1884 snd_printdd(KERN_INFO "-- dsp_dma_stop() -- Complete ---------\n"); 1885 1886 return status; 1887 } 1888 1889 /** 1890 * Allocate router ports 1891 * 1892 * @codec: the HDA codec 1893 * @num_chans: number of channels in the stream 1894 * @ports_per_channel: number of ports per channel 1895 * @start_device: start device 1896 * @port_map: pointer to the port list to hold the allocated ports 1897 * 1898 * Returns zero or a negative error code. 1899 */ 1900 static int dsp_allocate_router_ports(struct hda_codec *codec, 1901 unsigned int num_chans, 1902 unsigned int ports_per_channel, 1903 unsigned int start_device, 1904 unsigned int *port_map) 1905 { 1906 int status = 0; 1907 int res; 1908 u8 val; 1909 1910 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 1911 if (status < 0) 1912 return status; 1913 1914 val = start_device << 6; 1915 val |= (ports_per_channel - 1) << 4; 1916 val |= num_chans - 1; 1917 1918 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1919 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET, 1920 val); 1921 1922 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1923 VENDOR_CHIPIO_PORT_ALLOC_SET, 1924 MEM_CONNID_DSP); 1925 1926 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 1927 if (status < 0) 1928 return status; 1929 1930 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1931 VENDOR_CHIPIO_PORT_ALLOC_GET, 0); 1932 1933 *port_map = res; 1934 1935 return (res < 0) ? res : 0; 1936 } 1937 1938 /* 1939 * Free router ports 1940 */ 1941 static int dsp_free_router_ports(struct hda_codec *codec) 1942 { 1943 int status = 0; 1944 1945 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 1946 if (status < 0) 1947 return status; 1948 1949 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1950 VENDOR_CHIPIO_PORT_FREE_SET, 1951 MEM_CONNID_DSP); 1952 1953 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 1954 1955 return status; 1956 } 1957 1958 /* 1959 * Allocate DSP ports for the download stream 1960 */ 1961 static int dsp_allocate_ports(struct hda_codec *codec, 1962 unsigned int num_chans, 1963 unsigned int rate_multi, unsigned int *port_map) 1964 { 1965 int status; 1966 1967 snd_printdd(KERN_INFO " dsp_allocate_ports() -- begin\n"); 1968 1969 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 1970 snd_printdd(KERN_ERR "bad rate multiple\n"); 1971 return -EINVAL; 1972 } 1973 1974 status = dsp_allocate_router_ports(codec, num_chans, 1975 rate_multi, 0, port_map); 1976 1977 snd_printdd(KERN_INFO " dsp_allocate_ports() -- complete\n"); 1978 1979 return status; 1980 } 1981 1982 static int dsp_allocate_ports_format(struct hda_codec *codec, 1983 const unsigned short fmt, 1984 unsigned int *port_map) 1985 { 1986 int status; 1987 unsigned int num_chans; 1988 1989 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1; 1990 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1; 1991 unsigned int rate_multi = sample_rate_mul / sample_rate_div; 1992 1993 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 1994 snd_printdd(KERN_ERR "bad rate multiple\n"); 1995 return -EINVAL; 1996 } 1997 1998 num_chans = get_hdafmt_chs(fmt) + 1; 1999 2000 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map); 2001 2002 return status; 2003 } 2004 2005 /* 2006 * free DSP ports 2007 */ 2008 static int dsp_free_ports(struct hda_codec *codec) 2009 { 2010 int status; 2011 2012 snd_printdd(KERN_INFO " dsp_free_ports() -- begin\n"); 2013 2014 status = dsp_free_router_ports(codec); 2015 if (status < 0) { 2016 snd_printdd(KERN_ERR "free router ports fail\n"); 2017 return status; 2018 } 2019 snd_printdd(KERN_INFO " dsp_free_ports() -- complete\n"); 2020 2021 return status; 2022 } 2023 2024 /* 2025 * HDA DMA engine stuffs for DSP code download 2026 */ 2027 struct dma_engine { 2028 struct hda_codec *codec; 2029 unsigned short m_converter_format; 2030 struct snd_dma_buffer *dmab; 2031 unsigned int buf_size; 2032 }; 2033 2034 2035 enum dma_state { 2036 DMA_STATE_STOP = 0, 2037 DMA_STATE_RUN = 1 2038 }; 2039 2040 static int dma_convert_to_hda_format( 2041 unsigned int sample_rate, 2042 unsigned short channels, 2043 unsigned short *hda_format) 2044 { 2045 unsigned int format_val; 2046 2047 format_val = snd_hda_calc_stream_format( 2048 sample_rate, 2049 channels, 2050 SNDRV_PCM_FORMAT_S32_LE, 2051 32, 0); 2052 2053 if (hda_format) 2054 *hda_format = (unsigned short)format_val; 2055 2056 return 0; 2057 } 2058 2059 /* 2060 * Reset DMA for DSP download 2061 */ 2062 static int dma_reset(struct dma_engine *dma) 2063 { 2064 struct hda_codec *codec = dma->codec; 2065 struct ca0132_spec *spec = codec->spec; 2066 int status; 2067 2068 if (dma->dmab->area) 2069 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab); 2070 2071 status = snd_hda_codec_load_dsp_prepare(codec, 2072 dma->m_converter_format, 2073 dma->buf_size, 2074 dma->dmab); 2075 if (status < 0) 2076 return status; 2077 spec->dsp_stream_id = status; 2078 return 0; 2079 } 2080 2081 static int dma_set_state(struct dma_engine *dma, enum dma_state state) 2082 { 2083 bool cmd; 2084 2085 snd_printdd("dma_set_state state=%d\n", state); 2086 2087 switch (state) { 2088 case DMA_STATE_STOP: 2089 cmd = false; 2090 break; 2091 case DMA_STATE_RUN: 2092 cmd = true; 2093 break; 2094 default: 2095 return 0; 2096 } 2097 2098 snd_hda_codec_load_dsp_trigger(dma->codec, cmd); 2099 return 0; 2100 } 2101 2102 static unsigned int dma_get_buffer_size(struct dma_engine *dma) 2103 { 2104 return dma->dmab->bytes; 2105 } 2106 2107 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma) 2108 { 2109 return dma->dmab->area; 2110 } 2111 2112 static int dma_xfer(struct dma_engine *dma, 2113 const unsigned int *data, 2114 unsigned int count) 2115 { 2116 memcpy(dma->dmab->area, data, count); 2117 return 0; 2118 } 2119 2120 static void dma_get_converter_format( 2121 struct dma_engine *dma, 2122 unsigned short *format) 2123 { 2124 if (format) 2125 *format = dma->m_converter_format; 2126 } 2127 2128 static unsigned int dma_get_stream_id(struct dma_engine *dma) 2129 { 2130 struct ca0132_spec *spec = dma->codec->spec; 2131 2132 return spec->dsp_stream_id; 2133 } 2134 2135 struct dsp_image_seg { 2136 u32 magic; 2137 u32 chip_addr; 2138 u32 count; 2139 u32 data[0]; 2140 }; 2141 2142 static const u32 g_magic_value = 0x4c46584d; 2143 static const u32 g_chip_addr_magic_value = 0xFFFFFF01; 2144 2145 static bool is_valid(const struct dsp_image_seg *p) 2146 { 2147 return p->magic == g_magic_value; 2148 } 2149 2150 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p) 2151 { 2152 return g_chip_addr_magic_value == p->chip_addr; 2153 } 2154 2155 static bool is_last(const struct dsp_image_seg *p) 2156 { 2157 return p->count == 0; 2158 } 2159 2160 static size_t dsp_sizeof(const struct dsp_image_seg *p) 2161 { 2162 return sizeof(*p) + p->count*sizeof(u32); 2163 } 2164 2165 static const struct dsp_image_seg *get_next_seg_ptr( 2166 const struct dsp_image_seg *p) 2167 { 2168 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p)); 2169 } 2170 2171 /* 2172 * CA0132 chip DSP transfer stuffs. For DSP download. 2173 */ 2174 #define INVALID_DMA_CHANNEL (~0U) 2175 2176 /* 2177 * Program a list of address/data pairs via the ChipIO widget. 2178 * The segment data is in the format of successive pairs of words. 2179 * These are repeated as indicated by the segment's count field. 2180 */ 2181 static int dspxfr_hci_write(struct hda_codec *codec, 2182 const struct dsp_image_seg *fls) 2183 { 2184 int status; 2185 const u32 *data; 2186 unsigned int count; 2187 2188 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) { 2189 snd_printdd(KERN_ERR "hci_write invalid params\n"); 2190 return -EINVAL; 2191 } 2192 2193 count = fls->count; 2194 data = (u32 *)(fls->data); 2195 while (count >= 2) { 2196 status = chipio_write(codec, data[0], data[1]); 2197 if (status < 0) { 2198 snd_printdd(KERN_ERR "hci_write chipio failed\n"); 2199 return status; 2200 } 2201 count -= 2; 2202 data += 2; 2203 } 2204 return 0; 2205 } 2206 2207 /** 2208 * Write a block of data into DSP code or data RAM using pre-allocated 2209 * DMA engine. 2210 * 2211 * @codec: the HDA codec 2212 * @fls: pointer to a fast load image 2213 * @reloc: Relocation address for loading single-segment overlays, or 0 for 2214 * no relocation 2215 * @dma_engine: pointer to DMA engine to be used for DSP download 2216 * @dma_chan: The number of DMA channels used for DSP download 2217 * @port_map_mask: port mapping 2218 * @ovly: TRUE if overlay format is required 2219 * 2220 * Returns zero or a negative error code. 2221 */ 2222 static int dspxfr_one_seg(struct hda_codec *codec, 2223 const struct dsp_image_seg *fls, 2224 unsigned int reloc, 2225 struct dma_engine *dma_engine, 2226 unsigned int dma_chan, 2227 unsigned int port_map_mask, 2228 bool ovly) 2229 { 2230 int status = 0; 2231 bool comm_dma_setup_done = false; 2232 const unsigned int *data; 2233 unsigned int chip_addx; 2234 unsigned int words_to_write; 2235 unsigned int buffer_size_words; 2236 unsigned char *buffer_addx; 2237 unsigned short hda_format; 2238 unsigned int sample_rate_div; 2239 unsigned int sample_rate_mul; 2240 unsigned int num_chans; 2241 unsigned int hda_frame_size_words; 2242 unsigned int remainder_words; 2243 const u32 *data_remainder; 2244 u32 chip_addx_remainder; 2245 unsigned int run_size_words; 2246 const struct dsp_image_seg *hci_write = NULL; 2247 unsigned long timeout; 2248 bool dma_active; 2249 2250 if (fls == NULL) 2251 return -EINVAL; 2252 if (is_hci_prog_list_seg(fls)) { 2253 hci_write = fls; 2254 fls = get_next_seg_ptr(fls); 2255 } 2256 2257 if (hci_write && (!fls || is_last(fls))) { 2258 snd_printdd("hci_write\n"); 2259 return dspxfr_hci_write(codec, hci_write); 2260 } 2261 2262 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) { 2263 snd_printdd("Invalid Params\n"); 2264 return -EINVAL; 2265 } 2266 2267 data = fls->data; 2268 chip_addx = fls->chip_addr, 2269 words_to_write = fls->count; 2270 2271 if (!words_to_write) 2272 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0; 2273 if (reloc) 2274 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2); 2275 2276 if (!UC_RANGE(chip_addx, words_to_write) && 2277 !X_RANGE_ALL(chip_addx, words_to_write) && 2278 !Y_RANGE_ALL(chip_addx, words_to_write)) { 2279 snd_printdd("Invalid chip_addx Params\n"); 2280 return -EINVAL; 2281 } 2282 2283 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) / 2284 sizeof(u32); 2285 2286 buffer_addx = dma_get_buffer_addr(dma_engine); 2287 2288 if (buffer_addx == NULL) { 2289 snd_printdd(KERN_ERR "dma_engine buffer NULL\n"); 2290 return -EINVAL; 2291 } 2292 2293 dma_get_converter_format(dma_engine, &hda_format); 2294 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1; 2295 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1; 2296 num_chans = get_hdafmt_chs(hda_format) + 1; 2297 2298 hda_frame_size_words = ((sample_rate_div == 0) ? 0 : 2299 (num_chans * sample_rate_mul / sample_rate_div)); 2300 2301 if (hda_frame_size_words == 0) { 2302 snd_printdd(KERN_ERR "frmsz zero\n"); 2303 return -EINVAL; 2304 } 2305 2306 buffer_size_words = min(buffer_size_words, 2307 (unsigned int)(UC_RANGE(chip_addx, 1) ? 2308 65536 : 32768)); 2309 buffer_size_words -= buffer_size_words % hda_frame_size_words; 2310 snd_printdd( 2311 "chpadr=0x%08x frmsz=%u nchan=%u " 2312 "rate_mul=%u div=%u bufsz=%u\n", 2313 chip_addx, hda_frame_size_words, num_chans, 2314 sample_rate_mul, sample_rate_div, buffer_size_words); 2315 2316 if (buffer_size_words < hda_frame_size_words) { 2317 snd_printdd(KERN_ERR "dspxfr_one_seg:failed\n"); 2318 return -EINVAL; 2319 } 2320 2321 remainder_words = words_to_write % hda_frame_size_words; 2322 data_remainder = data; 2323 chip_addx_remainder = chip_addx; 2324 2325 data += remainder_words; 2326 chip_addx += remainder_words*sizeof(u32); 2327 words_to_write -= remainder_words; 2328 2329 while (words_to_write != 0) { 2330 run_size_words = min(buffer_size_words, words_to_write); 2331 snd_printdd("dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n", 2332 words_to_write, run_size_words, remainder_words); 2333 dma_xfer(dma_engine, data, run_size_words*sizeof(u32)); 2334 if (!comm_dma_setup_done) { 2335 status = dsp_dma_stop(codec, dma_chan, ovly); 2336 if (status < 0) 2337 return status; 2338 status = dsp_dma_setup_common(codec, chip_addx, 2339 dma_chan, port_map_mask, ovly); 2340 if (status < 0) 2341 return status; 2342 comm_dma_setup_done = true; 2343 } 2344 2345 status = dsp_dma_setup(codec, chip_addx, 2346 run_size_words, dma_chan); 2347 if (status < 0) 2348 return status; 2349 status = dsp_dma_start(codec, dma_chan, ovly); 2350 if (status < 0) 2351 return status; 2352 if (!dsp_is_dma_active(codec, dma_chan)) { 2353 snd_printdd(KERN_ERR "dspxfr:DMA did not start\n"); 2354 return -EIO; 2355 } 2356 status = dma_set_state(dma_engine, DMA_STATE_RUN); 2357 if (status < 0) 2358 return status; 2359 if (remainder_words != 0) { 2360 status = chipio_write_multiple(codec, 2361 chip_addx_remainder, 2362 data_remainder, 2363 remainder_words); 2364 if (status < 0) 2365 return status; 2366 remainder_words = 0; 2367 } 2368 if (hci_write) { 2369 status = dspxfr_hci_write(codec, hci_write); 2370 if (status < 0) 2371 return status; 2372 hci_write = NULL; 2373 } 2374 2375 timeout = jiffies + msecs_to_jiffies(2000); 2376 do { 2377 dma_active = dsp_is_dma_active(codec, dma_chan); 2378 if (!dma_active) 2379 break; 2380 msleep(20); 2381 } while (time_before(jiffies, timeout)); 2382 if (dma_active) 2383 break; 2384 2385 snd_printdd(KERN_INFO "+++++ DMA complete\n"); 2386 dma_set_state(dma_engine, DMA_STATE_STOP); 2387 status = dma_reset(dma_engine); 2388 2389 if (status < 0) 2390 return status; 2391 2392 data += run_size_words; 2393 chip_addx += run_size_words*sizeof(u32); 2394 words_to_write -= run_size_words; 2395 } 2396 2397 if (remainder_words != 0) { 2398 status = chipio_write_multiple(codec, chip_addx_remainder, 2399 data_remainder, remainder_words); 2400 } 2401 2402 return status; 2403 } 2404 2405 /** 2406 * Write the entire DSP image of a DSP code/data overlay to DSP memories 2407 * 2408 * @codec: the HDA codec 2409 * @fls_data: pointer to a fast load image 2410 * @reloc: Relocation address for loading single-segment overlays, or 0 for 2411 * no relocation 2412 * @sample_rate: sampling rate of the stream used for DSP download 2413 * @number_channels: channels of the stream used for DSP download 2414 * @ovly: TRUE if overlay format is required 2415 * 2416 * Returns zero or a negative error code. 2417 */ 2418 static int dspxfr_image(struct hda_codec *codec, 2419 const struct dsp_image_seg *fls_data, 2420 unsigned int reloc, 2421 unsigned int sample_rate, 2422 unsigned short channels, 2423 bool ovly) 2424 { 2425 struct ca0132_spec *spec = codec->spec; 2426 int status; 2427 unsigned short hda_format = 0; 2428 unsigned int response; 2429 unsigned char stream_id = 0; 2430 struct dma_engine *dma_engine; 2431 unsigned int dma_chan; 2432 unsigned int port_map_mask; 2433 2434 if (fls_data == NULL) 2435 return -EINVAL; 2436 2437 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL); 2438 if (!dma_engine) 2439 return -ENOMEM; 2440 2441 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL); 2442 if (!dma_engine->dmab) { 2443 kfree(dma_engine); 2444 return -ENOMEM; 2445 } 2446 2447 dma_engine->codec = codec; 2448 dma_convert_to_hda_format(sample_rate, channels, &hda_format); 2449 dma_engine->m_converter_format = hda_format; 2450 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY : 2451 DSP_DMA_WRITE_BUFLEN_INIT) * 2; 2452 2453 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0; 2454 2455 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL, 2456 hda_format, &response); 2457 2458 if (status < 0) { 2459 snd_printdd(KERN_ERR "set converter format fail\n"); 2460 goto exit; 2461 } 2462 2463 status = snd_hda_codec_load_dsp_prepare(codec, 2464 dma_engine->m_converter_format, 2465 dma_engine->buf_size, 2466 dma_engine->dmab); 2467 if (status < 0) 2468 goto exit; 2469 spec->dsp_stream_id = status; 2470 2471 if (ovly) { 2472 status = dspio_alloc_dma_chan(codec, &dma_chan); 2473 if (status < 0) { 2474 snd_printdd(KERN_ERR "alloc dmachan fail\n"); 2475 dma_chan = INVALID_DMA_CHANNEL; 2476 goto exit; 2477 } 2478 } 2479 2480 port_map_mask = 0; 2481 status = dsp_allocate_ports_format(codec, hda_format, 2482 &port_map_mask); 2483 if (status < 0) { 2484 snd_printdd(KERN_ERR "alloc ports fail\n"); 2485 goto exit; 2486 } 2487 2488 stream_id = dma_get_stream_id(dma_engine); 2489 status = codec_set_converter_stream_channel(codec, 2490 WIDGET_CHIP_CTRL, stream_id, 0, &response); 2491 if (status < 0) { 2492 snd_printdd(KERN_ERR "set stream chan fail\n"); 2493 goto exit; 2494 } 2495 2496 while ((fls_data != NULL) && !is_last(fls_data)) { 2497 if (!is_valid(fls_data)) { 2498 snd_printdd(KERN_ERR "FLS check fail\n"); 2499 status = -EINVAL; 2500 goto exit; 2501 } 2502 status = dspxfr_one_seg(codec, fls_data, reloc, 2503 dma_engine, dma_chan, 2504 port_map_mask, ovly); 2505 if (status < 0) 2506 break; 2507 2508 if (is_hci_prog_list_seg(fls_data)) 2509 fls_data = get_next_seg_ptr(fls_data); 2510 2511 if ((fls_data != NULL) && !is_last(fls_data)) 2512 fls_data = get_next_seg_ptr(fls_data); 2513 } 2514 2515 if (port_map_mask != 0) 2516 status = dsp_free_ports(codec); 2517 2518 if (status < 0) 2519 goto exit; 2520 2521 status = codec_set_converter_stream_channel(codec, 2522 WIDGET_CHIP_CTRL, 0, 0, &response); 2523 2524 exit: 2525 if (ovly && (dma_chan != INVALID_DMA_CHANNEL)) 2526 dspio_free_dma_chan(codec, dma_chan); 2527 2528 if (dma_engine->dmab->area) 2529 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab); 2530 kfree(dma_engine->dmab); 2531 kfree(dma_engine); 2532 2533 return status; 2534 } 2535 2536 /* 2537 * CA0132 DSP download stuffs. 2538 */ 2539 static void dspload_post_setup(struct hda_codec *codec) 2540 { 2541 snd_printdd(KERN_INFO "---- dspload_post_setup ------\n"); 2542 2543 /*set DSP speaker to 2.0 configuration*/ 2544 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080); 2545 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000); 2546 2547 /*update write pointer*/ 2548 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002); 2549 } 2550 2551 /** 2552 * Download DSP from a DSP Image Fast Load structure. This structure is a 2553 * linear, non-constant sized element array of structures, each of which 2554 * contain the count of the data to be loaded, the data itself, and the 2555 * corresponding starting chip address of the starting data location. 2556 * 2557 * @codec: the HDA codec 2558 * @fls: pointer to a fast load image 2559 * @ovly: TRUE if overlay format is required 2560 * @reloc: Relocation address for loading single-segment overlays, or 0 for 2561 * no relocation 2562 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE 2563 * @router_chans: number of audio router channels to be allocated (0 means use 2564 * internal defaults; max is 32) 2565 * 2566 * Returns zero or a negative error code. 2567 */ 2568 static int dspload_image(struct hda_codec *codec, 2569 const struct dsp_image_seg *fls, 2570 bool ovly, 2571 unsigned int reloc, 2572 bool autostart, 2573 int router_chans) 2574 { 2575 int status = 0; 2576 unsigned int sample_rate; 2577 unsigned short channels; 2578 2579 snd_printdd(KERN_INFO "---- dspload_image begin ------\n"); 2580 if (router_chans == 0) { 2581 if (!ovly) 2582 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS; 2583 else 2584 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS; 2585 } 2586 2587 sample_rate = 48000; 2588 channels = (unsigned short)router_chans; 2589 2590 while (channels > 16) { 2591 sample_rate *= 2; 2592 channels /= 2; 2593 } 2594 2595 do { 2596 snd_printdd(KERN_INFO "Ready to program DMA\n"); 2597 if (!ovly) 2598 status = dsp_reset(codec); 2599 2600 if (status < 0) 2601 break; 2602 2603 snd_printdd(KERN_INFO "dsp_reset() complete\n"); 2604 status = dspxfr_image(codec, fls, reloc, sample_rate, channels, 2605 ovly); 2606 2607 if (status < 0) 2608 break; 2609 2610 snd_printdd(KERN_INFO "dspxfr_image() complete\n"); 2611 if (autostart && !ovly) { 2612 dspload_post_setup(codec); 2613 status = dsp_set_run_state(codec); 2614 } 2615 2616 snd_printdd(KERN_INFO "LOAD FINISHED\n"); 2617 } while (0); 2618 2619 return status; 2620 } 2621 2622 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 2623 static bool dspload_is_loaded(struct hda_codec *codec) 2624 { 2625 unsigned int data = 0; 2626 int status = 0; 2627 2628 status = chipio_read(codec, 0x40004, &data); 2629 if ((status < 0) || (data != 1)) 2630 return false; 2631 2632 return true; 2633 } 2634 #else 2635 #define dspload_is_loaded(codec) false 2636 #endif 2637 2638 static bool dspload_wait_loaded(struct hda_codec *codec) 2639 { 2640 unsigned long timeout = jiffies + msecs_to_jiffies(2000); 2641 2642 do { 2643 if (dspload_is_loaded(codec)) { 2644 pr_info("ca0132 DOWNLOAD OK :-) DSP IS RUNNING.\n"); 2645 return true; 2646 } 2647 msleep(20); 2648 } while (time_before(jiffies, timeout)); 2649 2650 pr_err("ca0132 DOWNLOAD FAILED!!! DSP IS NOT RUNNING.\n"); 2651 return false; 2652 } 2653 2654 /* 2655 * PCM stuffs 2656 */ 2657 static void ca0132_setup_stream(struct hda_codec *codec, hda_nid_t nid, 2658 u32 stream_tag, 2659 int channel_id, int format) 2660 { 2661 unsigned int oldval, newval; 2662 2663 if (!nid) 2664 return; 2665 2666 snd_printdd( 2667 "ca0132_setup_stream: NID=0x%x, stream=0x%x, " 2668 "channel=%d, format=0x%x\n", 2669 nid, stream_tag, channel_id, format); 2670 2671 /* update the format-id if changed */ 2672 oldval = snd_hda_codec_read(codec, nid, 0, 2673 AC_VERB_GET_STREAM_FORMAT, 2674 0); 2675 if (oldval != format) { 2676 msleep(20); 2677 snd_hda_codec_write(codec, nid, 0, 2678 AC_VERB_SET_STREAM_FORMAT, 2679 format); 2680 } 2681 2682 oldval = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_CONV, 0); 2683 newval = (stream_tag << 4) | channel_id; 2684 if (oldval != newval) { 2685 snd_hda_codec_write(codec, nid, 0, 2686 AC_VERB_SET_CHANNEL_STREAMID, 2687 newval); 2688 } 2689 } 2690 2691 static void ca0132_cleanup_stream(struct hda_codec *codec, hda_nid_t nid) 2692 { 2693 unsigned int val; 2694 2695 if (!nid) 2696 return; 2697 2698 snd_printdd(KERN_INFO "ca0132_cleanup_stream: NID=0x%x\n", nid); 2699 2700 val = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_CONV, 0); 2701 if (!val) 2702 return; 2703 2704 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_STREAM_FORMAT, 0); 2705 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_CHANNEL_STREAMID, 0); 2706 } 2707 2708 /* 2709 * PCM callbacks 2710 */ 2711 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 2712 struct hda_codec *codec, 2713 unsigned int stream_tag, 2714 unsigned int format, 2715 struct snd_pcm_substream *substream) 2716 { 2717 struct ca0132_spec *spec = codec->spec; 2718 2719 ca0132_setup_stream(codec, spec->dacs[0], stream_tag, 0, format); 2720 2721 return 0; 2722 } 2723 2724 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 2725 struct hda_codec *codec, 2726 struct snd_pcm_substream *substream) 2727 { 2728 struct ca0132_spec *spec = codec->spec; 2729 2730 if (spec->dsp_state == DSP_DOWNLOADING) 2731 return 0; 2732 2733 /*If Playback effects are on, allow stream some time to flush 2734 *effects tail*/ 2735 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 2736 msleep(50); 2737 2738 ca0132_cleanup_stream(codec, spec->dacs[0]); 2739 2740 return 0; 2741 } 2742 2743 /* 2744 * Digital out 2745 */ 2746 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo, 2747 struct hda_codec *codec, 2748 struct snd_pcm_substream *substream) 2749 { 2750 struct ca0132_spec *spec = codec->spec; 2751 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 2752 } 2753 2754 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 2755 struct hda_codec *codec, 2756 unsigned int stream_tag, 2757 unsigned int format, 2758 struct snd_pcm_substream *substream) 2759 { 2760 struct ca0132_spec *spec = codec->spec; 2761 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 2762 stream_tag, format, substream); 2763 } 2764 2765 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 2766 struct hda_codec *codec, 2767 struct snd_pcm_substream *substream) 2768 { 2769 struct ca0132_spec *spec = codec->spec; 2770 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout); 2771 } 2772 2773 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo, 2774 struct hda_codec *codec, 2775 struct snd_pcm_substream *substream) 2776 { 2777 struct ca0132_spec *spec = codec->spec; 2778 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 2779 } 2780 2781 /* 2782 * Analog capture 2783 */ 2784 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo, 2785 struct hda_codec *codec, 2786 unsigned int stream_tag, 2787 unsigned int format, 2788 struct snd_pcm_substream *substream) 2789 { 2790 struct ca0132_spec *spec = codec->spec; 2791 2792 ca0132_setup_stream(codec, spec->adcs[substream->number], 2793 stream_tag, 0, format); 2794 2795 return 0; 2796 } 2797 2798 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo, 2799 struct hda_codec *codec, 2800 struct snd_pcm_substream *substream) 2801 { 2802 struct ca0132_spec *spec = codec->spec; 2803 2804 if (spec->dsp_state == DSP_DOWNLOADING) 2805 return 0; 2806 2807 ca0132_cleanup_stream(codec, hinfo->nid); 2808 return 0; 2809 } 2810 2811 /* 2812 * Controls stuffs. 2813 */ 2814 2815 /* 2816 * Mixer controls helpers. 2817 */ 2818 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \ 2819 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2820 .name = xname, \ 2821 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 2822 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 2823 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 2824 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 2825 .info = ca0132_volume_info, \ 2826 .get = ca0132_volume_get, \ 2827 .put = ca0132_volume_put, \ 2828 .tlv = { .c = ca0132_volume_tlv }, \ 2829 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 2830 2831 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \ 2832 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2833 .name = xname, \ 2834 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 2835 .info = snd_hda_mixer_amp_switch_info, \ 2836 .get = ca0132_switch_get, \ 2837 .put = ca0132_switch_put, \ 2838 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 2839 2840 /* stereo */ 2841 #define CA0132_CODEC_VOL(xname, nid, dir) \ 2842 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir) 2843 #define CA0132_CODEC_MUTE(xname, nid, dir) \ 2844 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir) 2845 2846 /* The followings are for tuning of products */ 2847 #ifdef ENABLE_TUNING_CONTROLS 2848 2849 static unsigned int voice_focus_vals_lookup[] = { 2850 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000, 2851 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000, 2852 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000, 2853 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000, 2854 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000, 2855 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000, 2856 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000, 2857 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000, 2858 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000, 2859 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000, 2860 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000, 2861 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000, 2862 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000, 2863 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000, 2864 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000, 2865 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000, 2866 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000, 2867 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000, 2868 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000, 2869 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000, 2870 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000, 2871 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000, 2872 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000, 2873 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000, 2874 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000, 2875 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000, 2876 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000 2877 }; 2878 2879 static unsigned int mic_svm_vals_lookup[] = { 2880 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 2881 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 2882 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 2883 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 2884 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 2885 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 2886 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 2887 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 2888 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 2889 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 2890 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 2891 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 2892 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 2893 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 2894 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 2895 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 2896 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 2897 }; 2898 2899 static unsigned int equalizer_vals_lookup[] = { 2900 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 2901 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 2902 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 2903 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 2904 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 2905 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000, 2906 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000, 2907 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 2908 0x41C00000 2909 }; 2910 2911 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid, 2912 unsigned int *lookup, int idx) 2913 { 2914 int i = 0; 2915 2916 for (i = 0; i < TUNING_CTLS_COUNT; i++) 2917 if (nid == ca0132_tuning_ctls[i].nid) 2918 break; 2919 2920 snd_hda_power_up(codec); 2921 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 2922 ca0132_tuning_ctls[i].req, 2923 &(lookup[idx]), sizeof(unsigned int)); 2924 snd_hda_power_down(codec); 2925 2926 return 1; 2927 } 2928 2929 static int tuning_ctl_get(struct snd_kcontrol *kcontrol, 2930 struct snd_ctl_elem_value *ucontrol) 2931 { 2932 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 2933 struct ca0132_spec *spec = codec->spec; 2934 hda_nid_t nid = get_amp_nid(kcontrol); 2935 long *valp = ucontrol->value.integer.value; 2936 int idx = nid - TUNING_CTL_START_NID; 2937 2938 *valp = spec->cur_ctl_vals[idx]; 2939 return 0; 2940 } 2941 2942 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol, 2943 struct snd_ctl_elem_info *uinfo) 2944 { 2945 int chs = get_amp_channels(kcontrol); 2946 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2947 uinfo->count = chs == 3 ? 2 : 1; 2948 uinfo->value.integer.min = 20; 2949 uinfo->value.integer.max = 180; 2950 uinfo->value.integer.step = 1; 2951 2952 return 0; 2953 } 2954 2955 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol, 2956 struct snd_ctl_elem_value *ucontrol) 2957 { 2958 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 2959 struct ca0132_spec *spec = codec->spec; 2960 hda_nid_t nid = get_amp_nid(kcontrol); 2961 long *valp = ucontrol->value.integer.value; 2962 int idx; 2963 2964 idx = nid - TUNING_CTL_START_NID; 2965 /* any change? */ 2966 if (spec->cur_ctl_vals[idx] == *valp) 2967 return 0; 2968 2969 spec->cur_ctl_vals[idx] = *valp; 2970 2971 idx = *valp - 20; 2972 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx); 2973 2974 return 1; 2975 } 2976 2977 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol, 2978 struct snd_ctl_elem_info *uinfo) 2979 { 2980 int chs = get_amp_channels(kcontrol); 2981 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2982 uinfo->count = chs == 3 ? 2 : 1; 2983 uinfo->value.integer.min = 0; 2984 uinfo->value.integer.max = 100; 2985 uinfo->value.integer.step = 1; 2986 2987 return 0; 2988 } 2989 2990 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol, 2991 struct snd_ctl_elem_value *ucontrol) 2992 { 2993 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 2994 struct ca0132_spec *spec = codec->spec; 2995 hda_nid_t nid = get_amp_nid(kcontrol); 2996 long *valp = ucontrol->value.integer.value; 2997 int idx; 2998 2999 idx = nid - TUNING_CTL_START_NID; 3000 /* any change? */ 3001 if (spec->cur_ctl_vals[idx] == *valp) 3002 return 0; 3003 3004 spec->cur_ctl_vals[idx] = *valp; 3005 3006 idx = *valp; 3007 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx); 3008 3009 return 0; 3010 } 3011 3012 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol, 3013 struct snd_ctl_elem_info *uinfo) 3014 { 3015 int chs = get_amp_channels(kcontrol); 3016 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3017 uinfo->count = chs == 3 ? 2 : 1; 3018 uinfo->value.integer.min = 0; 3019 uinfo->value.integer.max = 48; 3020 uinfo->value.integer.step = 1; 3021 3022 return 0; 3023 } 3024 3025 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol, 3026 struct snd_ctl_elem_value *ucontrol) 3027 { 3028 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3029 struct ca0132_spec *spec = codec->spec; 3030 hda_nid_t nid = get_amp_nid(kcontrol); 3031 long *valp = ucontrol->value.integer.value; 3032 int idx; 3033 3034 idx = nid - TUNING_CTL_START_NID; 3035 /* any change? */ 3036 if (spec->cur_ctl_vals[idx] == *valp) 3037 return 0; 3038 3039 spec->cur_ctl_vals[idx] = *valp; 3040 3041 idx = *valp; 3042 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx); 3043 3044 return 1; 3045 } 3046 3047 static const DECLARE_TLV_DB_SCALE(voice_focus_db_scale, 2000, 100, 0); 3048 static const DECLARE_TLV_DB_SCALE(eq_db_scale, -2400, 100, 0); 3049 3050 static int add_tuning_control(struct hda_codec *codec, 3051 hda_nid_t pnid, hda_nid_t nid, 3052 const char *name, int dir) 3053 { 3054 char namestr[44]; 3055 int type = dir ? HDA_INPUT : HDA_OUTPUT; 3056 struct snd_kcontrol_new knew = 3057 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 3058 3059 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 3060 SNDRV_CTL_ELEM_ACCESS_TLV_READ; 3061 knew.tlv.c = 0; 3062 knew.tlv.p = 0; 3063 switch (pnid) { 3064 case VOICE_FOCUS: 3065 knew.info = voice_focus_ctl_info; 3066 knew.get = tuning_ctl_get; 3067 knew.put = voice_focus_ctl_put; 3068 knew.tlv.p = voice_focus_db_scale; 3069 break; 3070 case MIC_SVM: 3071 knew.info = mic_svm_ctl_info; 3072 knew.get = tuning_ctl_get; 3073 knew.put = mic_svm_ctl_put; 3074 break; 3075 case EQUALIZER: 3076 knew.info = equalizer_ctl_info; 3077 knew.get = tuning_ctl_get; 3078 knew.put = equalizer_ctl_put; 3079 knew.tlv.p = eq_db_scale; 3080 break; 3081 default: 3082 return 0; 3083 } 3084 knew.private_value = 3085 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 3086 sprintf(namestr, "%s %s Volume", name, dirstr[dir]); 3087 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 3088 } 3089 3090 static int add_tuning_ctls(struct hda_codec *codec) 3091 { 3092 int i; 3093 int err; 3094 3095 for (i = 0; i < TUNING_CTLS_COUNT; i++) { 3096 err = add_tuning_control(codec, 3097 ca0132_tuning_ctls[i].parent_nid, 3098 ca0132_tuning_ctls[i].nid, 3099 ca0132_tuning_ctls[i].name, 3100 ca0132_tuning_ctls[i].direct); 3101 if (err < 0) 3102 return err; 3103 } 3104 3105 return 0; 3106 } 3107 3108 static void ca0132_init_tuning_defaults(struct hda_codec *codec) 3109 { 3110 struct ca0132_spec *spec = codec->spec; 3111 int i; 3112 3113 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */ 3114 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10; 3115 /* SVM level defaults to 0.74. */ 3116 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74; 3117 3118 /* EQ defaults to 0dB. */ 3119 for (i = 2; i < TUNING_CTLS_COUNT; i++) 3120 spec->cur_ctl_vals[i] = 24; 3121 } 3122 #endif /*ENABLE_TUNING_CONTROLS*/ 3123 3124 /* 3125 * Select the active output. 3126 * If autodetect is enabled, output will be selected based on jack detection. 3127 * If jack inserted, headphone will be selected, else built-in speakers 3128 * If autodetect is disabled, output will be selected based on selection. 3129 */ 3130 static int ca0132_select_out(struct hda_codec *codec) 3131 { 3132 struct ca0132_spec *spec = codec->spec; 3133 unsigned int pin_ctl; 3134 int jack_present; 3135 int auto_jack; 3136 unsigned int tmp; 3137 int err; 3138 3139 snd_printdd(KERN_INFO "ca0132_select_out\n"); 3140 3141 snd_hda_power_up(codec); 3142 3143 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 3144 3145 if (auto_jack) 3146 jack_present = snd_hda_jack_detect(codec, spec->out_pins[1]); 3147 else 3148 jack_present = 3149 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID]; 3150 3151 if (jack_present) 3152 spec->cur_out_type = HEADPHONE_OUT; 3153 else 3154 spec->cur_out_type = SPEAKER_OUT; 3155 3156 if (spec->cur_out_type == SPEAKER_OUT) { 3157 snd_printdd(KERN_INFO "ca0132_select_out speaker\n"); 3158 /*speaker out config*/ 3159 tmp = FLOAT_ONE; 3160 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 3161 if (err < 0) 3162 goto exit; 3163 /*enable speaker EQ*/ 3164 tmp = FLOAT_ONE; 3165 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 3166 if (err < 0) 3167 goto exit; 3168 3169 /* Setup EAPD */ 3170 snd_hda_codec_write(codec, spec->out_pins[1], 0, 3171 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 3172 snd_hda_codec_write(codec, spec->out_pins[0], 0, 3173 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 3174 snd_hda_codec_write(codec, spec->out_pins[0], 0, 3175 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 3176 snd_hda_codec_write(codec, spec->out_pins[0], 0, 3177 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 3178 3179 /* disable headphone node */ 3180 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 3181 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 3182 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 3183 pin_ctl & ~PIN_HP); 3184 /* enable speaker node */ 3185 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 3186 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 3187 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 3188 pin_ctl | PIN_OUT); 3189 } else { 3190 snd_printdd(KERN_INFO "ca0132_select_out hp\n"); 3191 /*headphone out config*/ 3192 tmp = FLOAT_ZERO; 3193 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 3194 if (err < 0) 3195 goto exit; 3196 /*disable speaker EQ*/ 3197 tmp = FLOAT_ZERO; 3198 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 3199 if (err < 0) 3200 goto exit; 3201 3202 /* Setup EAPD */ 3203 snd_hda_codec_write(codec, spec->out_pins[0], 0, 3204 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 3205 snd_hda_codec_write(codec, spec->out_pins[0], 0, 3206 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 3207 snd_hda_codec_write(codec, spec->out_pins[1], 0, 3208 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 3209 snd_hda_codec_write(codec, spec->out_pins[0], 0, 3210 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 3211 3212 /* disable speaker*/ 3213 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 3214 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 3215 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 3216 pin_ctl & ~PIN_HP); 3217 /* enable headphone*/ 3218 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 3219 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 3220 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 3221 pin_ctl | PIN_HP); 3222 } 3223 3224 exit: 3225 snd_hda_power_down(codec); 3226 3227 return err < 0 ? err : 0; 3228 } 3229 3230 static void ca0132_set_dmic(struct hda_codec *codec, int enable); 3231 static int ca0132_mic_boost_set(struct hda_codec *codec, long val); 3232 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val); 3233 3234 /* 3235 * Select the active VIP source 3236 */ 3237 static int ca0132_set_vipsource(struct hda_codec *codec, int val) 3238 { 3239 struct ca0132_spec *spec = codec->spec; 3240 unsigned int tmp; 3241 3242 if (!dspload_is_loaded(codec)) 3243 return 0; 3244 3245 /* if CrystalVoice if off, vipsource should be 0 */ 3246 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 3247 (val == 0)) { 3248 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 3249 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 3250 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 3251 if (spec->cur_mic_type == DIGITAL_MIC) 3252 tmp = FLOAT_TWO; 3253 else 3254 tmp = FLOAT_ONE; 3255 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 3256 tmp = FLOAT_ZERO; 3257 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 3258 } else { 3259 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 3260 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 3261 if (spec->cur_mic_type == DIGITAL_MIC) 3262 tmp = FLOAT_TWO; 3263 else 3264 tmp = FLOAT_ONE; 3265 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 3266 tmp = FLOAT_ONE; 3267 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 3268 msleep(20); 3269 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 3270 } 3271 3272 return 1; 3273 } 3274 3275 /* 3276 * Select the active microphone. 3277 * If autodetect is enabled, mic will be selected based on jack detection. 3278 * If jack inserted, ext.mic will be selected, else built-in mic 3279 * If autodetect is disabled, mic will be selected based on selection. 3280 */ 3281 static int ca0132_select_mic(struct hda_codec *codec) 3282 { 3283 struct ca0132_spec *spec = codec->spec; 3284 int jack_present; 3285 int auto_jack; 3286 3287 snd_printdd(KERN_INFO "ca0132_select_mic\n"); 3288 3289 snd_hda_power_up(codec); 3290 3291 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 3292 3293 if (auto_jack) 3294 jack_present = snd_hda_jack_detect(codec, spec->input_pins[0]); 3295 else 3296 jack_present = 3297 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID]; 3298 3299 if (jack_present) 3300 spec->cur_mic_type = LINE_MIC_IN; 3301 else 3302 spec->cur_mic_type = DIGITAL_MIC; 3303 3304 if (spec->cur_mic_type == DIGITAL_MIC) { 3305 /* enable digital Mic */ 3306 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000); 3307 ca0132_set_dmic(codec, 1); 3308 ca0132_mic_boost_set(codec, 0); 3309 /* set voice focus */ 3310 ca0132_effects_set(codec, VOICE_FOCUS, 3311 spec->effects_switch 3312 [VOICE_FOCUS - EFFECT_START_NID]); 3313 } else { 3314 /* disable digital Mic */ 3315 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000); 3316 ca0132_set_dmic(codec, 0); 3317 ca0132_mic_boost_set(codec, spec->cur_mic_boost); 3318 /* disable voice focus */ 3319 ca0132_effects_set(codec, VOICE_FOCUS, 0); 3320 } 3321 3322 snd_hda_power_down(codec); 3323 3324 return 0; 3325 } 3326 3327 /* 3328 * Check if VNODE settings take effect immediately. 3329 */ 3330 static bool ca0132_is_vnode_effective(struct hda_codec *codec, 3331 hda_nid_t vnid, 3332 hda_nid_t *shared_nid) 3333 { 3334 struct ca0132_spec *spec = codec->spec; 3335 hda_nid_t nid; 3336 3337 switch (vnid) { 3338 case VNID_SPK: 3339 nid = spec->shared_out_nid; 3340 break; 3341 case VNID_MIC: 3342 nid = spec->shared_mic_nid; 3343 break; 3344 default: 3345 return false; 3346 } 3347 3348 if (shared_nid) 3349 *shared_nid = nid; 3350 3351 return true; 3352 } 3353 3354 /* 3355 * The following functions are control change helpers. 3356 * They return 0 if no changed. Return 1 if changed. 3357 */ 3358 static int ca0132_voicefx_set(struct hda_codec *codec, int enable) 3359 { 3360 struct ca0132_spec *spec = codec->spec; 3361 unsigned int tmp; 3362 3363 /* based on CrystalVoice state to enable VoiceFX. */ 3364 if (enable) { 3365 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ? 3366 FLOAT_ONE : FLOAT_ZERO; 3367 } else { 3368 tmp = FLOAT_ZERO; 3369 } 3370 3371 dspio_set_uint_param(codec, ca0132_voicefx.mid, 3372 ca0132_voicefx.reqs[0], tmp); 3373 3374 return 1; 3375 } 3376 3377 /* 3378 * Set the effects parameters 3379 */ 3380 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val) 3381 { 3382 struct ca0132_spec *spec = codec->spec; 3383 unsigned int on; 3384 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 3385 int err = 0; 3386 int idx = nid - EFFECT_START_NID; 3387 3388 if ((idx < 0) || (idx >= num_fx)) 3389 return 0; /* no changed */ 3390 3391 /* for out effect, qualify with PE */ 3392 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) { 3393 /* if PE if off, turn off out effects. */ 3394 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 3395 val = 0; 3396 } 3397 3398 /* for in effect, qualify with CrystalVoice */ 3399 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) { 3400 /* if CrystalVoice if off, turn off in effects. */ 3401 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 3402 val = 0; 3403 3404 /* Voice Focus applies to 2-ch Mic, Digital Mic */ 3405 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC)) 3406 val = 0; 3407 } 3408 3409 snd_printdd(KERN_INFO "ca0132_effect_set: nid=0x%x, val=%ld\n", 3410 nid, val); 3411 3412 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE; 3413 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid, 3414 ca0132_effects[idx].reqs[0], on); 3415 3416 if (err < 0) 3417 return 0; /* no changed */ 3418 3419 return 1; 3420 } 3421 3422 /* 3423 * Turn on/off Playback Enhancements 3424 */ 3425 static int ca0132_pe_switch_set(struct hda_codec *codec) 3426 { 3427 struct ca0132_spec *spec = codec->spec; 3428 hda_nid_t nid; 3429 int i, ret = 0; 3430 3431 snd_printdd(KERN_INFO "ca0132_pe_switch_set: val=%ld\n", 3432 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]); 3433 3434 i = OUT_EFFECT_START_NID - EFFECT_START_NID; 3435 nid = OUT_EFFECT_START_NID; 3436 /* PE affects all out effects */ 3437 for (; nid < OUT_EFFECT_END_NID; nid++, i++) 3438 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 3439 3440 return ret; 3441 } 3442 3443 /* Check if Mic1 is streaming, if so, stop streaming */ 3444 static int stop_mic1(struct hda_codec *codec) 3445 { 3446 struct ca0132_spec *spec = codec->spec; 3447 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0, 3448 AC_VERB_GET_CONV, 0); 3449 if (oldval != 0) 3450 snd_hda_codec_write(codec, spec->adcs[0], 0, 3451 AC_VERB_SET_CHANNEL_STREAMID, 3452 0); 3453 return oldval; 3454 } 3455 3456 /* Resume Mic1 streaming if it was stopped. */ 3457 static void resume_mic1(struct hda_codec *codec, unsigned int oldval) 3458 { 3459 struct ca0132_spec *spec = codec->spec; 3460 /* Restore the previous stream and channel */ 3461 if (oldval != 0) 3462 snd_hda_codec_write(codec, spec->adcs[0], 0, 3463 AC_VERB_SET_CHANNEL_STREAMID, 3464 oldval); 3465 } 3466 3467 /* 3468 * Turn on/off CrystalVoice 3469 */ 3470 static int ca0132_cvoice_switch_set(struct hda_codec *codec) 3471 { 3472 struct ca0132_spec *spec = codec->spec; 3473 hda_nid_t nid; 3474 int i, ret = 0; 3475 unsigned int oldval; 3476 3477 snd_printdd(KERN_INFO "ca0132_cvoice_switch_set: val=%ld\n", 3478 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]); 3479 3480 i = IN_EFFECT_START_NID - EFFECT_START_NID; 3481 nid = IN_EFFECT_START_NID; 3482 /* CrystalVoice affects all in effects */ 3483 for (; nid < IN_EFFECT_END_NID; nid++, i++) 3484 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 3485 3486 /* including VoiceFX */ 3487 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0)); 3488 3489 /* set correct vipsource */ 3490 oldval = stop_mic1(codec); 3491 ret |= ca0132_set_vipsource(codec, 1); 3492 resume_mic1(codec, oldval); 3493 return ret; 3494 } 3495 3496 static int ca0132_mic_boost_set(struct hda_codec *codec, long val) 3497 { 3498 struct ca0132_spec *spec = codec->spec; 3499 int ret = 0; 3500 3501 if (val) /* on */ 3502 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 3503 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3); 3504 else /* off */ 3505 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 3506 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0); 3507 3508 return ret; 3509 } 3510 3511 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol, 3512 struct snd_ctl_elem_value *ucontrol) 3513 { 3514 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3515 hda_nid_t nid = get_amp_nid(kcontrol); 3516 hda_nid_t shared_nid = 0; 3517 bool effective; 3518 int ret = 0; 3519 struct ca0132_spec *spec = codec->spec; 3520 int auto_jack; 3521 3522 if (nid == VNID_HP_SEL) { 3523 auto_jack = 3524 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 3525 if (!auto_jack) 3526 ca0132_select_out(codec); 3527 return 1; 3528 } 3529 3530 if (nid == VNID_AMIC1_SEL) { 3531 auto_jack = 3532 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 3533 if (!auto_jack) 3534 ca0132_select_mic(codec); 3535 return 1; 3536 } 3537 3538 if (nid == VNID_HP_ASEL) { 3539 ca0132_select_out(codec); 3540 return 1; 3541 } 3542 3543 if (nid == VNID_AMIC1_ASEL) { 3544 ca0132_select_mic(codec); 3545 return 1; 3546 } 3547 3548 /* if effective conditions, then update hw immediately. */ 3549 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 3550 if (effective) { 3551 int dir = get_amp_direction(kcontrol); 3552 int ch = get_amp_channels(kcontrol); 3553 unsigned long pval; 3554 3555 mutex_lock(&codec->control_mutex); 3556 pval = kcontrol->private_value; 3557 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 3558 0, dir); 3559 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol); 3560 kcontrol->private_value = pval; 3561 mutex_unlock(&codec->control_mutex); 3562 } 3563 3564 return ret; 3565 } 3566 /* End of control change helpers. */ 3567 3568 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol, 3569 struct snd_ctl_elem_info *uinfo) 3570 { 3571 unsigned int items = sizeof(ca0132_voicefx_presets) 3572 / sizeof(struct ct_voicefx_preset); 3573 3574 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3575 uinfo->count = 1; 3576 uinfo->value.enumerated.items = items; 3577 if (uinfo->value.enumerated.item >= items) 3578 uinfo->value.enumerated.item = items - 1; 3579 strcpy(uinfo->value.enumerated.name, 3580 ca0132_voicefx_presets[uinfo->value.enumerated.item].name); 3581 return 0; 3582 } 3583 3584 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol, 3585 struct snd_ctl_elem_value *ucontrol) 3586 { 3587 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3588 struct ca0132_spec *spec = codec->spec; 3589 3590 ucontrol->value.enumerated.item[0] = spec->voicefx_val; 3591 return 0; 3592 } 3593 3594 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol, 3595 struct snd_ctl_elem_value *ucontrol) 3596 { 3597 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3598 struct ca0132_spec *spec = codec->spec; 3599 int i, err = 0; 3600 int sel = ucontrol->value.enumerated.item[0]; 3601 unsigned int items = sizeof(ca0132_voicefx_presets) 3602 / sizeof(struct ct_voicefx_preset); 3603 3604 if (sel >= items) 3605 return 0; 3606 3607 snd_printdd(KERN_INFO "ca0132_voicefx_put: sel=%d, preset=%s\n", 3608 sel, ca0132_voicefx_presets[sel].name); 3609 3610 /* 3611 * Idx 0 is default. 3612 * Default needs to qualify with CrystalVoice state. 3613 */ 3614 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) { 3615 err = dspio_set_uint_param(codec, ca0132_voicefx.mid, 3616 ca0132_voicefx.reqs[i], 3617 ca0132_voicefx_presets[sel].vals[i]); 3618 if (err < 0) 3619 break; 3620 } 3621 3622 if (err >= 0) { 3623 spec->voicefx_val = sel; 3624 /* enable voice fx */ 3625 ca0132_voicefx_set(codec, (sel ? 1 : 0)); 3626 } 3627 3628 return 1; 3629 } 3630 3631 static int ca0132_switch_get(struct snd_kcontrol *kcontrol, 3632 struct snd_ctl_elem_value *ucontrol) 3633 { 3634 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3635 struct ca0132_spec *spec = codec->spec; 3636 hda_nid_t nid = get_amp_nid(kcontrol); 3637 int ch = get_amp_channels(kcontrol); 3638 long *valp = ucontrol->value.integer.value; 3639 3640 /* vnode */ 3641 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 3642 if (ch & 1) { 3643 *valp = spec->vnode_lswitch[nid - VNODE_START_NID]; 3644 valp++; 3645 } 3646 if (ch & 2) { 3647 *valp = spec->vnode_rswitch[nid - VNODE_START_NID]; 3648 valp++; 3649 } 3650 return 0; 3651 } 3652 3653 /* effects, include PE and CrystalVoice */ 3654 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) { 3655 *valp = spec->effects_switch[nid - EFFECT_START_NID]; 3656 return 0; 3657 } 3658 3659 /* mic boost */ 3660 if (nid == spec->input_pins[0]) { 3661 *valp = spec->cur_mic_boost; 3662 return 0; 3663 } 3664 3665 return 0; 3666 } 3667 3668 static int ca0132_switch_put(struct snd_kcontrol *kcontrol, 3669 struct snd_ctl_elem_value *ucontrol) 3670 { 3671 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3672 struct ca0132_spec *spec = codec->spec; 3673 hda_nid_t nid = get_amp_nid(kcontrol); 3674 int ch = get_amp_channels(kcontrol); 3675 long *valp = ucontrol->value.integer.value; 3676 int changed = 1; 3677 3678 snd_printdd(KERN_INFO "ca0132_switch_put: nid=0x%x, val=%ld\n", 3679 nid, *valp); 3680 3681 snd_hda_power_up(codec); 3682 /* vnode */ 3683 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 3684 if (ch & 1) { 3685 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp; 3686 valp++; 3687 } 3688 if (ch & 2) { 3689 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp; 3690 valp++; 3691 } 3692 changed = ca0132_vnode_switch_set(kcontrol, ucontrol); 3693 goto exit; 3694 } 3695 3696 /* PE */ 3697 if (nid == PLAY_ENHANCEMENT) { 3698 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 3699 changed = ca0132_pe_switch_set(codec); 3700 goto exit; 3701 } 3702 3703 /* CrystalVoice */ 3704 if (nid == CRYSTAL_VOICE) { 3705 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 3706 changed = ca0132_cvoice_switch_set(codec); 3707 goto exit; 3708 } 3709 3710 /* out and in effects */ 3711 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) || 3712 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) { 3713 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 3714 changed = ca0132_effects_set(codec, nid, *valp); 3715 goto exit; 3716 } 3717 3718 /* mic boost */ 3719 if (nid == spec->input_pins[0]) { 3720 spec->cur_mic_boost = *valp; 3721 3722 /* Mic boost does not apply to Digital Mic */ 3723 if (spec->cur_mic_type != DIGITAL_MIC) 3724 changed = ca0132_mic_boost_set(codec, *valp); 3725 goto exit; 3726 } 3727 3728 exit: 3729 snd_hda_power_down(codec); 3730 return changed; 3731 } 3732 3733 /* 3734 * Volume related 3735 */ 3736 static int ca0132_volume_info(struct snd_kcontrol *kcontrol, 3737 struct snd_ctl_elem_info *uinfo) 3738 { 3739 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3740 struct ca0132_spec *spec = codec->spec; 3741 hda_nid_t nid = get_amp_nid(kcontrol); 3742 int ch = get_amp_channels(kcontrol); 3743 int dir = get_amp_direction(kcontrol); 3744 unsigned long pval; 3745 int err; 3746 3747 switch (nid) { 3748 case VNID_SPK: 3749 /* follow shared_out info */ 3750 nid = spec->shared_out_nid; 3751 mutex_lock(&codec->control_mutex); 3752 pval = kcontrol->private_value; 3753 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 3754 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 3755 kcontrol->private_value = pval; 3756 mutex_unlock(&codec->control_mutex); 3757 break; 3758 case VNID_MIC: 3759 /* follow shared_mic info */ 3760 nid = spec->shared_mic_nid; 3761 mutex_lock(&codec->control_mutex); 3762 pval = kcontrol->private_value; 3763 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 3764 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 3765 kcontrol->private_value = pval; 3766 mutex_unlock(&codec->control_mutex); 3767 break; 3768 default: 3769 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 3770 } 3771 return err; 3772 } 3773 3774 static int ca0132_volume_get(struct snd_kcontrol *kcontrol, 3775 struct snd_ctl_elem_value *ucontrol) 3776 { 3777 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3778 struct ca0132_spec *spec = codec->spec; 3779 hda_nid_t nid = get_amp_nid(kcontrol); 3780 int ch = get_amp_channels(kcontrol); 3781 long *valp = ucontrol->value.integer.value; 3782 3783 /* store the left and right volume */ 3784 if (ch & 1) { 3785 *valp = spec->vnode_lvol[nid - VNODE_START_NID]; 3786 valp++; 3787 } 3788 if (ch & 2) { 3789 *valp = spec->vnode_rvol[nid - VNODE_START_NID]; 3790 valp++; 3791 } 3792 return 0; 3793 } 3794 3795 static int ca0132_volume_put(struct snd_kcontrol *kcontrol, 3796 struct snd_ctl_elem_value *ucontrol) 3797 { 3798 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3799 struct ca0132_spec *spec = codec->spec; 3800 hda_nid_t nid = get_amp_nid(kcontrol); 3801 int ch = get_amp_channels(kcontrol); 3802 long *valp = ucontrol->value.integer.value; 3803 hda_nid_t shared_nid = 0; 3804 bool effective; 3805 int changed = 1; 3806 3807 /* store the left and right volume */ 3808 if (ch & 1) { 3809 spec->vnode_lvol[nid - VNODE_START_NID] = *valp; 3810 valp++; 3811 } 3812 if (ch & 2) { 3813 spec->vnode_rvol[nid - VNODE_START_NID] = *valp; 3814 valp++; 3815 } 3816 3817 /* if effective conditions, then update hw immediately. */ 3818 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 3819 if (effective) { 3820 int dir = get_amp_direction(kcontrol); 3821 unsigned long pval; 3822 3823 snd_hda_power_up(codec); 3824 mutex_lock(&codec->control_mutex); 3825 pval = kcontrol->private_value; 3826 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 3827 0, dir); 3828 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 3829 kcontrol->private_value = pval; 3830 mutex_unlock(&codec->control_mutex); 3831 snd_hda_power_down(codec); 3832 } 3833 3834 return changed; 3835 } 3836 3837 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag, 3838 unsigned int size, unsigned int __user *tlv) 3839 { 3840 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3841 struct ca0132_spec *spec = codec->spec; 3842 hda_nid_t nid = get_amp_nid(kcontrol); 3843 int ch = get_amp_channels(kcontrol); 3844 int dir = get_amp_direction(kcontrol); 3845 unsigned long pval; 3846 int err; 3847 3848 switch (nid) { 3849 case VNID_SPK: 3850 /* follow shared_out tlv */ 3851 nid = spec->shared_out_nid; 3852 mutex_lock(&codec->control_mutex); 3853 pval = kcontrol->private_value; 3854 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 3855 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 3856 kcontrol->private_value = pval; 3857 mutex_unlock(&codec->control_mutex); 3858 break; 3859 case VNID_MIC: 3860 /* follow shared_mic tlv */ 3861 nid = spec->shared_mic_nid; 3862 mutex_lock(&codec->control_mutex); 3863 pval = kcontrol->private_value; 3864 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 3865 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 3866 kcontrol->private_value = pval; 3867 mutex_unlock(&codec->control_mutex); 3868 break; 3869 default: 3870 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 3871 } 3872 return err; 3873 } 3874 3875 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid, 3876 const char *pfx, int dir) 3877 { 3878 char namestr[44]; 3879 int type = dir ? HDA_INPUT : HDA_OUTPUT; 3880 struct snd_kcontrol_new knew = 3881 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type); 3882 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]); 3883 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 3884 } 3885 3886 static int add_voicefx(struct hda_codec *codec) 3887 { 3888 struct snd_kcontrol_new knew = 3889 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name, 3890 VOICEFX, 1, 0, HDA_INPUT); 3891 knew.info = ca0132_voicefx_info; 3892 knew.get = ca0132_voicefx_get; 3893 knew.put = ca0132_voicefx_put; 3894 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec)); 3895 } 3896 3897 /* 3898 * When changing Node IDs for Mixer Controls below, make sure to update 3899 * Node IDs in ca0132_config() as well. 3900 */ 3901 static struct snd_kcontrol_new ca0132_mixer[] = { 3902 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT), 3903 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT), 3904 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 3905 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 3906 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT), 3907 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT), 3908 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 3909 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 3910 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch", 3911 0x12, 1, HDA_INPUT), 3912 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch", 3913 VNID_HP_SEL, 1, HDA_OUTPUT), 3914 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch", 3915 VNID_AMIC1_SEL, 1, HDA_INPUT), 3916 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 3917 VNID_HP_ASEL, 1, HDA_OUTPUT), 3918 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch", 3919 VNID_AMIC1_ASEL, 1, HDA_INPUT), 3920 { } /* end */ 3921 }; 3922 3923 static int ca0132_build_controls(struct hda_codec *codec) 3924 { 3925 struct ca0132_spec *spec = codec->spec; 3926 int i, num_fx; 3927 int err = 0; 3928 3929 /* Add Mixer controls */ 3930 for (i = 0; i < spec->num_mixers; i++) { 3931 err = snd_hda_add_new_ctls(codec, spec->mixers[i]); 3932 if (err < 0) 3933 return err; 3934 } 3935 3936 /* Add in and out effects controls. 3937 * VoiceFX, PE and CrystalVoice are added separately. 3938 */ 3939 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 3940 for (i = 0; i < num_fx; i++) { 3941 err = add_fx_switch(codec, ca0132_effects[i].nid, 3942 ca0132_effects[i].name, 3943 ca0132_effects[i].direct); 3944 if (err < 0) 3945 return err; 3946 } 3947 3948 err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0); 3949 if (err < 0) 3950 return err; 3951 3952 err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1); 3953 if (err < 0) 3954 return err; 3955 3956 add_voicefx(codec); 3957 3958 #ifdef ENABLE_TUNING_CONTROLS 3959 add_tuning_ctls(codec); 3960 #endif 3961 3962 err = snd_hda_jack_add_kctls(codec, &spec->autocfg); 3963 if (err < 0) 3964 return err; 3965 3966 if (spec->dig_out) { 3967 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 3968 spec->dig_out); 3969 if (err < 0) 3970 return err; 3971 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout); 3972 if (err < 0) 3973 return err; 3974 /* spec->multiout.share_spdif = 1; */ 3975 } 3976 3977 if (spec->dig_in) { 3978 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 3979 if (err < 0) 3980 return err; 3981 } 3982 return 0; 3983 } 3984 3985 /* 3986 * PCM 3987 */ 3988 static struct hda_pcm_stream ca0132_pcm_analog_playback = { 3989 .substreams = 1, 3990 .channels_min = 2, 3991 .channels_max = 6, 3992 .ops = { 3993 .prepare = ca0132_playback_pcm_prepare, 3994 .cleanup = ca0132_playback_pcm_cleanup 3995 }, 3996 }; 3997 3998 static struct hda_pcm_stream ca0132_pcm_analog_capture = { 3999 .substreams = 1, 4000 .channels_min = 2, 4001 .channels_max = 2, 4002 .ops = { 4003 .prepare = ca0132_capture_pcm_prepare, 4004 .cleanup = ca0132_capture_pcm_cleanup 4005 }, 4006 }; 4007 4008 static struct hda_pcm_stream ca0132_pcm_digital_playback = { 4009 .substreams = 1, 4010 .channels_min = 2, 4011 .channels_max = 2, 4012 .ops = { 4013 .open = ca0132_dig_playback_pcm_open, 4014 .close = ca0132_dig_playback_pcm_close, 4015 .prepare = ca0132_dig_playback_pcm_prepare, 4016 .cleanup = ca0132_dig_playback_pcm_cleanup 4017 }, 4018 }; 4019 4020 static struct hda_pcm_stream ca0132_pcm_digital_capture = { 4021 .substreams = 1, 4022 .channels_min = 2, 4023 .channels_max = 2, 4024 }; 4025 4026 static int ca0132_build_pcms(struct hda_codec *codec) 4027 { 4028 struct ca0132_spec *spec = codec->spec; 4029 struct hda_pcm *info = spec->pcm_rec; 4030 4031 codec->pcm_info = info; 4032 codec->num_pcms = 0; 4033 4034 info->name = "CA0132 Analog"; 4035 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback; 4036 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0]; 4037 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max = 4038 spec->multiout.max_channels; 4039 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 4040 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 4041 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 4042 codec->num_pcms++; 4043 4044 info++; 4045 info->name = "CA0132 Analog Mic-In2"; 4046 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 4047 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 4048 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1]; 4049 codec->num_pcms++; 4050 4051 info++; 4052 info->name = "CA0132 What U Hear"; 4053 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 4054 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 4055 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2]; 4056 codec->num_pcms++; 4057 4058 if (!spec->dig_out && !spec->dig_in) 4059 return 0; 4060 4061 info++; 4062 info->name = "CA0132 Digital"; 4063 info->pcm_type = HDA_PCM_TYPE_SPDIF; 4064 if (spec->dig_out) { 4065 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 4066 ca0132_pcm_digital_playback; 4067 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 4068 } 4069 if (spec->dig_in) { 4070 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 4071 ca0132_pcm_digital_capture; 4072 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 4073 } 4074 codec->num_pcms++; 4075 4076 return 0; 4077 } 4078 4079 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac) 4080 { 4081 if (pin) { 4082 snd_hda_set_pin_ctl(codec, pin, PIN_HP); 4083 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 4084 snd_hda_codec_write(codec, pin, 0, 4085 AC_VERB_SET_AMP_GAIN_MUTE, 4086 AMP_OUT_UNMUTE); 4087 } 4088 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP)) 4089 snd_hda_codec_write(codec, dac, 0, 4090 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO); 4091 } 4092 4093 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc) 4094 { 4095 if (pin) { 4096 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80); 4097 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP) 4098 snd_hda_codec_write(codec, pin, 0, 4099 AC_VERB_SET_AMP_GAIN_MUTE, 4100 AMP_IN_UNMUTE(0)); 4101 } 4102 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) { 4103 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE, 4104 AMP_IN_UNMUTE(0)); 4105 4106 /* init to 0 dB and unmute. */ 4107 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 4108 HDA_AMP_VOLMASK, 0x5a); 4109 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 4110 HDA_AMP_MUTE, 0); 4111 } 4112 } 4113 4114 static void ca0132_init_unsol(struct hda_codec *codec) 4115 { 4116 snd_hda_jack_detect_enable(codec, UNSOL_TAG_HP, UNSOL_TAG_HP); 4117 snd_hda_jack_detect_enable(codec, UNSOL_TAG_AMIC1, UNSOL_TAG_AMIC1); 4118 } 4119 4120 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir) 4121 { 4122 unsigned int caps; 4123 4124 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ? 4125 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP); 4126 snd_hda_override_amp_caps(codec, nid, dir, caps); 4127 } 4128 4129 /* 4130 * Switch between Digital built-in mic and analog mic. 4131 */ 4132 static void ca0132_set_dmic(struct hda_codec *codec, int enable) 4133 { 4134 struct ca0132_spec *spec = codec->spec; 4135 unsigned int tmp; 4136 u8 val; 4137 unsigned int oldval; 4138 4139 snd_printdd(KERN_INFO "ca0132_set_dmic: enable=%d\n", enable); 4140 4141 oldval = stop_mic1(codec); 4142 ca0132_set_vipsource(codec, 0); 4143 if (enable) { 4144 /* set DMic input as 2-ch */ 4145 tmp = FLOAT_TWO; 4146 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4147 4148 val = spec->dmic_ctl; 4149 val |= 0x80; 4150 snd_hda_codec_write(codec, spec->input_pins[0], 0, 4151 VENDOR_CHIPIO_DMIC_CTL_SET, val); 4152 4153 if (!(spec->dmic_ctl & 0x20)) 4154 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1); 4155 } else { 4156 /* set AMic input as mono */ 4157 tmp = FLOAT_ONE; 4158 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4159 4160 val = spec->dmic_ctl; 4161 /* clear bit7 and bit5 to disable dmic */ 4162 val &= 0x5f; 4163 snd_hda_codec_write(codec, spec->input_pins[0], 0, 4164 VENDOR_CHIPIO_DMIC_CTL_SET, val); 4165 4166 if (!(spec->dmic_ctl & 0x20)) 4167 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0); 4168 } 4169 ca0132_set_vipsource(codec, 1); 4170 resume_mic1(codec, oldval); 4171 } 4172 4173 /* 4174 * Initialization for Digital Mic. 4175 */ 4176 static void ca0132_init_dmic(struct hda_codec *codec) 4177 { 4178 struct ca0132_spec *spec = codec->spec; 4179 u8 val; 4180 4181 /* Setup Digital Mic here, but don't enable. 4182 * Enable based on jack detect. 4183 */ 4184 4185 /* MCLK uses MPIO1, set to enable. 4186 * Bit 2-0: MPIO select 4187 * Bit 3: set to disable 4188 * Bit 7-4: reserved 4189 */ 4190 val = 0x01; 4191 snd_hda_codec_write(codec, spec->input_pins[0], 0, 4192 VENDOR_CHIPIO_DMIC_MCLK_SET, val); 4193 4194 /* Data1 uses MPIO3. Data2 not use 4195 * Bit 2-0: Data1 MPIO select 4196 * Bit 3: set disable Data1 4197 * Bit 6-4: Data2 MPIO select 4198 * Bit 7: set disable Data2 4199 */ 4200 val = 0x83; 4201 snd_hda_codec_write(codec, spec->input_pins[0], 0, 4202 VENDOR_CHIPIO_DMIC_PIN_SET, val); 4203 4204 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first. 4205 * Bit 3-0: Channel mask 4206 * Bit 4: set for 48KHz, clear for 32KHz 4207 * Bit 5: mode 4208 * Bit 6: set to select Data2, clear for Data1 4209 * Bit 7: set to enable DMic, clear for AMic 4210 */ 4211 val = 0x23; 4212 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */ 4213 spec->dmic_ctl = val; 4214 snd_hda_codec_write(codec, spec->input_pins[0], 0, 4215 VENDOR_CHIPIO_DMIC_CTL_SET, val); 4216 } 4217 4218 /* 4219 * Initialization for Analog Mic 2 4220 */ 4221 static void ca0132_init_analog_mic2(struct hda_codec *codec) 4222 { 4223 struct ca0132_spec *spec = codec->spec; 4224 4225 mutex_lock(&spec->chipio_mutex); 4226 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 4227 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); 4228 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 4229 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 4230 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 4231 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 4232 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 4233 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D); 4234 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 4235 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 4236 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 4237 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 4238 mutex_unlock(&spec->chipio_mutex); 4239 } 4240 4241 static void ca0132_refresh_widget_caps(struct hda_codec *codec) 4242 { 4243 struct ca0132_spec *spec = codec->spec; 4244 int i; 4245 hda_nid_t nid; 4246 4247 snd_printdd(KERN_INFO "ca0132_refresh_widget_caps.\n"); 4248 nid = codec->start_nid; 4249 for (i = 0; i < codec->num_nodes; i++, nid++) 4250 codec->wcaps[i] = snd_hda_param_read(codec, nid, 4251 AC_PAR_AUDIO_WIDGET_CAP); 4252 4253 for (i = 0; i < spec->multiout.num_dacs; i++) 4254 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT); 4255 4256 for (i = 0; i < spec->num_outputs; i++) 4257 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT); 4258 4259 for (i = 0; i < spec->num_inputs; i++) { 4260 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT); 4261 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT); 4262 } 4263 } 4264 4265 /* 4266 * Setup default parameters for DSP 4267 */ 4268 static void ca0132_setup_defaults(struct hda_codec *codec) 4269 { 4270 unsigned int tmp; 4271 int num_fx; 4272 int idx, i; 4273 4274 if (!dspload_is_loaded(codec)) 4275 return; 4276 4277 /* out, in effects + voicefx */ 4278 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 4279 for (idx = 0; idx < num_fx; idx++) { 4280 for (i = 0; i <= ca0132_effects[idx].params; i++) { 4281 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 4282 ca0132_effects[idx].reqs[i], 4283 ca0132_effects[idx].def_vals[i]); 4284 } 4285 } 4286 4287 /*remove DSP headroom*/ 4288 tmp = FLOAT_ZERO; 4289 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 4290 4291 /*set speaker EQ bypass attenuation*/ 4292 dspio_set_uint_param(codec, 0x8f, 0x01, tmp); 4293 4294 /* set AMic1 and AMic2 as mono mic */ 4295 tmp = FLOAT_ONE; 4296 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4297 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 4298 4299 /* set AMic1 as CrystalVoice input */ 4300 tmp = FLOAT_ONE; 4301 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4302 4303 /* set WUH source */ 4304 tmp = FLOAT_TWO; 4305 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 4306 } 4307 4308 /* 4309 * Initialization of flags in chip 4310 */ 4311 static void ca0132_init_flags(struct hda_codec *codec) 4312 { 4313 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 4314 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0); 4315 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0); 4316 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0); 4317 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 4318 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1); 4319 } 4320 4321 /* 4322 * Initialization of parameters in chip 4323 */ 4324 static void ca0132_init_params(struct hda_codec *codec) 4325 { 4326 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6); 4327 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6); 4328 } 4329 4330 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k) 4331 { 4332 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k); 4333 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k); 4334 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k); 4335 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k); 4336 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k); 4337 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k); 4338 4339 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4340 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4341 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 4342 } 4343 4344 static bool ca0132_download_dsp_images(struct hda_codec *codec) 4345 { 4346 bool dsp_loaded = false; 4347 const struct dsp_image_seg *dsp_os_image; 4348 const struct firmware *fw_entry; 4349 4350 if (request_firmware(&fw_entry, EFX_FILE, codec->bus->card->dev) != 0) 4351 return false; 4352 4353 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data); 4354 dspload_image(codec, dsp_os_image, 0, 0, true, 0); 4355 dsp_loaded = dspload_wait_loaded(codec); 4356 4357 release_firmware(fw_entry); 4358 4359 4360 return dsp_loaded; 4361 } 4362 4363 static void ca0132_download_dsp(struct hda_codec *codec) 4364 { 4365 struct ca0132_spec *spec = codec->spec; 4366 4367 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP 4368 return; /* NOP */ 4369 #endif 4370 spec->dsp_state = DSP_DOWNLOAD_INIT; 4371 4372 if (spec->dsp_state == DSP_DOWNLOAD_INIT) { 4373 chipio_enable_clocks(codec); 4374 spec->dsp_state = DSP_DOWNLOADING; 4375 if (!ca0132_download_dsp_images(codec)) 4376 spec->dsp_state = DSP_DOWNLOAD_FAILED; 4377 else 4378 spec->dsp_state = DSP_DOWNLOADED; 4379 } 4380 4381 if (spec->dsp_state == DSP_DOWNLOADED) 4382 ca0132_set_dsp_msr(codec, true); 4383 } 4384 4385 static void ca0132_process_dsp_response(struct hda_codec *codec) 4386 { 4387 struct ca0132_spec *spec = codec->spec; 4388 4389 snd_printdd(KERN_INFO "ca0132_process_dsp_response\n"); 4390 if (spec->wait_scp) { 4391 if (dspio_get_response_data(codec) >= 0) 4392 spec->wait_scp = 0; 4393 } 4394 4395 dspio_clear_response_queue(codec); 4396 } 4397 4398 static void ca0132_unsol_event(struct hda_codec *codec, unsigned int res) 4399 { 4400 snd_printdd(KERN_INFO "ca0132_unsol_event: 0x%x\n", res); 4401 4402 4403 if (((res >> AC_UNSOL_RES_TAG_SHIFT) & 0x3f) == UNSOL_TAG_DSP) { 4404 ca0132_process_dsp_response(codec); 4405 } else { 4406 res = snd_hda_jack_get_action(codec, 4407 (res >> AC_UNSOL_RES_TAG_SHIFT) & 0x3f); 4408 4409 snd_printdd(KERN_INFO "snd_hda_jack_get_action: 0x%x\n", res); 4410 4411 switch (res) { 4412 case UNSOL_TAG_HP: 4413 ca0132_select_out(codec); 4414 snd_hda_jack_report_sync(codec); 4415 break; 4416 case UNSOL_TAG_AMIC1: 4417 ca0132_select_mic(codec); 4418 snd_hda_jack_report_sync(codec); 4419 break; 4420 default: 4421 break; 4422 } 4423 } 4424 } 4425 4426 /* 4427 * Verbs tables. 4428 */ 4429 4430 /* Sends before DSP download. */ 4431 static struct hda_verb ca0132_base_init_verbs[] = { 4432 /*enable ct extension*/ 4433 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1}, 4434 /*enable DSP node unsol, needed for DSP download*/ 4435 {0x16, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_DSP}, 4436 {} 4437 }; 4438 4439 /* Send at exit. */ 4440 static struct hda_verb ca0132_base_exit_verbs[] = { 4441 /*set afg to D3*/ 4442 {0x01, AC_VERB_SET_POWER_STATE, 0x03}, 4443 /*disable ct extension*/ 4444 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0}, 4445 {} 4446 }; 4447 4448 /* Other verbs tables. Sends after DSP download. */ 4449 static struct hda_verb ca0132_init_verbs0[] = { 4450 /* chip init verbs */ 4451 {0x15, 0x70D, 0xF0}, 4452 {0x15, 0x70E, 0xFE}, 4453 {0x15, 0x707, 0x75}, 4454 {0x15, 0x707, 0xD3}, 4455 {0x15, 0x707, 0x09}, 4456 {0x15, 0x707, 0x53}, 4457 {0x15, 0x707, 0xD4}, 4458 {0x15, 0x707, 0xEF}, 4459 {0x15, 0x707, 0x75}, 4460 {0x15, 0x707, 0xD3}, 4461 {0x15, 0x707, 0x09}, 4462 {0x15, 0x707, 0x02}, 4463 {0x15, 0x707, 0x37}, 4464 {0x15, 0x707, 0x78}, 4465 {0x15, 0x53C, 0xCE}, 4466 {0x15, 0x575, 0xC9}, 4467 {0x15, 0x53D, 0xCE}, 4468 {0x15, 0x5B7, 0xC9}, 4469 {0x15, 0x70D, 0xE8}, 4470 {0x15, 0x70E, 0xFE}, 4471 {0x15, 0x707, 0x02}, 4472 {0x15, 0x707, 0x68}, 4473 {0x15, 0x707, 0x62}, 4474 {0x15, 0x53A, 0xCE}, 4475 {0x15, 0x546, 0xC9}, 4476 {0x15, 0x53B, 0xCE}, 4477 {0x15, 0x5E8, 0xC9}, 4478 {0x15, 0x717, 0x0D}, 4479 {0x15, 0x718, 0x20}, 4480 {} 4481 }; 4482 4483 static struct hda_verb ca0132_init_verbs1[] = { 4484 {0x10, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_HP}, 4485 {0x12, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_AMIC1}, 4486 /* config EAPD */ 4487 {0x0b, 0x78D, 0x00}, 4488 /*{0x0b, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/ 4489 /*{0x10, 0x78D, 0x02},*/ 4490 /*{0x10, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/ 4491 {} 4492 }; 4493 4494 static void ca0132_init_chip(struct hda_codec *codec) 4495 { 4496 struct ca0132_spec *spec = codec->spec; 4497 int num_fx; 4498 int i; 4499 unsigned int on; 4500 4501 mutex_init(&spec->chipio_mutex); 4502 4503 spec->cur_out_type = SPEAKER_OUT; 4504 spec->cur_mic_type = DIGITAL_MIC; 4505 spec->cur_mic_boost = 0; 4506 4507 for (i = 0; i < VNODES_COUNT; i++) { 4508 spec->vnode_lvol[i] = 0x5a; 4509 spec->vnode_rvol[i] = 0x5a; 4510 spec->vnode_lswitch[i] = 0; 4511 spec->vnode_rswitch[i] = 0; 4512 } 4513 4514 /* 4515 * Default states for effects are in ca0132_effects[]. 4516 */ 4517 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 4518 for (i = 0; i < num_fx; i++) { 4519 on = (unsigned int)ca0132_effects[i].reqs[0]; 4520 spec->effects_switch[i] = on ? 1 : 0; 4521 } 4522 4523 spec->voicefx_val = 0; 4524 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1; 4525 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0; 4526 4527 #ifdef ENABLE_TUNING_CONTROLS 4528 ca0132_init_tuning_defaults(codec); 4529 #endif 4530 } 4531 4532 static void ca0132_exit_chip(struct hda_codec *codec) 4533 { 4534 /* put any chip cleanup stuffs here. */ 4535 4536 if (dspload_is_loaded(codec)) 4537 dsp_reset(codec); 4538 } 4539 4540 static int ca0132_init(struct hda_codec *codec) 4541 { 4542 struct ca0132_spec *spec = codec->spec; 4543 struct auto_pin_cfg *cfg = &spec->autocfg; 4544 int i; 4545 4546 spec->dsp_state = DSP_DOWNLOAD_INIT; 4547 spec->curr_chip_addx = INVALID_CHIP_ADDRESS; 4548 4549 snd_hda_power_up(codec); 4550 4551 ca0132_init_params(codec); 4552 ca0132_init_flags(codec); 4553 snd_hda_sequence_write(codec, spec->base_init_verbs); 4554 ca0132_download_dsp(codec); 4555 ca0132_refresh_widget_caps(codec); 4556 ca0132_setup_defaults(codec); 4557 ca0132_init_analog_mic2(codec); 4558 ca0132_init_dmic(codec); 4559 4560 for (i = 0; i < spec->num_outputs; i++) 4561 init_output(codec, spec->out_pins[i], spec->dacs[0]); 4562 4563 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 4564 4565 for (i = 0; i < spec->num_inputs; i++) 4566 init_input(codec, spec->input_pins[i], spec->adcs[i]); 4567 4568 init_input(codec, cfg->dig_in_pin, spec->dig_in); 4569 4570 for (i = 0; i < spec->num_init_verbs; i++) 4571 snd_hda_sequence_write(codec, spec->init_verbs[i]); 4572 4573 ca0132_init_unsol(codec); 4574 4575 ca0132_select_out(codec); 4576 ca0132_select_mic(codec); 4577 4578 snd_hda_jack_report_sync(codec); 4579 4580 snd_hda_power_down(codec); 4581 4582 return 0; 4583 } 4584 4585 static void ca0132_free(struct hda_codec *codec) 4586 { 4587 struct ca0132_spec *spec = codec->spec; 4588 4589 snd_hda_power_up(codec); 4590 snd_hda_sequence_write(codec, spec->base_exit_verbs); 4591 ca0132_exit_chip(codec); 4592 snd_hda_power_down(codec); 4593 kfree(codec->spec); 4594 } 4595 4596 static struct hda_codec_ops ca0132_patch_ops = { 4597 .build_controls = ca0132_build_controls, 4598 .build_pcms = ca0132_build_pcms, 4599 .init = ca0132_init, 4600 .free = ca0132_free, 4601 .unsol_event = ca0132_unsol_event, 4602 }; 4603 4604 static void ca0132_config(struct hda_codec *codec) 4605 { 4606 struct ca0132_spec *spec = codec->spec; 4607 struct auto_pin_cfg *cfg = &spec->autocfg; 4608 4609 spec->dacs[0] = 0x2; 4610 spec->dacs[1] = 0x3; 4611 spec->dacs[2] = 0x4; 4612 4613 spec->multiout.dac_nids = spec->dacs; 4614 spec->multiout.num_dacs = 3; 4615 spec->multiout.max_channels = 2; 4616 4617 spec->num_outputs = 2; 4618 spec->out_pins[0] = 0x0b; /* speaker out */ 4619 spec->out_pins[1] = 0x10; /* headphone out */ 4620 spec->shared_out_nid = 0x2; 4621 4622 spec->num_inputs = 3; 4623 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 4624 spec->adcs[1] = 0x8; /* analog mic2 */ 4625 spec->adcs[2] = 0xa; /* what u hear */ 4626 spec->shared_mic_nid = 0x7; 4627 4628 spec->input_pins[0] = 0x12; 4629 spec->input_pins[1] = 0x11; 4630 spec->input_pins[2] = 0x13; 4631 4632 /* SPDIF I/O */ 4633 spec->dig_out = 0x05; 4634 spec->multiout.dig_out_nid = spec->dig_out; 4635 cfg->dig_out_pins[0] = 0x0c; 4636 cfg->dig_outs = 1; 4637 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF; 4638 spec->dig_in = 0x09; 4639 cfg->dig_in_pin = 0x0e; 4640 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF; 4641 } 4642 4643 static int patch_ca0132(struct hda_codec *codec) 4644 { 4645 struct ca0132_spec *spec; 4646 int err; 4647 4648 snd_printdd("patch_ca0132\n"); 4649 4650 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 4651 if (!spec) 4652 return -ENOMEM; 4653 codec->spec = spec; 4654 4655 spec->num_mixers = 1; 4656 spec->mixers[0] = ca0132_mixer; 4657 4658 spec->base_init_verbs = ca0132_base_init_verbs; 4659 spec->base_exit_verbs = ca0132_base_exit_verbs; 4660 spec->init_verbs[0] = ca0132_init_verbs0; 4661 spec->init_verbs[1] = ca0132_init_verbs1; 4662 spec->num_init_verbs = 2; 4663 4664 ca0132_init_chip(codec); 4665 4666 ca0132_config(codec); 4667 4668 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL); 4669 if (err < 0) 4670 return err; 4671 4672 codec->patch_ops = ca0132_patch_ops; 4673 4674 return 0; 4675 } 4676 4677 /* 4678 * patch entries 4679 */ 4680 static struct hda_codec_preset snd_hda_preset_ca0132[] = { 4681 { .id = 0x11020011, .name = "CA0132", .patch = patch_ca0132 }, 4682 {} /* terminator */ 4683 }; 4684 4685 MODULE_ALIAS("snd-hda-codec-id:11020011"); 4686 4687 MODULE_LICENSE("GPL"); 4688 MODULE_DESCRIPTION("Creative Sound Core3D codec"); 4689 4690 static struct hda_codec_preset_list ca0132_list = { 4691 .preset = snd_hda_preset_ca0132, 4692 .owner = THIS_MODULE, 4693 }; 4694 4695 static int __init patch_ca0132_init(void) 4696 { 4697 return snd_hda_add_codec_preset(&ca0132_list); 4698 } 4699 4700 static void __exit patch_ca0132_exit(void) 4701 { 4702 snd_hda_delete_codec_preset(&ca0132_list); 4703 } 4704 4705 module_init(patch_ca0132_init) 4706 module_exit(patch_ca0132_exit) 4707