1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * HD audio interface patch for Creative CA0132 chip 4 * 5 * Copyright (c) 2011, Creative Technology Ltd. 6 * 7 * Based on patch_ca0110.c 8 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de> 9 */ 10 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/slab.h> 14 #include <linux/mutex.h> 15 #include <linux/module.h> 16 #include <linux/firmware.h> 17 #include <linux/kernel.h> 18 #include <linux/types.h> 19 #include <linux/io.h> 20 #include <linux/pci.h> 21 #include <asm/io.h> 22 #include <sound/core.h> 23 #include <sound/hda_codec.h> 24 #include "hda_local.h" 25 #include "hda_auto_parser.h" 26 #include "hda_jack.h" 27 28 #include "ca0132_regs.h" 29 30 /* Enable this to see controls for tuning purpose. */ 31 /*#define ENABLE_TUNING_CONTROLS*/ 32 33 #ifdef ENABLE_TUNING_CONTROLS 34 #include <sound/tlv.h> 35 #endif 36 37 #define FLOAT_ZERO 0x00000000 38 #define FLOAT_ONE 0x3f800000 39 #define FLOAT_TWO 0x40000000 40 #define FLOAT_THREE 0x40400000 41 #define FLOAT_EIGHT 0x41000000 42 #define FLOAT_MINUS_5 0xc0a00000 43 44 #define UNSOL_TAG_DSP 0x16 45 46 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18) 47 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15) 48 49 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8 50 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32 51 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2 52 53 #define MASTERCONTROL 0x80 54 #define MASTERCONTROL_ALLOC_DMA_CHAN 10 55 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60 56 57 #define WIDGET_CHIP_CTRL 0x15 58 #define WIDGET_DSP_CTRL 0x16 59 60 #define MEM_CONNID_MICIN1 3 61 #define MEM_CONNID_MICIN2 5 62 #define MEM_CONNID_MICOUT1 12 63 #define MEM_CONNID_MICOUT2 14 64 #define MEM_CONNID_WUH 10 65 #define MEM_CONNID_DSP 16 66 #define MEM_CONNID_DMIC 100 67 68 #define SCP_SET 0 69 #define SCP_GET 1 70 71 #define EFX_FILE "ctefx.bin" 72 #define DESKTOP_EFX_FILE "ctefx-desktop.bin" 73 #define R3DI_EFX_FILE "ctefx-r3di.bin" 74 75 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 76 MODULE_FIRMWARE(EFX_FILE); 77 MODULE_FIRMWARE(DESKTOP_EFX_FILE); 78 MODULE_FIRMWARE(R3DI_EFX_FILE); 79 #endif 80 81 static const char *const dirstr[2] = { "Playback", "Capture" }; 82 83 #define NUM_OF_OUTPUTS 3 84 enum { 85 SPEAKER_OUT, 86 HEADPHONE_OUT, 87 SURROUND_OUT 88 }; 89 90 enum { 91 DIGITAL_MIC, 92 LINE_MIC_IN 93 }; 94 95 /* Strings for Input Source Enum Control */ 96 static const char *const in_src_str[3] = {"Rear Mic", "Line", "Front Mic" }; 97 #define IN_SRC_NUM_OF_INPUTS 3 98 enum { 99 REAR_MIC, 100 REAR_LINE_IN, 101 FRONT_MIC, 102 }; 103 104 enum { 105 #define VNODE_START_NID 0x80 106 VNID_SPK = VNODE_START_NID, /* Speaker vnid */ 107 VNID_MIC, 108 VNID_HP_SEL, 109 VNID_AMIC1_SEL, 110 VNID_HP_ASEL, 111 VNID_AMIC1_ASEL, 112 VNODE_END_NID, 113 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID) 114 115 #define EFFECT_START_NID 0x90 116 #define OUT_EFFECT_START_NID EFFECT_START_NID 117 SURROUND = OUT_EFFECT_START_NID, 118 CRYSTALIZER, 119 DIALOG_PLUS, 120 SMART_VOLUME, 121 X_BASS, 122 EQUALIZER, 123 OUT_EFFECT_END_NID, 124 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID) 125 126 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID 127 ECHO_CANCELLATION = IN_EFFECT_START_NID, 128 VOICE_FOCUS, 129 MIC_SVM, 130 NOISE_REDUCTION, 131 IN_EFFECT_END_NID, 132 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID) 133 134 VOICEFX = IN_EFFECT_END_NID, 135 PLAY_ENHANCEMENT, 136 CRYSTAL_VOICE, 137 EFFECT_END_NID, 138 OUTPUT_SOURCE_ENUM, 139 INPUT_SOURCE_ENUM, 140 XBASS_XOVER, 141 EQ_PRESET_ENUM, 142 SMART_VOLUME_ENUM, 143 MIC_BOOST_ENUM, 144 AE5_HEADPHONE_GAIN_ENUM, 145 AE5_SOUND_FILTER_ENUM, 146 ZXR_HEADPHONE_GAIN 147 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID) 148 }; 149 150 /* Effects values size*/ 151 #define EFFECT_VALS_MAX_COUNT 12 152 153 /* 154 * Default values for the effect slider controls, they are in order of their 155 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then 156 * X-bass. 157 */ 158 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50}; 159 /* Amount of effect level sliders for ca0132_alt controls. */ 160 #define EFFECT_LEVEL_SLIDERS 5 161 162 /* Latency introduced by DSP blocks in milliseconds. */ 163 #define DSP_CAPTURE_INIT_LATENCY 0 164 #define DSP_CRYSTAL_VOICE_LATENCY 124 165 #define DSP_PLAYBACK_INIT_LATENCY 13 166 #define DSP_PLAY_ENHANCEMENT_LATENCY 30 167 #define DSP_SPEAKER_OUT_LATENCY 7 168 169 struct ct_effect { 170 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 171 hda_nid_t nid; 172 int mid; /*effect module ID*/ 173 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/ 174 int direct; /* 0:output; 1:input*/ 175 int params; /* number of default non-on/off params */ 176 /*effect default values, 1st is on/off. */ 177 unsigned int def_vals[EFFECT_VALS_MAX_COUNT]; 178 }; 179 180 #define EFX_DIR_OUT 0 181 #define EFX_DIR_IN 1 182 183 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = { 184 { .name = "Surround", 185 .nid = SURROUND, 186 .mid = 0x96, 187 .reqs = {0, 1}, 188 .direct = EFX_DIR_OUT, 189 .params = 1, 190 .def_vals = {0x3F800000, 0x3F2B851F} 191 }, 192 { .name = "Crystalizer", 193 .nid = CRYSTALIZER, 194 .mid = 0x96, 195 .reqs = {7, 8}, 196 .direct = EFX_DIR_OUT, 197 .params = 1, 198 .def_vals = {0x3F800000, 0x3F266666} 199 }, 200 { .name = "Dialog Plus", 201 .nid = DIALOG_PLUS, 202 .mid = 0x96, 203 .reqs = {2, 3}, 204 .direct = EFX_DIR_OUT, 205 .params = 1, 206 .def_vals = {0x00000000, 0x3F000000} 207 }, 208 { .name = "Smart Volume", 209 .nid = SMART_VOLUME, 210 .mid = 0x96, 211 .reqs = {4, 5, 6}, 212 .direct = EFX_DIR_OUT, 213 .params = 2, 214 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000} 215 }, 216 { .name = "X-Bass", 217 .nid = X_BASS, 218 .mid = 0x96, 219 .reqs = {24, 23, 25}, 220 .direct = EFX_DIR_OUT, 221 .params = 2, 222 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000} 223 }, 224 { .name = "Equalizer", 225 .nid = EQUALIZER, 226 .mid = 0x96, 227 .reqs = {9, 10, 11, 12, 13, 14, 228 15, 16, 17, 18, 19, 20}, 229 .direct = EFX_DIR_OUT, 230 .params = 11, 231 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000, 232 0x00000000, 0x00000000, 0x00000000, 0x00000000, 233 0x00000000, 0x00000000, 0x00000000, 0x00000000} 234 }, 235 { .name = "Echo Cancellation", 236 .nid = ECHO_CANCELLATION, 237 .mid = 0x95, 238 .reqs = {0, 1, 2, 3}, 239 .direct = EFX_DIR_IN, 240 .params = 3, 241 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000} 242 }, 243 { .name = "Voice Focus", 244 .nid = VOICE_FOCUS, 245 .mid = 0x95, 246 .reqs = {6, 7, 8, 9}, 247 .direct = EFX_DIR_IN, 248 .params = 3, 249 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000} 250 }, 251 { .name = "Mic SVM", 252 .nid = MIC_SVM, 253 .mid = 0x95, 254 .reqs = {44, 45}, 255 .direct = EFX_DIR_IN, 256 .params = 1, 257 .def_vals = {0x00000000, 0x3F3D70A4} 258 }, 259 { .name = "Noise Reduction", 260 .nid = NOISE_REDUCTION, 261 .mid = 0x95, 262 .reqs = {4, 5}, 263 .direct = EFX_DIR_IN, 264 .params = 1, 265 .def_vals = {0x3F800000, 0x3F000000} 266 }, 267 { .name = "VoiceFX", 268 .nid = VOICEFX, 269 .mid = 0x95, 270 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}, 271 .direct = EFX_DIR_IN, 272 .params = 8, 273 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000, 274 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000, 275 0x00000000} 276 } 277 }; 278 279 /* Tuning controls */ 280 #ifdef ENABLE_TUNING_CONTROLS 281 282 enum { 283 #define TUNING_CTL_START_NID 0xC0 284 WEDGE_ANGLE = TUNING_CTL_START_NID, 285 SVM_LEVEL, 286 EQUALIZER_BAND_0, 287 EQUALIZER_BAND_1, 288 EQUALIZER_BAND_2, 289 EQUALIZER_BAND_3, 290 EQUALIZER_BAND_4, 291 EQUALIZER_BAND_5, 292 EQUALIZER_BAND_6, 293 EQUALIZER_BAND_7, 294 EQUALIZER_BAND_8, 295 EQUALIZER_BAND_9, 296 TUNING_CTL_END_NID 297 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID) 298 }; 299 300 struct ct_tuning_ctl { 301 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 302 hda_nid_t parent_nid; 303 hda_nid_t nid; 304 int mid; /*effect module ID*/ 305 int req; /*effect module request*/ 306 int direct; /* 0:output; 1:input*/ 307 unsigned int def_val;/*effect default values*/ 308 }; 309 310 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = { 311 { .name = "Wedge Angle", 312 .parent_nid = VOICE_FOCUS, 313 .nid = WEDGE_ANGLE, 314 .mid = 0x95, 315 .req = 8, 316 .direct = EFX_DIR_IN, 317 .def_val = 0x41F00000 318 }, 319 { .name = "SVM Level", 320 .parent_nid = MIC_SVM, 321 .nid = SVM_LEVEL, 322 .mid = 0x95, 323 .req = 45, 324 .direct = EFX_DIR_IN, 325 .def_val = 0x3F3D70A4 326 }, 327 { .name = "EQ Band0", 328 .parent_nid = EQUALIZER, 329 .nid = EQUALIZER_BAND_0, 330 .mid = 0x96, 331 .req = 11, 332 .direct = EFX_DIR_OUT, 333 .def_val = 0x00000000 334 }, 335 { .name = "EQ Band1", 336 .parent_nid = EQUALIZER, 337 .nid = EQUALIZER_BAND_1, 338 .mid = 0x96, 339 .req = 12, 340 .direct = EFX_DIR_OUT, 341 .def_val = 0x00000000 342 }, 343 { .name = "EQ Band2", 344 .parent_nid = EQUALIZER, 345 .nid = EQUALIZER_BAND_2, 346 .mid = 0x96, 347 .req = 13, 348 .direct = EFX_DIR_OUT, 349 .def_val = 0x00000000 350 }, 351 { .name = "EQ Band3", 352 .parent_nid = EQUALIZER, 353 .nid = EQUALIZER_BAND_3, 354 .mid = 0x96, 355 .req = 14, 356 .direct = EFX_DIR_OUT, 357 .def_val = 0x00000000 358 }, 359 { .name = "EQ Band4", 360 .parent_nid = EQUALIZER, 361 .nid = EQUALIZER_BAND_4, 362 .mid = 0x96, 363 .req = 15, 364 .direct = EFX_DIR_OUT, 365 .def_val = 0x00000000 366 }, 367 { .name = "EQ Band5", 368 .parent_nid = EQUALIZER, 369 .nid = EQUALIZER_BAND_5, 370 .mid = 0x96, 371 .req = 16, 372 .direct = EFX_DIR_OUT, 373 .def_val = 0x00000000 374 }, 375 { .name = "EQ Band6", 376 .parent_nid = EQUALIZER, 377 .nid = EQUALIZER_BAND_6, 378 .mid = 0x96, 379 .req = 17, 380 .direct = EFX_DIR_OUT, 381 .def_val = 0x00000000 382 }, 383 { .name = "EQ Band7", 384 .parent_nid = EQUALIZER, 385 .nid = EQUALIZER_BAND_7, 386 .mid = 0x96, 387 .req = 18, 388 .direct = EFX_DIR_OUT, 389 .def_val = 0x00000000 390 }, 391 { .name = "EQ Band8", 392 .parent_nid = EQUALIZER, 393 .nid = EQUALIZER_BAND_8, 394 .mid = 0x96, 395 .req = 19, 396 .direct = EFX_DIR_OUT, 397 .def_val = 0x00000000 398 }, 399 { .name = "EQ Band9", 400 .parent_nid = EQUALIZER, 401 .nid = EQUALIZER_BAND_9, 402 .mid = 0x96, 403 .req = 20, 404 .direct = EFX_DIR_OUT, 405 .def_val = 0x00000000 406 } 407 }; 408 #endif 409 410 /* Voice FX Presets */ 411 #define VOICEFX_MAX_PARAM_COUNT 9 412 413 struct ct_voicefx { 414 char *name; 415 hda_nid_t nid; 416 int mid; 417 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/ 418 }; 419 420 struct ct_voicefx_preset { 421 char *name; /*preset name*/ 422 unsigned int vals[VOICEFX_MAX_PARAM_COUNT]; 423 }; 424 425 static const struct ct_voicefx ca0132_voicefx = { 426 .name = "VoiceFX Capture Switch", 427 .nid = VOICEFX, 428 .mid = 0x95, 429 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18} 430 }; 431 432 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = { 433 { .name = "Neutral", 434 .vals = { 0x00000000, 0x43C80000, 0x44AF0000, 435 0x44FA0000, 0x3F800000, 0x3F800000, 436 0x3F800000, 0x00000000, 0x00000000 } 437 }, 438 { .name = "Female2Male", 439 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 440 0x44FA0000, 0x3F19999A, 0x3F866666, 441 0x3F800000, 0x00000000, 0x00000000 } 442 }, 443 { .name = "Male2Female", 444 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 445 0x450AC000, 0x4017AE14, 0x3F6B851F, 446 0x3F800000, 0x00000000, 0x00000000 } 447 }, 448 { .name = "ScrappyKid", 449 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 450 0x44FA0000, 0x40400000, 0x3F28F5C3, 451 0x3F800000, 0x00000000, 0x00000000 } 452 }, 453 { .name = "Elderly", 454 .vals = { 0x3F800000, 0x44324000, 0x44BB8000, 455 0x44E10000, 0x3FB33333, 0x3FB9999A, 456 0x3F800000, 0x3E3A2E43, 0x00000000 } 457 }, 458 { .name = "Orc", 459 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000, 460 0x45098000, 0x3F266666, 0x3FC00000, 461 0x3F800000, 0x00000000, 0x00000000 } 462 }, 463 { .name = "Elf", 464 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000, 465 0x45193000, 0x3F8E147B, 0x3F75C28F, 466 0x3F800000, 0x00000000, 0x00000000 } 467 }, 468 { .name = "Dwarf", 469 .vals = { 0x3F800000, 0x43930000, 0x44BEE000, 470 0x45007000, 0x3F451EB8, 0x3F7851EC, 471 0x3F800000, 0x00000000, 0x00000000 } 472 }, 473 { .name = "AlienBrute", 474 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF, 475 0x451F6000, 0x3F266666, 0x3FA7D945, 476 0x3F800000, 0x3CF5C28F, 0x00000000 } 477 }, 478 { .name = "Robot", 479 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 480 0x44FA0000, 0x3FB2718B, 0x3F800000, 481 0xBC07010E, 0x00000000, 0x00000000 } 482 }, 483 { .name = "Marine", 484 .vals = { 0x3F800000, 0x43C20000, 0x44906000, 485 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71, 486 0x3F0A3D71, 0x00000000, 0x00000000 } 487 }, 488 { .name = "Emo", 489 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 490 0x44FA0000, 0x3F800000, 0x3F800000, 491 0x3E4CCCCD, 0x00000000, 0x00000000 } 492 }, 493 { .name = "DeepVoice", 494 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF, 495 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA, 496 0x3F800000, 0x00000000, 0x00000000 } 497 }, 498 { .name = "Munchkin", 499 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 500 0x44FA0000, 0x3F800000, 0x3F1A043C, 501 0x3F800000, 0x00000000, 0x00000000 } 502 } 503 }; 504 505 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */ 506 507 #define EQ_PRESET_MAX_PARAM_COUNT 11 508 509 struct ct_eq { 510 char *name; 511 hda_nid_t nid; 512 int mid; 513 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/ 514 }; 515 516 struct ct_eq_preset { 517 char *name; /*preset name*/ 518 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT]; 519 }; 520 521 static const struct ct_eq ca0132_alt_eq_enum = { 522 .name = "FX: Equalizer Preset Switch", 523 .nid = EQ_PRESET_ENUM, 524 .mid = 0x96, 525 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20} 526 }; 527 528 529 static const struct ct_eq_preset ca0132_alt_eq_presets[] = { 530 { .name = "Flat", 531 .vals = { 0x00000000, 0x00000000, 0x00000000, 532 0x00000000, 0x00000000, 0x00000000, 533 0x00000000, 0x00000000, 0x00000000, 534 0x00000000, 0x00000000 } 535 }, 536 { .name = "Acoustic", 537 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD, 538 0x40000000, 0x00000000, 0x00000000, 539 0x00000000, 0x00000000, 0x40000000, 540 0x40000000, 0x40000000 } 541 }, 542 { .name = "Classical", 543 .vals = { 0x00000000, 0x00000000, 0x40C00000, 544 0x40C00000, 0x40466666, 0x00000000, 545 0x00000000, 0x00000000, 0x00000000, 546 0x40466666, 0x40466666 } 547 }, 548 { .name = "Country", 549 .vals = { 0x00000000, 0xBF99999A, 0x00000000, 550 0x3FA66666, 0x3FA66666, 0x3F8CCCCD, 551 0x00000000, 0x00000000, 0x40000000, 552 0x40466666, 0x40800000 } 553 }, 554 { .name = "Dance", 555 .vals = { 0x00000000, 0xBF99999A, 0x40000000, 556 0x40466666, 0x40866666, 0xBF99999A, 557 0xBF99999A, 0x00000000, 0x00000000, 558 0x40800000, 0x40800000 } 559 }, 560 { .name = "Jazz", 561 .vals = { 0x00000000, 0x00000000, 0x00000000, 562 0x3F8CCCCD, 0x40800000, 0x40800000, 563 0x40800000, 0x00000000, 0x3F8CCCCD, 564 0x40466666, 0x40466666 } 565 }, 566 { .name = "New Age", 567 .vals = { 0x00000000, 0x00000000, 0x40000000, 568 0x40000000, 0x00000000, 0x00000000, 569 0x00000000, 0x3F8CCCCD, 0x40000000, 570 0x40000000, 0x40000000 } 571 }, 572 { .name = "Pop", 573 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000, 574 0x40000000, 0x40000000, 0x00000000, 575 0xBF99999A, 0xBF99999A, 0x00000000, 576 0x40466666, 0x40C00000 } 577 }, 578 { .name = "Rock", 579 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A, 580 0x3F8CCCCD, 0x40000000, 0xBF99999A, 581 0xBF99999A, 0x00000000, 0x00000000, 582 0x40800000, 0x40800000 } 583 }, 584 { .name = "Vocal", 585 .vals = { 0x00000000, 0xC0000000, 0xBF99999A, 586 0xBF99999A, 0x00000000, 0x40466666, 587 0x40800000, 0x40466666, 0x00000000, 588 0x00000000, 0x3F8CCCCD } 589 } 590 }; 591 592 /* DSP command sequences for ca0132_alt_select_out */ 593 #define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */ 594 struct ca0132_alt_out_set { 595 char *name; /*preset name*/ 596 unsigned char commands; 597 unsigned int mids[ALT_OUT_SET_MAX_COMMANDS]; 598 unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS]; 599 unsigned int vals[ALT_OUT_SET_MAX_COMMANDS]; 600 }; 601 602 static const struct ca0132_alt_out_set alt_out_presets[] = { 603 { .name = "Line Out", 604 .commands = 7, 605 .mids = { 0x96, 0x96, 0x96, 0x8F, 606 0x96, 0x96, 0x96 }, 607 .reqs = { 0x19, 0x17, 0x18, 0x01, 608 0x1F, 0x15, 0x3A }, 609 .vals = { 0x3F000000, 0x42A00000, 0x00000000, 610 0x00000000, 0x00000000, 0x00000000, 611 0x00000000 } 612 }, 613 { .name = "Headphone", 614 .commands = 7, 615 .mids = { 0x96, 0x96, 0x96, 0x8F, 616 0x96, 0x96, 0x96 }, 617 .reqs = { 0x19, 0x17, 0x18, 0x01, 618 0x1F, 0x15, 0x3A }, 619 .vals = { 0x3F000000, 0x42A00000, 0x00000000, 620 0x00000000, 0x00000000, 0x00000000, 621 0x00000000 } 622 }, 623 { .name = "Surround", 624 .commands = 8, 625 .mids = { 0x96, 0x8F, 0x96, 0x96, 626 0x96, 0x96, 0x96, 0x96 }, 627 .reqs = { 0x18, 0x01, 0x1F, 0x15, 628 0x3A, 0x1A, 0x1B, 0x1C }, 629 .vals = { 0x00000000, 0x00000000, 0x00000000, 630 0x00000000, 0x00000000, 0x00000000, 631 0x00000000, 0x00000000 } 632 } 633 }; 634 635 /* 636 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume, 637 * and I don't know what the third req is, but it's always zero. I assume it's 638 * some sort of update or set command to tell the DSP there's new volume info. 639 */ 640 #define DSP_VOL_OUT 0 641 #define DSP_VOL_IN 1 642 643 struct ct_dsp_volume_ctl { 644 hda_nid_t vnid; 645 int mid; /* module ID*/ 646 unsigned int reqs[3]; /* scp req ID */ 647 }; 648 649 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = { 650 { .vnid = VNID_SPK, 651 .mid = 0x32, 652 .reqs = {3, 4, 2} 653 }, 654 { .vnid = VNID_MIC, 655 .mid = 0x37, 656 .reqs = {2, 3, 1} 657 } 658 }; 659 660 /* Values for ca0113_mmio_command_set for selecting output. */ 661 #define AE5_CA0113_OUT_SET_COMMANDS 6 662 struct ae5_ca0113_output_set { 663 unsigned int group[AE5_CA0113_OUT_SET_COMMANDS]; 664 unsigned int target[AE5_CA0113_OUT_SET_COMMANDS]; 665 unsigned int vals[AE5_CA0113_OUT_SET_COMMANDS]; 666 }; 667 668 static const struct ae5_ca0113_output_set ae5_ca0113_output_presets[] = { 669 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 670 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 671 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f } 672 }, 673 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 674 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 675 .vals = { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } 676 }, 677 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 678 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 679 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f } 680 } 681 }; 682 683 /* ae5 ca0113 command sequences to set headphone gain levels. */ 684 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4 685 struct ae5_headphone_gain_set { 686 char *name; 687 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS]; 688 }; 689 690 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = { 691 { .name = "Low (16-31", 692 .vals = { 0xff, 0x2c, 0xf5, 0x32 } 693 }, 694 { .name = "Medium (32-149", 695 .vals = { 0x38, 0xa8, 0x3e, 0x4c } 696 }, 697 { .name = "High (150-600", 698 .vals = { 0xff, 0xff, 0xff, 0x7f } 699 } 700 }; 701 702 struct ae5_filter_set { 703 char *name; 704 unsigned int val; 705 }; 706 707 static const struct ae5_filter_set ae5_filter_presets[] = { 708 { .name = "Slow Roll Off", 709 .val = 0xa0 710 }, 711 { .name = "Minimum Phase", 712 .val = 0xc0 713 }, 714 { .name = "Fast Roll Off", 715 .val = 0x80 716 } 717 }; 718 719 enum hda_cmd_vendor_io { 720 /* for DspIO node */ 721 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000, 722 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100, 723 724 VENDOR_DSPIO_STATUS = 0xF01, 725 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702, 726 VENDOR_DSPIO_SCP_READ_DATA = 0xF02, 727 VENDOR_DSPIO_DSP_INIT = 0x703, 728 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704, 729 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04, 730 731 /* for ChipIO node */ 732 VENDOR_CHIPIO_ADDRESS_LOW = 0x000, 733 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100, 734 VENDOR_CHIPIO_STREAM_FORMAT = 0x200, 735 VENDOR_CHIPIO_DATA_LOW = 0x300, 736 VENDOR_CHIPIO_DATA_HIGH = 0x400, 737 738 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500, 739 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00, 740 741 VENDOR_CHIPIO_GET_PARAMETER = 0xF00, 742 VENDOR_CHIPIO_STATUS = 0xF01, 743 VENDOR_CHIPIO_HIC_POST_READ = 0x702, 744 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03, 745 746 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707, 747 VENDOR_CHIPIO_8051_DATA_READ = 0xF07, 748 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08, 749 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709, 750 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09, 751 752 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A, 753 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A, 754 755 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C, 756 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C, 757 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D, 758 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E, 759 VENDOR_CHIPIO_FLAG_SET = 0x70F, 760 VENDOR_CHIPIO_FLAGS_GET = 0xF0F, 761 VENDOR_CHIPIO_PARAM_SET = 0x710, 762 VENDOR_CHIPIO_PARAM_GET = 0xF10, 763 764 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711, 765 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712, 766 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12, 767 VENDOR_CHIPIO_PORT_FREE_SET = 0x713, 768 769 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17, 770 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717, 771 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18, 772 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718, 773 774 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788, 775 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88, 776 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789, 777 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89, 778 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A, 779 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A, 780 781 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D 782 }; 783 784 /* 785 * Control flag IDs 786 */ 787 enum control_flag_id { 788 /* Connection manager stream setup is bypassed/enabled */ 789 CONTROL_FLAG_C_MGR = 0, 790 /* DSP DMA is bypassed/enabled */ 791 CONTROL_FLAG_DMA = 1, 792 /* 8051 'idle' mode is disabled/enabled */ 793 CONTROL_FLAG_IDLE_ENABLE = 2, 794 /* Tracker for the SPDIF-in path is bypassed/enabled */ 795 CONTROL_FLAG_TRACKER = 3, 796 /* DigitalOut to Spdif2Out connection is disabled/enabled */ 797 CONTROL_FLAG_SPDIF2OUT = 4, 798 /* Digital Microphone is disabled/enabled */ 799 CONTROL_FLAG_DMIC = 5, 800 /* ADC_B rate is 48 kHz/96 kHz */ 801 CONTROL_FLAG_ADC_B_96KHZ = 6, 802 /* ADC_C rate is 48 kHz/96 kHz */ 803 CONTROL_FLAG_ADC_C_96KHZ = 7, 804 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */ 805 CONTROL_FLAG_DAC_96KHZ = 8, 806 /* DSP rate is 48 kHz/96 kHz */ 807 CONTROL_FLAG_DSP_96KHZ = 9, 808 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */ 809 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10, 810 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */ 811 CONTROL_FLAG_SRC_RATE_96KHZ = 11, 812 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */ 813 CONTROL_FLAG_DECODE_LOOP = 12, 814 /* De-emphasis filter on DAC-1 disabled/enabled */ 815 CONTROL_FLAG_DAC1_DEEMPHASIS = 13, 816 /* De-emphasis filter on DAC-2 disabled/enabled */ 817 CONTROL_FLAG_DAC2_DEEMPHASIS = 14, 818 /* De-emphasis filter on DAC-3 disabled/enabled */ 819 CONTROL_FLAG_DAC3_DEEMPHASIS = 15, 820 /* High-pass filter on ADC_B disabled/enabled */ 821 CONTROL_FLAG_ADC_B_HIGH_PASS = 16, 822 /* High-pass filter on ADC_C disabled/enabled */ 823 CONTROL_FLAG_ADC_C_HIGH_PASS = 17, 824 /* Common mode on Port_A disabled/enabled */ 825 CONTROL_FLAG_PORT_A_COMMON_MODE = 18, 826 /* Common mode on Port_D disabled/enabled */ 827 CONTROL_FLAG_PORT_D_COMMON_MODE = 19, 828 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */ 829 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20, 830 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */ 831 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21, 832 /* ASI rate is 48kHz/96kHz */ 833 CONTROL_FLAG_ASI_96KHZ = 22, 834 /* DAC power settings able to control attached ports no/yes */ 835 CONTROL_FLAG_DACS_CONTROL_PORTS = 23, 836 /* Clock Stop OK reporting is disabled/enabled */ 837 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24, 838 /* Number of control flags */ 839 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1) 840 }; 841 842 /* 843 * Control parameter IDs 844 */ 845 enum control_param_id { 846 /* 0: None, 1: Mic1In*/ 847 CONTROL_PARAM_VIP_SOURCE = 1, 848 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */ 849 CONTROL_PARAM_SPDIF1_SOURCE = 2, 850 /* Port A output stage gain setting to use when 16 Ohm output 851 * impedance is selected*/ 852 CONTROL_PARAM_PORTA_160OHM_GAIN = 8, 853 /* Port D output stage gain setting to use when 16 Ohm output 854 * impedance is selected*/ 855 CONTROL_PARAM_PORTD_160OHM_GAIN = 10, 856 857 /* 858 * This control param name was found in the 8051 memory, and makes 859 * sense given the fact the AE-5 uses it and has the ASI flag set. 860 */ 861 CONTROL_PARAM_ASI = 23, 862 863 /* Stream Control */ 864 865 /* Select stream with the given ID */ 866 CONTROL_PARAM_STREAM_ID = 24, 867 /* Source connection point for the selected stream */ 868 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25, 869 /* Destination connection point for the selected stream */ 870 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26, 871 /* Number of audio channels in the selected stream */ 872 CONTROL_PARAM_STREAMS_CHANNELS = 27, 873 /*Enable control for the selected stream */ 874 CONTROL_PARAM_STREAM_CONTROL = 28, 875 876 /* Connection Point Control */ 877 878 /* Select connection point with the given ID */ 879 CONTROL_PARAM_CONN_POINT_ID = 29, 880 /* Connection point sample rate */ 881 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30, 882 883 /* Node Control */ 884 885 /* Select HDA node with the given ID */ 886 CONTROL_PARAM_NODE_ID = 31 887 }; 888 889 /* 890 * Dsp Io Status codes 891 */ 892 enum hda_vendor_status_dspio { 893 /* Success */ 894 VENDOR_STATUS_DSPIO_OK = 0x00, 895 /* Busy, unable to accept new command, the host must retry */ 896 VENDOR_STATUS_DSPIO_BUSY = 0x01, 897 /* SCP command queue is full */ 898 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02, 899 /* SCP response queue is empty */ 900 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03 901 }; 902 903 /* 904 * Chip Io Status codes 905 */ 906 enum hda_vendor_status_chipio { 907 /* Success */ 908 VENDOR_STATUS_CHIPIO_OK = 0x00, 909 /* Busy, unable to accept new command, the host must retry */ 910 VENDOR_STATUS_CHIPIO_BUSY = 0x01 911 }; 912 913 /* 914 * CA0132 sample rate 915 */ 916 enum ca0132_sample_rate { 917 SR_6_000 = 0x00, 918 SR_8_000 = 0x01, 919 SR_9_600 = 0x02, 920 SR_11_025 = 0x03, 921 SR_16_000 = 0x04, 922 SR_22_050 = 0x05, 923 SR_24_000 = 0x06, 924 SR_32_000 = 0x07, 925 SR_44_100 = 0x08, 926 SR_48_000 = 0x09, 927 SR_88_200 = 0x0A, 928 SR_96_000 = 0x0B, 929 SR_144_000 = 0x0C, 930 SR_176_400 = 0x0D, 931 SR_192_000 = 0x0E, 932 SR_384_000 = 0x0F, 933 934 SR_COUNT = 0x10, 935 936 SR_RATE_UNKNOWN = 0x1F 937 }; 938 939 enum dsp_download_state { 940 DSP_DOWNLOAD_FAILED = -1, 941 DSP_DOWNLOAD_INIT = 0, 942 DSP_DOWNLOADING = 1, 943 DSP_DOWNLOADED = 2 944 }; 945 946 /* retrieve parameters from hda format */ 947 #define get_hdafmt_chs(fmt) (fmt & 0xf) 948 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7) 949 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f) 950 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1) 951 952 /* 953 * CA0132 specific 954 */ 955 956 struct ca0132_spec { 957 const struct snd_kcontrol_new *mixers[5]; 958 unsigned int num_mixers; 959 const struct hda_verb *base_init_verbs; 960 const struct hda_verb *base_exit_verbs; 961 const struct hda_verb *chip_init_verbs; 962 const struct hda_verb *desktop_init_verbs; 963 struct hda_verb *spec_init_verbs; 964 struct auto_pin_cfg autocfg; 965 966 /* Nodes configurations */ 967 struct hda_multi_out multiout; 968 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS]; 969 hda_nid_t dacs[AUTO_CFG_MAX_OUTS]; 970 unsigned int num_outputs; 971 hda_nid_t input_pins[AUTO_PIN_LAST]; 972 hda_nid_t adcs[AUTO_PIN_LAST]; 973 hda_nid_t dig_out; 974 hda_nid_t dig_in; 975 unsigned int num_inputs; 976 hda_nid_t shared_mic_nid; 977 hda_nid_t shared_out_nid; 978 hda_nid_t unsol_tag_hp; 979 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */ 980 hda_nid_t unsol_tag_amic1; 981 982 /* chip access */ 983 struct mutex chipio_mutex; /* chip access mutex */ 984 u32 curr_chip_addx; 985 986 /* DSP download related */ 987 enum dsp_download_state dsp_state; 988 unsigned int dsp_stream_id; 989 unsigned int wait_scp; 990 unsigned int wait_scp_header; 991 unsigned int wait_num_data; 992 unsigned int scp_resp_header; 993 unsigned int scp_resp_data[4]; 994 unsigned int scp_resp_count; 995 bool startup_check_entered; 996 bool dsp_reload; 997 998 /* mixer and effects related */ 999 unsigned char dmic_ctl; 1000 int cur_out_type; 1001 int cur_mic_type; 1002 long vnode_lvol[VNODES_COUNT]; 1003 long vnode_rvol[VNODES_COUNT]; 1004 long vnode_lswitch[VNODES_COUNT]; 1005 long vnode_rswitch[VNODES_COUNT]; 1006 long effects_switch[EFFECTS_COUNT]; 1007 long voicefx_val; 1008 long cur_mic_boost; 1009 /* ca0132_alt control related values */ 1010 unsigned char in_enum_val; 1011 unsigned char out_enum_val; 1012 unsigned char mic_boost_enum_val; 1013 unsigned char smart_volume_setting; 1014 long fx_ctl_val[EFFECT_LEVEL_SLIDERS]; 1015 long xbass_xover_freq; 1016 long eq_preset_val; 1017 unsigned int tlv[4]; 1018 struct hda_vmaster_mute_hook vmaster_mute; 1019 /* AE-5 Control values */ 1020 unsigned char ae5_headphone_gain_val; 1021 unsigned char ae5_filter_val; 1022 /* ZxR Control Values */ 1023 unsigned char zxr_gain_set; 1024 1025 struct hda_codec *codec; 1026 struct delayed_work unsol_hp_work; 1027 int quirk; 1028 1029 #ifdef ENABLE_TUNING_CONTROLS 1030 long cur_ctl_vals[TUNING_CTLS_COUNT]; 1031 #endif 1032 /* 1033 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster 1034 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown 1035 * things. 1036 */ 1037 bool use_pci_mmio; 1038 void __iomem *mem_base; 1039 1040 /* 1041 * Whether or not to use the alt functions like alt_select_out, 1042 * alt_select_in, etc. Only used on desktop codecs for now, because of 1043 * surround sound support. 1044 */ 1045 bool use_alt_functions; 1046 1047 /* 1048 * Whether or not to use alt controls: volume effect sliders, EQ 1049 * presets, smart volume presets, and new control names with FX prefix. 1050 * Renames PlayEnhancement and CrystalVoice too. 1051 */ 1052 bool use_alt_controls; 1053 }; 1054 1055 /* 1056 * CA0132 quirks table 1057 */ 1058 enum { 1059 QUIRK_NONE, 1060 QUIRK_ALIENWARE, 1061 QUIRK_ALIENWARE_M17XR4, 1062 QUIRK_SBZ, 1063 QUIRK_ZXR, 1064 QUIRK_ZXR_DBPRO, 1065 QUIRK_R3DI, 1066 QUIRK_R3D, 1067 QUIRK_AE5, 1068 }; 1069 1070 #ifdef CONFIG_PCI 1071 #define ca0132_quirk(spec) ((spec)->quirk) 1072 #define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio) 1073 #define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions) 1074 #define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls) 1075 #else 1076 #define ca0132_quirk(spec) ({ (void)(spec); QUIRK_NONE; }) 1077 #define ca0132_use_alt_functions(spec) ({ (void)(spec); false; }) 1078 #define ca0132_use_pci_mmio(spec) ({ (void)(spec); false; }) 1079 #define ca0132_use_alt_controls(spec) ({ (void)(spec); false; }) 1080 #endif 1081 1082 static const struct hda_pintbl alienware_pincfgs[] = { 1083 { 0x0b, 0x90170110 }, /* Builtin Speaker */ 1084 { 0x0c, 0x411111f0 }, /* N/A */ 1085 { 0x0d, 0x411111f0 }, /* N/A */ 1086 { 0x0e, 0x411111f0 }, /* N/A */ 1087 { 0x0f, 0x0321101f }, /* HP */ 1088 { 0x10, 0x411111f0 }, /* Headset? disabled for now */ 1089 { 0x11, 0x03a11021 }, /* Mic */ 1090 { 0x12, 0xd5a30140 }, /* Builtin Mic */ 1091 { 0x13, 0x411111f0 }, /* N/A */ 1092 { 0x18, 0x411111f0 }, /* N/A */ 1093 {} 1094 }; 1095 1096 /* Sound Blaster Z pin configs taken from Windows Driver */ 1097 static const struct hda_pintbl sbz_pincfgs[] = { 1098 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1099 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1100 { 0x0d, 0x014510f0 }, /* Digital Out */ 1101 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1102 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */ 1103 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1104 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1105 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1106 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1107 { 0x18, 0x50d000f0 }, /* N/A */ 1108 {} 1109 }; 1110 1111 /* Sound Blaster ZxR pin configs taken from Windows Driver */ 1112 static const struct hda_pintbl zxr_pincfgs[] = { 1113 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */ 1114 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/ 1115 { 0x0d, 0x014510f0 }, /* Digital Out */ 1116 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/ 1117 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */ 1118 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */ 1119 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */ 1120 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */ 1121 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1122 { 0x18, 0x50d000f0 }, /* N/A */ 1123 {} 1124 }; 1125 1126 /* Recon3D pin configs taken from Windows Driver */ 1127 static const struct hda_pintbl r3d_pincfgs[] = { 1128 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1129 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1130 { 0x0d, 0x014510f0 }, /* Digital Out */ 1131 { 0x0e, 0x01c520f0 }, /* SPDIF In */ 1132 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1133 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1134 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1135 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1136 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1137 { 0x18, 0x50d000f0 }, /* N/A */ 1138 {} 1139 }; 1140 1141 /* Sound Blaster AE-5 pin configs taken from Windows Driver */ 1142 static const struct hda_pintbl ae5_pincfgs[] = { 1143 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1144 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1145 { 0x0d, 0x014510f0 }, /* Digital Out */ 1146 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1147 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */ 1148 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1149 { 0x11, 0x01a170ff }, /* Port B -- LineMicIn2 / Rear Headphone */ 1150 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1151 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1152 { 0x18, 0x50d000f0 }, /* N/A */ 1153 {} 1154 }; 1155 1156 /* Recon3D integrated pin configs taken from Windows Driver */ 1157 static const struct hda_pintbl r3di_pincfgs[] = { 1158 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1159 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1160 { 0x0d, 0x014510f0 }, /* Digital Out */ 1161 { 0x0e, 0x41c520f0 }, /* SPDIF In */ 1162 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1163 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1164 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1165 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1166 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1167 { 0x18, 0x500000f0 }, /* N/A */ 1168 {} 1169 }; 1170 1171 static const struct snd_pci_quirk ca0132_quirks[] = { 1172 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4), 1173 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE), 1174 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE), 1175 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE), 1176 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ), 1177 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ), 1178 SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ), 1179 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ), 1180 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI), 1181 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI), 1182 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI), 1183 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D), 1184 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5), 1185 {} 1186 }; 1187 1188 /* 1189 * CA0132 codec access 1190 */ 1191 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid, 1192 unsigned int verb, unsigned int parm, unsigned int *res) 1193 { 1194 unsigned int response; 1195 response = snd_hda_codec_read(codec, nid, 0, verb, parm); 1196 *res = response; 1197 1198 return ((response == -1) ? -1 : 0); 1199 } 1200 1201 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid, 1202 unsigned short converter_format, unsigned int *res) 1203 { 1204 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT, 1205 converter_format & 0xffff, res); 1206 } 1207 1208 static int codec_set_converter_stream_channel(struct hda_codec *codec, 1209 hda_nid_t nid, unsigned char stream, 1210 unsigned char channel, unsigned int *res) 1211 { 1212 unsigned char converter_stream_channel = 0; 1213 1214 converter_stream_channel = (stream << 4) | (channel & 0x0f); 1215 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID, 1216 converter_stream_channel, res); 1217 } 1218 1219 /* Chip access helper function */ 1220 static int chipio_send(struct hda_codec *codec, 1221 unsigned int reg, 1222 unsigned int data) 1223 { 1224 unsigned int res; 1225 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1226 1227 /* send bits of data specified by reg */ 1228 do { 1229 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1230 reg, data); 1231 if (res == VENDOR_STATUS_CHIPIO_OK) 1232 return 0; 1233 msleep(20); 1234 } while (time_before(jiffies, timeout)); 1235 1236 return -EIO; 1237 } 1238 1239 /* 1240 * Write chip address through the vendor widget -- NOT protected by the Mutex! 1241 */ 1242 static int chipio_write_address(struct hda_codec *codec, 1243 unsigned int chip_addx) 1244 { 1245 struct ca0132_spec *spec = codec->spec; 1246 int res; 1247 1248 if (spec->curr_chip_addx == chip_addx) 1249 return 0; 1250 1251 /* send low 16 bits of the address */ 1252 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW, 1253 chip_addx & 0xffff); 1254 1255 if (res != -EIO) { 1256 /* send high 16 bits of the address */ 1257 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH, 1258 chip_addx >> 16); 1259 } 1260 1261 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx; 1262 1263 return res; 1264 } 1265 1266 /* 1267 * Write data through the vendor widget -- NOT protected by the Mutex! 1268 */ 1269 static int chipio_write_data(struct hda_codec *codec, unsigned int data) 1270 { 1271 struct ca0132_spec *spec = codec->spec; 1272 int res; 1273 1274 /* send low 16 bits of the data */ 1275 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff); 1276 1277 if (res != -EIO) { 1278 /* send high 16 bits of the data */ 1279 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH, 1280 data >> 16); 1281 } 1282 1283 /*If no error encountered, automatically increment the address 1284 as per chip behaviour*/ 1285 spec->curr_chip_addx = (res != -EIO) ? 1286 (spec->curr_chip_addx + 4) : ~0U; 1287 return res; 1288 } 1289 1290 /* 1291 * Write multiple data through the vendor widget -- NOT protected by the Mutex! 1292 */ 1293 static int chipio_write_data_multiple(struct hda_codec *codec, 1294 const u32 *data, 1295 unsigned int count) 1296 { 1297 int status = 0; 1298 1299 if (data == NULL) { 1300 codec_dbg(codec, "chipio_write_data null ptr\n"); 1301 return -EINVAL; 1302 } 1303 1304 while ((count-- != 0) && (status == 0)) 1305 status = chipio_write_data(codec, *data++); 1306 1307 return status; 1308 } 1309 1310 1311 /* 1312 * Read data through the vendor widget -- NOT protected by the Mutex! 1313 */ 1314 static int chipio_read_data(struct hda_codec *codec, unsigned int *data) 1315 { 1316 struct ca0132_spec *spec = codec->spec; 1317 int res; 1318 1319 /* post read */ 1320 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0); 1321 1322 if (res != -EIO) { 1323 /* read status */ 1324 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 1325 } 1326 1327 if (res != -EIO) { 1328 /* read data */ 1329 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1330 VENDOR_CHIPIO_HIC_READ_DATA, 1331 0); 1332 } 1333 1334 /*If no error encountered, automatically increment the address 1335 as per chip behaviour*/ 1336 spec->curr_chip_addx = (res != -EIO) ? 1337 (spec->curr_chip_addx + 4) : ~0U; 1338 return res; 1339 } 1340 1341 /* 1342 * Write given value to the given address through the chip I/O widget. 1343 * protected by the Mutex 1344 */ 1345 static int chipio_write(struct hda_codec *codec, 1346 unsigned int chip_addx, const unsigned int data) 1347 { 1348 struct ca0132_spec *spec = codec->spec; 1349 int err; 1350 1351 mutex_lock(&spec->chipio_mutex); 1352 1353 /* write the address, and if successful proceed to write data */ 1354 err = chipio_write_address(codec, chip_addx); 1355 if (err < 0) 1356 goto exit; 1357 1358 err = chipio_write_data(codec, data); 1359 if (err < 0) 1360 goto exit; 1361 1362 exit: 1363 mutex_unlock(&spec->chipio_mutex); 1364 return err; 1365 } 1366 1367 /* 1368 * Write given value to the given address through the chip I/O widget. 1369 * not protected by the Mutex 1370 */ 1371 static int chipio_write_no_mutex(struct hda_codec *codec, 1372 unsigned int chip_addx, const unsigned int data) 1373 { 1374 int err; 1375 1376 1377 /* write the address, and if successful proceed to write data */ 1378 err = chipio_write_address(codec, chip_addx); 1379 if (err < 0) 1380 goto exit; 1381 1382 err = chipio_write_data(codec, data); 1383 if (err < 0) 1384 goto exit; 1385 1386 exit: 1387 return err; 1388 } 1389 1390 /* 1391 * Write multiple values to the given address through the chip I/O widget. 1392 * protected by the Mutex 1393 */ 1394 static int chipio_write_multiple(struct hda_codec *codec, 1395 u32 chip_addx, 1396 const u32 *data, 1397 unsigned int count) 1398 { 1399 struct ca0132_spec *spec = codec->spec; 1400 int status; 1401 1402 mutex_lock(&spec->chipio_mutex); 1403 status = chipio_write_address(codec, chip_addx); 1404 if (status < 0) 1405 goto error; 1406 1407 status = chipio_write_data_multiple(codec, data, count); 1408 error: 1409 mutex_unlock(&spec->chipio_mutex); 1410 1411 return status; 1412 } 1413 1414 /* 1415 * Read the given address through the chip I/O widget 1416 * protected by the Mutex 1417 */ 1418 static int chipio_read(struct hda_codec *codec, 1419 unsigned int chip_addx, unsigned int *data) 1420 { 1421 struct ca0132_spec *spec = codec->spec; 1422 int err; 1423 1424 mutex_lock(&spec->chipio_mutex); 1425 1426 /* write the address, and if successful proceed to write data */ 1427 err = chipio_write_address(codec, chip_addx); 1428 if (err < 0) 1429 goto exit; 1430 1431 err = chipio_read_data(codec, data); 1432 if (err < 0) 1433 goto exit; 1434 1435 exit: 1436 mutex_unlock(&spec->chipio_mutex); 1437 return err; 1438 } 1439 1440 /* 1441 * Set chip control flags through the chip I/O widget. 1442 */ 1443 static void chipio_set_control_flag(struct hda_codec *codec, 1444 enum control_flag_id flag_id, 1445 bool flag_state) 1446 { 1447 unsigned int val; 1448 unsigned int flag_bit; 1449 1450 flag_bit = (flag_state ? 1 : 0); 1451 val = (flag_bit << 7) | (flag_id); 1452 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1453 VENDOR_CHIPIO_FLAG_SET, val); 1454 } 1455 1456 /* 1457 * Set chip parameters through the chip I/O widget. 1458 */ 1459 static void chipio_set_control_param(struct hda_codec *codec, 1460 enum control_param_id param_id, int param_val) 1461 { 1462 struct ca0132_spec *spec = codec->spec; 1463 int val; 1464 1465 if ((param_id < 32) && (param_val < 8)) { 1466 val = (param_val << 5) | (param_id); 1467 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1468 VENDOR_CHIPIO_PARAM_SET, val); 1469 } else { 1470 mutex_lock(&spec->chipio_mutex); 1471 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1472 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1473 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1474 param_id); 1475 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1476 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1477 param_val); 1478 } 1479 mutex_unlock(&spec->chipio_mutex); 1480 } 1481 } 1482 1483 /* 1484 * Set chip parameters through the chip I/O widget. NO MUTEX. 1485 */ 1486 static void chipio_set_control_param_no_mutex(struct hda_codec *codec, 1487 enum control_param_id param_id, int param_val) 1488 { 1489 int val; 1490 1491 if ((param_id < 32) && (param_val < 8)) { 1492 val = (param_val << 5) | (param_id); 1493 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1494 VENDOR_CHIPIO_PARAM_SET, val); 1495 } else { 1496 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1497 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1498 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1499 param_id); 1500 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1501 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1502 param_val); 1503 } 1504 } 1505 } 1506 /* 1507 * Connect stream to a source point, and then connect 1508 * that source point to a destination point. 1509 */ 1510 static void chipio_set_stream_source_dest(struct hda_codec *codec, 1511 int streamid, int source_point, int dest_point) 1512 { 1513 chipio_set_control_param_no_mutex(codec, 1514 CONTROL_PARAM_STREAM_ID, streamid); 1515 chipio_set_control_param_no_mutex(codec, 1516 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point); 1517 chipio_set_control_param_no_mutex(codec, 1518 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point); 1519 } 1520 1521 /* 1522 * Set number of channels in the selected stream. 1523 */ 1524 static void chipio_set_stream_channels(struct hda_codec *codec, 1525 int streamid, unsigned int channels) 1526 { 1527 chipio_set_control_param_no_mutex(codec, 1528 CONTROL_PARAM_STREAM_ID, streamid); 1529 chipio_set_control_param_no_mutex(codec, 1530 CONTROL_PARAM_STREAMS_CHANNELS, channels); 1531 } 1532 1533 /* 1534 * Enable/Disable audio stream. 1535 */ 1536 static void chipio_set_stream_control(struct hda_codec *codec, 1537 int streamid, int enable) 1538 { 1539 chipio_set_control_param_no_mutex(codec, 1540 CONTROL_PARAM_STREAM_ID, streamid); 1541 chipio_set_control_param_no_mutex(codec, 1542 CONTROL_PARAM_STREAM_CONTROL, enable); 1543 } 1544 1545 1546 /* 1547 * Set sampling rate of the connection point. NO MUTEX. 1548 */ 1549 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec, 1550 int connid, enum ca0132_sample_rate rate) 1551 { 1552 chipio_set_control_param_no_mutex(codec, 1553 CONTROL_PARAM_CONN_POINT_ID, connid); 1554 chipio_set_control_param_no_mutex(codec, 1555 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate); 1556 } 1557 1558 /* 1559 * Set sampling rate of the connection point. 1560 */ 1561 static void chipio_set_conn_rate(struct hda_codec *codec, 1562 int connid, enum ca0132_sample_rate rate) 1563 { 1564 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid); 1565 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, 1566 rate); 1567 } 1568 1569 /* 1570 * Writes to the 8051's internal address space directly instead of indirectly, 1571 * giving access to the special function registers located at addresses 1572 * 0x80-0xFF. 1573 */ 1574 static void chipio_8051_write_direct(struct hda_codec *codec, 1575 unsigned int addr, unsigned int data) 1576 { 1577 unsigned int verb; 1578 1579 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data; 1580 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr); 1581 } 1582 1583 /* 1584 * Enable clocks. 1585 */ 1586 static void chipio_enable_clocks(struct hda_codec *codec) 1587 { 1588 struct ca0132_spec *spec = codec->spec; 1589 1590 mutex_lock(&spec->chipio_mutex); 1591 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1592 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0); 1593 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1594 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); 1595 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1596 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5); 1597 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1598 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b); 1599 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1600 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6); 1601 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1602 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); 1603 mutex_unlock(&spec->chipio_mutex); 1604 } 1605 1606 /* 1607 * CA0132 DSP IO stuffs 1608 */ 1609 static int dspio_send(struct hda_codec *codec, unsigned int reg, 1610 unsigned int data) 1611 { 1612 int res; 1613 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1614 1615 /* send bits of data specified by reg to dsp */ 1616 do { 1617 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data); 1618 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY)) 1619 return res; 1620 msleep(20); 1621 } while (time_before(jiffies, timeout)); 1622 1623 return -EIO; 1624 } 1625 1626 /* 1627 * Wait for DSP to be ready for commands 1628 */ 1629 static void dspio_write_wait(struct hda_codec *codec) 1630 { 1631 int status; 1632 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1633 1634 do { 1635 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1636 VENDOR_DSPIO_STATUS, 0); 1637 if ((status == VENDOR_STATUS_DSPIO_OK) || 1638 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)) 1639 break; 1640 msleep(1); 1641 } while (time_before(jiffies, timeout)); 1642 } 1643 1644 /* 1645 * Write SCP data to DSP 1646 */ 1647 static int dspio_write(struct hda_codec *codec, unsigned int scp_data) 1648 { 1649 struct ca0132_spec *spec = codec->spec; 1650 int status; 1651 1652 dspio_write_wait(codec); 1653 1654 mutex_lock(&spec->chipio_mutex); 1655 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW, 1656 scp_data & 0xffff); 1657 if (status < 0) 1658 goto error; 1659 1660 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH, 1661 scp_data >> 16); 1662 if (status < 0) 1663 goto error; 1664 1665 /* OK, now check if the write itself has executed*/ 1666 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1667 VENDOR_DSPIO_STATUS, 0); 1668 error: 1669 mutex_unlock(&spec->chipio_mutex); 1670 1671 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ? 1672 -EIO : 0; 1673 } 1674 1675 /* 1676 * Write multiple SCP data to DSP 1677 */ 1678 static int dspio_write_multiple(struct hda_codec *codec, 1679 unsigned int *buffer, unsigned int size) 1680 { 1681 int status = 0; 1682 unsigned int count; 1683 1684 if (buffer == NULL) 1685 return -EINVAL; 1686 1687 count = 0; 1688 while (count < size) { 1689 status = dspio_write(codec, *buffer++); 1690 if (status != 0) 1691 break; 1692 count++; 1693 } 1694 1695 return status; 1696 } 1697 1698 static int dspio_read(struct hda_codec *codec, unsigned int *data) 1699 { 1700 int status; 1701 1702 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0); 1703 if (status == -EIO) 1704 return status; 1705 1706 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0); 1707 if (status == -EIO || 1708 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY) 1709 return -EIO; 1710 1711 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1712 VENDOR_DSPIO_SCP_READ_DATA, 0); 1713 1714 return 0; 1715 } 1716 1717 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer, 1718 unsigned int *buf_size, unsigned int size_count) 1719 { 1720 int status = 0; 1721 unsigned int size = *buf_size; 1722 unsigned int count; 1723 unsigned int skip_count; 1724 unsigned int dummy; 1725 1726 if (buffer == NULL) 1727 return -1; 1728 1729 count = 0; 1730 while (count < size && count < size_count) { 1731 status = dspio_read(codec, buffer++); 1732 if (status != 0) 1733 break; 1734 count++; 1735 } 1736 1737 skip_count = count; 1738 if (status == 0) { 1739 while (skip_count < size) { 1740 status = dspio_read(codec, &dummy); 1741 if (status != 0) 1742 break; 1743 skip_count++; 1744 } 1745 } 1746 *buf_size = count; 1747 1748 return status; 1749 } 1750 1751 /* 1752 * Construct the SCP header using corresponding fields 1753 */ 1754 static inline unsigned int 1755 make_scp_header(unsigned int target_id, unsigned int source_id, 1756 unsigned int get_flag, unsigned int req, 1757 unsigned int device_flag, unsigned int resp_flag, 1758 unsigned int error_flag, unsigned int data_size) 1759 { 1760 unsigned int header = 0; 1761 1762 header = (data_size & 0x1f) << 27; 1763 header |= (error_flag & 0x01) << 26; 1764 header |= (resp_flag & 0x01) << 25; 1765 header |= (device_flag & 0x01) << 24; 1766 header |= (req & 0x7f) << 17; 1767 header |= (get_flag & 0x01) << 16; 1768 header |= (source_id & 0xff) << 8; 1769 header |= target_id & 0xff; 1770 1771 return header; 1772 } 1773 1774 /* 1775 * Extract corresponding fields from SCP header 1776 */ 1777 static inline void 1778 extract_scp_header(unsigned int header, 1779 unsigned int *target_id, unsigned int *source_id, 1780 unsigned int *get_flag, unsigned int *req, 1781 unsigned int *device_flag, unsigned int *resp_flag, 1782 unsigned int *error_flag, unsigned int *data_size) 1783 { 1784 if (data_size) 1785 *data_size = (header >> 27) & 0x1f; 1786 if (error_flag) 1787 *error_flag = (header >> 26) & 0x01; 1788 if (resp_flag) 1789 *resp_flag = (header >> 25) & 0x01; 1790 if (device_flag) 1791 *device_flag = (header >> 24) & 0x01; 1792 if (req) 1793 *req = (header >> 17) & 0x7f; 1794 if (get_flag) 1795 *get_flag = (header >> 16) & 0x01; 1796 if (source_id) 1797 *source_id = (header >> 8) & 0xff; 1798 if (target_id) 1799 *target_id = header & 0xff; 1800 } 1801 1802 #define SCP_MAX_DATA_WORDS (16) 1803 1804 /* Structure to contain any SCP message */ 1805 struct scp_msg { 1806 unsigned int hdr; 1807 unsigned int data[SCP_MAX_DATA_WORDS]; 1808 }; 1809 1810 static void dspio_clear_response_queue(struct hda_codec *codec) 1811 { 1812 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1813 unsigned int dummy = 0; 1814 int status; 1815 1816 /* clear all from the response queue */ 1817 do { 1818 status = dspio_read(codec, &dummy); 1819 } while (status == 0 && time_before(jiffies, timeout)); 1820 } 1821 1822 static int dspio_get_response_data(struct hda_codec *codec) 1823 { 1824 struct ca0132_spec *spec = codec->spec; 1825 unsigned int data = 0; 1826 unsigned int count; 1827 1828 if (dspio_read(codec, &data) < 0) 1829 return -EIO; 1830 1831 if ((data & 0x00ffffff) == spec->wait_scp_header) { 1832 spec->scp_resp_header = data; 1833 spec->scp_resp_count = data >> 27; 1834 count = spec->wait_num_data; 1835 dspio_read_multiple(codec, spec->scp_resp_data, 1836 &spec->scp_resp_count, count); 1837 return 0; 1838 } 1839 1840 return -EIO; 1841 } 1842 1843 /* 1844 * Send SCP message to DSP 1845 */ 1846 static int dspio_send_scp_message(struct hda_codec *codec, 1847 unsigned char *send_buf, 1848 unsigned int send_buf_size, 1849 unsigned char *return_buf, 1850 unsigned int return_buf_size, 1851 unsigned int *bytes_returned) 1852 { 1853 struct ca0132_spec *spec = codec->spec; 1854 int status = -1; 1855 unsigned int scp_send_size = 0; 1856 unsigned int total_size; 1857 bool waiting_for_resp = false; 1858 unsigned int header; 1859 struct scp_msg *ret_msg; 1860 unsigned int resp_src_id, resp_target_id; 1861 unsigned int data_size, src_id, target_id, get_flag, device_flag; 1862 1863 if (bytes_returned) 1864 *bytes_returned = 0; 1865 1866 /* get scp header from buffer */ 1867 header = *((unsigned int *)send_buf); 1868 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL, 1869 &device_flag, NULL, NULL, &data_size); 1870 scp_send_size = data_size + 1; 1871 total_size = (scp_send_size * 4); 1872 1873 if (send_buf_size < total_size) 1874 return -EINVAL; 1875 1876 if (get_flag || device_flag) { 1877 if (!return_buf || return_buf_size < 4 || !bytes_returned) 1878 return -EINVAL; 1879 1880 spec->wait_scp_header = *((unsigned int *)send_buf); 1881 1882 /* swap source id with target id */ 1883 resp_target_id = src_id; 1884 resp_src_id = target_id; 1885 spec->wait_scp_header &= 0xffff0000; 1886 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id); 1887 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1; 1888 spec->wait_scp = 1; 1889 waiting_for_resp = true; 1890 } 1891 1892 status = dspio_write_multiple(codec, (unsigned int *)send_buf, 1893 scp_send_size); 1894 if (status < 0) { 1895 spec->wait_scp = 0; 1896 return status; 1897 } 1898 1899 if (waiting_for_resp) { 1900 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1901 memset(return_buf, 0, return_buf_size); 1902 do { 1903 msleep(20); 1904 } while (spec->wait_scp && time_before(jiffies, timeout)); 1905 waiting_for_resp = false; 1906 if (!spec->wait_scp) { 1907 ret_msg = (struct scp_msg *)return_buf; 1908 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4); 1909 memcpy(&ret_msg->data, spec->scp_resp_data, 1910 spec->wait_num_data); 1911 *bytes_returned = (spec->scp_resp_count + 1) * 4; 1912 status = 0; 1913 } else { 1914 status = -EIO; 1915 } 1916 spec->wait_scp = 0; 1917 } 1918 1919 return status; 1920 } 1921 1922 /** 1923 * Prepare and send the SCP message to DSP 1924 * @codec: the HDA codec 1925 * @mod_id: ID of the DSP module to send the command 1926 * @src_id: ID of the source 1927 * @req: ID of request to send to the DSP module 1928 * @dir: SET or GET 1929 * @data: pointer to the data to send with the request, request specific 1930 * @len: length of the data, in bytes 1931 * @reply: point to the buffer to hold data returned for a reply 1932 * @reply_len: length of the reply buffer returned from GET 1933 * 1934 * Returns zero or a negative error code. 1935 */ 1936 static int dspio_scp(struct hda_codec *codec, 1937 int mod_id, int src_id, int req, int dir, const void *data, 1938 unsigned int len, void *reply, unsigned int *reply_len) 1939 { 1940 int status = 0; 1941 struct scp_msg scp_send, scp_reply; 1942 unsigned int ret_bytes, send_size, ret_size; 1943 unsigned int send_get_flag, reply_resp_flag, reply_error_flag; 1944 unsigned int reply_data_size; 1945 1946 memset(&scp_send, 0, sizeof(scp_send)); 1947 memset(&scp_reply, 0, sizeof(scp_reply)); 1948 1949 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS)) 1950 return -EINVAL; 1951 1952 if (dir == SCP_GET && reply == NULL) { 1953 codec_dbg(codec, "dspio_scp get but has no buffer\n"); 1954 return -EINVAL; 1955 } 1956 1957 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) { 1958 codec_dbg(codec, "dspio_scp bad resp buf len parms\n"); 1959 return -EINVAL; 1960 } 1961 1962 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req, 1963 0, 0, 0, len/sizeof(unsigned int)); 1964 if (data != NULL && len > 0) { 1965 len = min((unsigned int)(sizeof(scp_send.data)), len); 1966 memcpy(scp_send.data, data, len); 1967 } 1968 1969 ret_bytes = 0; 1970 send_size = sizeof(unsigned int) + len; 1971 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send, 1972 send_size, (unsigned char *)&scp_reply, 1973 sizeof(scp_reply), &ret_bytes); 1974 1975 if (status < 0) { 1976 codec_dbg(codec, "dspio_scp: send scp msg failed\n"); 1977 return status; 1978 } 1979 1980 /* extract send and reply headers members */ 1981 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag, 1982 NULL, NULL, NULL, NULL, NULL); 1983 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL, 1984 &reply_resp_flag, &reply_error_flag, 1985 &reply_data_size); 1986 1987 if (!send_get_flag) 1988 return 0; 1989 1990 if (reply_resp_flag && !reply_error_flag) { 1991 ret_size = (ret_bytes - sizeof(scp_reply.hdr)) 1992 / sizeof(unsigned int); 1993 1994 if (*reply_len < ret_size*sizeof(unsigned int)) { 1995 codec_dbg(codec, "reply too long for buf\n"); 1996 return -EINVAL; 1997 } else if (ret_size != reply_data_size) { 1998 codec_dbg(codec, "RetLen and HdrLen .NE.\n"); 1999 return -EINVAL; 2000 } else if (!reply) { 2001 codec_dbg(codec, "NULL reply\n"); 2002 return -EINVAL; 2003 } else { 2004 *reply_len = ret_size*sizeof(unsigned int); 2005 memcpy(reply, scp_reply.data, *reply_len); 2006 } 2007 } else { 2008 codec_dbg(codec, "reply ill-formed or errflag set\n"); 2009 return -EIO; 2010 } 2011 2012 return status; 2013 } 2014 2015 /* 2016 * Set DSP parameters 2017 */ 2018 static int dspio_set_param(struct hda_codec *codec, int mod_id, 2019 int src_id, int req, const void *data, unsigned int len) 2020 { 2021 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL, 2022 NULL); 2023 } 2024 2025 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id, 2026 int req, const unsigned int data) 2027 { 2028 return dspio_set_param(codec, mod_id, 0x20, req, &data, 2029 sizeof(unsigned int)); 2030 } 2031 2032 static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id, 2033 int req, const unsigned int data) 2034 { 2035 return dspio_set_param(codec, mod_id, 0x00, req, &data, 2036 sizeof(unsigned int)); 2037 } 2038 2039 /* 2040 * Allocate a DSP DMA channel via an SCP message 2041 */ 2042 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan) 2043 { 2044 int status = 0; 2045 unsigned int size = sizeof(dma_chan); 2046 2047 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n"); 2048 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2049 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0, 2050 dma_chan, &size); 2051 2052 if (status < 0) { 2053 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n"); 2054 return status; 2055 } 2056 2057 if ((*dma_chan + 1) == 0) { 2058 codec_dbg(codec, "no free dma channels to allocate\n"); 2059 return -EBUSY; 2060 } 2061 2062 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan); 2063 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n"); 2064 2065 return status; 2066 } 2067 2068 /* 2069 * Free a DSP DMA via an SCP message 2070 */ 2071 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan) 2072 { 2073 int status = 0; 2074 unsigned int dummy = 0; 2075 2076 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n"); 2077 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan); 2078 2079 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2080 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan, 2081 sizeof(dma_chan), NULL, &dummy); 2082 2083 if (status < 0) { 2084 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n"); 2085 return status; 2086 } 2087 2088 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n"); 2089 2090 return status; 2091 } 2092 2093 /* 2094 * (Re)start the DSP 2095 */ 2096 static int dsp_set_run_state(struct hda_codec *codec) 2097 { 2098 unsigned int dbg_ctrl_reg; 2099 unsigned int halt_state; 2100 int err; 2101 2102 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg); 2103 if (err < 0) 2104 return err; 2105 2106 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >> 2107 DSP_DBGCNTL_STATE_LOBIT; 2108 2109 if (halt_state != 0) { 2110 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) & 2111 DSP_DBGCNTL_SS_MASK); 2112 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2113 dbg_ctrl_reg); 2114 if (err < 0) 2115 return err; 2116 2117 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) & 2118 DSP_DBGCNTL_EXEC_MASK; 2119 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2120 dbg_ctrl_reg); 2121 if (err < 0) 2122 return err; 2123 } 2124 2125 return 0; 2126 } 2127 2128 /* 2129 * Reset the DSP 2130 */ 2131 static int dsp_reset(struct hda_codec *codec) 2132 { 2133 unsigned int res; 2134 int retry = 20; 2135 2136 codec_dbg(codec, "dsp_reset\n"); 2137 do { 2138 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0); 2139 retry--; 2140 } while (res == -EIO && retry); 2141 2142 if (!retry) { 2143 codec_dbg(codec, "dsp_reset timeout\n"); 2144 return -EIO; 2145 } 2146 2147 return 0; 2148 } 2149 2150 /* 2151 * Convert chip address to DSP address 2152 */ 2153 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx, 2154 bool *code, bool *yram) 2155 { 2156 *code = *yram = false; 2157 2158 if (UC_RANGE(chip_addx, 1)) { 2159 *code = true; 2160 return UC_OFF(chip_addx); 2161 } else if (X_RANGE_ALL(chip_addx, 1)) { 2162 return X_OFF(chip_addx); 2163 } else if (Y_RANGE_ALL(chip_addx, 1)) { 2164 *yram = true; 2165 return Y_OFF(chip_addx); 2166 } 2167 2168 return INVALID_CHIP_ADDRESS; 2169 } 2170 2171 /* 2172 * Check if the DSP DMA is active 2173 */ 2174 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan) 2175 { 2176 unsigned int dma_chnlstart_reg; 2177 2178 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg); 2179 2180 return ((dma_chnlstart_reg & (1 << 2181 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0); 2182 } 2183 2184 static int dsp_dma_setup_common(struct hda_codec *codec, 2185 unsigned int chip_addx, 2186 unsigned int dma_chan, 2187 unsigned int port_map_mask, 2188 bool ovly) 2189 { 2190 int status = 0; 2191 unsigned int chnl_prop; 2192 unsigned int dsp_addx; 2193 unsigned int active; 2194 bool code, yram; 2195 2196 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n"); 2197 2198 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) { 2199 codec_dbg(codec, "dma chan num invalid\n"); 2200 return -EINVAL; 2201 } 2202 2203 if (dsp_is_dma_active(codec, dma_chan)) { 2204 codec_dbg(codec, "dma already active\n"); 2205 return -EBUSY; 2206 } 2207 2208 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2209 2210 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2211 codec_dbg(codec, "invalid chip addr\n"); 2212 return -ENXIO; 2213 } 2214 2215 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK; 2216 active = 0; 2217 2218 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n"); 2219 2220 if (ovly) { 2221 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET, 2222 &chnl_prop); 2223 2224 if (status < 0) { 2225 codec_dbg(codec, "read CHNLPROP Reg fail\n"); 2226 return status; 2227 } 2228 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n"); 2229 } 2230 2231 if (!code) 2232 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2233 else 2234 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2235 2236 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan)); 2237 2238 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop); 2239 if (status < 0) { 2240 codec_dbg(codec, "write CHNLPROP Reg fail\n"); 2241 return status; 2242 } 2243 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n"); 2244 2245 if (ovly) { 2246 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET, 2247 &active); 2248 2249 if (status < 0) { 2250 codec_dbg(codec, "read ACTIVE Reg fail\n"); 2251 return status; 2252 } 2253 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n"); 2254 } 2255 2256 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) & 2257 DSPDMAC_ACTIVE_AAR_MASK; 2258 2259 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active); 2260 if (status < 0) { 2261 codec_dbg(codec, "write ACTIVE Reg fail\n"); 2262 return status; 2263 } 2264 2265 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n"); 2266 2267 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan), 2268 port_map_mask); 2269 if (status < 0) { 2270 codec_dbg(codec, "write AUDCHSEL Reg fail\n"); 2271 return status; 2272 } 2273 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n"); 2274 2275 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan), 2276 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK); 2277 if (status < 0) { 2278 codec_dbg(codec, "write IRQCNT Reg fail\n"); 2279 return status; 2280 } 2281 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n"); 2282 2283 codec_dbg(codec, 2284 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, " 2285 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n", 2286 chip_addx, dsp_addx, dma_chan, 2287 port_map_mask, chnl_prop, active); 2288 2289 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n"); 2290 2291 return 0; 2292 } 2293 2294 /* 2295 * Setup the DSP DMA per-transfer-specific registers 2296 */ 2297 static int dsp_dma_setup(struct hda_codec *codec, 2298 unsigned int chip_addx, 2299 unsigned int count, 2300 unsigned int dma_chan) 2301 { 2302 int status = 0; 2303 bool code, yram; 2304 unsigned int dsp_addx; 2305 unsigned int addr_field; 2306 unsigned int incr_field; 2307 unsigned int base_cnt; 2308 unsigned int cur_cnt; 2309 unsigned int dma_cfg = 0; 2310 unsigned int adr_ofs = 0; 2311 unsigned int xfr_cnt = 0; 2312 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT - 2313 DSPDMAC_XFRCNT_BCNT_LOBIT + 1); 2314 2315 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n"); 2316 2317 if (count > max_dma_count) { 2318 codec_dbg(codec, "count too big\n"); 2319 return -EINVAL; 2320 } 2321 2322 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2323 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2324 codec_dbg(codec, "invalid chip addr\n"); 2325 return -ENXIO; 2326 } 2327 2328 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n"); 2329 2330 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT; 2331 incr_field = 0; 2332 2333 if (!code) { 2334 addr_field <<= 1; 2335 if (yram) 2336 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT); 2337 2338 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT); 2339 } 2340 2341 dma_cfg = addr_field + incr_field; 2342 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan), 2343 dma_cfg); 2344 if (status < 0) { 2345 codec_dbg(codec, "write DMACFG Reg fail\n"); 2346 return status; 2347 } 2348 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n"); 2349 2350 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT + 2351 (code ? 0 : 1)); 2352 2353 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan), 2354 adr_ofs); 2355 if (status < 0) { 2356 codec_dbg(codec, "write DSPADROFS Reg fail\n"); 2357 return status; 2358 } 2359 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n"); 2360 2361 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT; 2362 2363 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT; 2364 2365 xfr_cnt = base_cnt | cur_cnt; 2366 2367 status = chipio_write(codec, 2368 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt); 2369 if (status < 0) { 2370 codec_dbg(codec, "write XFRCNT Reg fail\n"); 2371 return status; 2372 } 2373 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n"); 2374 2375 codec_dbg(codec, 2376 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, " 2377 "ADROFS=0x%x, XFRCNT=0x%x\n", 2378 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt); 2379 2380 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n"); 2381 2382 return 0; 2383 } 2384 2385 /* 2386 * Start the DSP DMA 2387 */ 2388 static int dsp_dma_start(struct hda_codec *codec, 2389 unsigned int dma_chan, bool ovly) 2390 { 2391 unsigned int reg = 0; 2392 int status = 0; 2393 2394 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n"); 2395 2396 if (ovly) { 2397 status = chipio_read(codec, 2398 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2399 2400 if (status < 0) { 2401 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2402 return status; 2403 } 2404 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n"); 2405 2406 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2407 DSPDMAC_CHNLSTART_DIS_MASK); 2408 } 2409 2410 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2411 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT))); 2412 if (status < 0) { 2413 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2414 return status; 2415 } 2416 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n"); 2417 2418 return status; 2419 } 2420 2421 /* 2422 * Stop the DSP DMA 2423 */ 2424 static int dsp_dma_stop(struct hda_codec *codec, 2425 unsigned int dma_chan, bool ovly) 2426 { 2427 unsigned int reg = 0; 2428 int status = 0; 2429 2430 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n"); 2431 2432 if (ovly) { 2433 status = chipio_read(codec, 2434 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2435 2436 if (status < 0) { 2437 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2438 return status; 2439 } 2440 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n"); 2441 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2442 DSPDMAC_CHNLSTART_DIS_MASK); 2443 } 2444 2445 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2446 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT))); 2447 if (status < 0) { 2448 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2449 return status; 2450 } 2451 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n"); 2452 2453 return status; 2454 } 2455 2456 /** 2457 * Allocate router ports 2458 * 2459 * @codec: the HDA codec 2460 * @num_chans: number of channels in the stream 2461 * @ports_per_channel: number of ports per channel 2462 * @start_device: start device 2463 * @port_map: pointer to the port list to hold the allocated ports 2464 * 2465 * Returns zero or a negative error code. 2466 */ 2467 static int dsp_allocate_router_ports(struct hda_codec *codec, 2468 unsigned int num_chans, 2469 unsigned int ports_per_channel, 2470 unsigned int start_device, 2471 unsigned int *port_map) 2472 { 2473 int status = 0; 2474 int res; 2475 u8 val; 2476 2477 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2478 if (status < 0) 2479 return status; 2480 2481 val = start_device << 6; 2482 val |= (ports_per_channel - 1) << 4; 2483 val |= num_chans - 1; 2484 2485 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2486 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET, 2487 val); 2488 2489 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2490 VENDOR_CHIPIO_PORT_ALLOC_SET, 2491 MEM_CONNID_DSP); 2492 2493 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2494 if (status < 0) 2495 return status; 2496 2497 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 2498 VENDOR_CHIPIO_PORT_ALLOC_GET, 0); 2499 2500 *port_map = res; 2501 2502 return (res < 0) ? res : 0; 2503 } 2504 2505 /* 2506 * Free router ports 2507 */ 2508 static int dsp_free_router_ports(struct hda_codec *codec) 2509 { 2510 int status = 0; 2511 2512 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2513 if (status < 0) 2514 return status; 2515 2516 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2517 VENDOR_CHIPIO_PORT_FREE_SET, 2518 MEM_CONNID_DSP); 2519 2520 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2521 2522 return status; 2523 } 2524 2525 /* 2526 * Allocate DSP ports for the download stream 2527 */ 2528 static int dsp_allocate_ports(struct hda_codec *codec, 2529 unsigned int num_chans, 2530 unsigned int rate_multi, unsigned int *port_map) 2531 { 2532 int status; 2533 2534 codec_dbg(codec, " dsp_allocate_ports() -- begin\n"); 2535 2536 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2537 codec_dbg(codec, "bad rate multiple\n"); 2538 return -EINVAL; 2539 } 2540 2541 status = dsp_allocate_router_ports(codec, num_chans, 2542 rate_multi, 0, port_map); 2543 2544 codec_dbg(codec, " dsp_allocate_ports() -- complete\n"); 2545 2546 return status; 2547 } 2548 2549 static int dsp_allocate_ports_format(struct hda_codec *codec, 2550 const unsigned short fmt, 2551 unsigned int *port_map) 2552 { 2553 int status; 2554 unsigned int num_chans; 2555 2556 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1; 2557 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1; 2558 unsigned int rate_multi = sample_rate_mul / sample_rate_div; 2559 2560 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2561 codec_dbg(codec, "bad rate multiple\n"); 2562 return -EINVAL; 2563 } 2564 2565 num_chans = get_hdafmt_chs(fmt) + 1; 2566 2567 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map); 2568 2569 return status; 2570 } 2571 2572 /* 2573 * free DSP ports 2574 */ 2575 static int dsp_free_ports(struct hda_codec *codec) 2576 { 2577 int status; 2578 2579 codec_dbg(codec, " dsp_free_ports() -- begin\n"); 2580 2581 status = dsp_free_router_ports(codec); 2582 if (status < 0) { 2583 codec_dbg(codec, "free router ports fail\n"); 2584 return status; 2585 } 2586 codec_dbg(codec, " dsp_free_ports() -- complete\n"); 2587 2588 return status; 2589 } 2590 2591 /* 2592 * HDA DMA engine stuffs for DSP code download 2593 */ 2594 struct dma_engine { 2595 struct hda_codec *codec; 2596 unsigned short m_converter_format; 2597 struct snd_dma_buffer *dmab; 2598 unsigned int buf_size; 2599 }; 2600 2601 2602 enum dma_state { 2603 DMA_STATE_STOP = 0, 2604 DMA_STATE_RUN = 1 2605 }; 2606 2607 static int dma_convert_to_hda_format(struct hda_codec *codec, 2608 unsigned int sample_rate, 2609 unsigned short channels, 2610 unsigned short *hda_format) 2611 { 2612 unsigned int format_val; 2613 2614 format_val = snd_hdac_calc_stream_format(sample_rate, 2615 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0); 2616 2617 if (hda_format) 2618 *hda_format = (unsigned short)format_val; 2619 2620 return 0; 2621 } 2622 2623 /* 2624 * Reset DMA for DSP download 2625 */ 2626 static int dma_reset(struct dma_engine *dma) 2627 { 2628 struct hda_codec *codec = dma->codec; 2629 struct ca0132_spec *spec = codec->spec; 2630 int status; 2631 2632 if (dma->dmab->area) 2633 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab); 2634 2635 status = snd_hda_codec_load_dsp_prepare(codec, 2636 dma->m_converter_format, 2637 dma->buf_size, 2638 dma->dmab); 2639 if (status < 0) 2640 return status; 2641 spec->dsp_stream_id = status; 2642 return 0; 2643 } 2644 2645 static int dma_set_state(struct dma_engine *dma, enum dma_state state) 2646 { 2647 bool cmd; 2648 2649 switch (state) { 2650 case DMA_STATE_STOP: 2651 cmd = false; 2652 break; 2653 case DMA_STATE_RUN: 2654 cmd = true; 2655 break; 2656 default: 2657 return 0; 2658 } 2659 2660 snd_hda_codec_load_dsp_trigger(dma->codec, cmd); 2661 return 0; 2662 } 2663 2664 static unsigned int dma_get_buffer_size(struct dma_engine *dma) 2665 { 2666 return dma->dmab->bytes; 2667 } 2668 2669 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma) 2670 { 2671 return dma->dmab->area; 2672 } 2673 2674 static int dma_xfer(struct dma_engine *dma, 2675 const unsigned int *data, 2676 unsigned int count) 2677 { 2678 memcpy(dma->dmab->area, data, count); 2679 return 0; 2680 } 2681 2682 static void dma_get_converter_format( 2683 struct dma_engine *dma, 2684 unsigned short *format) 2685 { 2686 if (format) 2687 *format = dma->m_converter_format; 2688 } 2689 2690 static unsigned int dma_get_stream_id(struct dma_engine *dma) 2691 { 2692 struct ca0132_spec *spec = dma->codec->spec; 2693 2694 return spec->dsp_stream_id; 2695 } 2696 2697 struct dsp_image_seg { 2698 u32 magic; 2699 u32 chip_addr; 2700 u32 count; 2701 u32 data[0]; 2702 }; 2703 2704 static const u32 g_magic_value = 0x4c46584d; 2705 static const u32 g_chip_addr_magic_value = 0xFFFFFF01; 2706 2707 static bool is_valid(const struct dsp_image_seg *p) 2708 { 2709 return p->magic == g_magic_value; 2710 } 2711 2712 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p) 2713 { 2714 return g_chip_addr_magic_value == p->chip_addr; 2715 } 2716 2717 static bool is_last(const struct dsp_image_seg *p) 2718 { 2719 return p->count == 0; 2720 } 2721 2722 static size_t dsp_sizeof(const struct dsp_image_seg *p) 2723 { 2724 return struct_size(p, data, p->count); 2725 } 2726 2727 static const struct dsp_image_seg *get_next_seg_ptr( 2728 const struct dsp_image_seg *p) 2729 { 2730 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p)); 2731 } 2732 2733 /* 2734 * CA0132 chip DSP transfer stuffs. For DSP download. 2735 */ 2736 #define INVALID_DMA_CHANNEL (~0U) 2737 2738 /* 2739 * Program a list of address/data pairs via the ChipIO widget. 2740 * The segment data is in the format of successive pairs of words. 2741 * These are repeated as indicated by the segment's count field. 2742 */ 2743 static int dspxfr_hci_write(struct hda_codec *codec, 2744 const struct dsp_image_seg *fls) 2745 { 2746 int status; 2747 const u32 *data; 2748 unsigned int count; 2749 2750 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) { 2751 codec_dbg(codec, "hci_write invalid params\n"); 2752 return -EINVAL; 2753 } 2754 2755 count = fls->count; 2756 data = (u32 *)(fls->data); 2757 while (count >= 2) { 2758 status = chipio_write(codec, data[0], data[1]); 2759 if (status < 0) { 2760 codec_dbg(codec, "hci_write chipio failed\n"); 2761 return status; 2762 } 2763 count -= 2; 2764 data += 2; 2765 } 2766 return 0; 2767 } 2768 2769 /** 2770 * Write a block of data into DSP code or data RAM using pre-allocated 2771 * DMA engine. 2772 * 2773 * @codec: the HDA codec 2774 * @fls: pointer to a fast load image 2775 * @reloc: Relocation address for loading single-segment overlays, or 0 for 2776 * no relocation 2777 * @dma_engine: pointer to DMA engine to be used for DSP download 2778 * @dma_chan: The number of DMA channels used for DSP download 2779 * @port_map_mask: port mapping 2780 * @ovly: TRUE if overlay format is required 2781 * 2782 * Returns zero or a negative error code. 2783 */ 2784 static int dspxfr_one_seg(struct hda_codec *codec, 2785 const struct dsp_image_seg *fls, 2786 unsigned int reloc, 2787 struct dma_engine *dma_engine, 2788 unsigned int dma_chan, 2789 unsigned int port_map_mask, 2790 bool ovly) 2791 { 2792 int status = 0; 2793 bool comm_dma_setup_done = false; 2794 const unsigned int *data; 2795 unsigned int chip_addx; 2796 unsigned int words_to_write; 2797 unsigned int buffer_size_words; 2798 unsigned char *buffer_addx; 2799 unsigned short hda_format; 2800 unsigned int sample_rate_div; 2801 unsigned int sample_rate_mul; 2802 unsigned int num_chans; 2803 unsigned int hda_frame_size_words; 2804 unsigned int remainder_words; 2805 const u32 *data_remainder; 2806 u32 chip_addx_remainder; 2807 unsigned int run_size_words; 2808 const struct dsp_image_seg *hci_write = NULL; 2809 unsigned long timeout; 2810 bool dma_active; 2811 2812 if (fls == NULL) 2813 return -EINVAL; 2814 if (is_hci_prog_list_seg(fls)) { 2815 hci_write = fls; 2816 fls = get_next_seg_ptr(fls); 2817 } 2818 2819 if (hci_write && (!fls || is_last(fls))) { 2820 codec_dbg(codec, "hci_write\n"); 2821 return dspxfr_hci_write(codec, hci_write); 2822 } 2823 2824 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) { 2825 codec_dbg(codec, "Invalid Params\n"); 2826 return -EINVAL; 2827 } 2828 2829 data = fls->data; 2830 chip_addx = fls->chip_addr, 2831 words_to_write = fls->count; 2832 2833 if (!words_to_write) 2834 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0; 2835 if (reloc) 2836 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2); 2837 2838 if (!UC_RANGE(chip_addx, words_to_write) && 2839 !X_RANGE_ALL(chip_addx, words_to_write) && 2840 !Y_RANGE_ALL(chip_addx, words_to_write)) { 2841 codec_dbg(codec, "Invalid chip_addx Params\n"); 2842 return -EINVAL; 2843 } 2844 2845 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) / 2846 sizeof(u32); 2847 2848 buffer_addx = dma_get_buffer_addr(dma_engine); 2849 2850 if (buffer_addx == NULL) { 2851 codec_dbg(codec, "dma_engine buffer NULL\n"); 2852 return -EINVAL; 2853 } 2854 2855 dma_get_converter_format(dma_engine, &hda_format); 2856 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1; 2857 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1; 2858 num_chans = get_hdafmt_chs(hda_format) + 1; 2859 2860 hda_frame_size_words = ((sample_rate_div == 0) ? 0 : 2861 (num_chans * sample_rate_mul / sample_rate_div)); 2862 2863 if (hda_frame_size_words == 0) { 2864 codec_dbg(codec, "frmsz zero\n"); 2865 return -EINVAL; 2866 } 2867 2868 buffer_size_words = min(buffer_size_words, 2869 (unsigned int)(UC_RANGE(chip_addx, 1) ? 2870 65536 : 32768)); 2871 buffer_size_words -= buffer_size_words % hda_frame_size_words; 2872 codec_dbg(codec, 2873 "chpadr=0x%08x frmsz=%u nchan=%u " 2874 "rate_mul=%u div=%u bufsz=%u\n", 2875 chip_addx, hda_frame_size_words, num_chans, 2876 sample_rate_mul, sample_rate_div, buffer_size_words); 2877 2878 if (buffer_size_words < hda_frame_size_words) { 2879 codec_dbg(codec, "dspxfr_one_seg:failed\n"); 2880 return -EINVAL; 2881 } 2882 2883 remainder_words = words_to_write % hda_frame_size_words; 2884 data_remainder = data; 2885 chip_addx_remainder = chip_addx; 2886 2887 data += remainder_words; 2888 chip_addx += remainder_words*sizeof(u32); 2889 words_to_write -= remainder_words; 2890 2891 while (words_to_write != 0) { 2892 run_size_words = min(buffer_size_words, words_to_write); 2893 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n", 2894 words_to_write, run_size_words, remainder_words); 2895 dma_xfer(dma_engine, data, run_size_words*sizeof(u32)); 2896 if (!comm_dma_setup_done) { 2897 status = dsp_dma_stop(codec, dma_chan, ovly); 2898 if (status < 0) 2899 return status; 2900 status = dsp_dma_setup_common(codec, chip_addx, 2901 dma_chan, port_map_mask, ovly); 2902 if (status < 0) 2903 return status; 2904 comm_dma_setup_done = true; 2905 } 2906 2907 status = dsp_dma_setup(codec, chip_addx, 2908 run_size_words, dma_chan); 2909 if (status < 0) 2910 return status; 2911 status = dsp_dma_start(codec, dma_chan, ovly); 2912 if (status < 0) 2913 return status; 2914 if (!dsp_is_dma_active(codec, dma_chan)) { 2915 codec_dbg(codec, "dspxfr:DMA did not start\n"); 2916 return -EIO; 2917 } 2918 status = dma_set_state(dma_engine, DMA_STATE_RUN); 2919 if (status < 0) 2920 return status; 2921 if (remainder_words != 0) { 2922 status = chipio_write_multiple(codec, 2923 chip_addx_remainder, 2924 data_remainder, 2925 remainder_words); 2926 if (status < 0) 2927 return status; 2928 remainder_words = 0; 2929 } 2930 if (hci_write) { 2931 status = dspxfr_hci_write(codec, hci_write); 2932 if (status < 0) 2933 return status; 2934 hci_write = NULL; 2935 } 2936 2937 timeout = jiffies + msecs_to_jiffies(2000); 2938 do { 2939 dma_active = dsp_is_dma_active(codec, dma_chan); 2940 if (!dma_active) 2941 break; 2942 msleep(20); 2943 } while (time_before(jiffies, timeout)); 2944 if (dma_active) 2945 break; 2946 2947 codec_dbg(codec, "+++++ DMA complete\n"); 2948 dma_set_state(dma_engine, DMA_STATE_STOP); 2949 status = dma_reset(dma_engine); 2950 2951 if (status < 0) 2952 return status; 2953 2954 data += run_size_words; 2955 chip_addx += run_size_words*sizeof(u32); 2956 words_to_write -= run_size_words; 2957 } 2958 2959 if (remainder_words != 0) { 2960 status = chipio_write_multiple(codec, chip_addx_remainder, 2961 data_remainder, remainder_words); 2962 } 2963 2964 return status; 2965 } 2966 2967 /** 2968 * Write the entire DSP image of a DSP code/data overlay to DSP memories 2969 * 2970 * @codec: the HDA codec 2971 * @fls_data: pointer to a fast load image 2972 * @reloc: Relocation address for loading single-segment overlays, or 0 for 2973 * no relocation 2974 * @sample_rate: sampling rate of the stream used for DSP download 2975 * @channels: channels of the stream used for DSP download 2976 * @ovly: TRUE if overlay format is required 2977 * 2978 * Returns zero or a negative error code. 2979 */ 2980 static int dspxfr_image(struct hda_codec *codec, 2981 const struct dsp_image_seg *fls_data, 2982 unsigned int reloc, 2983 unsigned int sample_rate, 2984 unsigned short channels, 2985 bool ovly) 2986 { 2987 struct ca0132_spec *spec = codec->spec; 2988 int status; 2989 unsigned short hda_format = 0; 2990 unsigned int response; 2991 unsigned char stream_id = 0; 2992 struct dma_engine *dma_engine; 2993 unsigned int dma_chan; 2994 unsigned int port_map_mask; 2995 2996 if (fls_data == NULL) 2997 return -EINVAL; 2998 2999 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL); 3000 if (!dma_engine) 3001 return -ENOMEM; 3002 3003 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL); 3004 if (!dma_engine->dmab) { 3005 kfree(dma_engine); 3006 return -ENOMEM; 3007 } 3008 3009 dma_engine->codec = codec; 3010 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format); 3011 dma_engine->m_converter_format = hda_format; 3012 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY : 3013 DSP_DMA_WRITE_BUFLEN_INIT) * 2; 3014 3015 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0; 3016 3017 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL, 3018 hda_format, &response); 3019 3020 if (status < 0) { 3021 codec_dbg(codec, "set converter format fail\n"); 3022 goto exit; 3023 } 3024 3025 status = snd_hda_codec_load_dsp_prepare(codec, 3026 dma_engine->m_converter_format, 3027 dma_engine->buf_size, 3028 dma_engine->dmab); 3029 if (status < 0) 3030 goto exit; 3031 spec->dsp_stream_id = status; 3032 3033 if (ovly) { 3034 status = dspio_alloc_dma_chan(codec, &dma_chan); 3035 if (status < 0) { 3036 codec_dbg(codec, "alloc dmachan fail\n"); 3037 dma_chan = INVALID_DMA_CHANNEL; 3038 goto exit; 3039 } 3040 } 3041 3042 port_map_mask = 0; 3043 status = dsp_allocate_ports_format(codec, hda_format, 3044 &port_map_mask); 3045 if (status < 0) { 3046 codec_dbg(codec, "alloc ports fail\n"); 3047 goto exit; 3048 } 3049 3050 stream_id = dma_get_stream_id(dma_engine); 3051 status = codec_set_converter_stream_channel(codec, 3052 WIDGET_CHIP_CTRL, stream_id, 0, &response); 3053 if (status < 0) { 3054 codec_dbg(codec, "set stream chan fail\n"); 3055 goto exit; 3056 } 3057 3058 while ((fls_data != NULL) && !is_last(fls_data)) { 3059 if (!is_valid(fls_data)) { 3060 codec_dbg(codec, "FLS check fail\n"); 3061 status = -EINVAL; 3062 goto exit; 3063 } 3064 status = dspxfr_one_seg(codec, fls_data, reloc, 3065 dma_engine, dma_chan, 3066 port_map_mask, ovly); 3067 if (status < 0) 3068 break; 3069 3070 if (is_hci_prog_list_seg(fls_data)) 3071 fls_data = get_next_seg_ptr(fls_data); 3072 3073 if ((fls_data != NULL) && !is_last(fls_data)) 3074 fls_data = get_next_seg_ptr(fls_data); 3075 } 3076 3077 if (port_map_mask != 0) 3078 status = dsp_free_ports(codec); 3079 3080 if (status < 0) 3081 goto exit; 3082 3083 status = codec_set_converter_stream_channel(codec, 3084 WIDGET_CHIP_CTRL, 0, 0, &response); 3085 3086 exit: 3087 if (ovly && (dma_chan != INVALID_DMA_CHANNEL)) 3088 dspio_free_dma_chan(codec, dma_chan); 3089 3090 if (dma_engine->dmab->area) 3091 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab); 3092 kfree(dma_engine->dmab); 3093 kfree(dma_engine); 3094 3095 return status; 3096 } 3097 3098 /* 3099 * CA0132 DSP download stuffs. 3100 */ 3101 static void dspload_post_setup(struct hda_codec *codec) 3102 { 3103 struct ca0132_spec *spec = codec->spec; 3104 codec_dbg(codec, "---- dspload_post_setup ------\n"); 3105 if (!ca0132_use_alt_functions(spec)) { 3106 /*set DSP speaker to 2.0 configuration*/ 3107 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080); 3108 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000); 3109 3110 /*update write pointer*/ 3111 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002); 3112 } 3113 } 3114 3115 /** 3116 * dspload_image - Download DSP from a DSP Image Fast Load structure. 3117 * 3118 * @codec: the HDA codec 3119 * @fls: pointer to a fast load image 3120 * @ovly: TRUE if overlay format is required 3121 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3122 * no relocation 3123 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE 3124 * @router_chans: number of audio router channels to be allocated (0 means use 3125 * internal defaults; max is 32) 3126 * 3127 * Download DSP from a DSP Image Fast Load structure. This structure is a 3128 * linear, non-constant sized element array of structures, each of which 3129 * contain the count of the data to be loaded, the data itself, and the 3130 * corresponding starting chip address of the starting data location. 3131 * Returns zero or a negative error code. 3132 */ 3133 static int dspload_image(struct hda_codec *codec, 3134 const struct dsp_image_seg *fls, 3135 bool ovly, 3136 unsigned int reloc, 3137 bool autostart, 3138 int router_chans) 3139 { 3140 int status = 0; 3141 unsigned int sample_rate; 3142 unsigned short channels; 3143 3144 codec_dbg(codec, "---- dspload_image begin ------\n"); 3145 if (router_chans == 0) { 3146 if (!ovly) 3147 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS; 3148 else 3149 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS; 3150 } 3151 3152 sample_rate = 48000; 3153 channels = (unsigned short)router_chans; 3154 3155 while (channels > 16) { 3156 sample_rate *= 2; 3157 channels /= 2; 3158 } 3159 3160 do { 3161 codec_dbg(codec, "Ready to program DMA\n"); 3162 if (!ovly) 3163 status = dsp_reset(codec); 3164 3165 if (status < 0) 3166 break; 3167 3168 codec_dbg(codec, "dsp_reset() complete\n"); 3169 status = dspxfr_image(codec, fls, reloc, sample_rate, channels, 3170 ovly); 3171 3172 if (status < 0) 3173 break; 3174 3175 codec_dbg(codec, "dspxfr_image() complete\n"); 3176 if (autostart && !ovly) { 3177 dspload_post_setup(codec); 3178 status = dsp_set_run_state(codec); 3179 } 3180 3181 codec_dbg(codec, "LOAD FINISHED\n"); 3182 } while (0); 3183 3184 return status; 3185 } 3186 3187 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 3188 static bool dspload_is_loaded(struct hda_codec *codec) 3189 { 3190 unsigned int data = 0; 3191 int status = 0; 3192 3193 status = chipio_read(codec, 0x40004, &data); 3194 if ((status < 0) || (data != 1)) 3195 return false; 3196 3197 return true; 3198 } 3199 #else 3200 #define dspload_is_loaded(codec) false 3201 #endif 3202 3203 static bool dspload_wait_loaded(struct hda_codec *codec) 3204 { 3205 unsigned long timeout = jiffies + msecs_to_jiffies(2000); 3206 3207 do { 3208 if (dspload_is_loaded(codec)) { 3209 codec_info(codec, "ca0132 DSP downloaded and running\n"); 3210 return true; 3211 } 3212 msleep(20); 3213 } while (time_before(jiffies, timeout)); 3214 3215 codec_err(codec, "ca0132 failed to download DSP\n"); 3216 return false; 3217 } 3218 3219 /* 3220 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e 3221 * based cards, and has a second mmio region, region2, that's used for special 3222 * commands. 3223 */ 3224 3225 /* 3226 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5) 3227 * the mmio address 0x320 is used to set GPIO pins. The format for the data 3228 * The first eight bits are just the number of the pin. So far, I've only seen 3229 * this number go to 7. 3230 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value 3231 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and 3232 * then off to send that bit. 3233 */ 3234 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin, 3235 bool enable) 3236 { 3237 struct ca0132_spec *spec = codec->spec; 3238 unsigned short gpio_data; 3239 3240 gpio_data = gpio_pin & 0xF; 3241 gpio_data |= ((enable << 8) & 0x100); 3242 3243 writew(gpio_data, spec->mem_base + 0x320); 3244 } 3245 3246 /* 3247 * Special pci region2 commands that are only used by the AE-5. They follow 3248 * a set format, and require reads at certain points to seemingly 'clear' 3249 * the response data. My first tests didn't do these reads, and would cause 3250 * the card to get locked up until the memory was read. These commands 3251 * seem to work with three distinct values that I've taken to calling group, 3252 * target-id, and value. 3253 */ 3254 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group, 3255 unsigned int target, unsigned int value) 3256 { 3257 struct ca0132_spec *spec = codec->spec; 3258 unsigned int write_val; 3259 3260 writel(0x0000007e, spec->mem_base + 0x210); 3261 readl(spec->mem_base + 0x210); 3262 writel(0x0000005a, spec->mem_base + 0x210); 3263 readl(spec->mem_base + 0x210); 3264 readl(spec->mem_base + 0x210); 3265 3266 writel(0x00800005, spec->mem_base + 0x20c); 3267 writel(group, spec->mem_base + 0x804); 3268 3269 writel(0x00800005, spec->mem_base + 0x20c); 3270 write_val = (target & 0xff); 3271 write_val |= (value << 8); 3272 3273 3274 writel(write_val, spec->mem_base + 0x204); 3275 /* 3276 * Need delay here or else it goes too fast and works inconsistently. 3277 */ 3278 msleep(20); 3279 3280 readl(spec->mem_base + 0x860); 3281 readl(spec->mem_base + 0x854); 3282 readl(spec->mem_base + 0x840); 3283 3284 writel(0x00800004, spec->mem_base + 0x20c); 3285 writel(0x00000000, spec->mem_base + 0x210); 3286 readl(spec->mem_base + 0x210); 3287 readl(spec->mem_base + 0x210); 3288 } 3289 3290 /* 3291 * This second type of command is used for setting the sound filter type. 3292 */ 3293 static void ca0113_mmio_command_set_type2(struct hda_codec *codec, 3294 unsigned int group, unsigned int target, unsigned int value) 3295 { 3296 struct ca0132_spec *spec = codec->spec; 3297 unsigned int write_val; 3298 3299 writel(0x0000007e, spec->mem_base + 0x210); 3300 readl(spec->mem_base + 0x210); 3301 writel(0x0000005a, spec->mem_base + 0x210); 3302 readl(spec->mem_base + 0x210); 3303 readl(spec->mem_base + 0x210); 3304 3305 writel(0x00800003, spec->mem_base + 0x20c); 3306 writel(group, spec->mem_base + 0x804); 3307 3308 writel(0x00800005, spec->mem_base + 0x20c); 3309 write_val = (target & 0xff); 3310 write_val |= (value << 8); 3311 3312 3313 writel(write_val, spec->mem_base + 0x204); 3314 msleep(20); 3315 readl(spec->mem_base + 0x860); 3316 readl(spec->mem_base + 0x854); 3317 readl(spec->mem_base + 0x840); 3318 3319 writel(0x00800004, spec->mem_base + 0x20c); 3320 writel(0x00000000, spec->mem_base + 0x210); 3321 readl(spec->mem_base + 0x210); 3322 readl(spec->mem_base + 0x210); 3323 } 3324 3325 /* 3326 * Setup GPIO for the other variants of Core3D. 3327 */ 3328 3329 /* 3330 * Sets up the GPIO pins so that they are discoverable. If this isn't done, 3331 * the card shows as having no GPIO pins. 3332 */ 3333 static void ca0132_gpio_init(struct hda_codec *codec) 3334 { 3335 struct ca0132_spec *spec = codec->spec; 3336 3337 switch (ca0132_quirk(spec)) { 3338 case QUIRK_SBZ: 3339 case QUIRK_AE5: 3340 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3341 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 3342 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23); 3343 break; 3344 case QUIRK_R3DI: 3345 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3346 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B); 3347 break; 3348 default: 3349 break; 3350 } 3351 3352 } 3353 3354 /* Sets the GPIO for audio output. */ 3355 static void ca0132_gpio_setup(struct hda_codec *codec) 3356 { 3357 struct ca0132_spec *spec = codec->spec; 3358 3359 switch (ca0132_quirk(spec)) { 3360 case QUIRK_SBZ: 3361 snd_hda_codec_write(codec, 0x01, 0, 3362 AC_VERB_SET_GPIO_DIRECTION, 0x07); 3363 snd_hda_codec_write(codec, 0x01, 0, 3364 AC_VERB_SET_GPIO_MASK, 0x07); 3365 snd_hda_codec_write(codec, 0x01, 0, 3366 AC_VERB_SET_GPIO_DATA, 0x04); 3367 snd_hda_codec_write(codec, 0x01, 0, 3368 AC_VERB_SET_GPIO_DATA, 0x06); 3369 break; 3370 case QUIRK_R3DI: 3371 snd_hda_codec_write(codec, 0x01, 0, 3372 AC_VERB_SET_GPIO_DIRECTION, 0x1E); 3373 snd_hda_codec_write(codec, 0x01, 0, 3374 AC_VERB_SET_GPIO_MASK, 0x1F); 3375 snd_hda_codec_write(codec, 0x01, 0, 3376 AC_VERB_SET_GPIO_DATA, 0x0C); 3377 break; 3378 default: 3379 break; 3380 } 3381 } 3382 3383 /* 3384 * GPIO control functions for the Recon3D integrated. 3385 */ 3386 3387 enum r3di_gpio_bit { 3388 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */ 3389 R3DI_MIC_SELECT_BIT = 1, 3390 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */ 3391 R3DI_OUT_SELECT_BIT = 2, 3392 /* 3393 * I dunno what this actually does, but it stays on until the dsp 3394 * is downloaded. 3395 */ 3396 R3DI_GPIO_DSP_DOWNLOADING = 3, 3397 /* 3398 * Same as above, no clue what it does, but it comes on after the dsp 3399 * is downloaded. 3400 */ 3401 R3DI_GPIO_DSP_DOWNLOADED = 4 3402 }; 3403 3404 enum r3di_mic_select { 3405 /* Set GPIO bit 1 to 0 for rear mic */ 3406 R3DI_REAR_MIC = 0, 3407 /* Set GPIO bit 1 to 1 for front microphone*/ 3408 R3DI_FRONT_MIC = 1 3409 }; 3410 3411 enum r3di_out_select { 3412 /* Set GPIO bit 2 to 0 for headphone */ 3413 R3DI_HEADPHONE_OUT = 0, 3414 /* Set GPIO bit 2 to 1 for speaker */ 3415 R3DI_LINE_OUT = 1 3416 }; 3417 enum r3di_dsp_status { 3418 /* Set GPIO bit 3 to 1 until DSP is downloaded */ 3419 R3DI_DSP_DOWNLOADING = 0, 3420 /* Set GPIO bit 4 to 1 once DSP is downloaded */ 3421 R3DI_DSP_DOWNLOADED = 1 3422 }; 3423 3424 3425 static void r3di_gpio_mic_set(struct hda_codec *codec, 3426 enum r3di_mic_select cur_mic) 3427 { 3428 unsigned int cur_gpio; 3429 3430 /* Get the current GPIO Data setup */ 3431 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3432 3433 switch (cur_mic) { 3434 case R3DI_REAR_MIC: 3435 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT); 3436 break; 3437 case R3DI_FRONT_MIC: 3438 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT); 3439 break; 3440 } 3441 snd_hda_codec_write(codec, codec->core.afg, 0, 3442 AC_VERB_SET_GPIO_DATA, cur_gpio); 3443 } 3444 3445 static void r3di_gpio_out_set(struct hda_codec *codec, 3446 enum r3di_out_select cur_out) 3447 { 3448 unsigned int cur_gpio; 3449 3450 /* Get the current GPIO Data setup */ 3451 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3452 3453 switch (cur_out) { 3454 case R3DI_HEADPHONE_OUT: 3455 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT); 3456 break; 3457 case R3DI_LINE_OUT: 3458 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT); 3459 break; 3460 } 3461 snd_hda_codec_write(codec, codec->core.afg, 0, 3462 AC_VERB_SET_GPIO_DATA, cur_gpio); 3463 } 3464 3465 static void r3di_gpio_dsp_status_set(struct hda_codec *codec, 3466 enum r3di_dsp_status dsp_status) 3467 { 3468 unsigned int cur_gpio; 3469 3470 /* Get the current GPIO Data setup */ 3471 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3472 3473 switch (dsp_status) { 3474 case R3DI_DSP_DOWNLOADING: 3475 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING); 3476 snd_hda_codec_write(codec, codec->core.afg, 0, 3477 AC_VERB_SET_GPIO_DATA, cur_gpio); 3478 break; 3479 case R3DI_DSP_DOWNLOADED: 3480 /* Set DOWNLOADING bit to 0. */ 3481 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING); 3482 3483 snd_hda_codec_write(codec, codec->core.afg, 0, 3484 AC_VERB_SET_GPIO_DATA, cur_gpio); 3485 3486 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED); 3487 break; 3488 } 3489 3490 snd_hda_codec_write(codec, codec->core.afg, 0, 3491 AC_VERB_SET_GPIO_DATA, cur_gpio); 3492 } 3493 3494 /* 3495 * PCM callbacks 3496 */ 3497 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3498 struct hda_codec *codec, 3499 unsigned int stream_tag, 3500 unsigned int format, 3501 struct snd_pcm_substream *substream) 3502 { 3503 struct ca0132_spec *spec = codec->spec; 3504 3505 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format); 3506 3507 return 0; 3508 } 3509 3510 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3511 struct hda_codec *codec, 3512 struct snd_pcm_substream *substream) 3513 { 3514 struct ca0132_spec *spec = codec->spec; 3515 3516 if (spec->dsp_state == DSP_DOWNLOADING) 3517 return 0; 3518 3519 /*If Playback effects are on, allow stream some time to flush 3520 *effects tail*/ 3521 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 3522 msleep(50); 3523 3524 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 3525 3526 return 0; 3527 } 3528 3529 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info, 3530 struct hda_codec *codec, 3531 struct snd_pcm_substream *substream) 3532 { 3533 struct ca0132_spec *spec = codec->spec; 3534 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY; 3535 struct snd_pcm_runtime *runtime = substream->runtime; 3536 3537 if (spec->dsp_state != DSP_DOWNLOADED) 3538 return 0; 3539 3540 /* Add latency if playback enhancement and either effect is enabled. */ 3541 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) { 3542 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) || 3543 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID])) 3544 latency += DSP_PLAY_ENHANCEMENT_LATENCY; 3545 } 3546 3547 /* Applying Speaker EQ adds latency as well. */ 3548 if (spec->cur_out_type == SPEAKER_OUT) 3549 latency += DSP_SPEAKER_OUT_LATENCY; 3550 3551 return (latency * runtime->rate) / 1000; 3552 } 3553 3554 /* 3555 * Digital out 3556 */ 3557 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo, 3558 struct hda_codec *codec, 3559 struct snd_pcm_substream *substream) 3560 { 3561 struct ca0132_spec *spec = codec->spec; 3562 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3563 } 3564 3565 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3566 struct hda_codec *codec, 3567 unsigned int stream_tag, 3568 unsigned int format, 3569 struct snd_pcm_substream *substream) 3570 { 3571 struct ca0132_spec *spec = codec->spec; 3572 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3573 stream_tag, format, substream); 3574 } 3575 3576 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3577 struct hda_codec *codec, 3578 struct snd_pcm_substream *substream) 3579 { 3580 struct ca0132_spec *spec = codec->spec; 3581 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout); 3582 } 3583 3584 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo, 3585 struct hda_codec *codec, 3586 struct snd_pcm_substream *substream) 3587 { 3588 struct ca0132_spec *spec = codec->spec; 3589 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3590 } 3591 3592 /* 3593 * Analog capture 3594 */ 3595 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo, 3596 struct hda_codec *codec, 3597 unsigned int stream_tag, 3598 unsigned int format, 3599 struct snd_pcm_substream *substream) 3600 { 3601 snd_hda_codec_setup_stream(codec, hinfo->nid, 3602 stream_tag, 0, format); 3603 3604 return 0; 3605 } 3606 3607 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo, 3608 struct hda_codec *codec, 3609 struct snd_pcm_substream *substream) 3610 { 3611 struct ca0132_spec *spec = codec->spec; 3612 3613 if (spec->dsp_state == DSP_DOWNLOADING) 3614 return 0; 3615 3616 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 3617 return 0; 3618 } 3619 3620 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info, 3621 struct hda_codec *codec, 3622 struct snd_pcm_substream *substream) 3623 { 3624 struct ca0132_spec *spec = codec->spec; 3625 unsigned int latency = DSP_CAPTURE_INIT_LATENCY; 3626 struct snd_pcm_runtime *runtime = substream->runtime; 3627 3628 if (spec->dsp_state != DSP_DOWNLOADED) 3629 return 0; 3630 3631 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 3632 latency += DSP_CRYSTAL_VOICE_LATENCY; 3633 3634 return (latency * runtime->rate) / 1000; 3635 } 3636 3637 /* 3638 * Controls stuffs. 3639 */ 3640 3641 /* 3642 * Mixer controls helpers. 3643 */ 3644 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \ 3645 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3646 .name = xname, \ 3647 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3648 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3649 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 3650 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 3651 .info = ca0132_volume_info, \ 3652 .get = ca0132_volume_get, \ 3653 .put = ca0132_volume_put, \ 3654 .tlv = { .c = ca0132_volume_tlv }, \ 3655 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3656 3657 /* 3658 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the 3659 * volume put, which is used for setting the DSP volume. This was done because 3660 * the ca0132 functions were taking too much time and causing lag. 3661 */ 3662 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \ 3663 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3664 .name = xname, \ 3665 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3666 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3667 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 3668 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 3669 .info = snd_hda_mixer_amp_volume_info, \ 3670 .get = snd_hda_mixer_amp_volume_get, \ 3671 .put = ca0132_alt_volume_put, \ 3672 .tlv = { .c = snd_hda_mixer_amp_tlv }, \ 3673 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3674 3675 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \ 3676 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3677 .name = xname, \ 3678 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3679 .info = snd_hda_mixer_amp_switch_info, \ 3680 .get = ca0132_switch_get, \ 3681 .put = ca0132_switch_put, \ 3682 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3683 3684 /* stereo */ 3685 #define CA0132_CODEC_VOL(xname, nid, dir) \ 3686 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir) 3687 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \ 3688 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir) 3689 #define CA0132_CODEC_MUTE(xname, nid, dir) \ 3690 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir) 3691 3692 /* lookup tables */ 3693 /* 3694 * Lookup table with decibel values for the DSP. When volume is changed in 3695 * Windows, the DSP is also sent the dB value in floating point. In Windows, 3696 * these values have decimal points, probably because the Windows driver 3697 * actually uses floating point. We can't here, so I made a lookup table of 3698 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the 3699 * DAC's, and 9 is the maximum. 3700 */ 3701 static const unsigned int float_vol_db_lookup[] = { 3702 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000, 3703 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000, 3704 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000, 3705 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000, 3706 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000, 3707 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000, 3708 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000, 3709 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000, 3710 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000, 3711 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000, 3712 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000, 3713 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 3714 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 3715 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 3716 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 3717 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 3718 0x40C00000, 0x40E00000, 0x41000000, 0x41100000 3719 }; 3720 3721 /* 3722 * This table counts from float 0 to 1 in increments of .01, which is 3723 * useful for a few different sliders. 3724 */ 3725 static const unsigned int float_zero_to_one_lookup[] = { 3726 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 3727 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 3728 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 3729 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 3730 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 3731 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 3732 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 3733 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 3734 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 3735 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 3736 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 3737 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 3738 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 3739 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 3740 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 3741 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 3742 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 3743 }; 3744 3745 /* 3746 * This table counts from float 10 to 1000, which is the range of the x-bass 3747 * crossover slider in Windows. 3748 */ 3749 static const unsigned int float_xbass_xover_lookup[] = { 3750 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000, 3751 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000, 3752 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000, 3753 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000, 3754 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000, 3755 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000, 3756 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000, 3757 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000, 3758 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000, 3759 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000, 3760 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000, 3761 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000, 3762 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000, 3763 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000, 3764 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000, 3765 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000, 3766 0x44728000, 0x44750000, 0x44778000, 0x447A0000 3767 }; 3768 3769 /* The following are for tuning of products */ 3770 #ifdef ENABLE_TUNING_CONTROLS 3771 3772 static const unsigned int voice_focus_vals_lookup[] = { 3773 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000, 3774 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000, 3775 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000, 3776 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000, 3777 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000, 3778 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000, 3779 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000, 3780 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000, 3781 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000, 3782 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000, 3783 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000, 3784 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000, 3785 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000, 3786 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000, 3787 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000, 3788 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000, 3789 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000, 3790 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000, 3791 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000, 3792 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000, 3793 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000, 3794 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000, 3795 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000, 3796 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000, 3797 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000, 3798 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000, 3799 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000 3800 }; 3801 3802 static const unsigned int mic_svm_vals_lookup[] = { 3803 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 3804 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 3805 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 3806 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 3807 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 3808 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 3809 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 3810 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 3811 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 3812 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 3813 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 3814 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 3815 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 3816 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 3817 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 3818 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 3819 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 3820 }; 3821 3822 static const unsigned int equalizer_vals_lookup[] = { 3823 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 3824 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 3825 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 3826 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 3827 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 3828 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000, 3829 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000, 3830 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 3831 0x41C00000 3832 }; 3833 3834 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid, 3835 const unsigned int *lookup, int idx) 3836 { 3837 int i = 0; 3838 3839 for (i = 0; i < TUNING_CTLS_COUNT; i++) 3840 if (nid == ca0132_tuning_ctls[i].nid) 3841 break; 3842 3843 snd_hda_power_up(codec); 3844 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20, 3845 ca0132_tuning_ctls[i].req, 3846 &(lookup[idx]), sizeof(unsigned int)); 3847 snd_hda_power_down(codec); 3848 3849 return 1; 3850 } 3851 3852 static int tuning_ctl_get(struct snd_kcontrol *kcontrol, 3853 struct snd_ctl_elem_value *ucontrol) 3854 { 3855 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3856 struct ca0132_spec *spec = codec->spec; 3857 hda_nid_t nid = get_amp_nid(kcontrol); 3858 long *valp = ucontrol->value.integer.value; 3859 int idx = nid - TUNING_CTL_START_NID; 3860 3861 *valp = spec->cur_ctl_vals[idx]; 3862 return 0; 3863 } 3864 3865 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol, 3866 struct snd_ctl_elem_info *uinfo) 3867 { 3868 int chs = get_amp_channels(kcontrol); 3869 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3870 uinfo->count = chs == 3 ? 2 : 1; 3871 uinfo->value.integer.min = 20; 3872 uinfo->value.integer.max = 180; 3873 uinfo->value.integer.step = 1; 3874 3875 return 0; 3876 } 3877 3878 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol, 3879 struct snd_ctl_elem_value *ucontrol) 3880 { 3881 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3882 struct ca0132_spec *spec = codec->spec; 3883 hda_nid_t nid = get_amp_nid(kcontrol); 3884 long *valp = ucontrol->value.integer.value; 3885 int idx; 3886 3887 idx = nid - TUNING_CTL_START_NID; 3888 /* any change? */ 3889 if (spec->cur_ctl_vals[idx] == *valp) 3890 return 0; 3891 3892 spec->cur_ctl_vals[idx] = *valp; 3893 3894 idx = *valp - 20; 3895 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx); 3896 3897 return 1; 3898 } 3899 3900 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol, 3901 struct snd_ctl_elem_info *uinfo) 3902 { 3903 int chs = get_amp_channels(kcontrol); 3904 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3905 uinfo->count = chs == 3 ? 2 : 1; 3906 uinfo->value.integer.min = 0; 3907 uinfo->value.integer.max = 100; 3908 uinfo->value.integer.step = 1; 3909 3910 return 0; 3911 } 3912 3913 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol, 3914 struct snd_ctl_elem_value *ucontrol) 3915 { 3916 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3917 struct ca0132_spec *spec = codec->spec; 3918 hda_nid_t nid = get_amp_nid(kcontrol); 3919 long *valp = ucontrol->value.integer.value; 3920 int idx; 3921 3922 idx = nid - TUNING_CTL_START_NID; 3923 /* any change? */ 3924 if (spec->cur_ctl_vals[idx] == *valp) 3925 return 0; 3926 3927 spec->cur_ctl_vals[idx] = *valp; 3928 3929 idx = *valp; 3930 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx); 3931 3932 return 0; 3933 } 3934 3935 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol, 3936 struct snd_ctl_elem_info *uinfo) 3937 { 3938 int chs = get_amp_channels(kcontrol); 3939 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3940 uinfo->count = chs == 3 ? 2 : 1; 3941 uinfo->value.integer.min = 0; 3942 uinfo->value.integer.max = 48; 3943 uinfo->value.integer.step = 1; 3944 3945 return 0; 3946 } 3947 3948 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol, 3949 struct snd_ctl_elem_value *ucontrol) 3950 { 3951 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3952 struct ca0132_spec *spec = codec->spec; 3953 hda_nid_t nid = get_amp_nid(kcontrol); 3954 long *valp = ucontrol->value.integer.value; 3955 int idx; 3956 3957 idx = nid - TUNING_CTL_START_NID; 3958 /* any change? */ 3959 if (spec->cur_ctl_vals[idx] == *valp) 3960 return 0; 3961 3962 spec->cur_ctl_vals[idx] = *valp; 3963 3964 idx = *valp; 3965 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx); 3966 3967 return 1; 3968 } 3969 3970 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0); 3971 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0); 3972 3973 static int add_tuning_control(struct hda_codec *codec, 3974 hda_nid_t pnid, hda_nid_t nid, 3975 const char *name, int dir) 3976 { 3977 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 3978 int type = dir ? HDA_INPUT : HDA_OUTPUT; 3979 struct snd_kcontrol_new knew = 3980 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 3981 3982 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 3983 SNDRV_CTL_ELEM_ACCESS_TLV_READ; 3984 knew.tlv.c = 0; 3985 knew.tlv.p = 0; 3986 switch (pnid) { 3987 case VOICE_FOCUS: 3988 knew.info = voice_focus_ctl_info; 3989 knew.get = tuning_ctl_get; 3990 knew.put = voice_focus_ctl_put; 3991 knew.tlv.p = voice_focus_db_scale; 3992 break; 3993 case MIC_SVM: 3994 knew.info = mic_svm_ctl_info; 3995 knew.get = tuning_ctl_get; 3996 knew.put = mic_svm_ctl_put; 3997 break; 3998 case EQUALIZER: 3999 knew.info = equalizer_ctl_info; 4000 knew.get = tuning_ctl_get; 4001 knew.put = equalizer_ctl_put; 4002 knew.tlv.p = eq_db_scale; 4003 break; 4004 default: 4005 return 0; 4006 } 4007 knew.private_value = 4008 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 4009 sprintf(namestr, "%s %s Volume", name, dirstr[dir]); 4010 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 4011 } 4012 4013 static int add_tuning_ctls(struct hda_codec *codec) 4014 { 4015 int i; 4016 int err; 4017 4018 for (i = 0; i < TUNING_CTLS_COUNT; i++) { 4019 err = add_tuning_control(codec, 4020 ca0132_tuning_ctls[i].parent_nid, 4021 ca0132_tuning_ctls[i].nid, 4022 ca0132_tuning_ctls[i].name, 4023 ca0132_tuning_ctls[i].direct); 4024 if (err < 0) 4025 return err; 4026 } 4027 4028 return 0; 4029 } 4030 4031 static void ca0132_init_tuning_defaults(struct hda_codec *codec) 4032 { 4033 struct ca0132_spec *spec = codec->spec; 4034 int i; 4035 4036 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */ 4037 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10; 4038 /* SVM level defaults to 0.74. */ 4039 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74; 4040 4041 /* EQ defaults to 0dB. */ 4042 for (i = 2; i < TUNING_CTLS_COUNT; i++) 4043 spec->cur_ctl_vals[i] = 24; 4044 } 4045 #endif /*ENABLE_TUNING_CONTROLS*/ 4046 4047 /* 4048 * Select the active output. 4049 * If autodetect is enabled, output will be selected based on jack detection. 4050 * If jack inserted, headphone will be selected, else built-in speakers 4051 * If autodetect is disabled, output will be selected based on selection. 4052 */ 4053 static int ca0132_select_out(struct hda_codec *codec) 4054 { 4055 struct ca0132_spec *spec = codec->spec; 4056 unsigned int pin_ctl; 4057 int jack_present; 4058 int auto_jack; 4059 unsigned int tmp; 4060 int err; 4061 4062 codec_dbg(codec, "ca0132_select_out\n"); 4063 4064 snd_hda_power_up_pm(codec); 4065 4066 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4067 4068 if (auto_jack) 4069 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp); 4070 else 4071 jack_present = 4072 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID]; 4073 4074 if (jack_present) 4075 spec->cur_out_type = HEADPHONE_OUT; 4076 else 4077 spec->cur_out_type = SPEAKER_OUT; 4078 4079 if (spec->cur_out_type == SPEAKER_OUT) { 4080 codec_dbg(codec, "ca0132_select_out speaker\n"); 4081 /*speaker out config*/ 4082 tmp = FLOAT_ONE; 4083 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4084 if (err < 0) 4085 goto exit; 4086 /*enable speaker EQ*/ 4087 tmp = FLOAT_ONE; 4088 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4089 if (err < 0) 4090 goto exit; 4091 4092 /* Setup EAPD */ 4093 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4094 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4095 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4096 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4097 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4098 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4099 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4100 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4101 4102 /* disable headphone node */ 4103 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4104 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4105 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4106 pin_ctl & ~PIN_HP); 4107 /* enable speaker node */ 4108 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4109 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4110 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4111 pin_ctl | PIN_OUT); 4112 } else { 4113 codec_dbg(codec, "ca0132_select_out hp\n"); 4114 /*headphone out config*/ 4115 tmp = FLOAT_ZERO; 4116 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4117 if (err < 0) 4118 goto exit; 4119 /*disable speaker EQ*/ 4120 tmp = FLOAT_ZERO; 4121 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4122 if (err < 0) 4123 goto exit; 4124 4125 /* Setup EAPD */ 4126 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4127 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4128 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4129 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4130 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4131 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4132 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4133 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4134 4135 /* disable speaker*/ 4136 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4137 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4138 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4139 pin_ctl & ~PIN_HP); 4140 /* enable headphone*/ 4141 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4142 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4143 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4144 pin_ctl | PIN_HP); 4145 } 4146 4147 exit: 4148 snd_hda_power_down_pm(codec); 4149 4150 return err < 0 ? err : 0; 4151 } 4152 4153 static int ae5_headphone_gain_set(struct hda_codec *codec, long val); 4154 static int zxr_headphone_gain_set(struct hda_codec *codec, long val); 4155 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val); 4156 4157 static void ae5_mmio_select_out(struct hda_codec *codec) 4158 { 4159 struct ca0132_spec *spec = codec->spec; 4160 unsigned int i; 4161 4162 for (i = 0; i < AE5_CA0113_OUT_SET_COMMANDS; i++) 4163 ca0113_mmio_command_set(codec, 4164 ae5_ca0113_output_presets[spec->cur_out_type].group[i], 4165 ae5_ca0113_output_presets[spec->cur_out_type].target[i], 4166 ae5_ca0113_output_presets[spec->cur_out_type].vals[i]); 4167 } 4168 4169 /* 4170 * These are the commands needed to setup output on each of the different card 4171 * types. 4172 */ 4173 static void ca0132_alt_select_out_quirk_handler(struct hda_codec *codec) 4174 { 4175 struct ca0132_spec *spec = codec->spec; 4176 unsigned int tmp; 4177 4178 switch (spec->cur_out_type) { 4179 case SPEAKER_OUT: 4180 switch (ca0132_quirk(spec)) { 4181 case QUIRK_SBZ: 4182 ca0113_mmio_gpio_set(codec, 7, false); 4183 ca0113_mmio_gpio_set(codec, 4, true); 4184 ca0113_mmio_gpio_set(codec, 1, true); 4185 chipio_set_control_param(codec, 0x0d, 0x18); 4186 break; 4187 case QUIRK_ZXR: 4188 ca0113_mmio_gpio_set(codec, 2, true); 4189 ca0113_mmio_gpio_set(codec, 3, true); 4190 ca0113_mmio_gpio_set(codec, 5, false); 4191 zxr_headphone_gain_set(codec, 0); 4192 chipio_set_control_param(codec, 0x0d, 0x24); 4193 break; 4194 case QUIRK_R3DI: 4195 chipio_set_control_param(codec, 0x0d, 0x24); 4196 r3di_gpio_out_set(codec, R3DI_LINE_OUT); 4197 break; 4198 case QUIRK_R3D: 4199 chipio_set_control_param(codec, 0x0d, 0x24); 4200 ca0113_mmio_gpio_set(codec, 1, true); 4201 break; 4202 case QUIRK_AE5: 4203 ae5_mmio_select_out(codec); 4204 ae5_headphone_gain_set(codec, 2); 4205 tmp = FLOAT_ZERO; 4206 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 4207 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 4208 chipio_set_control_param(codec, 0x0d, 0xa4); 4209 chipio_write(codec, 0x18b03c, 0x00000012); 4210 break; 4211 default: 4212 break; 4213 } 4214 break; 4215 case HEADPHONE_OUT: 4216 switch (ca0132_quirk(spec)) { 4217 case QUIRK_SBZ: 4218 ca0113_mmio_gpio_set(codec, 7, true); 4219 ca0113_mmio_gpio_set(codec, 4, true); 4220 ca0113_mmio_gpio_set(codec, 1, false); 4221 chipio_set_control_param(codec, 0x0d, 0x12); 4222 break; 4223 case QUIRK_ZXR: 4224 ca0113_mmio_gpio_set(codec, 2, false); 4225 ca0113_mmio_gpio_set(codec, 3, false); 4226 ca0113_mmio_gpio_set(codec, 5, true); 4227 zxr_headphone_gain_set(codec, spec->zxr_gain_set); 4228 chipio_set_control_param(codec, 0x0d, 0x21); 4229 break; 4230 case QUIRK_R3DI: 4231 chipio_set_control_param(codec, 0x0d, 0x21); 4232 r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT); 4233 break; 4234 case QUIRK_R3D: 4235 chipio_set_control_param(codec, 0x0d, 0x21); 4236 ca0113_mmio_gpio_set(codec, 0x1, false); 4237 break; 4238 case QUIRK_AE5: 4239 ae5_mmio_select_out(codec); 4240 ae5_headphone_gain_set(codec, 4241 spec->ae5_headphone_gain_val); 4242 tmp = FLOAT_ONE; 4243 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 4244 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 4245 chipio_set_control_param(codec, 0x0d, 0xa1); 4246 chipio_write(codec, 0x18b03c, 0x00000012); 4247 break; 4248 default: 4249 break; 4250 } 4251 break; 4252 case SURROUND_OUT: 4253 switch (ca0132_quirk(spec)) { 4254 case QUIRK_SBZ: 4255 ca0113_mmio_gpio_set(codec, 7, false); 4256 ca0113_mmio_gpio_set(codec, 4, true); 4257 ca0113_mmio_gpio_set(codec, 1, true); 4258 chipio_set_control_param(codec, 0x0d, 0x18); 4259 break; 4260 case QUIRK_ZXR: 4261 ca0113_mmio_gpio_set(codec, 2, true); 4262 ca0113_mmio_gpio_set(codec, 3, true); 4263 ca0113_mmio_gpio_set(codec, 5, false); 4264 zxr_headphone_gain_set(codec, 0); 4265 chipio_set_control_param(codec, 0x0d, 0x24); 4266 break; 4267 case QUIRK_R3DI: 4268 chipio_set_control_param(codec, 0x0d, 0x24); 4269 r3di_gpio_out_set(codec, R3DI_LINE_OUT); 4270 break; 4271 case QUIRK_R3D: 4272 ca0113_mmio_gpio_set(codec, 1, true); 4273 chipio_set_control_param(codec, 0x0d, 0x24); 4274 break; 4275 case QUIRK_AE5: 4276 ae5_mmio_select_out(codec); 4277 ae5_headphone_gain_set(codec, 2); 4278 tmp = FLOAT_ZERO; 4279 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 4280 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 4281 chipio_set_control_param(codec, 0x0d, 0xa4); 4282 chipio_write(codec, 0x18b03c, 0x00000012); 4283 break; 4284 default: 4285 break; 4286 } 4287 break; 4288 } 4289 } 4290 4291 /* 4292 * This function behaves similarly to the ca0132_select_out funciton above, 4293 * except with a few differences. It adds the ability to select the current 4294 * output with an enumerated control "output source" if the auto detect 4295 * mute switch is set to off. If the auto detect mute switch is enabled, it 4296 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection. 4297 * It also adds the ability to auto-detect the front headphone port. The only 4298 * way to select surround is to disable auto detect, and set Surround with the 4299 * enumerated control. 4300 */ 4301 static int ca0132_alt_select_out(struct hda_codec *codec) 4302 { 4303 struct ca0132_spec *spec = codec->spec; 4304 unsigned int pin_ctl; 4305 int jack_present; 4306 int auto_jack; 4307 unsigned int i; 4308 unsigned int tmp; 4309 int err; 4310 /* Default Headphone is rear headphone */ 4311 hda_nid_t headphone_nid = spec->out_pins[1]; 4312 4313 codec_dbg(codec, "%s\n", __func__); 4314 4315 snd_hda_power_up_pm(codec); 4316 4317 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4318 4319 /* 4320 * If headphone rear or front is plugged in, set to headphone. 4321 * If neither is plugged in, set to rear line out. Only if 4322 * hp/speaker auto detect is enabled. 4323 */ 4324 if (auto_jack) { 4325 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) || 4326 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp); 4327 4328 if (jack_present) 4329 spec->cur_out_type = HEADPHONE_OUT; 4330 else 4331 spec->cur_out_type = SPEAKER_OUT; 4332 } else 4333 spec->cur_out_type = spec->out_enum_val; 4334 4335 /* Begin DSP output switch */ 4336 tmp = FLOAT_ONE; 4337 err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp); 4338 if (err < 0) 4339 goto exit; 4340 4341 ca0132_alt_select_out_quirk_handler(codec); 4342 4343 switch (spec->cur_out_type) { 4344 case SPEAKER_OUT: 4345 codec_dbg(codec, "%s speaker\n", __func__); 4346 4347 /* disable headphone node */ 4348 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4349 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4350 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4351 pin_ctl & ~PIN_HP); 4352 /* enable line-out node */ 4353 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4354 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4355 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4356 pin_ctl | PIN_OUT); 4357 /* Enable EAPD */ 4358 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4359 AC_VERB_SET_EAPD_BTLENABLE, 0x01); 4360 4361 /* If PlayEnhancement is enabled, set different source */ 4362 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4363 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE); 4364 else 4365 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT); 4366 break; 4367 case HEADPHONE_OUT: 4368 codec_dbg(codec, "%s hp\n", __func__); 4369 4370 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4371 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4372 4373 /* disable speaker*/ 4374 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4375 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4376 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4377 pin_ctl & ~PIN_HP); 4378 4379 /* enable headphone, either front or rear */ 4380 4381 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp)) 4382 headphone_nid = spec->out_pins[2]; 4383 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp)) 4384 headphone_nid = spec->out_pins[1]; 4385 4386 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0, 4387 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4388 snd_hda_set_pin_ctl(codec, headphone_nid, 4389 pin_ctl | PIN_HP); 4390 4391 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4392 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE); 4393 else 4394 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO); 4395 break; 4396 case SURROUND_OUT: 4397 codec_dbg(codec, "%s surround\n", __func__); 4398 4399 /* enable line out node */ 4400 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4401 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4402 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4403 pin_ctl | PIN_OUT); 4404 /* Disable headphone out */ 4405 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4406 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4407 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4408 pin_ctl & ~PIN_HP); 4409 /* Enable EAPD on line out */ 4410 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4411 AC_VERB_SET_EAPD_BTLENABLE, 0x01); 4412 /* enable center/lfe out node */ 4413 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0, 4414 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4415 snd_hda_set_pin_ctl(codec, spec->out_pins[2], 4416 pin_ctl | PIN_OUT); 4417 /* Now set rear surround node as out. */ 4418 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0, 4419 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4420 snd_hda_set_pin_ctl(codec, spec->out_pins[3], 4421 pin_ctl | PIN_OUT); 4422 4423 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT); 4424 break; 4425 } 4426 /* 4427 * Surround always sets it's scp command to req 0x04 to FLOAT_EIGHT. 4428 * With this set though, X_BASS cannot be enabled. So, if we have OutFX 4429 * enabled, we need to make sure X_BASS is off, otherwise everything 4430 * sounds all muffled. Running ca0132_effects_set with X_BASS as the 4431 * effect should sort this out. 4432 */ 4433 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4434 ca0132_effects_set(codec, X_BASS, 4435 spec->effects_switch[X_BASS - EFFECT_START_NID]); 4436 4437 /* run through the output dsp commands for the selected output. */ 4438 for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) { 4439 err = dspio_set_uint_param(codec, 4440 alt_out_presets[spec->cur_out_type].mids[i], 4441 alt_out_presets[spec->cur_out_type].reqs[i], 4442 alt_out_presets[spec->cur_out_type].vals[i]); 4443 4444 if (err < 0) 4445 goto exit; 4446 } 4447 4448 exit: 4449 snd_hda_power_down_pm(codec); 4450 4451 return err < 0 ? err : 0; 4452 } 4453 4454 static void ca0132_unsol_hp_delayed(struct work_struct *work) 4455 { 4456 struct ca0132_spec *spec = container_of( 4457 to_delayed_work(work), struct ca0132_spec, unsol_hp_work); 4458 struct hda_jack_tbl *jack; 4459 4460 if (ca0132_use_alt_functions(spec)) 4461 ca0132_alt_select_out(spec->codec); 4462 else 4463 ca0132_select_out(spec->codec); 4464 4465 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp); 4466 if (jack) { 4467 jack->block_report = 0; 4468 snd_hda_jack_report_sync(spec->codec); 4469 } 4470 } 4471 4472 static void ca0132_set_dmic(struct hda_codec *codec, int enable); 4473 static int ca0132_mic_boost_set(struct hda_codec *codec, long val); 4474 static void resume_mic1(struct hda_codec *codec, unsigned int oldval); 4475 static int stop_mic1(struct hda_codec *codec); 4476 static int ca0132_cvoice_switch_set(struct hda_codec *codec); 4477 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val); 4478 4479 /* 4480 * Select the active VIP source 4481 */ 4482 static int ca0132_set_vipsource(struct hda_codec *codec, int val) 4483 { 4484 struct ca0132_spec *spec = codec->spec; 4485 unsigned int tmp; 4486 4487 if (spec->dsp_state != DSP_DOWNLOADED) 4488 return 0; 4489 4490 /* if CrystalVoice if off, vipsource should be 0 */ 4491 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4492 (val == 0)) { 4493 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4494 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4495 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4496 if (spec->cur_mic_type == DIGITAL_MIC) 4497 tmp = FLOAT_TWO; 4498 else 4499 tmp = FLOAT_ONE; 4500 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4501 tmp = FLOAT_ZERO; 4502 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4503 } else { 4504 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4505 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4506 if (spec->cur_mic_type == DIGITAL_MIC) 4507 tmp = FLOAT_TWO; 4508 else 4509 tmp = FLOAT_ONE; 4510 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4511 tmp = FLOAT_ONE; 4512 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4513 msleep(20); 4514 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4515 } 4516 4517 return 1; 4518 } 4519 4520 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val) 4521 { 4522 struct ca0132_spec *spec = codec->spec; 4523 unsigned int tmp; 4524 4525 if (spec->dsp_state != DSP_DOWNLOADED) 4526 return 0; 4527 4528 codec_dbg(codec, "%s\n", __func__); 4529 4530 chipio_set_stream_control(codec, 0x03, 0); 4531 chipio_set_stream_control(codec, 0x04, 0); 4532 4533 /* if CrystalVoice is off, vipsource should be 0 */ 4534 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4535 (val == 0) || spec->in_enum_val == REAR_LINE_IN) { 4536 codec_dbg(codec, "%s: off.", __func__); 4537 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4538 4539 tmp = FLOAT_ZERO; 4540 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4541 4542 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4543 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4544 if (ca0132_quirk(spec) == QUIRK_R3DI) 4545 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4546 4547 4548 if (spec->in_enum_val == REAR_LINE_IN) 4549 tmp = FLOAT_ZERO; 4550 else { 4551 if (ca0132_quirk(spec) == QUIRK_SBZ) 4552 tmp = FLOAT_THREE; 4553 else 4554 tmp = FLOAT_ONE; 4555 } 4556 4557 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4558 4559 } else { 4560 codec_dbg(codec, "%s: on.", __func__); 4561 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4562 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4563 if (ca0132_quirk(spec) == QUIRK_R3DI) 4564 chipio_set_conn_rate(codec, 0x0F, SR_16_000); 4565 4566 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID]) 4567 tmp = FLOAT_TWO; 4568 else 4569 tmp = FLOAT_ONE; 4570 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4571 4572 tmp = FLOAT_ONE; 4573 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4574 4575 msleep(20); 4576 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4577 } 4578 4579 chipio_set_stream_control(codec, 0x03, 1); 4580 chipio_set_stream_control(codec, 0x04, 1); 4581 4582 return 1; 4583 } 4584 4585 /* 4586 * Select the active microphone. 4587 * If autodetect is enabled, mic will be selected based on jack detection. 4588 * If jack inserted, ext.mic will be selected, else built-in mic 4589 * If autodetect is disabled, mic will be selected based on selection. 4590 */ 4591 static int ca0132_select_mic(struct hda_codec *codec) 4592 { 4593 struct ca0132_spec *spec = codec->spec; 4594 int jack_present; 4595 int auto_jack; 4596 4597 codec_dbg(codec, "ca0132_select_mic\n"); 4598 4599 snd_hda_power_up_pm(codec); 4600 4601 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 4602 4603 if (auto_jack) 4604 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1); 4605 else 4606 jack_present = 4607 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID]; 4608 4609 if (jack_present) 4610 spec->cur_mic_type = LINE_MIC_IN; 4611 else 4612 spec->cur_mic_type = DIGITAL_MIC; 4613 4614 if (spec->cur_mic_type == DIGITAL_MIC) { 4615 /* enable digital Mic */ 4616 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000); 4617 ca0132_set_dmic(codec, 1); 4618 ca0132_mic_boost_set(codec, 0); 4619 /* set voice focus */ 4620 ca0132_effects_set(codec, VOICE_FOCUS, 4621 spec->effects_switch 4622 [VOICE_FOCUS - EFFECT_START_NID]); 4623 } else { 4624 /* disable digital Mic */ 4625 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000); 4626 ca0132_set_dmic(codec, 0); 4627 ca0132_mic_boost_set(codec, spec->cur_mic_boost); 4628 /* disable voice focus */ 4629 ca0132_effects_set(codec, VOICE_FOCUS, 0); 4630 } 4631 4632 snd_hda_power_down_pm(codec); 4633 4634 return 0; 4635 } 4636 4637 /* 4638 * Select the active input. 4639 * Mic detection isn't used, because it's kind of pointless on the SBZ. 4640 * The front mic has no jack-detection, so the only way to switch to it 4641 * is to do it manually in alsamixer. 4642 */ 4643 static int ca0132_alt_select_in(struct hda_codec *codec) 4644 { 4645 struct ca0132_spec *spec = codec->spec; 4646 unsigned int tmp; 4647 4648 codec_dbg(codec, "%s\n", __func__); 4649 4650 snd_hda_power_up_pm(codec); 4651 4652 chipio_set_stream_control(codec, 0x03, 0); 4653 chipio_set_stream_control(codec, 0x04, 0); 4654 4655 spec->cur_mic_type = spec->in_enum_val; 4656 4657 switch (spec->cur_mic_type) { 4658 case REAR_MIC: 4659 switch (ca0132_quirk(spec)) { 4660 case QUIRK_SBZ: 4661 case QUIRK_R3D: 4662 ca0113_mmio_gpio_set(codec, 0, false); 4663 tmp = FLOAT_THREE; 4664 break; 4665 case QUIRK_ZXR: 4666 tmp = FLOAT_THREE; 4667 break; 4668 case QUIRK_R3DI: 4669 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 4670 tmp = FLOAT_ONE; 4671 break; 4672 case QUIRK_AE5: 4673 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x00); 4674 tmp = FLOAT_THREE; 4675 break; 4676 default: 4677 tmp = FLOAT_ONE; 4678 break; 4679 } 4680 4681 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4682 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4683 if (ca0132_quirk(spec) == QUIRK_R3DI) 4684 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4685 4686 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4687 4688 chipio_set_stream_control(codec, 0x03, 1); 4689 chipio_set_stream_control(codec, 0x04, 1); 4690 switch (ca0132_quirk(spec)) { 4691 case QUIRK_SBZ: 4692 chipio_write(codec, 0x18B098, 0x0000000C); 4693 chipio_write(codec, 0x18B09C, 0x0000000C); 4694 break; 4695 case QUIRK_ZXR: 4696 chipio_write(codec, 0x18B098, 0x0000000C); 4697 chipio_write(codec, 0x18B09C, 0x000000CC); 4698 break; 4699 case QUIRK_AE5: 4700 chipio_write(codec, 0x18B098, 0x0000000C); 4701 chipio_write(codec, 0x18B09C, 0x0000004C); 4702 break; 4703 default: 4704 break; 4705 } 4706 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 4707 break; 4708 case REAR_LINE_IN: 4709 ca0132_mic_boost_set(codec, 0); 4710 switch (ca0132_quirk(spec)) { 4711 case QUIRK_SBZ: 4712 case QUIRK_R3D: 4713 ca0113_mmio_gpio_set(codec, 0, false); 4714 break; 4715 case QUIRK_R3DI: 4716 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 4717 break; 4718 case QUIRK_AE5: 4719 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x00); 4720 break; 4721 default: 4722 break; 4723 } 4724 4725 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4726 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4727 if (ca0132_quirk(spec) == QUIRK_R3DI) 4728 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4729 4730 tmp = FLOAT_ZERO; 4731 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4732 4733 switch (ca0132_quirk(spec)) { 4734 case QUIRK_SBZ: 4735 case QUIRK_AE5: 4736 chipio_write(codec, 0x18B098, 0x00000000); 4737 chipio_write(codec, 0x18B09C, 0x00000000); 4738 break; 4739 default: 4740 break; 4741 } 4742 chipio_set_stream_control(codec, 0x03, 1); 4743 chipio_set_stream_control(codec, 0x04, 1); 4744 break; 4745 case FRONT_MIC: 4746 switch (ca0132_quirk(spec)) { 4747 case QUIRK_SBZ: 4748 case QUIRK_R3D: 4749 ca0113_mmio_gpio_set(codec, 0, true); 4750 ca0113_mmio_gpio_set(codec, 5, false); 4751 tmp = FLOAT_THREE; 4752 break; 4753 case QUIRK_R3DI: 4754 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC); 4755 tmp = FLOAT_ONE; 4756 break; 4757 case QUIRK_AE5: 4758 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x3f); 4759 tmp = FLOAT_THREE; 4760 break; 4761 default: 4762 tmp = FLOAT_ONE; 4763 break; 4764 } 4765 4766 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4767 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4768 if (ca0132_quirk(spec) == QUIRK_R3DI) 4769 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4770 4771 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4772 4773 chipio_set_stream_control(codec, 0x03, 1); 4774 chipio_set_stream_control(codec, 0x04, 1); 4775 4776 switch (ca0132_quirk(spec)) { 4777 case QUIRK_SBZ: 4778 chipio_write(codec, 0x18B098, 0x0000000C); 4779 chipio_write(codec, 0x18B09C, 0x000000CC); 4780 break; 4781 case QUIRK_AE5: 4782 chipio_write(codec, 0x18B098, 0x0000000C); 4783 chipio_write(codec, 0x18B09C, 0x0000004C); 4784 break; 4785 default: 4786 break; 4787 } 4788 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 4789 break; 4790 } 4791 ca0132_cvoice_switch_set(codec); 4792 4793 snd_hda_power_down_pm(codec); 4794 return 0; 4795 } 4796 4797 /* 4798 * Check if VNODE settings take effect immediately. 4799 */ 4800 static bool ca0132_is_vnode_effective(struct hda_codec *codec, 4801 hda_nid_t vnid, 4802 hda_nid_t *shared_nid) 4803 { 4804 struct ca0132_spec *spec = codec->spec; 4805 hda_nid_t nid; 4806 4807 switch (vnid) { 4808 case VNID_SPK: 4809 nid = spec->shared_out_nid; 4810 break; 4811 case VNID_MIC: 4812 nid = spec->shared_mic_nid; 4813 break; 4814 default: 4815 return false; 4816 } 4817 4818 if (shared_nid) 4819 *shared_nid = nid; 4820 4821 return true; 4822 } 4823 4824 /* 4825 * The following functions are control change helpers. 4826 * They return 0 if no changed. Return 1 if changed. 4827 */ 4828 static int ca0132_voicefx_set(struct hda_codec *codec, int enable) 4829 { 4830 struct ca0132_spec *spec = codec->spec; 4831 unsigned int tmp; 4832 4833 /* based on CrystalVoice state to enable VoiceFX. */ 4834 if (enable) { 4835 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ? 4836 FLOAT_ONE : FLOAT_ZERO; 4837 } else { 4838 tmp = FLOAT_ZERO; 4839 } 4840 4841 dspio_set_uint_param(codec, ca0132_voicefx.mid, 4842 ca0132_voicefx.reqs[0], tmp); 4843 4844 return 1; 4845 } 4846 4847 /* 4848 * Set the effects parameters 4849 */ 4850 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val) 4851 { 4852 struct ca0132_spec *spec = codec->spec; 4853 unsigned int on, tmp; 4854 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 4855 int err = 0; 4856 int idx = nid - EFFECT_START_NID; 4857 4858 if ((idx < 0) || (idx >= num_fx)) 4859 return 0; /* no changed */ 4860 4861 /* for out effect, qualify with PE */ 4862 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) { 4863 /* if PE if off, turn off out effects. */ 4864 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4865 val = 0; 4866 if (spec->cur_out_type == SURROUND_OUT && nid == X_BASS) 4867 val = 0; 4868 } 4869 4870 /* for in effect, qualify with CrystalVoice */ 4871 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) { 4872 /* if CrystalVoice if off, turn off in effects. */ 4873 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 4874 val = 0; 4875 4876 /* Voice Focus applies to 2-ch Mic, Digital Mic */ 4877 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC)) 4878 val = 0; 4879 4880 /* If Voice Focus on SBZ, set to two channel. */ 4881 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec) 4882 && (spec->cur_mic_type != REAR_LINE_IN)) { 4883 if (spec->effects_switch[CRYSTAL_VOICE - 4884 EFFECT_START_NID]) { 4885 4886 if (spec->effects_switch[VOICE_FOCUS - 4887 EFFECT_START_NID]) { 4888 tmp = FLOAT_TWO; 4889 val = 1; 4890 } else 4891 tmp = FLOAT_ONE; 4892 4893 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4894 } 4895 } 4896 /* 4897 * For SBZ noise reduction, there's an extra command 4898 * to module ID 0x47. No clue why. 4899 */ 4900 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec) 4901 && (spec->cur_mic_type != REAR_LINE_IN)) { 4902 if (spec->effects_switch[CRYSTAL_VOICE - 4903 EFFECT_START_NID]) { 4904 if (spec->effects_switch[NOISE_REDUCTION - 4905 EFFECT_START_NID]) 4906 tmp = FLOAT_ONE; 4907 else 4908 tmp = FLOAT_ZERO; 4909 } else 4910 tmp = FLOAT_ZERO; 4911 4912 dspio_set_uint_param(codec, 0x47, 0x00, tmp); 4913 } 4914 4915 /* If rear line in disable effects. */ 4916 if (ca0132_use_alt_functions(spec) && 4917 spec->in_enum_val == REAR_LINE_IN) 4918 val = 0; 4919 } 4920 4921 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n", 4922 nid, val); 4923 4924 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE; 4925 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid, 4926 ca0132_effects[idx].reqs[0], on); 4927 4928 if (err < 0) 4929 return 0; /* no changed */ 4930 4931 return 1; 4932 } 4933 4934 /* 4935 * Turn on/off Playback Enhancements 4936 */ 4937 static int ca0132_pe_switch_set(struct hda_codec *codec) 4938 { 4939 struct ca0132_spec *spec = codec->spec; 4940 hda_nid_t nid; 4941 int i, ret = 0; 4942 4943 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n", 4944 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]); 4945 4946 if (ca0132_use_alt_functions(spec)) 4947 ca0132_alt_select_out(codec); 4948 4949 i = OUT_EFFECT_START_NID - EFFECT_START_NID; 4950 nid = OUT_EFFECT_START_NID; 4951 /* PE affects all out effects */ 4952 for (; nid < OUT_EFFECT_END_NID; nid++, i++) 4953 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 4954 4955 return ret; 4956 } 4957 4958 /* Check if Mic1 is streaming, if so, stop streaming */ 4959 static int stop_mic1(struct hda_codec *codec) 4960 { 4961 struct ca0132_spec *spec = codec->spec; 4962 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0, 4963 AC_VERB_GET_CONV, 0); 4964 if (oldval != 0) 4965 snd_hda_codec_write(codec, spec->adcs[0], 0, 4966 AC_VERB_SET_CHANNEL_STREAMID, 4967 0); 4968 return oldval; 4969 } 4970 4971 /* Resume Mic1 streaming if it was stopped. */ 4972 static void resume_mic1(struct hda_codec *codec, unsigned int oldval) 4973 { 4974 struct ca0132_spec *spec = codec->spec; 4975 /* Restore the previous stream and channel */ 4976 if (oldval != 0) 4977 snd_hda_codec_write(codec, spec->adcs[0], 0, 4978 AC_VERB_SET_CHANNEL_STREAMID, 4979 oldval); 4980 } 4981 4982 /* 4983 * Turn on/off CrystalVoice 4984 */ 4985 static int ca0132_cvoice_switch_set(struct hda_codec *codec) 4986 { 4987 struct ca0132_spec *spec = codec->spec; 4988 hda_nid_t nid; 4989 int i, ret = 0; 4990 unsigned int oldval; 4991 4992 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n", 4993 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]); 4994 4995 i = IN_EFFECT_START_NID - EFFECT_START_NID; 4996 nid = IN_EFFECT_START_NID; 4997 /* CrystalVoice affects all in effects */ 4998 for (; nid < IN_EFFECT_END_NID; nid++, i++) 4999 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 5000 5001 /* including VoiceFX */ 5002 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0)); 5003 5004 /* set correct vipsource */ 5005 oldval = stop_mic1(codec); 5006 if (ca0132_use_alt_functions(spec)) 5007 ret |= ca0132_alt_set_vipsource(codec, 1); 5008 else 5009 ret |= ca0132_set_vipsource(codec, 1); 5010 resume_mic1(codec, oldval); 5011 return ret; 5012 } 5013 5014 static int ca0132_mic_boost_set(struct hda_codec *codec, long val) 5015 { 5016 struct ca0132_spec *spec = codec->spec; 5017 int ret = 0; 5018 5019 if (val) /* on */ 5020 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5021 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3); 5022 else /* off */ 5023 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5024 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0); 5025 5026 return ret; 5027 } 5028 5029 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val) 5030 { 5031 struct ca0132_spec *spec = codec->spec; 5032 int ret = 0; 5033 5034 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5035 HDA_INPUT, 0, HDA_AMP_VOLMASK, val); 5036 return ret; 5037 } 5038 5039 static int ae5_headphone_gain_set(struct hda_codec *codec, long val) 5040 { 5041 unsigned int i; 5042 5043 for (i = 0; i < 4; i++) 5044 ca0113_mmio_command_set(codec, 0x48, 0x11 + i, 5045 ae5_headphone_gain_presets[val].vals[i]); 5046 return 0; 5047 } 5048 5049 /* 5050 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone 5051 * amplifier to handle a 600 ohm load. 5052 */ 5053 static int zxr_headphone_gain_set(struct hda_codec *codec, long val) 5054 { 5055 ca0113_mmio_gpio_set(codec, 1, val); 5056 5057 return 0; 5058 } 5059 5060 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol, 5061 struct snd_ctl_elem_value *ucontrol) 5062 { 5063 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5064 hda_nid_t nid = get_amp_nid(kcontrol); 5065 hda_nid_t shared_nid = 0; 5066 bool effective; 5067 int ret = 0; 5068 struct ca0132_spec *spec = codec->spec; 5069 int auto_jack; 5070 5071 if (nid == VNID_HP_SEL) { 5072 auto_jack = 5073 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 5074 if (!auto_jack) { 5075 if (ca0132_use_alt_functions(spec)) 5076 ca0132_alt_select_out(codec); 5077 else 5078 ca0132_select_out(codec); 5079 } 5080 return 1; 5081 } 5082 5083 if (nid == VNID_AMIC1_SEL) { 5084 auto_jack = 5085 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 5086 if (!auto_jack) 5087 ca0132_select_mic(codec); 5088 return 1; 5089 } 5090 5091 if (nid == VNID_HP_ASEL) { 5092 if (ca0132_use_alt_functions(spec)) 5093 ca0132_alt_select_out(codec); 5094 else 5095 ca0132_select_out(codec); 5096 return 1; 5097 } 5098 5099 if (nid == VNID_AMIC1_ASEL) { 5100 ca0132_select_mic(codec); 5101 return 1; 5102 } 5103 5104 /* if effective conditions, then update hw immediately. */ 5105 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 5106 if (effective) { 5107 int dir = get_amp_direction(kcontrol); 5108 int ch = get_amp_channels(kcontrol); 5109 unsigned long pval; 5110 5111 mutex_lock(&codec->control_mutex); 5112 pval = kcontrol->private_value; 5113 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 5114 0, dir); 5115 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol); 5116 kcontrol->private_value = pval; 5117 mutex_unlock(&codec->control_mutex); 5118 } 5119 5120 return ret; 5121 } 5122 /* End of control change helpers. */ 5123 /* 5124 * Below I've added controls to mess with the effect levels, I've only enabled 5125 * them on the Sound Blaster Z, but they would probably also work on the 5126 * Chromebook. I figured they were probably tuned specifically for it, and left 5127 * out for a reason. 5128 */ 5129 5130 /* Sets DSP effect level from the sliders above the controls */ 5131 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid, 5132 const unsigned int *lookup, int idx) 5133 { 5134 int i = 0; 5135 unsigned int y; 5136 /* 5137 * For X_BASS, req 2 is actually crossover freq instead of 5138 * effect level 5139 */ 5140 if (nid == X_BASS) 5141 y = 2; 5142 else 5143 y = 1; 5144 5145 snd_hda_power_up(codec); 5146 if (nid == XBASS_XOVER) { 5147 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5148 if (ca0132_effects[i].nid == X_BASS) 5149 break; 5150 5151 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5152 ca0132_effects[i].reqs[1], 5153 &(lookup[idx - 1]), sizeof(unsigned int)); 5154 } else { 5155 /* Find the actual effect structure */ 5156 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5157 if (nid == ca0132_effects[i].nid) 5158 break; 5159 5160 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5161 ca0132_effects[i].reqs[y], 5162 &(lookup[idx]), sizeof(unsigned int)); 5163 } 5164 5165 snd_hda_power_down(codec); 5166 5167 return 0; 5168 } 5169 5170 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol, 5171 struct snd_ctl_elem_value *ucontrol) 5172 { 5173 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5174 struct ca0132_spec *spec = codec->spec; 5175 long *valp = ucontrol->value.integer.value; 5176 5177 *valp = spec->xbass_xover_freq; 5178 return 0; 5179 } 5180 5181 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol, 5182 struct snd_ctl_elem_value *ucontrol) 5183 { 5184 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5185 struct ca0132_spec *spec = codec->spec; 5186 hda_nid_t nid = get_amp_nid(kcontrol); 5187 long *valp = ucontrol->value.integer.value; 5188 int idx = nid - OUT_EFFECT_START_NID; 5189 5190 *valp = spec->fx_ctl_val[idx]; 5191 return 0; 5192 } 5193 5194 /* 5195 * The X-bass crossover starts at 10hz, so the min is 1. The 5196 * frequency is set in multiples of 10. 5197 */ 5198 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol, 5199 struct snd_ctl_elem_info *uinfo) 5200 { 5201 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5202 uinfo->count = 1; 5203 uinfo->value.integer.min = 1; 5204 uinfo->value.integer.max = 100; 5205 uinfo->value.integer.step = 1; 5206 5207 return 0; 5208 } 5209 5210 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol, 5211 struct snd_ctl_elem_info *uinfo) 5212 { 5213 int chs = get_amp_channels(kcontrol); 5214 5215 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5216 uinfo->count = chs == 3 ? 2 : 1; 5217 uinfo->value.integer.min = 0; 5218 uinfo->value.integer.max = 100; 5219 uinfo->value.integer.step = 1; 5220 5221 return 0; 5222 } 5223 5224 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol, 5225 struct snd_ctl_elem_value *ucontrol) 5226 { 5227 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5228 struct ca0132_spec *spec = codec->spec; 5229 hda_nid_t nid = get_amp_nid(kcontrol); 5230 long *valp = ucontrol->value.integer.value; 5231 int idx; 5232 5233 /* any change? */ 5234 if (spec->xbass_xover_freq == *valp) 5235 return 0; 5236 5237 spec->xbass_xover_freq = *valp; 5238 5239 idx = *valp; 5240 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx); 5241 5242 return 0; 5243 } 5244 5245 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol, 5246 struct snd_ctl_elem_value *ucontrol) 5247 { 5248 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5249 struct ca0132_spec *spec = codec->spec; 5250 hda_nid_t nid = get_amp_nid(kcontrol); 5251 long *valp = ucontrol->value.integer.value; 5252 int idx; 5253 5254 idx = nid - EFFECT_START_NID; 5255 /* any change? */ 5256 if (spec->fx_ctl_val[idx] == *valp) 5257 return 0; 5258 5259 spec->fx_ctl_val[idx] = *valp; 5260 5261 idx = *valp; 5262 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx); 5263 5264 return 0; 5265 } 5266 5267 5268 /* 5269 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original 5270 * only has off or full 30 dB, and didn't like making a volume slider that has 5271 * traditional 0-100 in alsamixer that goes in big steps. I like enum better. 5272 */ 5273 #define MIC_BOOST_NUM_OF_STEPS 4 5274 #define MIC_BOOST_ENUM_MAX_STRLEN 10 5275 5276 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol, 5277 struct snd_ctl_elem_info *uinfo) 5278 { 5279 char *sfx = "dB"; 5280 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5281 5282 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5283 uinfo->count = 1; 5284 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS; 5285 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS) 5286 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1; 5287 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx); 5288 strcpy(uinfo->value.enumerated.name, namestr); 5289 return 0; 5290 } 5291 5292 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol, 5293 struct snd_ctl_elem_value *ucontrol) 5294 { 5295 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5296 struct ca0132_spec *spec = codec->spec; 5297 5298 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val; 5299 return 0; 5300 } 5301 5302 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol, 5303 struct snd_ctl_elem_value *ucontrol) 5304 { 5305 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5306 struct ca0132_spec *spec = codec->spec; 5307 int sel = ucontrol->value.enumerated.item[0]; 5308 unsigned int items = MIC_BOOST_NUM_OF_STEPS; 5309 5310 if (sel >= items) 5311 return 0; 5312 5313 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n", 5314 sel); 5315 5316 spec->mic_boost_enum_val = sel; 5317 5318 if (spec->in_enum_val != REAR_LINE_IN) 5319 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5320 5321 return 1; 5322 } 5323 5324 /* 5325 * Sound BlasterX AE-5 Headphone Gain Controls. 5326 */ 5327 #define AE5_HEADPHONE_GAIN_MAX 3 5328 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol, 5329 struct snd_ctl_elem_info *uinfo) 5330 { 5331 char *sfx = " Ohms)"; 5332 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5333 5334 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5335 uinfo->count = 1; 5336 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX; 5337 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX) 5338 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1; 5339 sprintf(namestr, "%s %s", 5340 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name, 5341 sfx); 5342 strcpy(uinfo->value.enumerated.name, namestr); 5343 return 0; 5344 } 5345 5346 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol, 5347 struct snd_ctl_elem_value *ucontrol) 5348 { 5349 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5350 struct ca0132_spec *spec = codec->spec; 5351 5352 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val; 5353 return 0; 5354 } 5355 5356 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol, 5357 struct snd_ctl_elem_value *ucontrol) 5358 { 5359 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5360 struct ca0132_spec *spec = codec->spec; 5361 int sel = ucontrol->value.enumerated.item[0]; 5362 unsigned int items = AE5_HEADPHONE_GAIN_MAX; 5363 5364 if (sel >= items) 5365 return 0; 5366 5367 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n", 5368 sel); 5369 5370 spec->ae5_headphone_gain_val = sel; 5371 5372 if (spec->out_enum_val == HEADPHONE_OUT) 5373 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val); 5374 5375 return 1; 5376 } 5377 5378 /* 5379 * Sound BlasterX AE-5 sound filter enumerated control. 5380 */ 5381 #define AE5_SOUND_FILTER_MAX 3 5382 5383 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol, 5384 struct snd_ctl_elem_info *uinfo) 5385 { 5386 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5387 5388 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5389 uinfo->count = 1; 5390 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX; 5391 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX) 5392 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1; 5393 sprintf(namestr, "%s", 5394 ae5_filter_presets[uinfo->value.enumerated.item].name); 5395 strcpy(uinfo->value.enumerated.name, namestr); 5396 return 0; 5397 } 5398 5399 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol, 5400 struct snd_ctl_elem_value *ucontrol) 5401 { 5402 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5403 struct ca0132_spec *spec = codec->spec; 5404 5405 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val; 5406 return 0; 5407 } 5408 5409 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol, 5410 struct snd_ctl_elem_value *ucontrol) 5411 { 5412 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5413 struct ca0132_spec *spec = codec->spec; 5414 int sel = ucontrol->value.enumerated.item[0]; 5415 unsigned int items = AE5_SOUND_FILTER_MAX; 5416 5417 if (sel >= items) 5418 return 0; 5419 5420 codec_dbg(codec, "ae5_sound_filter: %s\n", 5421 ae5_filter_presets[sel].name); 5422 5423 spec->ae5_filter_val = sel; 5424 5425 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 5426 ae5_filter_presets[sel].val); 5427 5428 return 1; 5429 } 5430 5431 /* 5432 * Input Select Control for alternative ca0132 codecs. This exists because 5433 * front microphone has no auto-detect, and we need a way to set the rear 5434 * as line-in 5435 */ 5436 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol, 5437 struct snd_ctl_elem_info *uinfo) 5438 { 5439 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5440 uinfo->count = 1; 5441 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS; 5442 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS) 5443 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1; 5444 strcpy(uinfo->value.enumerated.name, 5445 in_src_str[uinfo->value.enumerated.item]); 5446 return 0; 5447 } 5448 5449 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol, 5450 struct snd_ctl_elem_value *ucontrol) 5451 { 5452 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5453 struct ca0132_spec *spec = codec->spec; 5454 5455 ucontrol->value.enumerated.item[0] = spec->in_enum_val; 5456 return 0; 5457 } 5458 5459 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol, 5460 struct snd_ctl_elem_value *ucontrol) 5461 { 5462 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5463 struct ca0132_spec *spec = codec->spec; 5464 int sel = ucontrol->value.enumerated.item[0]; 5465 unsigned int items = IN_SRC_NUM_OF_INPUTS; 5466 5467 if (sel >= items) 5468 return 0; 5469 5470 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n", 5471 sel, in_src_str[sel]); 5472 5473 spec->in_enum_val = sel; 5474 5475 ca0132_alt_select_in(codec); 5476 5477 return 1; 5478 } 5479 5480 /* Sound Blaster Z Output Select Control */ 5481 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol, 5482 struct snd_ctl_elem_info *uinfo) 5483 { 5484 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5485 uinfo->count = 1; 5486 uinfo->value.enumerated.items = NUM_OF_OUTPUTS; 5487 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS) 5488 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1; 5489 strcpy(uinfo->value.enumerated.name, 5490 alt_out_presets[uinfo->value.enumerated.item].name); 5491 return 0; 5492 } 5493 5494 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol, 5495 struct snd_ctl_elem_value *ucontrol) 5496 { 5497 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5498 struct ca0132_spec *spec = codec->spec; 5499 5500 ucontrol->value.enumerated.item[0] = spec->out_enum_val; 5501 return 0; 5502 } 5503 5504 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol, 5505 struct snd_ctl_elem_value *ucontrol) 5506 { 5507 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5508 struct ca0132_spec *spec = codec->spec; 5509 int sel = ucontrol->value.enumerated.item[0]; 5510 unsigned int items = NUM_OF_OUTPUTS; 5511 unsigned int auto_jack; 5512 5513 if (sel >= items) 5514 return 0; 5515 5516 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n", 5517 sel, alt_out_presets[sel].name); 5518 5519 spec->out_enum_val = sel; 5520 5521 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 5522 5523 if (!auto_jack) 5524 ca0132_alt_select_out(codec); 5525 5526 return 1; 5527 } 5528 5529 /* 5530 * Smart Volume output setting control. Three different settings, Normal, 5531 * which takes the value from the smart volume slider. The two others, loud 5532 * and night, disregard the slider value and have uneditable values. 5533 */ 5534 #define NUM_OF_SVM_SETTINGS 3 5535 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" }; 5536 5537 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol, 5538 struct snd_ctl_elem_info *uinfo) 5539 { 5540 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5541 uinfo->count = 1; 5542 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS; 5543 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS) 5544 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1; 5545 strcpy(uinfo->value.enumerated.name, 5546 out_svm_set_enum_str[uinfo->value.enumerated.item]); 5547 return 0; 5548 } 5549 5550 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol, 5551 struct snd_ctl_elem_value *ucontrol) 5552 { 5553 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5554 struct ca0132_spec *spec = codec->spec; 5555 5556 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting; 5557 return 0; 5558 } 5559 5560 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol, 5561 struct snd_ctl_elem_value *ucontrol) 5562 { 5563 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5564 struct ca0132_spec *spec = codec->spec; 5565 int sel = ucontrol->value.enumerated.item[0]; 5566 unsigned int items = NUM_OF_SVM_SETTINGS; 5567 unsigned int idx = SMART_VOLUME - EFFECT_START_NID; 5568 unsigned int tmp; 5569 5570 if (sel >= items) 5571 return 0; 5572 5573 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n", 5574 sel, out_svm_set_enum_str[sel]); 5575 5576 spec->smart_volume_setting = sel; 5577 5578 switch (sel) { 5579 case 0: 5580 tmp = FLOAT_ZERO; 5581 break; 5582 case 1: 5583 tmp = FLOAT_ONE; 5584 break; 5585 case 2: 5586 tmp = FLOAT_TWO; 5587 break; 5588 default: 5589 tmp = FLOAT_ZERO; 5590 break; 5591 } 5592 /* Req 2 is the Smart Volume Setting req. */ 5593 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 5594 ca0132_effects[idx].reqs[2], tmp); 5595 return 1; 5596 } 5597 5598 /* Sound Blaster Z EQ preset controls */ 5599 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol, 5600 struct snd_ctl_elem_info *uinfo) 5601 { 5602 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 5603 5604 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5605 uinfo->count = 1; 5606 uinfo->value.enumerated.items = items; 5607 if (uinfo->value.enumerated.item >= items) 5608 uinfo->value.enumerated.item = items - 1; 5609 strcpy(uinfo->value.enumerated.name, 5610 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name); 5611 return 0; 5612 } 5613 5614 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol, 5615 struct snd_ctl_elem_value *ucontrol) 5616 { 5617 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5618 struct ca0132_spec *spec = codec->spec; 5619 5620 ucontrol->value.enumerated.item[0] = spec->eq_preset_val; 5621 return 0; 5622 } 5623 5624 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol, 5625 struct snd_ctl_elem_value *ucontrol) 5626 { 5627 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5628 struct ca0132_spec *spec = codec->spec; 5629 int i, err = 0; 5630 int sel = ucontrol->value.enumerated.item[0]; 5631 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 5632 5633 if (sel >= items) 5634 return 0; 5635 5636 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel, 5637 ca0132_alt_eq_presets[sel].name); 5638 /* 5639 * Idx 0 is default. 5640 * Default needs to qualify with CrystalVoice state. 5641 */ 5642 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) { 5643 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid, 5644 ca0132_alt_eq_enum.reqs[i], 5645 ca0132_alt_eq_presets[sel].vals[i]); 5646 if (err < 0) 5647 break; 5648 } 5649 5650 if (err >= 0) 5651 spec->eq_preset_val = sel; 5652 5653 return 1; 5654 } 5655 5656 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol, 5657 struct snd_ctl_elem_info *uinfo) 5658 { 5659 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets); 5660 5661 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5662 uinfo->count = 1; 5663 uinfo->value.enumerated.items = items; 5664 if (uinfo->value.enumerated.item >= items) 5665 uinfo->value.enumerated.item = items - 1; 5666 strcpy(uinfo->value.enumerated.name, 5667 ca0132_voicefx_presets[uinfo->value.enumerated.item].name); 5668 return 0; 5669 } 5670 5671 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol, 5672 struct snd_ctl_elem_value *ucontrol) 5673 { 5674 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5675 struct ca0132_spec *spec = codec->spec; 5676 5677 ucontrol->value.enumerated.item[0] = spec->voicefx_val; 5678 return 0; 5679 } 5680 5681 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol, 5682 struct snd_ctl_elem_value *ucontrol) 5683 { 5684 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5685 struct ca0132_spec *spec = codec->spec; 5686 int i, err = 0; 5687 int sel = ucontrol->value.enumerated.item[0]; 5688 5689 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets)) 5690 return 0; 5691 5692 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n", 5693 sel, ca0132_voicefx_presets[sel].name); 5694 5695 /* 5696 * Idx 0 is default. 5697 * Default needs to qualify with CrystalVoice state. 5698 */ 5699 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) { 5700 err = dspio_set_uint_param(codec, ca0132_voicefx.mid, 5701 ca0132_voicefx.reqs[i], 5702 ca0132_voicefx_presets[sel].vals[i]); 5703 if (err < 0) 5704 break; 5705 } 5706 5707 if (err >= 0) { 5708 spec->voicefx_val = sel; 5709 /* enable voice fx */ 5710 ca0132_voicefx_set(codec, (sel ? 1 : 0)); 5711 } 5712 5713 return 1; 5714 } 5715 5716 static int ca0132_switch_get(struct snd_kcontrol *kcontrol, 5717 struct snd_ctl_elem_value *ucontrol) 5718 { 5719 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5720 struct ca0132_spec *spec = codec->spec; 5721 hda_nid_t nid = get_amp_nid(kcontrol); 5722 int ch = get_amp_channels(kcontrol); 5723 long *valp = ucontrol->value.integer.value; 5724 5725 /* vnode */ 5726 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 5727 if (ch & 1) { 5728 *valp = spec->vnode_lswitch[nid - VNODE_START_NID]; 5729 valp++; 5730 } 5731 if (ch & 2) { 5732 *valp = spec->vnode_rswitch[nid - VNODE_START_NID]; 5733 valp++; 5734 } 5735 return 0; 5736 } 5737 5738 /* effects, include PE and CrystalVoice */ 5739 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) { 5740 *valp = spec->effects_switch[nid - EFFECT_START_NID]; 5741 return 0; 5742 } 5743 5744 /* mic boost */ 5745 if (nid == spec->input_pins[0]) { 5746 *valp = spec->cur_mic_boost; 5747 return 0; 5748 } 5749 5750 return 0; 5751 } 5752 5753 static int ca0132_switch_put(struct snd_kcontrol *kcontrol, 5754 struct snd_ctl_elem_value *ucontrol) 5755 { 5756 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5757 struct ca0132_spec *spec = codec->spec; 5758 hda_nid_t nid = get_amp_nid(kcontrol); 5759 int ch = get_amp_channels(kcontrol); 5760 long *valp = ucontrol->value.integer.value; 5761 int changed = 1; 5762 5763 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n", 5764 nid, *valp); 5765 5766 snd_hda_power_up(codec); 5767 /* vnode */ 5768 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 5769 if (ch & 1) { 5770 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp; 5771 valp++; 5772 } 5773 if (ch & 2) { 5774 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp; 5775 valp++; 5776 } 5777 changed = ca0132_vnode_switch_set(kcontrol, ucontrol); 5778 goto exit; 5779 } 5780 5781 /* PE */ 5782 if (nid == PLAY_ENHANCEMENT) { 5783 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 5784 changed = ca0132_pe_switch_set(codec); 5785 goto exit; 5786 } 5787 5788 /* CrystalVoice */ 5789 if (nid == CRYSTAL_VOICE) { 5790 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 5791 changed = ca0132_cvoice_switch_set(codec); 5792 goto exit; 5793 } 5794 5795 /* out and in effects */ 5796 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) || 5797 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) { 5798 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 5799 changed = ca0132_effects_set(codec, nid, *valp); 5800 goto exit; 5801 } 5802 5803 /* mic boost */ 5804 if (nid == spec->input_pins[0]) { 5805 spec->cur_mic_boost = *valp; 5806 if (ca0132_use_alt_functions(spec)) { 5807 if (spec->in_enum_val != REAR_LINE_IN) 5808 changed = ca0132_mic_boost_set(codec, *valp); 5809 } else { 5810 /* Mic boost does not apply to Digital Mic */ 5811 if (spec->cur_mic_type != DIGITAL_MIC) 5812 changed = ca0132_mic_boost_set(codec, *valp); 5813 } 5814 5815 goto exit; 5816 } 5817 5818 if (nid == ZXR_HEADPHONE_GAIN) { 5819 spec->zxr_gain_set = *valp; 5820 if (spec->cur_out_type == HEADPHONE_OUT) 5821 changed = zxr_headphone_gain_set(codec, *valp); 5822 else 5823 changed = 0; 5824 5825 goto exit; 5826 } 5827 5828 exit: 5829 snd_hda_power_down(codec); 5830 return changed; 5831 } 5832 5833 /* 5834 * Volume related 5835 */ 5836 /* 5837 * Sets the internal DSP decibel level to match the DAC for output, and the 5838 * ADC for input. Currently only the SBZ sets dsp capture volume level, and 5839 * all alternative codecs set DSP playback volume. 5840 */ 5841 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid) 5842 { 5843 struct ca0132_spec *spec = codec->spec; 5844 unsigned int dsp_dir; 5845 unsigned int lookup_val; 5846 5847 if (nid == VNID_SPK) 5848 dsp_dir = DSP_VOL_OUT; 5849 else 5850 dsp_dir = DSP_VOL_IN; 5851 5852 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID]; 5853 5854 dspio_set_uint_param(codec, 5855 ca0132_alt_vol_ctls[dsp_dir].mid, 5856 ca0132_alt_vol_ctls[dsp_dir].reqs[0], 5857 float_vol_db_lookup[lookup_val]); 5858 5859 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID]; 5860 5861 dspio_set_uint_param(codec, 5862 ca0132_alt_vol_ctls[dsp_dir].mid, 5863 ca0132_alt_vol_ctls[dsp_dir].reqs[1], 5864 float_vol_db_lookup[lookup_val]); 5865 5866 dspio_set_uint_param(codec, 5867 ca0132_alt_vol_ctls[dsp_dir].mid, 5868 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO); 5869 } 5870 5871 static int ca0132_volume_info(struct snd_kcontrol *kcontrol, 5872 struct snd_ctl_elem_info *uinfo) 5873 { 5874 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5875 struct ca0132_spec *spec = codec->spec; 5876 hda_nid_t nid = get_amp_nid(kcontrol); 5877 int ch = get_amp_channels(kcontrol); 5878 int dir = get_amp_direction(kcontrol); 5879 unsigned long pval; 5880 int err; 5881 5882 switch (nid) { 5883 case VNID_SPK: 5884 /* follow shared_out info */ 5885 nid = spec->shared_out_nid; 5886 mutex_lock(&codec->control_mutex); 5887 pval = kcontrol->private_value; 5888 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 5889 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 5890 kcontrol->private_value = pval; 5891 mutex_unlock(&codec->control_mutex); 5892 break; 5893 case VNID_MIC: 5894 /* follow shared_mic info */ 5895 nid = spec->shared_mic_nid; 5896 mutex_lock(&codec->control_mutex); 5897 pval = kcontrol->private_value; 5898 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 5899 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 5900 kcontrol->private_value = pval; 5901 mutex_unlock(&codec->control_mutex); 5902 break; 5903 default: 5904 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 5905 } 5906 return err; 5907 } 5908 5909 static int ca0132_volume_get(struct snd_kcontrol *kcontrol, 5910 struct snd_ctl_elem_value *ucontrol) 5911 { 5912 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5913 struct ca0132_spec *spec = codec->spec; 5914 hda_nid_t nid = get_amp_nid(kcontrol); 5915 int ch = get_amp_channels(kcontrol); 5916 long *valp = ucontrol->value.integer.value; 5917 5918 /* store the left and right volume */ 5919 if (ch & 1) { 5920 *valp = spec->vnode_lvol[nid - VNODE_START_NID]; 5921 valp++; 5922 } 5923 if (ch & 2) { 5924 *valp = spec->vnode_rvol[nid - VNODE_START_NID]; 5925 valp++; 5926 } 5927 return 0; 5928 } 5929 5930 static int ca0132_volume_put(struct snd_kcontrol *kcontrol, 5931 struct snd_ctl_elem_value *ucontrol) 5932 { 5933 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5934 struct ca0132_spec *spec = codec->spec; 5935 hda_nid_t nid = get_amp_nid(kcontrol); 5936 int ch = get_amp_channels(kcontrol); 5937 long *valp = ucontrol->value.integer.value; 5938 hda_nid_t shared_nid = 0; 5939 bool effective; 5940 int changed = 1; 5941 5942 /* store the left and right volume */ 5943 if (ch & 1) { 5944 spec->vnode_lvol[nid - VNODE_START_NID] = *valp; 5945 valp++; 5946 } 5947 if (ch & 2) { 5948 spec->vnode_rvol[nid - VNODE_START_NID] = *valp; 5949 valp++; 5950 } 5951 5952 /* if effective conditions, then update hw immediately. */ 5953 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 5954 if (effective) { 5955 int dir = get_amp_direction(kcontrol); 5956 unsigned long pval; 5957 5958 snd_hda_power_up(codec); 5959 mutex_lock(&codec->control_mutex); 5960 pval = kcontrol->private_value; 5961 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 5962 0, dir); 5963 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 5964 kcontrol->private_value = pval; 5965 mutex_unlock(&codec->control_mutex); 5966 snd_hda_power_down(codec); 5967 } 5968 5969 return changed; 5970 } 5971 5972 /* 5973 * This function is the same as the one above, because using an if statement 5974 * inside of the above volume control for the DSP volume would cause too much 5975 * lag. This is a lot more smooth. 5976 */ 5977 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol, 5978 struct snd_ctl_elem_value *ucontrol) 5979 { 5980 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5981 struct ca0132_spec *spec = codec->spec; 5982 hda_nid_t nid = get_amp_nid(kcontrol); 5983 int ch = get_amp_channels(kcontrol); 5984 long *valp = ucontrol->value.integer.value; 5985 hda_nid_t vnid = 0; 5986 int changed; 5987 5988 switch (nid) { 5989 case 0x02: 5990 vnid = VNID_SPK; 5991 break; 5992 case 0x07: 5993 vnid = VNID_MIC; 5994 break; 5995 } 5996 5997 /* store the left and right volume */ 5998 if (ch & 1) { 5999 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp; 6000 valp++; 6001 } 6002 if (ch & 2) { 6003 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp; 6004 valp++; 6005 } 6006 6007 snd_hda_power_up(codec); 6008 ca0132_alt_dsp_volume_put(codec, vnid); 6009 mutex_lock(&codec->control_mutex); 6010 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 6011 mutex_unlock(&codec->control_mutex); 6012 snd_hda_power_down(codec); 6013 6014 return changed; 6015 } 6016 6017 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag, 6018 unsigned int size, unsigned int __user *tlv) 6019 { 6020 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6021 struct ca0132_spec *spec = codec->spec; 6022 hda_nid_t nid = get_amp_nid(kcontrol); 6023 int ch = get_amp_channels(kcontrol); 6024 int dir = get_amp_direction(kcontrol); 6025 unsigned long pval; 6026 int err; 6027 6028 switch (nid) { 6029 case VNID_SPK: 6030 /* follow shared_out tlv */ 6031 nid = spec->shared_out_nid; 6032 mutex_lock(&codec->control_mutex); 6033 pval = kcontrol->private_value; 6034 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6035 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6036 kcontrol->private_value = pval; 6037 mutex_unlock(&codec->control_mutex); 6038 break; 6039 case VNID_MIC: 6040 /* follow shared_mic tlv */ 6041 nid = spec->shared_mic_nid; 6042 mutex_lock(&codec->control_mutex); 6043 pval = kcontrol->private_value; 6044 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6045 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6046 kcontrol->private_value = pval; 6047 mutex_unlock(&codec->control_mutex); 6048 break; 6049 default: 6050 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6051 } 6052 return err; 6053 } 6054 6055 /* Add volume slider control for effect level */ 6056 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid, 6057 const char *pfx, int dir) 6058 { 6059 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6060 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6061 struct snd_kcontrol_new knew = 6062 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 6063 6064 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]); 6065 6066 knew.tlv.c = NULL; 6067 6068 switch (nid) { 6069 case XBASS_XOVER: 6070 knew.info = ca0132_alt_xbass_xover_slider_info; 6071 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 6072 knew.put = ca0132_alt_xbass_xover_slider_put; 6073 break; 6074 default: 6075 knew.info = ca0132_alt_effect_slider_info; 6076 knew.get = ca0132_alt_slider_ctl_get; 6077 knew.put = ca0132_alt_effect_slider_put; 6078 knew.private_value = 6079 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 6080 break; 6081 } 6082 6083 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6084 } 6085 6086 /* 6087 * Added FX: prefix for the alternative codecs, because otherwise the surround 6088 * effect would conflict with the Surround sound volume control. Also seems more 6089 * clear as to what the switches do. Left alone for others. 6090 */ 6091 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid, 6092 const char *pfx, int dir) 6093 { 6094 struct ca0132_spec *spec = codec->spec; 6095 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6096 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6097 struct snd_kcontrol_new knew = 6098 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type); 6099 /* If using alt_controls, add FX: prefix. But, don't add FX: 6100 * prefix to OutFX or InFX enable controls. 6101 */ 6102 if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID)) 6103 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]); 6104 else 6105 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]); 6106 6107 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6108 } 6109 6110 static int add_voicefx(struct hda_codec *codec) 6111 { 6112 struct snd_kcontrol_new knew = 6113 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name, 6114 VOICEFX, 1, 0, HDA_INPUT); 6115 knew.info = ca0132_voicefx_info; 6116 knew.get = ca0132_voicefx_get; 6117 knew.put = ca0132_voicefx_put; 6118 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec)); 6119 } 6120 6121 /* Create the EQ Preset control */ 6122 static int add_ca0132_alt_eq_presets(struct hda_codec *codec) 6123 { 6124 struct snd_kcontrol_new knew = 6125 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name, 6126 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT); 6127 knew.info = ca0132_alt_eq_preset_info; 6128 knew.get = ca0132_alt_eq_preset_get; 6129 knew.put = ca0132_alt_eq_preset_put; 6130 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM, 6131 snd_ctl_new1(&knew, codec)); 6132 } 6133 6134 /* 6135 * Add enumerated control for the three different settings of the smart volume 6136 * output effect. Normal just uses the slider value, and loud and night are 6137 * their own things that ignore that value. 6138 */ 6139 static int ca0132_alt_add_svm_enum(struct hda_codec *codec) 6140 { 6141 struct snd_kcontrol_new knew = 6142 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting", 6143 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT); 6144 knew.info = ca0132_alt_svm_setting_info; 6145 knew.get = ca0132_alt_svm_setting_get; 6146 knew.put = ca0132_alt_svm_setting_put; 6147 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM, 6148 snd_ctl_new1(&knew, codec)); 6149 6150 } 6151 6152 /* 6153 * Create an Output Select enumerated control for codecs with surround 6154 * out capabilities. 6155 */ 6156 static int ca0132_alt_add_output_enum(struct hda_codec *codec) 6157 { 6158 struct snd_kcontrol_new knew = 6159 HDA_CODEC_MUTE_MONO("Output Select", 6160 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT); 6161 knew.info = ca0132_alt_output_select_get_info; 6162 knew.get = ca0132_alt_output_select_get; 6163 knew.put = ca0132_alt_output_select_put; 6164 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM, 6165 snd_ctl_new1(&knew, codec)); 6166 } 6167 6168 /* 6169 * Create an Input Source enumerated control for the alternate ca0132 codecs 6170 * because the front microphone has no auto-detect, and Line-in has to be set 6171 * somehow. 6172 */ 6173 static int ca0132_alt_add_input_enum(struct hda_codec *codec) 6174 { 6175 struct snd_kcontrol_new knew = 6176 HDA_CODEC_MUTE_MONO("Input Source", 6177 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT); 6178 knew.info = ca0132_alt_input_source_info; 6179 knew.get = ca0132_alt_input_source_get; 6180 knew.put = ca0132_alt_input_source_put; 6181 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM, 6182 snd_ctl_new1(&knew, codec)); 6183 } 6184 6185 /* 6186 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds 6187 * more control than the original mic boost, which is either full 30dB or off. 6188 */ 6189 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec) 6190 { 6191 struct snd_kcontrol_new knew = 6192 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch", 6193 MIC_BOOST_ENUM, 1, 0, HDA_INPUT); 6194 knew.info = ca0132_alt_mic_boost_info; 6195 knew.get = ca0132_alt_mic_boost_get; 6196 knew.put = ca0132_alt_mic_boost_put; 6197 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM, 6198 snd_ctl_new1(&knew, codec)); 6199 6200 } 6201 6202 /* 6203 * Add headphone gain enumerated control for the AE-5. This switches between 6204 * three modes, low, medium, and high. When non-headphone outputs are selected, 6205 * it is automatically set to high. This is the same behavior as Windows. 6206 */ 6207 static int ae5_add_headphone_gain_enum(struct hda_codec *codec) 6208 { 6209 struct snd_kcontrol_new knew = 6210 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain", 6211 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT); 6212 knew.info = ae5_headphone_gain_info; 6213 knew.get = ae5_headphone_gain_get; 6214 knew.put = ae5_headphone_gain_put; 6215 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM, 6216 snd_ctl_new1(&knew, codec)); 6217 } 6218 6219 /* 6220 * Add sound filter enumerated control for the AE-5. This adds three different 6221 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've 6222 * read into it, it changes the DAC's interpolation filter. 6223 */ 6224 static int ae5_add_sound_filter_enum(struct hda_codec *codec) 6225 { 6226 struct snd_kcontrol_new knew = 6227 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter", 6228 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT); 6229 knew.info = ae5_sound_filter_info; 6230 knew.get = ae5_sound_filter_get; 6231 knew.put = ae5_sound_filter_put; 6232 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM, 6233 snd_ctl_new1(&knew, codec)); 6234 } 6235 6236 static int zxr_add_headphone_gain_switch(struct hda_codec *codec) 6237 { 6238 struct snd_kcontrol_new knew = 6239 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain", 6240 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT); 6241 6242 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN, 6243 snd_ctl_new1(&knew, codec)); 6244 } 6245 6246 /* 6247 * Need to create slave controls for the alternate codecs that have surround 6248 * capabilities. 6249 */ 6250 static const char * const ca0132_alt_slave_pfxs[] = { 6251 "Front", "Surround", "Center", "LFE", NULL, 6252 }; 6253 6254 /* 6255 * Also need special channel map, because the default one is incorrect. 6256 * I think this has to do with the pin for rear surround being 0x11, 6257 * and the center/lfe being 0x10. Usually the pin order is the opposite. 6258 */ 6259 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = { 6260 { .channels = 2, 6261 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } }, 6262 { .channels = 4, 6263 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6264 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6265 { .channels = 6, 6266 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6267 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE, 6268 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6269 { } 6270 }; 6271 6272 /* Add the correct chmap for streams with 6 channels. */ 6273 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec) 6274 { 6275 int err = 0; 6276 struct hda_pcm *pcm; 6277 6278 list_for_each_entry(pcm, &codec->pcm_list_head, list) { 6279 struct hda_pcm_stream *hinfo = 6280 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 6281 struct snd_pcm_chmap *chmap; 6282 const struct snd_pcm_chmap_elem *elem; 6283 6284 elem = ca0132_alt_chmaps; 6285 if (hinfo->channels_max == 6) { 6286 err = snd_pcm_add_chmap_ctls(pcm->pcm, 6287 SNDRV_PCM_STREAM_PLAYBACK, 6288 elem, hinfo->channels_max, 0, &chmap); 6289 if (err < 0) 6290 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!"); 6291 } 6292 } 6293 } 6294 6295 /* 6296 * When changing Node IDs for Mixer Controls below, make sure to update 6297 * Node IDs in ca0132_config() as well. 6298 */ 6299 static const struct snd_kcontrol_new ca0132_mixer[] = { 6300 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT), 6301 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT), 6302 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 6303 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6304 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT), 6305 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT), 6306 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6307 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6308 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch", 6309 0x12, 1, HDA_INPUT), 6310 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch", 6311 VNID_HP_SEL, 1, HDA_OUTPUT), 6312 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch", 6313 VNID_AMIC1_SEL, 1, HDA_INPUT), 6314 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6315 VNID_HP_ASEL, 1, HDA_OUTPUT), 6316 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch", 6317 VNID_AMIC1_ASEL, 1, HDA_INPUT), 6318 { } /* end */ 6319 }; 6320 6321 /* 6322 * Desktop specific control mixer. Removes auto-detect for mic, and adds 6323 * surround controls. Also sets both the Front Playback and Capture Volume 6324 * controls to alt so they set the DSP's decibel level. 6325 */ 6326 static const struct snd_kcontrol_new desktop_mixer[] = { 6327 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 6328 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 6329 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 6330 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 6331 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 6332 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 6333 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 6334 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 6335 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT), 6336 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6337 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6338 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6339 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6340 VNID_HP_ASEL, 1, HDA_OUTPUT), 6341 { } /* end */ 6342 }; 6343 6344 /* 6345 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture 6346 * because it doesn't set decibel levels for the DSP for capture. 6347 */ 6348 static const struct snd_kcontrol_new r3di_mixer[] = { 6349 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 6350 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 6351 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 6352 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 6353 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 6354 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 6355 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 6356 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 6357 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 6358 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6359 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6360 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6361 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6362 VNID_HP_ASEL, 1, HDA_OUTPUT), 6363 { } /* end */ 6364 }; 6365 6366 static int ca0132_build_controls(struct hda_codec *codec) 6367 { 6368 struct ca0132_spec *spec = codec->spec; 6369 int i, num_fx, num_sliders; 6370 int err = 0; 6371 6372 /* Add Mixer controls */ 6373 for (i = 0; i < spec->num_mixers; i++) { 6374 err = snd_hda_add_new_ctls(codec, spec->mixers[i]); 6375 if (err < 0) 6376 return err; 6377 } 6378 /* Setup vmaster with surround slaves for desktop ca0132 devices */ 6379 if (ca0132_use_alt_functions(spec)) { 6380 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT, 6381 spec->tlv); 6382 snd_hda_add_vmaster(codec, "Master Playback Volume", 6383 spec->tlv, ca0132_alt_slave_pfxs, 6384 "Playback Volume"); 6385 err = __snd_hda_add_vmaster(codec, "Master Playback Switch", 6386 NULL, ca0132_alt_slave_pfxs, 6387 "Playback Switch", 6388 true, &spec->vmaster_mute.sw_kctl); 6389 if (err < 0) 6390 return err; 6391 } 6392 6393 /* Add in and out effects controls. 6394 * VoiceFX, PE and CrystalVoice are added separately. 6395 */ 6396 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 6397 for (i = 0; i < num_fx; i++) { 6398 /* Desktop cards break if Echo Cancellation is used. */ 6399 if (ca0132_use_pci_mmio(spec)) { 6400 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID + 6401 OUT_EFFECTS_COUNT)) 6402 continue; 6403 } 6404 6405 err = add_fx_switch(codec, ca0132_effects[i].nid, 6406 ca0132_effects[i].name, 6407 ca0132_effects[i].direct); 6408 if (err < 0) 6409 return err; 6410 } 6411 /* 6412 * If codec has use_alt_controls set to true, add effect level sliders, 6413 * EQ presets, and Smart Volume presets. Also, change names to add FX 6414 * prefix, and change PlayEnhancement and CrystalVoice to match. 6415 */ 6416 if (ca0132_use_alt_controls(spec)) { 6417 err = ca0132_alt_add_svm_enum(codec); 6418 if (err < 0) 6419 return err; 6420 6421 err = add_ca0132_alt_eq_presets(codec); 6422 if (err < 0) 6423 return err; 6424 6425 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 6426 "Enable OutFX", 0); 6427 if (err < 0) 6428 return err; 6429 6430 err = add_fx_switch(codec, CRYSTAL_VOICE, 6431 "Enable InFX", 1); 6432 if (err < 0) 6433 return err; 6434 6435 num_sliders = OUT_EFFECTS_COUNT - 1; 6436 for (i = 0; i < num_sliders; i++) { 6437 err = ca0132_alt_add_effect_slider(codec, 6438 ca0132_effects[i].nid, 6439 ca0132_effects[i].name, 6440 ca0132_effects[i].direct); 6441 if (err < 0) 6442 return err; 6443 } 6444 6445 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER, 6446 "X-Bass Crossover", EFX_DIR_OUT); 6447 6448 if (err < 0) 6449 return err; 6450 } else { 6451 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 6452 "PlayEnhancement", 0); 6453 if (err < 0) 6454 return err; 6455 6456 err = add_fx_switch(codec, CRYSTAL_VOICE, 6457 "CrystalVoice", 1); 6458 if (err < 0) 6459 return err; 6460 } 6461 err = add_voicefx(codec); 6462 if (err < 0) 6463 return err; 6464 6465 /* 6466 * If the codec uses alt_functions, you need the enumerated controls 6467 * to select the new outputs and inputs, plus add the new mic boost 6468 * setting control. 6469 */ 6470 if (ca0132_use_alt_functions(spec)) { 6471 err = ca0132_alt_add_output_enum(codec); 6472 if (err < 0) 6473 return err; 6474 err = ca0132_alt_add_mic_boost_enum(codec); 6475 if (err < 0) 6476 return err; 6477 /* 6478 * ZxR only has microphone input, there is no front panel 6479 * header on the card, and aux-in is handled by the DBPro board. 6480 */ 6481 if (ca0132_quirk(spec) != QUIRK_ZXR) { 6482 err = ca0132_alt_add_input_enum(codec); 6483 if (err < 0) 6484 return err; 6485 } 6486 } 6487 6488 if (ca0132_quirk(spec) == QUIRK_AE5) { 6489 err = ae5_add_headphone_gain_enum(codec); 6490 if (err < 0) 6491 return err; 6492 err = ae5_add_sound_filter_enum(codec); 6493 if (err < 0) 6494 return err; 6495 } 6496 6497 if (ca0132_quirk(spec) == QUIRK_ZXR) { 6498 err = zxr_add_headphone_gain_switch(codec); 6499 if (err < 0) 6500 return err; 6501 } 6502 #ifdef ENABLE_TUNING_CONTROLS 6503 add_tuning_ctls(codec); 6504 #endif 6505 6506 err = snd_hda_jack_add_kctls(codec, &spec->autocfg); 6507 if (err < 0) 6508 return err; 6509 6510 if (spec->dig_out) { 6511 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 6512 spec->dig_out); 6513 if (err < 0) 6514 return err; 6515 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout); 6516 if (err < 0) 6517 return err; 6518 /* spec->multiout.share_spdif = 1; */ 6519 } 6520 6521 if (spec->dig_in) { 6522 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 6523 if (err < 0) 6524 return err; 6525 } 6526 6527 if (ca0132_use_alt_functions(spec)) 6528 ca0132_alt_add_chmap_ctls(codec); 6529 6530 return 0; 6531 } 6532 6533 static int dbpro_build_controls(struct hda_codec *codec) 6534 { 6535 struct ca0132_spec *spec = codec->spec; 6536 int err = 0; 6537 6538 if (spec->dig_out) { 6539 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 6540 spec->dig_out); 6541 if (err < 0) 6542 return err; 6543 } 6544 6545 if (spec->dig_in) { 6546 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 6547 if (err < 0) 6548 return err; 6549 } 6550 6551 return 0; 6552 } 6553 6554 /* 6555 * PCM 6556 */ 6557 static const struct hda_pcm_stream ca0132_pcm_analog_playback = { 6558 .substreams = 1, 6559 .channels_min = 2, 6560 .channels_max = 6, 6561 .ops = { 6562 .prepare = ca0132_playback_pcm_prepare, 6563 .cleanup = ca0132_playback_pcm_cleanup, 6564 .get_delay = ca0132_playback_pcm_delay, 6565 }, 6566 }; 6567 6568 static const struct hda_pcm_stream ca0132_pcm_analog_capture = { 6569 .substreams = 1, 6570 .channels_min = 2, 6571 .channels_max = 2, 6572 .ops = { 6573 .prepare = ca0132_capture_pcm_prepare, 6574 .cleanup = ca0132_capture_pcm_cleanup, 6575 .get_delay = ca0132_capture_pcm_delay, 6576 }, 6577 }; 6578 6579 static const struct hda_pcm_stream ca0132_pcm_digital_playback = { 6580 .substreams = 1, 6581 .channels_min = 2, 6582 .channels_max = 2, 6583 .ops = { 6584 .open = ca0132_dig_playback_pcm_open, 6585 .close = ca0132_dig_playback_pcm_close, 6586 .prepare = ca0132_dig_playback_pcm_prepare, 6587 .cleanup = ca0132_dig_playback_pcm_cleanup 6588 }, 6589 }; 6590 6591 static const struct hda_pcm_stream ca0132_pcm_digital_capture = { 6592 .substreams = 1, 6593 .channels_min = 2, 6594 .channels_max = 2, 6595 }; 6596 6597 static int ca0132_build_pcms(struct hda_codec *codec) 6598 { 6599 struct ca0132_spec *spec = codec->spec; 6600 struct hda_pcm *info; 6601 6602 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog"); 6603 if (!info) 6604 return -ENOMEM; 6605 if (ca0132_use_alt_functions(spec)) { 6606 info->own_chmap = true; 6607 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap 6608 = ca0132_alt_chmaps; 6609 } 6610 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback; 6611 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0]; 6612 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max = 6613 spec->multiout.max_channels; 6614 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 6615 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 6616 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 6617 6618 /* With the DSP enabled, desktops don't use this ADC. */ 6619 if (!ca0132_use_alt_functions(spec)) { 6620 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2"); 6621 if (!info) 6622 return -ENOMEM; 6623 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 6624 ca0132_pcm_analog_capture; 6625 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 6626 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1]; 6627 } 6628 6629 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear"); 6630 if (!info) 6631 return -ENOMEM; 6632 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 6633 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 6634 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2]; 6635 6636 if (!spec->dig_out && !spec->dig_in) 6637 return 0; 6638 6639 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 6640 if (!info) 6641 return -ENOMEM; 6642 info->pcm_type = HDA_PCM_TYPE_SPDIF; 6643 if (spec->dig_out) { 6644 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 6645 ca0132_pcm_digital_playback; 6646 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 6647 } 6648 if (spec->dig_in) { 6649 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 6650 ca0132_pcm_digital_capture; 6651 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 6652 } 6653 6654 return 0; 6655 } 6656 6657 static int dbpro_build_pcms(struct hda_codec *codec) 6658 { 6659 struct ca0132_spec *spec = codec->spec; 6660 struct hda_pcm *info; 6661 6662 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog"); 6663 if (!info) 6664 return -ENOMEM; 6665 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 6666 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 6667 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 6668 6669 6670 if (!spec->dig_out && !spec->dig_in) 6671 return 0; 6672 6673 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 6674 if (!info) 6675 return -ENOMEM; 6676 info->pcm_type = HDA_PCM_TYPE_SPDIF; 6677 if (spec->dig_out) { 6678 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 6679 ca0132_pcm_digital_playback; 6680 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 6681 } 6682 if (spec->dig_in) { 6683 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 6684 ca0132_pcm_digital_capture; 6685 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 6686 } 6687 6688 return 0; 6689 } 6690 6691 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac) 6692 { 6693 if (pin) { 6694 snd_hda_set_pin_ctl(codec, pin, PIN_HP); 6695 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 6696 snd_hda_codec_write(codec, pin, 0, 6697 AC_VERB_SET_AMP_GAIN_MUTE, 6698 AMP_OUT_UNMUTE); 6699 } 6700 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP)) 6701 snd_hda_codec_write(codec, dac, 0, 6702 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO); 6703 } 6704 6705 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc) 6706 { 6707 if (pin) { 6708 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80); 6709 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP) 6710 snd_hda_codec_write(codec, pin, 0, 6711 AC_VERB_SET_AMP_GAIN_MUTE, 6712 AMP_IN_UNMUTE(0)); 6713 } 6714 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) { 6715 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE, 6716 AMP_IN_UNMUTE(0)); 6717 6718 /* init to 0 dB and unmute. */ 6719 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 6720 HDA_AMP_VOLMASK, 0x5a); 6721 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 6722 HDA_AMP_MUTE, 0); 6723 } 6724 } 6725 6726 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir) 6727 { 6728 unsigned int caps; 6729 6730 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ? 6731 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP); 6732 snd_hda_override_amp_caps(codec, nid, dir, caps); 6733 } 6734 6735 /* 6736 * Switch between Digital built-in mic and analog mic. 6737 */ 6738 static void ca0132_set_dmic(struct hda_codec *codec, int enable) 6739 { 6740 struct ca0132_spec *spec = codec->spec; 6741 unsigned int tmp; 6742 u8 val; 6743 unsigned int oldval; 6744 6745 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable); 6746 6747 oldval = stop_mic1(codec); 6748 ca0132_set_vipsource(codec, 0); 6749 if (enable) { 6750 /* set DMic input as 2-ch */ 6751 tmp = FLOAT_TWO; 6752 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 6753 6754 val = spec->dmic_ctl; 6755 val |= 0x80; 6756 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6757 VENDOR_CHIPIO_DMIC_CTL_SET, val); 6758 6759 if (!(spec->dmic_ctl & 0x20)) 6760 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1); 6761 } else { 6762 /* set AMic input as mono */ 6763 tmp = FLOAT_ONE; 6764 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 6765 6766 val = spec->dmic_ctl; 6767 /* clear bit7 and bit5 to disable dmic */ 6768 val &= 0x5f; 6769 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6770 VENDOR_CHIPIO_DMIC_CTL_SET, val); 6771 6772 if (!(spec->dmic_ctl & 0x20)) 6773 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0); 6774 } 6775 ca0132_set_vipsource(codec, 1); 6776 resume_mic1(codec, oldval); 6777 } 6778 6779 /* 6780 * Initialization for Digital Mic. 6781 */ 6782 static void ca0132_init_dmic(struct hda_codec *codec) 6783 { 6784 struct ca0132_spec *spec = codec->spec; 6785 u8 val; 6786 6787 /* Setup Digital Mic here, but don't enable. 6788 * Enable based on jack detect. 6789 */ 6790 6791 /* MCLK uses MPIO1, set to enable. 6792 * Bit 2-0: MPIO select 6793 * Bit 3: set to disable 6794 * Bit 7-4: reserved 6795 */ 6796 val = 0x01; 6797 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6798 VENDOR_CHIPIO_DMIC_MCLK_SET, val); 6799 6800 /* Data1 uses MPIO3. Data2 not use 6801 * Bit 2-0: Data1 MPIO select 6802 * Bit 3: set disable Data1 6803 * Bit 6-4: Data2 MPIO select 6804 * Bit 7: set disable Data2 6805 */ 6806 val = 0x83; 6807 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6808 VENDOR_CHIPIO_DMIC_PIN_SET, val); 6809 6810 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first. 6811 * Bit 3-0: Channel mask 6812 * Bit 4: set for 48KHz, clear for 32KHz 6813 * Bit 5: mode 6814 * Bit 6: set to select Data2, clear for Data1 6815 * Bit 7: set to enable DMic, clear for AMic 6816 */ 6817 if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4) 6818 val = 0x33; 6819 else 6820 val = 0x23; 6821 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */ 6822 spec->dmic_ctl = val; 6823 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6824 VENDOR_CHIPIO_DMIC_CTL_SET, val); 6825 } 6826 6827 /* 6828 * Initialization for Analog Mic 2 6829 */ 6830 static void ca0132_init_analog_mic2(struct hda_codec *codec) 6831 { 6832 struct ca0132_spec *spec = codec->spec; 6833 6834 mutex_lock(&spec->chipio_mutex); 6835 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6836 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); 6837 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6838 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 6839 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6840 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 6841 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6842 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D); 6843 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6844 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 6845 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6846 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 6847 mutex_unlock(&spec->chipio_mutex); 6848 } 6849 6850 static void ca0132_refresh_widget_caps(struct hda_codec *codec) 6851 { 6852 struct ca0132_spec *spec = codec->spec; 6853 int i; 6854 6855 codec_dbg(codec, "ca0132_refresh_widget_caps.\n"); 6856 snd_hda_codec_update_widgets(codec); 6857 6858 for (i = 0; i < spec->multiout.num_dacs; i++) 6859 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT); 6860 6861 for (i = 0; i < spec->num_outputs; i++) 6862 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT); 6863 6864 for (i = 0; i < spec->num_inputs; i++) { 6865 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT); 6866 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT); 6867 } 6868 } 6869 6870 /* 6871 * Creates a dummy stream to bind the output to. This seems to have to be done 6872 * after changing the main outputs source and destination streams. 6873 */ 6874 static void ca0132_alt_create_dummy_stream(struct hda_codec *codec) 6875 { 6876 struct ca0132_spec *spec = codec->spec; 6877 unsigned int stream_format; 6878 6879 stream_format = snd_hdac_calc_stream_format(48000, 2, 6880 SNDRV_PCM_FORMAT_S32_LE, 32, 0); 6881 6882 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id, 6883 0, stream_format); 6884 6885 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 6886 } 6887 6888 /* 6889 * Initialize mic for non-chromebook ca0132 implementations. 6890 */ 6891 static void ca0132_alt_init_analog_mics(struct hda_codec *codec) 6892 { 6893 struct ca0132_spec *spec = codec->spec; 6894 unsigned int tmp; 6895 6896 /* Mic 1 Setup */ 6897 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 6898 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 6899 if (ca0132_quirk(spec) == QUIRK_R3DI) { 6900 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 6901 tmp = FLOAT_ONE; 6902 } else 6903 tmp = FLOAT_THREE; 6904 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 6905 6906 /* Mic 2 setup (not present on desktop cards) */ 6907 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000); 6908 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000); 6909 if (ca0132_quirk(spec) == QUIRK_R3DI) 6910 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 6911 tmp = FLOAT_ZERO; 6912 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 6913 } 6914 6915 /* 6916 * Sets the source of stream 0x14 to connpointID 0x48, and the destination 6917 * connpointID to 0x91. If this isn't done, the destination is 0x71, and 6918 * you get no sound. I'm guessing this has to do with the Sound Blaster Z 6919 * having an updated DAC, which changes the destination to that DAC. 6920 */ 6921 static void sbz_connect_streams(struct hda_codec *codec) 6922 { 6923 struct ca0132_spec *spec = codec->spec; 6924 6925 mutex_lock(&spec->chipio_mutex); 6926 6927 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n"); 6928 6929 chipio_set_stream_channels(codec, 0x0C, 6); 6930 chipio_set_stream_control(codec, 0x0C, 1); 6931 6932 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */ 6933 chipio_write_no_mutex(codec, 0x18a020, 0x00000043); 6934 6935 /* Setup stream 0x14 with it's source and destination points */ 6936 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91); 6937 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000); 6938 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000); 6939 chipio_set_stream_channels(codec, 0x14, 2); 6940 chipio_set_stream_control(codec, 0x14, 1); 6941 6942 codec_dbg(codec, "Connect Streams exited, mutex released.\n"); 6943 6944 mutex_unlock(&spec->chipio_mutex); 6945 } 6946 6947 /* 6948 * Write data through ChipIO to setup proper stream destinations. 6949 * Not sure how it exactly works, but it seems to direct data 6950 * to different destinations. Example is f8 to c0, e0 to c0. 6951 * All I know is, if you don't set these, you get no sound. 6952 */ 6953 static void sbz_chipio_startup_data(struct hda_codec *codec) 6954 { 6955 struct ca0132_spec *spec = codec->spec; 6956 6957 mutex_lock(&spec->chipio_mutex); 6958 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n"); 6959 6960 /* These control audio output */ 6961 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0); 6962 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1); 6963 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6); 6964 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7); 6965 /* Signal to update I think */ 6966 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 6967 6968 chipio_set_stream_channels(codec, 0x0C, 6); 6969 chipio_set_stream_control(codec, 0x0C, 1); 6970 /* No clue what these control */ 6971 if (ca0132_quirk(spec) == QUIRK_SBZ) { 6972 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0); 6973 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1); 6974 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2); 6975 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3); 6976 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4); 6977 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5); 6978 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6); 6979 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7); 6980 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8); 6981 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9); 6982 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca); 6983 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb); 6984 } else if (ca0132_quirk(spec) == QUIRK_ZXR) { 6985 chipio_write_no_mutex(codec, 0x190038, 0x000140c2); 6986 chipio_write_no_mutex(codec, 0x19003c, 0x000141c3); 6987 chipio_write_no_mutex(codec, 0x190040, 0x000150c4); 6988 chipio_write_no_mutex(codec, 0x190044, 0x000151c5); 6989 chipio_write_no_mutex(codec, 0x190050, 0x000142c8); 6990 chipio_write_no_mutex(codec, 0x190054, 0x000143c9); 6991 chipio_write_no_mutex(codec, 0x190058, 0x000152ca); 6992 chipio_write_no_mutex(codec, 0x19005c, 0x000153cb); 6993 } 6994 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 6995 6996 codec_dbg(codec, "Startup Data exited, mutex released.\n"); 6997 mutex_unlock(&spec->chipio_mutex); 6998 } 6999 7000 /* 7001 * Custom DSP SCP commands where the src value is 0x00 instead of 0x20. This is 7002 * done after the DSP is loaded. 7003 */ 7004 static void ca0132_alt_dsp_scp_startup(struct hda_codec *codec) 7005 { 7006 struct ca0132_spec *spec = codec->spec; 7007 unsigned int tmp, i; 7008 7009 /* 7010 * Gotta run these twice, or else mic works inconsistently. Not clear 7011 * why this is, but multiple tests have confirmed it. 7012 */ 7013 for (i = 0; i < 2; i++) { 7014 switch (ca0132_quirk(spec)) { 7015 case QUIRK_SBZ: 7016 case QUIRK_AE5: 7017 tmp = 0x00000003; 7018 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7019 tmp = 0x00000000; 7020 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp); 7021 tmp = 0x00000001; 7022 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp); 7023 tmp = 0x00000004; 7024 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7025 tmp = 0x00000005; 7026 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7027 tmp = 0x00000000; 7028 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7029 break; 7030 case QUIRK_R3D: 7031 case QUIRK_R3DI: 7032 tmp = 0x00000000; 7033 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp); 7034 tmp = 0x00000001; 7035 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp); 7036 tmp = 0x00000004; 7037 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7038 tmp = 0x00000005; 7039 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7040 tmp = 0x00000000; 7041 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7042 break; 7043 default: 7044 break; 7045 } 7046 msleep(100); 7047 } 7048 } 7049 7050 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec) 7051 { 7052 struct ca0132_spec *spec = codec->spec; 7053 unsigned int tmp; 7054 7055 chipio_set_stream_control(codec, 0x03, 0); 7056 chipio_set_stream_control(codec, 0x04, 0); 7057 7058 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7059 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7060 7061 tmp = FLOAT_THREE; 7062 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7063 7064 chipio_set_stream_control(codec, 0x03, 1); 7065 chipio_set_stream_control(codec, 0x04, 1); 7066 7067 switch (ca0132_quirk(spec)) { 7068 case QUIRK_SBZ: 7069 chipio_write(codec, 0x18b098, 0x0000000c); 7070 chipio_write(codec, 0x18b09C, 0x0000000c); 7071 break; 7072 case QUIRK_AE5: 7073 chipio_write(codec, 0x18b098, 0x0000000c); 7074 chipio_write(codec, 0x18b09c, 0x0000004c); 7075 break; 7076 default: 7077 break; 7078 } 7079 } 7080 7081 static void ae5_post_dsp_register_set(struct hda_codec *codec) 7082 { 7083 struct ca0132_spec *spec = codec->spec; 7084 7085 chipio_8051_write_direct(codec, 0x93, 0x10); 7086 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7087 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44); 7088 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7089 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2); 7090 7091 writeb(0xff, spec->mem_base + 0x304); 7092 writeb(0xff, spec->mem_base + 0x304); 7093 writeb(0xff, spec->mem_base + 0x304); 7094 writeb(0xff, spec->mem_base + 0x304); 7095 writeb(0x00, spec->mem_base + 0x100); 7096 writeb(0xff, spec->mem_base + 0x304); 7097 writeb(0x00, spec->mem_base + 0x100); 7098 writeb(0xff, spec->mem_base + 0x304); 7099 writeb(0x00, spec->mem_base + 0x100); 7100 writeb(0xff, spec->mem_base + 0x304); 7101 writeb(0x00, spec->mem_base + 0x100); 7102 writeb(0xff, spec->mem_base + 0x304); 7103 7104 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f); 7105 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 7106 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7107 } 7108 7109 static void ae5_post_dsp_param_setup(struct hda_codec *codec) 7110 { 7111 /* 7112 * Param3 in the 8051's memory is represented by the ascii string 'mch' 7113 * which seems to be 'multichannel'. This is also mentioned in the 7114 * AE-5's registry values in Windows. 7115 */ 7116 chipio_set_control_param(codec, 3, 0); 7117 /* 7118 * I believe ASI is 'audio serial interface' and that it's used to 7119 * change colors on the external LED strip connected to the AE-5. 7120 */ 7121 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); 7122 7123 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); 7124 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 7125 7126 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7127 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92); 7128 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7129 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa); 7130 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7131 VENDOR_CHIPIO_8051_DATA_WRITE, 0x22); 7132 } 7133 7134 static void ae5_post_dsp_pll_setup(struct hda_codec *codec) 7135 { 7136 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7137 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41); 7138 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7139 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8); 7140 7141 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7142 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x45); 7143 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7144 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcc); 7145 7146 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7147 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x40); 7148 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7149 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcb); 7150 7151 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7152 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43); 7153 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7154 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7); 7155 7156 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7157 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x51); 7158 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7159 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x8d); 7160 } 7161 7162 static void ae5_post_dsp_stream_setup(struct hda_codec *codec) 7163 { 7164 struct ca0132_spec *spec = codec->spec; 7165 7166 mutex_lock(&spec->chipio_mutex); 7167 7168 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); 7169 7170 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); 7171 7172 chipio_set_stream_channels(codec, 0x0C, 6); 7173 chipio_set_stream_control(codec, 0x0C, 1); 7174 7175 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0); 7176 7177 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0); 7178 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 7179 chipio_set_stream_channels(codec, 0x18, 6); 7180 chipio_set_stream_control(codec, 0x18, 1); 7181 7182 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); 7183 7184 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7185 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43); 7186 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7187 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7); 7188 7189 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80); 7190 7191 mutex_unlock(&spec->chipio_mutex); 7192 } 7193 7194 static void ae5_post_dsp_startup_data(struct hda_codec *codec) 7195 { 7196 struct ca0132_spec *spec = codec->spec; 7197 7198 mutex_lock(&spec->chipio_mutex); 7199 7200 chipio_write_no_mutex(codec, 0x189000, 0x0001f101); 7201 chipio_write_no_mutex(codec, 0x189004, 0x0001f101); 7202 chipio_write_no_mutex(codec, 0x189024, 0x00014004); 7203 chipio_write_no_mutex(codec, 0x189028, 0x0002000f); 7204 7205 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 7206 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 7207 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12); 7208 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00); 7209 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48); 7210 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 7211 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7212 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 7213 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 7214 ca0113_mmio_gpio_set(codec, 0, true); 7215 ca0113_mmio_gpio_set(codec, 1, true); 7216 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80); 7217 7218 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012); 7219 7220 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 7221 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 7222 7223 mutex_unlock(&spec->chipio_mutex); 7224 } 7225 7226 /* 7227 * Setup default parameters for DSP 7228 */ 7229 static void ca0132_setup_defaults(struct hda_codec *codec) 7230 { 7231 struct ca0132_spec *spec = codec->spec; 7232 unsigned int tmp; 7233 int num_fx; 7234 int idx, i; 7235 7236 if (spec->dsp_state != DSP_DOWNLOADED) 7237 return; 7238 7239 /* out, in effects + voicefx */ 7240 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 7241 for (idx = 0; idx < num_fx; idx++) { 7242 for (i = 0; i <= ca0132_effects[idx].params; i++) { 7243 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 7244 ca0132_effects[idx].reqs[i], 7245 ca0132_effects[idx].def_vals[i]); 7246 } 7247 } 7248 7249 /*remove DSP headroom*/ 7250 tmp = FLOAT_ZERO; 7251 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 7252 7253 /*set speaker EQ bypass attenuation*/ 7254 dspio_set_uint_param(codec, 0x8f, 0x01, tmp); 7255 7256 /* set AMic1 and AMic2 as mono mic */ 7257 tmp = FLOAT_ONE; 7258 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7259 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 7260 7261 /* set AMic1 as CrystalVoice input */ 7262 tmp = FLOAT_ONE; 7263 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 7264 7265 /* set WUH source */ 7266 tmp = FLOAT_TWO; 7267 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 7268 } 7269 7270 /* 7271 * Setup default parameters for Recon3D/Recon3Di DSP. 7272 */ 7273 7274 static void r3d_setup_defaults(struct hda_codec *codec) 7275 { 7276 struct ca0132_spec *spec = codec->spec; 7277 unsigned int tmp; 7278 int num_fx; 7279 int idx, i; 7280 7281 if (spec->dsp_state != DSP_DOWNLOADED) 7282 return; 7283 7284 ca0132_alt_dsp_scp_startup(codec); 7285 ca0132_alt_init_analog_mics(codec); 7286 7287 /*remove DSP headroom*/ 7288 tmp = FLOAT_ZERO; 7289 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 7290 7291 /* set WUH source */ 7292 tmp = FLOAT_TWO; 7293 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 7294 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7295 7296 /* Set speaker source? */ 7297 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 7298 7299 if (ca0132_quirk(spec) == QUIRK_R3DI) 7300 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED); 7301 7302 /* Setup effect defaults */ 7303 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 7304 for (idx = 0; idx < num_fx; idx++) { 7305 for (i = 0; i <= ca0132_effects[idx].params; i++) { 7306 dspio_set_uint_param(codec, 7307 ca0132_effects[idx].mid, 7308 ca0132_effects[idx].reqs[i], 7309 ca0132_effects[idx].def_vals[i]); 7310 } 7311 } 7312 } 7313 7314 /* 7315 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on 7316 * than the Chromebook setup. 7317 */ 7318 static void sbz_setup_defaults(struct hda_codec *codec) 7319 { 7320 struct ca0132_spec *spec = codec->spec; 7321 unsigned int tmp; 7322 int num_fx; 7323 int idx, i; 7324 7325 if (spec->dsp_state != DSP_DOWNLOADED) 7326 return; 7327 7328 ca0132_alt_dsp_scp_startup(codec); 7329 ca0132_alt_init_analog_mics(codec); 7330 sbz_connect_streams(codec); 7331 sbz_chipio_startup_data(codec); 7332 7333 chipio_set_stream_control(codec, 0x03, 1); 7334 chipio_set_stream_control(codec, 0x04, 1); 7335 7336 /* 7337 * Sets internal input loopback to off, used to have a switch to 7338 * enable input loopback, but turned out to be way too buggy. 7339 */ 7340 tmp = FLOAT_ONE; 7341 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 7342 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 7343 7344 /*remove DSP headroom*/ 7345 tmp = FLOAT_ZERO; 7346 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 7347 7348 /* set WUH source */ 7349 tmp = FLOAT_TWO; 7350 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 7351 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7352 7353 /* Set speaker source? */ 7354 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 7355 7356 ca0132_alt_dsp_initial_mic_setup(codec); 7357 7358 /* out, in effects + voicefx */ 7359 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 7360 for (idx = 0; idx < num_fx; idx++) { 7361 for (i = 0; i <= ca0132_effects[idx].params; i++) { 7362 dspio_set_uint_param(codec, 7363 ca0132_effects[idx].mid, 7364 ca0132_effects[idx].reqs[i], 7365 ca0132_effects[idx].def_vals[i]); 7366 } 7367 } 7368 7369 ca0132_alt_create_dummy_stream(codec); 7370 } 7371 7372 /* 7373 * Setup default parameters for the Sound BlasterX AE-5 DSP. 7374 */ 7375 static void ae5_setup_defaults(struct hda_codec *codec) 7376 { 7377 struct ca0132_spec *spec = codec->spec; 7378 unsigned int tmp; 7379 int num_fx; 7380 int idx, i; 7381 7382 if (spec->dsp_state != DSP_DOWNLOADED) 7383 return; 7384 7385 ca0132_alt_dsp_scp_startup(codec); 7386 ca0132_alt_init_analog_mics(codec); 7387 chipio_set_stream_control(codec, 0x03, 1); 7388 chipio_set_stream_control(codec, 0x04, 1); 7389 7390 /* New, unknown SCP req's */ 7391 tmp = FLOAT_ZERO; 7392 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 7393 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 7394 dspio_set_uint_param(codec, 0x80, 0x0d, tmp); 7395 dspio_set_uint_param(codec, 0x80, 0x0e, tmp); 7396 7397 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 7398 ca0113_mmio_gpio_set(codec, 0, false); 7399 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 7400 7401 /* Internal loopback off */ 7402 tmp = FLOAT_ONE; 7403 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 7404 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 7405 7406 /*remove DSP headroom*/ 7407 tmp = FLOAT_ZERO; 7408 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 7409 7410 /* set WUH source */ 7411 tmp = FLOAT_TWO; 7412 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 7413 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7414 7415 /* Set speaker source? */ 7416 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 7417 7418 ca0132_alt_dsp_initial_mic_setup(codec); 7419 ae5_post_dsp_register_set(codec); 7420 ae5_post_dsp_param_setup(codec); 7421 ae5_post_dsp_pll_setup(codec); 7422 ae5_post_dsp_stream_setup(codec); 7423 ae5_post_dsp_startup_data(codec); 7424 7425 /* out, in effects + voicefx */ 7426 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 7427 for (idx = 0; idx < num_fx; idx++) { 7428 for (i = 0; i <= ca0132_effects[idx].params; i++) { 7429 dspio_set_uint_param(codec, 7430 ca0132_effects[idx].mid, 7431 ca0132_effects[idx].reqs[i], 7432 ca0132_effects[idx].def_vals[i]); 7433 } 7434 } 7435 7436 ca0132_alt_create_dummy_stream(codec); 7437 } 7438 7439 /* 7440 * Initialization of flags in chip 7441 */ 7442 static void ca0132_init_flags(struct hda_codec *codec) 7443 { 7444 struct ca0132_spec *spec = codec->spec; 7445 7446 if (ca0132_use_alt_functions(spec)) { 7447 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1); 7448 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1); 7449 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1); 7450 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1); 7451 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1); 7452 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 7453 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0); 7454 chipio_set_control_flag(codec, 7455 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 7456 chipio_set_control_flag(codec, 7457 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1); 7458 } else { 7459 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 7460 chipio_set_control_flag(codec, 7461 CONTROL_FLAG_PORT_A_COMMON_MODE, 0); 7462 chipio_set_control_flag(codec, 7463 CONTROL_FLAG_PORT_D_COMMON_MODE, 0); 7464 chipio_set_control_flag(codec, 7465 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0); 7466 chipio_set_control_flag(codec, 7467 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 7468 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1); 7469 } 7470 } 7471 7472 /* 7473 * Initialization of parameters in chip 7474 */ 7475 static void ca0132_init_params(struct hda_codec *codec) 7476 { 7477 struct ca0132_spec *spec = codec->spec; 7478 7479 if (ca0132_use_alt_functions(spec)) { 7480 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7481 chipio_set_conn_rate(codec, 0x0B, SR_48_000); 7482 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0); 7483 chipio_set_control_param(codec, 0, 0); 7484 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 7485 } 7486 7487 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6); 7488 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6); 7489 } 7490 7491 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k) 7492 { 7493 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k); 7494 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k); 7495 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k); 7496 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k); 7497 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k); 7498 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k); 7499 7500 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7501 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7502 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7503 } 7504 7505 static bool ca0132_download_dsp_images(struct hda_codec *codec) 7506 { 7507 bool dsp_loaded = false; 7508 struct ca0132_spec *spec = codec->spec; 7509 const struct dsp_image_seg *dsp_os_image; 7510 const struct firmware *fw_entry = NULL; 7511 /* 7512 * Alternate firmwares for different variants. The Recon3Di apparently 7513 * can use the default firmware, but I'll leave the option in case 7514 * it needs it again. 7515 */ 7516 switch (ca0132_quirk(spec)) { 7517 case QUIRK_SBZ: 7518 case QUIRK_R3D: 7519 case QUIRK_AE5: 7520 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE, 7521 codec->card->dev) != 0) 7522 codec_dbg(codec, "Desktop firmware not found."); 7523 else 7524 codec_dbg(codec, "Desktop firmware selected."); 7525 break; 7526 case QUIRK_R3DI: 7527 if (request_firmware(&fw_entry, R3DI_EFX_FILE, 7528 codec->card->dev) != 0) 7529 codec_dbg(codec, "Recon3Di alt firmware not detected."); 7530 else 7531 codec_dbg(codec, "Recon3Di firmware selected."); 7532 break; 7533 default: 7534 break; 7535 } 7536 /* 7537 * Use default ctefx.bin if no alt firmware is detected, or if none 7538 * exists for your particular codec. 7539 */ 7540 if (!fw_entry) { 7541 codec_dbg(codec, "Default firmware selected."); 7542 if (request_firmware(&fw_entry, EFX_FILE, 7543 codec->card->dev) != 0) 7544 return false; 7545 } 7546 7547 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data); 7548 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) { 7549 codec_err(codec, "ca0132 DSP load image failed\n"); 7550 goto exit_download; 7551 } 7552 7553 dsp_loaded = dspload_wait_loaded(codec); 7554 7555 exit_download: 7556 release_firmware(fw_entry); 7557 7558 return dsp_loaded; 7559 } 7560 7561 static void ca0132_download_dsp(struct hda_codec *codec) 7562 { 7563 struct ca0132_spec *spec = codec->spec; 7564 7565 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP 7566 return; /* NOP */ 7567 #endif 7568 7569 if (spec->dsp_state == DSP_DOWNLOAD_FAILED) 7570 return; /* don't retry failures */ 7571 7572 chipio_enable_clocks(codec); 7573 if (spec->dsp_state != DSP_DOWNLOADED) { 7574 spec->dsp_state = DSP_DOWNLOADING; 7575 7576 if (!ca0132_download_dsp_images(codec)) 7577 spec->dsp_state = DSP_DOWNLOAD_FAILED; 7578 else 7579 spec->dsp_state = DSP_DOWNLOADED; 7580 } 7581 7582 /* For codecs using alt functions, this is already done earlier */ 7583 if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec)) 7584 ca0132_set_dsp_msr(codec, true); 7585 } 7586 7587 static void ca0132_process_dsp_response(struct hda_codec *codec, 7588 struct hda_jack_callback *callback) 7589 { 7590 struct ca0132_spec *spec = codec->spec; 7591 7592 codec_dbg(codec, "ca0132_process_dsp_response\n"); 7593 snd_hda_power_up_pm(codec); 7594 if (spec->wait_scp) { 7595 if (dspio_get_response_data(codec) >= 0) 7596 spec->wait_scp = 0; 7597 } 7598 7599 dspio_clear_response_queue(codec); 7600 snd_hda_power_down_pm(codec); 7601 } 7602 7603 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 7604 { 7605 struct ca0132_spec *spec = codec->spec; 7606 struct hda_jack_tbl *tbl; 7607 7608 /* Delay enabling the HP amp, to let the mic-detection 7609 * state machine run. 7610 */ 7611 tbl = snd_hda_jack_tbl_get(codec, cb->nid); 7612 if (tbl) 7613 tbl->block_report = 1; 7614 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500)); 7615 } 7616 7617 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 7618 { 7619 struct ca0132_spec *spec = codec->spec; 7620 7621 if (ca0132_use_alt_functions(spec)) 7622 ca0132_alt_select_in(codec); 7623 else 7624 ca0132_select_mic(codec); 7625 } 7626 7627 static void ca0132_init_unsol(struct hda_codec *codec) 7628 { 7629 struct ca0132_spec *spec = codec->spec; 7630 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback); 7631 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1, 7632 amic_callback); 7633 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP, 7634 ca0132_process_dsp_response); 7635 /* Front headphone jack detection */ 7636 if (ca0132_use_alt_functions(spec)) 7637 snd_hda_jack_detect_enable_callback(codec, 7638 spec->unsol_tag_front_hp, hp_callback); 7639 } 7640 7641 /* 7642 * Verbs tables. 7643 */ 7644 7645 /* Sends before DSP download. */ 7646 static const struct hda_verb ca0132_base_init_verbs[] = { 7647 /*enable ct extension*/ 7648 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1}, 7649 {} 7650 }; 7651 7652 /* Send at exit. */ 7653 static const struct hda_verb ca0132_base_exit_verbs[] = { 7654 /*set afg to D3*/ 7655 {0x01, AC_VERB_SET_POWER_STATE, 0x03}, 7656 /*disable ct extension*/ 7657 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0}, 7658 {} 7659 }; 7660 7661 /* Other verbs tables. Sends after DSP download. */ 7662 7663 static const struct hda_verb ca0132_init_verbs0[] = { 7664 /* chip init verbs */ 7665 {0x15, 0x70D, 0xF0}, 7666 {0x15, 0x70E, 0xFE}, 7667 {0x15, 0x707, 0x75}, 7668 {0x15, 0x707, 0xD3}, 7669 {0x15, 0x707, 0x09}, 7670 {0x15, 0x707, 0x53}, 7671 {0x15, 0x707, 0xD4}, 7672 {0x15, 0x707, 0xEF}, 7673 {0x15, 0x707, 0x75}, 7674 {0x15, 0x707, 0xD3}, 7675 {0x15, 0x707, 0x09}, 7676 {0x15, 0x707, 0x02}, 7677 {0x15, 0x707, 0x37}, 7678 {0x15, 0x707, 0x78}, 7679 {0x15, 0x53C, 0xCE}, 7680 {0x15, 0x575, 0xC9}, 7681 {0x15, 0x53D, 0xCE}, 7682 {0x15, 0x5B7, 0xC9}, 7683 {0x15, 0x70D, 0xE8}, 7684 {0x15, 0x70E, 0xFE}, 7685 {0x15, 0x707, 0x02}, 7686 {0x15, 0x707, 0x68}, 7687 {0x15, 0x707, 0x62}, 7688 {0x15, 0x53A, 0xCE}, 7689 {0x15, 0x546, 0xC9}, 7690 {0x15, 0x53B, 0xCE}, 7691 {0x15, 0x5E8, 0xC9}, 7692 {} 7693 }; 7694 7695 /* Extra init verbs for desktop cards. */ 7696 static const struct hda_verb ca0132_init_verbs1[] = { 7697 {0x15, 0x70D, 0x20}, 7698 {0x15, 0x70E, 0x19}, 7699 {0x15, 0x707, 0x00}, 7700 {0x15, 0x539, 0xCE}, 7701 {0x15, 0x546, 0xC9}, 7702 {0x15, 0x70D, 0xB7}, 7703 {0x15, 0x70E, 0x09}, 7704 {0x15, 0x707, 0x10}, 7705 {0x15, 0x70D, 0xAF}, 7706 {0x15, 0x70E, 0x09}, 7707 {0x15, 0x707, 0x01}, 7708 {0x15, 0x707, 0x05}, 7709 {0x15, 0x70D, 0x73}, 7710 {0x15, 0x70E, 0x09}, 7711 {0x15, 0x707, 0x14}, 7712 {0x15, 0x6FF, 0xC4}, 7713 {} 7714 }; 7715 7716 static void ca0132_init_chip(struct hda_codec *codec) 7717 { 7718 struct ca0132_spec *spec = codec->spec; 7719 int num_fx; 7720 int i; 7721 unsigned int on; 7722 7723 mutex_init(&spec->chipio_mutex); 7724 7725 spec->cur_out_type = SPEAKER_OUT; 7726 if (!ca0132_use_alt_functions(spec)) 7727 spec->cur_mic_type = DIGITAL_MIC; 7728 else 7729 spec->cur_mic_type = REAR_MIC; 7730 7731 spec->cur_mic_boost = 0; 7732 7733 for (i = 0; i < VNODES_COUNT; i++) { 7734 spec->vnode_lvol[i] = 0x5a; 7735 spec->vnode_rvol[i] = 0x5a; 7736 spec->vnode_lswitch[i] = 0; 7737 spec->vnode_rswitch[i] = 0; 7738 } 7739 7740 /* 7741 * Default states for effects are in ca0132_effects[]. 7742 */ 7743 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 7744 for (i = 0; i < num_fx; i++) { 7745 on = (unsigned int)ca0132_effects[i].reqs[0]; 7746 spec->effects_switch[i] = on ? 1 : 0; 7747 } 7748 /* 7749 * Sets defaults for the effect slider controls, only for alternative 7750 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz. 7751 */ 7752 if (ca0132_use_alt_controls(spec)) { 7753 spec->xbass_xover_freq = 8; 7754 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++) 7755 spec->fx_ctl_val[i] = effect_slider_defaults[i]; 7756 } 7757 7758 spec->voicefx_val = 0; 7759 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1; 7760 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0; 7761 7762 /* 7763 * The ZxR doesn't have a front panel header, and it's line-in is on 7764 * the daughter board. So, there is no input enum control, and we need 7765 * to make sure that spec->in_enum_val is set properly. 7766 */ 7767 if (ca0132_quirk(spec) == QUIRK_ZXR) 7768 spec->in_enum_val = REAR_MIC; 7769 7770 #ifdef ENABLE_TUNING_CONTROLS 7771 ca0132_init_tuning_defaults(codec); 7772 #endif 7773 } 7774 7775 /* 7776 * Recon3Di exit specific commands. 7777 */ 7778 /* prevents popping noise on shutdown */ 7779 static void r3di_gpio_shutdown(struct hda_codec *codec) 7780 { 7781 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00); 7782 } 7783 7784 /* 7785 * Sound Blaster Z exit specific commands. 7786 */ 7787 static void sbz_region2_exit(struct hda_codec *codec) 7788 { 7789 struct ca0132_spec *spec = codec->spec; 7790 unsigned int i; 7791 7792 for (i = 0; i < 4; i++) 7793 writeb(0x0, spec->mem_base + 0x100); 7794 for (i = 0; i < 8; i++) 7795 writeb(0xb3, spec->mem_base + 0x304); 7796 7797 ca0113_mmio_gpio_set(codec, 0, false); 7798 ca0113_mmio_gpio_set(codec, 1, false); 7799 ca0113_mmio_gpio_set(codec, 4, true); 7800 ca0113_mmio_gpio_set(codec, 5, false); 7801 ca0113_mmio_gpio_set(codec, 7, false); 7802 } 7803 7804 static void sbz_set_pin_ctl_default(struct hda_codec *codec) 7805 { 7806 static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13}; 7807 unsigned int i; 7808 7809 snd_hda_codec_write(codec, 0x11, 0, 7810 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40); 7811 7812 for (i = 0; i < ARRAY_SIZE(pins); i++) 7813 snd_hda_codec_write(codec, pins[i], 0, 7814 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00); 7815 } 7816 7817 static void ca0132_clear_unsolicited(struct hda_codec *codec) 7818 { 7819 static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13}; 7820 unsigned int i; 7821 7822 for (i = 0; i < ARRAY_SIZE(pins); i++) { 7823 snd_hda_codec_write(codec, pins[i], 0, 7824 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00); 7825 } 7826 } 7827 7828 /* On shutdown, sends commands in sets of three */ 7829 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir, 7830 int mask, int data) 7831 { 7832 if (dir >= 0) 7833 snd_hda_codec_write(codec, 0x01, 0, 7834 AC_VERB_SET_GPIO_DIRECTION, dir); 7835 if (mask >= 0) 7836 snd_hda_codec_write(codec, 0x01, 0, 7837 AC_VERB_SET_GPIO_MASK, mask); 7838 7839 if (data >= 0) 7840 snd_hda_codec_write(codec, 0x01, 0, 7841 AC_VERB_SET_GPIO_DATA, data); 7842 } 7843 7844 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec) 7845 { 7846 static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01}; 7847 unsigned int i; 7848 7849 for (i = 0; i < ARRAY_SIZE(pins); i++) 7850 snd_hda_codec_write(codec, pins[i], 0, 7851 AC_VERB_SET_POWER_STATE, 0x03); 7852 } 7853 7854 static void sbz_exit_chip(struct hda_codec *codec) 7855 { 7856 chipio_set_stream_control(codec, 0x03, 0); 7857 chipio_set_stream_control(codec, 0x04, 0); 7858 7859 /* Mess with GPIO */ 7860 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1); 7861 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05); 7862 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01); 7863 7864 chipio_set_stream_control(codec, 0x14, 0); 7865 chipio_set_stream_control(codec, 0x0C, 0); 7866 7867 chipio_set_conn_rate(codec, 0x41, SR_192_000); 7868 chipio_set_conn_rate(codec, 0x91, SR_192_000); 7869 7870 chipio_write(codec, 0x18a020, 0x00000083); 7871 7872 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03); 7873 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07); 7874 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06); 7875 7876 chipio_set_stream_control(codec, 0x0C, 0); 7877 7878 chipio_set_control_param(codec, 0x0D, 0x24); 7879 7880 ca0132_clear_unsolicited(codec); 7881 sbz_set_pin_ctl_default(codec); 7882 7883 snd_hda_codec_write(codec, 0x0B, 0, 7884 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 7885 7886 sbz_region2_exit(codec); 7887 } 7888 7889 static void r3d_exit_chip(struct hda_codec *codec) 7890 { 7891 ca0132_clear_unsolicited(codec); 7892 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 7893 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b); 7894 } 7895 7896 static void ae5_exit_chip(struct hda_codec *codec) 7897 { 7898 chipio_set_stream_control(codec, 0x03, 0); 7899 chipio_set_stream_control(codec, 0x04, 0); 7900 7901 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 7902 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7903 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7904 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 7905 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 7906 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00); 7907 ca0113_mmio_gpio_set(codec, 0, false); 7908 ca0113_mmio_gpio_set(codec, 1, false); 7909 7910 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 7911 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 7912 7913 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 7914 7915 chipio_set_stream_control(codec, 0x18, 0); 7916 chipio_set_stream_control(codec, 0x0c, 0); 7917 7918 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83); 7919 } 7920 7921 static void zxr_exit_chip(struct hda_codec *codec) 7922 { 7923 chipio_set_stream_control(codec, 0x03, 0); 7924 chipio_set_stream_control(codec, 0x04, 0); 7925 chipio_set_stream_control(codec, 0x14, 0); 7926 chipio_set_stream_control(codec, 0x0C, 0); 7927 7928 chipio_set_conn_rate(codec, 0x41, SR_192_000); 7929 chipio_set_conn_rate(codec, 0x91, SR_192_000); 7930 7931 chipio_write(codec, 0x18a020, 0x00000083); 7932 7933 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 7934 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 7935 7936 ca0132_clear_unsolicited(codec); 7937 sbz_set_pin_ctl_default(codec); 7938 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00); 7939 7940 ca0113_mmio_gpio_set(codec, 5, false); 7941 ca0113_mmio_gpio_set(codec, 2, false); 7942 ca0113_mmio_gpio_set(codec, 3, false); 7943 ca0113_mmio_gpio_set(codec, 0, false); 7944 ca0113_mmio_gpio_set(codec, 4, true); 7945 ca0113_mmio_gpio_set(codec, 0, true); 7946 ca0113_mmio_gpio_set(codec, 5, true); 7947 ca0113_mmio_gpio_set(codec, 2, false); 7948 ca0113_mmio_gpio_set(codec, 3, false); 7949 } 7950 7951 static void ca0132_exit_chip(struct hda_codec *codec) 7952 { 7953 /* put any chip cleanup stuffs here. */ 7954 7955 if (dspload_is_loaded(codec)) 7956 dsp_reset(codec); 7957 } 7958 7959 /* 7960 * This fixes a problem that was hard to reproduce. Very rarely, I would 7961 * boot up, and there would be no sound, but the DSP indicated it had loaded 7962 * properly. I did a few memory dumps to see if anything was different, and 7963 * there were a few areas of memory uninitialized with a1a2a3a4. This function 7964 * checks if those areas are uninitialized, and if they are, it'll attempt to 7965 * reload the card 3 times. Usually it fixes by the second. 7966 */ 7967 static void sbz_dsp_startup_check(struct hda_codec *codec) 7968 { 7969 struct ca0132_spec *spec = codec->spec; 7970 unsigned int dsp_data_check[4]; 7971 unsigned int cur_address = 0x390; 7972 unsigned int i; 7973 unsigned int failure = 0; 7974 unsigned int reload = 3; 7975 7976 if (spec->startup_check_entered) 7977 return; 7978 7979 spec->startup_check_entered = true; 7980 7981 for (i = 0; i < 4; i++) { 7982 chipio_read(codec, cur_address, &dsp_data_check[i]); 7983 cur_address += 0x4; 7984 } 7985 for (i = 0; i < 4; i++) { 7986 if (dsp_data_check[i] == 0xa1a2a3a4) 7987 failure = 1; 7988 } 7989 7990 codec_dbg(codec, "Startup Check: %d ", failure); 7991 if (failure) 7992 codec_info(codec, "DSP not initialized properly. Attempting to fix."); 7993 /* 7994 * While the failure condition is true, and we haven't reached our 7995 * three reload limit, continue trying to reload the driver and 7996 * fix the issue. 7997 */ 7998 while (failure && (reload != 0)) { 7999 codec_info(codec, "Reloading... Tries left: %d", reload); 8000 sbz_exit_chip(codec); 8001 spec->dsp_state = DSP_DOWNLOAD_INIT; 8002 codec->patch_ops.init(codec); 8003 failure = 0; 8004 for (i = 0; i < 4; i++) { 8005 chipio_read(codec, cur_address, &dsp_data_check[i]); 8006 cur_address += 0x4; 8007 } 8008 for (i = 0; i < 4; i++) { 8009 if (dsp_data_check[i] == 0xa1a2a3a4) 8010 failure = 1; 8011 } 8012 reload--; 8013 } 8014 8015 if (!failure && reload < 3) 8016 codec_info(codec, "DSP fixed."); 8017 8018 if (!failure) 8019 return; 8020 8021 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory."); 8022 } 8023 8024 /* 8025 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add 8026 * extra precision for decibel values. If you had the dB value in floating point 8027 * you would take the value after the decimal point, multiply by 64, and divide 8028 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to 8029 * implement fixed point or floating point dB volumes. For now, I'll set them 8030 * to 0 just incase a value has lingered from a boot into Windows. 8031 */ 8032 static void ca0132_alt_vol_setup(struct hda_codec *codec) 8033 { 8034 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00); 8035 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00); 8036 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00); 8037 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00); 8038 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00); 8039 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00); 8040 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00); 8041 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00); 8042 } 8043 8044 /* 8045 * Extra commands that don't really fit anywhere else. 8046 */ 8047 static void sbz_pre_dsp_setup(struct hda_codec *codec) 8048 { 8049 struct ca0132_spec *spec = codec->spec; 8050 8051 writel(0x00820680, spec->mem_base + 0x01C); 8052 writel(0x00820680, spec->mem_base + 0x01C); 8053 8054 chipio_write(codec, 0x18b0a4, 0x000000c2); 8055 8056 snd_hda_codec_write(codec, 0x11, 0, 8057 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 8058 } 8059 8060 static void r3d_pre_dsp_setup(struct hda_codec *codec) 8061 { 8062 chipio_write(codec, 0x18b0a4, 0x000000c2); 8063 8064 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8065 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E); 8066 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8067 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C); 8068 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8069 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B); 8070 8071 snd_hda_codec_write(codec, 0x11, 0, 8072 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 8073 } 8074 8075 static void r3di_pre_dsp_setup(struct hda_codec *codec) 8076 { 8077 chipio_write(codec, 0x18b0a4, 0x000000c2); 8078 8079 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8080 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E); 8081 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8082 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C); 8083 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8084 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B); 8085 8086 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8087 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); 8088 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8089 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 8090 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8091 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 8092 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8093 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40); 8094 8095 snd_hda_codec_write(codec, 0x11, 0, 8096 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04); 8097 } 8098 8099 /* 8100 * These are sent before the DSP is downloaded. Not sure 8101 * what they do, or if they're necessary. Could possibly 8102 * be removed. Figure they're better to leave in. 8103 */ 8104 static void ca0132_mmio_init(struct hda_codec *codec) 8105 { 8106 struct ca0132_spec *spec = codec->spec; 8107 8108 if (ca0132_quirk(spec) == QUIRK_AE5) 8109 writel(0x00000001, spec->mem_base + 0x400); 8110 else 8111 writel(0x00000000, spec->mem_base + 0x400); 8112 8113 if (ca0132_quirk(spec) == QUIRK_AE5) 8114 writel(0x00000001, spec->mem_base + 0x408); 8115 else 8116 writel(0x00000000, spec->mem_base + 0x408); 8117 8118 if (ca0132_quirk(spec) == QUIRK_AE5) 8119 writel(0x00000001, spec->mem_base + 0x40c); 8120 else 8121 writel(0x00000000, spec->mem_base + 0x40C); 8122 8123 if (ca0132_quirk(spec) == QUIRK_ZXR) 8124 writel(0x00880640, spec->mem_base + 0x01C); 8125 else 8126 writel(0x00880680, spec->mem_base + 0x01C); 8127 8128 if (ca0132_quirk(spec) == QUIRK_AE5) 8129 writel(0x00000080, spec->mem_base + 0xC0C); 8130 else 8131 writel(0x00000083, spec->mem_base + 0xC0C); 8132 8133 writel(0x00000030, spec->mem_base + 0xC00); 8134 writel(0x00000000, spec->mem_base + 0xC04); 8135 8136 if (ca0132_quirk(spec) == QUIRK_AE5) 8137 writel(0x00000000, spec->mem_base + 0xC0C); 8138 else 8139 writel(0x00000003, spec->mem_base + 0xC0C); 8140 8141 writel(0x00000003, spec->mem_base + 0xC0C); 8142 writel(0x00000003, spec->mem_base + 0xC0C); 8143 writel(0x00000003, spec->mem_base + 0xC0C); 8144 8145 if (ca0132_quirk(spec) == QUIRK_AE5) 8146 writel(0x00000001, spec->mem_base + 0xC08); 8147 else 8148 writel(0x000000C1, spec->mem_base + 0xC08); 8149 8150 writel(0x000000F1, spec->mem_base + 0xC08); 8151 writel(0x00000001, spec->mem_base + 0xC08); 8152 writel(0x000000C7, spec->mem_base + 0xC08); 8153 writel(0x000000C1, spec->mem_base + 0xC08); 8154 writel(0x00000080, spec->mem_base + 0xC04); 8155 8156 if (ca0132_quirk(spec) == QUIRK_AE5) { 8157 writel(0x00000000, spec->mem_base + 0x42c); 8158 writel(0x00000000, spec->mem_base + 0x46c); 8159 writel(0x00000000, spec->mem_base + 0x4ac); 8160 writel(0x00000000, spec->mem_base + 0x4ec); 8161 writel(0x00000000, spec->mem_base + 0x43c); 8162 writel(0x00000000, spec->mem_base + 0x47c); 8163 writel(0x00000000, spec->mem_base + 0x4bc); 8164 writel(0x00000000, spec->mem_base + 0x4fc); 8165 writel(0x00000600, spec->mem_base + 0x100); 8166 writel(0x00000014, spec->mem_base + 0x410); 8167 writel(0x0000060f, spec->mem_base + 0x100); 8168 writel(0x0000070f, spec->mem_base + 0x100); 8169 writel(0x00000aff, spec->mem_base + 0x830); 8170 writel(0x00000000, spec->mem_base + 0x86c); 8171 writel(0x0000006b, spec->mem_base + 0x800); 8172 writel(0x00000001, spec->mem_base + 0x86c); 8173 writel(0x0000006b, spec->mem_base + 0x800); 8174 writel(0x00000057, spec->mem_base + 0x804); 8175 writel(0x00800000, spec->mem_base + 0x20c); 8176 } 8177 } 8178 8179 /* 8180 * This function writes to some SFR's, does some region2 writes, and then 8181 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does 8182 * what it does. 8183 */ 8184 static void ae5_register_set(struct hda_codec *codec) 8185 { 8186 struct ca0132_spec *spec = codec->spec; 8187 8188 chipio_8051_write_direct(codec, 0x93, 0x10); 8189 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8190 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44); 8191 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8192 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2); 8193 8194 writeb(0x0f, spec->mem_base + 0x304); 8195 writeb(0x0f, spec->mem_base + 0x304); 8196 writeb(0x0f, spec->mem_base + 0x304); 8197 writeb(0x0f, spec->mem_base + 0x304); 8198 writeb(0x0e, spec->mem_base + 0x100); 8199 writeb(0x1f, spec->mem_base + 0x304); 8200 writeb(0x0c, spec->mem_base + 0x100); 8201 writeb(0x3f, spec->mem_base + 0x304); 8202 writeb(0x08, spec->mem_base + 0x100); 8203 writeb(0x7f, spec->mem_base + 0x304); 8204 writeb(0x00, spec->mem_base + 0x100); 8205 writeb(0xff, spec->mem_base + 0x304); 8206 8207 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 8208 8209 chipio_8051_write_direct(codec, 0x90, 0x00); 8210 chipio_8051_write_direct(codec, 0x90, 0x10); 8211 8212 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8213 8214 chipio_write(codec, 0x18b0a4, 0x000000c2); 8215 8216 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00); 8217 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00); 8218 } 8219 8220 /* 8221 * Extra init functions for alternative ca0132 codecs. Done 8222 * here so they don't clutter up the main ca0132_init function 8223 * anymore than they have to. 8224 */ 8225 static void ca0132_alt_init(struct hda_codec *codec) 8226 { 8227 struct ca0132_spec *spec = codec->spec; 8228 8229 ca0132_alt_vol_setup(codec); 8230 8231 switch (ca0132_quirk(spec)) { 8232 case QUIRK_SBZ: 8233 codec_dbg(codec, "SBZ alt_init"); 8234 ca0132_gpio_init(codec); 8235 sbz_pre_dsp_setup(codec); 8236 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8237 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 8238 break; 8239 case QUIRK_R3DI: 8240 codec_dbg(codec, "R3DI alt_init"); 8241 ca0132_gpio_init(codec); 8242 ca0132_gpio_setup(codec); 8243 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING); 8244 r3di_pre_dsp_setup(codec); 8245 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8246 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4); 8247 break; 8248 case QUIRK_R3D: 8249 r3d_pre_dsp_setup(codec); 8250 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8251 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 8252 break; 8253 case QUIRK_AE5: 8254 ca0132_gpio_init(codec); 8255 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8256 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49); 8257 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8258 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88); 8259 chipio_write(codec, 0x18b030, 0x00000020); 8260 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8261 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 8262 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 8263 break; 8264 case QUIRK_ZXR: 8265 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8266 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 8267 break; 8268 default: 8269 break; 8270 } 8271 } 8272 8273 static int ca0132_init(struct hda_codec *codec) 8274 { 8275 struct ca0132_spec *spec = codec->spec; 8276 struct auto_pin_cfg *cfg = &spec->autocfg; 8277 int i; 8278 bool dsp_loaded; 8279 8280 /* 8281 * If the DSP is already downloaded, and init has been entered again, 8282 * there's only two reasons for it. One, the codec has awaken from a 8283 * suspended state, and in that case dspload_is_loaded will return 8284 * false, and the init will be ran again. The other reason it gets 8285 * re entered is on startup for some reason it triggers a suspend and 8286 * resume state. In this case, it will check if the DSP is downloaded, 8287 * and not run the init function again. For codecs using alt_functions, 8288 * it will check if the DSP is loaded properly. 8289 */ 8290 if (spec->dsp_state == DSP_DOWNLOADED) { 8291 dsp_loaded = dspload_is_loaded(codec); 8292 if (!dsp_loaded) { 8293 spec->dsp_reload = true; 8294 spec->dsp_state = DSP_DOWNLOAD_INIT; 8295 } else { 8296 if (ca0132_quirk(spec) == QUIRK_SBZ) 8297 sbz_dsp_startup_check(codec); 8298 return 0; 8299 } 8300 } 8301 8302 if (spec->dsp_state != DSP_DOWNLOAD_FAILED) 8303 spec->dsp_state = DSP_DOWNLOAD_INIT; 8304 spec->curr_chip_addx = INVALID_CHIP_ADDRESS; 8305 8306 if (ca0132_use_pci_mmio(spec)) 8307 ca0132_mmio_init(codec); 8308 8309 snd_hda_power_up_pm(codec); 8310 8311 if (ca0132_quirk(spec) == QUIRK_AE5) 8312 ae5_register_set(codec); 8313 8314 ca0132_init_unsol(codec); 8315 ca0132_init_params(codec); 8316 ca0132_init_flags(codec); 8317 8318 snd_hda_sequence_write(codec, spec->base_init_verbs); 8319 8320 if (ca0132_use_alt_functions(spec)) 8321 ca0132_alt_init(codec); 8322 8323 ca0132_download_dsp(codec); 8324 8325 ca0132_refresh_widget_caps(codec); 8326 8327 switch (ca0132_quirk(spec)) { 8328 case QUIRK_R3DI: 8329 case QUIRK_R3D: 8330 r3d_setup_defaults(codec); 8331 break; 8332 case QUIRK_SBZ: 8333 case QUIRK_ZXR: 8334 sbz_setup_defaults(codec); 8335 break; 8336 case QUIRK_AE5: 8337 ae5_setup_defaults(codec); 8338 break; 8339 default: 8340 ca0132_setup_defaults(codec); 8341 ca0132_init_analog_mic2(codec); 8342 ca0132_init_dmic(codec); 8343 break; 8344 } 8345 8346 for (i = 0; i < spec->num_outputs; i++) 8347 init_output(codec, spec->out_pins[i], spec->dacs[0]); 8348 8349 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 8350 8351 for (i = 0; i < spec->num_inputs; i++) 8352 init_input(codec, spec->input_pins[i], spec->adcs[i]); 8353 8354 init_input(codec, cfg->dig_in_pin, spec->dig_in); 8355 8356 if (!ca0132_use_alt_functions(spec)) { 8357 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8358 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8359 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D); 8360 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8361 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20); 8362 } 8363 8364 if (ca0132_quirk(spec) == QUIRK_SBZ) 8365 ca0132_gpio_setup(codec); 8366 8367 snd_hda_sequence_write(codec, spec->spec_init_verbs); 8368 if (ca0132_use_alt_functions(spec)) { 8369 ca0132_alt_select_out(codec); 8370 ca0132_alt_select_in(codec); 8371 } else { 8372 ca0132_select_out(codec); 8373 ca0132_select_mic(codec); 8374 } 8375 8376 snd_hda_jack_report_sync(codec); 8377 8378 /* 8379 * Re set the PlayEnhancement switch on a resume event, because the 8380 * controls will not be reloaded. 8381 */ 8382 if (spec->dsp_reload) { 8383 spec->dsp_reload = false; 8384 ca0132_pe_switch_set(codec); 8385 } 8386 8387 snd_hda_power_down_pm(codec); 8388 8389 return 0; 8390 } 8391 8392 static int dbpro_init(struct hda_codec *codec) 8393 { 8394 struct ca0132_spec *spec = codec->spec; 8395 struct auto_pin_cfg *cfg = &spec->autocfg; 8396 unsigned int i; 8397 8398 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 8399 init_input(codec, cfg->dig_in_pin, spec->dig_in); 8400 8401 for (i = 0; i < spec->num_inputs; i++) 8402 init_input(codec, spec->input_pins[i], spec->adcs[i]); 8403 8404 return 0; 8405 } 8406 8407 static void ca0132_free(struct hda_codec *codec) 8408 { 8409 struct ca0132_spec *spec = codec->spec; 8410 8411 cancel_delayed_work_sync(&spec->unsol_hp_work); 8412 snd_hda_power_up(codec); 8413 switch (ca0132_quirk(spec)) { 8414 case QUIRK_SBZ: 8415 sbz_exit_chip(codec); 8416 break; 8417 case QUIRK_ZXR: 8418 zxr_exit_chip(codec); 8419 break; 8420 case QUIRK_R3D: 8421 r3d_exit_chip(codec); 8422 break; 8423 case QUIRK_AE5: 8424 ae5_exit_chip(codec); 8425 break; 8426 case QUIRK_R3DI: 8427 r3di_gpio_shutdown(codec); 8428 break; 8429 default: 8430 break; 8431 } 8432 8433 snd_hda_sequence_write(codec, spec->base_exit_verbs); 8434 ca0132_exit_chip(codec); 8435 8436 snd_hda_power_down(codec); 8437 #ifdef CONFIG_PCI 8438 if (spec->mem_base) 8439 pci_iounmap(codec->bus->pci, spec->mem_base); 8440 #endif 8441 kfree(spec->spec_init_verbs); 8442 kfree(codec->spec); 8443 } 8444 8445 static void dbpro_free(struct hda_codec *codec) 8446 { 8447 struct ca0132_spec *spec = codec->spec; 8448 8449 zxr_dbpro_power_state_shutdown(codec); 8450 8451 kfree(spec->spec_init_verbs); 8452 kfree(codec->spec); 8453 } 8454 8455 static void ca0132_reboot_notify(struct hda_codec *codec) 8456 { 8457 codec->patch_ops.free(codec); 8458 } 8459 8460 #ifdef CONFIG_PM 8461 static int ca0132_suspend(struct hda_codec *codec) 8462 { 8463 struct ca0132_spec *spec = codec->spec; 8464 8465 cancel_delayed_work_sync(&spec->unsol_hp_work); 8466 return 0; 8467 } 8468 #endif 8469 8470 static const struct hda_codec_ops ca0132_patch_ops = { 8471 .build_controls = ca0132_build_controls, 8472 .build_pcms = ca0132_build_pcms, 8473 .init = ca0132_init, 8474 .free = ca0132_free, 8475 .unsol_event = snd_hda_jack_unsol_event, 8476 #ifdef CONFIG_PM 8477 .suspend = ca0132_suspend, 8478 #endif 8479 .reboot_notify = ca0132_reboot_notify, 8480 }; 8481 8482 static const struct hda_codec_ops dbpro_patch_ops = { 8483 .build_controls = dbpro_build_controls, 8484 .build_pcms = dbpro_build_pcms, 8485 .init = dbpro_init, 8486 .free = dbpro_free, 8487 }; 8488 8489 static void ca0132_config(struct hda_codec *codec) 8490 { 8491 struct ca0132_spec *spec = codec->spec; 8492 8493 spec->dacs[0] = 0x2; 8494 spec->dacs[1] = 0x3; 8495 spec->dacs[2] = 0x4; 8496 8497 spec->multiout.dac_nids = spec->dacs; 8498 spec->multiout.num_dacs = 3; 8499 8500 if (!ca0132_use_alt_functions(spec)) 8501 spec->multiout.max_channels = 2; 8502 else 8503 spec->multiout.max_channels = 6; 8504 8505 switch (ca0132_quirk(spec)) { 8506 case QUIRK_ALIENWARE: 8507 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__); 8508 snd_hda_apply_pincfgs(codec, alienware_pincfgs); 8509 break; 8510 case QUIRK_SBZ: 8511 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__); 8512 snd_hda_apply_pincfgs(codec, sbz_pincfgs); 8513 break; 8514 case QUIRK_ZXR: 8515 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__); 8516 snd_hda_apply_pincfgs(codec, zxr_pincfgs); 8517 break; 8518 case QUIRK_R3D: 8519 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__); 8520 snd_hda_apply_pincfgs(codec, r3d_pincfgs); 8521 break; 8522 case QUIRK_R3DI: 8523 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__); 8524 snd_hda_apply_pincfgs(codec, r3di_pincfgs); 8525 break; 8526 case QUIRK_AE5: 8527 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__); 8528 snd_hda_apply_pincfgs(codec, ae5_pincfgs); 8529 break; 8530 default: 8531 break; 8532 } 8533 8534 switch (ca0132_quirk(spec)) { 8535 case QUIRK_ALIENWARE: 8536 spec->num_outputs = 2; 8537 spec->out_pins[0] = 0x0b; /* speaker out */ 8538 spec->out_pins[1] = 0x0f; 8539 spec->shared_out_nid = 0x2; 8540 spec->unsol_tag_hp = 0x0f; 8541 8542 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 8543 spec->adcs[1] = 0x8; /* analog mic2 */ 8544 spec->adcs[2] = 0xa; /* what u hear */ 8545 8546 spec->num_inputs = 3; 8547 spec->input_pins[0] = 0x12; 8548 spec->input_pins[1] = 0x11; 8549 spec->input_pins[2] = 0x13; 8550 spec->shared_mic_nid = 0x7; 8551 spec->unsol_tag_amic1 = 0x11; 8552 break; 8553 case QUIRK_SBZ: 8554 case QUIRK_R3D: 8555 spec->num_outputs = 2; 8556 spec->out_pins[0] = 0x0B; /* Line out */ 8557 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 8558 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 8559 spec->out_pins[3] = 0x11; /* Rear surround */ 8560 spec->shared_out_nid = 0x2; 8561 spec->unsol_tag_hp = spec->out_pins[1]; 8562 spec->unsol_tag_front_hp = spec->out_pins[2]; 8563 8564 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 8565 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 8566 spec->adcs[2] = 0xa; /* what u hear */ 8567 8568 spec->num_inputs = 2; 8569 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 8570 spec->input_pins[1] = 0x13; /* What U Hear */ 8571 spec->shared_mic_nid = 0x7; 8572 spec->unsol_tag_amic1 = spec->input_pins[0]; 8573 8574 /* SPDIF I/O */ 8575 spec->dig_out = 0x05; 8576 spec->multiout.dig_out_nid = spec->dig_out; 8577 spec->dig_in = 0x09; 8578 break; 8579 case QUIRK_ZXR: 8580 spec->num_outputs = 2; 8581 spec->out_pins[0] = 0x0B; /* Line out */ 8582 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 8583 spec->out_pins[2] = 0x10; /* Center/LFE */ 8584 spec->out_pins[3] = 0x11; /* Rear surround */ 8585 spec->shared_out_nid = 0x2; 8586 spec->unsol_tag_hp = spec->out_pins[1]; 8587 spec->unsol_tag_front_hp = spec->out_pins[2]; 8588 8589 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 8590 spec->adcs[1] = 0x8; /* Not connected, no front mic */ 8591 spec->adcs[2] = 0xa; /* what u hear */ 8592 8593 spec->num_inputs = 2; 8594 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 8595 spec->input_pins[1] = 0x13; /* What U Hear */ 8596 spec->shared_mic_nid = 0x7; 8597 spec->unsol_tag_amic1 = spec->input_pins[0]; 8598 break; 8599 case QUIRK_ZXR_DBPRO: 8600 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */ 8601 8602 spec->num_inputs = 1; 8603 spec->input_pins[0] = 0x11; /* RCA Line-in */ 8604 8605 spec->dig_out = 0x05; 8606 spec->multiout.dig_out_nid = spec->dig_out; 8607 8608 spec->dig_in = 0x09; 8609 break; 8610 case QUIRK_AE5: 8611 spec->num_outputs = 2; 8612 spec->out_pins[0] = 0x0B; /* Line out */ 8613 spec->out_pins[1] = 0x11; /* Rear headphone out */ 8614 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 8615 spec->out_pins[3] = 0x0F; /* Rear surround */ 8616 spec->shared_out_nid = 0x2; 8617 spec->unsol_tag_hp = spec->out_pins[1]; 8618 spec->unsol_tag_front_hp = spec->out_pins[2]; 8619 8620 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 8621 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 8622 spec->adcs[2] = 0xa; /* what u hear */ 8623 8624 spec->num_inputs = 2; 8625 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 8626 spec->input_pins[1] = 0x13; /* What U Hear */ 8627 spec->shared_mic_nid = 0x7; 8628 spec->unsol_tag_amic1 = spec->input_pins[0]; 8629 8630 /* SPDIF I/O */ 8631 spec->dig_out = 0x05; 8632 spec->multiout.dig_out_nid = spec->dig_out; 8633 break; 8634 case QUIRK_R3DI: 8635 spec->num_outputs = 2; 8636 spec->out_pins[0] = 0x0B; /* Line out */ 8637 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 8638 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 8639 spec->out_pins[3] = 0x11; /* Rear surround */ 8640 spec->shared_out_nid = 0x2; 8641 spec->unsol_tag_hp = spec->out_pins[1]; 8642 spec->unsol_tag_front_hp = spec->out_pins[2]; 8643 8644 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */ 8645 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */ 8646 spec->adcs[2] = 0x0a; /* what u hear */ 8647 8648 spec->num_inputs = 2; 8649 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 8650 spec->input_pins[1] = 0x13; /* What U Hear */ 8651 spec->shared_mic_nid = 0x7; 8652 spec->unsol_tag_amic1 = spec->input_pins[0]; 8653 8654 /* SPDIF I/O */ 8655 spec->dig_out = 0x05; 8656 spec->multiout.dig_out_nid = spec->dig_out; 8657 break; 8658 default: 8659 spec->num_outputs = 2; 8660 spec->out_pins[0] = 0x0b; /* speaker out */ 8661 spec->out_pins[1] = 0x10; /* headphone out */ 8662 spec->shared_out_nid = 0x2; 8663 spec->unsol_tag_hp = spec->out_pins[1]; 8664 8665 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 8666 spec->adcs[1] = 0x8; /* analog mic2 */ 8667 spec->adcs[2] = 0xa; /* what u hear */ 8668 8669 spec->num_inputs = 3; 8670 spec->input_pins[0] = 0x12; 8671 spec->input_pins[1] = 0x11; 8672 spec->input_pins[2] = 0x13; 8673 spec->shared_mic_nid = 0x7; 8674 spec->unsol_tag_amic1 = spec->input_pins[0]; 8675 8676 /* SPDIF I/O */ 8677 spec->dig_out = 0x05; 8678 spec->multiout.dig_out_nid = spec->dig_out; 8679 spec->dig_in = 0x09; 8680 break; 8681 } 8682 } 8683 8684 static int ca0132_prepare_verbs(struct hda_codec *codec) 8685 { 8686 /* Verbs + terminator (an empty element) */ 8687 #define NUM_SPEC_VERBS 2 8688 struct ca0132_spec *spec = codec->spec; 8689 8690 spec->chip_init_verbs = ca0132_init_verbs0; 8691 /* 8692 * Since desktop cards use pci_mmio, this can be used to determine 8693 * whether or not to use these verbs instead of a separate bool. 8694 */ 8695 if (ca0132_use_pci_mmio(spec)) 8696 spec->desktop_init_verbs = ca0132_init_verbs1; 8697 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS, 8698 sizeof(struct hda_verb), 8699 GFP_KERNEL); 8700 if (!spec->spec_init_verbs) 8701 return -ENOMEM; 8702 8703 /* config EAPD */ 8704 spec->spec_init_verbs[0].nid = 0x0b; 8705 spec->spec_init_verbs[0].param = 0x78D; 8706 spec->spec_init_verbs[0].verb = 0x00; 8707 8708 /* Previously commented configuration */ 8709 /* 8710 spec->spec_init_verbs[2].nid = 0x0b; 8711 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE; 8712 spec->spec_init_verbs[2].verb = 0x02; 8713 8714 spec->spec_init_verbs[3].nid = 0x10; 8715 spec->spec_init_verbs[3].param = 0x78D; 8716 spec->spec_init_verbs[3].verb = 0x02; 8717 8718 spec->spec_init_verbs[4].nid = 0x10; 8719 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE; 8720 spec->spec_init_verbs[4].verb = 0x02; 8721 */ 8722 8723 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */ 8724 return 0; 8725 } 8726 8727 /* 8728 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular 8729 * Sound Blaster Z cards. However, they have different HDA codec subsystem 8730 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro 8731 * daughter boards ID. 8732 */ 8733 static void sbz_detect_quirk(struct hda_codec *codec) 8734 { 8735 struct ca0132_spec *spec = codec->spec; 8736 8737 switch (codec->core.subsystem_id) { 8738 case 0x11020033: 8739 spec->quirk = QUIRK_ZXR; 8740 break; 8741 case 0x1102003f: 8742 spec->quirk = QUIRK_ZXR_DBPRO; 8743 break; 8744 default: 8745 spec->quirk = QUIRK_SBZ; 8746 break; 8747 } 8748 } 8749 8750 static int patch_ca0132(struct hda_codec *codec) 8751 { 8752 struct ca0132_spec *spec; 8753 int err; 8754 const struct snd_pci_quirk *quirk; 8755 8756 codec_dbg(codec, "patch_ca0132\n"); 8757 8758 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 8759 if (!spec) 8760 return -ENOMEM; 8761 codec->spec = spec; 8762 spec->codec = codec; 8763 8764 /* Detect codec quirk */ 8765 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks); 8766 if (quirk) 8767 spec->quirk = quirk->value; 8768 else 8769 spec->quirk = QUIRK_NONE; 8770 if (ca0132_quirk(spec) == QUIRK_SBZ) 8771 sbz_detect_quirk(codec); 8772 8773 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO) 8774 codec->patch_ops = dbpro_patch_ops; 8775 else 8776 codec->patch_ops = ca0132_patch_ops; 8777 8778 codec->pcm_format_first = 1; 8779 codec->no_sticky_stream = 1; 8780 8781 8782 spec->dsp_state = DSP_DOWNLOAD_INIT; 8783 spec->num_mixers = 1; 8784 8785 /* Set which mixers each quirk uses. */ 8786 switch (ca0132_quirk(spec)) { 8787 case QUIRK_SBZ: 8788 spec->mixers[0] = desktop_mixer; 8789 snd_hda_codec_set_name(codec, "Sound Blaster Z"); 8790 break; 8791 case QUIRK_ZXR: 8792 spec->mixers[0] = desktop_mixer; 8793 snd_hda_codec_set_name(codec, "Sound Blaster ZxR"); 8794 break; 8795 case QUIRK_ZXR_DBPRO: 8796 break; 8797 case QUIRK_R3D: 8798 spec->mixers[0] = desktop_mixer; 8799 snd_hda_codec_set_name(codec, "Recon3D"); 8800 break; 8801 case QUIRK_R3DI: 8802 spec->mixers[0] = r3di_mixer; 8803 snd_hda_codec_set_name(codec, "Recon3Di"); 8804 break; 8805 case QUIRK_AE5: 8806 spec->mixers[0] = desktop_mixer; 8807 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5"); 8808 break; 8809 default: 8810 spec->mixers[0] = ca0132_mixer; 8811 break; 8812 } 8813 8814 /* Setup whether or not to use alt functions/controls/pci_mmio */ 8815 switch (ca0132_quirk(spec)) { 8816 case QUIRK_SBZ: 8817 case QUIRK_R3D: 8818 case QUIRK_AE5: 8819 case QUIRK_ZXR: 8820 spec->use_alt_controls = true; 8821 spec->use_alt_functions = true; 8822 spec->use_pci_mmio = true; 8823 break; 8824 case QUIRK_R3DI: 8825 spec->use_alt_controls = true; 8826 spec->use_alt_functions = true; 8827 spec->use_pci_mmio = false; 8828 break; 8829 default: 8830 spec->use_alt_controls = false; 8831 spec->use_alt_functions = false; 8832 spec->use_pci_mmio = false; 8833 break; 8834 } 8835 8836 #ifdef CONFIG_PCI 8837 if (spec->use_pci_mmio) { 8838 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20); 8839 if (spec->mem_base == NULL) { 8840 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE."); 8841 spec->quirk = QUIRK_NONE; 8842 } 8843 } 8844 #endif 8845 8846 spec->base_init_verbs = ca0132_base_init_verbs; 8847 spec->base_exit_verbs = ca0132_base_exit_verbs; 8848 8849 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed); 8850 8851 ca0132_init_chip(codec); 8852 8853 ca0132_config(codec); 8854 8855 err = ca0132_prepare_verbs(codec); 8856 if (err < 0) 8857 goto error; 8858 8859 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL); 8860 if (err < 0) 8861 goto error; 8862 8863 return 0; 8864 8865 error: 8866 ca0132_free(codec); 8867 return err; 8868 } 8869 8870 /* 8871 * patch entries 8872 */ 8873 static const struct hda_device_id snd_hda_id_ca0132[] = { 8874 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132), 8875 {} /* terminator */ 8876 }; 8877 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132); 8878 8879 MODULE_LICENSE("GPL"); 8880 MODULE_DESCRIPTION("Creative Sound Core3D codec"); 8881 8882 static struct hda_codec_driver ca0132_driver = { 8883 .id = snd_hda_id_ca0132, 8884 }; 8885 8886 module_hda_codec_driver(ca0132_driver); 8887