1 /* 2 * HD audio interface patch for Creative CA0132 chip 3 * 4 * Copyright (c) 2011, Creative Technology Ltd. 5 * 6 * Based on patch_ca0110.c 7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de> 8 * 9 * This driver is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This driver is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 */ 23 24 #include <linux/init.h> 25 #include <linux/delay.h> 26 #include <linux/slab.h> 27 #include <linux/mutex.h> 28 #include <linux/module.h> 29 #include <linux/firmware.h> 30 #include <linux/kernel.h> 31 #include <linux/types.h> 32 #include <linux/io.h> 33 #include <linux/pci.h> 34 #include <asm/io.h> 35 #include <sound/core.h> 36 #include <sound/hda_codec.h> 37 #include "hda_local.h" 38 #include "hda_auto_parser.h" 39 #include "hda_jack.h" 40 41 #include "ca0132_regs.h" 42 43 /* Enable this to see controls for tuning purpose. */ 44 /*#define ENABLE_TUNING_CONTROLS*/ 45 46 #ifdef ENABLE_TUNING_CONTROLS 47 #include <sound/tlv.h> 48 #endif 49 50 #define FLOAT_ZERO 0x00000000 51 #define FLOAT_ONE 0x3f800000 52 #define FLOAT_TWO 0x40000000 53 #define FLOAT_THREE 0x40400000 54 #define FLOAT_EIGHT 0x41000000 55 #define FLOAT_MINUS_5 0xc0a00000 56 57 #define UNSOL_TAG_DSP 0x16 58 59 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18) 60 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15) 61 62 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8 63 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32 64 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2 65 66 #define MASTERCONTROL 0x80 67 #define MASTERCONTROL_ALLOC_DMA_CHAN 10 68 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60 69 70 #define WIDGET_CHIP_CTRL 0x15 71 #define WIDGET_DSP_CTRL 0x16 72 73 #define MEM_CONNID_MICIN1 3 74 #define MEM_CONNID_MICIN2 5 75 #define MEM_CONNID_MICOUT1 12 76 #define MEM_CONNID_MICOUT2 14 77 #define MEM_CONNID_WUH 10 78 #define MEM_CONNID_DSP 16 79 #define MEM_CONNID_DMIC 100 80 81 #define SCP_SET 0 82 #define SCP_GET 1 83 84 #define EFX_FILE "ctefx.bin" 85 #define DESKTOP_EFX_FILE "ctefx-desktop.bin" 86 #define R3DI_EFX_FILE "ctefx-r3di.bin" 87 88 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 89 MODULE_FIRMWARE(EFX_FILE); 90 MODULE_FIRMWARE(DESKTOP_EFX_FILE); 91 MODULE_FIRMWARE(R3DI_EFX_FILE); 92 #endif 93 94 static const char *const dirstr[2] = { "Playback", "Capture" }; 95 96 #define NUM_OF_OUTPUTS 3 97 enum { 98 SPEAKER_OUT, 99 HEADPHONE_OUT, 100 SURROUND_OUT 101 }; 102 103 enum { 104 DIGITAL_MIC, 105 LINE_MIC_IN 106 }; 107 108 /* Strings for Input Source Enum Control */ 109 static const char *const in_src_str[3] = {"Rear Mic", "Line", "Front Mic" }; 110 #define IN_SRC_NUM_OF_INPUTS 3 111 enum { 112 REAR_MIC, 113 REAR_LINE_IN, 114 FRONT_MIC, 115 }; 116 117 enum { 118 #define VNODE_START_NID 0x80 119 VNID_SPK = VNODE_START_NID, /* Speaker vnid */ 120 VNID_MIC, 121 VNID_HP_SEL, 122 VNID_AMIC1_SEL, 123 VNID_HP_ASEL, 124 VNID_AMIC1_ASEL, 125 VNODE_END_NID, 126 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID) 127 128 #define EFFECT_START_NID 0x90 129 #define OUT_EFFECT_START_NID EFFECT_START_NID 130 SURROUND = OUT_EFFECT_START_NID, 131 CRYSTALIZER, 132 DIALOG_PLUS, 133 SMART_VOLUME, 134 X_BASS, 135 EQUALIZER, 136 OUT_EFFECT_END_NID, 137 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID) 138 139 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID 140 ECHO_CANCELLATION = IN_EFFECT_START_NID, 141 VOICE_FOCUS, 142 MIC_SVM, 143 NOISE_REDUCTION, 144 IN_EFFECT_END_NID, 145 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID) 146 147 VOICEFX = IN_EFFECT_END_NID, 148 PLAY_ENHANCEMENT, 149 CRYSTAL_VOICE, 150 EFFECT_END_NID, 151 OUTPUT_SOURCE_ENUM, 152 INPUT_SOURCE_ENUM, 153 XBASS_XOVER, 154 EQ_PRESET_ENUM, 155 SMART_VOLUME_ENUM, 156 MIC_BOOST_ENUM, 157 AE5_HEADPHONE_GAIN_ENUM, 158 AE5_SOUND_FILTER_ENUM, 159 ZXR_HEADPHONE_GAIN 160 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID) 161 }; 162 163 /* Effects values size*/ 164 #define EFFECT_VALS_MAX_COUNT 12 165 166 /* 167 * Default values for the effect slider controls, they are in order of their 168 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then 169 * X-bass. 170 */ 171 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50}; 172 /* Amount of effect level sliders for ca0132_alt controls. */ 173 #define EFFECT_LEVEL_SLIDERS 5 174 175 /* Latency introduced by DSP blocks in milliseconds. */ 176 #define DSP_CAPTURE_INIT_LATENCY 0 177 #define DSP_CRYSTAL_VOICE_LATENCY 124 178 #define DSP_PLAYBACK_INIT_LATENCY 13 179 #define DSP_PLAY_ENHANCEMENT_LATENCY 30 180 #define DSP_SPEAKER_OUT_LATENCY 7 181 182 struct ct_effect { 183 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 184 hda_nid_t nid; 185 int mid; /*effect module ID*/ 186 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/ 187 int direct; /* 0:output; 1:input*/ 188 int params; /* number of default non-on/off params */ 189 /*effect default values, 1st is on/off. */ 190 unsigned int def_vals[EFFECT_VALS_MAX_COUNT]; 191 }; 192 193 #define EFX_DIR_OUT 0 194 #define EFX_DIR_IN 1 195 196 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = { 197 { .name = "Surround", 198 .nid = SURROUND, 199 .mid = 0x96, 200 .reqs = {0, 1}, 201 .direct = EFX_DIR_OUT, 202 .params = 1, 203 .def_vals = {0x3F800000, 0x3F2B851F} 204 }, 205 { .name = "Crystalizer", 206 .nid = CRYSTALIZER, 207 .mid = 0x96, 208 .reqs = {7, 8}, 209 .direct = EFX_DIR_OUT, 210 .params = 1, 211 .def_vals = {0x3F800000, 0x3F266666} 212 }, 213 { .name = "Dialog Plus", 214 .nid = DIALOG_PLUS, 215 .mid = 0x96, 216 .reqs = {2, 3}, 217 .direct = EFX_DIR_OUT, 218 .params = 1, 219 .def_vals = {0x00000000, 0x3F000000} 220 }, 221 { .name = "Smart Volume", 222 .nid = SMART_VOLUME, 223 .mid = 0x96, 224 .reqs = {4, 5, 6}, 225 .direct = EFX_DIR_OUT, 226 .params = 2, 227 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000} 228 }, 229 { .name = "X-Bass", 230 .nid = X_BASS, 231 .mid = 0x96, 232 .reqs = {24, 23, 25}, 233 .direct = EFX_DIR_OUT, 234 .params = 2, 235 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000} 236 }, 237 { .name = "Equalizer", 238 .nid = EQUALIZER, 239 .mid = 0x96, 240 .reqs = {9, 10, 11, 12, 13, 14, 241 15, 16, 17, 18, 19, 20}, 242 .direct = EFX_DIR_OUT, 243 .params = 11, 244 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000, 245 0x00000000, 0x00000000, 0x00000000, 0x00000000, 246 0x00000000, 0x00000000, 0x00000000, 0x00000000} 247 }, 248 { .name = "Echo Cancellation", 249 .nid = ECHO_CANCELLATION, 250 .mid = 0x95, 251 .reqs = {0, 1, 2, 3}, 252 .direct = EFX_DIR_IN, 253 .params = 3, 254 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000} 255 }, 256 { .name = "Voice Focus", 257 .nid = VOICE_FOCUS, 258 .mid = 0x95, 259 .reqs = {6, 7, 8, 9}, 260 .direct = EFX_DIR_IN, 261 .params = 3, 262 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000} 263 }, 264 { .name = "Mic SVM", 265 .nid = MIC_SVM, 266 .mid = 0x95, 267 .reqs = {44, 45}, 268 .direct = EFX_DIR_IN, 269 .params = 1, 270 .def_vals = {0x00000000, 0x3F3D70A4} 271 }, 272 { .name = "Noise Reduction", 273 .nid = NOISE_REDUCTION, 274 .mid = 0x95, 275 .reqs = {4, 5}, 276 .direct = EFX_DIR_IN, 277 .params = 1, 278 .def_vals = {0x3F800000, 0x3F000000} 279 }, 280 { .name = "VoiceFX", 281 .nid = VOICEFX, 282 .mid = 0x95, 283 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}, 284 .direct = EFX_DIR_IN, 285 .params = 8, 286 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000, 287 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000, 288 0x00000000} 289 } 290 }; 291 292 /* Tuning controls */ 293 #ifdef ENABLE_TUNING_CONTROLS 294 295 enum { 296 #define TUNING_CTL_START_NID 0xC0 297 WEDGE_ANGLE = TUNING_CTL_START_NID, 298 SVM_LEVEL, 299 EQUALIZER_BAND_0, 300 EQUALIZER_BAND_1, 301 EQUALIZER_BAND_2, 302 EQUALIZER_BAND_3, 303 EQUALIZER_BAND_4, 304 EQUALIZER_BAND_5, 305 EQUALIZER_BAND_6, 306 EQUALIZER_BAND_7, 307 EQUALIZER_BAND_8, 308 EQUALIZER_BAND_9, 309 TUNING_CTL_END_NID 310 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID) 311 }; 312 313 struct ct_tuning_ctl { 314 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 315 hda_nid_t parent_nid; 316 hda_nid_t nid; 317 int mid; /*effect module ID*/ 318 int req; /*effect module request*/ 319 int direct; /* 0:output; 1:input*/ 320 unsigned int def_val;/*effect default values*/ 321 }; 322 323 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = { 324 { .name = "Wedge Angle", 325 .parent_nid = VOICE_FOCUS, 326 .nid = WEDGE_ANGLE, 327 .mid = 0x95, 328 .req = 8, 329 .direct = EFX_DIR_IN, 330 .def_val = 0x41F00000 331 }, 332 { .name = "SVM Level", 333 .parent_nid = MIC_SVM, 334 .nid = SVM_LEVEL, 335 .mid = 0x95, 336 .req = 45, 337 .direct = EFX_DIR_IN, 338 .def_val = 0x3F3D70A4 339 }, 340 { .name = "EQ Band0", 341 .parent_nid = EQUALIZER, 342 .nid = EQUALIZER_BAND_0, 343 .mid = 0x96, 344 .req = 11, 345 .direct = EFX_DIR_OUT, 346 .def_val = 0x00000000 347 }, 348 { .name = "EQ Band1", 349 .parent_nid = EQUALIZER, 350 .nid = EQUALIZER_BAND_1, 351 .mid = 0x96, 352 .req = 12, 353 .direct = EFX_DIR_OUT, 354 .def_val = 0x00000000 355 }, 356 { .name = "EQ Band2", 357 .parent_nid = EQUALIZER, 358 .nid = EQUALIZER_BAND_2, 359 .mid = 0x96, 360 .req = 13, 361 .direct = EFX_DIR_OUT, 362 .def_val = 0x00000000 363 }, 364 { .name = "EQ Band3", 365 .parent_nid = EQUALIZER, 366 .nid = EQUALIZER_BAND_3, 367 .mid = 0x96, 368 .req = 14, 369 .direct = EFX_DIR_OUT, 370 .def_val = 0x00000000 371 }, 372 { .name = "EQ Band4", 373 .parent_nid = EQUALIZER, 374 .nid = EQUALIZER_BAND_4, 375 .mid = 0x96, 376 .req = 15, 377 .direct = EFX_DIR_OUT, 378 .def_val = 0x00000000 379 }, 380 { .name = "EQ Band5", 381 .parent_nid = EQUALIZER, 382 .nid = EQUALIZER_BAND_5, 383 .mid = 0x96, 384 .req = 16, 385 .direct = EFX_DIR_OUT, 386 .def_val = 0x00000000 387 }, 388 { .name = "EQ Band6", 389 .parent_nid = EQUALIZER, 390 .nid = EQUALIZER_BAND_6, 391 .mid = 0x96, 392 .req = 17, 393 .direct = EFX_DIR_OUT, 394 .def_val = 0x00000000 395 }, 396 { .name = "EQ Band7", 397 .parent_nid = EQUALIZER, 398 .nid = EQUALIZER_BAND_7, 399 .mid = 0x96, 400 .req = 18, 401 .direct = EFX_DIR_OUT, 402 .def_val = 0x00000000 403 }, 404 { .name = "EQ Band8", 405 .parent_nid = EQUALIZER, 406 .nid = EQUALIZER_BAND_8, 407 .mid = 0x96, 408 .req = 19, 409 .direct = EFX_DIR_OUT, 410 .def_val = 0x00000000 411 }, 412 { .name = "EQ Band9", 413 .parent_nid = EQUALIZER, 414 .nid = EQUALIZER_BAND_9, 415 .mid = 0x96, 416 .req = 20, 417 .direct = EFX_DIR_OUT, 418 .def_val = 0x00000000 419 } 420 }; 421 #endif 422 423 /* Voice FX Presets */ 424 #define VOICEFX_MAX_PARAM_COUNT 9 425 426 struct ct_voicefx { 427 char *name; 428 hda_nid_t nid; 429 int mid; 430 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/ 431 }; 432 433 struct ct_voicefx_preset { 434 char *name; /*preset name*/ 435 unsigned int vals[VOICEFX_MAX_PARAM_COUNT]; 436 }; 437 438 static const struct ct_voicefx ca0132_voicefx = { 439 .name = "VoiceFX Capture Switch", 440 .nid = VOICEFX, 441 .mid = 0x95, 442 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18} 443 }; 444 445 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = { 446 { .name = "Neutral", 447 .vals = { 0x00000000, 0x43C80000, 0x44AF0000, 448 0x44FA0000, 0x3F800000, 0x3F800000, 449 0x3F800000, 0x00000000, 0x00000000 } 450 }, 451 { .name = "Female2Male", 452 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 453 0x44FA0000, 0x3F19999A, 0x3F866666, 454 0x3F800000, 0x00000000, 0x00000000 } 455 }, 456 { .name = "Male2Female", 457 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 458 0x450AC000, 0x4017AE14, 0x3F6B851F, 459 0x3F800000, 0x00000000, 0x00000000 } 460 }, 461 { .name = "ScrappyKid", 462 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 463 0x44FA0000, 0x40400000, 0x3F28F5C3, 464 0x3F800000, 0x00000000, 0x00000000 } 465 }, 466 { .name = "Elderly", 467 .vals = { 0x3F800000, 0x44324000, 0x44BB8000, 468 0x44E10000, 0x3FB33333, 0x3FB9999A, 469 0x3F800000, 0x3E3A2E43, 0x00000000 } 470 }, 471 { .name = "Orc", 472 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000, 473 0x45098000, 0x3F266666, 0x3FC00000, 474 0x3F800000, 0x00000000, 0x00000000 } 475 }, 476 { .name = "Elf", 477 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000, 478 0x45193000, 0x3F8E147B, 0x3F75C28F, 479 0x3F800000, 0x00000000, 0x00000000 } 480 }, 481 { .name = "Dwarf", 482 .vals = { 0x3F800000, 0x43930000, 0x44BEE000, 483 0x45007000, 0x3F451EB8, 0x3F7851EC, 484 0x3F800000, 0x00000000, 0x00000000 } 485 }, 486 { .name = "AlienBrute", 487 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF, 488 0x451F6000, 0x3F266666, 0x3FA7D945, 489 0x3F800000, 0x3CF5C28F, 0x00000000 } 490 }, 491 { .name = "Robot", 492 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 493 0x44FA0000, 0x3FB2718B, 0x3F800000, 494 0xBC07010E, 0x00000000, 0x00000000 } 495 }, 496 { .name = "Marine", 497 .vals = { 0x3F800000, 0x43C20000, 0x44906000, 498 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71, 499 0x3F0A3D71, 0x00000000, 0x00000000 } 500 }, 501 { .name = "Emo", 502 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 503 0x44FA0000, 0x3F800000, 0x3F800000, 504 0x3E4CCCCD, 0x00000000, 0x00000000 } 505 }, 506 { .name = "DeepVoice", 507 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF, 508 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA, 509 0x3F800000, 0x00000000, 0x00000000 } 510 }, 511 { .name = "Munchkin", 512 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 513 0x44FA0000, 0x3F800000, 0x3F1A043C, 514 0x3F800000, 0x00000000, 0x00000000 } 515 } 516 }; 517 518 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */ 519 520 #define EQ_PRESET_MAX_PARAM_COUNT 11 521 522 struct ct_eq { 523 char *name; 524 hda_nid_t nid; 525 int mid; 526 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/ 527 }; 528 529 struct ct_eq_preset { 530 char *name; /*preset name*/ 531 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT]; 532 }; 533 534 static const struct ct_eq ca0132_alt_eq_enum = { 535 .name = "FX: Equalizer Preset Switch", 536 .nid = EQ_PRESET_ENUM, 537 .mid = 0x96, 538 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20} 539 }; 540 541 542 static const struct ct_eq_preset ca0132_alt_eq_presets[] = { 543 { .name = "Flat", 544 .vals = { 0x00000000, 0x00000000, 0x00000000, 545 0x00000000, 0x00000000, 0x00000000, 546 0x00000000, 0x00000000, 0x00000000, 547 0x00000000, 0x00000000 } 548 }, 549 { .name = "Acoustic", 550 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD, 551 0x40000000, 0x00000000, 0x00000000, 552 0x00000000, 0x00000000, 0x40000000, 553 0x40000000, 0x40000000 } 554 }, 555 { .name = "Classical", 556 .vals = { 0x00000000, 0x00000000, 0x40C00000, 557 0x40C00000, 0x40466666, 0x00000000, 558 0x00000000, 0x00000000, 0x00000000, 559 0x40466666, 0x40466666 } 560 }, 561 { .name = "Country", 562 .vals = { 0x00000000, 0xBF99999A, 0x00000000, 563 0x3FA66666, 0x3FA66666, 0x3F8CCCCD, 564 0x00000000, 0x00000000, 0x40000000, 565 0x40466666, 0x40800000 } 566 }, 567 { .name = "Dance", 568 .vals = { 0x00000000, 0xBF99999A, 0x40000000, 569 0x40466666, 0x40866666, 0xBF99999A, 570 0xBF99999A, 0x00000000, 0x00000000, 571 0x40800000, 0x40800000 } 572 }, 573 { .name = "Jazz", 574 .vals = { 0x00000000, 0x00000000, 0x00000000, 575 0x3F8CCCCD, 0x40800000, 0x40800000, 576 0x40800000, 0x00000000, 0x3F8CCCCD, 577 0x40466666, 0x40466666 } 578 }, 579 { .name = "New Age", 580 .vals = { 0x00000000, 0x00000000, 0x40000000, 581 0x40000000, 0x00000000, 0x00000000, 582 0x00000000, 0x3F8CCCCD, 0x40000000, 583 0x40000000, 0x40000000 } 584 }, 585 { .name = "Pop", 586 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000, 587 0x40000000, 0x40000000, 0x00000000, 588 0xBF99999A, 0xBF99999A, 0x00000000, 589 0x40466666, 0x40C00000 } 590 }, 591 { .name = "Rock", 592 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A, 593 0x3F8CCCCD, 0x40000000, 0xBF99999A, 594 0xBF99999A, 0x00000000, 0x00000000, 595 0x40800000, 0x40800000 } 596 }, 597 { .name = "Vocal", 598 .vals = { 0x00000000, 0xC0000000, 0xBF99999A, 599 0xBF99999A, 0x00000000, 0x40466666, 600 0x40800000, 0x40466666, 0x00000000, 601 0x00000000, 0x3F8CCCCD } 602 } 603 }; 604 605 /* DSP command sequences for ca0132_alt_select_out */ 606 #define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */ 607 struct ca0132_alt_out_set { 608 char *name; /*preset name*/ 609 unsigned char commands; 610 unsigned int mids[ALT_OUT_SET_MAX_COMMANDS]; 611 unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS]; 612 unsigned int vals[ALT_OUT_SET_MAX_COMMANDS]; 613 }; 614 615 static const struct ca0132_alt_out_set alt_out_presets[] = { 616 { .name = "Line Out", 617 .commands = 7, 618 .mids = { 0x96, 0x96, 0x96, 0x8F, 619 0x96, 0x96, 0x96 }, 620 .reqs = { 0x19, 0x17, 0x18, 0x01, 621 0x1F, 0x15, 0x3A }, 622 .vals = { 0x3F000000, 0x42A00000, 0x00000000, 623 0x00000000, 0x00000000, 0x00000000, 624 0x00000000 } 625 }, 626 { .name = "Headphone", 627 .commands = 7, 628 .mids = { 0x96, 0x96, 0x96, 0x8F, 629 0x96, 0x96, 0x96 }, 630 .reqs = { 0x19, 0x17, 0x18, 0x01, 631 0x1F, 0x15, 0x3A }, 632 .vals = { 0x3F000000, 0x42A00000, 0x00000000, 633 0x00000000, 0x00000000, 0x00000000, 634 0x00000000 } 635 }, 636 { .name = "Surround", 637 .commands = 8, 638 .mids = { 0x96, 0x8F, 0x96, 0x96, 639 0x96, 0x96, 0x96, 0x96 }, 640 .reqs = { 0x18, 0x01, 0x1F, 0x15, 641 0x3A, 0x1A, 0x1B, 0x1C }, 642 .vals = { 0x00000000, 0x00000000, 0x00000000, 643 0x00000000, 0x00000000, 0x00000000, 644 0x00000000, 0x00000000 } 645 } 646 }; 647 648 /* 649 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume, 650 * and I don't know what the third req is, but it's always zero. I assume it's 651 * some sort of update or set command to tell the DSP there's new volume info. 652 */ 653 #define DSP_VOL_OUT 0 654 #define DSP_VOL_IN 1 655 656 struct ct_dsp_volume_ctl { 657 hda_nid_t vnid; 658 int mid; /* module ID*/ 659 unsigned int reqs[3]; /* scp req ID */ 660 }; 661 662 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = { 663 { .vnid = VNID_SPK, 664 .mid = 0x32, 665 .reqs = {3, 4, 2} 666 }, 667 { .vnid = VNID_MIC, 668 .mid = 0x37, 669 .reqs = {2, 3, 1} 670 } 671 }; 672 673 /* Values for ca0113_mmio_command_set for selecting output. */ 674 #define AE5_CA0113_OUT_SET_COMMANDS 6 675 struct ae5_ca0113_output_set { 676 unsigned int group[AE5_CA0113_OUT_SET_COMMANDS]; 677 unsigned int target[AE5_CA0113_OUT_SET_COMMANDS]; 678 unsigned int vals[AE5_CA0113_OUT_SET_COMMANDS]; 679 }; 680 681 static const struct ae5_ca0113_output_set ae5_ca0113_output_presets[] = { 682 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 683 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 684 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f } 685 }, 686 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 687 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 688 .vals = { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } 689 }, 690 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 691 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 692 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f } 693 } 694 }; 695 696 /* ae5 ca0113 command sequences to set headphone gain levels. */ 697 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4 698 struct ae5_headphone_gain_set { 699 char *name; 700 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS]; 701 }; 702 703 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = { 704 { .name = "Low (16-31", 705 .vals = { 0xff, 0x2c, 0xf5, 0x32 } 706 }, 707 { .name = "Medium (32-149", 708 .vals = { 0x38, 0xa8, 0x3e, 0x4c } 709 }, 710 { .name = "High (150-600", 711 .vals = { 0xff, 0xff, 0xff, 0x7f } 712 } 713 }; 714 715 struct ae5_filter_set { 716 char *name; 717 unsigned int val; 718 }; 719 720 static const struct ae5_filter_set ae5_filter_presets[] = { 721 { .name = "Slow Roll Off", 722 .val = 0xa0 723 }, 724 { .name = "Minimum Phase", 725 .val = 0xc0 726 }, 727 { .name = "Fast Roll Off", 728 .val = 0x80 729 } 730 }; 731 732 enum hda_cmd_vendor_io { 733 /* for DspIO node */ 734 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000, 735 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100, 736 737 VENDOR_DSPIO_STATUS = 0xF01, 738 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702, 739 VENDOR_DSPIO_SCP_READ_DATA = 0xF02, 740 VENDOR_DSPIO_DSP_INIT = 0x703, 741 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704, 742 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04, 743 744 /* for ChipIO node */ 745 VENDOR_CHIPIO_ADDRESS_LOW = 0x000, 746 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100, 747 VENDOR_CHIPIO_STREAM_FORMAT = 0x200, 748 VENDOR_CHIPIO_DATA_LOW = 0x300, 749 VENDOR_CHIPIO_DATA_HIGH = 0x400, 750 751 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500, 752 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00, 753 754 VENDOR_CHIPIO_GET_PARAMETER = 0xF00, 755 VENDOR_CHIPIO_STATUS = 0xF01, 756 VENDOR_CHIPIO_HIC_POST_READ = 0x702, 757 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03, 758 759 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707, 760 VENDOR_CHIPIO_8051_DATA_READ = 0xF07, 761 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08, 762 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709, 763 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09, 764 765 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A, 766 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A, 767 768 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C, 769 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C, 770 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D, 771 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E, 772 VENDOR_CHIPIO_FLAG_SET = 0x70F, 773 VENDOR_CHIPIO_FLAGS_GET = 0xF0F, 774 VENDOR_CHIPIO_PARAM_SET = 0x710, 775 VENDOR_CHIPIO_PARAM_GET = 0xF10, 776 777 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711, 778 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712, 779 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12, 780 VENDOR_CHIPIO_PORT_FREE_SET = 0x713, 781 782 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17, 783 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717, 784 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18, 785 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718, 786 787 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788, 788 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88, 789 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789, 790 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89, 791 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A, 792 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A, 793 794 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D 795 }; 796 797 /* 798 * Control flag IDs 799 */ 800 enum control_flag_id { 801 /* Connection manager stream setup is bypassed/enabled */ 802 CONTROL_FLAG_C_MGR = 0, 803 /* DSP DMA is bypassed/enabled */ 804 CONTROL_FLAG_DMA = 1, 805 /* 8051 'idle' mode is disabled/enabled */ 806 CONTROL_FLAG_IDLE_ENABLE = 2, 807 /* Tracker for the SPDIF-in path is bypassed/enabled */ 808 CONTROL_FLAG_TRACKER = 3, 809 /* DigitalOut to Spdif2Out connection is disabled/enabled */ 810 CONTROL_FLAG_SPDIF2OUT = 4, 811 /* Digital Microphone is disabled/enabled */ 812 CONTROL_FLAG_DMIC = 5, 813 /* ADC_B rate is 48 kHz/96 kHz */ 814 CONTROL_FLAG_ADC_B_96KHZ = 6, 815 /* ADC_C rate is 48 kHz/96 kHz */ 816 CONTROL_FLAG_ADC_C_96KHZ = 7, 817 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */ 818 CONTROL_FLAG_DAC_96KHZ = 8, 819 /* DSP rate is 48 kHz/96 kHz */ 820 CONTROL_FLAG_DSP_96KHZ = 9, 821 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */ 822 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10, 823 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */ 824 CONTROL_FLAG_SRC_RATE_96KHZ = 11, 825 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */ 826 CONTROL_FLAG_DECODE_LOOP = 12, 827 /* De-emphasis filter on DAC-1 disabled/enabled */ 828 CONTROL_FLAG_DAC1_DEEMPHASIS = 13, 829 /* De-emphasis filter on DAC-2 disabled/enabled */ 830 CONTROL_FLAG_DAC2_DEEMPHASIS = 14, 831 /* De-emphasis filter on DAC-3 disabled/enabled */ 832 CONTROL_FLAG_DAC3_DEEMPHASIS = 15, 833 /* High-pass filter on ADC_B disabled/enabled */ 834 CONTROL_FLAG_ADC_B_HIGH_PASS = 16, 835 /* High-pass filter on ADC_C disabled/enabled */ 836 CONTROL_FLAG_ADC_C_HIGH_PASS = 17, 837 /* Common mode on Port_A disabled/enabled */ 838 CONTROL_FLAG_PORT_A_COMMON_MODE = 18, 839 /* Common mode on Port_D disabled/enabled */ 840 CONTROL_FLAG_PORT_D_COMMON_MODE = 19, 841 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */ 842 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20, 843 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */ 844 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21, 845 /* ASI rate is 48kHz/96kHz */ 846 CONTROL_FLAG_ASI_96KHZ = 22, 847 /* DAC power settings able to control attached ports no/yes */ 848 CONTROL_FLAG_DACS_CONTROL_PORTS = 23, 849 /* Clock Stop OK reporting is disabled/enabled */ 850 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24, 851 /* Number of control flags */ 852 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1) 853 }; 854 855 /* 856 * Control parameter IDs 857 */ 858 enum control_param_id { 859 /* 0: None, 1: Mic1In*/ 860 CONTROL_PARAM_VIP_SOURCE = 1, 861 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */ 862 CONTROL_PARAM_SPDIF1_SOURCE = 2, 863 /* Port A output stage gain setting to use when 16 Ohm output 864 * impedance is selected*/ 865 CONTROL_PARAM_PORTA_160OHM_GAIN = 8, 866 /* Port D output stage gain setting to use when 16 Ohm output 867 * impedance is selected*/ 868 CONTROL_PARAM_PORTD_160OHM_GAIN = 10, 869 870 /* 871 * This control param name was found in the 8051 memory, and makes 872 * sense given the fact the AE-5 uses it and has the ASI flag set. 873 */ 874 CONTROL_PARAM_ASI = 23, 875 876 /* Stream Control */ 877 878 /* Select stream with the given ID */ 879 CONTROL_PARAM_STREAM_ID = 24, 880 /* Source connection point for the selected stream */ 881 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25, 882 /* Destination connection point for the selected stream */ 883 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26, 884 /* Number of audio channels in the selected stream */ 885 CONTROL_PARAM_STREAMS_CHANNELS = 27, 886 /*Enable control for the selected stream */ 887 CONTROL_PARAM_STREAM_CONTROL = 28, 888 889 /* Connection Point Control */ 890 891 /* Select connection point with the given ID */ 892 CONTROL_PARAM_CONN_POINT_ID = 29, 893 /* Connection point sample rate */ 894 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30, 895 896 /* Node Control */ 897 898 /* Select HDA node with the given ID */ 899 CONTROL_PARAM_NODE_ID = 31 900 }; 901 902 /* 903 * Dsp Io Status codes 904 */ 905 enum hda_vendor_status_dspio { 906 /* Success */ 907 VENDOR_STATUS_DSPIO_OK = 0x00, 908 /* Busy, unable to accept new command, the host must retry */ 909 VENDOR_STATUS_DSPIO_BUSY = 0x01, 910 /* SCP command queue is full */ 911 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02, 912 /* SCP response queue is empty */ 913 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03 914 }; 915 916 /* 917 * Chip Io Status codes 918 */ 919 enum hda_vendor_status_chipio { 920 /* Success */ 921 VENDOR_STATUS_CHIPIO_OK = 0x00, 922 /* Busy, unable to accept new command, the host must retry */ 923 VENDOR_STATUS_CHIPIO_BUSY = 0x01 924 }; 925 926 /* 927 * CA0132 sample rate 928 */ 929 enum ca0132_sample_rate { 930 SR_6_000 = 0x00, 931 SR_8_000 = 0x01, 932 SR_9_600 = 0x02, 933 SR_11_025 = 0x03, 934 SR_16_000 = 0x04, 935 SR_22_050 = 0x05, 936 SR_24_000 = 0x06, 937 SR_32_000 = 0x07, 938 SR_44_100 = 0x08, 939 SR_48_000 = 0x09, 940 SR_88_200 = 0x0A, 941 SR_96_000 = 0x0B, 942 SR_144_000 = 0x0C, 943 SR_176_400 = 0x0D, 944 SR_192_000 = 0x0E, 945 SR_384_000 = 0x0F, 946 947 SR_COUNT = 0x10, 948 949 SR_RATE_UNKNOWN = 0x1F 950 }; 951 952 enum dsp_download_state { 953 DSP_DOWNLOAD_FAILED = -1, 954 DSP_DOWNLOAD_INIT = 0, 955 DSP_DOWNLOADING = 1, 956 DSP_DOWNLOADED = 2 957 }; 958 959 /* retrieve parameters from hda format */ 960 #define get_hdafmt_chs(fmt) (fmt & 0xf) 961 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7) 962 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f) 963 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1) 964 965 /* 966 * CA0132 specific 967 */ 968 969 struct ca0132_spec { 970 const struct snd_kcontrol_new *mixers[5]; 971 unsigned int num_mixers; 972 const struct hda_verb *base_init_verbs; 973 const struct hda_verb *base_exit_verbs; 974 const struct hda_verb *chip_init_verbs; 975 const struct hda_verb *desktop_init_verbs; 976 struct hda_verb *spec_init_verbs; 977 struct auto_pin_cfg autocfg; 978 979 /* Nodes configurations */ 980 struct hda_multi_out multiout; 981 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS]; 982 hda_nid_t dacs[AUTO_CFG_MAX_OUTS]; 983 unsigned int num_outputs; 984 hda_nid_t input_pins[AUTO_PIN_LAST]; 985 hda_nid_t adcs[AUTO_PIN_LAST]; 986 hda_nid_t dig_out; 987 hda_nid_t dig_in; 988 unsigned int num_inputs; 989 hda_nid_t shared_mic_nid; 990 hda_nid_t shared_out_nid; 991 hda_nid_t unsol_tag_hp; 992 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */ 993 hda_nid_t unsol_tag_amic1; 994 995 /* chip access */ 996 struct mutex chipio_mutex; /* chip access mutex */ 997 u32 curr_chip_addx; 998 999 /* DSP download related */ 1000 enum dsp_download_state dsp_state; 1001 unsigned int dsp_stream_id; 1002 unsigned int wait_scp; 1003 unsigned int wait_scp_header; 1004 unsigned int wait_num_data; 1005 unsigned int scp_resp_header; 1006 unsigned int scp_resp_data[4]; 1007 unsigned int scp_resp_count; 1008 bool alt_firmware_present; 1009 bool startup_check_entered; 1010 bool dsp_reload; 1011 1012 /* mixer and effects related */ 1013 unsigned char dmic_ctl; 1014 int cur_out_type; 1015 int cur_mic_type; 1016 long vnode_lvol[VNODES_COUNT]; 1017 long vnode_rvol[VNODES_COUNT]; 1018 long vnode_lswitch[VNODES_COUNT]; 1019 long vnode_rswitch[VNODES_COUNT]; 1020 long effects_switch[EFFECTS_COUNT]; 1021 long voicefx_val; 1022 long cur_mic_boost; 1023 /* ca0132_alt control related values */ 1024 unsigned char in_enum_val; 1025 unsigned char out_enum_val; 1026 unsigned char mic_boost_enum_val; 1027 unsigned char smart_volume_setting; 1028 long fx_ctl_val[EFFECT_LEVEL_SLIDERS]; 1029 long xbass_xover_freq; 1030 long eq_preset_val; 1031 unsigned int tlv[4]; 1032 struct hda_vmaster_mute_hook vmaster_mute; 1033 /* AE-5 Control values */ 1034 unsigned char ae5_headphone_gain_val; 1035 unsigned char ae5_filter_val; 1036 /* ZxR Control Values */ 1037 unsigned char zxr_gain_set; 1038 1039 struct hda_codec *codec; 1040 struct delayed_work unsol_hp_work; 1041 int quirk; 1042 1043 #ifdef ENABLE_TUNING_CONTROLS 1044 long cur_ctl_vals[TUNING_CTLS_COUNT]; 1045 #endif 1046 /* 1047 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster 1048 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown 1049 * things. 1050 */ 1051 bool use_pci_mmio; 1052 void __iomem *mem_base; 1053 1054 /* 1055 * Whether or not to use the alt functions like alt_select_out, 1056 * alt_select_in, etc. Only used on desktop codecs for now, because of 1057 * surround sound support. 1058 */ 1059 bool use_alt_functions; 1060 1061 /* 1062 * Whether or not to use alt controls: volume effect sliders, EQ 1063 * presets, smart volume presets, and new control names with FX prefix. 1064 * Renames PlayEnhancement and CrystalVoice too. 1065 */ 1066 bool use_alt_controls; 1067 }; 1068 1069 /* 1070 * CA0132 quirks table 1071 */ 1072 enum { 1073 QUIRK_NONE, 1074 QUIRK_ALIENWARE, 1075 QUIRK_ALIENWARE_M17XR4, 1076 QUIRK_SBZ, 1077 QUIRK_ZXR, 1078 QUIRK_ZXR_DBPRO, 1079 QUIRK_R3DI, 1080 QUIRK_R3D, 1081 QUIRK_AE5, 1082 }; 1083 1084 static const struct hda_pintbl alienware_pincfgs[] = { 1085 { 0x0b, 0x90170110 }, /* Builtin Speaker */ 1086 { 0x0c, 0x411111f0 }, /* N/A */ 1087 { 0x0d, 0x411111f0 }, /* N/A */ 1088 { 0x0e, 0x411111f0 }, /* N/A */ 1089 { 0x0f, 0x0321101f }, /* HP */ 1090 { 0x10, 0x411111f0 }, /* Headset? disabled for now */ 1091 { 0x11, 0x03a11021 }, /* Mic */ 1092 { 0x12, 0xd5a30140 }, /* Builtin Mic */ 1093 { 0x13, 0x411111f0 }, /* N/A */ 1094 { 0x18, 0x411111f0 }, /* N/A */ 1095 {} 1096 }; 1097 1098 /* Sound Blaster Z pin configs taken from Windows Driver */ 1099 static const struct hda_pintbl sbz_pincfgs[] = { 1100 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1101 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1102 { 0x0d, 0x014510f0 }, /* Digital Out */ 1103 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1104 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */ 1105 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1106 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1107 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1108 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1109 { 0x18, 0x50d000f0 }, /* N/A */ 1110 {} 1111 }; 1112 1113 /* Sound Blaster ZxR pin configs taken from Windows Driver */ 1114 static const struct hda_pintbl zxr_pincfgs[] = { 1115 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */ 1116 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/ 1117 { 0x0d, 0x014510f0 }, /* Digital Out */ 1118 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/ 1119 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */ 1120 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */ 1121 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */ 1122 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */ 1123 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1124 { 0x18, 0x50d000f0 }, /* N/A */ 1125 {} 1126 }; 1127 1128 /* Recon3D pin configs taken from Windows Driver */ 1129 static const struct hda_pintbl r3d_pincfgs[] = { 1130 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1131 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1132 { 0x0d, 0x014510f0 }, /* Digital Out */ 1133 { 0x0e, 0x01c520f0 }, /* SPDIF In */ 1134 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1135 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1136 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1137 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1138 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1139 { 0x18, 0x50d000f0 }, /* N/A */ 1140 {} 1141 }; 1142 1143 /* Sound Blaster AE-5 pin configs taken from Windows Driver */ 1144 static const struct hda_pintbl ae5_pincfgs[] = { 1145 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1146 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1147 { 0x0d, 0x014510f0 }, /* Digital Out */ 1148 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1149 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */ 1150 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1151 { 0x11, 0x01a170ff }, /* Port B -- LineMicIn2 / Rear Headphone */ 1152 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1153 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1154 { 0x18, 0x50d000f0 }, /* N/A */ 1155 {} 1156 }; 1157 1158 /* Recon3D integrated pin configs taken from Windows Driver */ 1159 static const struct hda_pintbl r3di_pincfgs[] = { 1160 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1161 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1162 { 0x0d, 0x014510f0 }, /* Digital Out */ 1163 { 0x0e, 0x41c520f0 }, /* SPDIF In */ 1164 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1165 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1166 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1167 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1168 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1169 { 0x18, 0x500000f0 }, /* N/A */ 1170 {} 1171 }; 1172 1173 static const struct snd_pci_quirk ca0132_quirks[] = { 1174 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4), 1175 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE), 1176 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE), 1177 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE), 1178 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ), 1179 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ), 1180 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI), 1181 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI), 1182 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI), 1183 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D), 1184 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5), 1185 {} 1186 }; 1187 1188 /* 1189 * CA0132 codec access 1190 */ 1191 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid, 1192 unsigned int verb, unsigned int parm, unsigned int *res) 1193 { 1194 unsigned int response; 1195 response = snd_hda_codec_read(codec, nid, 0, verb, parm); 1196 *res = response; 1197 1198 return ((response == -1) ? -1 : 0); 1199 } 1200 1201 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid, 1202 unsigned short converter_format, unsigned int *res) 1203 { 1204 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT, 1205 converter_format & 0xffff, res); 1206 } 1207 1208 static int codec_set_converter_stream_channel(struct hda_codec *codec, 1209 hda_nid_t nid, unsigned char stream, 1210 unsigned char channel, unsigned int *res) 1211 { 1212 unsigned char converter_stream_channel = 0; 1213 1214 converter_stream_channel = (stream << 4) | (channel & 0x0f); 1215 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID, 1216 converter_stream_channel, res); 1217 } 1218 1219 /* Chip access helper function */ 1220 static int chipio_send(struct hda_codec *codec, 1221 unsigned int reg, 1222 unsigned int data) 1223 { 1224 unsigned int res; 1225 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1226 1227 /* send bits of data specified by reg */ 1228 do { 1229 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1230 reg, data); 1231 if (res == VENDOR_STATUS_CHIPIO_OK) 1232 return 0; 1233 msleep(20); 1234 } while (time_before(jiffies, timeout)); 1235 1236 return -EIO; 1237 } 1238 1239 /* 1240 * Write chip address through the vendor widget -- NOT protected by the Mutex! 1241 */ 1242 static int chipio_write_address(struct hda_codec *codec, 1243 unsigned int chip_addx) 1244 { 1245 struct ca0132_spec *spec = codec->spec; 1246 int res; 1247 1248 if (spec->curr_chip_addx == chip_addx) 1249 return 0; 1250 1251 /* send low 16 bits of the address */ 1252 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW, 1253 chip_addx & 0xffff); 1254 1255 if (res != -EIO) { 1256 /* send high 16 bits of the address */ 1257 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH, 1258 chip_addx >> 16); 1259 } 1260 1261 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx; 1262 1263 return res; 1264 } 1265 1266 /* 1267 * Write data through the vendor widget -- NOT protected by the Mutex! 1268 */ 1269 static int chipio_write_data(struct hda_codec *codec, unsigned int data) 1270 { 1271 struct ca0132_spec *spec = codec->spec; 1272 int res; 1273 1274 /* send low 16 bits of the data */ 1275 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff); 1276 1277 if (res != -EIO) { 1278 /* send high 16 bits of the data */ 1279 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH, 1280 data >> 16); 1281 } 1282 1283 /*If no error encountered, automatically increment the address 1284 as per chip behaviour*/ 1285 spec->curr_chip_addx = (res != -EIO) ? 1286 (spec->curr_chip_addx + 4) : ~0U; 1287 return res; 1288 } 1289 1290 /* 1291 * Write multiple data through the vendor widget -- NOT protected by the Mutex! 1292 */ 1293 static int chipio_write_data_multiple(struct hda_codec *codec, 1294 const u32 *data, 1295 unsigned int count) 1296 { 1297 int status = 0; 1298 1299 if (data == NULL) { 1300 codec_dbg(codec, "chipio_write_data null ptr\n"); 1301 return -EINVAL; 1302 } 1303 1304 while ((count-- != 0) && (status == 0)) 1305 status = chipio_write_data(codec, *data++); 1306 1307 return status; 1308 } 1309 1310 1311 /* 1312 * Read data through the vendor widget -- NOT protected by the Mutex! 1313 */ 1314 static int chipio_read_data(struct hda_codec *codec, unsigned int *data) 1315 { 1316 struct ca0132_spec *spec = codec->spec; 1317 int res; 1318 1319 /* post read */ 1320 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0); 1321 1322 if (res != -EIO) { 1323 /* read status */ 1324 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 1325 } 1326 1327 if (res != -EIO) { 1328 /* read data */ 1329 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1330 VENDOR_CHIPIO_HIC_READ_DATA, 1331 0); 1332 } 1333 1334 /*If no error encountered, automatically increment the address 1335 as per chip behaviour*/ 1336 spec->curr_chip_addx = (res != -EIO) ? 1337 (spec->curr_chip_addx + 4) : ~0U; 1338 return res; 1339 } 1340 1341 /* 1342 * Write given value to the given address through the chip I/O widget. 1343 * protected by the Mutex 1344 */ 1345 static int chipio_write(struct hda_codec *codec, 1346 unsigned int chip_addx, const unsigned int data) 1347 { 1348 struct ca0132_spec *spec = codec->spec; 1349 int err; 1350 1351 mutex_lock(&spec->chipio_mutex); 1352 1353 /* write the address, and if successful proceed to write data */ 1354 err = chipio_write_address(codec, chip_addx); 1355 if (err < 0) 1356 goto exit; 1357 1358 err = chipio_write_data(codec, data); 1359 if (err < 0) 1360 goto exit; 1361 1362 exit: 1363 mutex_unlock(&spec->chipio_mutex); 1364 return err; 1365 } 1366 1367 /* 1368 * Write given value to the given address through the chip I/O widget. 1369 * not protected by the Mutex 1370 */ 1371 static int chipio_write_no_mutex(struct hda_codec *codec, 1372 unsigned int chip_addx, const unsigned int data) 1373 { 1374 int err; 1375 1376 1377 /* write the address, and if successful proceed to write data */ 1378 err = chipio_write_address(codec, chip_addx); 1379 if (err < 0) 1380 goto exit; 1381 1382 err = chipio_write_data(codec, data); 1383 if (err < 0) 1384 goto exit; 1385 1386 exit: 1387 return err; 1388 } 1389 1390 /* 1391 * Write multiple values to the given address through the chip I/O widget. 1392 * protected by the Mutex 1393 */ 1394 static int chipio_write_multiple(struct hda_codec *codec, 1395 u32 chip_addx, 1396 const u32 *data, 1397 unsigned int count) 1398 { 1399 struct ca0132_spec *spec = codec->spec; 1400 int status; 1401 1402 mutex_lock(&spec->chipio_mutex); 1403 status = chipio_write_address(codec, chip_addx); 1404 if (status < 0) 1405 goto error; 1406 1407 status = chipio_write_data_multiple(codec, data, count); 1408 error: 1409 mutex_unlock(&spec->chipio_mutex); 1410 1411 return status; 1412 } 1413 1414 /* 1415 * Read the given address through the chip I/O widget 1416 * protected by the Mutex 1417 */ 1418 static int chipio_read(struct hda_codec *codec, 1419 unsigned int chip_addx, unsigned int *data) 1420 { 1421 struct ca0132_spec *spec = codec->spec; 1422 int err; 1423 1424 mutex_lock(&spec->chipio_mutex); 1425 1426 /* write the address, and if successful proceed to write data */ 1427 err = chipio_write_address(codec, chip_addx); 1428 if (err < 0) 1429 goto exit; 1430 1431 err = chipio_read_data(codec, data); 1432 if (err < 0) 1433 goto exit; 1434 1435 exit: 1436 mutex_unlock(&spec->chipio_mutex); 1437 return err; 1438 } 1439 1440 /* 1441 * Set chip control flags through the chip I/O widget. 1442 */ 1443 static void chipio_set_control_flag(struct hda_codec *codec, 1444 enum control_flag_id flag_id, 1445 bool flag_state) 1446 { 1447 unsigned int val; 1448 unsigned int flag_bit; 1449 1450 flag_bit = (flag_state ? 1 : 0); 1451 val = (flag_bit << 7) | (flag_id); 1452 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1453 VENDOR_CHIPIO_FLAG_SET, val); 1454 } 1455 1456 /* 1457 * Set chip parameters through the chip I/O widget. 1458 */ 1459 static void chipio_set_control_param(struct hda_codec *codec, 1460 enum control_param_id param_id, int param_val) 1461 { 1462 struct ca0132_spec *spec = codec->spec; 1463 int val; 1464 1465 if ((param_id < 32) && (param_val < 8)) { 1466 val = (param_val << 5) | (param_id); 1467 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1468 VENDOR_CHIPIO_PARAM_SET, val); 1469 } else { 1470 mutex_lock(&spec->chipio_mutex); 1471 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1472 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1473 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1474 param_id); 1475 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1476 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1477 param_val); 1478 } 1479 mutex_unlock(&spec->chipio_mutex); 1480 } 1481 } 1482 1483 /* 1484 * Set chip parameters through the chip I/O widget. NO MUTEX. 1485 */ 1486 static void chipio_set_control_param_no_mutex(struct hda_codec *codec, 1487 enum control_param_id param_id, int param_val) 1488 { 1489 int val; 1490 1491 if ((param_id < 32) && (param_val < 8)) { 1492 val = (param_val << 5) | (param_id); 1493 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1494 VENDOR_CHIPIO_PARAM_SET, val); 1495 } else { 1496 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1497 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1498 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1499 param_id); 1500 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1501 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1502 param_val); 1503 } 1504 } 1505 } 1506 /* 1507 * Connect stream to a source point, and then connect 1508 * that source point to a destination point. 1509 */ 1510 static void chipio_set_stream_source_dest(struct hda_codec *codec, 1511 int streamid, int source_point, int dest_point) 1512 { 1513 chipio_set_control_param_no_mutex(codec, 1514 CONTROL_PARAM_STREAM_ID, streamid); 1515 chipio_set_control_param_no_mutex(codec, 1516 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point); 1517 chipio_set_control_param_no_mutex(codec, 1518 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point); 1519 } 1520 1521 /* 1522 * Set number of channels in the selected stream. 1523 */ 1524 static void chipio_set_stream_channels(struct hda_codec *codec, 1525 int streamid, unsigned int channels) 1526 { 1527 chipio_set_control_param_no_mutex(codec, 1528 CONTROL_PARAM_STREAM_ID, streamid); 1529 chipio_set_control_param_no_mutex(codec, 1530 CONTROL_PARAM_STREAMS_CHANNELS, channels); 1531 } 1532 1533 /* 1534 * Enable/Disable audio stream. 1535 */ 1536 static void chipio_set_stream_control(struct hda_codec *codec, 1537 int streamid, int enable) 1538 { 1539 chipio_set_control_param_no_mutex(codec, 1540 CONTROL_PARAM_STREAM_ID, streamid); 1541 chipio_set_control_param_no_mutex(codec, 1542 CONTROL_PARAM_STREAM_CONTROL, enable); 1543 } 1544 1545 1546 /* 1547 * Set sampling rate of the connection point. NO MUTEX. 1548 */ 1549 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec, 1550 int connid, enum ca0132_sample_rate rate) 1551 { 1552 chipio_set_control_param_no_mutex(codec, 1553 CONTROL_PARAM_CONN_POINT_ID, connid); 1554 chipio_set_control_param_no_mutex(codec, 1555 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate); 1556 } 1557 1558 /* 1559 * Set sampling rate of the connection point. 1560 */ 1561 static void chipio_set_conn_rate(struct hda_codec *codec, 1562 int connid, enum ca0132_sample_rate rate) 1563 { 1564 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid); 1565 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, 1566 rate); 1567 } 1568 1569 /* 1570 * Writes to the 8051's internal address space directly instead of indirectly, 1571 * giving access to the special function registers located at addresses 1572 * 0x80-0xFF. 1573 */ 1574 static void chipio_8051_write_direct(struct hda_codec *codec, 1575 unsigned int addr, unsigned int data) 1576 { 1577 unsigned int verb; 1578 1579 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data; 1580 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr); 1581 } 1582 1583 /* 1584 * Enable clocks. 1585 */ 1586 static void chipio_enable_clocks(struct hda_codec *codec) 1587 { 1588 struct ca0132_spec *spec = codec->spec; 1589 1590 mutex_lock(&spec->chipio_mutex); 1591 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1592 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0); 1593 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1594 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); 1595 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1596 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5); 1597 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1598 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b); 1599 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1600 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6); 1601 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1602 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); 1603 mutex_unlock(&spec->chipio_mutex); 1604 } 1605 1606 /* 1607 * CA0132 DSP IO stuffs 1608 */ 1609 static int dspio_send(struct hda_codec *codec, unsigned int reg, 1610 unsigned int data) 1611 { 1612 int res; 1613 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1614 1615 /* send bits of data specified by reg to dsp */ 1616 do { 1617 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data); 1618 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY)) 1619 return res; 1620 msleep(20); 1621 } while (time_before(jiffies, timeout)); 1622 1623 return -EIO; 1624 } 1625 1626 /* 1627 * Wait for DSP to be ready for commands 1628 */ 1629 static void dspio_write_wait(struct hda_codec *codec) 1630 { 1631 int status; 1632 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1633 1634 do { 1635 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1636 VENDOR_DSPIO_STATUS, 0); 1637 if ((status == VENDOR_STATUS_DSPIO_OK) || 1638 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)) 1639 break; 1640 msleep(1); 1641 } while (time_before(jiffies, timeout)); 1642 } 1643 1644 /* 1645 * Write SCP data to DSP 1646 */ 1647 static int dspio_write(struct hda_codec *codec, unsigned int scp_data) 1648 { 1649 struct ca0132_spec *spec = codec->spec; 1650 int status; 1651 1652 dspio_write_wait(codec); 1653 1654 mutex_lock(&spec->chipio_mutex); 1655 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW, 1656 scp_data & 0xffff); 1657 if (status < 0) 1658 goto error; 1659 1660 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH, 1661 scp_data >> 16); 1662 if (status < 0) 1663 goto error; 1664 1665 /* OK, now check if the write itself has executed*/ 1666 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1667 VENDOR_DSPIO_STATUS, 0); 1668 error: 1669 mutex_unlock(&spec->chipio_mutex); 1670 1671 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ? 1672 -EIO : 0; 1673 } 1674 1675 /* 1676 * Write multiple SCP data to DSP 1677 */ 1678 static int dspio_write_multiple(struct hda_codec *codec, 1679 unsigned int *buffer, unsigned int size) 1680 { 1681 int status = 0; 1682 unsigned int count; 1683 1684 if (buffer == NULL) 1685 return -EINVAL; 1686 1687 count = 0; 1688 while (count < size) { 1689 status = dspio_write(codec, *buffer++); 1690 if (status != 0) 1691 break; 1692 count++; 1693 } 1694 1695 return status; 1696 } 1697 1698 static int dspio_read(struct hda_codec *codec, unsigned int *data) 1699 { 1700 int status; 1701 1702 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0); 1703 if (status == -EIO) 1704 return status; 1705 1706 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0); 1707 if (status == -EIO || 1708 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY) 1709 return -EIO; 1710 1711 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1712 VENDOR_DSPIO_SCP_READ_DATA, 0); 1713 1714 return 0; 1715 } 1716 1717 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer, 1718 unsigned int *buf_size, unsigned int size_count) 1719 { 1720 int status = 0; 1721 unsigned int size = *buf_size; 1722 unsigned int count; 1723 unsigned int skip_count; 1724 unsigned int dummy; 1725 1726 if (buffer == NULL) 1727 return -1; 1728 1729 count = 0; 1730 while (count < size && count < size_count) { 1731 status = dspio_read(codec, buffer++); 1732 if (status != 0) 1733 break; 1734 count++; 1735 } 1736 1737 skip_count = count; 1738 if (status == 0) { 1739 while (skip_count < size) { 1740 status = dspio_read(codec, &dummy); 1741 if (status != 0) 1742 break; 1743 skip_count++; 1744 } 1745 } 1746 *buf_size = count; 1747 1748 return status; 1749 } 1750 1751 /* 1752 * Construct the SCP header using corresponding fields 1753 */ 1754 static inline unsigned int 1755 make_scp_header(unsigned int target_id, unsigned int source_id, 1756 unsigned int get_flag, unsigned int req, 1757 unsigned int device_flag, unsigned int resp_flag, 1758 unsigned int error_flag, unsigned int data_size) 1759 { 1760 unsigned int header = 0; 1761 1762 header = (data_size & 0x1f) << 27; 1763 header |= (error_flag & 0x01) << 26; 1764 header |= (resp_flag & 0x01) << 25; 1765 header |= (device_flag & 0x01) << 24; 1766 header |= (req & 0x7f) << 17; 1767 header |= (get_flag & 0x01) << 16; 1768 header |= (source_id & 0xff) << 8; 1769 header |= target_id & 0xff; 1770 1771 return header; 1772 } 1773 1774 /* 1775 * Extract corresponding fields from SCP header 1776 */ 1777 static inline void 1778 extract_scp_header(unsigned int header, 1779 unsigned int *target_id, unsigned int *source_id, 1780 unsigned int *get_flag, unsigned int *req, 1781 unsigned int *device_flag, unsigned int *resp_flag, 1782 unsigned int *error_flag, unsigned int *data_size) 1783 { 1784 if (data_size) 1785 *data_size = (header >> 27) & 0x1f; 1786 if (error_flag) 1787 *error_flag = (header >> 26) & 0x01; 1788 if (resp_flag) 1789 *resp_flag = (header >> 25) & 0x01; 1790 if (device_flag) 1791 *device_flag = (header >> 24) & 0x01; 1792 if (req) 1793 *req = (header >> 17) & 0x7f; 1794 if (get_flag) 1795 *get_flag = (header >> 16) & 0x01; 1796 if (source_id) 1797 *source_id = (header >> 8) & 0xff; 1798 if (target_id) 1799 *target_id = header & 0xff; 1800 } 1801 1802 #define SCP_MAX_DATA_WORDS (16) 1803 1804 /* Structure to contain any SCP message */ 1805 struct scp_msg { 1806 unsigned int hdr; 1807 unsigned int data[SCP_MAX_DATA_WORDS]; 1808 }; 1809 1810 static void dspio_clear_response_queue(struct hda_codec *codec) 1811 { 1812 unsigned int dummy = 0; 1813 int status = -1; 1814 1815 /* clear all from the response queue */ 1816 do { 1817 status = dspio_read(codec, &dummy); 1818 } while (status == 0); 1819 } 1820 1821 static int dspio_get_response_data(struct hda_codec *codec) 1822 { 1823 struct ca0132_spec *spec = codec->spec; 1824 unsigned int data = 0; 1825 unsigned int count; 1826 1827 if (dspio_read(codec, &data) < 0) 1828 return -EIO; 1829 1830 if ((data & 0x00ffffff) == spec->wait_scp_header) { 1831 spec->scp_resp_header = data; 1832 spec->scp_resp_count = data >> 27; 1833 count = spec->wait_num_data; 1834 dspio_read_multiple(codec, spec->scp_resp_data, 1835 &spec->scp_resp_count, count); 1836 return 0; 1837 } 1838 1839 return -EIO; 1840 } 1841 1842 /* 1843 * Send SCP message to DSP 1844 */ 1845 static int dspio_send_scp_message(struct hda_codec *codec, 1846 unsigned char *send_buf, 1847 unsigned int send_buf_size, 1848 unsigned char *return_buf, 1849 unsigned int return_buf_size, 1850 unsigned int *bytes_returned) 1851 { 1852 struct ca0132_spec *spec = codec->spec; 1853 int status = -1; 1854 unsigned int scp_send_size = 0; 1855 unsigned int total_size; 1856 bool waiting_for_resp = false; 1857 unsigned int header; 1858 struct scp_msg *ret_msg; 1859 unsigned int resp_src_id, resp_target_id; 1860 unsigned int data_size, src_id, target_id, get_flag, device_flag; 1861 1862 if (bytes_returned) 1863 *bytes_returned = 0; 1864 1865 /* get scp header from buffer */ 1866 header = *((unsigned int *)send_buf); 1867 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL, 1868 &device_flag, NULL, NULL, &data_size); 1869 scp_send_size = data_size + 1; 1870 total_size = (scp_send_size * 4); 1871 1872 if (send_buf_size < total_size) 1873 return -EINVAL; 1874 1875 if (get_flag || device_flag) { 1876 if (!return_buf || return_buf_size < 4 || !bytes_returned) 1877 return -EINVAL; 1878 1879 spec->wait_scp_header = *((unsigned int *)send_buf); 1880 1881 /* swap source id with target id */ 1882 resp_target_id = src_id; 1883 resp_src_id = target_id; 1884 spec->wait_scp_header &= 0xffff0000; 1885 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id); 1886 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1; 1887 spec->wait_scp = 1; 1888 waiting_for_resp = true; 1889 } 1890 1891 status = dspio_write_multiple(codec, (unsigned int *)send_buf, 1892 scp_send_size); 1893 if (status < 0) { 1894 spec->wait_scp = 0; 1895 return status; 1896 } 1897 1898 if (waiting_for_resp) { 1899 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1900 memset(return_buf, 0, return_buf_size); 1901 do { 1902 msleep(20); 1903 } while (spec->wait_scp && time_before(jiffies, timeout)); 1904 waiting_for_resp = false; 1905 if (!spec->wait_scp) { 1906 ret_msg = (struct scp_msg *)return_buf; 1907 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4); 1908 memcpy(&ret_msg->data, spec->scp_resp_data, 1909 spec->wait_num_data); 1910 *bytes_returned = (spec->scp_resp_count + 1) * 4; 1911 status = 0; 1912 } else { 1913 status = -EIO; 1914 } 1915 spec->wait_scp = 0; 1916 } 1917 1918 return status; 1919 } 1920 1921 /** 1922 * Prepare and send the SCP message to DSP 1923 * @codec: the HDA codec 1924 * @mod_id: ID of the DSP module to send the command 1925 * @req: ID of request to send to the DSP module 1926 * @dir: SET or GET 1927 * @data: pointer to the data to send with the request, request specific 1928 * @len: length of the data, in bytes 1929 * @reply: point to the buffer to hold data returned for a reply 1930 * @reply_len: length of the reply buffer returned from GET 1931 * 1932 * Returns zero or a negative error code. 1933 */ 1934 static int dspio_scp(struct hda_codec *codec, 1935 int mod_id, int src_id, int req, int dir, const void *data, 1936 unsigned int len, void *reply, unsigned int *reply_len) 1937 { 1938 int status = 0; 1939 struct scp_msg scp_send, scp_reply; 1940 unsigned int ret_bytes, send_size, ret_size; 1941 unsigned int send_get_flag, reply_resp_flag, reply_error_flag; 1942 unsigned int reply_data_size; 1943 1944 memset(&scp_send, 0, sizeof(scp_send)); 1945 memset(&scp_reply, 0, sizeof(scp_reply)); 1946 1947 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS)) 1948 return -EINVAL; 1949 1950 if (dir == SCP_GET && reply == NULL) { 1951 codec_dbg(codec, "dspio_scp get but has no buffer\n"); 1952 return -EINVAL; 1953 } 1954 1955 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) { 1956 codec_dbg(codec, "dspio_scp bad resp buf len parms\n"); 1957 return -EINVAL; 1958 } 1959 1960 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req, 1961 0, 0, 0, len/sizeof(unsigned int)); 1962 if (data != NULL && len > 0) { 1963 len = min((unsigned int)(sizeof(scp_send.data)), len); 1964 memcpy(scp_send.data, data, len); 1965 } 1966 1967 ret_bytes = 0; 1968 send_size = sizeof(unsigned int) + len; 1969 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send, 1970 send_size, (unsigned char *)&scp_reply, 1971 sizeof(scp_reply), &ret_bytes); 1972 1973 if (status < 0) { 1974 codec_dbg(codec, "dspio_scp: send scp msg failed\n"); 1975 return status; 1976 } 1977 1978 /* extract send and reply headers members */ 1979 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag, 1980 NULL, NULL, NULL, NULL, NULL); 1981 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL, 1982 &reply_resp_flag, &reply_error_flag, 1983 &reply_data_size); 1984 1985 if (!send_get_flag) 1986 return 0; 1987 1988 if (reply_resp_flag && !reply_error_flag) { 1989 ret_size = (ret_bytes - sizeof(scp_reply.hdr)) 1990 / sizeof(unsigned int); 1991 1992 if (*reply_len < ret_size*sizeof(unsigned int)) { 1993 codec_dbg(codec, "reply too long for buf\n"); 1994 return -EINVAL; 1995 } else if (ret_size != reply_data_size) { 1996 codec_dbg(codec, "RetLen and HdrLen .NE.\n"); 1997 return -EINVAL; 1998 } else if (!reply) { 1999 codec_dbg(codec, "NULL reply\n"); 2000 return -EINVAL; 2001 } else { 2002 *reply_len = ret_size*sizeof(unsigned int); 2003 memcpy(reply, scp_reply.data, *reply_len); 2004 } 2005 } else { 2006 codec_dbg(codec, "reply ill-formed or errflag set\n"); 2007 return -EIO; 2008 } 2009 2010 return status; 2011 } 2012 2013 /* 2014 * Set DSP parameters 2015 */ 2016 static int dspio_set_param(struct hda_codec *codec, int mod_id, 2017 int src_id, int req, const void *data, unsigned int len) 2018 { 2019 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL, 2020 NULL); 2021 } 2022 2023 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id, 2024 int req, const unsigned int data) 2025 { 2026 return dspio_set_param(codec, mod_id, 0x20, req, &data, 2027 sizeof(unsigned int)); 2028 } 2029 2030 static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id, 2031 int req, const unsigned int data) 2032 { 2033 return dspio_set_param(codec, mod_id, 0x00, req, &data, 2034 sizeof(unsigned int)); 2035 } 2036 2037 /* 2038 * Allocate a DSP DMA channel via an SCP message 2039 */ 2040 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan) 2041 { 2042 int status = 0; 2043 unsigned int size = sizeof(dma_chan); 2044 2045 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n"); 2046 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2047 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0, 2048 dma_chan, &size); 2049 2050 if (status < 0) { 2051 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n"); 2052 return status; 2053 } 2054 2055 if ((*dma_chan + 1) == 0) { 2056 codec_dbg(codec, "no free dma channels to allocate\n"); 2057 return -EBUSY; 2058 } 2059 2060 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan); 2061 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n"); 2062 2063 return status; 2064 } 2065 2066 /* 2067 * Free a DSP DMA via an SCP message 2068 */ 2069 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan) 2070 { 2071 int status = 0; 2072 unsigned int dummy = 0; 2073 2074 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n"); 2075 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan); 2076 2077 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2078 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan, 2079 sizeof(dma_chan), NULL, &dummy); 2080 2081 if (status < 0) { 2082 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n"); 2083 return status; 2084 } 2085 2086 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n"); 2087 2088 return status; 2089 } 2090 2091 /* 2092 * (Re)start the DSP 2093 */ 2094 static int dsp_set_run_state(struct hda_codec *codec) 2095 { 2096 unsigned int dbg_ctrl_reg; 2097 unsigned int halt_state; 2098 int err; 2099 2100 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg); 2101 if (err < 0) 2102 return err; 2103 2104 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >> 2105 DSP_DBGCNTL_STATE_LOBIT; 2106 2107 if (halt_state != 0) { 2108 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) & 2109 DSP_DBGCNTL_SS_MASK); 2110 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2111 dbg_ctrl_reg); 2112 if (err < 0) 2113 return err; 2114 2115 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) & 2116 DSP_DBGCNTL_EXEC_MASK; 2117 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2118 dbg_ctrl_reg); 2119 if (err < 0) 2120 return err; 2121 } 2122 2123 return 0; 2124 } 2125 2126 /* 2127 * Reset the DSP 2128 */ 2129 static int dsp_reset(struct hda_codec *codec) 2130 { 2131 unsigned int res; 2132 int retry = 20; 2133 2134 codec_dbg(codec, "dsp_reset\n"); 2135 do { 2136 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0); 2137 retry--; 2138 } while (res == -EIO && retry); 2139 2140 if (!retry) { 2141 codec_dbg(codec, "dsp_reset timeout\n"); 2142 return -EIO; 2143 } 2144 2145 return 0; 2146 } 2147 2148 /* 2149 * Convert chip address to DSP address 2150 */ 2151 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx, 2152 bool *code, bool *yram) 2153 { 2154 *code = *yram = false; 2155 2156 if (UC_RANGE(chip_addx, 1)) { 2157 *code = true; 2158 return UC_OFF(chip_addx); 2159 } else if (X_RANGE_ALL(chip_addx, 1)) { 2160 return X_OFF(chip_addx); 2161 } else if (Y_RANGE_ALL(chip_addx, 1)) { 2162 *yram = true; 2163 return Y_OFF(chip_addx); 2164 } 2165 2166 return INVALID_CHIP_ADDRESS; 2167 } 2168 2169 /* 2170 * Check if the DSP DMA is active 2171 */ 2172 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan) 2173 { 2174 unsigned int dma_chnlstart_reg; 2175 2176 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg); 2177 2178 return ((dma_chnlstart_reg & (1 << 2179 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0); 2180 } 2181 2182 static int dsp_dma_setup_common(struct hda_codec *codec, 2183 unsigned int chip_addx, 2184 unsigned int dma_chan, 2185 unsigned int port_map_mask, 2186 bool ovly) 2187 { 2188 int status = 0; 2189 unsigned int chnl_prop; 2190 unsigned int dsp_addx; 2191 unsigned int active; 2192 bool code, yram; 2193 2194 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n"); 2195 2196 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) { 2197 codec_dbg(codec, "dma chan num invalid\n"); 2198 return -EINVAL; 2199 } 2200 2201 if (dsp_is_dma_active(codec, dma_chan)) { 2202 codec_dbg(codec, "dma already active\n"); 2203 return -EBUSY; 2204 } 2205 2206 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2207 2208 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2209 codec_dbg(codec, "invalid chip addr\n"); 2210 return -ENXIO; 2211 } 2212 2213 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK; 2214 active = 0; 2215 2216 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n"); 2217 2218 if (ovly) { 2219 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET, 2220 &chnl_prop); 2221 2222 if (status < 0) { 2223 codec_dbg(codec, "read CHNLPROP Reg fail\n"); 2224 return status; 2225 } 2226 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n"); 2227 } 2228 2229 if (!code) 2230 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2231 else 2232 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2233 2234 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan)); 2235 2236 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop); 2237 if (status < 0) { 2238 codec_dbg(codec, "write CHNLPROP Reg fail\n"); 2239 return status; 2240 } 2241 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n"); 2242 2243 if (ovly) { 2244 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET, 2245 &active); 2246 2247 if (status < 0) { 2248 codec_dbg(codec, "read ACTIVE Reg fail\n"); 2249 return status; 2250 } 2251 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n"); 2252 } 2253 2254 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) & 2255 DSPDMAC_ACTIVE_AAR_MASK; 2256 2257 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active); 2258 if (status < 0) { 2259 codec_dbg(codec, "write ACTIVE Reg fail\n"); 2260 return status; 2261 } 2262 2263 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n"); 2264 2265 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan), 2266 port_map_mask); 2267 if (status < 0) { 2268 codec_dbg(codec, "write AUDCHSEL Reg fail\n"); 2269 return status; 2270 } 2271 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n"); 2272 2273 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan), 2274 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK); 2275 if (status < 0) { 2276 codec_dbg(codec, "write IRQCNT Reg fail\n"); 2277 return status; 2278 } 2279 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n"); 2280 2281 codec_dbg(codec, 2282 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, " 2283 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n", 2284 chip_addx, dsp_addx, dma_chan, 2285 port_map_mask, chnl_prop, active); 2286 2287 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n"); 2288 2289 return 0; 2290 } 2291 2292 /* 2293 * Setup the DSP DMA per-transfer-specific registers 2294 */ 2295 static int dsp_dma_setup(struct hda_codec *codec, 2296 unsigned int chip_addx, 2297 unsigned int count, 2298 unsigned int dma_chan) 2299 { 2300 int status = 0; 2301 bool code, yram; 2302 unsigned int dsp_addx; 2303 unsigned int addr_field; 2304 unsigned int incr_field; 2305 unsigned int base_cnt; 2306 unsigned int cur_cnt; 2307 unsigned int dma_cfg = 0; 2308 unsigned int adr_ofs = 0; 2309 unsigned int xfr_cnt = 0; 2310 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT - 2311 DSPDMAC_XFRCNT_BCNT_LOBIT + 1); 2312 2313 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n"); 2314 2315 if (count > max_dma_count) { 2316 codec_dbg(codec, "count too big\n"); 2317 return -EINVAL; 2318 } 2319 2320 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2321 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2322 codec_dbg(codec, "invalid chip addr\n"); 2323 return -ENXIO; 2324 } 2325 2326 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n"); 2327 2328 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT; 2329 incr_field = 0; 2330 2331 if (!code) { 2332 addr_field <<= 1; 2333 if (yram) 2334 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT); 2335 2336 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT); 2337 } 2338 2339 dma_cfg = addr_field + incr_field; 2340 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan), 2341 dma_cfg); 2342 if (status < 0) { 2343 codec_dbg(codec, "write DMACFG Reg fail\n"); 2344 return status; 2345 } 2346 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n"); 2347 2348 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT + 2349 (code ? 0 : 1)); 2350 2351 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan), 2352 adr_ofs); 2353 if (status < 0) { 2354 codec_dbg(codec, "write DSPADROFS Reg fail\n"); 2355 return status; 2356 } 2357 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n"); 2358 2359 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT; 2360 2361 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT; 2362 2363 xfr_cnt = base_cnt | cur_cnt; 2364 2365 status = chipio_write(codec, 2366 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt); 2367 if (status < 0) { 2368 codec_dbg(codec, "write XFRCNT Reg fail\n"); 2369 return status; 2370 } 2371 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n"); 2372 2373 codec_dbg(codec, 2374 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, " 2375 "ADROFS=0x%x, XFRCNT=0x%x\n", 2376 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt); 2377 2378 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n"); 2379 2380 return 0; 2381 } 2382 2383 /* 2384 * Start the DSP DMA 2385 */ 2386 static int dsp_dma_start(struct hda_codec *codec, 2387 unsigned int dma_chan, bool ovly) 2388 { 2389 unsigned int reg = 0; 2390 int status = 0; 2391 2392 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n"); 2393 2394 if (ovly) { 2395 status = chipio_read(codec, 2396 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2397 2398 if (status < 0) { 2399 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2400 return status; 2401 } 2402 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n"); 2403 2404 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2405 DSPDMAC_CHNLSTART_DIS_MASK); 2406 } 2407 2408 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2409 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT))); 2410 if (status < 0) { 2411 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2412 return status; 2413 } 2414 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n"); 2415 2416 return status; 2417 } 2418 2419 /* 2420 * Stop the DSP DMA 2421 */ 2422 static int dsp_dma_stop(struct hda_codec *codec, 2423 unsigned int dma_chan, bool ovly) 2424 { 2425 unsigned int reg = 0; 2426 int status = 0; 2427 2428 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n"); 2429 2430 if (ovly) { 2431 status = chipio_read(codec, 2432 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2433 2434 if (status < 0) { 2435 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2436 return status; 2437 } 2438 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n"); 2439 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2440 DSPDMAC_CHNLSTART_DIS_MASK); 2441 } 2442 2443 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2444 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT))); 2445 if (status < 0) { 2446 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2447 return status; 2448 } 2449 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n"); 2450 2451 return status; 2452 } 2453 2454 /** 2455 * Allocate router ports 2456 * 2457 * @codec: the HDA codec 2458 * @num_chans: number of channels in the stream 2459 * @ports_per_channel: number of ports per channel 2460 * @start_device: start device 2461 * @port_map: pointer to the port list to hold the allocated ports 2462 * 2463 * Returns zero or a negative error code. 2464 */ 2465 static int dsp_allocate_router_ports(struct hda_codec *codec, 2466 unsigned int num_chans, 2467 unsigned int ports_per_channel, 2468 unsigned int start_device, 2469 unsigned int *port_map) 2470 { 2471 int status = 0; 2472 int res; 2473 u8 val; 2474 2475 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2476 if (status < 0) 2477 return status; 2478 2479 val = start_device << 6; 2480 val |= (ports_per_channel - 1) << 4; 2481 val |= num_chans - 1; 2482 2483 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2484 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET, 2485 val); 2486 2487 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2488 VENDOR_CHIPIO_PORT_ALLOC_SET, 2489 MEM_CONNID_DSP); 2490 2491 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2492 if (status < 0) 2493 return status; 2494 2495 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 2496 VENDOR_CHIPIO_PORT_ALLOC_GET, 0); 2497 2498 *port_map = res; 2499 2500 return (res < 0) ? res : 0; 2501 } 2502 2503 /* 2504 * Free router ports 2505 */ 2506 static int dsp_free_router_ports(struct hda_codec *codec) 2507 { 2508 int status = 0; 2509 2510 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2511 if (status < 0) 2512 return status; 2513 2514 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2515 VENDOR_CHIPIO_PORT_FREE_SET, 2516 MEM_CONNID_DSP); 2517 2518 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2519 2520 return status; 2521 } 2522 2523 /* 2524 * Allocate DSP ports for the download stream 2525 */ 2526 static int dsp_allocate_ports(struct hda_codec *codec, 2527 unsigned int num_chans, 2528 unsigned int rate_multi, unsigned int *port_map) 2529 { 2530 int status; 2531 2532 codec_dbg(codec, " dsp_allocate_ports() -- begin\n"); 2533 2534 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2535 codec_dbg(codec, "bad rate multiple\n"); 2536 return -EINVAL; 2537 } 2538 2539 status = dsp_allocate_router_ports(codec, num_chans, 2540 rate_multi, 0, port_map); 2541 2542 codec_dbg(codec, " dsp_allocate_ports() -- complete\n"); 2543 2544 return status; 2545 } 2546 2547 static int dsp_allocate_ports_format(struct hda_codec *codec, 2548 const unsigned short fmt, 2549 unsigned int *port_map) 2550 { 2551 int status; 2552 unsigned int num_chans; 2553 2554 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1; 2555 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1; 2556 unsigned int rate_multi = sample_rate_mul / sample_rate_div; 2557 2558 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2559 codec_dbg(codec, "bad rate multiple\n"); 2560 return -EINVAL; 2561 } 2562 2563 num_chans = get_hdafmt_chs(fmt) + 1; 2564 2565 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map); 2566 2567 return status; 2568 } 2569 2570 /* 2571 * free DSP ports 2572 */ 2573 static int dsp_free_ports(struct hda_codec *codec) 2574 { 2575 int status; 2576 2577 codec_dbg(codec, " dsp_free_ports() -- begin\n"); 2578 2579 status = dsp_free_router_ports(codec); 2580 if (status < 0) { 2581 codec_dbg(codec, "free router ports fail\n"); 2582 return status; 2583 } 2584 codec_dbg(codec, " dsp_free_ports() -- complete\n"); 2585 2586 return status; 2587 } 2588 2589 /* 2590 * HDA DMA engine stuffs for DSP code download 2591 */ 2592 struct dma_engine { 2593 struct hda_codec *codec; 2594 unsigned short m_converter_format; 2595 struct snd_dma_buffer *dmab; 2596 unsigned int buf_size; 2597 }; 2598 2599 2600 enum dma_state { 2601 DMA_STATE_STOP = 0, 2602 DMA_STATE_RUN = 1 2603 }; 2604 2605 static int dma_convert_to_hda_format(struct hda_codec *codec, 2606 unsigned int sample_rate, 2607 unsigned short channels, 2608 unsigned short *hda_format) 2609 { 2610 unsigned int format_val; 2611 2612 format_val = snd_hdac_calc_stream_format(sample_rate, 2613 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0); 2614 2615 if (hda_format) 2616 *hda_format = (unsigned short)format_val; 2617 2618 return 0; 2619 } 2620 2621 /* 2622 * Reset DMA for DSP download 2623 */ 2624 static int dma_reset(struct dma_engine *dma) 2625 { 2626 struct hda_codec *codec = dma->codec; 2627 struct ca0132_spec *spec = codec->spec; 2628 int status; 2629 2630 if (dma->dmab->area) 2631 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab); 2632 2633 status = snd_hda_codec_load_dsp_prepare(codec, 2634 dma->m_converter_format, 2635 dma->buf_size, 2636 dma->dmab); 2637 if (status < 0) 2638 return status; 2639 spec->dsp_stream_id = status; 2640 return 0; 2641 } 2642 2643 static int dma_set_state(struct dma_engine *dma, enum dma_state state) 2644 { 2645 bool cmd; 2646 2647 switch (state) { 2648 case DMA_STATE_STOP: 2649 cmd = false; 2650 break; 2651 case DMA_STATE_RUN: 2652 cmd = true; 2653 break; 2654 default: 2655 return 0; 2656 } 2657 2658 snd_hda_codec_load_dsp_trigger(dma->codec, cmd); 2659 return 0; 2660 } 2661 2662 static unsigned int dma_get_buffer_size(struct dma_engine *dma) 2663 { 2664 return dma->dmab->bytes; 2665 } 2666 2667 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma) 2668 { 2669 return dma->dmab->area; 2670 } 2671 2672 static int dma_xfer(struct dma_engine *dma, 2673 const unsigned int *data, 2674 unsigned int count) 2675 { 2676 memcpy(dma->dmab->area, data, count); 2677 return 0; 2678 } 2679 2680 static void dma_get_converter_format( 2681 struct dma_engine *dma, 2682 unsigned short *format) 2683 { 2684 if (format) 2685 *format = dma->m_converter_format; 2686 } 2687 2688 static unsigned int dma_get_stream_id(struct dma_engine *dma) 2689 { 2690 struct ca0132_spec *spec = dma->codec->spec; 2691 2692 return spec->dsp_stream_id; 2693 } 2694 2695 struct dsp_image_seg { 2696 u32 magic; 2697 u32 chip_addr; 2698 u32 count; 2699 u32 data[0]; 2700 }; 2701 2702 static const u32 g_magic_value = 0x4c46584d; 2703 static const u32 g_chip_addr_magic_value = 0xFFFFFF01; 2704 2705 static bool is_valid(const struct dsp_image_seg *p) 2706 { 2707 return p->magic == g_magic_value; 2708 } 2709 2710 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p) 2711 { 2712 return g_chip_addr_magic_value == p->chip_addr; 2713 } 2714 2715 static bool is_last(const struct dsp_image_seg *p) 2716 { 2717 return p->count == 0; 2718 } 2719 2720 static size_t dsp_sizeof(const struct dsp_image_seg *p) 2721 { 2722 return sizeof(*p) + p->count*sizeof(u32); 2723 } 2724 2725 static const struct dsp_image_seg *get_next_seg_ptr( 2726 const struct dsp_image_seg *p) 2727 { 2728 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p)); 2729 } 2730 2731 /* 2732 * CA0132 chip DSP transfer stuffs. For DSP download. 2733 */ 2734 #define INVALID_DMA_CHANNEL (~0U) 2735 2736 /* 2737 * Program a list of address/data pairs via the ChipIO widget. 2738 * The segment data is in the format of successive pairs of words. 2739 * These are repeated as indicated by the segment's count field. 2740 */ 2741 static int dspxfr_hci_write(struct hda_codec *codec, 2742 const struct dsp_image_seg *fls) 2743 { 2744 int status; 2745 const u32 *data; 2746 unsigned int count; 2747 2748 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) { 2749 codec_dbg(codec, "hci_write invalid params\n"); 2750 return -EINVAL; 2751 } 2752 2753 count = fls->count; 2754 data = (u32 *)(fls->data); 2755 while (count >= 2) { 2756 status = chipio_write(codec, data[0], data[1]); 2757 if (status < 0) { 2758 codec_dbg(codec, "hci_write chipio failed\n"); 2759 return status; 2760 } 2761 count -= 2; 2762 data += 2; 2763 } 2764 return 0; 2765 } 2766 2767 /** 2768 * Write a block of data into DSP code or data RAM using pre-allocated 2769 * DMA engine. 2770 * 2771 * @codec: the HDA codec 2772 * @fls: pointer to a fast load image 2773 * @reloc: Relocation address for loading single-segment overlays, or 0 for 2774 * no relocation 2775 * @dma_engine: pointer to DMA engine to be used for DSP download 2776 * @dma_chan: The number of DMA channels used for DSP download 2777 * @port_map_mask: port mapping 2778 * @ovly: TRUE if overlay format is required 2779 * 2780 * Returns zero or a negative error code. 2781 */ 2782 static int dspxfr_one_seg(struct hda_codec *codec, 2783 const struct dsp_image_seg *fls, 2784 unsigned int reloc, 2785 struct dma_engine *dma_engine, 2786 unsigned int dma_chan, 2787 unsigned int port_map_mask, 2788 bool ovly) 2789 { 2790 int status = 0; 2791 bool comm_dma_setup_done = false; 2792 const unsigned int *data; 2793 unsigned int chip_addx; 2794 unsigned int words_to_write; 2795 unsigned int buffer_size_words; 2796 unsigned char *buffer_addx; 2797 unsigned short hda_format; 2798 unsigned int sample_rate_div; 2799 unsigned int sample_rate_mul; 2800 unsigned int num_chans; 2801 unsigned int hda_frame_size_words; 2802 unsigned int remainder_words; 2803 const u32 *data_remainder; 2804 u32 chip_addx_remainder; 2805 unsigned int run_size_words; 2806 const struct dsp_image_seg *hci_write = NULL; 2807 unsigned long timeout; 2808 bool dma_active; 2809 2810 if (fls == NULL) 2811 return -EINVAL; 2812 if (is_hci_prog_list_seg(fls)) { 2813 hci_write = fls; 2814 fls = get_next_seg_ptr(fls); 2815 } 2816 2817 if (hci_write && (!fls || is_last(fls))) { 2818 codec_dbg(codec, "hci_write\n"); 2819 return dspxfr_hci_write(codec, hci_write); 2820 } 2821 2822 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) { 2823 codec_dbg(codec, "Invalid Params\n"); 2824 return -EINVAL; 2825 } 2826 2827 data = fls->data; 2828 chip_addx = fls->chip_addr, 2829 words_to_write = fls->count; 2830 2831 if (!words_to_write) 2832 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0; 2833 if (reloc) 2834 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2); 2835 2836 if (!UC_RANGE(chip_addx, words_to_write) && 2837 !X_RANGE_ALL(chip_addx, words_to_write) && 2838 !Y_RANGE_ALL(chip_addx, words_to_write)) { 2839 codec_dbg(codec, "Invalid chip_addx Params\n"); 2840 return -EINVAL; 2841 } 2842 2843 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) / 2844 sizeof(u32); 2845 2846 buffer_addx = dma_get_buffer_addr(dma_engine); 2847 2848 if (buffer_addx == NULL) { 2849 codec_dbg(codec, "dma_engine buffer NULL\n"); 2850 return -EINVAL; 2851 } 2852 2853 dma_get_converter_format(dma_engine, &hda_format); 2854 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1; 2855 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1; 2856 num_chans = get_hdafmt_chs(hda_format) + 1; 2857 2858 hda_frame_size_words = ((sample_rate_div == 0) ? 0 : 2859 (num_chans * sample_rate_mul / sample_rate_div)); 2860 2861 if (hda_frame_size_words == 0) { 2862 codec_dbg(codec, "frmsz zero\n"); 2863 return -EINVAL; 2864 } 2865 2866 buffer_size_words = min(buffer_size_words, 2867 (unsigned int)(UC_RANGE(chip_addx, 1) ? 2868 65536 : 32768)); 2869 buffer_size_words -= buffer_size_words % hda_frame_size_words; 2870 codec_dbg(codec, 2871 "chpadr=0x%08x frmsz=%u nchan=%u " 2872 "rate_mul=%u div=%u bufsz=%u\n", 2873 chip_addx, hda_frame_size_words, num_chans, 2874 sample_rate_mul, sample_rate_div, buffer_size_words); 2875 2876 if (buffer_size_words < hda_frame_size_words) { 2877 codec_dbg(codec, "dspxfr_one_seg:failed\n"); 2878 return -EINVAL; 2879 } 2880 2881 remainder_words = words_to_write % hda_frame_size_words; 2882 data_remainder = data; 2883 chip_addx_remainder = chip_addx; 2884 2885 data += remainder_words; 2886 chip_addx += remainder_words*sizeof(u32); 2887 words_to_write -= remainder_words; 2888 2889 while (words_to_write != 0) { 2890 run_size_words = min(buffer_size_words, words_to_write); 2891 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n", 2892 words_to_write, run_size_words, remainder_words); 2893 dma_xfer(dma_engine, data, run_size_words*sizeof(u32)); 2894 if (!comm_dma_setup_done) { 2895 status = dsp_dma_stop(codec, dma_chan, ovly); 2896 if (status < 0) 2897 return status; 2898 status = dsp_dma_setup_common(codec, chip_addx, 2899 dma_chan, port_map_mask, ovly); 2900 if (status < 0) 2901 return status; 2902 comm_dma_setup_done = true; 2903 } 2904 2905 status = dsp_dma_setup(codec, chip_addx, 2906 run_size_words, dma_chan); 2907 if (status < 0) 2908 return status; 2909 status = dsp_dma_start(codec, dma_chan, ovly); 2910 if (status < 0) 2911 return status; 2912 if (!dsp_is_dma_active(codec, dma_chan)) { 2913 codec_dbg(codec, "dspxfr:DMA did not start\n"); 2914 return -EIO; 2915 } 2916 status = dma_set_state(dma_engine, DMA_STATE_RUN); 2917 if (status < 0) 2918 return status; 2919 if (remainder_words != 0) { 2920 status = chipio_write_multiple(codec, 2921 chip_addx_remainder, 2922 data_remainder, 2923 remainder_words); 2924 if (status < 0) 2925 return status; 2926 remainder_words = 0; 2927 } 2928 if (hci_write) { 2929 status = dspxfr_hci_write(codec, hci_write); 2930 if (status < 0) 2931 return status; 2932 hci_write = NULL; 2933 } 2934 2935 timeout = jiffies + msecs_to_jiffies(2000); 2936 do { 2937 dma_active = dsp_is_dma_active(codec, dma_chan); 2938 if (!dma_active) 2939 break; 2940 msleep(20); 2941 } while (time_before(jiffies, timeout)); 2942 if (dma_active) 2943 break; 2944 2945 codec_dbg(codec, "+++++ DMA complete\n"); 2946 dma_set_state(dma_engine, DMA_STATE_STOP); 2947 status = dma_reset(dma_engine); 2948 2949 if (status < 0) 2950 return status; 2951 2952 data += run_size_words; 2953 chip_addx += run_size_words*sizeof(u32); 2954 words_to_write -= run_size_words; 2955 } 2956 2957 if (remainder_words != 0) { 2958 status = chipio_write_multiple(codec, chip_addx_remainder, 2959 data_remainder, remainder_words); 2960 } 2961 2962 return status; 2963 } 2964 2965 /** 2966 * Write the entire DSP image of a DSP code/data overlay to DSP memories 2967 * 2968 * @codec: the HDA codec 2969 * @fls_data: pointer to a fast load image 2970 * @reloc: Relocation address for loading single-segment overlays, or 0 for 2971 * no relocation 2972 * @sample_rate: sampling rate of the stream used for DSP download 2973 * @channels: channels of the stream used for DSP download 2974 * @ovly: TRUE if overlay format is required 2975 * 2976 * Returns zero or a negative error code. 2977 */ 2978 static int dspxfr_image(struct hda_codec *codec, 2979 const struct dsp_image_seg *fls_data, 2980 unsigned int reloc, 2981 unsigned int sample_rate, 2982 unsigned short channels, 2983 bool ovly) 2984 { 2985 struct ca0132_spec *spec = codec->spec; 2986 int status; 2987 unsigned short hda_format = 0; 2988 unsigned int response; 2989 unsigned char stream_id = 0; 2990 struct dma_engine *dma_engine; 2991 unsigned int dma_chan; 2992 unsigned int port_map_mask; 2993 2994 if (fls_data == NULL) 2995 return -EINVAL; 2996 2997 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL); 2998 if (!dma_engine) 2999 return -ENOMEM; 3000 3001 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL); 3002 if (!dma_engine->dmab) { 3003 kfree(dma_engine); 3004 return -ENOMEM; 3005 } 3006 3007 dma_engine->codec = codec; 3008 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format); 3009 dma_engine->m_converter_format = hda_format; 3010 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY : 3011 DSP_DMA_WRITE_BUFLEN_INIT) * 2; 3012 3013 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0; 3014 3015 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL, 3016 hda_format, &response); 3017 3018 if (status < 0) { 3019 codec_dbg(codec, "set converter format fail\n"); 3020 goto exit; 3021 } 3022 3023 status = snd_hda_codec_load_dsp_prepare(codec, 3024 dma_engine->m_converter_format, 3025 dma_engine->buf_size, 3026 dma_engine->dmab); 3027 if (status < 0) 3028 goto exit; 3029 spec->dsp_stream_id = status; 3030 3031 if (ovly) { 3032 status = dspio_alloc_dma_chan(codec, &dma_chan); 3033 if (status < 0) { 3034 codec_dbg(codec, "alloc dmachan fail\n"); 3035 dma_chan = INVALID_DMA_CHANNEL; 3036 goto exit; 3037 } 3038 } 3039 3040 port_map_mask = 0; 3041 status = dsp_allocate_ports_format(codec, hda_format, 3042 &port_map_mask); 3043 if (status < 0) { 3044 codec_dbg(codec, "alloc ports fail\n"); 3045 goto exit; 3046 } 3047 3048 stream_id = dma_get_stream_id(dma_engine); 3049 status = codec_set_converter_stream_channel(codec, 3050 WIDGET_CHIP_CTRL, stream_id, 0, &response); 3051 if (status < 0) { 3052 codec_dbg(codec, "set stream chan fail\n"); 3053 goto exit; 3054 } 3055 3056 while ((fls_data != NULL) && !is_last(fls_data)) { 3057 if (!is_valid(fls_data)) { 3058 codec_dbg(codec, "FLS check fail\n"); 3059 status = -EINVAL; 3060 goto exit; 3061 } 3062 status = dspxfr_one_seg(codec, fls_data, reloc, 3063 dma_engine, dma_chan, 3064 port_map_mask, ovly); 3065 if (status < 0) 3066 break; 3067 3068 if (is_hci_prog_list_seg(fls_data)) 3069 fls_data = get_next_seg_ptr(fls_data); 3070 3071 if ((fls_data != NULL) && !is_last(fls_data)) 3072 fls_data = get_next_seg_ptr(fls_data); 3073 } 3074 3075 if (port_map_mask != 0) 3076 status = dsp_free_ports(codec); 3077 3078 if (status < 0) 3079 goto exit; 3080 3081 status = codec_set_converter_stream_channel(codec, 3082 WIDGET_CHIP_CTRL, 0, 0, &response); 3083 3084 exit: 3085 if (ovly && (dma_chan != INVALID_DMA_CHANNEL)) 3086 dspio_free_dma_chan(codec, dma_chan); 3087 3088 if (dma_engine->dmab->area) 3089 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab); 3090 kfree(dma_engine->dmab); 3091 kfree(dma_engine); 3092 3093 return status; 3094 } 3095 3096 /* 3097 * CA0132 DSP download stuffs. 3098 */ 3099 static void dspload_post_setup(struct hda_codec *codec) 3100 { 3101 struct ca0132_spec *spec = codec->spec; 3102 codec_dbg(codec, "---- dspload_post_setup ------\n"); 3103 if (!spec->use_alt_functions) { 3104 /*set DSP speaker to 2.0 configuration*/ 3105 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080); 3106 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000); 3107 3108 /*update write pointer*/ 3109 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002); 3110 } 3111 } 3112 3113 /** 3114 * dspload_image - Download DSP from a DSP Image Fast Load structure. 3115 * 3116 * @codec: the HDA codec 3117 * @fls: pointer to a fast load image 3118 * @ovly: TRUE if overlay format is required 3119 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3120 * no relocation 3121 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE 3122 * @router_chans: number of audio router channels to be allocated (0 means use 3123 * internal defaults; max is 32) 3124 * 3125 * Download DSP from a DSP Image Fast Load structure. This structure is a 3126 * linear, non-constant sized element array of structures, each of which 3127 * contain the count of the data to be loaded, the data itself, and the 3128 * corresponding starting chip address of the starting data location. 3129 * Returns zero or a negative error code. 3130 */ 3131 static int dspload_image(struct hda_codec *codec, 3132 const struct dsp_image_seg *fls, 3133 bool ovly, 3134 unsigned int reloc, 3135 bool autostart, 3136 int router_chans) 3137 { 3138 int status = 0; 3139 unsigned int sample_rate; 3140 unsigned short channels; 3141 3142 codec_dbg(codec, "---- dspload_image begin ------\n"); 3143 if (router_chans == 0) { 3144 if (!ovly) 3145 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS; 3146 else 3147 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS; 3148 } 3149 3150 sample_rate = 48000; 3151 channels = (unsigned short)router_chans; 3152 3153 while (channels > 16) { 3154 sample_rate *= 2; 3155 channels /= 2; 3156 } 3157 3158 do { 3159 codec_dbg(codec, "Ready to program DMA\n"); 3160 if (!ovly) 3161 status = dsp_reset(codec); 3162 3163 if (status < 0) 3164 break; 3165 3166 codec_dbg(codec, "dsp_reset() complete\n"); 3167 status = dspxfr_image(codec, fls, reloc, sample_rate, channels, 3168 ovly); 3169 3170 if (status < 0) 3171 break; 3172 3173 codec_dbg(codec, "dspxfr_image() complete\n"); 3174 if (autostart && !ovly) { 3175 dspload_post_setup(codec); 3176 status = dsp_set_run_state(codec); 3177 } 3178 3179 codec_dbg(codec, "LOAD FINISHED\n"); 3180 } while (0); 3181 3182 return status; 3183 } 3184 3185 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 3186 static bool dspload_is_loaded(struct hda_codec *codec) 3187 { 3188 unsigned int data = 0; 3189 int status = 0; 3190 3191 status = chipio_read(codec, 0x40004, &data); 3192 if ((status < 0) || (data != 1)) 3193 return false; 3194 3195 return true; 3196 } 3197 #else 3198 #define dspload_is_loaded(codec) false 3199 #endif 3200 3201 static bool dspload_wait_loaded(struct hda_codec *codec) 3202 { 3203 unsigned long timeout = jiffies + msecs_to_jiffies(2000); 3204 3205 do { 3206 if (dspload_is_loaded(codec)) { 3207 codec_info(codec, "ca0132 DSP downloaded and running\n"); 3208 return true; 3209 } 3210 msleep(20); 3211 } while (time_before(jiffies, timeout)); 3212 3213 codec_err(codec, "ca0132 failed to download DSP\n"); 3214 return false; 3215 } 3216 3217 /* 3218 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e 3219 * based cards, and has a second mmio region, region2, that's used for special 3220 * commands. 3221 */ 3222 3223 /* 3224 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5) 3225 * the mmio address 0x320 is used to set GPIO pins. The format for the data 3226 * The first eight bits are just the number of the pin. So far, I've only seen 3227 * this number go to 7. 3228 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value 3229 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and 3230 * then off to send that bit. 3231 */ 3232 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin, 3233 bool enable) 3234 { 3235 struct ca0132_spec *spec = codec->spec; 3236 unsigned short gpio_data; 3237 3238 gpio_data = gpio_pin & 0xF; 3239 gpio_data |= ((enable << 8) & 0x100); 3240 3241 writew(gpio_data, spec->mem_base + 0x320); 3242 } 3243 3244 /* 3245 * Special pci region2 commands that are only used by the AE-5. They follow 3246 * a set format, and require reads at certain points to seemingly 'clear' 3247 * the response data. My first tests didn't do these reads, and would cause 3248 * the card to get locked up until the memory was read. These commands 3249 * seem to work with three distinct values that I've taken to calling group, 3250 * target-id, and value. 3251 */ 3252 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group, 3253 unsigned int target, unsigned int value) 3254 { 3255 struct ca0132_spec *spec = codec->spec; 3256 unsigned int write_val; 3257 3258 writel(0x0000007e, spec->mem_base + 0x210); 3259 readl(spec->mem_base + 0x210); 3260 writel(0x0000005a, spec->mem_base + 0x210); 3261 readl(spec->mem_base + 0x210); 3262 readl(spec->mem_base + 0x210); 3263 3264 writel(0x00800005, spec->mem_base + 0x20c); 3265 writel(group, spec->mem_base + 0x804); 3266 3267 writel(0x00800005, spec->mem_base + 0x20c); 3268 write_val = (target & 0xff); 3269 write_val |= (value << 8); 3270 3271 3272 writel(write_val, spec->mem_base + 0x204); 3273 /* 3274 * Need delay here or else it goes too fast and works inconsistently. 3275 */ 3276 msleep(20); 3277 3278 readl(spec->mem_base + 0x860); 3279 readl(spec->mem_base + 0x854); 3280 readl(spec->mem_base + 0x840); 3281 3282 writel(0x00800004, spec->mem_base + 0x20c); 3283 writel(0x00000000, spec->mem_base + 0x210); 3284 readl(spec->mem_base + 0x210); 3285 readl(spec->mem_base + 0x210); 3286 } 3287 3288 /* 3289 * This second type of command is used for setting the sound filter type. 3290 */ 3291 static void ca0113_mmio_command_set_type2(struct hda_codec *codec, 3292 unsigned int group, unsigned int target, unsigned int value) 3293 { 3294 struct ca0132_spec *spec = codec->spec; 3295 unsigned int write_val; 3296 3297 writel(0x0000007e, spec->mem_base + 0x210); 3298 readl(spec->mem_base + 0x210); 3299 writel(0x0000005a, spec->mem_base + 0x210); 3300 readl(spec->mem_base + 0x210); 3301 readl(spec->mem_base + 0x210); 3302 3303 writel(0x00800003, spec->mem_base + 0x20c); 3304 writel(group, spec->mem_base + 0x804); 3305 3306 writel(0x00800005, spec->mem_base + 0x20c); 3307 write_val = (target & 0xff); 3308 write_val |= (value << 8); 3309 3310 3311 writel(write_val, spec->mem_base + 0x204); 3312 msleep(20); 3313 readl(spec->mem_base + 0x860); 3314 readl(spec->mem_base + 0x854); 3315 readl(spec->mem_base + 0x840); 3316 3317 writel(0x00800004, spec->mem_base + 0x20c); 3318 writel(0x00000000, spec->mem_base + 0x210); 3319 readl(spec->mem_base + 0x210); 3320 readl(spec->mem_base + 0x210); 3321 } 3322 3323 /* 3324 * Setup GPIO for the other variants of Core3D. 3325 */ 3326 3327 /* 3328 * Sets up the GPIO pins so that they are discoverable. If this isn't done, 3329 * the card shows as having no GPIO pins. 3330 */ 3331 static void ca0132_gpio_init(struct hda_codec *codec) 3332 { 3333 struct ca0132_spec *spec = codec->spec; 3334 3335 switch (spec->quirk) { 3336 case QUIRK_SBZ: 3337 case QUIRK_AE5: 3338 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3339 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 3340 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23); 3341 break; 3342 case QUIRK_R3DI: 3343 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3344 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B); 3345 break; 3346 } 3347 3348 } 3349 3350 /* Sets the GPIO for audio output. */ 3351 static void ca0132_gpio_setup(struct hda_codec *codec) 3352 { 3353 struct ca0132_spec *spec = codec->spec; 3354 3355 switch (spec->quirk) { 3356 case QUIRK_SBZ: 3357 snd_hda_codec_write(codec, 0x01, 0, 3358 AC_VERB_SET_GPIO_DIRECTION, 0x07); 3359 snd_hda_codec_write(codec, 0x01, 0, 3360 AC_VERB_SET_GPIO_MASK, 0x07); 3361 snd_hda_codec_write(codec, 0x01, 0, 3362 AC_VERB_SET_GPIO_DATA, 0x04); 3363 snd_hda_codec_write(codec, 0x01, 0, 3364 AC_VERB_SET_GPIO_DATA, 0x06); 3365 break; 3366 case QUIRK_R3DI: 3367 snd_hda_codec_write(codec, 0x01, 0, 3368 AC_VERB_SET_GPIO_DIRECTION, 0x1E); 3369 snd_hda_codec_write(codec, 0x01, 0, 3370 AC_VERB_SET_GPIO_MASK, 0x1F); 3371 snd_hda_codec_write(codec, 0x01, 0, 3372 AC_VERB_SET_GPIO_DATA, 0x0C); 3373 break; 3374 } 3375 } 3376 3377 /* 3378 * GPIO control functions for the Recon3D integrated. 3379 */ 3380 3381 enum r3di_gpio_bit { 3382 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */ 3383 R3DI_MIC_SELECT_BIT = 1, 3384 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */ 3385 R3DI_OUT_SELECT_BIT = 2, 3386 /* 3387 * I dunno what this actually does, but it stays on until the dsp 3388 * is downloaded. 3389 */ 3390 R3DI_GPIO_DSP_DOWNLOADING = 3, 3391 /* 3392 * Same as above, no clue what it does, but it comes on after the dsp 3393 * is downloaded. 3394 */ 3395 R3DI_GPIO_DSP_DOWNLOADED = 4 3396 }; 3397 3398 enum r3di_mic_select { 3399 /* Set GPIO bit 1 to 0 for rear mic */ 3400 R3DI_REAR_MIC = 0, 3401 /* Set GPIO bit 1 to 1 for front microphone*/ 3402 R3DI_FRONT_MIC = 1 3403 }; 3404 3405 enum r3di_out_select { 3406 /* Set GPIO bit 2 to 0 for headphone */ 3407 R3DI_HEADPHONE_OUT = 0, 3408 /* Set GPIO bit 2 to 1 for speaker */ 3409 R3DI_LINE_OUT = 1 3410 }; 3411 enum r3di_dsp_status { 3412 /* Set GPIO bit 3 to 1 until DSP is downloaded */ 3413 R3DI_DSP_DOWNLOADING = 0, 3414 /* Set GPIO bit 4 to 1 once DSP is downloaded */ 3415 R3DI_DSP_DOWNLOADED = 1 3416 }; 3417 3418 3419 static void r3di_gpio_mic_set(struct hda_codec *codec, 3420 enum r3di_mic_select cur_mic) 3421 { 3422 unsigned int cur_gpio; 3423 3424 /* Get the current GPIO Data setup */ 3425 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3426 3427 switch (cur_mic) { 3428 case R3DI_REAR_MIC: 3429 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT); 3430 break; 3431 case R3DI_FRONT_MIC: 3432 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT); 3433 break; 3434 } 3435 snd_hda_codec_write(codec, codec->core.afg, 0, 3436 AC_VERB_SET_GPIO_DATA, cur_gpio); 3437 } 3438 3439 static void r3di_gpio_out_set(struct hda_codec *codec, 3440 enum r3di_out_select cur_out) 3441 { 3442 unsigned int cur_gpio; 3443 3444 /* Get the current GPIO Data setup */ 3445 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3446 3447 switch (cur_out) { 3448 case R3DI_HEADPHONE_OUT: 3449 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT); 3450 break; 3451 case R3DI_LINE_OUT: 3452 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT); 3453 break; 3454 } 3455 snd_hda_codec_write(codec, codec->core.afg, 0, 3456 AC_VERB_SET_GPIO_DATA, cur_gpio); 3457 } 3458 3459 static void r3di_gpio_dsp_status_set(struct hda_codec *codec, 3460 enum r3di_dsp_status dsp_status) 3461 { 3462 unsigned int cur_gpio; 3463 3464 /* Get the current GPIO Data setup */ 3465 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3466 3467 switch (dsp_status) { 3468 case R3DI_DSP_DOWNLOADING: 3469 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING); 3470 snd_hda_codec_write(codec, codec->core.afg, 0, 3471 AC_VERB_SET_GPIO_DATA, cur_gpio); 3472 break; 3473 case R3DI_DSP_DOWNLOADED: 3474 /* Set DOWNLOADING bit to 0. */ 3475 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING); 3476 3477 snd_hda_codec_write(codec, codec->core.afg, 0, 3478 AC_VERB_SET_GPIO_DATA, cur_gpio); 3479 3480 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED); 3481 break; 3482 } 3483 3484 snd_hda_codec_write(codec, codec->core.afg, 0, 3485 AC_VERB_SET_GPIO_DATA, cur_gpio); 3486 } 3487 3488 /* 3489 * PCM callbacks 3490 */ 3491 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3492 struct hda_codec *codec, 3493 unsigned int stream_tag, 3494 unsigned int format, 3495 struct snd_pcm_substream *substream) 3496 { 3497 struct ca0132_spec *spec = codec->spec; 3498 3499 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format); 3500 3501 return 0; 3502 } 3503 3504 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3505 struct hda_codec *codec, 3506 struct snd_pcm_substream *substream) 3507 { 3508 struct ca0132_spec *spec = codec->spec; 3509 3510 if (spec->dsp_state == DSP_DOWNLOADING) 3511 return 0; 3512 3513 /*If Playback effects are on, allow stream some time to flush 3514 *effects tail*/ 3515 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 3516 msleep(50); 3517 3518 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 3519 3520 return 0; 3521 } 3522 3523 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info, 3524 struct hda_codec *codec, 3525 struct snd_pcm_substream *substream) 3526 { 3527 struct ca0132_spec *spec = codec->spec; 3528 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY; 3529 struct snd_pcm_runtime *runtime = substream->runtime; 3530 3531 if (spec->dsp_state != DSP_DOWNLOADED) 3532 return 0; 3533 3534 /* Add latency if playback enhancement and either effect is enabled. */ 3535 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) { 3536 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) || 3537 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID])) 3538 latency += DSP_PLAY_ENHANCEMENT_LATENCY; 3539 } 3540 3541 /* Applying Speaker EQ adds latency as well. */ 3542 if (spec->cur_out_type == SPEAKER_OUT) 3543 latency += DSP_SPEAKER_OUT_LATENCY; 3544 3545 return (latency * runtime->rate) / 1000; 3546 } 3547 3548 /* 3549 * Digital out 3550 */ 3551 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo, 3552 struct hda_codec *codec, 3553 struct snd_pcm_substream *substream) 3554 { 3555 struct ca0132_spec *spec = codec->spec; 3556 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3557 } 3558 3559 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3560 struct hda_codec *codec, 3561 unsigned int stream_tag, 3562 unsigned int format, 3563 struct snd_pcm_substream *substream) 3564 { 3565 struct ca0132_spec *spec = codec->spec; 3566 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3567 stream_tag, format, substream); 3568 } 3569 3570 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3571 struct hda_codec *codec, 3572 struct snd_pcm_substream *substream) 3573 { 3574 struct ca0132_spec *spec = codec->spec; 3575 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout); 3576 } 3577 3578 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo, 3579 struct hda_codec *codec, 3580 struct snd_pcm_substream *substream) 3581 { 3582 struct ca0132_spec *spec = codec->spec; 3583 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3584 } 3585 3586 /* 3587 * Analog capture 3588 */ 3589 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo, 3590 struct hda_codec *codec, 3591 unsigned int stream_tag, 3592 unsigned int format, 3593 struct snd_pcm_substream *substream) 3594 { 3595 snd_hda_codec_setup_stream(codec, hinfo->nid, 3596 stream_tag, 0, format); 3597 3598 return 0; 3599 } 3600 3601 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo, 3602 struct hda_codec *codec, 3603 struct snd_pcm_substream *substream) 3604 { 3605 struct ca0132_spec *spec = codec->spec; 3606 3607 if (spec->dsp_state == DSP_DOWNLOADING) 3608 return 0; 3609 3610 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 3611 return 0; 3612 } 3613 3614 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info, 3615 struct hda_codec *codec, 3616 struct snd_pcm_substream *substream) 3617 { 3618 struct ca0132_spec *spec = codec->spec; 3619 unsigned int latency = DSP_CAPTURE_INIT_LATENCY; 3620 struct snd_pcm_runtime *runtime = substream->runtime; 3621 3622 if (spec->dsp_state != DSP_DOWNLOADED) 3623 return 0; 3624 3625 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 3626 latency += DSP_CRYSTAL_VOICE_LATENCY; 3627 3628 return (latency * runtime->rate) / 1000; 3629 } 3630 3631 /* 3632 * Controls stuffs. 3633 */ 3634 3635 /* 3636 * Mixer controls helpers. 3637 */ 3638 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \ 3639 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3640 .name = xname, \ 3641 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3642 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3643 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 3644 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 3645 .info = ca0132_volume_info, \ 3646 .get = ca0132_volume_get, \ 3647 .put = ca0132_volume_put, \ 3648 .tlv = { .c = ca0132_volume_tlv }, \ 3649 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3650 3651 /* 3652 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the 3653 * volume put, which is used for setting the DSP volume. This was done because 3654 * the ca0132 functions were taking too much time and causing lag. 3655 */ 3656 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \ 3657 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3658 .name = xname, \ 3659 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3660 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3661 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 3662 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 3663 .info = snd_hda_mixer_amp_volume_info, \ 3664 .get = snd_hda_mixer_amp_volume_get, \ 3665 .put = ca0132_alt_volume_put, \ 3666 .tlv = { .c = snd_hda_mixer_amp_tlv }, \ 3667 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3668 3669 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \ 3670 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3671 .name = xname, \ 3672 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3673 .info = snd_hda_mixer_amp_switch_info, \ 3674 .get = ca0132_switch_get, \ 3675 .put = ca0132_switch_put, \ 3676 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3677 3678 /* stereo */ 3679 #define CA0132_CODEC_VOL(xname, nid, dir) \ 3680 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir) 3681 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \ 3682 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir) 3683 #define CA0132_CODEC_MUTE(xname, nid, dir) \ 3684 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir) 3685 3686 /* lookup tables */ 3687 /* 3688 * Lookup table with decibel values for the DSP. When volume is changed in 3689 * Windows, the DSP is also sent the dB value in floating point. In Windows, 3690 * these values have decimal points, probably because the Windows driver 3691 * actually uses floating point. We can't here, so I made a lookup table of 3692 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the 3693 * DAC's, and 9 is the maximum. 3694 */ 3695 static const unsigned int float_vol_db_lookup[] = { 3696 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000, 3697 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000, 3698 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000, 3699 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000, 3700 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000, 3701 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000, 3702 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000, 3703 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000, 3704 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000, 3705 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000, 3706 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000, 3707 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 3708 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 3709 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 3710 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 3711 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 3712 0x40C00000, 0x40E00000, 0x41000000, 0x41100000 3713 }; 3714 3715 /* 3716 * This table counts from float 0 to 1 in increments of .01, which is 3717 * useful for a few different sliders. 3718 */ 3719 static const unsigned int float_zero_to_one_lookup[] = { 3720 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 3721 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 3722 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 3723 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 3724 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 3725 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 3726 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 3727 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 3728 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 3729 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 3730 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 3731 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 3732 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 3733 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 3734 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 3735 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 3736 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 3737 }; 3738 3739 /* 3740 * This table counts from float 10 to 1000, which is the range of the x-bass 3741 * crossover slider in Windows. 3742 */ 3743 static const unsigned int float_xbass_xover_lookup[] = { 3744 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000, 3745 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000, 3746 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000, 3747 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000, 3748 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000, 3749 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000, 3750 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000, 3751 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000, 3752 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000, 3753 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000, 3754 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000, 3755 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000, 3756 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000, 3757 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000, 3758 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000, 3759 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000, 3760 0x44728000, 0x44750000, 0x44778000, 0x447A0000 3761 }; 3762 3763 /* The following are for tuning of products */ 3764 #ifdef ENABLE_TUNING_CONTROLS 3765 3766 static unsigned int voice_focus_vals_lookup[] = { 3767 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000, 3768 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000, 3769 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000, 3770 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000, 3771 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000, 3772 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000, 3773 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000, 3774 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000, 3775 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000, 3776 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000, 3777 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000, 3778 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000, 3779 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000, 3780 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000, 3781 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000, 3782 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000, 3783 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000, 3784 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000, 3785 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000, 3786 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000, 3787 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000, 3788 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000, 3789 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000, 3790 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000, 3791 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000, 3792 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000, 3793 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000 3794 }; 3795 3796 static unsigned int mic_svm_vals_lookup[] = { 3797 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 3798 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 3799 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 3800 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 3801 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 3802 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 3803 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 3804 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 3805 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 3806 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 3807 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 3808 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 3809 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 3810 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 3811 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 3812 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 3813 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 3814 }; 3815 3816 static unsigned int equalizer_vals_lookup[] = { 3817 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 3818 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 3819 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 3820 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 3821 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 3822 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000, 3823 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000, 3824 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 3825 0x41C00000 3826 }; 3827 3828 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid, 3829 unsigned int *lookup, int idx) 3830 { 3831 int i = 0; 3832 3833 for (i = 0; i < TUNING_CTLS_COUNT; i++) 3834 if (nid == ca0132_tuning_ctls[i].nid) 3835 break; 3836 3837 snd_hda_power_up(codec); 3838 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20, 3839 ca0132_tuning_ctls[i].req, 3840 &(lookup[idx]), sizeof(unsigned int)); 3841 snd_hda_power_down(codec); 3842 3843 return 1; 3844 } 3845 3846 static int tuning_ctl_get(struct snd_kcontrol *kcontrol, 3847 struct snd_ctl_elem_value *ucontrol) 3848 { 3849 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3850 struct ca0132_spec *spec = codec->spec; 3851 hda_nid_t nid = get_amp_nid(kcontrol); 3852 long *valp = ucontrol->value.integer.value; 3853 int idx = nid - TUNING_CTL_START_NID; 3854 3855 *valp = spec->cur_ctl_vals[idx]; 3856 return 0; 3857 } 3858 3859 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol, 3860 struct snd_ctl_elem_info *uinfo) 3861 { 3862 int chs = get_amp_channels(kcontrol); 3863 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3864 uinfo->count = chs == 3 ? 2 : 1; 3865 uinfo->value.integer.min = 20; 3866 uinfo->value.integer.max = 180; 3867 uinfo->value.integer.step = 1; 3868 3869 return 0; 3870 } 3871 3872 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol, 3873 struct snd_ctl_elem_value *ucontrol) 3874 { 3875 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3876 struct ca0132_spec *spec = codec->spec; 3877 hda_nid_t nid = get_amp_nid(kcontrol); 3878 long *valp = ucontrol->value.integer.value; 3879 int idx; 3880 3881 idx = nid - TUNING_CTL_START_NID; 3882 /* any change? */ 3883 if (spec->cur_ctl_vals[idx] == *valp) 3884 return 0; 3885 3886 spec->cur_ctl_vals[idx] = *valp; 3887 3888 idx = *valp - 20; 3889 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx); 3890 3891 return 1; 3892 } 3893 3894 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol, 3895 struct snd_ctl_elem_info *uinfo) 3896 { 3897 int chs = get_amp_channels(kcontrol); 3898 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3899 uinfo->count = chs == 3 ? 2 : 1; 3900 uinfo->value.integer.min = 0; 3901 uinfo->value.integer.max = 100; 3902 uinfo->value.integer.step = 1; 3903 3904 return 0; 3905 } 3906 3907 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol, 3908 struct snd_ctl_elem_value *ucontrol) 3909 { 3910 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3911 struct ca0132_spec *spec = codec->spec; 3912 hda_nid_t nid = get_amp_nid(kcontrol); 3913 long *valp = ucontrol->value.integer.value; 3914 int idx; 3915 3916 idx = nid - TUNING_CTL_START_NID; 3917 /* any change? */ 3918 if (spec->cur_ctl_vals[idx] == *valp) 3919 return 0; 3920 3921 spec->cur_ctl_vals[idx] = *valp; 3922 3923 idx = *valp; 3924 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx); 3925 3926 return 0; 3927 } 3928 3929 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol, 3930 struct snd_ctl_elem_info *uinfo) 3931 { 3932 int chs = get_amp_channels(kcontrol); 3933 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3934 uinfo->count = chs == 3 ? 2 : 1; 3935 uinfo->value.integer.min = 0; 3936 uinfo->value.integer.max = 48; 3937 uinfo->value.integer.step = 1; 3938 3939 return 0; 3940 } 3941 3942 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol, 3943 struct snd_ctl_elem_value *ucontrol) 3944 { 3945 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3946 struct ca0132_spec *spec = codec->spec; 3947 hda_nid_t nid = get_amp_nid(kcontrol); 3948 long *valp = ucontrol->value.integer.value; 3949 int idx; 3950 3951 idx = nid - TUNING_CTL_START_NID; 3952 /* any change? */ 3953 if (spec->cur_ctl_vals[idx] == *valp) 3954 return 0; 3955 3956 spec->cur_ctl_vals[idx] = *valp; 3957 3958 idx = *valp; 3959 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx); 3960 3961 return 1; 3962 } 3963 3964 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0); 3965 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0); 3966 3967 static int add_tuning_control(struct hda_codec *codec, 3968 hda_nid_t pnid, hda_nid_t nid, 3969 const char *name, int dir) 3970 { 3971 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 3972 int type = dir ? HDA_INPUT : HDA_OUTPUT; 3973 struct snd_kcontrol_new knew = 3974 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 3975 3976 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 3977 SNDRV_CTL_ELEM_ACCESS_TLV_READ; 3978 knew.tlv.c = 0; 3979 knew.tlv.p = 0; 3980 switch (pnid) { 3981 case VOICE_FOCUS: 3982 knew.info = voice_focus_ctl_info; 3983 knew.get = tuning_ctl_get; 3984 knew.put = voice_focus_ctl_put; 3985 knew.tlv.p = voice_focus_db_scale; 3986 break; 3987 case MIC_SVM: 3988 knew.info = mic_svm_ctl_info; 3989 knew.get = tuning_ctl_get; 3990 knew.put = mic_svm_ctl_put; 3991 break; 3992 case EQUALIZER: 3993 knew.info = equalizer_ctl_info; 3994 knew.get = tuning_ctl_get; 3995 knew.put = equalizer_ctl_put; 3996 knew.tlv.p = eq_db_scale; 3997 break; 3998 default: 3999 return 0; 4000 } 4001 knew.private_value = 4002 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 4003 sprintf(namestr, "%s %s Volume", name, dirstr[dir]); 4004 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 4005 } 4006 4007 static int add_tuning_ctls(struct hda_codec *codec) 4008 { 4009 int i; 4010 int err; 4011 4012 for (i = 0; i < TUNING_CTLS_COUNT; i++) { 4013 err = add_tuning_control(codec, 4014 ca0132_tuning_ctls[i].parent_nid, 4015 ca0132_tuning_ctls[i].nid, 4016 ca0132_tuning_ctls[i].name, 4017 ca0132_tuning_ctls[i].direct); 4018 if (err < 0) 4019 return err; 4020 } 4021 4022 return 0; 4023 } 4024 4025 static void ca0132_init_tuning_defaults(struct hda_codec *codec) 4026 { 4027 struct ca0132_spec *spec = codec->spec; 4028 int i; 4029 4030 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */ 4031 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10; 4032 /* SVM level defaults to 0.74. */ 4033 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74; 4034 4035 /* EQ defaults to 0dB. */ 4036 for (i = 2; i < TUNING_CTLS_COUNT; i++) 4037 spec->cur_ctl_vals[i] = 24; 4038 } 4039 #endif /*ENABLE_TUNING_CONTROLS*/ 4040 4041 /* 4042 * Select the active output. 4043 * If autodetect is enabled, output will be selected based on jack detection. 4044 * If jack inserted, headphone will be selected, else built-in speakers 4045 * If autodetect is disabled, output will be selected based on selection. 4046 */ 4047 static int ca0132_select_out(struct hda_codec *codec) 4048 { 4049 struct ca0132_spec *spec = codec->spec; 4050 unsigned int pin_ctl; 4051 int jack_present; 4052 int auto_jack; 4053 unsigned int tmp; 4054 int err; 4055 4056 codec_dbg(codec, "ca0132_select_out\n"); 4057 4058 snd_hda_power_up_pm(codec); 4059 4060 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4061 4062 if (auto_jack) 4063 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp); 4064 else 4065 jack_present = 4066 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID]; 4067 4068 if (jack_present) 4069 spec->cur_out_type = HEADPHONE_OUT; 4070 else 4071 spec->cur_out_type = SPEAKER_OUT; 4072 4073 if (spec->cur_out_type == SPEAKER_OUT) { 4074 codec_dbg(codec, "ca0132_select_out speaker\n"); 4075 /*speaker out config*/ 4076 tmp = FLOAT_ONE; 4077 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4078 if (err < 0) 4079 goto exit; 4080 /*enable speaker EQ*/ 4081 tmp = FLOAT_ONE; 4082 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4083 if (err < 0) 4084 goto exit; 4085 4086 /* Setup EAPD */ 4087 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4088 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4089 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4090 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4091 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4092 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4093 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4094 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4095 4096 /* disable headphone node */ 4097 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4098 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4099 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4100 pin_ctl & ~PIN_HP); 4101 /* enable speaker node */ 4102 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4103 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4104 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4105 pin_ctl | PIN_OUT); 4106 } else { 4107 codec_dbg(codec, "ca0132_select_out hp\n"); 4108 /*headphone out config*/ 4109 tmp = FLOAT_ZERO; 4110 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4111 if (err < 0) 4112 goto exit; 4113 /*disable speaker EQ*/ 4114 tmp = FLOAT_ZERO; 4115 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4116 if (err < 0) 4117 goto exit; 4118 4119 /* Setup EAPD */ 4120 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4121 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4122 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4123 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4124 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4125 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4126 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4127 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4128 4129 /* disable speaker*/ 4130 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4131 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4132 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4133 pin_ctl & ~PIN_HP); 4134 /* enable headphone*/ 4135 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4136 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4137 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4138 pin_ctl | PIN_HP); 4139 } 4140 4141 exit: 4142 snd_hda_power_down_pm(codec); 4143 4144 return err < 0 ? err : 0; 4145 } 4146 4147 static int ae5_headphone_gain_set(struct hda_codec *codec, long val); 4148 static int zxr_headphone_gain_set(struct hda_codec *codec, long val); 4149 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val); 4150 4151 static void ae5_mmio_select_out(struct hda_codec *codec) 4152 { 4153 struct ca0132_spec *spec = codec->spec; 4154 unsigned int i; 4155 4156 for (i = 0; i < AE5_CA0113_OUT_SET_COMMANDS; i++) 4157 ca0113_mmio_command_set(codec, 4158 ae5_ca0113_output_presets[spec->cur_out_type].group[i], 4159 ae5_ca0113_output_presets[spec->cur_out_type].target[i], 4160 ae5_ca0113_output_presets[spec->cur_out_type].vals[i]); 4161 } 4162 4163 /* 4164 * These are the commands needed to setup output on each of the different card 4165 * types. 4166 */ 4167 static void ca0132_alt_select_out_quirk_handler(struct hda_codec *codec) 4168 { 4169 struct ca0132_spec *spec = codec->spec; 4170 unsigned int tmp; 4171 4172 switch (spec->cur_out_type) { 4173 case SPEAKER_OUT: 4174 switch (spec->quirk) { 4175 case QUIRK_SBZ: 4176 ca0113_mmio_gpio_set(codec, 7, false); 4177 ca0113_mmio_gpio_set(codec, 4, true); 4178 ca0113_mmio_gpio_set(codec, 1, true); 4179 chipio_set_control_param(codec, 0x0d, 0x18); 4180 break; 4181 case QUIRK_ZXR: 4182 ca0113_mmio_gpio_set(codec, 2, true); 4183 ca0113_mmio_gpio_set(codec, 3, true); 4184 ca0113_mmio_gpio_set(codec, 5, false); 4185 zxr_headphone_gain_set(codec, 0); 4186 chipio_set_control_param(codec, 0x0d, 0x24); 4187 break; 4188 case QUIRK_R3DI: 4189 chipio_set_control_param(codec, 0x0d, 0x24); 4190 r3di_gpio_out_set(codec, R3DI_LINE_OUT); 4191 break; 4192 case QUIRK_R3D: 4193 chipio_set_control_param(codec, 0x0d, 0x24); 4194 ca0113_mmio_gpio_set(codec, 1, true); 4195 break; 4196 case QUIRK_AE5: 4197 ae5_mmio_select_out(codec); 4198 ae5_headphone_gain_set(codec, 2); 4199 tmp = FLOAT_ZERO; 4200 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 4201 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 4202 chipio_set_control_param(codec, 0x0d, 0xa4); 4203 chipio_write(codec, 0x18b03c, 0x00000012); 4204 break; 4205 } 4206 break; 4207 case HEADPHONE_OUT: 4208 switch (spec->quirk) { 4209 case QUIRK_SBZ: 4210 ca0113_mmio_gpio_set(codec, 7, true); 4211 ca0113_mmio_gpio_set(codec, 4, true); 4212 ca0113_mmio_gpio_set(codec, 1, false); 4213 chipio_set_control_param(codec, 0x0d, 0x12); 4214 break; 4215 case QUIRK_ZXR: 4216 ca0113_mmio_gpio_set(codec, 2, false); 4217 ca0113_mmio_gpio_set(codec, 3, false); 4218 ca0113_mmio_gpio_set(codec, 5, true); 4219 zxr_headphone_gain_set(codec, spec->zxr_gain_set); 4220 chipio_set_control_param(codec, 0x0d, 0x21); 4221 break; 4222 case QUIRK_R3DI: 4223 chipio_set_control_param(codec, 0x0d, 0x21); 4224 r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT); 4225 break; 4226 case QUIRK_R3D: 4227 chipio_set_control_param(codec, 0x0d, 0x21); 4228 ca0113_mmio_gpio_set(codec, 0x1, false); 4229 break; 4230 case QUIRK_AE5: 4231 ae5_mmio_select_out(codec); 4232 ae5_headphone_gain_set(codec, 4233 spec->ae5_headphone_gain_val); 4234 tmp = FLOAT_ONE; 4235 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 4236 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 4237 chipio_set_control_param(codec, 0x0d, 0xa1); 4238 chipio_write(codec, 0x18b03c, 0x00000012); 4239 break; 4240 } 4241 break; 4242 case SURROUND_OUT: 4243 switch (spec->quirk) { 4244 case QUIRK_SBZ: 4245 ca0113_mmio_gpio_set(codec, 7, false); 4246 ca0113_mmio_gpio_set(codec, 4, true); 4247 ca0113_mmio_gpio_set(codec, 1, true); 4248 chipio_set_control_param(codec, 0x0d, 0x18); 4249 break; 4250 case QUIRK_ZXR: 4251 ca0113_mmio_gpio_set(codec, 2, true); 4252 ca0113_mmio_gpio_set(codec, 3, true); 4253 ca0113_mmio_gpio_set(codec, 5, false); 4254 zxr_headphone_gain_set(codec, 0); 4255 chipio_set_control_param(codec, 0x0d, 0x24); 4256 break; 4257 case QUIRK_R3DI: 4258 chipio_set_control_param(codec, 0x0d, 0x24); 4259 r3di_gpio_out_set(codec, R3DI_LINE_OUT); 4260 break; 4261 case QUIRK_R3D: 4262 ca0113_mmio_gpio_set(codec, 1, true); 4263 chipio_set_control_param(codec, 0x0d, 0x24); 4264 break; 4265 case QUIRK_AE5: 4266 ae5_mmio_select_out(codec); 4267 ae5_headphone_gain_set(codec, 2); 4268 tmp = FLOAT_ZERO; 4269 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 4270 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 4271 chipio_set_control_param(codec, 0x0d, 0xa4); 4272 chipio_write(codec, 0x18b03c, 0x00000012); 4273 break; 4274 } 4275 break; 4276 } 4277 } 4278 4279 /* 4280 * This function behaves similarly to the ca0132_select_out funciton above, 4281 * except with a few differences. It adds the ability to select the current 4282 * output with an enumerated control "output source" if the auto detect 4283 * mute switch is set to off. If the auto detect mute switch is enabled, it 4284 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection. 4285 * It also adds the ability to auto-detect the front headphone port. The only 4286 * way to select surround is to disable auto detect, and set Surround with the 4287 * enumerated control. 4288 */ 4289 static int ca0132_alt_select_out(struct hda_codec *codec) 4290 { 4291 struct ca0132_spec *spec = codec->spec; 4292 unsigned int pin_ctl; 4293 int jack_present; 4294 int auto_jack; 4295 unsigned int i; 4296 unsigned int tmp; 4297 int err; 4298 /* Default Headphone is rear headphone */ 4299 hda_nid_t headphone_nid = spec->out_pins[1]; 4300 4301 codec_dbg(codec, "%s\n", __func__); 4302 4303 snd_hda_power_up_pm(codec); 4304 4305 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4306 4307 /* 4308 * If headphone rear or front is plugged in, set to headphone. 4309 * If neither is plugged in, set to rear line out. Only if 4310 * hp/speaker auto detect is enabled. 4311 */ 4312 if (auto_jack) { 4313 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) || 4314 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp); 4315 4316 if (jack_present) 4317 spec->cur_out_type = HEADPHONE_OUT; 4318 else 4319 spec->cur_out_type = SPEAKER_OUT; 4320 } else 4321 spec->cur_out_type = spec->out_enum_val; 4322 4323 /* Begin DSP output switch */ 4324 tmp = FLOAT_ONE; 4325 err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp); 4326 if (err < 0) 4327 goto exit; 4328 4329 ca0132_alt_select_out_quirk_handler(codec); 4330 4331 switch (spec->cur_out_type) { 4332 case SPEAKER_OUT: 4333 codec_dbg(codec, "%s speaker\n", __func__); 4334 4335 /* disable headphone node */ 4336 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4337 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4338 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4339 pin_ctl & ~PIN_HP); 4340 /* enable line-out node */ 4341 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4342 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4343 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4344 pin_ctl | PIN_OUT); 4345 /* Enable EAPD */ 4346 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4347 AC_VERB_SET_EAPD_BTLENABLE, 0x01); 4348 4349 /* If PlayEnhancement is enabled, set different source */ 4350 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4351 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE); 4352 else 4353 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT); 4354 break; 4355 case HEADPHONE_OUT: 4356 codec_dbg(codec, "%s hp\n", __func__); 4357 4358 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4359 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4360 4361 /* disable speaker*/ 4362 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4363 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4364 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4365 pin_ctl & ~PIN_HP); 4366 4367 /* enable headphone, either front or rear */ 4368 4369 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp)) 4370 headphone_nid = spec->out_pins[2]; 4371 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp)) 4372 headphone_nid = spec->out_pins[1]; 4373 4374 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0, 4375 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4376 snd_hda_set_pin_ctl(codec, headphone_nid, 4377 pin_ctl | PIN_HP); 4378 4379 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4380 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE); 4381 else 4382 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO); 4383 break; 4384 case SURROUND_OUT: 4385 codec_dbg(codec, "%s surround\n", __func__); 4386 4387 /* enable line out node */ 4388 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4389 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4390 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4391 pin_ctl | PIN_OUT); 4392 /* Disable headphone out */ 4393 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4394 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4395 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4396 pin_ctl & ~PIN_HP); 4397 /* Enable EAPD on line out */ 4398 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4399 AC_VERB_SET_EAPD_BTLENABLE, 0x01); 4400 /* enable center/lfe out node */ 4401 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0, 4402 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4403 snd_hda_set_pin_ctl(codec, spec->out_pins[2], 4404 pin_ctl | PIN_OUT); 4405 /* Now set rear surround node as out. */ 4406 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0, 4407 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4408 snd_hda_set_pin_ctl(codec, spec->out_pins[3], 4409 pin_ctl | PIN_OUT); 4410 4411 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT); 4412 break; 4413 } 4414 /* 4415 * Surround always sets it's scp command to req 0x04 to FLOAT_EIGHT. 4416 * With this set though, X_BASS cannot be enabled. So, if we have OutFX 4417 * enabled, we need to make sure X_BASS is off, otherwise everything 4418 * sounds all muffled. Running ca0132_effects_set with X_BASS as the 4419 * effect should sort this out. 4420 */ 4421 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4422 ca0132_effects_set(codec, X_BASS, 4423 spec->effects_switch[X_BASS - EFFECT_START_NID]); 4424 4425 /* run through the output dsp commands for the selected output. */ 4426 for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) { 4427 err = dspio_set_uint_param(codec, 4428 alt_out_presets[spec->cur_out_type].mids[i], 4429 alt_out_presets[spec->cur_out_type].reqs[i], 4430 alt_out_presets[spec->cur_out_type].vals[i]); 4431 4432 if (err < 0) 4433 goto exit; 4434 } 4435 4436 exit: 4437 snd_hda_power_down_pm(codec); 4438 4439 return err < 0 ? err : 0; 4440 } 4441 4442 static void ca0132_unsol_hp_delayed(struct work_struct *work) 4443 { 4444 struct ca0132_spec *spec = container_of( 4445 to_delayed_work(work), struct ca0132_spec, unsol_hp_work); 4446 struct hda_jack_tbl *jack; 4447 4448 if (spec->use_alt_functions) 4449 ca0132_alt_select_out(spec->codec); 4450 else 4451 ca0132_select_out(spec->codec); 4452 4453 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp); 4454 if (jack) { 4455 jack->block_report = 0; 4456 snd_hda_jack_report_sync(spec->codec); 4457 } 4458 } 4459 4460 static void ca0132_set_dmic(struct hda_codec *codec, int enable); 4461 static int ca0132_mic_boost_set(struct hda_codec *codec, long val); 4462 static void resume_mic1(struct hda_codec *codec, unsigned int oldval); 4463 static int stop_mic1(struct hda_codec *codec); 4464 static int ca0132_cvoice_switch_set(struct hda_codec *codec); 4465 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val); 4466 4467 /* 4468 * Select the active VIP source 4469 */ 4470 static int ca0132_set_vipsource(struct hda_codec *codec, int val) 4471 { 4472 struct ca0132_spec *spec = codec->spec; 4473 unsigned int tmp; 4474 4475 if (spec->dsp_state != DSP_DOWNLOADED) 4476 return 0; 4477 4478 /* if CrystalVoice if off, vipsource should be 0 */ 4479 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4480 (val == 0)) { 4481 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4482 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4483 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4484 if (spec->cur_mic_type == DIGITAL_MIC) 4485 tmp = FLOAT_TWO; 4486 else 4487 tmp = FLOAT_ONE; 4488 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4489 tmp = FLOAT_ZERO; 4490 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4491 } else { 4492 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4493 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4494 if (spec->cur_mic_type == DIGITAL_MIC) 4495 tmp = FLOAT_TWO; 4496 else 4497 tmp = FLOAT_ONE; 4498 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4499 tmp = FLOAT_ONE; 4500 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4501 msleep(20); 4502 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4503 } 4504 4505 return 1; 4506 } 4507 4508 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val) 4509 { 4510 struct ca0132_spec *spec = codec->spec; 4511 unsigned int tmp; 4512 4513 if (spec->dsp_state != DSP_DOWNLOADED) 4514 return 0; 4515 4516 codec_dbg(codec, "%s\n", __func__); 4517 4518 chipio_set_stream_control(codec, 0x03, 0); 4519 chipio_set_stream_control(codec, 0x04, 0); 4520 4521 /* if CrystalVoice is off, vipsource should be 0 */ 4522 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4523 (val == 0) || spec->in_enum_val == REAR_LINE_IN) { 4524 codec_dbg(codec, "%s: off.", __func__); 4525 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4526 4527 tmp = FLOAT_ZERO; 4528 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4529 4530 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4531 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4532 if (spec->quirk == QUIRK_R3DI) 4533 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4534 4535 4536 if (spec->in_enum_val == REAR_LINE_IN) 4537 tmp = FLOAT_ZERO; 4538 else { 4539 if (spec->quirk == QUIRK_SBZ) 4540 tmp = FLOAT_THREE; 4541 else 4542 tmp = FLOAT_ONE; 4543 } 4544 4545 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4546 4547 } else { 4548 codec_dbg(codec, "%s: on.", __func__); 4549 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4550 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4551 if (spec->quirk == QUIRK_R3DI) 4552 chipio_set_conn_rate(codec, 0x0F, SR_16_000); 4553 4554 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID]) 4555 tmp = FLOAT_TWO; 4556 else 4557 tmp = FLOAT_ONE; 4558 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4559 4560 tmp = FLOAT_ONE; 4561 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4562 4563 msleep(20); 4564 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4565 } 4566 4567 chipio_set_stream_control(codec, 0x03, 1); 4568 chipio_set_stream_control(codec, 0x04, 1); 4569 4570 return 1; 4571 } 4572 4573 /* 4574 * Select the active microphone. 4575 * If autodetect is enabled, mic will be selected based on jack detection. 4576 * If jack inserted, ext.mic will be selected, else built-in mic 4577 * If autodetect is disabled, mic will be selected based on selection. 4578 */ 4579 static int ca0132_select_mic(struct hda_codec *codec) 4580 { 4581 struct ca0132_spec *spec = codec->spec; 4582 int jack_present; 4583 int auto_jack; 4584 4585 codec_dbg(codec, "ca0132_select_mic\n"); 4586 4587 snd_hda_power_up_pm(codec); 4588 4589 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 4590 4591 if (auto_jack) 4592 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1); 4593 else 4594 jack_present = 4595 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID]; 4596 4597 if (jack_present) 4598 spec->cur_mic_type = LINE_MIC_IN; 4599 else 4600 spec->cur_mic_type = DIGITAL_MIC; 4601 4602 if (spec->cur_mic_type == DIGITAL_MIC) { 4603 /* enable digital Mic */ 4604 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000); 4605 ca0132_set_dmic(codec, 1); 4606 ca0132_mic_boost_set(codec, 0); 4607 /* set voice focus */ 4608 ca0132_effects_set(codec, VOICE_FOCUS, 4609 spec->effects_switch 4610 [VOICE_FOCUS - EFFECT_START_NID]); 4611 } else { 4612 /* disable digital Mic */ 4613 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000); 4614 ca0132_set_dmic(codec, 0); 4615 ca0132_mic_boost_set(codec, spec->cur_mic_boost); 4616 /* disable voice focus */ 4617 ca0132_effects_set(codec, VOICE_FOCUS, 0); 4618 } 4619 4620 snd_hda_power_down_pm(codec); 4621 4622 return 0; 4623 } 4624 4625 /* 4626 * Select the active input. 4627 * Mic detection isn't used, because it's kind of pointless on the SBZ. 4628 * The front mic has no jack-detection, so the only way to switch to it 4629 * is to do it manually in alsamixer. 4630 */ 4631 static int ca0132_alt_select_in(struct hda_codec *codec) 4632 { 4633 struct ca0132_spec *spec = codec->spec; 4634 unsigned int tmp; 4635 4636 codec_dbg(codec, "%s\n", __func__); 4637 4638 snd_hda_power_up_pm(codec); 4639 4640 chipio_set_stream_control(codec, 0x03, 0); 4641 chipio_set_stream_control(codec, 0x04, 0); 4642 4643 spec->cur_mic_type = spec->in_enum_val; 4644 4645 switch (spec->cur_mic_type) { 4646 case REAR_MIC: 4647 switch (spec->quirk) { 4648 case QUIRK_SBZ: 4649 case QUIRK_R3D: 4650 ca0113_mmio_gpio_set(codec, 0, false); 4651 tmp = FLOAT_THREE; 4652 break; 4653 case QUIRK_ZXR: 4654 tmp = FLOAT_THREE; 4655 break; 4656 case QUIRK_R3DI: 4657 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 4658 tmp = FLOAT_ONE; 4659 break; 4660 case QUIRK_AE5: 4661 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x00); 4662 tmp = FLOAT_THREE; 4663 break; 4664 default: 4665 tmp = FLOAT_ONE; 4666 break; 4667 } 4668 4669 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4670 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4671 if (spec->quirk == QUIRK_R3DI) 4672 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4673 4674 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4675 4676 chipio_set_stream_control(codec, 0x03, 1); 4677 chipio_set_stream_control(codec, 0x04, 1); 4678 switch (spec->quirk) { 4679 case QUIRK_SBZ: 4680 chipio_write(codec, 0x18B098, 0x0000000C); 4681 chipio_write(codec, 0x18B09C, 0x0000000C); 4682 break; 4683 case QUIRK_ZXR: 4684 chipio_write(codec, 0x18B098, 0x0000000C); 4685 chipio_write(codec, 0x18B09C, 0x000000CC); 4686 break; 4687 case QUIRK_AE5: 4688 chipio_write(codec, 0x18B098, 0x0000000C); 4689 chipio_write(codec, 0x18B09C, 0x0000004C); 4690 break; 4691 } 4692 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 4693 break; 4694 case REAR_LINE_IN: 4695 ca0132_mic_boost_set(codec, 0); 4696 switch (spec->quirk) { 4697 case QUIRK_SBZ: 4698 case QUIRK_R3D: 4699 ca0113_mmio_gpio_set(codec, 0, false); 4700 break; 4701 case QUIRK_R3DI: 4702 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 4703 break; 4704 case QUIRK_AE5: 4705 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x00); 4706 break; 4707 } 4708 4709 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4710 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4711 if (spec->quirk == QUIRK_R3DI) 4712 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4713 4714 tmp = FLOAT_ZERO; 4715 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4716 4717 switch (spec->quirk) { 4718 case QUIRK_SBZ: 4719 case QUIRK_AE5: 4720 chipio_write(codec, 0x18B098, 0x00000000); 4721 chipio_write(codec, 0x18B09C, 0x00000000); 4722 break; 4723 } 4724 chipio_set_stream_control(codec, 0x03, 1); 4725 chipio_set_stream_control(codec, 0x04, 1); 4726 break; 4727 case FRONT_MIC: 4728 switch (spec->quirk) { 4729 case QUIRK_SBZ: 4730 case QUIRK_R3D: 4731 ca0113_mmio_gpio_set(codec, 0, true); 4732 ca0113_mmio_gpio_set(codec, 5, false); 4733 tmp = FLOAT_THREE; 4734 break; 4735 case QUIRK_R3DI: 4736 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC); 4737 tmp = FLOAT_ONE; 4738 break; 4739 case QUIRK_AE5: 4740 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x3f); 4741 tmp = FLOAT_THREE; 4742 break; 4743 default: 4744 tmp = FLOAT_ONE; 4745 break; 4746 } 4747 4748 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4749 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4750 if (spec->quirk == QUIRK_R3DI) 4751 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4752 4753 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4754 4755 chipio_set_stream_control(codec, 0x03, 1); 4756 chipio_set_stream_control(codec, 0x04, 1); 4757 4758 switch (spec->quirk) { 4759 case QUIRK_SBZ: 4760 chipio_write(codec, 0x18B098, 0x0000000C); 4761 chipio_write(codec, 0x18B09C, 0x000000CC); 4762 break; 4763 case QUIRK_AE5: 4764 chipio_write(codec, 0x18B098, 0x0000000C); 4765 chipio_write(codec, 0x18B09C, 0x0000004C); 4766 break; 4767 } 4768 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 4769 break; 4770 } 4771 ca0132_cvoice_switch_set(codec); 4772 4773 snd_hda_power_down_pm(codec); 4774 return 0; 4775 } 4776 4777 /* 4778 * Check if VNODE settings take effect immediately. 4779 */ 4780 static bool ca0132_is_vnode_effective(struct hda_codec *codec, 4781 hda_nid_t vnid, 4782 hda_nid_t *shared_nid) 4783 { 4784 struct ca0132_spec *spec = codec->spec; 4785 hda_nid_t nid; 4786 4787 switch (vnid) { 4788 case VNID_SPK: 4789 nid = spec->shared_out_nid; 4790 break; 4791 case VNID_MIC: 4792 nid = spec->shared_mic_nid; 4793 break; 4794 default: 4795 return false; 4796 } 4797 4798 if (shared_nid) 4799 *shared_nid = nid; 4800 4801 return true; 4802 } 4803 4804 /* 4805 * The following functions are control change helpers. 4806 * They return 0 if no changed. Return 1 if changed. 4807 */ 4808 static int ca0132_voicefx_set(struct hda_codec *codec, int enable) 4809 { 4810 struct ca0132_spec *spec = codec->spec; 4811 unsigned int tmp; 4812 4813 /* based on CrystalVoice state to enable VoiceFX. */ 4814 if (enable) { 4815 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ? 4816 FLOAT_ONE : FLOAT_ZERO; 4817 } else { 4818 tmp = FLOAT_ZERO; 4819 } 4820 4821 dspio_set_uint_param(codec, ca0132_voicefx.mid, 4822 ca0132_voicefx.reqs[0], tmp); 4823 4824 return 1; 4825 } 4826 4827 /* 4828 * Set the effects parameters 4829 */ 4830 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val) 4831 { 4832 struct ca0132_spec *spec = codec->spec; 4833 unsigned int on, tmp; 4834 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 4835 int err = 0; 4836 int idx = nid - EFFECT_START_NID; 4837 4838 if ((idx < 0) || (idx >= num_fx)) 4839 return 0; /* no changed */ 4840 4841 /* for out effect, qualify with PE */ 4842 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) { 4843 /* if PE if off, turn off out effects. */ 4844 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4845 val = 0; 4846 if (spec->cur_out_type == SURROUND_OUT && nid == X_BASS) 4847 val = 0; 4848 } 4849 4850 /* for in effect, qualify with CrystalVoice */ 4851 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) { 4852 /* if CrystalVoice if off, turn off in effects. */ 4853 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 4854 val = 0; 4855 4856 /* Voice Focus applies to 2-ch Mic, Digital Mic */ 4857 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC)) 4858 val = 0; 4859 4860 /* If Voice Focus on SBZ, set to two channel. */ 4861 if ((nid == VOICE_FOCUS) && (spec->use_pci_mmio) 4862 && (spec->cur_mic_type != REAR_LINE_IN)) { 4863 if (spec->effects_switch[CRYSTAL_VOICE - 4864 EFFECT_START_NID]) { 4865 4866 if (spec->effects_switch[VOICE_FOCUS - 4867 EFFECT_START_NID]) { 4868 tmp = FLOAT_TWO; 4869 val = 1; 4870 } else 4871 tmp = FLOAT_ONE; 4872 4873 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4874 } 4875 } 4876 /* 4877 * For SBZ noise reduction, there's an extra command 4878 * to module ID 0x47. No clue why. 4879 */ 4880 if ((nid == NOISE_REDUCTION) && (spec->use_pci_mmio) 4881 && (spec->cur_mic_type != REAR_LINE_IN)) { 4882 if (spec->effects_switch[CRYSTAL_VOICE - 4883 EFFECT_START_NID]) { 4884 if (spec->effects_switch[NOISE_REDUCTION - 4885 EFFECT_START_NID]) 4886 tmp = FLOAT_ONE; 4887 else 4888 tmp = FLOAT_ZERO; 4889 } else 4890 tmp = FLOAT_ZERO; 4891 4892 dspio_set_uint_param(codec, 0x47, 0x00, tmp); 4893 } 4894 4895 /* If rear line in disable effects. */ 4896 if (spec->use_alt_functions && 4897 spec->in_enum_val == REAR_LINE_IN) 4898 val = 0; 4899 } 4900 4901 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n", 4902 nid, val); 4903 4904 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE; 4905 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid, 4906 ca0132_effects[idx].reqs[0], on); 4907 4908 if (err < 0) 4909 return 0; /* no changed */ 4910 4911 return 1; 4912 } 4913 4914 /* 4915 * Turn on/off Playback Enhancements 4916 */ 4917 static int ca0132_pe_switch_set(struct hda_codec *codec) 4918 { 4919 struct ca0132_spec *spec = codec->spec; 4920 hda_nid_t nid; 4921 int i, ret = 0; 4922 4923 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n", 4924 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]); 4925 4926 if (spec->use_alt_functions) 4927 ca0132_alt_select_out(codec); 4928 4929 i = OUT_EFFECT_START_NID - EFFECT_START_NID; 4930 nid = OUT_EFFECT_START_NID; 4931 /* PE affects all out effects */ 4932 for (; nid < OUT_EFFECT_END_NID; nid++, i++) 4933 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 4934 4935 return ret; 4936 } 4937 4938 /* Check if Mic1 is streaming, if so, stop streaming */ 4939 static int stop_mic1(struct hda_codec *codec) 4940 { 4941 struct ca0132_spec *spec = codec->spec; 4942 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0, 4943 AC_VERB_GET_CONV, 0); 4944 if (oldval != 0) 4945 snd_hda_codec_write(codec, spec->adcs[0], 0, 4946 AC_VERB_SET_CHANNEL_STREAMID, 4947 0); 4948 return oldval; 4949 } 4950 4951 /* Resume Mic1 streaming if it was stopped. */ 4952 static void resume_mic1(struct hda_codec *codec, unsigned int oldval) 4953 { 4954 struct ca0132_spec *spec = codec->spec; 4955 /* Restore the previous stream and channel */ 4956 if (oldval != 0) 4957 snd_hda_codec_write(codec, spec->adcs[0], 0, 4958 AC_VERB_SET_CHANNEL_STREAMID, 4959 oldval); 4960 } 4961 4962 /* 4963 * Turn on/off CrystalVoice 4964 */ 4965 static int ca0132_cvoice_switch_set(struct hda_codec *codec) 4966 { 4967 struct ca0132_spec *spec = codec->spec; 4968 hda_nid_t nid; 4969 int i, ret = 0; 4970 unsigned int oldval; 4971 4972 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n", 4973 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]); 4974 4975 i = IN_EFFECT_START_NID - EFFECT_START_NID; 4976 nid = IN_EFFECT_START_NID; 4977 /* CrystalVoice affects all in effects */ 4978 for (; nid < IN_EFFECT_END_NID; nid++, i++) 4979 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 4980 4981 /* including VoiceFX */ 4982 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0)); 4983 4984 /* set correct vipsource */ 4985 oldval = stop_mic1(codec); 4986 if (spec->use_alt_functions) 4987 ret |= ca0132_alt_set_vipsource(codec, 1); 4988 else 4989 ret |= ca0132_set_vipsource(codec, 1); 4990 resume_mic1(codec, oldval); 4991 return ret; 4992 } 4993 4994 static int ca0132_mic_boost_set(struct hda_codec *codec, long val) 4995 { 4996 struct ca0132_spec *spec = codec->spec; 4997 int ret = 0; 4998 4999 if (val) /* on */ 5000 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5001 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3); 5002 else /* off */ 5003 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5004 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0); 5005 5006 return ret; 5007 } 5008 5009 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val) 5010 { 5011 struct ca0132_spec *spec = codec->spec; 5012 int ret = 0; 5013 5014 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5015 HDA_INPUT, 0, HDA_AMP_VOLMASK, val); 5016 return ret; 5017 } 5018 5019 static int ae5_headphone_gain_set(struct hda_codec *codec, long val) 5020 { 5021 unsigned int i; 5022 5023 for (i = 0; i < 4; i++) 5024 ca0113_mmio_command_set(codec, 0x48, 0x11 + i, 5025 ae5_headphone_gain_presets[val].vals[i]); 5026 return 0; 5027 } 5028 5029 /* 5030 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone 5031 * amplifier to handle a 600 ohm load. 5032 */ 5033 static int zxr_headphone_gain_set(struct hda_codec *codec, long val) 5034 { 5035 ca0113_mmio_gpio_set(codec, 1, val); 5036 5037 return 0; 5038 } 5039 5040 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol, 5041 struct snd_ctl_elem_value *ucontrol) 5042 { 5043 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5044 hda_nid_t nid = get_amp_nid(kcontrol); 5045 hda_nid_t shared_nid = 0; 5046 bool effective; 5047 int ret = 0; 5048 struct ca0132_spec *spec = codec->spec; 5049 int auto_jack; 5050 5051 if (nid == VNID_HP_SEL) { 5052 auto_jack = 5053 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 5054 if (!auto_jack) { 5055 if (spec->use_alt_functions) 5056 ca0132_alt_select_out(codec); 5057 else 5058 ca0132_select_out(codec); 5059 } 5060 return 1; 5061 } 5062 5063 if (nid == VNID_AMIC1_SEL) { 5064 auto_jack = 5065 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 5066 if (!auto_jack) 5067 ca0132_select_mic(codec); 5068 return 1; 5069 } 5070 5071 if (nid == VNID_HP_ASEL) { 5072 if (spec->use_alt_functions) 5073 ca0132_alt_select_out(codec); 5074 else 5075 ca0132_select_out(codec); 5076 return 1; 5077 } 5078 5079 if (nid == VNID_AMIC1_ASEL) { 5080 ca0132_select_mic(codec); 5081 return 1; 5082 } 5083 5084 /* if effective conditions, then update hw immediately. */ 5085 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 5086 if (effective) { 5087 int dir = get_amp_direction(kcontrol); 5088 int ch = get_amp_channels(kcontrol); 5089 unsigned long pval; 5090 5091 mutex_lock(&codec->control_mutex); 5092 pval = kcontrol->private_value; 5093 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 5094 0, dir); 5095 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol); 5096 kcontrol->private_value = pval; 5097 mutex_unlock(&codec->control_mutex); 5098 } 5099 5100 return ret; 5101 } 5102 /* End of control change helpers. */ 5103 /* 5104 * Below I've added controls to mess with the effect levels, I've only enabled 5105 * them on the Sound Blaster Z, but they would probably also work on the 5106 * Chromebook. I figured they were probably tuned specifically for it, and left 5107 * out for a reason. 5108 */ 5109 5110 /* Sets DSP effect level from the sliders above the controls */ 5111 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid, 5112 const unsigned int *lookup, int idx) 5113 { 5114 int i = 0; 5115 unsigned int y; 5116 /* 5117 * For X_BASS, req 2 is actually crossover freq instead of 5118 * effect level 5119 */ 5120 if (nid == X_BASS) 5121 y = 2; 5122 else 5123 y = 1; 5124 5125 snd_hda_power_up(codec); 5126 if (nid == XBASS_XOVER) { 5127 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5128 if (ca0132_effects[i].nid == X_BASS) 5129 break; 5130 5131 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5132 ca0132_effects[i].reqs[1], 5133 &(lookup[idx - 1]), sizeof(unsigned int)); 5134 } else { 5135 /* Find the actual effect structure */ 5136 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5137 if (nid == ca0132_effects[i].nid) 5138 break; 5139 5140 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5141 ca0132_effects[i].reqs[y], 5142 &(lookup[idx]), sizeof(unsigned int)); 5143 } 5144 5145 snd_hda_power_down(codec); 5146 5147 return 0; 5148 } 5149 5150 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol, 5151 struct snd_ctl_elem_value *ucontrol) 5152 { 5153 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5154 struct ca0132_spec *spec = codec->spec; 5155 long *valp = ucontrol->value.integer.value; 5156 5157 *valp = spec->xbass_xover_freq; 5158 return 0; 5159 } 5160 5161 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol, 5162 struct snd_ctl_elem_value *ucontrol) 5163 { 5164 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5165 struct ca0132_spec *spec = codec->spec; 5166 hda_nid_t nid = get_amp_nid(kcontrol); 5167 long *valp = ucontrol->value.integer.value; 5168 int idx = nid - OUT_EFFECT_START_NID; 5169 5170 *valp = spec->fx_ctl_val[idx]; 5171 return 0; 5172 } 5173 5174 /* 5175 * The X-bass crossover starts at 10hz, so the min is 1. The 5176 * frequency is set in multiples of 10. 5177 */ 5178 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol, 5179 struct snd_ctl_elem_info *uinfo) 5180 { 5181 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5182 uinfo->count = 1; 5183 uinfo->value.integer.min = 1; 5184 uinfo->value.integer.max = 100; 5185 uinfo->value.integer.step = 1; 5186 5187 return 0; 5188 } 5189 5190 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol, 5191 struct snd_ctl_elem_info *uinfo) 5192 { 5193 int chs = get_amp_channels(kcontrol); 5194 5195 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5196 uinfo->count = chs == 3 ? 2 : 1; 5197 uinfo->value.integer.min = 0; 5198 uinfo->value.integer.max = 100; 5199 uinfo->value.integer.step = 1; 5200 5201 return 0; 5202 } 5203 5204 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol, 5205 struct snd_ctl_elem_value *ucontrol) 5206 { 5207 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5208 struct ca0132_spec *spec = codec->spec; 5209 hda_nid_t nid = get_amp_nid(kcontrol); 5210 long *valp = ucontrol->value.integer.value; 5211 int idx; 5212 5213 /* any change? */ 5214 if (spec->xbass_xover_freq == *valp) 5215 return 0; 5216 5217 spec->xbass_xover_freq = *valp; 5218 5219 idx = *valp; 5220 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx); 5221 5222 return 0; 5223 } 5224 5225 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol, 5226 struct snd_ctl_elem_value *ucontrol) 5227 { 5228 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5229 struct ca0132_spec *spec = codec->spec; 5230 hda_nid_t nid = get_amp_nid(kcontrol); 5231 long *valp = ucontrol->value.integer.value; 5232 int idx; 5233 5234 idx = nid - EFFECT_START_NID; 5235 /* any change? */ 5236 if (spec->fx_ctl_val[idx] == *valp) 5237 return 0; 5238 5239 spec->fx_ctl_val[idx] = *valp; 5240 5241 idx = *valp; 5242 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx); 5243 5244 return 0; 5245 } 5246 5247 5248 /* 5249 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original 5250 * only has off or full 30 dB, and didn't like making a volume slider that has 5251 * traditional 0-100 in alsamixer that goes in big steps. I like enum better. 5252 */ 5253 #define MIC_BOOST_NUM_OF_STEPS 4 5254 #define MIC_BOOST_ENUM_MAX_STRLEN 10 5255 5256 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol, 5257 struct snd_ctl_elem_info *uinfo) 5258 { 5259 char *sfx = "dB"; 5260 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5261 5262 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5263 uinfo->count = 1; 5264 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS; 5265 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS) 5266 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1; 5267 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx); 5268 strcpy(uinfo->value.enumerated.name, namestr); 5269 return 0; 5270 } 5271 5272 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol, 5273 struct snd_ctl_elem_value *ucontrol) 5274 { 5275 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5276 struct ca0132_spec *spec = codec->spec; 5277 5278 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val; 5279 return 0; 5280 } 5281 5282 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol, 5283 struct snd_ctl_elem_value *ucontrol) 5284 { 5285 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5286 struct ca0132_spec *spec = codec->spec; 5287 int sel = ucontrol->value.enumerated.item[0]; 5288 unsigned int items = MIC_BOOST_NUM_OF_STEPS; 5289 5290 if (sel >= items) 5291 return 0; 5292 5293 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n", 5294 sel); 5295 5296 spec->mic_boost_enum_val = sel; 5297 5298 if (spec->in_enum_val != REAR_LINE_IN) 5299 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5300 5301 return 1; 5302 } 5303 5304 /* 5305 * Sound BlasterX AE-5 Headphone Gain Controls. 5306 */ 5307 #define AE5_HEADPHONE_GAIN_MAX 3 5308 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol, 5309 struct snd_ctl_elem_info *uinfo) 5310 { 5311 char *sfx = " Ohms)"; 5312 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5313 5314 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5315 uinfo->count = 1; 5316 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX; 5317 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX) 5318 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1; 5319 sprintf(namestr, "%s %s", 5320 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name, 5321 sfx); 5322 strcpy(uinfo->value.enumerated.name, namestr); 5323 return 0; 5324 } 5325 5326 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol, 5327 struct snd_ctl_elem_value *ucontrol) 5328 { 5329 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5330 struct ca0132_spec *spec = codec->spec; 5331 5332 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val; 5333 return 0; 5334 } 5335 5336 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol, 5337 struct snd_ctl_elem_value *ucontrol) 5338 { 5339 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5340 struct ca0132_spec *spec = codec->spec; 5341 int sel = ucontrol->value.enumerated.item[0]; 5342 unsigned int items = AE5_HEADPHONE_GAIN_MAX; 5343 5344 if (sel >= items) 5345 return 0; 5346 5347 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n", 5348 sel); 5349 5350 spec->ae5_headphone_gain_val = sel; 5351 5352 if (spec->out_enum_val == HEADPHONE_OUT) 5353 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val); 5354 5355 return 1; 5356 } 5357 5358 /* 5359 * Sound BlasterX AE-5 sound filter enumerated control. 5360 */ 5361 #define AE5_SOUND_FILTER_MAX 3 5362 5363 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol, 5364 struct snd_ctl_elem_info *uinfo) 5365 { 5366 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5367 5368 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5369 uinfo->count = 1; 5370 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX; 5371 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX) 5372 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1; 5373 sprintf(namestr, "%s", 5374 ae5_filter_presets[uinfo->value.enumerated.item].name); 5375 strcpy(uinfo->value.enumerated.name, namestr); 5376 return 0; 5377 } 5378 5379 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol, 5380 struct snd_ctl_elem_value *ucontrol) 5381 { 5382 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5383 struct ca0132_spec *spec = codec->spec; 5384 5385 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val; 5386 return 0; 5387 } 5388 5389 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol, 5390 struct snd_ctl_elem_value *ucontrol) 5391 { 5392 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5393 struct ca0132_spec *spec = codec->spec; 5394 int sel = ucontrol->value.enumerated.item[0]; 5395 unsigned int items = AE5_SOUND_FILTER_MAX; 5396 5397 if (sel >= items) 5398 return 0; 5399 5400 codec_dbg(codec, "ae5_sound_filter: %s\n", 5401 ae5_filter_presets[sel].name); 5402 5403 spec->ae5_filter_val = sel; 5404 5405 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 5406 ae5_filter_presets[sel].val); 5407 5408 return 1; 5409 } 5410 5411 /* 5412 * Input Select Control for alternative ca0132 codecs. This exists because 5413 * front microphone has no auto-detect, and we need a way to set the rear 5414 * as line-in 5415 */ 5416 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol, 5417 struct snd_ctl_elem_info *uinfo) 5418 { 5419 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5420 uinfo->count = 1; 5421 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS; 5422 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS) 5423 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1; 5424 strcpy(uinfo->value.enumerated.name, 5425 in_src_str[uinfo->value.enumerated.item]); 5426 return 0; 5427 } 5428 5429 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol, 5430 struct snd_ctl_elem_value *ucontrol) 5431 { 5432 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5433 struct ca0132_spec *spec = codec->spec; 5434 5435 ucontrol->value.enumerated.item[0] = spec->in_enum_val; 5436 return 0; 5437 } 5438 5439 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol, 5440 struct snd_ctl_elem_value *ucontrol) 5441 { 5442 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5443 struct ca0132_spec *spec = codec->spec; 5444 int sel = ucontrol->value.enumerated.item[0]; 5445 unsigned int items = IN_SRC_NUM_OF_INPUTS; 5446 5447 if (sel >= items) 5448 return 0; 5449 5450 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n", 5451 sel, in_src_str[sel]); 5452 5453 spec->in_enum_val = sel; 5454 5455 ca0132_alt_select_in(codec); 5456 5457 return 1; 5458 } 5459 5460 /* Sound Blaster Z Output Select Control */ 5461 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol, 5462 struct snd_ctl_elem_info *uinfo) 5463 { 5464 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5465 uinfo->count = 1; 5466 uinfo->value.enumerated.items = NUM_OF_OUTPUTS; 5467 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS) 5468 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1; 5469 strcpy(uinfo->value.enumerated.name, 5470 alt_out_presets[uinfo->value.enumerated.item].name); 5471 return 0; 5472 } 5473 5474 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol, 5475 struct snd_ctl_elem_value *ucontrol) 5476 { 5477 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5478 struct ca0132_spec *spec = codec->spec; 5479 5480 ucontrol->value.enumerated.item[0] = spec->out_enum_val; 5481 return 0; 5482 } 5483 5484 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol, 5485 struct snd_ctl_elem_value *ucontrol) 5486 { 5487 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5488 struct ca0132_spec *spec = codec->spec; 5489 int sel = ucontrol->value.enumerated.item[0]; 5490 unsigned int items = NUM_OF_OUTPUTS; 5491 unsigned int auto_jack; 5492 5493 if (sel >= items) 5494 return 0; 5495 5496 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n", 5497 sel, alt_out_presets[sel].name); 5498 5499 spec->out_enum_val = sel; 5500 5501 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 5502 5503 if (!auto_jack) 5504 ca0132_alt_select_out(codec); 5505 5506 return 1; 5507 } 5508 5509 /* 5510 * Smart Volume output setting control. Three different settings, Normal, 5511 * which takes the value from the smart volume slider. The two others, loud 5512 * and night, disregard the slider value and have uneditable values. 5513 */ 5514 #define NUM_OF_SVM_SETTINGS 3 5515 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" }; 5516 5517 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol, 5518 struct snd_ctl_elem_info *uinfo) 5519 { 5520 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5521 uinfo->count = 1; 5522 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS; 5523 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS) 5524 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1; 5525 strcpy(uinfo->value.enumerated.name, 5526 out_svm_set_enum_str[uinfo->value.enumerated.item]); 5527 return 0; 5528 } 5529 5530 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol, 5531 struct snd_ctl_elem_value *ucontrol) 5532 { 5533 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5534 struct ca0132_spec *spec = codec->spec; 5535 5536 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting; 5537 return 0; 5538 } 5539 5540 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol, 5541 struct snd_ctl_elem_value *ucontrol) 5542 { 5543 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5544 struct ca0132_spec *spec = codec->spec; 5545 int sel = ucontrol->value.enumerated.item[0]; 5546 unsigned int items = NUM_OF_SVM_SETTINGS; 5547 unsigned int idx = SMART_VOLUME - EFFECT_START_NID; 5548 unsigned int tmp; 5549 5550 if (sel >= items) 5551 return 0; 5552 5553 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n", 5554 sel, out_svm_set_enum_str[sel]); 5555 5556 spec->smart_volume_setting = sel; 5557 5558 switch (sel) { 5559 case 0: 5560 tmp = FLOAT_ZERO; 5561 break; 5562 case 1: 5563 tmp = FLOAT_ONE; 5564 break; 5565 case 2: 5566 tmp = FLOAT_TWO; 5567 break; 5568 default: 5569 tmp = FLOAT_ZERO; 5570 break; 5571 } 5572 /* Req 2 is the Smart Volume Setting req. */ 5573 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 5574 ca0132_effects[idx].reqs[2], tmp); 5575 return 1; 5576 } 5577 5578 /* Sound Blaster Z EQ preset controls */ 5579 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol, 5580 struct snd_ctl_elem_info *uinfo) 5581 { 5582 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 5583 5584 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5585 uinfo->count = 1; 5586 uinfo->value.enumerated.items = items; 5587 if (uinfo->value.enumerated.item >= items) 5588 uinfo->value.enumerated.item = items - 1; 5589 strcpy(uinfo->value.enumerated.name, 5590 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name); 5591 return 0; 5592 } 5593 5594 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol, 5595 struct snd_ctl_elem_value *ucontrol) 5596 { 5597 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5598 struct ca0132_spec *spec = codec->spec; 5599 5600 ucontrol->value.enumerated.item[0] = spec->eq_preset_val; 5601 return 0; 5602 } 5603 5604 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol, 5605 struct snd_ctl_elem_value *ucontrol) 5606 { 5607 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5608 struct ca0132_spec *spec = codec->spec; 5609 int i, err = 0; 5610 int sel = ucontrol->value.enumerated.item[0]; 5611 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 5612 5613 if (sel >= items) 5614 return 0; 5615 5616 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel, 5617 ca0132_alt_eq_presets[sel].name); 5618 /* 5619 * Idx 0 is default. 5620 * Default needs to qualify with CrystalVoice state. 5621 */ 5622 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) { 5623 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid, 5624 ca0132_alt_eq_enum.reqs[i], 5625 ca0132_alt_eq_presets[sel].vals[i]); 5626 if (err < 0) 5627 break; 5628 } 5629 5630 if (err >= 0) 5631 spec->eq_preset_val = sel; 5632 5633 return 1; 5634 } 5635 5636 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol, 5637 struct snd_ctl_elem_info *uinfo) 5638 { 5639 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets); 5640 5641 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5642 uinfo->count = 1; 5643 uinfo->value.enumerated.items = items; 5644 if (uinfo->value.enumerated.item >= items) 5645 uinfo->value.enumerated.item = items - 1; 5646 strcpy(uinfo->value.enumerated.name, 5647 ca0132_voicefx_presets[uinfo->value.enumerated.item].name); 5648 return 0; 5649 } 5650 5651 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol, 5652 struct snd_ctl_elem_value *ucontrol) 5653 { 5654 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5655 struct ca0132_spec *spec = codec->spec; 5656 5657 ucontrol->value.enumerated.item[0] = spec->voicefx_val; 5658 return 0; 5659 } 5660 5661 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol, 5662 struct snd_ctl_elem_value *ucontrol) 5663 { 5664 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5665 struct ca0132_spec *spec = codec->spec; 5666 int i, err = 0; 5667 int sel = ucontrol->value.enumerated.item[0]; 5668 5669 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets)) 5670 return 0; 5671 5672 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n", 5673 sel, ca0132_voicefx_presets[sel].name); 5674 5675 /* 5676 * Idx 0 is default. 5677 * Default needs to qualify with CrystalVoice state. 5678 */ 5679 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) { 5680 err = dspio_set_uint_param(codec, ca0132_voicefx.mid, 5681 ca0132_voicefx.reqs[i], 5682 ca0132_voicefx_presets[sel].vals[i]); 5683 if (err < 0) 5684 break; 5685 } 5686 5687 if (err >= 0) { 5688 spec->voicefx_val = sel; 5689 /* enable voice fx */ 5690 ca0132_voicefx_set(codec, (sel ? 1 : 0)); 5691 } 5692 5693 return 1; 5694 } 5695 5696 static int ca0132_switch_get(struct snd_kcontrol *kcontrol, 5697 struct snd_ctl_elem_value *ucontrol) 5698 { 5699 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5700 struct ca0132_spec *spec = codec->spec; 5701 hda_nid_t nid = get_amp_nid(kcontrol); 5702 int ch = get_amp_channels(kcontrol); 5703 long *valp = ucontrol->value.integer.value; 5704 5705 /* vnode */ 5706 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 5707 if (ch & 1) { 5708 *valp = spec->vnode_lswitch[nid - VNODE_START_NID]; 5709 valp++; 5710 } 5711 if (ch & 2) { 5712 *valp = spec->vnode_rswitch[nid - VNODE_START_NID]; 5713 valp++; 5714 } 5715 return 0; 5716 } 5717 5718 /* effects, include PE and CrystalVoice */ 5719 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) { 5720 *valp = spec->effects_switch[nid - EFFECT_START_NID]; 5721 return 0; 5722 } 5723 5724 /* mic boost */ 5725 if (nid == spec->input_pins[0]) { 5726 *valp = spec->cur_mic_boost; 5727 return 0; 5728 } 5729 5730 return 0; 5731 } 5732 5733 static int ca0132_switch_put(struct snd_kcontrol *kcontrol, 5734 struct snd_ctl_elem_value *ucontrol) 5735 { 5736 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5737 struct ca0132_spec *spec = codec->spec; 5738 hda_nid_t nid = get_amp_nid(kcontrol); 5739 int ch = get_amp_channels(kcontrol); 5740 long *valp = ucontrol->value.integer.value; 5741 int changed = 1; 5742 5743 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n", 5744 nid, *valp); 5745 5746 snd_hda_power_up(codec); 5747 /* vnode */ 5748 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 5749 if (ch & 1) { 5750 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp; 5751 valp++; 5752 } 5753 if (ch & 2) { 5754 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp; 5755 valp++; 5756 } 5757 changed = ca0132_vnode_switch_set(kcontrol, ucontrol); 5758 goto exit; 5759 } 5760 5761 /* PE */ 5762 if (nid == PLAY_ENHANCEMENT) { 5763 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 5764 changed = ca0132_pe_switch_set(codec); 5765 goto exit; 5766 } 5767 5768 /* CrystalVoice */ 5769 if (nid == CRYSTAL_VOICE) { 5770 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 5771 changed = ca0132_cvoice_switch_set(codec); 5772 goto exit; 5773 } 5774 5775 /* out and in effects */ 5776 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) || 5777 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) { 5778 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 5779 changed = ca0132_effects_set(codec, nid, *valp); 5780 goto exit; 5781 } 5782 5783 /* mic boost */ 5784 if (nid == spec->input_pins[0]) { 5785 spec->cur_mic_boost = *valp; 5786 if (spec->use_alt_functions) { 5787 if (spec->in_enum_val != REAR_LINE_IN) 5788 changed = ca0132_mic_boost_set(codec, *valp); 5789 } else { 5790 /* Mic boost does not apply to Digital Mic */ 5791 if (spec->cur_mic_type != DIGITAL_MIC) 5792 changed = ca0132_mic_boost_set(codec, *valp); 5793 } 5794 5795 goto exit; 5796 } 5797 5798 if (nid == ZXR_HEADPHONE_GAIN) { 5799 spec->zxr_gain_set = *valp; 5800 if (spec->cur_out_type == HEADPHONE_OUT) 5801 changed = zxr_headphone_gain_set(codec, *valp); 5802 else 5803 changed = 0; 5804 5805 goto exit; 5806 } 5807 5808 exit: 5809 snd_hda_power_down(codec); 5810 return changed; 5811 } 5812 5813 /* 5814 * Volume related 5815 */ 5816 /* 5817 * Sets the internal DSP decibel level to match the DAC for output, and the 5818 * ADC for input. Currently only the SBZ sets dsp capture volume level, and 5819 * all alternative codecs set DSP playback volume. 5820 */ 5821 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid) 5822 { 5823 struct ca0132_spec *spec = codec->spec; 5824 unsigned int dsp_dir; 5825 unsigned int lookup_val; 5826 5827 if (nid == VNID_SPK) 5828 dsp_dir = DSP_VOL_OUT; 5829 else 5830 dsp_dir = DSP_VOL_IN; 5831 5832 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID]; 5833 5834 dspio_set_uint_param(codec, 5835 ca0132_alt_vol_ctls[dsp_dir].mid, 5836 ca0132_alt_vol_ctls[dsp_dir].reqs[0], 5837 float_vol_db_lookup[lookup_val]); 5838 5839 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID]; 5840 5841 dspio_set_uint_param(codec, 5842 ca0132_alt_vol_ctls[dsp_dir].mid, 5843 ca0132_alt_vol_ctls[dsp_dir].reqs[1], 5844 float_vol_db_lookup[lookup_val]); 5845 5846 dspio_set_uint_param(codec, 5847 ca0132_alt_vol_ctls[dsp_dir].mid, 5848 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO); 5849 } 5850 5851 static int ca0132_volume_info(struct snd_kcontrol *kcontrol, 5852 struct snd_ctl_elem_info *uinfo) 5853 { 5854 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5855 struct ca0132_spec *spec = codec->spec; 5856 hda_nid_t nid = get_amp_nid(kcontrol); 5857 int ch = get_amp_channels(kcontrol); 5858 int dir = get_amp_direction(kcontrol); 5859 unsigned long pval; 5860 int err; 5861 5862 switch (nid) { 5863 case VNID_SPK: 5864 /* follow shared_out info */ 5865 nid = spec->shared_out_nid; 5866 mutex_lock(&codec->control_mutex); 5867 pval = kcontrol->private_value; 5868 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 5869 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 5870 kcontrol->private_value = pval; 5871 mutex_unlock(&codec->control_mutex); 5872 break; 5873 case VNID_MIC: 5874 /* follow shared_mic info */ 5875 nid = spec->shared_mic_nid; 5876 mutex_lock(&codec->control_mutex); 5877 pval = kcontrol->private_value; 5878 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 5879 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 5880 kcontrol->private_value = pval; 5881 mutex_unlock(&codec->control_mutex); 5882 break; 5883 default: 5884 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 5885 } 5886 return err; 5887 } 5888 5889 static int ca0132_volume_get(struct snd_kcontrol *kcontrol, 5890 struct snd_ctl_elem_value *ucontrol) 5891 { 5892 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5893 struct ca0132_spec *spec = codec->spec; 5894 hda_nid_t nid = get_amp_nid(kcontrol); 5895 int ch = get_amp_channels(kcontrol); 5896 long *valp = ucontrol->value.integer.value; 5897 5898 /* store the left and right volume */ 5899 if (ch & 1) { 5900 *valp = spec->vnode_lvol[nid - VNODE_START_NID]; 5901 valp++; 5902 } 5903 if (ch & 2) { 5904 *valp = spec->vnode_rvol[nid - VNODE_START_NID]; 5905 valp++; 5906 } 5907 return 0; 5908 } 5909 5910 static int ca0132_volume_put(struct snd_kcontrol *kcontrol, 5911 struct snd_ctl_elem_value *ucontrol) 5912 { 5913 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5914 struct ca0132_spec *spec = codec->spec; 5915 hda_nid_t nid = get_amp_nid(kcontrol); 5916 int ch = get_amp_channels(kcontrol); 5917 long *valp = ucontrol->value.integer.value; 5918 hda_nid_t shared_nid = 0; 5919 bool effective; 5920 int changed = 1; 5921 5922 /* store the left and right volume */ 5923 if (ch & 1) { 5924 spec->vnode_lvol[nid - VNODE_START_NID] = *valp; 5925 valp++; 5926 } 5927 if (ch & 2) { 5928 spec->vnode_rvol[nid - VNODE_START_NID] = *valp; 5929 valp++; 5930 } 5931 5932 /* if effective conditions, then update hw immediately. */ 5933 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 5934 if (effective) { 5935 int dir = get_amp_direction(kcontrol); 5936 unsigned long pval; 5937 5938 snd_hda_power_up(codec); 5939 mutex_lock(&codec->control_mutex); 5940 pval = kcontrol->private_value; 5941 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 5942 0, dir); 5943 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 5944 kcontrol->private_value = pval; 5945 mutex_unlock(&codec->control_mutex); 5946 snd_hda_power_down(codec); 5947 } 5948 5949 return changed; 5950 } 5951 5952 /* 5953 * This function is the same as the one above, because using an if statement 5954 * inside of the above volume control for the DSP volume would cause too much 5955 * lag. This is a lot more smooth. 5956 */ 5957 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol, 5958 struct snd_ctl_elem_value *ucontrol) 5959 { 5960 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5961 struct ca0132_spec *spec = codec->spec; 5962 hda_nid_t nid = get_amp_nid(kcontrol); 5963 int ch = get_amp_channels(kcontrol); 5964 long *valp = ucontrol->value.integer.value; 5965 hda_nid_t vnid = 0; 5966 int changed = 1; 5967 5968 switch (nid) { 5969 case 0x02: 5970 vnid = VNID_SPK; 5971 break; 5972 case 0x07: 5973 vnid = VNID_MIC; 5974 break; 5975 } 5976 5977 /* store the left and right volume */ 5978 if (ch & 1) { 5979 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp; 5980 valp++; 5981 } 5982 if (ch & 2) { 5983 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp; 5984 valp++; 5985 } 5986 5987 snd_hda_power_up(codec); 5988 ca0132_alt_dsp_volume_put(codec, vnid); 5989 mutex_lock(&codec->control_mutex); 5990 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 5991 mutex_unlock(&codec->control_mutex); 5992 snd_hda_power_down(codec); 5993 5994 return changed; 5995 } 5996 5997 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag, 5998 unsigned int size, unsigned int __user *tlv) 5999 { 6000 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6001 struct ca0132_spec *spec = codec->spec; 6002 hda_nid_t nid = get_amp_nid(kcontrol); 6003 int ch = get_amp_channels(kcontrol); 6004 int dir = get_amp_direction(kcontrol); 6005 unsigned long pval; 6006 int err; 6007 6008 switch (nid) { 6009 case VNID_SPK: 6010 /* follow shared_out tlv */ 6011 nid = spec->shared_out_nid; 6012 mutex_lock(&codec->control_mutex); 6013 pval = kcontrol->private_value; 6014 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6015 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6016 kcontrol->private_value = pval; 6017 mutex_unlock(&codec->control_mutex); 6018 break; 6019 case VNID_MIC: 6020 /* follow shared_mic tlv */ 6021 nid = spec->shared_mic_nid; 6022 mutex_lock(&codec->control_mutex); 6023 pval = kcontrol->private_value; 6024 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6025 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6026 kcontrol->private_value = pval; 6027 mutex_unlock(&codec->control_mutex); 6028 break; 6029 default: 6030 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6031 } 6032 return err; 6033 } 6034 6035 /* Add volume slider control for effect level */ 6036 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid, 6037 const char *pfx, int dir) 6038 { 6039 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6040 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6041 struct snd_kcontrol_new knew = 6042 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 6043 6044 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]); 6045 6046 knew.tlv.c = NULL; 6047 6048 switch (nid) { 6049 case XBASS_XOVER: 6050 knew.info = ca0132_alt_xbass_xover_slider_info; 6051 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 6052 knew.put = ca0132_alt_xbass_xover_slider_put; 6053 break; 6054 default: 6055 knew.info = ca0132_alt_effect_slider_info; 6056 knew.get = ca0132_alt_slider_ctl_get; 6057 knew.put = ca0132_alt_effect_slider_put; 6058 knew.private_value = 6059 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 6060 break; 6061 } 6062 6063 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6064 } 6065 6066 /* 6067 * Added FX: prefix for the alternative codecs, because otherwise the surround 6068 * effect would conflict with the Surround sound volume control. Also seems more 6069 * clear as to what the switches do. Left alone for others. 6070 */ 6071 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid, 6072 const char *pfx, int dir) 6073 { 6074 struct ca0132_spec *spec = codec->spec; 6075 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6076 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6077 struct snd_kcontrol_new knew = 6078 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type); 6079 /* If using alt_controls, add FX: prefix. But, don't add FX: 6080 * prefix to OutFX or InFX enable controls. 6081 */ 6082 if ((spec->use_alt_controls) && (nid <= IN_EFFECT_END_NID)) 6083 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]); 6084 else 6085 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]); 6086 6087 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6088 } 6089 6090 static int add_voicefx(struct hda_codec *codec) 6091 { 6092 struct snd_kcontrol_new knew = 6093 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name, 6094 VOICEFX, 1, 0, HDA_INPUT); 6095 knew.info = ca0132_voicefx_info; 6096 knew.get = ca0132_voicefx_get; 6097 knew.put = ca0132_voicefx_put; 6098 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec)); 6099 } 6100 6101 /* Create the EQ Preset control */ 6102 static int add_ca0132_alt_eq_presets(struct hda_codec *codec) 6103 { 6104 struct snd_kcontrol_new knew = 6105 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name, 6106 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT); 6107 knew.info = ca0132_alt_eq_preset_info; 6108 knew.get = ca0132_alt_eq_preset_get; 6109 knew.put = ca0132_alt_eq_preset_put; 6110 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM, 6111 snd_ctl_new1(&knew, codec)); 6112 } 6113 6114 /* 6115 * Add enumerated control for the three different settings of the smart volume 6116 * output effect. Normal just uses the slider value, and loud and night are 6117 * their own things that ignore that value. 6118 */ 6119 static int ca0132_alt_add_svm_enum(struct hda_codec *codec) 6120 { 6121 struct snd_kcontrol_new knew = 6122 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting", 6123 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT); 6124 knew.info = ca0132_alt_svm_setting_info; 6125 knew.get = ca0132_alt_svm_setting_get; 6126 knew.put = ca0132_alt_svm_setting_put; 6127 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM, 6128 snd_ctl_new1(&knew, codec)); 6129 6130 } 6131 6132 /* 6133 * Create an Output Select enumerated control for codecs with surround 6134 * out capabilities. 6135 */ 6136 static int ca0132_alt_add_output_enum(struct hda_codec *codec) 6137 { 6138 struct snd_kcontrol_new knew = 6139 HDA_CODEC_MUTE_MONO("Output Select", 6140 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT); 6141 knew.info = ca0132_alt_output_select_get_info; 6142 knew.get = ca0132_alt_output_select_get; 6143 knew.put = ca0132_alt_output_select_put; 6144 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM, 6145 snd_ctl_new1(&knew, codec)); 6146 } 6147 6148 /* 6149 * Create an Input Source enumerated control for the alternate ca0132 codecs 6150 * because the front microphone has no auto-detect, and Line-in has to be set 6151 * somehow. 6152 */ 6153 static int ca0132_alt_add_input_enum(struct hda_codec *codec) 6154 { 6155 struct snd_kcontrol_new knew = 6156 HDA_CODEC_MUTE_MONO("Input Source", 6157 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT); 6158 knew.info = ca0132_alt_input_source_info; 6159 knew.get = ca0132_alt_input_source_get; 6160 knew.put = ca0132_alt_input_source_put; 6161 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM, 6162 snd_ctl_new1(&knew, codec)); 6163 } 6164 6165 /* 6166 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds 6167 * more control than the original mic boost, which is either full 30dB or off. 6168 */ 6169 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec) 6170 { 6171 struct snd_kcontrol_new knew = 6172 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch", 6173 MIC_BOOST_ENUM, 1, 0, HDA_INPUT); 6174 knew.info = ca0132_alt_mic_boost_info; 6175 knew.get = ca0132_alt_mic_boost_get; 6176 knew.put = ca0132_alt_mic_boost_put; 6177 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM, 6178 snd_ctl_new1(&knew, codec)); 6179 6180 } 6181 6182 /* 6183 * Add headphone gain enumerated control for the AE-5. This switches between 6184 * three modes, low, medium, and high. When non-headphone outputs are selected, 6185 * it is automatically set to high. This is the same behavior as Windows. 6186 */ 6187 static int ae5_add_headphone_gain_enum(struct hda_codec *codec) 6188 { 6189 struct snd_kcontrol_new knew = 6190 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain", 6191 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT); 6192 knew.info = ae5_headphone_gain_info; 6193 knew.get = ae5_headphone_gain_get; 6194 knew.put = ae5_headphone_gain_put; 6195 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM, 6196 snd_ctl_new1(&knew, codec)); 6197 } 6198 6199 /* 6200 * Add sound filter enumerated control for the AE-5. This adds three different 6201 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've 6202 * read into it, it changes the DAC's interpolation filter. 6203 */ 6204 static int ae5_add_sound_filter_enum(struct hda_codec *codec) 6205 { 6206 struct snd_kcontrol_new knew = 6207 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter", 6208 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT); 6209 knew.info = ae5_sound_filter_info; 6210 knew.get = ae5_sound_filter_get; 6211 knew.put = ae5_sound_filter_put; 6212 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM, 6213 snd_ctl_new1(&knew, codec)); 6214 } 6215 6216 static int zxr_add_headphone_gain_switch(struct hda_codec *codec) 6217 { 6218 struct snd_kcontrol_new knew = 6219 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain", 6220 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT); 6221 6222 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN, 6223 snd_ctl_new1(&knew, codec)); 6224 } 6225 6226 /* 6227 * Need to create slave controls for the alternate codecs that have surround 6228 * capabilities. 6229 */ 6230 static const char * const ca0132_alt_slave_pfxs[] = { 6231 "Front", "Surround", "Center", "LFE", NULL, 6232 }; 6233 6234 /* 6235 * Also need special channel map, because the default one is incorrect. 6236 * I think this has to do with the pin for rear surround being 0x11, 6237 * and the center/lfe being 0x10. Usually the pin order is the opposite. 6238 */ 6239 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = { 6240 { .channels = 2, 6241 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } }, 6242 { .channels = 4, 6243 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6244 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6245 { .channels = 6, 6246 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6247 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE, 6248 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6249 { } 6250 }; 6251 6252 /* Add the correct chmap for streams with 6 channels. */ 6253 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec) 6254 { 6255 int err = 0; 6256 struct hda_pcm *pcm; 6257 6258 list_for_each_entry(pcm, &codec->pcm_list_head, list) { 6259 struct hda_pcm_stream *hinfo = 6260 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 6261 struct snd_pcm_chmap *chmap; 6262 const struct snd_pcm_chmap_elem *elem; 6263 6264 elem = ca0132_alt_chmaps; 6265 if (hinfo->channels_max == 6) { 6266 err = snd_pcm_add_chmap_ctls(pcm->pcm, 6267 SNDRV_PCM_STREAM_PLAYBACK, 6268 elem, hinfo->channels_max, 0, &chmap); 6269 if (err < 0) 6270 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!"); 6271 } 6272 } 6273 } 6274 6275 /* 6276 * When changing Node IDs for Mixer Controls below, make sure to update 6277 * Node IDs in ca0132_config() as well. 6278 */ 6279 static const struct snd_kcontrol_new ca0132_mixer[] = { 6280 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT), 6281 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT), 6282 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 6283 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6284 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT), 6285 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT), 6286 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6287 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6288 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch", 6289 0x12, 1, HDA_INPUT), 6290 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch", 6291 VNID_HP_SEL, 1, HDA_OUTPUT), 6292 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch", 6293 VNID_AMIC1_SEL, 1, HDA_INPUT), 6294 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6295 VNID_HP_ASEL, 1, HDA_OUTPUT), 6296 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch", 6297 VNID_AMIC1_ASEL, 1, HDA_INPUT), 6298 { } /* end */ 6299 }; 6300 6301 /* 6302 * Desktop specific control mixer. Removes auto-detect for mic, and adds 6303 * surround controls. Also sets both the Front Playback and Capture Volume 6304 * controls to alt so they set the DSP's decibel level. 6305 */ 6306 static const struct snd_kcontrol_new desktop_mixer[] = { 6307 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 6308 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 6309 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 6310 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 6311 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 6312 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 6313 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 6314 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 6315 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT), 6316 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6317 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6318 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6319 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6320 VNID_HP_ASEL, 1, HDA_OUTPUT), 6321 { } /* end */ 6322 }; 6323 6324 /* 6325 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture 6326 * because it doesn't set decibel levels for the DSP for capture. 6327 */ 6328 static const struct snd_kcontrol_new r3di_mixer[] = { 6329 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 6330 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 6331 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 6332 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 6333 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 6334 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 6335 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 6336 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 6337 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 6338 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6339 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6340 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6341 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6342 VNID_HP_ASEL, 1, HDA_OUTPUT), 6343 { } /* end */ 6344 }; 6345 6346 static int ca0132_build_controls(struct hda_codec *codec) 6347 { 6348 struct ca0132_spec *spec = codec->spec; 6349 int i, num_fx, num_sliders; 6350 int err = 0; 6351 6352 /* Add Mixer controls */ 6353 for (i = 0; i < spec->num_mixers; i++) { 6354 err = snd_hda_add_new_ctls(codec, spec->mixers[i]); 6355 if (err < 0) 6356 return err; 6357 } 6358 /* Setup vmaster with surround slaves for desktop ca0132 devices */ 6359 if (spec->use_alt_functions) { 6360 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT, 6361 spec->tlv); 6362 snd_hda_add_vmaster(codec, "Master Playback Volume", 6363 spec->tlv, ca0132_alt_slave_pfxs, 6364 "Playback Volume"); 6365 err = __snd_hda_add_vmaster(codec, "Master Playback Switch", 6366 NULL, ca0132_alt_slave_pfxs, 6367 "Playback Switch", 6368 true, &spec->vmaster_mute.sw_kctl); 6369 if (err < 0) 6370 return err; 6371 } 6372 6373 /* Add in and out effects controls. 6374 * VoiceFX, PE and CrystalVoice are added separately. 6375 */ 6376 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 6377 for (i = 0; i < num_fx; i++) { 6378 /* Desktop cards break if Echo Cancellation is used. */ 6379 if (spec->use_pci_mmio) { 6380 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID + 6381 OUT_EFFECTS_COUNT)) 6382 continue; 6383 } 6384 6385 err = add_fx_switch(codec, ca0132_effects[i].nid, 6386 ca0132_effects[i].name, 6387 ca0132_effects[i].direct); 6388 if (err < 0) 6389 return err; 6390 } 6391 /* 6392 * If codec has use_alt_controls set to true, add effect level sliders, 6393 * EQ presets, and Smart Volume presets. Also, change names to add FX 6394 * prefix, and change PlayEnhancement and CrystalVoice to match. 6395 */ 6396 if (spec->use_alt_controls) { 6397 err = ca0132_alt_add_svm_enum(codec); 6398 if (err < 0) 6399 return err; 6400 6401 err = add_ca0132_alt_eq_presets(codec); 6402 if (err < 0) 6403 return err; 6404 6405 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 6406 "Enable OutFX", 0); 6407 if (err < 0) 6408 return err; 6409 6410 err = add_fx_switch(codec, CRYSTAL_VOICE, 6411 "Enable InFX", 1); 6412 if (err < 0) 6413 return err; 6414 6415 num_sliders = OUT_EFFECTS_COUNT - 1; 6416 for (i = 0; i < num_sliders; i++) { 6417 err = ca0132_alt_add_effect_slider(codec, 6418 ca0132_effects[i].nid, 6419 ca0132_effects[i].name, 6420 ca0132_effects[i].direct); 6421 if (err < 0) 6422 return err; 6423 } 6424 6425 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER, 6426 "X-Bass Crossover", EFX_DIR_OUT); 6427 6428 if (err < 0) 6429 return err; 6430 } else { 6431 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 6432 "PlayEnhancement", 0); 6433 if (err < 0) 6434 return err; 6435 6436 err = add_fx_switch(codec, CRYSTAL_VOICE, 6437 "CrystalVoice", 1); 6438 if (err < 0) 6439 return err; 6440 } 6441 err = add_voicefx(codec); 6442 if (err < 0) 6443 return err; 6444 6445 /* 6446 * If the codec uses alt_functions, you need the enumerated controls 6447 * to select the new outputs and inputs, plus add the new mic boost 6448 * setting control. 6449 */ 6450 if (spec->use_alt_functions) { 6451 err = ca0132_alt_add_output_enum(codec); 6452 if (err < 0) 6453 return err; 6454 err = ca0132_alt_add_mic_boost_enum(codec); 6455 if (err < 0) 6456 return err; 6457 /* 6458 * ZxR only has microphone input, there is no front panel 6459 * header on the card, and aux-in is handled by the DBPro board. 6460 */ 6461 if (spec->quirk != QUIRK_ZXR) { 6462 err = ca0132_alt_add_input_enum(codec); 6463 if (err < 0) 6464 return err; 6465 } 6466 } 6467 6468 if (spec->quirk == QUIRK_AE5) { 6469 err = ae5_add_headphone_gain_enum(codec); 6470 if (err < 0) 6471 return err; 6472 err = ae5_add_sound_filter_enum(codec); 6473 if (err < 0) 6474 return err; 6475 } 6476 6477 if (spec->quirk == QUIRK_ZXR) { 6478 err = zxr_add_headphone_gain_switch(codec); 6479 if (err < 0) 6480 return err; 6481 } 6482 #ifdef ENABLE_TUNING_CONTROLS 6483 add_tuning_ctls(codec); 6484 #endif 6485 6486 err = snd_hda_jack_add_kctls(codec, &spec->autocfg); 6487 if (err < 0) 6488 return err; 6489 6490 if (spec->dig_out) { 6491 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 6492 spec->dig_out); 6493 if (err < 0) 6494 return err; 6495 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout); 6496 if (err < 0) 6497 return err; 6498 /* spec->multiout.share_spdif = 1; */ 6499 } 6500 6501 if (spec->dig_in) { 6502 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 6503 if (err < 0) 6504 return err; 6505 } 6506 6507 if (spec->use_alt_functions) 6508 ca0132_alt_add_chmap_ctls(codec); 6509 6510 return 0; 6511 } 6512 6513 static int dbpro_build_controls(struct hda_codec *codec) 6514 { 6515 struct ca0132_spec *spec = codec->spec; 6516 int err = 0; 6517 6518 if (spec->dig_out) { 6519 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 6520 spec->dig_out); 6521 if (err < 0) 6522 return err; 6523 } 6524 6525 if (spec->dig_in) { 6526 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 6527 if (err < 0) 6528 return err; 6529 } 6530 6531 return 0; 6532 } 6533 6534 /* 6535 * PCM 6536 */ 6537 static const struct hda_pcm_stream ca0132_pcm_analog_playback = { 6538 .substreams = 1, 6539 .channels_min = 2, 6540 .channels_max = 6, 6541 .ops = { 6542 .prepare = ca0132_playback_pcm_prepare, 6543 .cleanup = ca0132_playback_pcm_cleanup, 6544 .get_delay = ca0132_playback_pcm_delay, 6545 }, 6546 }; 6547 6548 static const struct hda_pcm_stream ca0132_pcm_analog_capture = { 6549 .substreams = 1, 6550 .channels_min = 2, 6551 .channels_max = 2, 6552 .ops = { 6553 .prepare = ca0132_capture_pcm_prepare, 6554 .cleanup = ca0132_capture_pcm_cleanup, 6555 .get_delay = ca0132_capture_pcm_delay, 6556 }, 6557 }; 6558 6559 static const struct hda_pcm_stream ca0132_pcm_digital_playback = { 6560 .substreams = 1, 6561 .channels_min = 2, 6562 .channels_max = 2, 6563 .ops = { 6564 .open = ca0132_dig_playback_pcm_open, 6565 .close = ca0132_dig_playback_pcm_close, 6566 .prepare = ca0132_dig_playback_pcm_prepare, 6567 .cleanup = ca0132_dig_playback_pcm_cleanup 6568 }, 6569 }; 6570 6571 static const struct hda_pcm_stream ca0132_pcm_digital_capture = { 6572 .substreams = 1, 6573 .channels_min = 2, 6574 .channels_max = 2, 6575 }; 6576 6577 static int ca0132_build_pcms(struct hda_codec *codec) 6578 { 6579 struct ca0132_spec *spec = codec->spec; 6580 struct hda_pcm *info; 6581 6582 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog"); 6583 if (!info) 6584 return -ENOMEM; 6585 if (spec->use_alt_functions) { 6586 info->own_chmap = true; 6587 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap 6588 = ca0132_alt_chmaps; 6589 } 6590 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback; 6591 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0]; 6592 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max = 6593 spec->multiout.max_channels; 6594 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 6595 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 6596 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 6597 6598 /* With the DSP enabled, desktops don't use this ADC. */ 6599 if (!spec->use_alt_functions) { 6600 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2"); 6601 if (!info) 6602 return -ENOMEM; 6603 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 6604 ca0132_pcm_analog_capture; 6605 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 6606 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1]; 6607 } 6608 6609 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear"); 6610 if (!info) 6611 return -ENOMEM; 6612 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 6613 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 6614 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2]; 6615 6616 if (!spec->dig_out && !spec->dig_in) 6617 return 0; 6618 6619 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 6620 if (!info) 6621 return -ENOMEM; 6622 info->pcm_type = HDA_PCM_TYPE_SPDIF; 6623 if (spec->dig_out) { 6624 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 6625 ca0132_pcm_digital_playback; 6626 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 6627 } 6628 if (spec->dig_in) { 6629 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 6630 ca0132_pcm_digital_capture; 6631 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 6632 } 6633 6634 return 0; 6635 } 6636 6637 static int dbpro_build_pcms(struct hda_codec *codec) 6638 { 6639 struct ca0132_spec *spec = codec->spec; 6640 struct hda_pcm *info; 6641 6642 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog"); 6643 if (!info) 6644 return -ENOMEM; 6645 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 6646 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 6647 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 6648 6649 6650 if (!spec->dig_out && !spec->dig_in) 6651 return 0; 6652 6653 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 6654 if (!info) 6655 return -ENOMEM; 6656 info->pcm_type = HDA_PCM_TYPE_SPDIF; 6657 if (spec->dig_out) { 6658 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 6659 ca0132_pcm_digital_playback; 6660 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 6661 } 6662 if (spec->dig_in) { 6663 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 6664 ca0132_pcm_digital_capture; 6665 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 6666 } 6667 6668 return 0; 6669 } 6670 6671 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac) 6672 { 6673 if (pin) { 6674 snd_hda_set_pin_ctl(codec, pin, PIN_HP); 6675 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 6676 snd_hda_codec_write(codec, pin, 0, 6677 AC_VERB_SET_AMP_GAIN_MUTE, 6678 AMP_OUT_UNMUTE); 6679 } 6680 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP)) 6681 snd_hda_codec_write(codec, dac, 0, 6682 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO); 6683 } 6684 6685 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc) 6686 { 6687 if (pin) { 6688 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80); 6689 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP) 6690 snd_hda_codec_write(codec, pin, 0, 6691 AC_VERB_SET_AMP_GAIN_MUTE, 6692 AMP_IN_UNMUTE(0)); 6693 } 6694 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) { 6695 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE, 6696 AMP_IN_UNMUTE(0)); 6697 6698 /* init to 0 dB and unmute. */ 6699 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 6700 HDA_AMP_VOLMASK, 0x5a); 6701 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 6702 HDA_AMP_MUTE, 0); 6703 } 6704 } 6705 6706 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir) 6707 { 6708 unsigned int caps; 6709 6710 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ? 6711 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP); 6712 snd_hda_override_amp_caps(codec, nid, dir, caps); 6713 } 6714 6715 /* 6716 * Switch between Digital built-in mic and analog mic. 6717 */ 6718 static void ca0132_set_dmic(struct hda_codec *codec, int enable) 6719 { 6720 struct ca0132_spec *spec = codec->spec; 6721 unsigned int tmp; 6722 u8 val; 6723 unsigned int oldval; 6724 6725 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable); 6726 6727 oldval = stop_mic1(codec); 6728 ca0132_set_vipsource(codec, 0); 6729 if (enable) { 6730 /* set DMic input as 2-ch */ 6731 tmp = FLOAT_TWO; 6732 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 6733 6734 val = spec->dmic_ctl; 6735 val |= 0x80; 6736 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6737 VENDOR_CHIPIO_DMIC_CTL_SET, val); 6738 6739 if (!(spec->dmic_ctl & 0x20)) 6740 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1); 6741 } else { 6742 /* set AMic input as mono */ 6743 tmp = FLOAT_ONE; 6744 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 6745 6746 val = spec->dmic_ctl; 6747 /* clear bit7 and bit5 to disable dmic */ 6748 val &= 0x5f; 6749 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6750 VENDOR_CHIPIO_DMIC_CTL_SET, val); 6751 6752 if (!(spec->dmic_ctl & 0x20)) 6753 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0); 6754 } 6755 ca0132_set_vipsource(codec, 1); 6756 resume_mic1(codec, oldval); 6757 } 6758 6759 /* 6760 * Initialization for Digital Mic. 6761 */ 6762 static void ca0132_init_dmic(struct hda_codec *codec) 6763 { 6764 struct ca0132_spec *spec = codec->spec; 6765 u8 val; 6766 6767 /* Setup Digital Mic here, but don't enable. 6768 * Enable based on jack detect. 6769 */ 6770 6771 /* MCLK uses MPIO1, set to enable. 6772 * Bit 2-0: MPIO select 6773 * Bit 3: set to disable 6774 * Bit 7-4: reserved 6775 */ 6776 val = 0x01; 6777 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6778 VENDOR_CHIPIO_DMIC_MCLK_SET, val); 6779 6780 /* Data1 uses MPIO3. Data2 not use 6781 * Bit 2-0: Data1 MPIO select 6782 * Bit 3: set disable Data1 6783 * Bit 6-4: Data2 MPIO select 6784 * Bit 7: set disable Data2 6785 */ 6786 val = 0x83; 6787 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6788 VENDOR_CHIPIO_DMIC_PIN_SET, val); 6789 6790 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first. 6791 * Bit 3-0: Channel mask 6792 * Bit 4: set for 48KHz, clear for 32KHz 6793 * Bit 5: mode 6794 * Bit 6: set to select Data2, clear for Data1 6795 * Bit 7: set to enable DMic, clear for AMic 6796 */ 6797 if (spec->quirk == QUIRK_ALIENWARE_M17XR4) 6798 val = 0x33; 6799 else 6800 val = 0x23; 6801 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */ 6802 spec->dmic_ctl = val; 6803 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6804 VENDOR_CHIPIO_DMIC_CTL_SET, val); 6805 } 6806 6807 /* 6808 * Initialization for Analog Mic 2 6809 */ 6810 static void ca0132_init_analog_mic2(struct hda_codec *codec) 6811 { 6812 struct ca0132_spec *spec = codec->spec; 6813 6814 mutex_lock(&spec->chipio_mutex); 6815 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6816 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); 6817 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6818 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 6819 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6820 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 6821 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6822 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D); 6823 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6824 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 6825 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6826 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 6827 mutex_unlock(&spec->chipio_mutex); 6828 } 6829 6830 static void ca0132_refresh_widget_caps(struct hda_codec *codec) 6831 { 6832 struct ca0132_spec *spec = codec->spec; 6833 int i; 6834 6835 codec_dbg(codec, "ca0132_refresh_widget_caps.\n"); 6836 snd_hda_codec_update_widgets(codec); 6837 6838 for (i = 0; i < spec->multiout.num_dacs; i++) 6839 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT); 6840 6841 for (i = 0; i < spec->num_outputs; i++) 6842 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT); 6843 6844 for (i = 0; i < spec->num_inputs; i++) { 6845 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT); 6846 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT); 6847 } 6848 } 6849 6850 /* 6851 * Creates a dummy stream to bind the output to. This seems to have to be done 6852 * after changing the main outputs source and destination streams. 6853 */ 6854 static void ca0132_alt_create_dummy_stream(struct hda_codec *codec) 6855 { 6856 struct ca0132_spec *spec = codec->spec; 6857 unsigned int stream_format; 6858 6859 stream_format = snd_hdac_calc_stream_format(48000, 2, 6860 SNDRV_PCM_FORMAT_S32_LE, 32, 0); 6861 6862 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id, 6863 0, stream_format); 6864 6865 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 6866 } 6867 6868 /* 6869 * Initialize mic for non-chromebook ca0132 implementations. 6870 */ 6871 static void ca0132_alt_init_analog_mics(struct hda_codec *codec) 6872 { 6873 struct ca0132_spec *spec = codec->spec; 6874 unsigned int tmp; 6875 6876 /* Mic 1 Setup */ 6877 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 6878 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 6879 if (spec->quirk == QUIRK_R3DI) { 6880 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 6881 tmp = FLOAT_ONE; 6882 } else 6883 tmp = FLOAT_THREE; 6884 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 6885 6886 /* Mic 2 setup (not present on desktop cards) */ 6887 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000); 6888 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000); 6889 if (spec->quirk == QUIRK_R3DI) 6890 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 6891 tmp = FLOAT_ZERO; 6892 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 6893 } 6894 6895 /* 6896 * Sets the source of stream 0x14 to connpointID 0x48, and the destination 6897 * connpointID to 0x91. If this isn't done, the destination is 0x71, and 6898 * you get no sound. I'm guessing this has to do with the Sound Blaster Z 6899 * having an updated DAC, which changes the destination to that DAC. 6900 */ 6901 static void sbz_connect_streams(struct hda_codec *codec) 6902 { 6903 struct ca0132_spec *spec = codec->spec; 6904 6905 mutex_lock(&spec->chipio_mutex); 6906 6907 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n"); 6908 6909 chipio_set_stream_channels(codec, 0x0C, 6); 6910 chipio_set_stream_control(codec, 0x0C, 1); 6911 6912 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */ 6913 chipio_write_no_mutex(codec, 0x18a020, 0x00000043); 6914 6915 /* Setup stream 0x14 with it's source and destination points */ 6916 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91); 6917 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000); 6918 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000); 6919 chipio_set_stream_channels(codec, 0x14, 2); 6920 chipio_set_stream_control(codec, 0x14, 1); 6921 6922 codec_dbg(codec, "Connect Streams exited, mutex released.\n"); 6923 6924 mutex_unlock(&spec->chipio_mutex); 6925 } 6926 6927 /* 6928 * Write data through ChipIO to setup proper stream destinations. 6929 * Not sure how it exactly works, but it seems to direct data 6930 * to different destinations. Example is f8 to c0, e0 to c0. 6931 * All I know is, if you don't set these, you get no sound. 6932 */ 6933 static void sbz_chipio_startup_data(struct hda_codec *codec) 6934 { 6935 struct ca0132_spec *spec = codec->spec; 6936 6937 mutex_lock(&spec->chipio_mutex); 6938 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n"); 6939 6940 /* These control audio output */ 6941 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0); 6942 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1); 6943 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6); 6944 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7); 6945 /* Signal to update I think */ 6946 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 6947 6948 chipio_set_stream_channels(codec, 0x0C, 6); 6949 chipio_set_stream_control(codec, 0x0C, 1); 6950 /* No clue what these control */ 6951 if (spec->quirk == QUIRK_SBZ) { 6952 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0); 6953 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1); 6954 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2); 6955 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3); 6956 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4); 6957 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5); 6958 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6); 6959 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7); 6960 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8); 6961 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9); 6962 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca); 6963 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb); 6964 } else if (spec->quirk == QUIRK_ZXR) { 6965 chipio_write_no_mutex(codec, 0x190038, 0x000140c2); 6966 chipio_write_no_mutex(codec, 0x19003c, 0x000141c3); 6967 chipio_write_no_mutex(codec, 0x190040, 0x000150c4); 6968 chipio_write_no_mutex(codec, 0x190044, 0x000151c5); 6969 chipio_write_no_mutex(codec, 0x190050, 0x000142c8); 6970 chipio_write_no_mutex(codec, 0x190054, 0x000143c9); 6971 chipio_write_no_mutex(codec, 0x190058, 0x000152ca); 6972 chipio_write_no_mutex(codec, 0x19005c, 0x000153cb); 6973 } 6974 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 6975 6976 codec_dbg(codec, "Startup Data exited, mutex released.\n"); 6977 mutex_unlock(&spec->chipio_mutex); 6978 } 6979 6980 /* 6981 * Custom DSP SCP commands where the src value is 0x00 instead of 0x20. This is 6982 * done after the DSP is loaded. 6983 */ 6984 static void ca0132_alt_dsp_scp_startup(struct hda_codec *codec) 6985 { 6986 struct ca0132_spec *spec = codec->spec; 6987 unsigned int tmp, i; 6988 6989 /* 6990 * Gotta run these twice, or else mic works inconsistently. Not clear 6991 * why this is, but multiple tests have confirmed it. 6992 */ 6993 for (i = 0; i < 2; i++) { 6994 switch (spec->quirk) { 6995 case QUIRK_SBZ: 6996 case QUIRK_AE5: 6997 tmp = 0x00000003; 6998 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 6999 tmp = 0x00000000; 7000 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp); 7001 tmp = 0x00000001; 7002 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp); 7003 tmp = 0x00000004; 7004 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7005 tmp = 0x00000005; 7006 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7007 tmp = 0x00000000; 7008 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7009 break; 7010 case QUIRK_R3D: 7011 case QUIRK_R3DI: 7012 tmp = 0x00000000; 7013 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp); 7014 tmp = 0x00000001; 7015 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp); 7016 tmp = 0x00000004; 7017 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7018 tmp = 0x00000005; 7019 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7020 tmp = 0x00000000; 7021 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7022 break; 7023 } 7024 msleep(100); 7025 } 7026 } 7027 7028 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec) 7029 { 7030 struct ca0132_spec *spec = codec->spec; 7031 unsigned int tmp; 7032 7033 chipio_set_stream_control(codec, 0x03, 0); 7034 chipio_set_stream_control(codec, 0x04, 0); 7035 7036 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7037 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7038 7039 tmp = FLOAT_THREE; 7040 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7041 7042 chipio_set_stream_control(codec, 0x03, 1); 7043 chipio_set_stream_control(codec, 0x04, 1); 7044 7045 switch (spec->quirk) { 7046 case QUIRK_SBZ: 7047 chipio_write(codec, 0x18b098, 0x0000000c); 7048 chipio_write(codec, 0x18b09C, 0x0000000c); 7049 break; 7050 case QUIRK_AE5: 7051 chipio_write(codec, 0x18b098, 0x0000000c); 7052 chipio_write(codec, 0x18b09c, 0x0000004c); 7053 break; 7054 } 7055 } 7056 7057 static void ae5_post_dsp_register_set(struct hda_codec *codec) 7058 { 7059 struct ca0132_spec *spec = codec->spec; 7060 7061 chipio_8051_write_direct(codec, 0x93, 0x10); 7062 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7063 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44); 7064 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7065 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2); 7066 7067 writeb(0xff, spec->mem_base + 0x304); 7068 writeb(0xff, spec->mem_base + 0x304); 7069 writeb(0xff, spec->mem_base + 0x304); 7070 writeb(0xff, spec->mem_base + 0x304); 7071 writeb(0x00, spec->mem_base + 0x100); 7072 writeb(0xff, spec->mem_base + 0x304); 7073 writeb(0x00, spec->mem_base + 0x100); 7074 writeb(0xff, spec->mem_base + 0x304); 7075 writeb(0x00, spec->mem_base + 0x100); 7076 writeb(0xff, spec->mem_base + 0x304); 7077 writeb(0x00, spec->mem_base + 0x100); 7078 writeb(0xff, spec->mem_base + 0x304); 7079 7080 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f); 7081 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 7082 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7083 } 7084 7085 static void ae5_post_dsp_param_setup(struct hda_codec *codec) 7086 { 7087 /* 7088 * Param3 in the 8051's memory is represented by the ascii string 'mch' 7089 * which seems to be 'multichannel'. This is also mentioned in the 7090 * AE-5's registry values in Windows. 7091 */ 7092 chipio_set_control_param(codec, 3, 0); 7093 /* 7094 * I believe ASI is 'audio serial interface' and that it's used to 7095 * change colors on the external LED strip connected to the AE-5. 7096 */ 7097 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); 7098 7099 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); 7100 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 7101 7102 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7103 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92); 7104 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7105 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa); 7106 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7107 VENDOR_CHIPIO_8051_DATA_WRITE, 0x22); 7108 } 7109 7110 static void ae5_post_dsp_pll_setup(struct hda_codec *codec) 7111 { 7112 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7113 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41); 7114 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7115 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8); 7116 7117 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7118 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x45); 7119 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7120 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcc); 7121 7122 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7123 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x40); 7124 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7125 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcb); 7126 7127 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7128 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43); 7129 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7130 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7); 7131 7132 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7133 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x51); 7134 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7135 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x8d); 7136 } 7137 7138 static void ae5_post_dsp_stream_setup(struct hda_codec *codec) 7139 { 7140 struct ca0132_spec *spec = codec->spec; 7141 7142 mutex_lock(&spec->chipio_mutex); 7143 7144 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); 7145 7146 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); 7147 7148 chipio_set_stream_channels(codec, 0x0C, 6); 7149 chipio_set_stream_control(codec, 0x0C, 1); 7150 7151 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0); 7152 7153 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0); 7154 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 7155 chipio_set_stream_channels(codec, 0x18, 6); 7156 chipio_set_stream_control(codec, 0x18, 1); 7157 7158 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); 7159 7160 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7161 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43); 7162 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7163 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7); 7164 7165 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80); 7166 7167 mutex_unlock(&spec->chipio_mutex); 7168 } 7169 7170 static void ae5_post_dsp_startup_data(struct hda_codec *codec) 7171 { 7172 struct ca0132_spec *spec = codec->spec; 7173 7174 mutex_lock(&spec->chipio_mutex); 7175 7176 chipio_write_no_mutex(codec, 0x189000, 0x0001f101); 7177 chipio_write_no_mutex(codec, 0x189004, 0x0001f101); 7178 chipio_write_no_mutex(codec, 0x189024, 0x00014004); 7179 chipio_write_no_mutex(codec, 0x189028, 0x0002000f); 7180 7181 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 7182 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 7183 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12); 7184 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00); 7185 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48); 7186 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 7187 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7188 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 7189 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 7190 ca0113_mmio_gpio_set(codec, 0, true); 7191 ca0113_mmio_gpio_set(codec, 1, true); 7192 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80); 7193 7194 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012); 7195 7196 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 7197 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 7198 7199 mutex_unlock(&spec->chipio_mutex); 7200 } 7201 7202 /* 7203 * Setup default parameters for DSP 7204 */ 7205 static void ca0132_setup_defaults(struct hda_codec *codec) 7206 { 7207 struct ca0132_spec *spec = codec->spec; 7208 unsigned int tmp; 7209 int num_fx; 7210 int idx, i; 7211 7212 if (spec->dsp_state != DSP_DOWNLOADED) 7213 return; 7214 7215 /* out, in effects + voicefx */ 7216 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 7217 for (idx = 0; idx < num_fx; idx++) { 7218 for (i = 0; i <= ca0132_effects[idx].params; i++) { 7219 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 7220 ca0132_effects[idx].reqs[i], 7221 ca0132_effects[idx].def_vals[i]); 7222 } 7223 } 7224 7225 /*remove DSP headroom*/ 7226 tmp = FLOAT_ZERO; 7227 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 7228 7229 /*set speaker EQ bypass attenuation*/ 7230 dspio_set_uint_param(codec, 0x8f, 0x01, tmp); 7231 7232 /* set AMic1 and AMic2 as mono mic */ 7233 tmp = FLOAT_ONE; 7234 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7235 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 7236 7237 /* set AMic1 as CrystalVoice input */ 7238 tmp = FLOAT_ONE; 7239 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 7240 7241 /* set WUH source */ 7242 tmp = FLOAT_TWO; 7243 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 7244 } 7245 7246 /* 7247 * Setup default parameters for Recon3D/Recon3Di DSP. 7248 */ 7249 7250 static void r3d_setup_defaults(struct hda_codec *codec) 7251 { 7252 struct ca0132_spec *spec = codec->spec; 7253 unsigned int tmp; 7254 int num_fx; 7255 int idx, i; 7256 7257 if (spec->dsp_state != DSP_DOWNLOADED) 7258 return; 7259 7260 ca0132_alt_dsp_scp_startup(codec); 7261 ca0132_alt_init_analog_mics(codec); 7262 7263 /*remove DSP headroom*/ 7264 tmp = FLOAT_ZERO; 7265 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 7266 7267 /* set WUH source */ 7268 tmp = FLOAT_TWO; 7269 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 7270 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7271 7272 /* Set speaker source? */ 7273 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 7274 7275 if (spec->quirk == QUIRK_R3DI) 7276 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED); 7277 7278 /* Setup effect defaults */ 7279 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 7280 for (idx = 0; idx < num_fx; idx++) { 7281 for (i = 0; i <= ca0132_effects[idx].params; i++) { 7282 dspio_set_uint_param(codec, 7283 ca0132_effects[idx].mid, 7284 ca0132_effects[idx].reqs[i], 7285 ca0132_effects[idx].def_vals[i]); 7286 } 7287 } 7288 } 7289 7290 /* 7291 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on 7292 * than the Chromebook setup. 7293 */ 7294 static void sbz_setup_defaults(struct hda_codec *codec) 7295 { 7296 struct ca0132_spec *spec = codec->spec; 7297 unsigned int tmp; 7298 int num_fx; 7299 int idx, i; 7300 7301 if (spec->dsp_state != DSP_DOWNLOADED) 7302 return; 7303 7304 ca0132_alt_dsp_scp_startup(codec); 7305 ca0132_alt_init_analog_mics(codec); 7306 sbz_connect_streams(codec); 7307 sbz_chipio_startup_data(codec); 7308 7309 chipio_set_stream_control(codec, 0x03, 1); 7310 chipio_set_stream_control(codec, 0x04, 1); 7311 7312 /* 7313 * Sets internal input loopback to off, used to have a switch to 7314 * enable input loopback, but turned out to be way too buggy. 7315 */ 7316 tmp = FLOAT_ONE; 7317 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 7318 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 7319 7320 /*remove DSP headroom*/ 7321 tmp = FLOAT_ZERO; 7322 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 7323 7324 /* set WUH source */ 7325 tmp = FLOAT_TWO; 7326 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 7327 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7328 7329 /* Set speaker source? */ 7330 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 7331 7332 ca0132_alt_dsp_initial_mic_setup(codec); 7333 7334 /* out, in effects + voicefx */ 7335 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 7336 for (idx = 0; idx < num_fx; idx++) { 7337 for (i = 0; i <= ca0132_effects[idx].params; i++) { 7338 dspio_set_uint_param(codec, 7339 ca0132_effects[idx].mid, 7340 ca0132_effects[idx].reqs[i], 7341 ca0132_effects[idx].def_vals[i]); 7342 } 7343 } 7344 7345 ca0132_alt_create_dummy_stream(codec); 7346 } 7347 7348 /* 7349 * Setup default parameters for the Sound BlasterX AE-5 DSP. 7350 */ 7351 static void ae5_setup_defaults(struct hda_codec *codec) 7352 { 7353 struct ca0132_spec *spec = codec->spec; 7354 unsigned int tmp; 7355 int num_fx; 7356 int idx, i; 7357 7358 if (spec->dsp_state != DSP_DOWNLOADED) 7359 return; 7360 7361 ca0132_alt_dsp_scp_startup(codec); 7362 ca0132_alt_init_analog_mics(codec); 7363 chipio_set_stream_control(codec, 0x03, 1); 7364 chipio_set_stream_control(codec, 0x04, 1); 7365 7366 /* New, unknown SCP req's */ 7367 tmp = FLOAT_ZERO; 7368 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 7369 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 7370 dspio_set_uint_param(codec, 0x80, 0x0d, tmp); 7371 dspio_set_uint_param(codec, 0x80, 0x0e, tmp); 7372 7373 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 7374 ca0113_mmio_gpio_set(codec, 0, false); 7375 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 7376 7377 /* Internal loopback off */ 7378 tmp = FLOAT_ONE; 7379 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 7380 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 7381 7382 /*remove DSP headroom*/ 7383 tmp = FLOAT_ZERO; 7384 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 7385 7386 /* set WUH source */ 7387 tmp = FLOAT_TWO; 7388 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 7389 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7390 7391 /* Set speaker source? */ 7392 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 7393 7394 ca0132_alt_dsp_initial_mic_setup(codec); 7395 ae5_post_dsp_register_set(codec); 7396 ae5_post_dsp_param_setup(codec); 7397 ae5_post_dsp_pll_setup(codec); 7398 ae5_post_dsp_stream_setup(codec); 7399 ae5_post_dsp_startup_data(codec); 7400 7401 /* out, in effects + voicefx */ 7402 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 7403 for (idx = 0; idx < num_fx; idx++) { 7404 for (i = 0; i <= ca0132_effects[idx].params; i++) { 7405 dspio_set_uint_param(codec, 7406 ca0132_effects[idx].mid, 7407 ca0132_effects[idx].reqs[i], 7408 ca0132_effects[idx].def_vals[i]); 7409 } 7410 } 7411 7412 ca0132_alt_create_dummy_stream(codec); 7413 } 7414 7415 /* 7416 * Initialization of flags in chip 7417 */ 7418 static void ca0132_init_flags(struct hda_codec *codec) 7419 { 7420 struct ca0132_spec *spec = codec->spec; 7421 7422 if (spec->use_alt_functions) { 7423 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1); 7424 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1); 7425 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1); 7426 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1); 7427 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1); 7428 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 7429 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0); 7430 chipio_set_control_flag(codec, 7431 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 7432 chipio_set_control_flag(codec, 7433 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1); 7434 } else { 7435 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 7436 chipio_set_control_flag(codec, 7437 CONTROL_FLAG_PORT_A_COMMON_MODE, 0); 7438 chipio_set_control_flag(codec, 7439 CONTROL_FLAG_PORT_D_COMMON_MODE, 0); 7440 chipio_set_control_flag(codec, 7441 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0); 7442 chipio_set_control_flag(codec, 7443 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 7444 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1); 7445 } 7446 } 7447 7448 /* 7449 * Initialization of parameters in chip 7450 */ 7451 static void ca0132_init_params(struct hda_codec *codec) 7452 { 7453 struct ca0132_spec *spec = codec->spec; 7454 7455 if (spec->use_alt_functions) { 7456 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7457 chipio_set_conn_rate(codec, 0x0B, SR_48_000); 7458 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0); 7459 chipio_set_control_param(codec, 0, 0); 7460 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 7461 } 7462 7463 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6); 7464 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6); 7465 } 7466 7467 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k) 7468 { 7469 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k); 7470 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k); 7471 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k); 7472 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k); 7473 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k); 7474 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k); 7475 7476 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7477 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7478 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7479 } 7480 7481 static bool ca0132_download_dsp_images(struct hda_codec *codec) 7482 { 7483 bool dsp_loaded = false; 7484 struct ca0132_spec *spec = codec->spec; 7485 const struct dsp_image_seg *dsp_os_image; 7486 const struct firmware *fw_entry; 7487 /* 7488 * Alternate firmwares for different variants. The Recon3Di apparently 7489 * can use the default firmware, but I'll leave the option in case 7490 * it needs it again. 7491 */ 7492 switch (spec->quirk) { 7493 case QUIRK_SBZ: 7494 case QUIRK_R3D: 7495 case QUIRK_AE5: 7496 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE, 7497 codec->card->dev) != 0) { 7498 codec_dbg(codec, "Desktop firmware not found."); 7499 spec->alt_firmware_present = false; 7500 } else { 7501 codec_dbg(codec, "Desktop firmware selected."); 7502 spec->alt_firmware_present = true; 7503 } 7504 break; 7505 case QUIRK_R3DI: 7506 if (request_firmware(&fw_entry, R3DI_EFX_FILE, 7507 codec->card->dev) != 0) { 7508 codec_dbg(codec, "Recon3Di alt firmware not detected."); 7509 spec->alt_firmware_present = false; 7510 } else { 7511 codec_dbg(codec, "Recon3Di firmware selected."); 7512 spec->alt_firmware_present = true; 7513 } 7514 break; 7515 default: 7516 spec->alt_firmware_present = false; 7517 break; 7518 } 7519 /* 7520 * Use default ctefx.bin if no alt firmware is detected, or if none 7521 * exists for your particular codec. 7522 */ 7523 if (!spec->alt_firmware_present) { 7524 codec_dbg(codec, "Default firmware selected."); 7525 if (request_firmware(&fw_entry, EFX_FILE, 7526 codec->card->dev) != 0) 7527 return false; 7528 } 7529 7530 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data); 7531 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) { 7532 codec_err(codec, "ca0132 DSP load image failed\n"); 7533 goto exit_download; 7534 } 7535 7536 dsp_loaded = dspload_wait_loaded(codec); 7537 7538 exit_download: 7539 release_firmware(fw_entry); 7540 7541 return dsp_loaded; 7542 } 7543 7544 static void ca0132_download_dsp(struct hda_codec *codec) 7545 { 7546 struct ca0132_spec *spec = codec->spec; 7547 7548 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP 7549 return; /* NOP */ 7550 #endif 7551 7552 if (spec->dsp_state == DSP_DOWNLOAD_FAILED) 7553 return; /* don't retry failures */ 7554 7555 chipio_enable_clocks(codec); 7556 if (spec->dsp_state != DSP_DOWNLOADED) { 7557 spec->dsp_state = DSP_DOWNLOADING; 7558 7559 if (!ca0132_download_dsp_images(codec)) 7560 spec->dsp_state = DSP_DOWNLOAD_FAILED; 7561 else 7562 spec->dsp_state = DSP_DOWNLOADED; 7563 } 7564 7565 /* For codecs using alt functions, this is already done earlier */ 7566 if (spec->dsp_state == DSP_DOWNLOADED && (!spec->use_alt_functions)) 7567 ca0132_set_dsp_msr(codec, true); 7568 } 7569 7570 static void ca0132_process_dsp_response(struct hda_codec *codec, 7571 struct hda_jack_callback *callback) 7572 { 7573 struct ca0132_spec *spec = codec->spec; 7574 7575 codec_dbg(codec, "ca0132_process_dsp_response\n"); 7576 if (spec->wait_scp) { 7577 if (dspio_get_response_data(codec) >= 0) 7578 spec->wait_scp = 0; 7579 } 7580 7581 dspio_clear_response_queue(codec); 7582 } 7583 7584 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 7585 { 7586 struct ca0132_spec *spec = codec->spec; 7587 struct hda_jack_tbl *tbl; 7588 7589 /* Delay enabling the HP amp, to let the mic-detection 7590 * state machine run. 7591 */ 7592 cancel_delayed_work_sync(&spec->unsol_hp_work); 7593 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500)); 7594 tbl = snd_hda_jack_tbl_get(codec, cb->nid); 7595 if (tbl) 7596 tbl->block_report = 1; 7597 } 7598 7599 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 7600 { 7601 struct ca0132_spec *spec = codec->spec; 7602 7603 if (spec->use_alt_functions) 7604 ca0132_alt_select_in(codec); 7605 else 7606 ca0132_select_mic(codec); 7607 } 7608 7609 static void ca0132_init_unsol(struct hda_codec *codec) 7610 { 7611 struct ca0132_spec *spec = codec->spec; 7612 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback); 7613 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1, 7614 amic_callback); 7615 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP, 7616 ca0132_process_dsp_response); 7617 /* Front headphone jack detection */ 7618 if (spec->use_alt_functions) 7619 snd_hda_jack_detect_enable_callback(codec, 7620 spec->unsol_tag_front_hp, hp_callback); 7621 } 7622 7623 /* 7624 * Verbs tables. 7625 */ 7626 7627 /* Sends before DSP download. */ 7628 static struct hda_verb ca0132_base_init_verbs[] = { 7629 /*enable ct extension*/ 7630 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1}, 7631 {} 7632 }; 7633 7634 /* Send at exit. */ 7635 static struct hda_verb ca0132_base_exit_verbs[] = { 7636 /*set afg to D3*/ 7637 {0x01, AC_VERB_SET_POWER_STATE, 0x03}, 7638 /*disable ct extension*/ 7639 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0}, 7640 {} 7641 }; 7642 7643 /* Other verbs tables. Sends after DSP download. */ 7644 7645 static struct hda_verb ca0132_init_verbs0[] = { 7646 /* chip init verbs */ 7647 {0x15, 0x70D, 0xF0}, 7648 {0x15, 0x70E, 0xFE}, 7649 {0x15, 0x707, 0x75}, 7650 {0x15, 0x707, 0xD3}, 7651 {0x15, 0x707, 0x09}, 7652 {0x15, 0x707, 0x53}, 7653 {0x15, 0x707, 0xD4}, 7654 {0x15, 0x707, 0xEF}, 7655 {0x15, 0x707, 0x75}, 7656 {0x15, 0x707, 0xD3}, 7657 {0x15, 0x707, 0x09}, 7658 {0x15, 0x707, 0x02}, 7659 {0x15, 0x707, 0x37}, 7660 {0x15, 0x707, 0x78}, 7661 {0x15, 0x53C, 0xCE}, 7662 {0x15, 0x575, 0xC9}, 7663 {0x15, 0x53D, 0xCE}, 7664 {0x15, 0x5B7, 0xC9}, 7665 {0x15, 0x70D, 0xE8}, 7666 {0x15, 0x70E, 0xFE}, 7667 {0x15, 0x707, 0x02}, 7668 {0x15, 0x707, 0x68}, 7669 {0x15, 0x707, 0x62}, 7670 {0x15, 0x53A, 0xCE}, 7671 {0x15, 0x546, 0xC9}, 7672 {0x15, 0x53B, 0xCE}, 7673 {0x15, 0x5E8, 0xC9}, 7674 {} 7675 }; 7676 7677 /* Extra init verbs for desktop cards. */ 7678 static struct hda_verb ca0132_init_verbs1[] = { 7679 {0x15, 0x70D, 0x20}, 7680 {0x15, 0x70E, 0x19}, 7681 {0x15, 0x707, 0x00}, 7682 {0x15, 0x539, 0xCE}, 7683 {0x15, 0x546, 0xC9}, 7684 {0x15, 0x70D, 0xB7}, 7685 {0x15, 0x70E, 0x09}, 7686 {0x15, 0x707, 0x10}, 7687 {0x15, 0x70D, 0xAF}, 7688 {0x15, 0x70E, 0x09}, 7689 {0x15, 0x707, 0x01}, 7690 {0x15, 0x707, 0x05}, 7691 {0x15, 0x70D, 0x73}, 7692 {0x15, 0x70E, 0x09}, 7693 {0x15, 0x707, 0x14}, 7694 {0x15, 0x6FF, 0xC4}, 7695 {} 7696 }; 7697 7698 static void ca0132_init_chip(struct hda_codec *codec) 7699 { 7700 struct ca0132_spec *spec = codec->spec; 7701 int num_fx; 7702 int i; 7703 unsigned int on; 7704 7705 mutex_init(&spec->chipio_mutex); 7706 7707 spec->cur_out_type = SPEAKER_OUT; 7708 if (!spec->use_alt_functions) 7709 spec->cur_mic_type = DIGITAL_MIC; 7710 else 7711 spec->cur_mic_type = REAR_MIC; 7712 7713 spec->cur_mic_boost = 0; 7714 7715 for (i = 0; i < VNODES_COUNT; i++) { 7716 spec->vnode_lvol[i] = 0x5a; 7717 spec->vnode_rvol[i] = 0x5a; 7718 spec->vnode_lswitch[i] = 0; 7719 spec->vnode_rswitch[i] = 0; 7720 } 7721 7722 /* 7723 * Default states for effects are in ca0132_effects[]. 7724 */ 7725 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 7726 for (i = 0; i < num_fx; i++) { 7727 on = (unsigned int)ca0132_effects[i].reqs[0]; 7728 spec->effects_switch[i] = on ? 1 : 0; 7729 } 7730 /* 7731 * Sets defaults for the effect slider controls, only for alternative 7732 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz. 7733 */ 7734 if (spec->use_alt_controls) { 7735 spec->xbass_xover_freq = 8; 7736 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++) 7737 spec->fx_ctl_val[i] = effect_slider_defaults[i]; 7738 } 7739 7740 spec->voicefx_val = 0; 7741 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1; 7742 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0; 7743 7744 /* 7745 * The ZxR doesn't have a front panel header, and it's line-in is on 7746 * the daughter board. So, there is no input enum control, and we need 7747 * to make sure that spec->in_enum_val is set properly. 7748 */ 7749 if (spec->quirk == QUIRK_ZXR) 7750 spec->in_enum_val = REAR_MIC; 7751 7752 #ifdef ENABLE_TUNING_CONTROLS 7753 ca0132_init_tuning_defaults(codec); 7754 #endif 7755 } 7756 7757 /* 7758 * Recon3Di exit specific commands. 7759 */ 7760 /* prevents popping noise on shutdown */ 7761 static void r3di_gpio_shutdown(struct hda_codec *codec) 7762 { 7763 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00); 7764 } 7765 7766 /* 7767 * Sound Blaster Z exit specific commands. 7768 */ 7769 static void sbz_region2_exit(struct hda_codec *codec) 7770 { 7771 struct ca0132_spec *spec = codec->spec; 7772 unsigned int i; 7773 7774 for (i = 0; i < 4; i++) 7775 writeb(0x0, spec->mem_base + 0x100); 7776 for (i = 0; i < 8; i++) 7777 writeb(0xb3, spec->mem_base + 0x304); 7778 7779 ca0113_mmio_gpio_set(codec, 0, false); 7780 ca0113_mmio_gpio_set(codec, 1, false); 7781 ca0113_mmio_gpio_set(codec, 4, true); 7782 ca0113_mmio_gpio_set(codec, 5, false); 7783 ca0113_mmio_gpio_set(codec, 7, false); 7784 } 7785 7786 static void sbz_set_pin_ctl_default(struct hda_codec *codec) 7787 { 7788 hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13}; 7789 unsigned int i; 7790 7791 snd_hda_codec_write(codec, 0x11, 0, 7792 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40); 7793 7794 for (i = 0; i < 5; i++) 7795 snd_hda_codec_write(codec, pins[i], 0, 7796 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00); 7797 } 7798 7799 static void ca0132_clear_unsolicited(struct hda_codec *codec) 7800 { 7801 hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13}; 7802 unsigned int i; 7803 7804 for (i = 0; i < 7; i++) { 7805 snd_hda_codec_write(codec, pins[i], 0, 7806 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00); 7807 } 7808 } 7809 7810 /* On shutdown, sends commands in sets of three */ 7811 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir, 7812 int mask, int data) 7813 { 7814 if (dir >= 0) 7815 snd_hda_codec_write(codec, 0x01, 0, 7816 AC_VERB_SET_GPIO_DIRECTION, dir); 7817 if (mask >= 0) 7818 snd_hda_codec_write(codec, 0x01, 0, 7819 AC_VERB_SET_GPIO_MASK, mask); 7820 7821 if (data >= 0) 7822 snd_hda_codec_write(codec, 0x01, 0, 7823 AC_VERB_SET_GPIO_DATA, data); 7824 } 7825 7826 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec) 7827 { 7828 hda_nid_t pins[7] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01}; 7829 unsigned int i; 7830 7831 for (i = 0; i < 7; i++) 7832 snd_hda_codec_write(codec, pins[i], 0, 7833 AC_VERB_SET_POWER_STATE, 0x03); 7834 } 7835 7836 static void sbz_exit_chip(struct hda_codec *codec) 7837 { 7838 chipio_set_stream_control(codec, 0x03, 0); 7839 chipio_set_stream_control(codec, 0x04, 0); 7840 7841 /* Mess with GPIO */ 7842 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1); 7843 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05); 7844 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01); 7845 7846 chipio_set_stream_control(codec, 0x14, 0); 7847 chipio_set_stream_control(codec, 0x0C, 0); 7848 7849 chipio_set_conn_rate(codec, 0x41, SR_192_000); 7850 chipio_set_conn_rate(codec, 0x91, SR_192_000); 7851 7852 chipio_write(codec, 0x18a020, 0x00000083); 7853 7854 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03); 7855 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07); 7856 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06); 7857 7858 chipio_set_stream_control(codec, 0x0C, 0); 7859 7860 chipio_set_control_param(codec, 0x0D, 0x24); 7861 7862 ca0132_clear_unsolicited(codec); 7863 sbz_set_pin_ctl_default(codec); 7864 7865 snd_hda_codec_write(codec, 0x0B, 0, 7866 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 7867 7868 sbz_region2_exit(codec); 7869 } 7870 7871 static void r3d_exit_chip(struct hda_codec *codec) 7872 { 7873 ca0132_clear_unsolicited(codec); 7874 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 7875 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b); 7876 } 7877 7878 static void ae5_exit_chip(struct hda_codec *codec) 7879 { 7880 chipio_set_stream_control(codec, 0x03, 0); 7881 chipio_set_stream_control(codec, 0x04, 0); 7882 7883 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 7884 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7885 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7886 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 7887 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 7888 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00); 7889 ca0113_mmio_gpio_set(codec, 0, false); 7890 ca0113_mmio_gpio_set(codec, 1, false); 7891 7892 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 7893 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 7894 7895 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 7896 7897 chipio_set_stream_control(codec, 0x18, 0); 7898 chipio_set_stream_control(codec, 0x0c, 0); 7899 7900 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83); 7901 } 7902 7903 static void zxr_exit_chip(struct hda_codec *codec) 7904 { 7905 chipio_set_stream_control(codec, 0x03, 0); 7906 chipio_set_stream_control(codec, 0x04, 0); 7907 chipio_set_stream_control(codec, 0x14, 0); 7908 chipio_set_stream_control(codec, 0x0C, 0); 7909 7910 chipio_set_conn_rate(codec, 0x41, SR_192_000); 7911 chipio_set_conn_rate(codec, 0x91, SR_192_000); 7912 7913 chipio_write(codec, 0x18a020, 0x00000083); 7914 7915 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 7916 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 7917 7918 ca0132_clear_unsolicited(codec); 7919 sbz_set_pin_ctl_default(codec); 7920 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00); 7921 7922 ca0113_mmio_gpio_set(codec, 5, false); 7923 ca0113_mmio_gpio_set(codec, 2, false); 7924 ca0113_mmio_gpio_set(codec, 3, false); 7925 ca0113_mmio_gpio_set(codec, 0, false); 7926 ca0113_mmio_gpio_set(codec, 4, true); 7927 ca0113_mmio_gpio_set(codec, 0, true); 7928 ca0113_mmio_gpio_set(codec, 5, true); 7929 ca0113_mmio_gpio_set(codec, 2, false); 7930 ca0113_mmio_gpio_set(codec, 3, false); 7931 } 7932 7933 static void ca0132_exit_chip(struct hda_codec *codec) 7934 { 7935 /* put any chip cleanup stuffs here. */ 7936 7937 if (dspload_is_loaded(codec)) 7938 dsp_reset(codec); 7939 } 7940 7941 /* 7942 * This fixes a problem that was hard to reproduce. Very rarely, I would 7943 * boot up, and there would be no sound, but the DSP indicated it had loaded 7944 * properly. I did a few memory dumps to see if anything was different, and 7945 * there were a few areas of memory uninitialized with a1a2a3a4. This function 7946 * checks if those areas are uninitialized, and if they are, it'll attempt to 7947 * reload the card 3 times. Usually it fixes by the second. 7948 */ 7949 static void sbz_dsp_startup_check(struct hda_codec *codec) 7950 { 7951 struct ca0132_spec *spec = codec->spec; 7952 unsigned int dsp_data_check[4]; 7953 unsigned int cur_address = 0x390; 7954 unsigned int i; 7955 unsigned int failure = 0; 7956 unsigned int reload = 3; 7957 7958 if (spec->startup_check_entered) 7959 return; 7960 7961 spec->startup_check_entered = true; 7962 7963 for (i = 0; i < 4; i++) { 7964 chipio_read(codec, cur_address, &dsp_data_check[i]); 7965 cur_address += 0x4; 7966 } 7967 for (i = 0; i < 4; i++) { 7968 if (dsp_data_check[i] == 0xa1a2a3a4) 7969 failure = 1; 7970 } 7971 7972 codec_dbg(codec, "Startup Check: %d ", failure); 7973 if (failure) 7974 codec_info(codec, "DSP not initialized properly. Attempting to fix."); 7975 /* 7976 * While the failure condition is true, and we haven't reached our 7977 * three reload limit, continue trying to reload the driver and 7978 * fix the issue. 7979 */ 7980 while (failure && (reload != 0)) { 7981 codec_info(codec, "Reloading... Tries left: %d", reload); 7982 sbz_exit_chip(codec); 7983 spec->dsp_state = DSP_DOWNLOAD_INIT; 7984 codec->patch_ops.init(codec); 7985 failure = 0; 7986 for (i = 0; i < 4; i++) { 7987 chipio_read(codec, cur_address, &dsp_data_check[i]); 7988 cur_address += 0x4; 7989 } 7990 for (i = 0; i < 4; i++) { 7991 if (dsp_data_check[i] == 0xa1a2a3a4) 7992 failure = 1; 7993 } 7994 reload--; 7995 } 7996 7997 if (!failure && reload < 3) 7998 codec_info(codec, "DSP fixed."); 7999 8000 if (!failure) 8001 return; 8002 8003 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory."); 8004 } 8005 8006 /* 8007 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add 8008 * extra precision for decibel values. If you had the dB value in floating point 8009 * you would take the value after the decimal point, multiply by 64, and divide 8010 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to 8011 * implement fixed point or floating point dB volumes. For now, I'll set them 8012 * to 0 just incase a value has lingered from a boot into Windows. 8013 */ 8014 static void ca0132_alt_vol_setup(struct hda_codec *codec) 8015 { 8016 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00); 8017 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00); 8018 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00); 8019 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00); 8020 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00); 8021 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00); 8022 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00); 8023 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00); 8024 } 8025 8026 /* 8027 * Extra commands that don't really fit anywhere else. 8028 */ 8029 static void sbz_pre_dsp_setup(struct hda_codec *codec) 8030 { 8031 struct ca0132_spec *spec = codec->spec; 8032 8033 writel(0x00820680, spec->mem_base + 0x01C); 8034 writel(0x00820680, spec->mem_base + 0x01C); 8035 8036 chipio_write(codec, 0x18b0a4, 0x000000c2); 8037 8038 snd_hda_codec_write(codec, 0x11, 0, 8039 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 8040 } 8041 8042 static void r3d_pre_dsp_setup(struct hda_codec *codec) 8043 { 8044 chipio_write(codec, 0x18b0a4, 0x000000c2); 8045 8046 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8047 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E); 8048 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8049 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C); 8050 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8051 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B); 8052 8053 snd_hda_codec_write(codec, 0x11, 0, 8054 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 8055 } 8056 8057 static void r3di_pre_dsp_setup(struct hda_codec *codec) 8058 { 8059 chipio_write(codec, 0x18b0a4, 0x000000c2); 8060 8061 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8062 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E); 8063 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8064 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C); 8065 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8066 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B); 8067 8068 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8069 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); 8070 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8071 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 8072 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8073 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 8074 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8075 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40); 8076 8077 snd_hda_codec_write(codec, 0x11, 0, 8078 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04); 8079 } 8080 8081 /* 8082 * These are sent before the DSP is downloaded. Not sure 8083 * what they do, or if they're necessary. Could possibly 8084 * be removed. Figure they're better to leave in. 8085 */ 8086 static void ca0132_mmio_init(struct hda_codec *codec) 8087 { 8088 struct ca0132_spec *spec = codec->spec; 8089 8090 if (spec->quirk == QUIRK_AE5) 8091 writel(0x00000001, spec->mem_base + 0x400); 8092 else 8093 writel(0x00000000, spec->mem_base + 0x400); 8094 8095 if (spec->quirk == QUIRK_AE5) 8096 writel(0x00000001, spec->mem_base + 0x408); 8097 else 8098 writel(0x00000000, spec->mem_base + 0x408); 8099 8100 if (spec->quirk == QUIRK_AE5) 8101 writel(0x00000001, spec->mem_base + 0x40c); 8102 else 8103 writel(0x00000000, spec->mem_base + 0x40C); 8104 8105 if (spec->quirk == QUIRK_ZXR) 8106 writel(0x00880640, spec->mem_base + 0x01C); 8107 else 8108 writel(0x00880680, spec->mem_base + 0x01C); 8109 8110 if (spec->quirk == QUIRK_AE5) 8111 writel(0x00000080, spec->mem_base + 0xC0C); 8112 else 8113 writel(0x00000083, spec->mem_base + 0xC0C); 8114 8115 writel(0x00000030, spec->mem_base + 0xC00); 8116 writel(0x00000000, spec->mem_base + 0xC04); 8117 8118 if (spec->quirk == QUIRK_AE5) 8119 writel(0x00000000, spec->mem_base + 0xC0C); 8120 else 8121 writel(0x00000003, spec->mem_base + 0xC0C); 8122 8123 writel(0x00000003, spec->mem_base + 0xC0C); 8124 writel(0x00000003, spec->mem_base + 0xC0C); 8125 writel(0x00000003, spec->mem_base + 0xC0C); 8126 8127 if (spec->quirk == QUIRK_AE5) 8128 writel(0x00000001, spec->mem_base + 0xC08); 8129 else 8130 writel(0x000000C1, spec->mem_base + 0xC08); 8131 8132 writel(0x000000F1, spec->mem_base + 0xC08); 8133 writel(0x00000001, spec->mem_base + 0xC08); 8134 writel(0x000000C7, spec->mem_base + 0xC08); 8135 writel(0x000000C1, spec->mem_base + 0xC08); 8136 writel(0x00000080, spec->mem_base + 0xC04); 8137 8138 if (spec->quirk == QUIRK_AE5) { 8139 writel(0x00000000, spec->mem_base + 0x42c); 8140 writel(0x00000000, spec->mem_base + 0x46c); 8141 writel(0x00000000, spec->mem_base + 0x4ac); 8142 writel(0x00000000, spec->mem_base + 0x4ec); 8143 writel(0x00000000, spec->mem_base + 0x43c); 8144 writel(0x00000000, spec->mem_base + 0x47c); 8145 writel(0x00000000, spec->mem_base + 0x4bc); 8146 writel(0x00000000, spec->mem_base + 0x4fc); 8147 writel(0x00000600, spec->mem_base + 0x100); 8148 writel(0x00000014, spec->mem_base + 0x410); 8149 writel(0x0000060f, spec->mem_base + 0x100); 8150 writel(0x0000070f, spec->mem_base + 0x100); 8151 writel(0x00000aff, spec->mem_base + 0x830); 8152 writel(0x00000000, spec->mem_base + 0x86c); 8153 writel(0x0000006b, spec->mem_base + 0x800); 8154 writel(0x00000001, spec->mem_base + 0x86c); 8155 writel(0x0000006b, spec->mem_base + 0x800); 8156 writel(0x00000057, spec->mem_base + 0x804); 8157 writel(0x00800000, spec->mem_base + 0x20c); 8158 } 8159 } 8160 8161 /* 8162 * This function writes to some SFR's, does some region2 writes, and then 8163 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does 8164 * what it does. 8165 */ 8166 static void ae5_register_set(struct hda_codec *codec) 8167 { 8168 struct ca0132_spec *spec = codec->spec; 8169 8170 chipio_8051_write_direct(codec, 0x93, 0x10); 8171 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8172 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44); 8173 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8174 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2); 8175 8176 writeb(0x0f, spec->mem_base + 0x304); 8177 writeb(0x0f, spec->mem_base + 0x304); 8178 writeb(0x0f, spec->mem_base + 0x304); 8179 writeb(0x0f, spec->mem_base + 0x304); 8180 writeb(0x0e, spec->mem_base + 0x100); 8181 writeb(0x1f, spec->mem_base + 0x304); 8182 writeb(0x0c, spec->mem_base + 0x100); 8183 writeb(0x3f, spec->mem_base + 0x304); 8184 writeb(0x08, spec->mem_base + 0x100); 8185 writeb(0x7f, spec->mem_base + 0x304); 8186 writeb(0x00, spec->mem_base + 0x100); 8187 writeb(0xff, spec->mem_base + 0x304); 8188 8189 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 8190 8191 chipio_8051_write_direct(codec, 0x90, 0x00); 8192 chipio_8051_write_direct(codec, 0x90, 0x10); 8193 8194 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8195 8196 chipio_write(codec, 0x18b0a4, 0x000000c2); 8197 8198 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00); 8199 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00); 8200 } 8201 8202 /* 8203 * Extra init functions for alternative ca0132 codecs. Done 8204 * here so they don't clutter up the main ca0132_init function 8205 * anymore than they have to. 8206 */ 8207 static void ca0132_alt_init(struct hda_codec *codec) 8208 { 8209 struct ca0132_spec *spec = codec->spec; 8210 8211 ca0132_alt_vol_setup(codec); 8212 8213 switch (spec->quirk) { 8214 case QUIRK_SBZ: 8215 codec_dbg(codec, "SBZ alt_init"); 8216 ca0132_gpio_init(codec); 8217 sbz_pre_dsp_setup(codec); 8218 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8219 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 8220 break; 8221 case QUIRK_R3DI: 8222 codec_dbg(codec, "R3DI alt_init"); 8223 ca0132_gpio_init(codec); 8224 ca0132_gpio_setup(codec); 8225 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING); 8226 r3di_pre_dsp_setup(codec); 8227 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8228 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4); 8229 break; 8230 case QUIRK_R3D: 8231 r3d_pre_dsp_setup(codec); 8232 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8233 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 8234 break; 8235 case QUIRK_AE5: 8236 ca0132_gpio_init(codec); 8237 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8238 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49); 8239 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8240 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88); 8241 chipio_write(codec, 0x18b030, 0x00000020); 8242 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8243 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 8244 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 8245 break; 8246 case QUIRK_ZXR: 8247 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8248 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 8249 break; 8250 } 8251 } 8252 8253 static int ca0132_init(struct hda_codec *codec) 8254 { 8255 struct ca0132_spec *spec = codec->spec; 8256 struct auto_pin_cfg *cfg = &spec->autocfg; 8257 int i; 8258 bool dsp_loaded; 8259 8260 /* 8261 * If the DSP is already downloaded, and init has been entered again, 8262 * there's only two reasons for it. One, the codec has awaken from a 8263 * suspended state, and in that case dspload_is_loaded will return 8264 * false, and the init will be ran again. The other reason it gets 8265 * re entered is on startup for some reason it triggers a suspend and 8266 * resume state. In this case, it will check if the DSP is downloaded, 8267 * and not run the init function again. For codecs using alt_functions, 8268 * it will check if the DSP is loaded properly. 8269 */ 8270 if (spec->dsp_state == DSP_DOWNLOADED) { 8271 dsp_loaded = dspload_is_loaded(codec); 8272 if (!dsp_loaded) { 8273 spec->dsp_reload = true; 8274 spec->dsp_state = DSP_DOWNLOAD_INIT; 8275 } else { 8276 if (spec->quirk == QUIRK_SBZ) 8277 sbz_dsp_startup_check(codec); 8278 return 0; 8279 } 8280 } 8281 8282 if (spec->dsp_state != DSP_DOWNLOAD_FAILED) 8283 spec->dsp_state = DSP_DOWNLOAD_INIT; 8284 spec->curr_chip_addx = INVALID_CHIP_ADDRESS; 8285 8286 if (spec->use_pci_mmio) 8287 ca0132_mmio_init(codec); 8288 8289 snd_hda_power_up_pm(codec); 8290 8291 if (spec->quirk == QUIRK_AE5) 8292 ae5_register_set(codec); 8293 8294 ca0132_init_unsol(codec); 8295 ca0132_init_params(codec); 8296 ca0132_init_flags(codec); 8297 8298 snd_hda_sequence_write(codec, spec->base_init_verbs); 8299 8300 if (spec->use_alt_functions) 8301 ca0132_alt_init(codec); 8302 8303 ca0132_download_dsp(codec); 8304 8305 ca0132_refresh_widget_caps(codec); 8306 8307 switch (spec->quirk) { 8308 case QUIRK_R3DI: 8309 case QUIRK_R3D: 8310 r3d_setup_defaults(codec); 8311 break; 8312 case QUIRK_SBZ: 8313 case QUIRK_ZXR: 8314 sbz_setup_defaults(codec); 8315 break; 8316 case QUIRK_AE5: 8317 ae5_setup_defaults(codec); 8318 break; 8319 default: 8320 ca0132_setup_defaults(codec); 8321 ca0132_init_analog_mic2(codec); 8322 ca0132_init_dmic(codec); 8323 break; 8324 } 8325 8326 for (i = 0; i < spec->num_outputs; i++) 8327 init_output(codec, spec->out_pins[i], spec->dacs[0]); 8328 8329 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 8330 8331 for (i = 0; i < spec->num_inputs; i++) 8332 init_input(codec, spec->input_pins[i], spec->adcs[i]); 8333 8334 init_input(codec, cfg->dig_in_pin, spec->dig_in); 8335 8336 if (!spec->use_alt_functions) { 8337 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8338 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8339 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D); 8340 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8341 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20); 8342 } 8343 8344 if (spec->quirk == QUIRK_SBZ) 8345 ca0132_gpio_setup(codec); 8346 8347 snd_hda_sequence_write(codec, spec->spec_init_verbs); 8348 if (spec->use_alt_functions) { 8349 ca0132_alt_select_out(codec); 8350 ca0132_alt_select_in(codec); 8351 } else { 8352 ca0132_select_out(codec); 8353 ca0132_select_mic(codec); 8354 } 8355 8356 snd_hda_jack_report_sync(codec); 8357 8358 /* 8359 * Re set the PlayEnhancement switch on a resume event, because the 8360 * controls will not be reloaded. 8361 */ 8362 if (spec->dsp_reload) { 8363 spec->dsp_reload = false; 8364 ca0132_pe_switch_set(codec); 8365 } 8366 8367 snd_hda_power_down_pm(codec); 8368 8369 return 0; 8370 } 8371 8372 static int dbpro_init(struct hda_codec *codec) 8373 { 8374 struct ca0132_spec *spec = codec->spec; 8375 struct auto_pin_cfg *cfg = &spec->autocfg; 8376 unsigned int i; 8377 8378 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 8379 init_input(codec, cfg->dig_in_pin, spec->dig_in); 8380 8381 for (i = 0; i < spec->num_inputs; i++) 8382 init_input(codec, spec->input_pins[i], spec->adcs[i]); 8383 8384 return 0; 8385 } 8386 8387 static void ca0132_free(struct hda_codec *codec) 8388 { 8389 struct ca0132_spec *spec = codec->spec; 8390 8391 cancel_delayed_work_sync(&spec->unsol_hp_work); 8392 snd_hda_power_up(codec); 8393 switch (spec->quirk) { 8394 case QUIRK_SBZ: 8395 sbz_exit_chip(codec); 8396 break; 8397 case QUIRK_ZXR: 8398 zxr_exit_chip(codec); 8399 break; 8400 case QUIRK_R3D: 8401 r3d_exit_chip(codec); 8402 break; 8403 case QUIRK_AE5: 8404 ae5_exit_chip(codec); 8405 break; 8406 case QUIRK_R3DI: 8407 r3di_gpio_shutdown(codec); 8408 break; 8409 } 8410 8411 snd_hda_sequence_write(codec, spec->base_exit_verbs); 8412 ca0132_exit_chip(codec); 8413 8414 snd_hda_power_down(codec); 8415 if (spec->mem_base) 8416 iounmap(spec->mem_base); 8417 kfree(spec->spec_init_verbs); 8418 kfree(codec->spec); 8419 } 8420 8421 static void dbpro_free(struct hda_codec *codec) 8422 { 8423 struct ca0132_spec *spec = codec->spec; 8424 8425 zxr_dbpro_power_state_shutdown(codec); 8426 8427 kfree(spec->spec_init_verbs); 8428 kfree(codec->spec); 8429 } 8430 8431 static void ca0132_reboot_notify(struct hda_codec *codec) 8432 { 8433 codec->patch_ops.free(codec); 8434 } 8435 8436 static const struct hda_codec_ops ca0132_patch_ops = { 8437 .build_controls = ca0132_build_controls, 8438 .build_pcms = ca0132_build_pcms, 8439 .init = ca0132_init, 8440 .free = ca0132_free, 8441 .unsol_event = snd_hda_jack_unsol_event, 8442 .reboot_notify = ca0132_reboot_notify, 8443 }; 8444 8445 static const struct hda_codec_ops dbpro_patch_ops = { 8446 .build_controls = dbpro_build_controls, 8447 .build_pcms = dbpro_build_pcms, 8448 .init = dbpro_init, 8449 .free = dbpro_free, 8450 }; 8451 8452 static void ca0132_config(struct hda_codec *codec) 8453 { 8454 struct ca0132_spec *spec = codec->spec; 8455 8456 spec->dacs[0] = 0x2; 8457 spec->dacs[1] = 0x3; 8458 spec->dacs[2] = 0x4; 8459 8460 spec->multiout.dac_nids = spec->dacs; 8461 spec->multiout.num_dacs = 3; 8462 8463 if (!spec->use_alt_functions) 8464 spec->multiout.max_channels = 2; 8465 else 8466 spec->multiout.max_channels = 6; 8467 8468 switch (spec->quirk) { 8469 case QUIRK_ALIENWARE: 8470 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__); 8471 snd_hda_apply_pincfgs(codec, alienware_pincfgs); 8472 break; 8473 case QUIRK_SBZ: 8474 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__); 8475 snd_hda_apply_pincfgs(codec, sbz_pincfgs); 8476 break; 8477 case QUIRK_ZXR: 8478 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__); 8479 snd_hda_apply_pincfgs(codec, zxr_pincfgs); 8480 break; 8481 case QUIRK_R3D: 8482 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__); 8483 snd_hda_apply_pincfgs(codec, r3d_pincfgs); 8484 break; 8485 case QUIRK_R3DI: 8486 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__); 8487 snd_hda_apply_pincfgs(codec, r3di_pincfgs); 8488 break; 8489 case QUIRK_AE5: 8490 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__); 8491 snd_hda_apply_pincfgs(codec, r3di_pincfgs); 8492 break; 8493 } 8494 8495 switch (spec->quirk) { 8496 case QUIRK_ALIENWARE: 8497 spec->num_outputs = 2; 8498 spec->out_pins[0] = 0x0b; /* speaker out */ 8499 spec->out_pins[1] = 0x0f; 8500 spec->shared_out_nid = 0x2; 8501 spec->unsol_tag_hp = 0x0f; 8502 8503 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 8504 spec->adcs[1] = 0x8; /* analog mic2 */ 8505 spec->adcs[2] = 0xa; /* what u hear */ 8506 8507 spec->num_inputs = 3; 8508 spec->input_pins[0] = 0x12; 8509 spec->input_pins[1] = 0x11; 8510 spec->input_pins[2] = 0x13; 8511 spec->shared_mic_nid = 0x7; 8512 spec->unsol_tag_amic1 = 0x11; 8513 break; 8514 case QUIRK_SBZ: 8515 case QUIRK_R3D: 8516 spec->num_outputs = 2; 8517 spec->out_pins[0] = 0x0B; /* Line out */ 8518 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 8519 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 8520 spec->out_pins[3] = 0x11; /* Rear surround */ 8521 spec->shared_out_nid = 0x2; 8522 spec->unsol_tag_hp = spec->out_pins[1]; 8523 spec->unsol_tag_front_hp = spec->out_pins[2]; 8524 8525 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 8526 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 8527 spec->adcs[2] = 0xa; /* what u hear */ 8528 8529 spec->num_inputs = 2; 8530 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 8531 spec->input_pins[1] = 0x13; /* What U Hear */ 8532 spec->shared_mic_nid = 0x7; 8533 spec->unsol_tag_amic1 = spec->input_pins[0]; 8534 8535 /* SPDIF I/O */ 8536 spec->dig_out = 0x05; 8537 spec->multiout.dig_out_nid = spec->dig_out; 8538 spec->dig_in = 0x09; 8539 break; 8540 case QUIRK_ZXR: 8541 spec->num_outputs = 2; 8542 spec->out_pins[0] = 0x0B; /* Line out */ 8543 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 8544 spec->out_pins[2] = 0x10; /* Center/LFE */ 8545 spec->out_pins[3] = 0x11; /* Rear surround */ 8546 spec->shared_out_nid = 0x2; 8547 spec->unsol_tag_hp = spec->out_pins[1]; 8548 spec->unsol_tag_front_hp = spec->out_pins[2]; 8549 8550 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 8551 spec->adcs[1] = 0x8; /* Not connected, no front mic */ 8552 spec->adcs[2] = 0xa; /* what u hear */ 8553 8554 spec->num_inputs = 2; 8555 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 8556 spec->input_pins[1] = 0x13; /* What U Hear */ 8557 spec->shared_mic_nid = 0x7; 8558 spec->unsol_tag_amic1 = spec->input_pins[0]; 8559 break; 8560 case QUIRK_ZXR_DBPRO: 8561 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */ 8562 8563 spec->num_inputs = 1; 8564 spec->input_pins[0] = 0x11; /* RCA Line-in */ 8565 8566 spec->dig_out = 0x05; 8567 spec->multiout.dig_out_nid = spec->dig_out; 8568 8569 spec->dig_in = 0x09; 8570 break; 8571 case QUIRK_AE5: 8572 spec->num_outputs = 2; 8573 spec->out_pins[0] = 0x0B; /* Line out */ 8574 spec->out_pins[1] = 0x11; /* Rear headphone out */ 8575 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 8576 spec->out_pins[3] = 0x0F; /* Rear surround */ 8577 spec->shared_out_nid = 0x2; 8578 spec->unsol_tag_hp = spec->out_pins[1]; 8579 spec->unsol_tag_front_hp = spec->out_pins[2]; 8580 8581 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 8582 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 8583 spec->adcs[2] = 0xa; /* what u hear */ 8584 8585 spec->num_inputs = 2; 8586 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 8587 spec->input_pins[1] = 0x13; /* What U Hear */ 8588 spec->shared_mic_nid = 0x7; 8589 spec->unsol_tag_amic1 = spec->input_pins[0]; 8590 8591 /* SPDIF I/O */ 8592 spec->dig_out = 0x05; 8593 spec->multiout.dig_out_nid = spec->dig_out; 8594 break; 8595 case QUIRK_R3DI: 8596 spec->num_outputs = 2; 8597 spec->out_pins[0] = 0x0B; /* Line out */ 8598 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 8599 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 8600 spec->out_pins[3] = 0x11; /* Rear surround */ 8601 spec->shared_out_nid = 0x2; 8602 spec->unsol_tag_hp = spec->out_pins[1]; 8603 spec->unsol_tag_front_hp = spec->out_pins[2]; 8604 8605 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */ 8606 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */ 8607 spec->adcs[2] = 0x0a; /* what u hear */ 8608 8609 spec->num_inputs = 2; 8610 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 8611 spec->input_pins[1] = 0x13; /* What U Hear */ 8612 spec->shared_mic_nid = 0x7; 8613 spec->unsol_tag_amic1 = spec->input_pins[0]; 8614 8615 /* SPDIF I/O */ 8616 spec->dig_out = 0x05; 8617 spec->multiout.dig_out_nid = spec->dig_out; 8618 break; 8619 default: 8620 spec->num_outputs = 2; 8621 spec->out_pins[0] = 0x0b; /* speaker out */ 8622 spec->out_pins[1] = 0x10; /* headphone out */ 8623 spec->shared_out_nid = 0x2; 8624 spec->unsol_tag_hp = spec->out_pins[1]; 8625 8626 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 8627 spec->adcs[1] = 0x8; /* analog mic2 */ 8628 spec->adcs[2] = 0xa; /* what u hear */ 8629 8630 spec->num_inputs = 3; 8631 spec->input_pins[0] = 0x12; 8632 spec->input_pins[1] = 0x11; 8633 spec->input_pins[2] = 0x13; 8634 spec->shared_mic_nid = 0x7; 8635 spec->unsol_tag_amic1 = spec->input_pins[0]; 8636 8637 /* SPDIF I/O */ 8638 spec->dig_out = 0x05; 8639 spec->multiout.dig_out_nid = spec->dig_out; 8640 spec->dig_in = 0x09; 8641 break; 8642 } 8643 } 8644 8645 static int ca0132_prepare_verbs(struct hda_codec *codec) 8646 { 8647 /* Verbs + terminator (an empty element) */ 8648 #define NUM_SPEC_VERBS 2 8649 struct ca0132_spec *spec = codec->spec; 8650 8651 spec->chip_init_verbs = ca0132_init_verbs0; 8652 /* 8653 * Since desktop cards use pci_mmio, this can be used to determine 8654 * whether or not to use these verbs instead of a separate bool. 8655 */ 8656 if (spec->use_pci_mmio) 8657 spec->desktop_init_verbs = ca0132_init_verbs1; 8658 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS, 8659 sizeof(struct hda_verb), 8660 GFP_KERNEL); 8661 if (!spec->spec_init_verbs) 8662 return -ENOMEM; 8663 8664 /* config EAPD */ 8665 spec->spec_init_verbs[0].nid = 0x0b; 8666 spec->spec_init_verbs[0].param = 0x78D; 8667 spec->spec_init_verbs[0].verb = 0x00; 8668 8669 /* Previously commented configuration */ 8670 /* 8671 spec->spec_init_verbs[2].nid = 0x0b; 8672 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE; 8673 spec->spec_init_verbs[2].verb = 0x02; 8674 8675 spec->spec_init_verbs[3].nid = 0x10; 8676 spec->spec_init_verbs[3].param = 0x78D; 8677 spec->spec_init_verbs[3].verb = 0x02; 8678 8679 spec->spec_init_verbs[4].nid = 0x10; 8680 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE; 8681 spec->spec_init_verbs[4].verb = 0x02; 8682 */ 8683 8684 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */ 8685 return 0; 8686 } 8687 8688 /* 8689 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular 8690 * Sound Blaster Z cards. However, they have different HDA codec subsystem 8691 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro 8692 * daughter boards ID. 8693 */ 8694 static void sbz_detect_quirk(struct hda_codec *codec) 8695 { 8696 struct ca0132_spec *spec = codec->spec; 8697 8698 switch (codec->core.subsystem_id) { 8699 case 0x11020033: 8700 spec->quirk = QUIRK_ZXR; 8701 break; 8702 case 0x1102003f: 8703 spec->quirk = QUIRK_ZXR_DBPRO; 8704 break; 8705 default: 8706 spec->quirk = QUIRK_SBZ; 8707 break; 8708 } 8709 } 8710 8711 static int patch_ca0132(struct hda_codec *codec) 8712 { 8713 struct ca0132_spec *spec; 8714 int err; 8715 const struct snd_pci_quirk *quirk; 8716 8717 codec_dbg(codec, "patch_ca0132\n"); 8718 8719 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 8720 if (!spec) 8721 return -ENOMEM; 8722 codec->spec = spec; 8723 spec->codec = codec; 8724 8725 /* Detect codec quirk */ 8726 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks); 8727 if (quirk) 8728 spec->quirk = quirk->value; 8729 else 8730 spec->quirk = QUIRK_NONE; 8731 8732 if (spec->quirk == QUIRK_SBZ) 8733 sbz_detect_quirk(codec); 8734 8735 if (spec->quirk == QUIRK_ZXR_DBPRO) 8736 codec->patch_ops = dbpro_patch_ops; 8737 else 8738 codec->patch_ops = ca0132_patch_ops; 8739 8740 codec->pcm_format_first = 1; 8741 codec->no_sticky_stream = 1; 8742 8743 8744 spec->dsp_state = DSP_DOWNLOAD_INIT; 8745 spec->num_mixers = 1; 8746 8747 /* Set which mixers each quirk uses. */ 8748 switch (spec->quirk) { 8749 case QUIRK_SBZ: 8750 spec->mixers[0] = desktop_mixer; 8751 snd_hda_codec_set_name(codec, "Sound Blaster Z"); 8752 break; 8753 case QUIRK_ZXR: 8754 spec->mixers[0] = desktop_mixer; 8755 snd_hda_codec_set_name(codec, "Sound Blaster ZxR"); 8756 break; 8757 case QUIRK_ZXR_DBPRO: 8758 break; 8759 case QUIRK_R3D: 8760 spec->mixers[0] = desktop_mixer; 8761 snd_hda_codec_set_name(codec, "Recon3D"); 8762 break; 8763 case QUIRK_R3DI: 8764 spec->mixers[0] = r3di_mixer; 8765 snd_hda_codec_set_name(codec, "Recon3Di"); 8766 break; 8767 case QUIRK_AE5: 8768 spec->mixers[0] = desktop_mixer; 8769 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5"); 8770 break; 8771 default: 8772 spec->mixers[0] = ca0132_mixer; 8773 break; 8774 } 8775 8776 /* Setup whether or not to use alt functions/controls/pci_mmio */ 8777 switch (spec->quirk) { 8778 case QUIRK_SBZ: 8779 case QUIRK_R3D: 8780 case QUIRK_AE5: 8781 case QUIRK_ZXR: 8782 spec->use_alt_controls = true; 8783 spec->use_alt_functions = true; 8784 spec->use_pci_mmio = true; 8785 break; 8786 case QUIRK_R3DI: 8787 spec->use_alt_controls = true; 8788 spec->use_alt_functions = true; 8789 spec->use_pci_mmio = false; 8790 break; 8791 default: 8792 spec->use_alt_controls = false; 8793 spec->use_alt_functions = false; 8794 spec->use_pci_mmio = false; 8795 break; 8796 } 8797 8798 if (spec->use_pci_mmio) { 8799 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20); 8800 if (spec->mem_base == NULL) { 8801 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE."); 8802 spec->quirk = QUIRK_NONE; 8803 } 8804 } 8805 8806 spec->base_init_verbs = ca0132_base_init_verbs; 8807 spec->base_exit_verbs = ca0132_base_exit_verbs; 8808 8809 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed); 8810 8811 ca0132_init_chip(codec); 8812 8813 ca0132_config(codec); 8814 8815 err = ca0132_prepare_verbs(codec); 8816 if (err < 0) 8817 goto error; 8818 8819 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL); 8820 if (err < 0) 8821 goto error; 8822 8823 return 0; 8824 8825 error: 8826 ca0132_free(codec); 8827 return err; 8828 } 8829 8830 /* 8831 * patch entries 8832 */ 8833 static struct hda_device_id snd_hda_id_ca0132[] = { 8834 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132), 8835 {} /* terminator */ 8836 }; 8837 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132); 8838 8839 MODULE_LICENSE("GPL"); 8840 MODULE_DESCRIPTION("Creative Sound Core3D codec"); 8841 8842 static struct hda_codec_driver ca0132_driver = { 8843 .id = snd_hda_id_ca0132, 8844 }; 8845 8846 module_hda_codec_driver(ca0132_driver); 8847