1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * HD audio interface patch for Creative CA0132 chip 4 * 5 * Copyright (c) 2011, Creative Technology Ltd. 6 * 7 * Based on patch_ca0110.c 8 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de> 9 */ 10 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/slab.h> 14 #include <linux/mutex.h> 15 #include <linux/module.h> 16 #include <linux/firmware.h> 17 #include <linux/kernel.h> 18 #include <linux/types.h> 19 #include <linux/io.h> 20 #include <linux/pci.h> 21 #include <asm/io.h> 22 #include <sound/core.h> 23 #include <sound/hda_codec.h> 24 #include "hda_local.h" 25 #include "hda_auto_parser.h" 26 #include "hda_jack.h" 27 28 #include "ca0132_regs.h" 29 30 /* Enable this to see controls for tuning purpose. */ 31 /*#define ENABLE_TUNING_CONTROLS*/ 32 33 #ifdef ENABLE_TUNING_CONTROLS 34 #include <sound/tlv.h> 35 #endif 36 37 #define FLOAT_ZERO 0x00000000 38 #define FLOAT_ONE 0x3f800000 39 #define FLOAT_TWO 0x40000000 40 #define FLOAT_THREE 0x40400000 41 #define FLOAT_EIGHT 0x41000000 42 #define FLOAT_MINUS_5 0xc0a00000 43 44 #define UNSOL_TAG_DSP 0x16 45 46 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18) 47 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15) 48 49 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8 50 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32 51 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2 52 53 #define MASTERCONTROL 0x80 54 #define MASTERCONTROL_ALLOC_DMA_CHAN 10 55 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60 56 57 #define WIDGET_CHIP_CTRL 0x15 58 #define WIDGET_DSP_CTRL 0x16 59 60 #define MEM_CONNID_MICIN1 3 61 #define MEM_CONNID_MICIN2 5 62 #define MEM_CONNID_MICOUT1 12 63 #define MEM_CONNID_MICOUT2 14 64 #define MEM_CONNID_WUH 10 65 #define MEM_CONNID_DSP 16 66 #define MEM_CONNID_DMIC 100 67 68 #define SCP_SET 0 69 #define SCP_GET 1 70 71 #define EFX_FILE "ctefx.bin" 72 #define DESKTOP_EFX_FILE "ctefx-desktop.bin" 73 #define R3DI_EFX_FILE "ctefx-r3di.bin" 74 75 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 76 MODULE_FIRMWARE(EFX_FILE); 77 MODULE_FIRMWARE(DESKTOP_EFX_FILE); 78 MODULE_FIRMWARE(R3DI_EFX_FILE); 79 #endif 80 81 static const char *const dirstr[2] = { "Playback", "Capture" }; 82 83 #define NUM_OF_OUTPUTS 3 84 enum { 85 SPEAKER_OUT, 86 HEADPHONE_OUT, 87 SURROUND_OUT 88 }; 89 90 enum { 91 DIGITAL_MIC, 92 LINE_MIC_IN 93 }; 94 95 /* Strings for Input Source Enum Control */ 96 static const char *const in_src_str[3] = {"Rear Mic", "Line", "Front Mic" }; 97 #define IN_SRC_NUM_OF_INPUTS 3 98 enum { 99 REAR_MIC, 100 REAR_LINE_IN, 101 FRONT_MIC, 102 }; 103 104 enum { 105 #define VNODE_START_NID 0x80 106 VNID_SPK = VNODE_START_NID, /* Speaker vnid */ 107 VNID_MIC, 108 VNID_HP_SEL, 109 VNID_AMIC1_SEL, 110 VNID_HP_ASEL, 111 VNID_AMIC1_ASEL, 112 VNODE_END_NID, 113 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID) 114 115 #define EFFECT_START_NID 0x90 116 #define OUT_EFFECT_START_NID EFFECT_START_NID 117 SURROUND = OUT_EFFECT_START_NID, 118 CRYSTALIZER, 119 DIALOG_PLUS, 120 SMART_VOLUME, 121 X_BASS, 122 EQUALIZER, 123 OUT_EFFECT_END_NID, 124 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID) 125 126 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID 127 ECHO_CANCELLATION = IN_EFFECT_START_NID, 128 VOICE_FOCUS, 129 MIC_SVM, 130 NOISE_REDUCTION, 131 IN_EFFECT_END_NID, 132 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID) 133 134 VOICEFX = IN_EFFECT_END_NID, 135 PLAY_ENHANCEMENT, 136 CRYSTAL_VOICE, 137 EFFECT_END_NID, 138 OUTPUT_SOURCE_ENUM, 139 INPUT_SOURCE_ENUM, 140 XBASS_XOVER, 141 EQ_PRESET_ENUM, 142 SMART_VOLUME_ENUM, 143 MIC_BOOST_ENUM, 144 AE5_HEADPHONE_GAIN_ENUM, 145 AE5_SOUND_FILTER_ENUM, 146 ZXR_HEADPHONE_GAIN 147 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID) 148 }; 149 150 /* Effects values size*/ 151 #define EFFECT_VALS_MAX_COUNT 12 152 153 /* 154 * Default values for the effect slider controls, they are in order of their 155 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then 156 * X-bass. 157 */ 158 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50}; 159 /* Amount of effect level sliders for ca0132_alt controls. */ 160 #define EFFECT_LEVEL_SLIDERS 5 161 162 /* Latency introduced by DSP blocks in milliseconds. */ 163 #define DSP_CAPTURE_INIT_LATENCY 0 164 #define DSP_CRYSTAL_VOICE_LATENCY 124 165 #define DSP_PLAYBACK_INIT_LATENCY 13 166 #define DSP_PLAY_ENHANCEMENT_LATENCY 30 167 #define DSP_SPEAKER_OUT_LATENCY 7 168 169 struct ct_effect { 170 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 171 hda_nid_t nid; 172 int mid; /*effect module ID*/ 173 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/ 174 int direct; /* 0:output; 1:input*/ 175 int params; /* number of default non-on/off params */ 176 /*effect default values, 1st is on/off. */ 177 unsigned int def_vals[EFFECT_VALS_MAX_COUNT]; 178 }; 179 180 #define EFX_DIR_OUT 0 181 #define EFX_DIR_IN 1 182 183 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = { 184 { .name = "Surround", 185 .nid = SURROUND, 186 .mid = 0x96, 187 .reqs = {0, 1}, 188 .direct = EFX_DIR_OUT, 189 .params = 1, 190 .def_vals = {0x3F800000, 0x3F2B851F} 191 }, 192 { .name = "Crystalizer", 193 .nid = CRYSTALIZER, 194 .mid = 0x96, 195 .reqs = {7, 8}, 196 .direct = EFX_DIR_OUT, 197 .params = 1, 198 .def_vals = {0x3F800000, 0x3F266666} 199 }, 200 { .name = "Dialog Plus", 201 .nid = DIALOG_PLUS, 202 .mid = 0x96, 203 .reqs = {2, 3}, 204 .direct = EFX_DIR_OUT, 205 .params = 1, 206 .def_vals = {0x00000000, 0x3F000000} 207 }, 208 { .name = "Smart Volume", 209 .nid = SMART_VOLUME, 210 .mid = 0x96, 211 .reqs = {4, 5, 6}, 212 .direct = EFX_DIR_OUT, 213 .params = 2, 214 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000} 215 }, 216 { .name = "X-Bass", 217 .nid = X_BASS, 218 .mid = 0x96, 219 .reqs = {24, 23, 25}, 220 .direct = EFX_DIR_OUT, 221 .params = 2, 222 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000} 223 }, 224 { .name = "Equalizer", 225 .nid = EQUALIZER, 226 .mid = 0x96, 227 .reqs = {9, 10, 11, 12, 13, 14, 228 15, 16, 17, 18, 19, 20}, 229 .direct = EFX_DIR_OUT, 230 .params = 11, 231 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000, 232 0x00000000, 0x00000000, 0x00000000, 0x00000000, 233 0x00000000, 0x00000000, 0x00000000, 0x00000000} 234 }, 235 { .name = "Echo Cancellation", 236 .nid = ECHO_CANCELLATION, 237 .mid = 0x95, 238 .reqs = {0, 1, 2, 3}, 239 .direct = EFX_DIR_IN, 240 .params = 3, 241 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000} 242 }, 243 { .name = "Voice Focus", 244 .nid = VOICE_FOCUS, 245 .mid = 0x95, 246 .reqs = {6, 7, 8, 9}, 247 .direct = EFX_DIR_IN, 248 .params = 3, 249 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000} 250 }, 251 { .name = "Mic SVM", 252 .nid = MIC_SVM, 253 .mid = 0x95, 254 .reqs = {44, 45}, 255 .direct = EFX_DIR_IN, 256 .params = 1, 257 .def_vals = {0x00000000, 0x3F3D70A4} 258 }, 259 { .name = "Noise Reduction", 260 .nid = NOISE_REDUCTION, 261 .mid = 0x95, 262 .reqs = {4, 5}, 263 .direct = EFX_DIR_IN, 264 .params = 1, 265 .def_vals = {0x3F800000, 0x3F000000} 266 }, 267 { .name = "VoiceFX", 268 .nid = VOICEFX, 269 .mid = 0x95, 270 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}, 271 .direct = EFX_DIR_IN, 272 .params = 8, 273 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000, 274 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000, 275 0x00000000} 276 } 277 }; 278 279 /* Tuning controls */ 280 #ifdef ENABLE_TUNING_CONTROLS 281 282 enum { 283 #define TUNING_CTL_START_NID 0xC0 284 WEDGE_ANGLE = TUNING_CTL_START_NID, 285 SVM_LEVEL, 286 EQUALIZER_BAND_0, 287 EQUALIZER_BAND_1, 288 EQUALIZER_BAND_2, 289 EQUALIZER_BAND_3, 290 EQUALIZER_BAND_4, 291 EQUALIZER_BAND_5, 292 EQUALIZER_BAND_6, 293 EQUALIZER_BAND_7, 294 EQUALIZER_BAND_8, 295 EQUALIZER_BAND_9, 296 TUNING_CTL_END_NID 297 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID) 298 }; 299 300 struct ct_tuning_ctl { 301 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 302 hda_nid_t parent_nid; 303 hda_nid_t nid; 304 int mid; /*effect module ID*/ 305 int req; /*effect module request*/ 306 int direct; /* 0:output; 1:input*/ 307 unsigned int def_val;/*effect default values*/ 308 }; 309 310 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = { 311 { .name = "Wedge Angle", 312 .parent_nid = VOICE_FOCUS, 313 .nid = WEDGE_ANGLE, 314 .mid = 0x95, 315 .req = 8, 316 .direct = EFX_DIR_IN, 317 .def_val = 0x41F00000 318 }, 319 { .name = "SVM Level", 320 .parent_nid = MIC_SVM, 321 .nid = SVM_LEVEL, 322 .mid = 0x95, 323 .req = 45, 324 .direct = EFX_DIR_IN, 325 .def_val = 0x3F3D70A4 326 }, 327 { .name = "EQ Band0", 328 .parent_nid = EQUALIZER, 329 .nid = EQUALIZER_BAND_0, 330 .mid = 0x96, 331 .req = 11, 332 .direct = EFX_DIR_OUT, 333 .def_val = 0x00000000 334 }, 335 { .name = "EQ Band1", 336 .parent_nid = EQUALIZER, 337 .nid = EQUALIZER_BAND_1, 338 .mid = 0x96, 339 .req = 12, 340 .direct = EFX_DIR_OUT, 341 .def_val = 0x00000000 342 }, 343 { .name = "EQ Band2", 344 .parent_nid = EQUALIZER, 345 .nid = EQUALIZER_BAND_2, 346 .mid = 0x96, 347 .req = 13, 348 .direct = EFX_DIR_OUT, 349 .def_val = 0x00000000 350 }, 351 { .name = "EQ Band3", 352 .parent_nid = EQUALIZER, 353 .nid = EQUALIZER_BAND_3, 354 .mid = 0x96, 355 .req = 14, 356 .direct = EFX_DIR_OUT, 357 .def_val = 0x00000000 358 }, 359 { .name = "EQ Band4", 360 .parent_nid = EQUALIZER, 361 .nid = EQUALIZER_BAND_4, 362 .mid = 0x96, 363 .req = 15, 364 .direct = EFX_DIR_OUT, 365 .def_val = 0x00000000 366 }, 367 { .name = "EQ Band5", 368 .parent_nid = EQUALIZER, 369 .nid = EQUALIZER_BAND_5, 370 .mid = 0x96, 371 .req = 16, 372 .direct = EFX_DIR_OUT, 373 .def_val = 0x00000000 374 }, 375 { .name = "EQ Band6", 376 .parent_nid = EQUALIZER, 377 .nid = EQUALIZER_BAND_6, 378 .mid = 0x96, 379 .req = 17, 380 .direct = EFX_DIR_OUT, 381 .def_val = 0x00000000 382 }, 383 { .name = "EQ Band7", 384 .parent_nid = EQUALIZER, 385 .nid = EQUALIZER_BAND_7, 386 .mid = 0x96, 387 .req = 18, 388 .direct = EFX_DIR_OUT, 389 .def_val = 0x00000000 390 }, 391 { .name = "EQ Band8", 392 .parent_nid = EQUALIZER, 393 .nid = EQUALIZER_BAND_8, 394 .mid = 0x96, 395 .req = 19, 396 .direct = EFX_DIR_OUT, 397 .def_val = 0x00000000 398 }, 399 { .name = "EQ Band9", 400 .parent_nid = EQUALIZER, 401 .nid = EQUALIZER_BAND_9, 402 .mid = 0x96, 403 .req = 20, 404 .direct = EFX_DIR_OUT, 405 .def_val = 0x00000000 406 } 407 }; 408 #endif 409 410 /* Voice FX Presets */ 411 #define VOICEFX_MAX_PARAM_COUNT 9 412 413 struct ct_voicefx { 414 char *name; 415 hda_nid_t nid; 416 int mid; 417 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/ 418 }; 419 420 struct ct_voicefx_preset { 421 char *name; /*preset name*/ 422 unsigned int vals[VOICEFX_MAX_PARAM_COUNT]; 423 }; 424 425 static const struct ct_voicefx ca0132_voicefx = { 426 .name = "VoiceFX Capture Switch", 427 .nid = VOICEFX, 428 .mid = 0x95, 429 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18} 430 }; 431 432 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = { 433 { .name = "Neutral", 434 .vals = { 0x00000000, 0x43C80000, 0x44AF0000, 435 0x44FA0000, 0x3F800000, 0x3F800000, 436 0x3F800000, 0x00000000, 0x00000000 } 437 }, 438 { .name = "Female2Male", 439 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 440 0x44FA0000, 0x3F19999A, 0x3F866666, 441 0x3F800000, 0x00000000, 0x00000000 } 442 }, 443 { .name = "Male2Female", 444 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 445 0x450AC000, 0x4017AE14, 0x3F6B851F, 446 0x3F800000, 0x00000000, 0x00000000 } 447 }, 448 { .name = "ScrappyKid", 449 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 450 0x44FA0000, 0x40400000, 0x3F28F5C3, 451 0x3F800000, 0x00000000, 0x00000000 } 452 }, 453 { .name = "Elderly", 454 .vals = { 0x3F800000, 0x44324000, 0x44BB8000, 455 0x44E10000, 0x3FB33333, 0x3FB9999A, 456 0x3F800000, 0x3E3A2E43, 0x00000000 } 457 }, 458 { .name = "Orc", 459 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000, 460 0x45098000, 0x3F266666, 0x3FC00000, 461 0x3F800000, 0x00000000, 0x00000000 } 462 }, 463 { .name = "Elf", 464 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000, 465 0x45193000, 0x3F8E147B, 0x3F75C28F, 466 0x3F800000, 0x00000000, 0x00000000 } 467 }, 468 { .name = "Dwarf", 469 .vals = { 0x3F800000, 0x43930000, 0x44BEE000, 470 0x45007000, 0x3F451EB8, 0x3F7851EC, 471 0x3F800000, 0x00000000, 0x00000000 } 472 }, 473 { .name = "AlienBrute", 474 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF, 475 0x451F6000, 0x3F266666, 0x3FA7D945, 476 0x3F800000, 0x3CF5C28F, 0x00000000 } 477 }, 478 { .name = "Robot", 479 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 480 0x44FA0000, 0x3FB2718B, 0x3F800000, 481 0xBC07010E, 0x00000000, 0x00000000 } 482 }, 483 { .name = "Marine", 484 .vals = { 0x3F800000, 0x43C20000, 0x44906000, 485 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71, 486 0x3F0A3D71, 0x00000000, 0x00000000 } 487 }, 488 { .name = "Emo", 489 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 490 0x44FA0000, 0x3F800000, 0x3F800000, 491 0x3E4CCCCD, 0x00000000, 0x00000000 } 492 }, 493 { .name = "DeepVoice", 494 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF, 495 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA, 496 0x3F800000, 0x00000000, 0x00000000 } 497 }, 498 { .name = "Munchkin", 499 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 500 0x44FA0000, 0x3F800000, 0x3F1A043C, 501 0x3F800000, 0x00000000, 0x00000000 } 502 } 503 }; 504 505 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */ 506 507 #define EQ_PRESET_MAX_PARAM_COUNT 11 508 509 struct ct_eq { 510 char *name; 511 hda_nid_t nid; 512 int mid; 513 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/ 514 }; 515 516 struct ct_eq_preset { 517 char *name; /*preset name*/ 518 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT]; 519 }; 520 521 static const struct ct_eq ca0132_alt_eq_enum = { 522 .name = "FX: Equalizer Preset Switch", 523 .nid = EQ_PRESET_ENUM, 524 .mid = 0x96, 525 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20} 526 }; 527 528 529 static const struct ct_eq_preset ca0132_alt_eq_presets[] = { 530 { .name = "Flat", 531 .vals = { 0x00000000, 0x00000000, 0x00000000, 532 0x00000000, 0x00000000, 0x00000000, 533 0x00000000, 0x00000000, 0x00000000, 534 0x00000000, 0x00000000 } 535 }, 536 { .name = "Acoustic", 537 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD, 538 0x40000000, 0x00000000, 0x00000000, 539 0x00000000, 0x00000000, 0x40000000, 540 0x40000000, 0x40000000 } 541 }, 542 { .name = "Classical", 543 .vals = { 0x00000000, 0x00000000, 0x40C00000, 544 0x40C00000, 0x40466666, 0x00000000, 545 0x00000000, 0x00000000, 0x00000000, 546 0x40466666, 0x40466666 } 547 }, 548 { .name = "Country", 549 .vals = { 0x00000000, 0xBF99999A, 0x00000000, 550 0x3FA66666, 0x3FA66666, 0x3F8CCCCD, 551 0x00000000, 0x00000000, 0x40000000, 552 0x40466666, 0x40800000 } 553 }, 554 { .name = "Dance", 555 .vals = { 0x00000000, 0xBF99999A, 0x40000000, 556 0x40466666, 0x40866666, 0xBF99999A, 557 0xBF99999A, 0x00000000, 0x00000000, 558 0x40800000, 0x40800000 } 559 }, 560 { .name = "Jazz", 561 .vals = { 0x00000000, 0x00000000, 0x00000000, 562 0x3F8CCCCD, 0x40800000, 0x40800000, 563 0x40800000, 0x00000000, 0x3F8CCCCD, 564 0x40466666, 0x40466666 } 565 }, 566 { .name = "New Age", 567 .vals = { 0x00000000, 0x00000000, 0x40000000, 568 0x40000000, 0x00000000, 0x00000000, 569 0x00000000, 0x3F8CCCCD, 0x40000000, 570 0x40000000, 0x40000000 } 571 }, 572 { .name = "Pop", 573 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000, 574 0x40000000, 0x40000000, 0x00000000, 575 0xBF99999A, 0xBF99999A, 0x00000000, 576 0x40466666, 0x40C00000 } 577 }, 578 { .name = "Rock", 579 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A, 580 0x3F8CCCCD, 0x40000000, 0xBF99999A, 581 0xBF99999A, 0x00000000, 0x00000000, 582 0x40800000, 0x40800000 } 583 }, 584 { .name = "Vocal", 585 .vals = { 0x00000000, 0xC0000000, 0xBF99999A, 586 0xBF99999A, 0x00000000, 0x40466666, 587 0x40800000, 0x40466666, 0x00000000, 588 0x00000000, 0x3F8CCCCD } 589 } 590 }; 591 592 /* DSP command sequences for ca0132_alt_select_out */ 593 #define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */ 594 struct ca0132_alt_out_set { 595 char *name; /*preset name*/ 596 unsigned char commands; 597 unsigned int mids[ALT_OUT_SET_MAX_COMMANDS]; 598 unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS]; 599 unsigned int vals[ALT_OUT_SET_MAX_COMMANDS]; 600 }; 601 602 static const struct ca0132_alt_out_set alt_out_presets[] = { 603 { .name = "Line Out", 604 .commands = 7, 605 .mids = { 0x96, 0x96, 0x96, 0x8F, 606 0x96, 0x96, 0x96 }, 607 .reqs = { 0x19, 0x17, 0x18, 0x01, 608 0x1F, 0x15, 0x3A }, 609 .vals = { 0x3F000000, 0x42A00000, 0x00000000, 610 0x00000000, 0x00000000, 0x00000000, 611 0x00000000 } 612 }, 613 { .name = "Headphone", 614 .commands = 7, 615 .mids = { 0x96, 0x96, 0x96, 0x8F, 616 0x96, 0x96, 0x96 }, 617 .reqs = { 0x19, 0x17, 0x18, 0x01, 618 0x1F, 0x15, 0x3A }, 619 .vals = { 0x3F000000, 0x42A00000, 0x00000000, 620 0x00000000, 0x00000000, 0x00000000, 621 0x00000000 } 622 }, 623 { .name = "Surround", 624 .commands = 8, 625 .mids = { 0x96, 0x8F, 0x96, 0x96, 626 0x96, 0x96, 0x96, 0x96 }, 627 .reqs = { 0x18, 0x01, 0x1F, 0x15, 628 0x3A, 0x1A, 0x1B, 0x1C }, 629 .vals = { 0x00000000, 0x00000000, 0x00000000, 630 0x00000000, 0x00000000, 0x00000000, 631 0x00000000, 0x00000000 } 632 } 633 }; 634 635 /* 636 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume, 637 * and I don't know what the third req is, but it's always zero. I assume it's 638 * some sort of update or set command to tell the DSP there's new volume info. 639 */ 640 #define DSP_VOL_OUT 0 641 #define DSP_VOL_IN 1 642 643 struct ct_dsp_volume_ctl { 644 hda_nid_t vnid; 645 int mid; /* module ID*/ 646 unsigned int reqs[3]; /* scp req ID */ 647 }; 648 649 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = { 650 { .vnid = VNID_SPK, 651 .mid = 0x32, 652 .reqs = {3, 4, 2} 653 }, 654 { .vnid = VNID_MIC, 655 .mid = 0x37, 656 .reqs = {2, 3, 1} 657 } 658 }; 659 660 /* Values for ca0113_mmio_command_set for selecting output. */ 661 #define AE5_CA0113_OUT_SET_COMMANDS 6 662 struct ae5_ca0113_output_set { 663 unsigned int group[AE5_CA0113_OUT_SET_COMMANDS]; 664 unsigned int target[AE5_CA0113_OUT_SET_COMMANDS]; 665 unsigned int vals[AE5_CA0113_OUT_SET_COMMANDS]; 666 }; 667 668 static const struct ae5_ca0113_output_set ae5_ca0113_output_presets[] = { 669 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 670 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 671 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f } 672 }, 673 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 674 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 675 .vals = { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } 676 }, 677 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 678 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 679 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f } 680 } 681 }; 682 683 /* ae5 ca0113 command sequences to set headphone gain levels. */ 684 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4 685 struct ae5_headphone_gain_set { 686 char *name; 687 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS]; 688 }; 689 690 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = { 691 { .name = "Low (16-31", 692 .vals = { 0xff, 0x2c, 0xf5, 0x32 } 693 }, 694 { .name = "Medium (32-149", 695 .vals = { 0x38, 0xa8, 0x3e, 0x4c } 696 }, 697 { .name = "High (150-600", 698 .vals = { 0xff, 0xff, 0xff, 0x7f } 699 } 700 }; 701 702 struct ae5_filter_set { 703 char *name; 704 unsigned int val; 705 }; 706 707 static const struct ae5_filter_set ae5_filter_presets[] = { 708 { .name = "Slow Roll Off", 709 .val = 0xa0 710 }, 711 { .name = "Minimum Phase", 712 .val = 0xc0 713 }, 714 { .name = "Fast Roll Off", 715 .val = 0x80 716 } 717 }; 718 719 enum hda_cmd_vendor_io { 720 /* for DspIO node */ 721 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000, 722 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100, 723 724 VENDOR_DSPIO_STATUS = 0xF01, 725 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702, 726 VENDOR_DSPIO_SCP_READ_DATA = 0xF02, 727 VENDOR_DSPIO_DSP_INIT = 0x703, 728 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704, 729 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04, 730 731 /* for ChipIO node */ 732 VENDOR_CHIPIO_ADDRESS_LOW = 0x000, 733 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100, 734 VENDOR_CHIPIO_STREAM_FORMAT = 0x200, 735 VENDOR_CHIPIO_DATA_LOW = 0x300, 736 VENDOR_CHIPIO_DATA_HIGH = 0x400, 737 738 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500, 739 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00, 740 741 VENDOR_CHIPIO_GET_PARAMETER = 0xF00, 742 VENDOR_CHIPIO_STATUS = 0xF01, 743 VENDOR_CHIPIO_HIC_POST_READ = 0x702, 744 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03, 745 746 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707, 747 VENDOR_CHIPIO_8051_DATA_READ = 0xF07, 748 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08, 749 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709, 750 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09, 751 752 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A, 753 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A, 754 755 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C, 756 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C, 757 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D, 758 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E, 759 VENDOR_CHIPIO_FLAG_SET = 0x70F, 760 VENDOR_CHIPIO_FLAGS_GET = 0xF0F, 761 VENDOR_CHIPIO_PARAM_SET = 0x710, 762 VENDOR_CHIPIO_PARAM_GET = 0xF10, 763 764 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711, 765 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712, 766 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12, 767 VENDOR_CHIPIO_PORT_FREE_SET = 0x713, 768 769 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17, 770 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717, 771 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18, 772 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718, 773 774 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788, 775 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88, 776 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789, 777 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89, 778 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A, 779 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A, 780 781 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D 782 }; 783 784 /* 785 * Control flag IDs 786 */ 787 enum control_flag_id { 788 /* Connection manager stream setup is bypassed/enabled */ 789 CONTROL_FLAG_C_MGR = 0, 790 /* DSP DMA is bypassed/enabled */ 791 CONTROL_FLAG_DMA = 1, 792 /* 8051 'idle' mode is disabled/enabled */ 793 CONTROL_FLAG_IDLE_ENABLE = 2, 794 /* Tracker for the SPDIF-in path is bypassed/enabled */ 795 CONTROL_FLAG_TRACKER = 3, 796 /* DigitalOut to Spdif2Out connection is disabled/enabled */ 797 CONTROL_FLAG_SPDIF2OUT = 4, 798 /* Digital Microphone is disabled/enabled */ 799 CONTROL_FLAG_DMIC = 5, 800 /* ADC_B rate is 48 kHz/96 kHz */ 801 CONTROL_FLAG_ADC_B_96KHZ = 6, 802 /* ADC_C rate is 48 kHz/96 kHz */ 803 CONTROL_FLAG_ADC_C_96KHZ = 7, 804 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */ 805 CONTROL_FLAG_DAC_96KHZ = 8, 806 /* DSP rate is 48 kHz/96 kHz */ 807 CONTROL_FLAG_DSP_96KHZ = 9, 808 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */ 809 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10, 810 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */ 811 CONTROL_FLAG_SRC_RATE_96KHZ = 11, 812 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */ 813 CONTROL_FLAG_DECODE_LOOP = 12, 814 /* De-emphasis filter on DAC-1 disabled/enabled */ 815 CONTROL_FLAG_DAC1_DEEMPHASIS = 13, 816 /* De-emphasis filter on DAC-2 disabled/enabled */ 817 CONTROL_FLAG_DAC2_DEEMPHASIS = 14, 818 /* De-emphasis filter on DAC-3 disabled/enabled */ 819 CONTROL_FLAG_DAC3_DEEMPHASIS = 15, 820 /* High-pass filter on ADC_B disabled/enabled */ 821 CONTROL_FLAG_ADC_B_HIGH_PASS = 16, 822 /* High-pass filter on ADC_C disabled/enabled */ 823 CONTROL_FLAG_ADC_C_HIGH_PASS = 17, 824 /* Common mode on Port_A disabled/enabled */ 825 CONTROL_FLAG_PORT_A_COMMON_MODE = 18, 826 /* Common mode on Port_D disabled/enabled */ 827 CONTROL_FLAG_PORT_D_COMMON_MODE = 19, 828 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */ 829 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20, 830 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */ 831 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21, 832 /* ASI rate is 48kHz/96kHz */ 833 CONTROL_FLAG_ASI_96KHZ = 22, 834 /* DAC power settings able to control attached ports no/yes */ 835 CONTROL_FLAG_DACS_CONTROL_PORTS = 23, 836 /* Clock Stop OK reporting is disabled/enabled */ 837 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24, 838 /* Number of control flags */ 839 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1) 840 }; 841 842 /* 843 * Control parameter IDs 844 */ 845 enum control_param_id { 846 /* 0: None, 1: Mic1In*/ 847 CONTROL_PARAM_VIP_SOURCE = 1, 848 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */ 849 CONTROL_PARAM_SPDIF1_SOURCE = 2, 850 /* Port A output stage gain setting to use when 16 Ohm output 851 * impedance is selected*/ 852 CONTROL_PARAM_PORTA_160OHM_GAIN = 8, 853 /* Port D output stage gain setting to use when 16 Ohm output 854 * impedance is selected*/ 855 CONTROL_PARAM_PORTD_160OHM_GAIN = 10, 856 857 /* 858 * This control param name was found in the 8051 memory, and makes 859 * sense given the fact the AE-5 uses it and has the ASI flag set. 860 */ 861 CONTROL_PARAM_ASI = 23, 862 863 /* Stream Control */ 864 865 /* Select stream with the given ID */ 866 CONTROL_PARAM_STREAM_ID = 24, 867 /* Source connection point for the selected stream */ 868 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25, 869 /* Destination connection point for the selected stream */ 870 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26, 871 /* Number of audio channels in the selected stream */ 872 CONTROL_PARAM_STREAMS_CHANNELS = 27, 873 /*Enable control for the selected stream */ 874 CONTROL_PARAM_STREAM_CONTROL = 28, 875 876 /* Connection Point Control */ 877 878 /* Select connection point with the given ID */ 879 CONTROL_PARAM_CONN_POINT_ID = 29, 880 /* Connection point sample rate */ 881 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30, 882 883 /* Node Control */ 884 885 /* Select HDA node with the given ID */ 886 CONTROL_PARAM_NODE_ID = 31 887 }; 888 889 /* 890 * Dsp Io Status codes 891 */ 892 enum hda_vendor_status_dspio { 893 /* Success */ 894 VENDOR_STATUS_DSPIO_OK = 0x00, 895 /* Busy, unable to accept new command, the host must retry */ 896 VENDOR_STATUS_DSPIO_BUSY = 0x01, 897 /* SCP command queue is full */ 898 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02, 899 /* SCP response queue is empty */ 900 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03 901 }; 902 903 /* 904 * Chip Io Status codes 905 */ 906 enum hda_vendor_status_chipio { 907 /* Success */ 908 VENDOR_STATUS_CHIPIO_OK = 0x00, 909 /* Busy, unable to accept new command, the host must retry */ 910 VENDOR_STATUS_CHIPIO_BUSY = 0x01 911 }; 912 913 /* 914 * CA0132 sample rate 915 */ 916 enum ca0132_sample_rate { 917 SR_6_000 = 0x00, 918 SR_8_000 = 0x01, 919 SR_9_600 = 0x02, 920 SR_11_025 = 0x03, 921 SR_16_000 = 0x04, 922 SR_22_050 = 0x05, 923 SR_24_000 = 0x06, 924 SR_32_000 = 0x07, 925 SR_44_100 = 0x08, 926 SR_48_000 = 0x09, 927 SR_88_200 = 0x0A, 928 SR_96_000 = 0x0B, 929 SR_144_000 = 0x0C, 930 SR_176_400 = 0x0D, 931 SR_192_000 = 0x0E, 932 SR_384_000 = 0x0F, 933 934 SR_COUNT = 0x10, 935 936 SR_RATE_UNKNOWN = 0x1F 937 }; 938 939 enum dsp_download_state { 940 DSP_DOWNLOAD_FAILED = -1, 941 DSP_DOWNLOAD_INIT = 0, 942 DSP_DOWNLOADING = 1, 943 DSP_DOWNLOADED = 2 944 }; 945 946 /* retrieve parameters from hda format */ 947 #define get_hdafmt_chs(fmt) (fmt & 0xf) 948 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7) 949 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f) 950 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1) 951 952 /* 953 * CA0132 specific 954 */ 955 956 struct ca0132_spec { 957 const struct snd_kcontrol_new *mixers[5]; 958 unsigned int num_mixers; 959 const struct hda_verb *base_init_verbs; 960 const struct hda_verb *base_exit_verbs; 961 const struct hda_verb *chip_init_verbs; 962 const struct hda_verb *desktop_init_verbs; 963 struct hda_verb *spec_init_verbs; 964 struct auto_pin_cfg autocfg; 965 966 /* Nodes configurations */ 967 struct hda_multi_out multiout; 968 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS]; 969 hda_nid_t dacs[AUTO_CFG_MAX_OUTS]; 970 unsigned int num_outputs; 971 hda_nid_t input_pins[AUTO_PIN_LAST]; 972 hda_nid_t adcs[AUTO_PIN_LAST]; 973 hda_nid_t dig_out; 974 hda_nid_t dig_in; 975 unsigned int num_inputs; 976 hda_nid_t shared_mic_nid; 977 hda_nid_t shared_out_nid; 978 hda_nid_t unsol_tag_hp; 979 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */ 980 hda_nid_t unsol_tag_amic1; 981 982 /* chip access */ 983 struct mutex chipio_mutex; /* chip access mutex */ 984 u32 curr_chip_addx; 985 986 /* DSP download related */ 987 enum dsp_download_state dsp_state; 988 unsigned int dsp_stream_id; 989 unsigned int wait_scp; 990 unsigned int wait_scp_header; 991 unsigned int wait_num_data; 992 unsigned int scp_resp_header; 993 unsigned int scp_resp_data[4]; 994 unsigned int scp_resp_count; 995 bool startup_check_entered; 996 bool dsp_reload; 997 998 /* mixer and effects related */ 999 unsigned char dmic_ctl; 1000 int cur_out_type; 1001 int cur_mic_type; 1002 long vnode_lvol[VNODES_COUNT]; 1003 long vnode_rvol[VNODES_COUNT]; 1004 long vnode_lswitch[VNODES_COUNT]; 1005 long vnode_rswitch[VNODES_COUNT]; 1006 long effects_switch[EFFECTS_COUNT]; 1007 long voicefx_val; 1008 long cur_mic_boost; 1009 /* ca0132_alt control related values */ 1010 unsigned char in_enum_val; 1011 unsigned char out_enum_val; 1012 unsigned char mic_boost_enum_val; 1013 unsigned char smart_volume_setting; 1014 long fx_ctl_val[EFFECT_LEVEL_SLIDERS]; 1015 long xbass_xover_freq; 1016 long eq_preset_val; 1017 unsigned int tlv[4]; 1018 struct hda_vmaster_mute_hook vmaster_mute; 1019 /* AE-5 Control values */ 1020 unsigned char ae5_headphone_gain_val; 1021 unsigned char ae5_filter_val; 1022 /* ZxR Control Values */ 1023 unsigned char zxr_gain_set; 1024 1025 struct hda_codec *codec; 1026 struct delayed_work unsol_hp_work; 1027 int quirk; 1028 1029 #ifdef ENABLE_TUNING_CONTROLS 1030 long cur_ctl_vals[TUNING_CTLS_COUNT]; 1031 #endif 1032 /* 1033 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster 1034 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown 1035 * things. 1036 */ 1037 bool use_pci_mmio; 1038 void __iomem *mem_base; 1039 1040 /* 1041 * Whether or not to use the alt functions like alt_select_out, 1042 * alt_select_in, etc. Only used on desktop codecs for now, because of 1043 * surround sound support. 1044 */ 1045 bool use_alt_functions; 1046 1047 /* 1048 * Whether or not to use alt controls: volume effect sliders, EQ 1049 * presets, smart volume presets, and new control names with FX prefix. 1050 * Renames PlayEnhancement and CrystalVoice too. 1051 */ 1052 bool use_alt_controls; 1053 }; 1054 1055 /* 1056 * CA0132 quirks table 1057 */ 1058 enum { 1059 QUIRK_NONE, 1060 QUIRK_ALIENWARE, 1061 QUIRK_ALIENWARE_M17XR4, 1062 QUIRK_SBZ, 1063 QUIRK_ZXR, 1064 QUIRK_ZXR_DBPRO, 1065 QUIRK_R3DI, 1066 QUIRK_R3D, 1067 QUIRK_AE5, 1068 }; 1069 1070 #ifdef CONFIG_PCI 1071 #define ca0132_quirk(spec) ((spec)->quirk) 1072 #define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio) 1073 #define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions) 1074 #define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls) 1075 #else 1076 #define ca0132_quirk(spec) ({ (void)(spec); QUIRK_NONE; }) 1077 #define ca0132_use_alt_functions(spec) ({ (void)(spec); false; }) 1078 #define ca0132_use_pci_mmio(spec) ({ (void)(spec); false; }) 1079 #define ca0132_use_alt_controls(spec) ({ (void)(spec); false; }) 1080 #endif 1081 1082 static const struct hda_pintbl alienware_pincfgs[] = { 1083 { 0x0b, 0x90170110 }, /* Builtin Speaker */ 1084 { 0x0c, 0x411111f0 }, /* N/A */ 1085 { 0x0d, 0x411111f0 }, /* N/A */ 1086 { 0x0e, 0x411111f0 }, /* N/A */ 1087 { 0x0f, 0x0321101f }, /* HP */ 1088 { 0x10, 0x411111f0 }, /* Headset? disabled for now */ 1089 { 0x11, 0x03a11021 }, /* Mic */ 1090 { 0x12, 0xd5a30140 }, /* Builtin Mic */ 1091 { 0x13, 0x411111f0 }, /* N/A */ 1092 { 0x18, 0x411111f0 }, /* N/A */ 1093 {} 1094 }; 1095 1096 /* Sound Blaster Z pin configs taken from Windows Driver */ 1097 static const struct hda_pintbl sbz_pincfgs[] = { 1098 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1099 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1100 { 0x0d, 0x014510f0 }, /* Digital Out */ 1101 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1102 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */ 1103 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1104 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1105 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1106 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1107 { 0x18, 0x50d000f0 }, /* N/A */ 1108 {} 1109 }; 1110 1111 /* Sound Blaster ZxR pin configs taken from Windows Driver */ 1112 static const struct hda_pintbl zxr_pincfgs[] = { 1113 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */ 1114 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/ 1115 { 0x0d, 0x014510f0 }, /* Digital Out */ 1116 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/ 1117 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */ 1118 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */ 1119 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */ 1120 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */ 1121 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1122 { 0x18, 0x50d000f0 }, /* N/A */ 1123 {} 1124 }; 1125 1126 /* Recon3D pin configs taken from Windows Driver */ 1127 static const struct hda_pintbl r3d_pincfgs[] = { 1128 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1129 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1130 { 0x0d, 0x014510f0 }, /* Digital Out */ 1131 { 0x0e, 0x01c520f0 }, /* SPDIF In */ 1132 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1133 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1134 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1135 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1136 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1137 { 0x18, 0x50d000f0 }, /* N/A */ 1138 {} 1139 }; 1140 1141 /* Sound Blaster AE-5 pin configs taken from Windows Driver */ 1142 static const struct hda_pintbl ae5_pincfgs[] = { 1143 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1144 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1145 { 0x0d, 0x014510f0 }, /* Digital Out */ 1146 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1147 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */ 1148 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1149 { 0x11, 0x01a170ff }, /* Port B -- LineMicIn2 / Rear Headphone */ 1150 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1151 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1152 { 0x18, 0x50d000f0 }, /* N/A */ 1153 {} 1154 }; 1155 1156 /* Recon3D integrated pin configs taken from Windows Driver */ 1157 static const struct hda_pintbl r3di_pincfgs[] = { 1158 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1159 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1160 { 0x0d, 0x014510f0 }, /* Digital Out */ 1161 { 0x0e, 0x41c520f0 }, /* SPDIF In */ 1162 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1163 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1164 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1165 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1166 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1167 { 0x18, 0x500000f0 }, /* N/A */ 1168 {} 1169 }; 1170 1171 static const struct snd_pci_quirk ca0132_quirks[] = { 1172 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4), 1173 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE), 1174 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE), 1175 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE), 1176 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ), 1177 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ), 1178 SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ), 1179 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ), 1180 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI), 1181 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI), 1182 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI), 1183 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D), 1184 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5), 1185 {} 1186 }; 1187 1188 /* 1189 * CA0132 codec access 1190 */ 1191 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid, 1192 unsigned int verb, unsigned int parm, unsigned int *res) 1193 { 1194 unsigned int response; 1195 response = snd_hda_codec_read(codec, nid, 0, verb, parm); 1196 *res = response; 1197 1198 return ((response == -1) ? -1 : 0); 1199 } 1200 1201 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid, 1202 unsigned short converter_format, unsigned int *res) 1203 { 1204 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT, 1205 converter_format & 0xffff, res); 1206 } 1207 1208 static int codec_set_converter_stream_channel(struct hda_codec *codec, 1209 hda_nid_t nid, unsigned char stream, 1210 unsigned char channel, unsigned int *res) 1211 { 1212 unsigned char converter_stream_channel = 0; 1213 1214 converter_stream_channel = (stream << 4) | (channel & 0x0f); 1215 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID, 1216 converter_stream_channel, res); 1217 } 1218 1219 /* Chip access helper function */ 1220 static int chipio_send(struct hda_codec *codec, 1221 unsigned int reg, 1222 unsigned int data) 1223 { 1224 unsigned int res; 1225 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1226 1227 /* send bits of data specified by reg */ 1228 do { 1229 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1230 reg, data); 1231 if (res == VENDOR_STATUS_CHIPIO_OK) 1232 return 0; 1233 msleep(20); 1234 } while (time_before(jiffies, timeout)); 1235 1236 return -EIO; 1237 } 1238 1239 /* 1240 * Write chip address through the vendor widget -- NOT protected by the Mutex! 1241 */ 1242 static int chipio_write_address(struct hda_codec *codec, 1243 unsigned int chip_addx) 1244 { 1245 struct ca0132_spec *spec = codec->spec; 1246 int res; 1247 1248 if (spec->curr_chip_addx == chip_addx) 1249 return 0; 1250 1251 /* send low 16 bits of the address */ 1252 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW, 1253 chip_addx & 0xffff); 1254 1255 if (res != -EIO) { 1256 /* send high 16 bits of the address */ 1257 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH, 1258 chip_addx >> 16); 1259 } 1260 1261 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx; 1262 1263 return res; 1264 } 1265 1266 /* 1267 * Write data through the vendor widget -- NOT protected by the Mutex! 1268 */ 1269 static int chipio_write_data(struct hda_codec *codec, unsigned int data) 1270 { 1271 struct ca0132_spec *spec = codec->spec; 1272 int res; 1273 1274 /* send low 16 bits of the data */ 1275 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff); 1276 1277 if (res != -EIO) { 1278 /* send high 16 bits of the data */ 1279 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH, 1280 data >> 16); 1281 } 1282 1283 /*If no error encountered, automatically increment the address 1284 as per chip behaviour*/ 1285 spec->curr_chip_addx = (res != -EIO) ? 1286 (spec->curr_chip_addx + 4) : ~0U; 1287 return res; 1288 } 1289 1290 /* 1291 * Write multiple data through the vendor widget -- NOT protected by the Mutex! 1292 */ 1293 static int chipio_write_data_multiple(struct hda_codec *codec, 1294 const u32 *data, 1295 unsigned int count) 1296 { 1297 int status = 0; 1298 1299 if (data == NULL) { 1300 codec_dbg(codec, "chipio_write_data null ptr\n"); 1301 return -EINVAL; 1302 } 1303 1304 while ((count-- != 0) && (status == 0)) 1305 status = chipio_write_data(codec, *data++); 1306 1307 return status; 1308 } 1309 1310 1311 /* 1312 * Read data through the vendor widget -- NOT protected by the Mutex! 1313 */ 1314 static int chipio_read_data(struct hda_codec *codec, unsigned int *data) 1315 { 1316 struct ca0132_spec *spec = codec->spec; 1317 int res; 1318 1319 /* post read */ 1320 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0); 1321 1322 if (res != -EIO) { 1323 /* read status */ 1324 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 1325 } 1326 1327 if (res != -EIO) { 1328 /* read data */ 1329 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1330 VENDOR_CHIPIO_HIC_READ_DATA, 1331 0); 1332 } 1333 1334 /*If no error encountered, automatically increment the address 1335 as per chip behaviour*/ 1336 spec->curr_chip_addx = (res != -EIO) ? 1337 (spec->curr_chip_addx + 4) : ~0U; 1338 return res; 1339 } 1340 1341 /* 1342 * Write given value to the given address through the chip I/O widget. 1343 * protected by the Mutex 1344 */ 1345 static int chipio_write(struct hda_codec *codec, 1346 unsigned int chip_addx, const unsigned int data) 1347 { 1348 struct ca0132_spec *spec = codec->spec; 1349 int err; 1350 1351 mutex_lock(&spec->chipio_mutex); 1352 1353 /* write the address, and if successful proceed to write data */ 1354 err = chipio_write_address(codec, chip_addx); 1355 if (err < 0) 1356 goto exit; 1357 1358 err = chipio_write_data(codec, data); 1359 if (err < 0) 1360 goto exit; 1361 1362 exit: 1363 mutex_unlock(&spec->chipio_mutex); 1364 return err; 1365 } 1366 1367 /* 1368 * Write given value to the given address through the chip I/O widget. 1369 * not protected by the Mutex 1370 */ 1371 static int chipio_write_no_mutex(struct hda_codec *codec, 1372 unsigned int chip_addx, const unsigned int data) 1373 { 1374 int err; 1375 1376 1377 /* write the address, and if successful proceed to write data */ 1378 err = chipio_write_address(codec, chip_addx); 1379 if (err < 0) 1380 goto exit; 1381 1382 err = chipio_write_data(codec, data); 1383 if (err < 0) 1384 goto exit; 1385 1386 exit: 1387 return err; 1388 } 1389 1390 /* 1391 * Write multiple values to the given address through the chip I/O widget. 1392 * protected by the Mutex 1393 */ 1394 static int chipio_write_multiple(struct hda_codec *codec, 1395 u32 chip_addx, 1396 const u32 *data, 1397 unsigned int count) 1398 { 1399 struct ca0132_spec *spec = codec->spec; 1400 int status; 1401 1402 mutex_lock(&spec->chipio_mutex); 1403 status = chipio_write_address(codec, chip_addx); 1404 if (status < 0) 1405 goto error; 1406 1407 status = chipio_write_data_multiple(codec, data, count); 1408 error: 1409 mutex_unlock(&spec->chipio_mutex); 1410 1411 return status; 1412 } 1413 1414 /* 1415 * Read the given address through the chip I/O widget 1416 * protected by the Mutex 1417 */ 1418 static int chipio_read(struct hda_codec *codec, 1419 unsigned int chip_addx, unsigned int *data) 1420 { 1421 struct ca0132_spec *spec = codec->spec; 1422 int err; 1423 1424 mutex_lock(&spec->chipio_mutex); 1425 1426 /* write the address, and if successful proceed to write data */ 1427 err = chipio_write_address(codec, chip_addx); 1428 if (err < 0) 1429 goto exit; 1430 1431 err = chipio_read_data(codec, data); 1432 if (err < 0) 1433 goto exit; 1434 1435 exit: 1436 mutex_unlock(&spec->chipio_mutex); 1437 return err; 1438 } 1439 1440 /* 1441 * Set chip control flags through the chip I/O widget. 1442 */ 1443 static void chipio_set_control_flag(struct hda_codec *codec, 1444 enum control_flag_id flag_id, 1445 bool flag_state) 1446 { 1447 unsigned int val; 1448 unsigned int flag_bit; 1449 1450 flag_bit = (flag_state ? 1 : 0); 1451 val = (flag_bit << 7) | (flag_id); 1452 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1453 VENDOR_CHIPIO_FLAG_SET, val); 1454 } 1455 1456 /* 1457 * Set chip parameters through the chip I/O widget. 1458 */ 1459 static void chipio_set_control_param(struct hda_codec *codec, 1460 enum control_param_id param_id, int param_val) 1461 { 1462 struct ca0132_spec *spec = codec->spec; 1463 int val; 1464 1465 if ((param_id < 32) && (param_val < 8)) { 1466 val = (param_val << 5) | (param_id); 1467 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1468 VENDOR_CHIPIO_PARAM_SET, val); 1469 } else { 1470 mutex_lock(&spec->chipio_mutex); 1471 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1472 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1473 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1474 param_id); 1475 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1476 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1477 param_val); 1478 } 1479 mutex_unlock(&spec->chipio_mutex); 1480 } 1481 } 1482 1483 /* 1484 * Set chip parameters through the chip I/O widget. NO MUTEX. 1485 */ 1486 static void chipio_set_control_param_no_mutex(struct hda_codec *codec, 1487 enum control_param_id param_id, int param_val) 1488 { 1489 int val; 1490 1491 if ((param_id < 32) && (param_val < 8)) { 1492 val = (param_val << 5) | (param_id); 1493 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1494 VENDOR_CHIPIO_PARAM_SET, val); 1495 } else { 1496 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1497 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1498 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1499 param_id); 1500 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1501 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1502 param_val); 1503 } 1504 } 1505 } 1506 /* 1507 * Connect stream to a source point, and then connect 1508 * that source point to a destination point. 1509 */ 1510 static void chipio_set_stream_source_dest(struct hda_codec *codec, 1511 int streamid, int source_point, int dest_point) 1512 { 1513 chipio_set_control_param_no_mutex(codec, 1514 CONTROL_PARAM_STREAM_ID, streamid); 1515 chipio_set_control_param_no_mutex(codec, 1516 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point); 1517 chipio_set_control_param_no_mutex(codec, 1518 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point); 1519 } 1520 1521 /* 1522 * Set number of channels in the selected stream. 1523 */ 1524 static void chipio_set_stream_channels(struct hda_codec *codec, 1525 int streamid, unsigned int channels) 1526 { 1527 chipio_set_control_param_no_mutex(codec, 1528 CONTROL_PARAM_STREAM_ID, streamid); 1529 chipio_set_control_param_no_mutex(codec, 1530 CONTROL_PARAM_STREAMS_CHANNELS, channels); 1531 } 1532 1533 /* 1534 * Enable/Disable audio stream. 1535 */ 1536 static void chipio_set_stream_control(struct hda_codec *codec, 1537 int streamid, int enable) 1538 { 1539 chipio_set_control_param_no_mutex(codec, 1540 CONTROL_PARAM_STREAM_ID, streamid); 1541 chipio_set_control_param_no_mutex(codec, 1542 CONTROL_PARAM_STREAM_CONTROL, enable); 1543 } 1544 1545 1546 /* 1547 * Set sampling rate of the connection point. NO MUTEX. 1548 */ 1549 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec, 1550 int connid, enum ca0132_sample_rate rate) 1551 { 1552 chipio_set_control_param_no_mutex(codec, 1553 CONTROL_PARAM_CONN_POINT_ID, connid); 1554 chipio_set_control_param_no_mutex(codec, 1555 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate); 1556 } 1557 1558 /* 1559 * Set sampling rate of the connection point. 1560 */ 1561 static void chipio_set_conn_rate(struct hda_codec *codec, 1562 int connid, enum ca0132_sample_rate rate) 1563 { 1564 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid); 1565 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, 1566 rate); 1567 } 1568 1569 /* 1570 * Writes to the 8051's internal address space directly instead of indirectly, 1571 * giving access to the special function registers located at addresses 1572 * 0x80-0xFF. 1573 */ 1574 static void chipio_8051_write_direct(struct hda_codec *codec, 1575 unsigned int addr, unsigned int data) 1576 { 1577 unsigned int verb; 1578 1579 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data; 1580 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr); 1581 } 1582 1583 /* 1584 * Enable clocks. 1585 */ 1586 static void chipio_enable_clocks(struct hda_codec *codec) 1587 { 1588 struct ca0132_spec *spec = codec->spec; 1589 1590 mutex_lock(&spec->chipio_mutex); 1591 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1592 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0); 1593 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1594 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); 1595 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1596 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5); 1597 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1598 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b); 1599 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1600 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6); 1601 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1602 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); 1603 mutex_unlock(&spec->chipio_mutex); 1604 } 1605 1606 /* 1607 * CA0132 DSP IO stuffs 1608 */ 1609 static int dspio_send(struct hda_codec *codec, unsigned int reg, 1610 unsigned int data) 1611 { 1612 int res; 1613 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1614 1615 /* send bits of data specified by reg to dsp */ 1616 do { 1617 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data); 1618 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY)) 1619 return res; 1620 msleep(20); 1621 } while (time_before(jiffies, timeout)); 1622 1623 return -EIO; 1624 } 1625 1626 /* 1627 * Wait for DSP to be ready for commands 1628 */ 1629 static void dspio_write_wait(struct hda_codec *codec) 1630 { 1631 int status; 1632 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1633 1634 do { 1635 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1636 VENDOR_DSPIO_STATUS, 0); 1637 if ((status == VENDOR_STATUS_DSPIO_OK) || 1638 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)) 1639 break; 1640 msleep(1); 1641 } while (time_before(jiffies, timeout)); 1642 } 1643 1644 /* 1645 * Write SCP data to DSP 1646 */ 1647 static int dspio_write(struct hda_codec *codec, unsigned int scp_data) 1648 { 1649 struct ca0132_spec *spec = codec->spec; 1650 int status; 1651 1652 dspio_write_wait(codec); 1653 1654 mutex_lock(&spec->chipio_mutex); 1655 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW, 1656 scp_data & 0xffff); 1657 if (status < 0) 1658 goto error; 1659 1660 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH, 1661 scp_data >> 16); 1662 if (status < 0) 1663 goto error; 1664 1665 /* OK, now check if the write itself has executed*/ 1666 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1667 VENDOR_DSPIO_STATUS, 0); 1668 error: 1669 mutex_unlock(&spec->chipio_mutex); 1670 1671 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ? 1672 -EIO : 0; 1673 } 1674 1675 /* 1676 * Write multiple SCP data to DSP 1677 */ 1678 static int dspio_write_multiple(struct hda_codec *codec, 1679 unsigned int *buffer, unsigned int size) 1680 { 1681 int status = 0; 1682 unsigned int count; 1683 1684 if (buffer == NULL) 1685 return -EINVAL; 1686 1687 count = 0; 1688 while (count < size) { 1689 status = dspio_write(codec, *buffer++); 1690 if (status != 0) 1691 break; 1692 count++; 1693 } 1694 1695 return status; 1696 } 1697 1698 static int dspio_read(struct hda_codec *codec, unsigned int *data) 1699 { 1700 int status; 1701 1702 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0); 1703 if (status == -EIO) 1704 return status; 1705 1706 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0); 1707 if (status == -EIO || 1708 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY) 1709 return -EIO; 1710 1711 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1712 VENDOR_DSPIO_SCP_READ_DATA, 0); 1713 1714 return 0; 1715 } 1716 1717 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer, 1718 unsigned int *buf_size, unsigned int size_count) 1719 { 1720 int status = 0; 1721 unsigned int size = *buf_size; 1722 unsigned int count; 1723 unsigned int skip_count; 1724 unsigned int dummy; 1725 1726 if (buffer == NULL) 1727 return -1; 1728 1729 count = 0; 1730 while (count < size && count < size_count) { 1731 status = dspio_read(codec, buffer++); 1732 if (status != 0) 1733 break; 1734 count++; 1735 } 1736 1737 skip_count = count; 1738 if (status == 0) { 1739 while (skip_count < size) { 1740 status = dspio_read(codec, &dummy); 1741 if (status != 0) 1742 break; 1743 skip_count++; 1744 } 1745 } 1746 *buf_size = count; 1747 1748 return status; 1749 } 1750 1751 /* 1752 * Construct the SCP header using corresponding fields 1753 */ 1754 static inline unsigned int 1755 make_scp_header(unsigned int target_id, unsigned int source_id, 1756 unsigned int get_flag, unsigned int req, 1757 unsigned int device_flag, unsigned int resp_flag, 1758 unsigned int error_flag, unsigned int data_size) 1759 { 1760 unsigned int header = 0; 1761 1762 header = (data_size & 0x1f) << 27; 1763 header |= (error_flag & 0x01) << 26; 1764 header |= (resp_flag & 0x01) << 25; 1765 header |= (device_flag & 0x01) << 24; 1766 header |= (req & 0x7f) << 17; 1767 header |= (get_flag & 0x01) << 16; 1768 header |= (source_id & 0xff) << 8; 1769 header |= target_id & 0xff; 1770 1771 return header; 1772 } 1773 1774 /* 1775 * Extract corresponding fields from SCP header 1776 */ 1777 static inline void 1778 extract_scp_header(unsigned int header, 1779 unsigned int *target_id, unsigned int *source_id, 1780 unsigned int *get_flag, unsigned int *req, 1781 unsigned int *device_flag, unsigned int *resp_flag, 1782 unsigned int *error_flag, unsigned int *data_size) 1783 { 1784 if (data_size) 1785 *data_size = (header >> 27) & 0x1f; 1786 if (error_flag) 1787 *error_flag = (header >> 26) & 0x01; 1788 if (resp_flag) 1789 *resp_flag = (header >> 25) & 0x01; 1790 if (device_flag) 1791 *device_flag = (header >> 24) & 0x01; 1792 if (req) 1793 *req = (header >> 17) & 0x7f; 1794 if (get_flag) 1795 *get_flag = (header >> 16) & 0x01; 1796 if (source_id) 1797 *source_id = (header >> 8) & 0xff; 1798 if (target_id) 1799 *target_id = header & 0xff; 1800 } 1801 1802 #define SCP_MAX_DATA_WORDS (16) 1803 1804 /* Structure to contain any SCP message */ 1805 struct scp_msg { 1806 unsigned int hdr; 1807 unsigned int data[SCP_MAX_DATA_WORDS]; 1808 }; 1809 1810 static void dspio_clear_response_queue(struct hda_codec *codec) 1811 { 1812 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1813 unsigned int dummy = 0; 1814 int status; 1815 1816 /* clear all from the response queue */ 1817 do { 1818 status = dspio_read(codec, &dummy); 1819 } while (status == 0 && time_before(jiffies, timeout)); 1820 } 1821 1822 static int dspio_get_response_data(struct hda_codec *codec) 1823 { 1824 struct ca0132_spec *spec = codec->spec; 1825 unsigned int data = 0; 1826 unsigned int count; 1827 1828 if (dspio_read(codec, &data) < 0) 1829 return -EIO; 1830 1831 if ((data & 0x00ffffff) == spec->wait_scp_header) { 1832 spec->scp_resp_header = data; 1833 spec->scp_resp_count = data >> 27; 1834 count = spec->wait_num_data; 1835 dspio_read_multiple(codec, spec->scp_resp_data, 1836 &spec->scp_resp_count, count); 1837 return 0; 1838 } 1839 1840 return -EIO; 1841 } 1842 1843 /* 1844 * Send SCP message to DSP 1845 */ 1846 static int dspio_send_scp_message(struct hda_codec *codec, 1847 unsigned char *send_buf, 1848 unsigned int send_buf_size, 1849 unsigned char *return_buf, 1850 unsigned int return_buf_size, 1851 unsigned int *bytes_returned) 1852 { 1853 struct ca0132_spec *spec = codec->spec; 1854 int status = -1; 1855 unsigned int scp_send_size = 0; 1856 unsigned int total_size; 1857 bool waiting_for_resp = false; 1858 unsigned int header; 1859 struct scp_msg *ret_msg; 1860 unsigned int resp_src_id, resp_target_id; 1861 unsigned int data_size, src_id, target_id, get_flag, device_flag; 1862 1863 if (bytes_returned) 1864 *bytes_returned = 0; 1865 1866 /* get scp header from buffer */ 1867 header = *((unsigned int *)send_buf); 1868 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL, 1869 &device_flag, NULL, NULL, &data_size); 1870 scp_send_size = data_size + 1; 1871 total_size = (scp_send_size * 4); 1872 1873 if (send_buf_size < total_size) 1874 return -EINVAL; 1875 1876 if (get_flag || device_flag) { 1877 if (!return_buf || return_buf_size < 4 || !bytes_returned) 1878 return -EINVAL; 1879 1880 spec->wait_scp_header = *((unsigned int *)send_buf); 1881 1882 /* swap source id with target id */ 1883 resp_target_id = src_id; 1884 resp_src_id = target_id; 1885 spec->wait_scp_header &= 0xffff0000; 1886 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id); 1887 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1; 1888 spec->wait_scp = 1; 1889 waiting_for_resp = true; 1890 } 1891 1892 status = dspio_write_multiple(codec, (unsigned int *)send_buf, 1893 scp_send_size); 1894 if (status < 0) { 1895 spec->wait_scp = 0; 1896 return status; 1897 } 1898 1899 if (waiting_for_resp) { 1900 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1901 memset(return_buf, 0, return_buf_size); 1902 do { 1903 msleep(20); 1904 } while (spec->wait_scp && time_before(jiffies, timeout)); 1905 waiting_for_resp = false; 1906 if (!spec->wait_scp) { 1907 ret_msg = (struct scp_msg *)return_buf; 1908 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4); 1909 memcpy(&ret_msg->data, spec->scp_resp_data, 1910 spec->wait_num_data); 1911 *bytes_returned = (spec->scp_resp_count + 1) * 4; 1912 status = 0; 1913 } else { 1914 status = -EIO; 1915 } 1916 spec->wait_scp = 0; 1917 } 1918 1919 return status; 1920 } 1921 1922 /** 1923 * Prepare and send the SCP message to DSP 1924 * @codec: the HDA codec 1925 * @mod_id: ID of the DSP module to send the command 1926 * @req: ID of request to send to the DSP module 1927 * @dir: SET or GET 1928 * @data: pointer to the data to send with the request, request specific 1929 * @len: length of the data, in bytes 1930 * @reply: point to the buffer to hold data returned for a reply 1931 * @reply_len: length of the reply buffer returned from GET 1932 * 1933 * Returns zero or a negative error code. 1934 */ 1935 static int dspio_scp(struct hda_codec *codec, 1936 int mod_id, int src_id, int req, int dir, const void *data, 1937 unsigned int len, void *reply, unsigned int *reply_len) 1938 { 1939 int status = 0; 1940 struct scp_msg scp_send, scp_reply; 1941 unsigned int ret_bytes, send_size, ret_size; 1942 unsigned int send_get_flag, reply_resp_flag, reply_error_flag; 1943 unsigned int reply_data_size; 1944 1945 memset(&scp_send, 0, sizeof(scp_send)); 1946 memset(&scp_reply, 0, sizeof(scp_reply)); 1947 1948 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS)) 1949 return -EINVAL; 1950 1951 if (dir == SCP_GET && reply == NULL) { 1952 codec_dbg(codec, "dspio_scp get but has no buffer\n"); 1953 return -EINVAL; 1954 } 1955 1956 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) { 1957 codec_dbg(codec, "dspio_scp bad resp buf len parms\n"); 1958 return -EINVAL; 1959 } 1960 1961 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req, 1962 0, 0, 0, len/sizeof(unsigned int)); 1963 if (data != NULL && len > 0) { 1964 len = min((unsigned int)(sizeof(scp_send.data)), len); 1965 memcpy(scp_send.data, data, len); 1966 } 1967 1968 ret_bytes = 0; 1969 send_size = sizeof(unsigned int) + len; 1970 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send, 1971 send_size, (unsigned char *)&scp_reply, 1972 sizeof(scp_reply), &ret_bytes); 1973 1974 if (status < 0) { 1975 codec_dbg(codec, "dspio_scp: send scp msg failed\n"); 1976 return status; 1977 } 1978 1979 /* extract send and reply headers members */ 1980 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag, 1981 NULL, NULL, NULL, NULL, NULL); 1982 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL, 1983 &reply_resp_flag, &reply_error_flag, 1984 &reply_data_size); 1985 1986 if (!send_get_flag) 1987 return 0; 1988 1989 if (reply_resp_flag && !reply_error_flag) { 1990 ret_size = (ret_bytes - sizeof(scp_reply.hdr)) 1991 / sizeof(unsigned int); 1992 1993 if (*reply_len < ret_size*sizeof(unsigned int)) { 1994 codec_dbg(codec, "reply too long for buf\n"); 1995 return -EINVAL; 1996 } else if (ret_size != reply_data_size) { 1997 codec_dbg(codec, "RetLen and HdrLen .NE.\n"); 1998 return -EINVAL; 1999 } else if (!reply) { 2000 codec_dbg(codec, "NULL reply\n"); 2001 return -EINVAL; 2002 } else { 2003 *reply_len = ret_size*sizeof(unsigned int); 2004 memcpy(reply, scp_reply.data, *reply_len); 2005 } 2006 } else { 2007 codec_dbg(codec, "reply ill-formed or errflag set\n"); 2008 return -EIO; 2009 } 2010 2011 return status; 2012 } 2013 2014 /* 2015 * Set DSP parameters 2016 */ 2017 static int dspio_set_param(struct hda_codec *codec, int mod_id, 2018 int src_id, int req, const void *data, unsigned int len) 2019 { 2020 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL, 2021 NULL); 2022 } 2023 2024 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id, 2025 int req, const unsigned int data) 2026 { 2027 return dspio_set_param(codec, mod_id, 0x20, req, &data, 2028 sizeof(unsigned int)); 2029 } 2030 2031 static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id, 2032 int req, const unsigned int data) 2033 { 2034 return dspio_set_param(codec, mod_id, 0x00, req, &data, 2035 sizeof(unsigned int)); 2036 } 2037 2038 /* 2039 * Allocate a DSP DMA channel via an SCP message 2040 */ 2041 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan) 2042 { 2043 int status = 0; 2044 unsigned int size = sizeof(dma_chan); 2045 2046 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n"); 2047 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2048 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0, 2049 dma_chan, &size); 2050 2051 if (status < 0) { 2052 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n"); 2053 return status; 2054 } 2055 2056 if ((*dma_chan + 1) == 0) { 2057 codec_dbg(codec, "no free dma channels to allocate\n"); 2058 return -EBUSY; 2059 } 2060 2061 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan); 2062 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n"); 2063 2064 return status; 2065 } 2066 2067 /* 2068 * Free a DSP DMA via an SCP message 2069 */ 2070 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan) 2071 { 2072 int status = 0; 2073 unsigned int dummy = 0; 2074 2075 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n"); 2076 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan); 2077 2078 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2079 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan, 2080 sizeof(dma_chan), NULL, &dummy); 2081 2082 if (status < 0) { 2083 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n"); 2084 return status; 2085 } 2086 2087 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n"); 2088 2089 return status; 2090 } 2091 2092 /* 2093 * (Re)start the DSP 2094 */ 2095 static int dsp_set_run_state(struct hda_codec *codec) 2096 { 2097 unsigned int dbg_ctrl_reg; 2098 unsigned int halt_state; 2099 int err; 2100 2101 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg); 2102 if (err < 0) 2103 return err; 2104 2105 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >> 2106 DSP_DBGCNTL_STATE_LOBIT; 2107 2108 if (halt_state != 0) { 2109 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) & 2110 DSP_DBGCNTL_SS_MASK); 2111 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2112 dbg_ctrl_reg); 2113 if (err < 0) 2114 return err; 2115 2116 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) & 2117 DSP_DBGCNTL_EXEC_MASK; 2118 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2119 dbg_ctrl_reg); 2120 if (err < 0) 2121 return err; 2122 } 2123 2124 return 0; 2125 } 2126 2127 /* 2128 * Reset the DSP 2129 */ 2130 static int dsp_reset(struct hda_codec *codec) 2131 { 2132 unsigned int res; 2133 int retry = 20; 2134 2135 codec_dbg(codec, "dsp_reset\n"); 2136 do { 2137 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0); 2138 retry--; 2139 } while (res == -EIO && retry); 2140 2141 if (!retry) { 2142 codec_dbg(codec, "dsp_reset timeout\n"); 2143 return -EIO; 2144 } 2145 2146 return 0; 2147 } 2148 2149 /* 2150 * Convert chip address to DSP address 2151 */ 2152 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx, 2153 bool *code, bool *yram) 2154 { 2155 *code = *yram = false; 2156 2157 if (UC_RANGE(chip_addx, 1)) { 2158 *code = true; 2159 return UC_OFF(chip_addx); 2160 } else if (X_RANGE_ALL(chip_addx, 1)) { 2161 return X_OFF(chip_addx); 2162 } else if (Y_RANGE_ALL(chip_addx, 1)) { 2163 *yram = true; 2164 return Y_OFF(chip_addx); 2165 } 2166 2167 return INVALID_CHIP_ADDRESS; 2168 } 2169 2170 /* 2171 * Check if the DSP DMA is active 2172 */ 2173 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan) 2174 { 2175 unsigned int dma_chnlstart_reg; 2176 2177 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg); 2178 2179 return ((dma_chnlstart_reg & (1 << 2180 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0); 2181 } 2182 2183 static int dsp_dma_setup_common(struct hda_codec *codec, 2184 unsigned int chip_addx, 2185 unsigned int dma_chan, 2186 unsigned int port_map_mask, 2187 bool ovly) 2188 { 2189 int status = 0; 2190 unsigned int chnl_prop; 2191 unsigned int dsp_addx; 2192 unsigned int active; 2193 bool code, yram; 2194 2195 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n"); 2196 2197 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) { 2198 codec_dbg(codec, "dma chan num invalid\n"); 2199 return -EINVAL; 2200 } 2201 2202 if (dsp_is_dma_active(codec, dma_chan)) { 2203 codec_dbg(codec, "dma already active\n"); 2204 return -EBUSY; 2205 } 2206 2207 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2208 2209 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2210 codec_dbg(codec, "invalid chip addr\n"); 2211 return -ENXIO; 2212 } 2213 2214 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK; 2215 active = 0; 2216 2217 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n"); 2218 2219 if (ovly) { 2220 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET, 2221 &chnl_prop); 2222 2223 if (status < 0) { 2224 codec_dbg(codec, "read CHNLPROP Reg fail\n"); 2225 return status; 2226 } 2227 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n"); 2228 } 2229 2230 if (!code) 2231 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2232 else 2233 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2234 2235 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan)); 2236 2237 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop); 2238 if (status < 0) { 2239 codec_dbg(codec, "write CHNLPROP Reg fail\n"); 2240 return status; 2241 } 2242 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n"); 2243 2244 if (ovly) { 2245 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET, 2246 &active); 2247 2248 if (status < 0) { 2249 codec_dbg(codec, "read ACTIVE Reg fail\n"); 2250 return status; 2251 } 2252 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n"); 2253 } 2254 2255 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) & 2256 DSPDMAC_ACTIVE_AAR_MASK; 2257 2258 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active); 2259 if (status < 0) { 2260 codec_dbg(codec, "write ACTIVE Reg fail\n"); 2261 return status; 2262 } 2263 2264 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n"); 2265 2266 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan), 2267 port_map_mask); 2268 if (status < 0) { 2269 codec_dbg(codec, "write AUDCHSEL Reg fail\n"); 2270 return status; 2271 } 2272 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n"); 2273 2274 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan), 2275 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK); 2276 if (status < 0) { 2277 codec_dbg(codec, "write IRQCNT Reg fail\n"); 2278 return status; 2279 } 2280 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n"); 2281 2282 codec_dbg(codec, 2283 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, " 2284 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n", 2285 chip_addx, dsp_addx, dma_chan, 2286 port_map_mask, chnl_prop, active); 2287 2288 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n"); 2289 2290 return 0; 2291 } 2292 2293 /* 2294 * Setup the DSP DMA per-transfer-specific registers 2295 */ 2296 static int dsp_dma_setup(struct hda_codec *codec, 2297 unsigned int chip_addx, 2298 unsigned int count, 2299 unsigned int dma_chan) 2300 { 2301 int status = 0; 2302 bool code, yram; 2303 unsigned int dsp_addx; 2304 unsigned int addr_field; 2305 unsigned int incr_field; 2306 unsigned int base_cnt; 2307 unsigned int cur_cnt; 2308 unsigned int dma_cfg = 0; 2309 unsigned int adr_ofs = 0; 2310 unsigned int xfr_cnt = 0; 2311 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT - 2312 DSPDMAC_XFRCNT_BCNT_LOBIT + 1); 2313 2314 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n"); 2315 2316 if (count > max_dma_count) { 2317 codec_dbg(codec, "count too big\n"); 2318 return -EINVAL; 2319 } 2320 2321 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2322 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2323 codec_dbg(codec, "invalid chip addr\n"); 2324 return -ENXIO; 2325 } 2326 2327 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n"); 2328 2329 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT; 2330 incr_field = 0; 2331 2332 if (!code) { 2333 addr_field <<= 1; 2334 if (yram) 2335 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT); 2336 2337 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT); 2338 } 2339 2340 dma_cfg = addr_field + incr_field; 2341 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan), 2342 dma_cfg); 2343 if (status < 0) { 2344 codec_dbg(codec, "write DMACFG Reg fail\n"); 2345 return status; 2346 } 2347 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n"); 2348 2349 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT + 2350 (code ? 0 : 1)); 2351 2352 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan), 2353 adr_ofs); 2354 if (status < 0) { 2355 codec_dbg(codec, "write DSPADROFS Reg fail\n"); 2356 return status; 2357 } 2358 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n"); 2359 2360 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT; 2361 2362 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT; 2363 2364 xfr_cnt = base_cnt | cur_cnt; 2365 2366 status = chipio_write(codec, 2367 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt); 2368 if (status < 0) { 2369 codec_dbg(codec, "write XFRCNT Reg fail\n"); 2370 return status; 2371 } 2372 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n"); 2373 2374 codec_dbg(codec, 2375 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, " 2376 "ADROFS=0x%x, XFRCNT=0x%x\n", 2377 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt); 2378 2379 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n"); 2380 2381 return 0; 2382 } 2383 2384 /* 2385 * Start the DSP DMA 2386 */ 2387 static int dsp_dma_start(struct hda_codec *codec, 2388 unsigned int dma_chan, bool ovly) 2389 { 2390 unsigned int reg = 0; 2391 int status = 0; 2392 2393 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n"); 2394 2395 if (ovly) { 2396 status = chipio_read(codec, 2397 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2398 2399 if (status < 0) { 2400 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2401 return status; 2402 } 2403 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n"); 2404 2405 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2406 DSPDMAC_CHNLSTART_DIS_MASK); 2407 } 2408 2409 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2410 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT))); 2411 if (status < 0) { 2412 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2413 return status; 2414 } 2415 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n"); 2416 2417 return status; 2418 } 2419 2420 /* 2421 * Stop the DSP DMA 2422 */ 2423 static int dsp_dma_stop(struct hda_codec *codec, 2424 unsigned int dma_chan, bool ovly) 2425 { 2426 unsigned int reg = 0; 2427 int status = 0; 2428 2429 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n"); 2430 2431 if (ovly) { 2432 status = chipio_read(codec, 2433 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2434 2435 if (status < 0) { 2436 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2437 return status; 2438 } 2439 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n"); 2440 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2441 DSPDMAC_CHNLSTART_DIS_MASK); 2442 } 2443 2444 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2445 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT))); 2446 if (status < 0) { 2447 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2448 return status; 2449 } 2450 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n"); 2451 2452 return status; 2453 } 2454 2455 /** 2456 * Allocate router ports 2457 * 2458 * @codec: the HDA codec 2459 * @num_chans: number of channels in the stream 2460 * @ports_per_channel: number of ports per channel 2461 * @start_device: start device 2462 * @port_map: pointer to the port list to hold the allocated ports 2463 * 2464 * Returns zero or a negative error code. 2465 */ 2466 static int dsp_allocate_router_ports(struct hda_codec *codec, 2467 unsigned int num_chans, 2468 unsigned int ports_per_channel, 2469 unsigned int start_device, 2470 unsigned int *port_map) 2471 { 2472 int status = 0; 2473 int res; 2474 u8 val; 2475 2476 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2477 if (status < 0) 2478 return status; 2479 2480 val = start_device << 6; 2481 val |= (ports_per_channel - 1) << 4; 2482 val |= num_chans - 1; 2483 2484 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2485 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET, 2486 val); 2487 2488 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2489 VENDOR_CHIPIO_PORT_ALLOC_SET, 2490 MEM_CONNID_DSP); 2491 2492 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2493 if (status < 0) 2494 return status; 2495 2496 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 2497 VENDOR_CHIPIO_PORT_ALLOC_GET, 0); 2498 2499 *port_map = res; 2500 2501 return (res < 0) ? res : 0; 2502 } 2503 2504 /* 2505 * Free router ports 2506 */ 2507 static int dsp_free_router_ports(struct hda_codec *codec) 2508 { 2509 int status = 0; 2510 2511 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2512 if (status < 0) 2513 return status; 2514 2515 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2516 VENDOR_CHIPIO_PORT_FREE_SET, 2517 MEM_CONNID_DSP); 2518 2519 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2520 2521 return status; 2522 } 2523 2524 /* 2525 * Allocate DSP ports for the download stream 2526 */ 2527 static int dsp_allocate_ports(struct hda_codec *codec, 2528 unsigned int num_chans, 2529 unsigned int rate_multi, unsigned int *port_map) 2530 { 2531 int status; 2532 2533 codec_dbg(codec, " dsp_allocate_ports() -- begin\n"); 2534 2535 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2536 codec_dbg(codec, "bad rate multiple\n"); 2537 return -EINVAL; 2538 } 2539 2540 status = dsp_allocate_router_ports(codec, num_chans, 2541 rate_multi, 0, port_map); 2542 2543 codec_dbg(codec, " dsp_allocate_ports() -- complete\n"); 2544 2545 return status; 2546 } 2547 2548 static int dsp_allocate_ports_format(struct hda_codec *codec, 2549 const unsigned short fmt, 2550 unsigned int *port_map) 2551 { 2552 int status; 2553 unsigned int num_chans; 2554 2555 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1; 2556 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1; 2557 unsigned int rate_multi = sample_rate_mul / sample_rate_div; 2558 2559 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2560 codec_dbg(codec, "bad rate multiple\n"); 2561 return -EINVAL; 2562 } 2563 2564 num_chans = get_hdafmt_chs(fmt) + 1; 2565 2566 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map); 2567 2568 return status; 2569 } 2570 2571 /* 2572 * free DSP ports 2573 */ 2574 static int dsp_free_ports(struct hda_codec *codec) 2575 { 2576 int status; 2577 2578 codec_dbg(codec, " dsp_free_ports() -- begin\n"); 2579 2580 status = dsp_free_router_ports(codec); 2581 if (status < 0) { 2582 codec_dbg(codec, "free router ports fail\n"); 2583 return status; 2584 } 2585 codec_dbg(codec, " dsp_free_ports() -- complete\n"); 2586 2587 return status; 2588 } 2589 2590 /* 2591 * HDA DMA engine stuffs for DSP code download 2592 */ 2593 struct dma_engine { 2594 struct hda_codec *codec; 2595 unsigned short m_converter_format; 2596 struct snd_dma_buffer *dmab; 2597 unsigned int buf_size; 2598 }; 2599 2600 2601 enum dma_state { 2602 DMA_STATE_STOP = 0, 2603 DMA_STATE_RUN = 1 2604 }; 2605 2606 static int dma_convert_to_hda_format(struct hda_codec *codec, 2607 unsigned int sample_rate, 2608 unsigned short channels, 2609 unsigned short *hda_format) 2610 { 2611 unsigned int format_val; 2612 2613 format_val = snd_hdac_calc_stream_format(sample_rate, 2614 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0); 2615 2616 if (hda_format) 2617 *hda_format = (unsigned short)format_val; 2618 2619 return 0; 2620 } 2621 2622 /* 2623 * Reset DMA for DSP download 2624 */ 2625 static int dma_reset(struct dma_engine *dma) 2626 { 2627 struct hda_codec *codec = dma->codec; 2628 struct ca0132_spec *spec = codec->spec; 2629 int status; 2630 2631 if (dma->dmab->area) 2632 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab); 2633 2634 status = snd_hda_codec_load_dsp_prepare(codec, 2635 dma->m_converter_format, 2636 dma->buf_size, 2637 dma->dmab); 2638 if (status < 0) 2639 return status; 2640 spec->dsp_stream_id = status; 2641 return 0; 2642 } 2643 2644 static int dma_set_state(struct dma_engine *dma, enum dma_state state) 2645 { 2646 bool cmd; 2647 2648 switch (state) { 2649 case DMA_STATE_STOP: 2650 cmd = false; 2651 break; 2652 case DMA_STATE_RUN: 2653 cmd = true; 2654 break; 2655 default: 2656 return 0; 2657 } 2658 2659 snd_hda_codec_load_dsp_trigger(dma->codec, cmd); 2660 return 0; 2661 } 2662 2663 static unsigned int dma_get_buffer_size(struct dma_engine *dma) 2664 { 2665 return dma->dmab->bytes; 2666 } 2667 2668 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma) 2669 { 2670 return dma->dmab->area; 2671 } 2672 2673 static int dma_xfer(struct dma_engine *dma, 2674 const unsigned int *data, 2675 unsigned int count) 2676 { 2677 memcpy(dma->dmab->area, data, count); 2678 return 0; 2679 } 2680 2681 static void dma_get_converter_format( 2682 struct dma_engine *dma, 2683 unsigned short *format) 2684 { 2685 if (format) 2686 *format = dma->m_converter_format; 2687 } 2688 2689 static unsigned int dma_get_stream_id(struct dma_engine *dma) 2690 { 2691 struct ca0132_spec *spec = dma->codec->spec; 2692 2693 return spec->dsp_stream_id; 2694 } 2695 2696 struct dsp_image_seg { 2697 u32 magic; 2698 u32 chip_addr; 2699 u32 count; 2700 u32 data[0]; 2701 }; 2702 2703 static const u32 g_magic_value = 0x4c46584d; 2704 static const u32 g_chip_addr_magic_value = 0xFFFFFF01; 2705 2706 static bool is_valid(const struct dsp_image_seg *p) 2707 { 2708 return p->magic == g_magic_value; 2709 } 2710 2711 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p) 2712 { 2713 return g_chip_addr_magic_value == p->chip_addr; 2714 } 2715 2716 static bool is_last(const struct dsp_image_seg *p) 2717 { 2718 return p->count == 0; 2719 } 2720 2721 static size_t dsp_sizeof(const struct dsp_image_seg *p) 2722 { 2723 return struct_size(p, data, p->count); 2724 } 2725 2726 static const struct dsp_image_seg *get_next_seg_ptr( 2727 const struct dsp_image_seg *p) 2728 { 2729 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p)); 2730 } 2731 2732 /* 2733 * CA0132 chip DSP transfer stuffs. For DSP download. 2734 */ 2735 #define INVALID_DMA_CHANNEL (~0U) 2736 2737 /* 2738 * Program a list of address/data pairs via the ChipIO widget. 2739 * The segment data is in the format of successive pairs of words. 2740 * These are repeated as indicated by the segment's count field. 2741 */ 2742 static int dspxfr_hci_write(struct hda_codec *codec, 2743 const struct dsp_image_seg *fls) 2744 { 2745 int status; 2746 const u32 *data; 2747 unsigned int count; 2748 2749 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) { 2750 codec_dbg(codec, "hci_write invalid params\n"); 2751 return -EINVAL; 2752 } 2753 2754 count = fls->count; 2755 data = (u32 *)(fls->data); 2756 while (count >= 2) { 2757 status = chipio_write(codec, data[0], data[1]); 2758 if (status < 0) { 2759 codec_dbg(codec, "hci_write chipio failed\n"); 2760 return status; 2761 } 2762 count -= 2; 2763 data += 2; 2764 } 2765 return 0; 2766 } 2767 2768 /** 2769 * Write a block of data into DSP code or data RAM using pre-allocated 2770 * DMA engine. 2771 * 2772 * @codec: the HDA codec 2773 * @fls: pointer to a fast load image 2774 * @reloc: Relocation address for loading single-segment overlays, or 0 for 2775 * no relocation 2776 * @dma_engine: pointer to DMA engine to be used for DSP download 2777 * @dma_chan: The number of DMA channels used for DSP download 2778 * @port_map_mask: port mapping 2779 * @ovly: TRUE if overlay format is required 2780 * 2781 * Returns zero or a negative error code. 2782 */ 2783 static int dspxfr_one_seg(struct hda_codec *codec, 2784 const struct dsp_image_seg *fls, 2785 unsigned int reloc, 2786 struct dma_engine *dma_engine, 2787 unsigned int dma_chan, 2788 unsigned int port_map_mask, 2789 bool ovly) 2790 { 2791 int status = 0; 2792 bool comm_dma_setup_done = false; 2793 const unsigned int *data; 2794 unsigned int chip_addx; 2795 unsigned int words_to_write; 2796 unsigned int buffer_size_words; 2797 unsigned char *buffer_addx; 2798 unsigned short hda_format; 2799 unsigned int sample_rate_div; 2800 unsigned int sample_rate_mul; 2801 unsigned int num_chans; 2802 unsigned int hda_frame_size_words; 2803 unsigned int remainder_words; 2804 const u32 *data_remainder; 2805 u32 chip_addx_remainder; 2806 unsigned int run_size_words; 2807 const struct dsp_image_seg *hci_write = NULL; 2808 unsigned long timeout; 2809 bool dma_active; 2810 2811 if (fls == NULL) 2812 return -EINVAL; 2813 if (is_hci_prog_list_seg(fls)) { 2814 hci_write = fls; 2815 fls = get_next_seg_ptr(fls); 2816 } 2817 2818 if (hci_write && (!fls || is_last(fls))) { 2819 codec_dbg(codec, "hci_write\n"); 2820 return dspxfr_hci_write(codec, hci_write); 2821 } 2822 2823 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) { 2824 codec_dbg(codec, "Invalid Params\n"); 2825 return -EINVAL; 2826 } 2827 2828 data = fls->data; 2829 chip_addx = fls->chip_addr, 2830 words_to_write = fls->count; 2831 2832 if (!words_to_write) 2833 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0; 2834 if (reloc) 2835 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2); 2836 2837 if (!UC_RANGE(chip_addx, words_to_write) && 2838 !X_RANGE_ALL(chip_addx, words_to_write) && 2839 !Y_RANGE_ALL(chip_addx, words_to_write)) { 2840 codec_dbg(codec, "Invalid chip_addx Params\n"); 2841 return -EINVAL; 2842 } 2843 2844 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) / 2845 sizeof(u32); 2846 2847 buffer_addx = dma_get_buffer_addr(dma_engine); 2848 2849 if (buffer_addx == NULL) { 2850 codec_dbg(codec, "dma_engine buffer NULL\n"); 2851 return -EINVAL; 2852 } 2853 2854 dma_get_converter_format(dma_engine, &hda_format); 2855 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1; 2856 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1; 2857 num_chans = get_hdafmt_chs(hda_format) + 1; 2858 2859 hda_frame_size_words = ((sample_rate_div == 0) ? 0 : 2860 (num_chans * sample_rate_mul / sample_rate_div)); 2861 2862 if (hda_frame_size_words == 0) { 2863 codec_dbg(codec, "frmsz zero\n"); 2864 return -EINVAL; 2865 } 2866 2867 buffer_size_words = min(buffer_size_words, 2868 (unsigned int)(UC_RANGE(chip_addx, 1) ? 2869 65536 : 32768)); 2870 buffer_size_words -= buffer_size_words % hda_frame_size_words; 2871 codec_dbg(codec, 2872 "chpadr=0x%08x frmsz=%u nchan=%u " 2873 "rate_mul=%u div=%u bufsz=%u\n", 2874 chip_addx, hda_frame_size_words, num_chans, 2875 sample_rate_mul, sample_rate_div, buffer_size_words); 2876 2877 if (buffer_size_words < hda_frame_size_words) { 2878 codec_dbg(codec, "dspxfr_one_seg:failed\n"); 2879 return -EINVAL; 2880 } 2881 2882 remainder_words = words_to_write % hda_frame_size_words; 2883 data_remainder = data; 2884 chip_addx_remainder = chip_addx; 2885 2886 data += remainder_words; 2887 chip_addx += remainder_words*sizeof(u32); 2888 words_to_write -= remainder_words; 2889 2890 while (words_to_write != 0) { 2891 run_size_words = min(buffer_size_words, words_to_write); 2892 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n", 2893 words_to_write, run_size_words, remainder_words); 2894 dma_xfer(dma_engine, data, run_size_words*sizeof(u32)); 2895 if (!comm_dma_setup_done) { 2896 status = dsp_dma_stop(codec, dma_chan, ovly); 2897 if (status < 0) 2898 return status; 2899 status = dsp_dma_setup_common(codec, chip_addx, 2900 dma_chan, port_map_mask, ovly); 2901 if (status < 0) 2902 return status; 2903 comm_dma_setup_done = true; 2904 } 2905 2906 status = dsp_dma_setup(codec, chip_addx, 2907 run_size_words, dma_chan); 2908 if (status < 0) 2909 return status; 2910 status = dsp_dma_start(codec, dma_chan, ovly); 2911 if (status < 0) 2912 return status; 2913 if (!dsp_is_dma_active(codec, dma_chan)) { 2914 codec_dbg(codec, "dspxfr:DMA did not start\n"); 2915 return -EIO; 2916 } 2917 status = dma_set_state(dma_engine, DMA_STATE_RUN); 2918 if (status < 0) 2919 return status; 2920 if (remainder_words != 0) { 2921 status = chipio_write_multiple(codec, 2922 chip_addx_remainder, 2923 data_remainder, 2924 remainder_words); 2925 if (status < 0) 2926 return status; 2927 remainder_words = 0; 2928 } 2929 if (hci_write) { 2930 status = dspxfr_hci_write(codec, hci_write); 2931 if (status < 0) 2932 return status; 2933 hci_write = NULL; 2934 } 2935 2936 timeout = jiffies + msecs_to_jiffies(2000); 2937 do { 2938 dma_active = dsp_is_dma_active(codec, dma_chan); 2939 if (!dma_active) 2940 break; 2941 msleep(20); 2942 } while (time_before(jiffies, timeout)); 2943 if (dma_active) 2944 break; 2945 2946 codec_dbg(codec, "+++++ DMA complete\n"); 2947 dma_set_state(dma_engine, DMA_STATE_STOP); 2948 status = dma_reset(dma_engine); 2949 2950 if (status < 0) 2951 return status; 2952 2953 data += run_size_words; 2954 chip_addx += run_size_words*sizeof(u32); 2955 words_to_write -= run_size_words; 2956 } 2957 2958 if (remainder_words != 0) { 2959 status = chipio_write_multiple(codec, chip_addx_remainder, 2960 data_remainder, remainder_words); 2961 } 2962 2963 return status; 2964 } 2965 2966 /** 2967 * Write the entire DSP image of a DSP code/data overlay to DSP memories 2968 * 2969 * @codec: the HDA codec 2970 * @fls_data: pointer to a fast load image 2971 * @reloc: Relocation address for loading single-segment overlays, or 0 for 2972 * no relocation 2973 * @sample_rate: sampling rate of the stream used for DSP download 2974 * @channels: channels of the stream used for DSP download 2975 * @ovly: TRUE if overlay format is required 2976 * 2977 * Returns zero or a negative error code. 2978 */ 2979 static int dspxfr_image(struct hda_codec *codec, 2980 const struct dsp_image_seg *fls_data, 2981 unsigned int reloc, 2982 unsigned int sample_rate, 2983 unsigned short channels, 2984 bool ovly) 2985 { 2986 struct ca0132_spec *spec = codec->spec; 2987 int status; 2988 unsigned short hda_format = 0; 2989 unsigned int response; 2990 unsigned char stream_id = 0; 2991 struct dma_engine *dma_engine; 2992 unsigned int dma_chan; 2993 unsigned int port_map_mask; 2994 2995 if (fls_data == NULL) 2996 return -EINVAL; 2997 2998 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL); 2999 if (!dma_engine) 3000 return -ENOMEM; 3001 3002 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL); 3003 if (!dma_engine->dmab) { 3004 kfree(dma_engine); 3005 return -ENOMEM; 3006 } 3007 3008 dma_engine->codec = codec; 3009 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format); 3010 dma_engine->m_converter_format = hda_format; 3011 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY : 3012 DSP_DMA_WRITE_BUFLEN_INIT) * 2; 3013 3014 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0; 3015 3016 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL, 3017 hda_format, &response); 3018 3019 if (status < 0) { 3020 codec_dbg(codec, "set converter format fail\n"); 3021 goto exit; 3022 } 3023 3024 status = snd_hda_codec_load_dsp_prepare(codec, 3025 dma_engine->m_converter_format, 3026 dma_engine->buf_size, 3027 dma_engine->dmab); 3028 if (status < 0) 3029 goto exit; 3030 spec->dsp_stream_id = status; 3031 3032 if (ovly) { 3033 status = dspio_alloc_dma_chan(codec, &dma_chan); 3034 if (status < 0) { 3035 codec_dbg(codec, "alloc dmachan fail\n"); 3036 dma_chan = INVALID_DMA_CHANNEL; 3037 goto exit; 3038 } 3039 } 3040 3041 port_map_mask = 0; 3042 status = dsp_allocate_ports_format(codec, hda_format, 3043 &port_map_mask); 3044 if (status < 0) { 3045 codec_dbg(codec, "alloc ports fail\n"); 3046 goto exit; 3047 } 3048 3049 stream_id = dma_get_stream_id(dma_engine); 3050 status = codec_set_converter_stream_channel(codec, 3051 WIDGET_CHIP_CTRL, stream_id, 0, &response); 3052 if (status < 0) { 3053 codec_dbg(codec, "set stream chan fail\n"); 3054 goto exit; 3055 } 3056 3057 while ((fls_data != NULL) && !is_last(fls_data)) { 3058 if (!is_valid(fls_data)) { 3059 codec_dbg(codec, "FLS check fail\n"); 3060 status = -EINVAL; 3061 goto exit; 3062 } 3063 status = dspxfr_one_seg(codec, fls_data, reloc, 3064 dma_engine, dma_chan, 3065 port_map_mask, ovly); 3066 if (status < 0) 3067 break; 3068 3069 if (is_hci_prog_list_seg(fls_data)) 3070 fls_data = get_next_seg_ptr(fls_data); 3071 3072 if ((fls_data != NULL) && !is_last(fls_data)) 3073 fls_data = get_next_seg_ptr(fls_data); 3074 } 3075 3076 if (port_map_mask != 0) 3077 status = dsp_free_ports(codec); 3078 3079 if (status < 0) 3080 goto exit; 3081 3082 status = codec_set_converter_stream_channel(codec, 3083 WIDGET_CHIP_CTRL, 0, 0, &response); 3084 3085 exit: 3086 if (ovly && (dma_chan != INVALID_DMA_CHANNEL)) 3087 dspio_free_dma_chan(codec, dma_chan); 3088 3089 if (dma_engine->dmab->area) 3090 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab); 3091 kfree(dma_engine->dmab); 3092 kfree(dma_engine); 3093 3094 return status; 3095 } 3096 3097 /* 3098 * CA0132 DSP download stuffs. 3099 */ 3100 static void dspload_post_setup(struct hda_codec *codec) 3101 { 3102 struct ca0132_spec *spec = codec->spec; 3103 codec_dbg(codec, "---- dspload_post_setup ------\n"); 3104 if (!ca0132_use_alt_functions(spec)) { 3105 /*set DSP speaker to 2.0 configuration*/ 3106 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080); 3107 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000); 3108 3109 /*update write pointer*/ 3110 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002); 3111 } 3112 } 3113 3114 /** 3115 * dspload_image - Download DSP from a DSP Image Fast Load structure. 3116 * 3117 * @codec: the HDA codec 3118 * @fls: pointer to a fast load image 3119 * @ovly: TRUE if overlay format is required 3120 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3121 * no relocation 3122 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE 3123 * @router_chans: number of audio router channels to be allocated (0 means use 3124 * internal defaults; max is 32) 3125 * 3126 * Download DSP from a DSP Image Fast Load structure. This structure is a 3127 * linear, non-constant sized element array of structures, each of which 3128 * contain the count of the data to be loaded, the data itself, and the 3129 * corresponding starting chip address of the starting data location. 3130 * Returns zero or a negative error code. 3131 */ 3132 static int dspload_image(struct hda_codec *codec, 3133 const struct dsp_image_seg *fls, 3134 bool ovly, 3135 unsigned int reloc, 3136 bool autostart, 3137 int router_chans) 3138 { 3139 int status = 0; 3140 unsigned int sample_rate; 3141 unsigned short channels; 3142 3143 codec_dbg(codec, "---- dspload_image begin ------\n"); 3144 if (router_chans == 0) { 3145 if (!ovly) 3146 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS; 3147 else 3148 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS; 3149 } 3150 3151 sample_rate = 48000; 3152 channels = (unsigned short)router_chans; 3153 3154 while (channels > 16) { 3155 sample_rate *= 2; 3156 channels /= 2; 3157 } 3158 3159 do { 3160 codec_dbg(codec, "Ready to program DMA\n"); 3161 if (!ovly) 3162 status = dsp_reset(codec); 3163 3164 if (status < 0) 3165 break; 3166 3167 codec_dbg(codec, "dsp_reset() complete\n"); 3168 status = dspxfr_image(codec, fls, reloc, sample_rate, channels, 3169 ovly); 3170 3171 if (status < 0) 3172 break; 3173 3174 codec_dbg(codec, "dspxfr_image() complete\n"); 3175 if (autostart && !ovly) { 3176 dspload_post_setup(codec); 3177 status = dsp_set_run_state(codec); 3178 } 3179 3180 codec_dbg(codec, "LOAD FINISHED\n"); 3181 } while (0); 3182 3183 return status; 3184 } 3185 3186 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 3187 static bool dspload_is_loaded(struct hda_codec *codec) 3188 { 3189 unsigned int data = 0; 3190 int status = 0; 3191 3192 status = chipio_read(codec, 0x40004, &data); 3193 if ((status < 0) || (data != 1)) 3194 return false; 3195 3196 return true; 3197 } 3198 #else 3199 #define dspload_is_loaded(codec) false 3200 #endif 3201 3202 static bool dspload_wait_loaded(struct hda_codec *codec) 3203 { 3204 unsigned long timeout = jiffies + msecs_to_jiffies(2000); 3205 3206 do { 3207 if (dspload_is_loaded(codec)) { 3208 codec_info(codec, "ca0132 DSP downloaded and running\n"); 3209 return true; 3210 } 3211 msleep(20); 3212 } while (time_before(jiffies, timeout)); 3213 3214 codec_err(codec, "ca0132 failed to download DSP\n"); 3215 return false; 3216 } 3217 3218 /* 3219 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e 3220 * based cards, and has a second mmio region, region2, that's used for special 3221 * commands. 3222 */ 3223 3224 /* 3225 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5) 3226 * the mmio address 0x320 is used to set GPIO pins. The format for the data 3227 * The first eight bits are just the number of the pin. So far, I've only seen 3228 * this number go to 7. 3229 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value 3230 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and 3231 * then off to send that bit. 3232 */ 3233 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin, 3234 bool enable) 3235 { 3236 struct ca0132_spec *spec = codec->spec; 3237 unsigned short gpio_data; 3238 3239 gpio_data = gpio_pin & 0xF; 3240 gpio_data |= ((enable << 8) & 0x100); 3241 3242 writew(gpio_data, spec->mem_base + 0x320); 3243 } 3244 3245 /* 3246 * Special pci region2 commands that are only used by the AE-5. They follow 3247 * a set format, and require reads at certain points to seemingly 'clear' 3248 * the response data. My first tests didn't do these reads, and would cause 3249 * the card to get locked up until the memory was read. These commands 3250 * seem to work with three distinct values that I've taken to calling group, 3251 * target-id, and value. 3252 */ 3253 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group, 3254 unsigned int target, unsigned int value) 3255 { 3256 struct ca0132_spec *spec = codec->spec; 3257 unsigned int write_val; 3258 3259 writel(0x0000007e, spec->mem_base + 0x210); 3260 readl(spec->mem_base + 0x210); 3261 writel(0x0000005a, spec->mem_base + 0x210); 3262 readl(spec->mem_base + 0x210); 3263 readl(spec->mem_base + 0x210); 3264 3265 writel(0x00800005, spec->mem_base + 0x20c); 3266 writel(group, spec->mem_base + 0x804); 3267 3268 writel(0x00800005, spec->mem_base + 0x20c); 3269 write_val = (target & 0xff); 3270 write_val |= (value << 8); 3271 3272 3273 writel(write_val, spec->mem_base + 0x204); 3274 /* 3275 * Need delay here or else it goes too fast and works inconsistently. 3276 */ 3277 msleep(20); 3278 3279 readl(spec->mem_base + 0x860); 3280 readl(spec->mem_base + 0x854); 3281 readl(spec->mem_base + 0x840); 3282 3283 writel(0x00800004, spec->mem_base + 0x20c); 3284 writel(0x00000000, spec->mem_base + 0x210); 3285 readl(spec->mem_base + 0x210); 3286 readl(spec->mem_base + 0x210); 3287 } 3288 3289 /* 3290 * This second type of command is used for setting the sound filter type. 3291 */ 3292 static void ca0113_mmio_command_set_type2(struct hda_codec *codec, 3293 unsigned int group, unsigned int target, unsigned int value) 3294 { 3295 struct ca0132_spec *spec = codec->spec; 3296 unsigned int write_val; 3297 3298 writel(0x0000007e, spec->mem_base + 0x210); 3299 readl(spec->mem_base + 0x210); 3300 writel(0x0000005a, spec->mem_base + 0x210); 3301 readl(spec->mem_base + 0x210); 3302 readl(spec->mem_base + 0x210); 3303 3304 writel(0x00800003, spec->mem_base + 0x20c); 3305 writel(group, spec->mem_base + 0x804); 3306 3307 writel(0x00800005, spec->mem_base + 0x20c); 3308 write_val = (target & 0xff); 3309 write_val |= (value << 8); 3310 3311 3312 writel(write_val, spec->mem_base + 0x204); 3313 msleep(20); 3314 readl(spec->mem_base + 0x860); 3315 readl(spec->mem_base + 0x854); 3316 readl(spec->mem_base + 0x840); 3317 3318 writel(0x00800004, spec->mem_base + 0x20c); 3319 writel(0x00000000, spec->mem_base + 0x210); 3320 readl(spec->mem_base + 0x210); 3321 readl(spec->mem_base + 0x210); 3322 } 3323 3324 /* 3325 * Setup GPIO for the other variants of Core3D. 3326 */ 3327 3328 /* 3329 * Sets up the GPIO pins so that they are discoverable. If this isn't done, 3330 * the card shows as having no GPIO pins. 3331 */ 3332 static void ca0132_gpio_init(struct hda_codec *codec) 3333 { 3334 struct ca0132_spec *spec = codec->spec; 3335 3336 switch (ca0132_quirk(spec)) { 3337 case QUIRK_SBZ: 3338 case QUIRK_AE5: 3339 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3340 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 3341 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23); 3342 break; 3343 case QUIRK_R3DI: 3344 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3345 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B); 3346 break; 3347 default: 3348 break; 3349 } 3350 3351 } 3352 3353 /* Sets the GPIO for audio output. */ 3354 static void ca0132_gpio_setup(struct hda_codec *codec) 3355 { 3356 struct ca0132_spec *spec = codec->spec; 3357 3358 switch (ca0132_quirk(spec)) { 3359 case QUIRK_SBZ: 3360 snd_hda_codec_write(codec, 0x01, 0, 3361 AC_VERB_SET_GPIO_DIRECTION, 0x07); 3362 snd_hda_codec_write(codec, 0x01, 0, 3363 AC_VERB_SET_GPIO_MASK, 0x07); 3364 snd_hda_codec_write(codec, 0x01, 0, 3365 AC_VERB_SET_GPIO_DATA, 0x04); 3366 snd_hda_codec_write(codec, 0x01, 0, 3367 AC_VERB_SET_GPIO_DATA, 0x06); 3368 break; 3369 case QUIRK_R3DI: 3370 snd_hda_codec_write(codec, 0x01, 0, 3371 AC_VERB_SET_GPIO_DIRECTION, 0x1E); 3372 snd_hda_codec_write(codec, 0x01, 0, 3373 AC_VERB_SET_GPIO_MASK, 0x1F); 3374 snd_hda_codec_write(codec, 0x01, 0, 3375 AC_VERB_SET_GPIO_DATA, 0x0C); 3376 break; 3377 default: 3378 break; 3379 } 3380 } 3381 3382 /* 3383 * GPIO control functions for the Recon3D integrated. 3384 */ 3385 3386 enum r3di_gpio_bit { 3387 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */ 3388 R3DI_MIC_SELECT_BIT = 1, 3389 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */ 3390 R3DI_OUT_SELECT_BIT = 2, 3391 /* 3392 * I dunno what this actually does, but it stays on until the dsp 3393 * is downloaded. 3394 */ 3395 R3DI_GPIO_DSP_DOWNLOADING = 3, 3396 /* 3397 * Same as above, no clue what it does, but it comes on after the dsp 3398 * is downloaded. 3399 */ 3400 R3DI_GPIO_DSP_DOWNLOADED = 4 3401 }; 3402 3403 enum r3di_mic_select { 3404 /* Set GPIO bit 1 to 0 for rear mic */ 3405 R3DI_REAR_MIC = 0, 3406 /* Set GPIO bit 1 to 1 for front microphone*/ 3407 R3DI_FRONT_MIC = 1 3408 }; 3409 3410 enum r3di_out_select { 3411 /* Set GPIO bit 2 to 0 for headphone */ 3412 R3DI_HEADPHONE_OUT = 0, 3413 /* Set GPIO bit 2 to 1 for speaker */ 3414 R3DI_LINE_OUT = 1 3415 }; 3416 enum r3di_dsp_status { 3417 /* Set GPIO bit 3 to 1 until DSP is downloaded */ 3418 R3DI_DSP_DOWNLOADING = 0, 3419 /* Set GPIO bit 4 to 1 once DSP is downloaded */ 3420 R3DI_DSP_DOWNLOADED = 1 3421 }; 3422 3423 3424 static void r3di_gpio_mic_set(struct hda_codec *codec, 3425 enum r3di_mic_select cur_mic) 3426 { 3427 unsigned int cur_gpio; 3428 3429 /* Get the current GPIO Data setup */ 3430 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3431 3432 switch (cur_mic) { 3433 case R3DI_REAR_MIC: 3434 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT); 3435 break; 3436 case R3DI_FRONT_MIC: 3437 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT); 3438 break; 3439 } 3440 snd_hda_codec_write(codec, codec->core.afg, 0, 3441 AC_VERB_SET_GPIO_DATA, cur_gpio); 3442 } 3443 3444 static void r3di_gpio_out_set(struct hda_codec *codec, 3445 enum r3di_out_select cur_out) 3446 { 3447 unsigned int cur_gpio; 3448 3449 /* Get the current GPIO Data setup */ 3450 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3451 3452 switch (cur_out) { 3453 case R3DI_HEADPHONE_OUT: 3454 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT); 3455 break; 3456 case R3DI_LINE_OUT: 3457 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT); 3458 break; 3459 } 3460 snd_hda_codec_write(codec, codec->core.afg, 0, 3461 AC_VERB_SET_GPIO_DATA, cur_gpio); 3462 } 3463 3464 static void r3di_gpio_dsp_status_set(struct hda_codec *codec, 3465 enum r3di_dsp_status dsp_status) 3466 { 3467 unsigned int cur_gpio; 3468 3469 /* Get the current GPIO Data setup */ 3470 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3471 3472 switch (dsp_status) { 3473 case R3DI_DSP_DOWNLOADING: 3474 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING); 3475 snd_hda_codec_write(codec, codec->core.afg, 0, 3476 AC_VERB_SET_GPIO_DATA, cur_gpio); 3477 break; 3478 case R3DI_DSP_DOWNLOADED: 3479 /* Set DOWNLOADING bit to 0. */ 3480 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING); 3481 3482 snd_hda_codec_write(codec, codec->core.afg, 0, 3483 AC_VERB_SET_GPIO_DATA, cur_gpio); 3484 3485 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED); 3486 break; 3487 } 3488 3489 snd_hda_codec_write(codec, codec->core.afg, 0, 3490 AC_VERB_SET_GPIO_DATA, cur_gpio); 3491 } 3492 3493 /* 3494 * PCM callbacks 3495 */ 3496 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3497 struct hda_codec *codec, 3498 unsigned int stream_tag, 3499 unsigned int format, 3500 struct snd_pcm_substream *substream) 3501 { 3502 struct ca0132_spec *spec = codec->spec; 3503 3504 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format); 3505 3506 return 0; 3507 } 3508 3509 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3510 struct hda_codec *codec, 3511 struct snd_pcm_substream *substream) 3512 { 3513 struct ca0132_spec *spec = codec->spec; 3514 3515 if (spec->dsp_state == DSP_DOWNLOADING) 3516 return 0; 3517 3518 /*If Playback effects are on, allow stream some time to flush 3519 *effects tail*/ 3520 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 3521 msleep(50); 3522 3523 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 3524 3525 return 0; 3526 } 3527 3528 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info, 3529 struct hda_codec *codec, 3530 struct snd_pcm_substream *substream) 3531 { 3532 struct ca0132_spec *spec = codec->spec; 3533 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY; 3534 struct snd_pcm_runtime *runtime = substream->runtime; 3535 3536 if (spec->dsp_state != DSP_DOWNLOADED) 3537 return 0; 3538 3539 /* Add latency if playback enhancement and either effect is enabled. */ 3540 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) { 3541 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) || 3542 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID])) 3543 latency += DSP_PLAY_ENHANCEMENT_LATENCY; 3544 } 3545 3546 /* Applying Speaker EQ adds latency as well. */ 3547 if (spec->cur_out_type == SPEAKER_OUT) 3548 latency += DSP_SPEAKER_OUT_LATENCY; 3549 3550 return (latency * runtime->rate) / 1000; 3551 } 3552 3553 /* 3554 * Digital out 3555 */ 3556 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo, 3557 struct hda_codec *codec, 3558 struct snd_pcm_substream *substream) 3559 { 3560 struct ca0132_spec *spec = codec->spec; 3561 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3562 } 3563 3564 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3565 struct hda_codec *codec, 3566 unsigned int stream_tag, 3567 unsigned int format, 3568 struct snd_pcm_substream *substream) 3569 { 3570 struct ca0132_spec *spec = codec->spec; 3571 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3572 stream_tag, format, substream); 3573 } 3574 3575 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3576 struct hda_codec *codec, 3577 struct snd_pcm_substream *substream) 3578 { 3579 struct ca0132_spec *spec = codec->spec; 3580 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout); 3581 } 3582 3583 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo, 3584 struct hda_codec *codec, 3585 struct snd_pcm_substream *substream) 3586 { 3587 struct ca0132_spec *spec = codec->spec; 3588 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3589 } 3590 3591 /* 3592 * Analog capture 3593 */ 3594 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo, 3595 struct hda_codec *codec, 3596 unsigned int stream_tag, 3597 unsigned int format, 3598 struct snd_pcm_substream *substream) 3599 { 3600 snd_hda_codec_setup_stream(codec, hinfo->nid, 3601 stream_tag, 0, format); 3602 3603 return 0; 3604 } 3605 3606 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo, 3607 struct hda_codec *codec, 3608 struct snd_pcm_substream *substream) 3609 { 3610 struct ca0132_spec *spec = codec->spec; 3611 3612 if (spec->dsp_state == DSP_DOWNLOADING) 3613 return 0; 3614 3615 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 3616 return 0; 3617 } 3618 3619 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info, 3620 struct hda_codec *codec, 3621 struct snd_pcm_substream *substream) 3622 { 3623 struct ca0132_spec *spec = codec->spec; 3624 unsigned int latency = DSP_CAPTURE_INIT_LATENCY; 3625 struct snd_pcm_runtime *runtime = substream->runtime; 3626 3627 if (spec->dsp_state != DSP_DOWNLOADED) 3628 return 0; 3629 3630 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 3631 latency += DSP_CRYSTAL_VOICE_LATENCY; 3632 3633 return (latency * runtime->rate) / 1000; 3634 } 3635 3636 /* 3637 * Controls stuffs. 3638 */ 3639 3640 /* 3641 * Mixer controls helpers. 3642 */ 3643 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \ 3644 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3645 .name = xname, \ 3646 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3647 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3648 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 3649 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 3650 .info = ca0132_volume_info, \ 3651 .get = ca0132_volume_get, \ 3652 .put = ca0132_volume_put, \ 3653 .tlv = { .c = ca0132_volume_tlv }, \ 3654 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3655 3656 /* 3657 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the 3658 * volume put, which is used for setting the DSP volume. This was done because 3659 * the ca0132 functions were taking too much time and causing lag. 3660 */ 3661 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \ 3662 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3663 .name = xname, \ 3664 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3665 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3666 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 3667 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 3668 .info = snd_hda_mixer_amp_volume_info, \ 3669 .get = snd_hda_mixer_amp_volume_get, \ 3670 .put = ca0132_alt_volume_put, \ 3671 .tlv = { .c = snd_hda_mixer_amp_tlv }, \ 3672 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3673 3674 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \ 3675 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3676 .name = xname, \ 3677 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3678 .info = snd_hda_mixer_amp_switch_info, \ 3679 .get = ca0132_switch_get, \ 3680 .put = ca0132_switch_put, \ 3681 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3682 3683 /* stereo */ 3684 #define CA0132_CODEC_VOL(xname, nid, dir) \ 3685 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir) 3686 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \ 3687 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir) 3688 #define CA0132_CODEC_MUTE(xname, nid, dir) \ 3689 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir) 3690 3691 /* lookup tables */ 3692 /* 3693 * Lookup table with decibel values for the DSP. When volume is changed in 3694 * Windows, the DSP is also sent the dB value in floating point. In Windows, 3695 * these values have decimal points, probably because the Windows driver 3696 * actually uses floating point. We can't here, so I made a lookup table of 3697 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the 3698 * DAC's, and 9 is the maximum. 3699 */ 3700 static const unsigned int float_vol_db_lookup[] = { 3701 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000, 3702 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000, 3703 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000, 3704 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000, 3705 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000, 3706 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000, 3707 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000, 3708 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000, 3709 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000, 3710 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000, 3711 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000, 3712 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 3713 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 3714 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 3715 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 3716 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 3717 0x40C00000, 0x40E00000, 0x41000000, 0x41100000 3718 }; 3719 3720 /* 3721 * This table counts from float 0 to 1 in increments of .01, which is 3722 * useful for a few different sliders. 3723 */ 3724 static const unsigned int float_zero_to_one_lookup[] = { 3725 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 3726 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 3727 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 3728 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 3729 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 3730 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 3731 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 3732 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 3733 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 3734 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 3735 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 3736 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 3737 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 3738 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 3739 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 3740 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 3741 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 3742 }; 3743 3744 /* 3745 * This table counts from float 10 to 1000, which is the range of the x-bass 3746 * crossover slider in Windows. 3747 */ 3748 static const unsigned int float_xbass_xover_lookup[] = { 3749 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000, 3750 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000, 3751 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000, 3752 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000, 3753 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000, 3754 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000, 3755 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000, 3756 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000, 3757 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000, 3758 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000, 3759 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000, 3760 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000, 3761 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000, 3762 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000, 3763 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000, 3764 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000, 3765 0x44728000, 0x44750000, 0x44778000, 0x447A0000 3766 }; 3767 3768 /* The following are for tuning of products */ 3769 #ifdef ENABLE_TUNING_CONTROLS 3770 3771 static unsigned int voice_focus_vals_lookup[] = { 3772 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000, 3773 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000, 3774 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000, 3775 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000, 3776 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000, 3777 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000, 3778 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000, 3779 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000, 3780 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000, 3781 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000, 3782 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000, 3783 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000, 3784 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000, 3785 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000, 3786 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000, 3787 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000, 3788 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000, 3789 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000, 3790 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000, 3791 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000, 3792 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000, 3793 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000, 3794 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000, 3795 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000, 3796 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000, 3797 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000, 3798 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000 3799 }; 3800 3801 static unsigned int mic_svm_vals_lookup[] = { 3802 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 3803 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 3804 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 3805 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 3806 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 3807 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 3808 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 3809 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 3810 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 3811 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 3812 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 3813 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 3814 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 3815 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 3816 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 3817 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 3818 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 3819 }; 3820 3821 static unsigned int equalizer_vals_lookup[] = { 3822 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 3823 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 3824 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 3825 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 3826 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 3827 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000, 3828 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000, 3829 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 3830 0x41C00000 3831 }; 3832 3833 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid, 3834 unsigned int *lookup, int idx) 3835 { 3836 int i = 0; 3837 3838 for (i = 0; i < TUNING_CTLS_COUNT; i++) 3839 if (nid == ca0132_tuning_ctls[i].nid) 3840 break; 3841 3842 snd_hda_power_up(codec); 3843 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20, 3844 ca0132_tuning_ctls[i].req, 3845 &(lookup[idx]), sizeof(unsigned int)); 3846 snd_hda_power_down(codec); 3847 3848 return 1; 3849 } 3850 3851 static int tuning_ctl_get(struct snd_kcontrol *kcontrol, 3852 struct snd_ctl_elem_value *ucontrol) 3853 { 3854 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3855 struct ca0132_spec *spec = codec->spec; 3856 hda_nid_t nid = get_amp_nid(kcontrol); 3857 long *valp = ucontrol->value.integer.value; 3858 int idx = nid - TUNING_CTL_START_NID; 3859 3860 *valp = spec->cur_ctl_vals[idx]; 3861 return 0; 3862 } 3863 3864 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol, 3865 struct snd_ctl_elem_info *uinfo) 3866 { 3867 int chs = get_amp_channels(kcontrol); 3868 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3869 uinfo->count = chs == 3 ? 2 : 1; 3870 uinfo->value.integer.min = 20; 3871 uinfo->value.integer.max = 180; 3872 uinfo->value.integer.step = 1; 3873 3874 return 0; 3875 } 3876 3877 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol, 3878 struct snd_ctl_elem_value *ucontrol) 3879 { 3880 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3881 struct ca0132_spec *spec = codec->spec; 3882 hda_nid_t nid = get_amp_nid(kcontrol); 3883 long *valp = ucontrol->value.integer.value; 3884 int idx; 3885 3886 idx = nid - TUNING_CTL_START_NID; 3887 /* any change? */ 3888 if (spec->cur_ctl_vals[idx] == *valp) 3889 return 0; 3890 3891 spec->cur_ctl_vals[idx] = *valp; 3892 3893 idx = *valp - 20; 3894 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx); 3895 3896 return 1; 3897 } 3898 3899 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol, 3900 struct snd_ctl_elem_info *uinfo) 3901 { 3902 int chs = get_amp_channels(kcontrol); 3903 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3904 uinfo->count = chs == 3 ? 2 : 1; 3905 uinfo->value.integer.min = 0; 3906 uinfo->value.integer.max = 100; 3907 uinfo->value.integer.step = 1; 3908 3909 return 0; 3910 } 3911 3912 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol, 3913 struct snd_ctl_elem_value *ucontrol) 3914 { 3915 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3916 struct ca0132_spec *spec = codec->spec; 3917 hda_nid_t nid = get_amp_nid(kcontrol); 3918 long *valp = ucontrol->value.integer.value; 3919 int idx; 3920 3921 idx = nid - TUNING_CTL_START_NID; 3922 /* any change? */ 3923 if (spec->cur_ctl_vals[idx] == *valp) 3924 return 0; 3925 3926 spec->cur_ctl_vals[idx] = *valp; 3927 3928 idx = *valp; 3929 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx); 3930 3931 return 0; 3932 } 3933 3934 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol, 3935 struct snd_ctl_elem_info *uinfo) 3936 { 3937 int chs = get_amp_channels(kcontrol); 3938 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3939 uinfo->count = chs == 3 ? 2 : 1; 3940 uinfo->value.integer.min = 0; 3941 uinfo->value.integer.max = 48; 3942 uinfo->value.integer.step = 1; 3943 3944 return 0; 3945 } 3946 3947 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol, 3948 struct snd_ctl_elem_value *ucontrol) 3949 { 3950 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3951 struct ca0132_spec *spec = codec->spec; 3952 hda_nid_t nid = get_amp_nid(kcontrol); 3953 long *valp = ucontrol->value.integer.value; 3954 int idx; 3955 3956 idx = nid - TUNING_CTL_START_NID; 3957 /* any change? */ 3958 if (spec->cur_ctl_vals[idx] == *valp) 3959 return 0; 3960 3961 spec->cur_ctl_vals[idx] = *valp; 3962 3963 idx = *valp; 3964 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx); 3965 3966 return 1; 3967 } 3968 3969 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0); 3970 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0); 3971 3972 static int add_tuning_control(struct hda_codec *codec, 3973 hda_nid_t pnid, hda_nid_t nid, 3974 const char *name, int dir) 3975 { 3976 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 3977 int type = dir ? HDA_INPUT : HDA_OUTPUT; 3978 struct snd_kcontrol_new knew = 3979 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 3980 3981 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 3982 SNDRV_CTL_ELEM_ACCESS_TLV_READ; 3983 knew.tlv.c = 0; 3984 knew.tlv.p = 0; 3985 switch (pnid) { 3986 case VOICE_FOCUS: 3987 knew.info = voice_focus_ctl_info; 3988 knew.get = tuning_ctl_get; 3989 knew.put = voice_focus_ctl_put; 3990 knew.tlv.p = voice_focus_db_scale; 3991 break; 3992 case MIC_SVM: 3993 knew.info = mic_svm_ctl_info; 3994 knew.get = tuning_ctl_get; 3995 knew.put = mic_svm_ctl_put; 3996 break; 3997 case EQUALIZER: 3998 knew.info = equalizer_ctl_info; 3999 knew.get = tuning_ctl_get; 4000 knew.put = equalizer_ctl_put; 4001 knew.tlv.p = eq_db_scale; 4002 break; 4003 default: 4004 return 0; 4005 } 4006 knew.private_value = 4007 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 4008 sprintf(namestr, "%s %s Volume", name, dirstr[dir]); 4009 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 4010 } 4011 4012 static int add_tuning_ctls(struct hda_codec *codec) 4013 { 4014 int i; 4015 int err; 4016 4017 for (i = 0; i < TUNING_CTLS_COUNT; i++) { 4018 err = add_tuning_control(codec, 4019 ca0132_tuning_ctls[i].parent_nid, 4020 ca0132_tuning_ctls[i].nid, 4021 ca0132_tuning_ctls[i].name, 4022 ca0132_tuning_ctls[i].direct); 4023 if (err < 0) 4024 return err; 4025 } 4026 4027 return 0; 4028 } 4029 4030 static void ca0132_init_tuning_defaults(struct hda_codec *codec) 4031 { 4032 struct ca0132_spec *spec = codec->spec; 4033 int i; 4034 4035 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */ 4036 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10; 4037 /* SVM level defaults to 0.74. */ 4038 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74; 4039 4040 /* EQ defaults to 0dB. */ 4041 for (i = 2; i < TUNING_CTLS_COUNT; i++) 4042 spec->cur_ctl_vals[i] = 24; 4043 } 4044 #endif /*ENABLE_TUNING_CONTROLS*/ 4045 4046 /* 4047 * Select the active output. 4048 * If autodetect is enabled, output will be selected based on jack detection. 4049 * If jack inserted, headphone will be selected, else built-in speakers 4050 * If autodetect is disabled, output will be selected based on selection. 4051 */ 4052 static int ca0132_select_out(struct hda_codec *codec) 4053 { 4054 struct ca0132_spec *spec = codec->spec; 4055 unsigned int pin_ctl; 4056 int jack_present; 4057 int auto_jack; 4058 unsigned int tmp; 4059 int err; 4060 4061 codec_dbg(codec, "ca0132_select_out\n"); 4062 4063 snd_hda_power_up_pm(codec); 4064 4065 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4066 4067 if (auto_jack) 4068 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp); 4069 else 4070 jack_present = 4071 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID]; 4072 4073 if (jack_present) 4074 spec->cur_out_type = HEADPHONE_OUT; 4075 else 4076 spec->cur_out_type = SPEAKER_OUT; 4077 4078 if (spec->cur_out_type == SPEAKER_OUT) { 4079 codec_dbg(codec, "ca0132_select_out speaker\n"); 4080 /*speaker out config*/ 4081 tmp = FLOAT_ONE; 4082 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4083 if (err < 0) 4084 goto exit; 4085 /*enable speaker EQ*/ 4086 tmp = FLOAT_ONE; 4087 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4088 if (err < 0) 4089 goto exit; 4090 4091 /* Setup EAPD */ 4092 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4093 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4094 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4095 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4096 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4097 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4098 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4099 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4100 4101 /* disable headphone node */ 4102 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4103 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4104 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4105 pin_ctl & ~PIN_HP); 4106 /* enable speaker node */ 4107 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4108 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4109 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4110 pin_ctl | PIN_OUT); 4111 } else { 4112 codec_dbg(codec, "ca0132_select_out hp\n"); 4113 /*headphone out config*/ 4114 tmp = FLOAT_ZERO; 4115 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4116 if (err < 0) 4117 goto exit; 4118 /*disable speaker EQ*/ 4119 tmp = FLOAT_ZERO; 4120 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4121 if (err < 0) 4122 goto exit; 4123 4124 /* Setup EAPD */ 4125 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4126 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4127 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4128 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4129 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4130 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4131 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4132 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4133 4134 /* disable speaker*/ 4135 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4136 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4137 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4138 pin_ctl & ~PIN_HP); 4139 /* enable headphone*/ 4140 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4141 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4142 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4143 pin_ctl | PIN_HP); 4144 } 4145 4146 exit: 4147 snd_hda_power_down_pm(codec); 4148 4149 return err < 0 ? err : 0; 4150 } 4151 4152 static int ae5_headphone_gain_set(struct hda_codec *codec, long val); 4153 static int zxr_headphone_gain_set(struct hda_codec *codec, long val); 4154 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val); 4155 4156 static void ae5_mmio_select_out(struct hda_codec *codec) 4157 { 4158 struct ca0132_spec *spec = codec->spec; 4159 unsigned int i; 4160 4161 for (i = 0; i < AE5_CA0113_OUT_SET_COMMANDS; i++) 4162 ca0113_mmio_command_set(codec, 4163 ae5_ca0113_output_presets[spec->cur_out_type].group[i], 4164 ae5_ca0113_output_presets[spec->cur_out_type].target[i], 4165 ae5_ca0113_output_presets[spec->cur_out_type].vals[i]); 4166 } 4167 4168 /* 4169 * These are the commands needed to setup output on each of the different card 4170 * types. 4171 */ 4172 static void ca0132_alt_select_out_quirk_handler(struct hda_codec *codec) 4173 { 4174 struct ca0132_spec *spec = codec->spec; 4175 unsigned int tmp; 4176 4177 switch (spec->cur_out_type) { 4178 case SPEAKER_OUT: 4179 switch (ca0132_quirk(spec)) { 4180 case QUIRK_SBZ: 4181 ca0113_mmio_gpio_set(codec, 7, false); 4182 ca0113_mmio_gpio_set(codec, 4, true); 4183 ca0113_mmio_gpio_set(codec, 1, true); 4184 chipio_set_control_param(codec, 0x0d, 0x18); 4185 break; 4186 case QUIRK_ZXR: 4187 ca0113_mmio_gpio_set(codec, 2, true); 4188 ca0113_mmio_gpio_set(codec, 3, true); 4189 ca0113_mmio_gpio_set(codec, 5, false); 4190 zxr_headphone_gain_set(codec, 0); 4191 chipio_set_control_param(codec, 0x0d, 0x24); 4192 break; 4193 case QUIRK_R3DI: 4194 chipio_set_control_param(codec, 0x0d, 0x24); 4195 r3di_gpio_out_set(codec, R3DI_LINE_OUT); 4196 break; 4197 case QUIRK_R3D: 4198 chipio_set_control_param(codec, 0x0d, 0x24); 4199 ca0113_mmio_gpio_set(codec, 1, true); 4200 break; 4201 case QUIRK_AE5: 4202 ae5_mmio_select_out(codec); 4203 ae5_headphone_gain_set(codec, 2); 4204 tmp = FLOAT_ZERO; 4205 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 4206 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 4207 chipio_set_control_param(codec, 0x0d, 0xa4); 4208 chipio_write(codec, 0x18b03c, 0x00000012); 4209 break; 4210 default: 4211 break; 4212 } 4213 break; 4214 case HEADPHONE_OUT: 4215 switch (ca0132_quirk(spec)) { 4216 case QUIRK_SBZ: 4217 ca0113_mmio_gpio_set(codec, 7, true); 4218 ca0113_mmio_gpio_set(codec, 4, true); 4219 ca0113_mmio_gpio_set(codec, 1, false); 4220 chipio_set_control_param(codec, 0x0d, 0x12); 4221 break; 4222 case QUIRK_ZXR: 4223 ca0113_mmio_gpio_set(codec, 2, false); 4224 ca0113_mmio_gpio_set(codec, 3, false); 4225 ca0113_mmio_gpio_set(codec, 5, true); 4226 zxr_headphone_gain_set(codec, spec->zxr_gain_set); 4227 chipio_set_control_param(codec, 0x0d, 0x21); 4228 break; 4229 case QUIRK_R3DI: 4230 chipio_set_control_param(codec, 0x0d, 0x21); 4231 r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT); 4232 break; 4233 case QUIRK_R3D: 4234 chipio_set_control_param(codec, 0x0d, 0x21); 4235 ca0113_mmio_gpio_set(codec, 0x1, false); 4236 break; 4237 case QUIRK_AE5: 4238 ae5_mmio_select_out(codec); 4239 ae5_headphone_gain_set(codec, 4240 spec->ae5_headphone_gain_val); 4241 tmp = FLOAT_ONE; 4242 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 4243 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 4244 chipio_set_control_param(codec, 0x0d, 0xa1); 4245 chipio_write(codec, 0x18b03c, 0x00000012); 4246 break; 4247 default: 4248 break; 4249 } 4250 break; 4251 case SURROUND_OUT: 4252 switch (ca0132_quirk(spec)) { 4253 case QUIRK_SBZ: 4254 ca0113_mmio_gpio_set(codec, 7, false); 4255 ca0113_mmio_gpio_set(codec, 4, true); 4256 ca0113_mmio_gpio_set(codec, 1, true); 4257 chipio_set_control_param(codec, 0x0d, 0x18); 4258 break; 4259 case QUIRK_ZXR: 4260 ca0113_mmio_gpio_set(codec, 2, true); 4261 ca0113_mmio_gpio_set(codec, 3, true); 4262 ca0113_mmio_gpio_set(codec, 5, false); 4263 zxr_headphone_gain_set(codec, 0); 4264 chipio_set_control_param(codec, 0x0d, 0x24); 4265 break; 4266 case QUIRK_R3DI: 4267 chipio_set_control_param(codec, 0x0d, 0x24); 4268 r3di_gpio_out_set(codec, R3DI_LINE_OUT); 4269 break; 4270 case QUIRK_R3D: 4271 ca0113_mmio_gpio_set(codec, 1, true); 4272 chipio_set_control_param(codec, 0x0d, 0x24); 4273 break; 4274 case QUIRK_AE5: 4275 ae5_mmio_select_out(codec); 4276 ae5_headphone_gain_set(codec, 2); 4277 tmp = FLOAT_ZERO; 4278 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 4279 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 4280 chipio_set_control_param(codec, 0x0d, 0xa4); 4281 chipio_write(codec, 0x18b03c, 0x00000012); 4282 break; 4283 default: 4284 break; 4285 } 4286 break; 4287 } 4288 } 4289 4290 /* 4291 * This function behaves similarly to the ca0132_select_out funciton above, 4292 * except with a few differences. It adds the ability to select the current 4293 * output with an enumerated control "output source" if the auto detect 4294 * mute switch is set to off. If the auto detect mute switch is enabled, it 4295 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection. 4296 * It also adds the ability to auto-detect the front headphone port. The only 4297 * way to select surround is to disable auto detect, and set Surround with the 4298 * enumerated control. 4299 */ 4300 static int ca0132_alt_select_out(struct hda_codec *codec) 4301 { 4302 struct ca0132_spec *spec = codec->spec; 4303 unsigned int pin_ctl; 4304 int jack_present; 4305 int auto_jack; 4306 unsigned int i; 4307 unsigned int tmp; 4308 int err; 4309 /* Default Headphone is rear headphone */ 4310 hda_nid_t headphone_nid = spec->out_pins[1]; 4311 4312 codec_dbg(codec, "%s\n", __func__); 4313 4314 snd_hda_power_up_pm(codec); 4315 4316 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4317 4318 /* 4319 * If headphone rear or front is plugged in, set to headphone. 4320 * If neither is plugged in, set to rear line out. Only if 4321 * hp/speaker auto detect is enabled. 4322 */ 4323 if (auto_jack) { 4324 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) || 4325 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp); 4326 4327 if (jack_present) 4328 spec->cur_out_type = HEADPHONE_OUT; 4329 else 4330 spec->cur_out_type = SPEAKER_OUT; 4331 } else 4332 spec->cur_out_type = spec->out_enum_val; 4333 4334 /* Begin DSP output switch */ 4335 tmp = FLOAT_ONE; 4336 err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp); 4337 if (err < 0) 4338 goto exit; 4339 4340 ca0132_alt_select_out_quirk_handler(codec); 4341 4342 switch (spec->cur_out_type) { 4343 case SPEAKER_OUT: 4344 codec_dbg(codec, "%s speaker\n", __func__); 4345 4346 /* disable headphone node */ 4347 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4348 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4349 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4350 pin_ctl & ~PIN_HP); 4351 /* enable line-out node */ 4352 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4353 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4354 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4355 pin_ctl | PIN_OUT); 4356 /* Enable EAPD */ 4357 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4358 AC_VERB_SET_EAPD_BTLENABLE, 0x01); 4359 4360 /* If PlayEnhancement is enabled, set different source */ 4361 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4362 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE); 4363 else 4364 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT); 4365 break; 4366 case HEADPHONE_OUT: 4367 codec_dbg(codec, "%s hp\n", __func__); 4368 4369 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4370 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4371 4372 /* disable speaker*/ 4373 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4374 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4375 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4376 pin_ctl & ~PIN_HP); 4377 4378 /* enable headphone, either front or rear */ 4379 4380 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp)) 4381 headphone_nid = spec->out_pins[2]; 4382 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp)) 4383 headphone_nid = spec->out_pins[1]; 4384 4385 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0, 4386 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4387 snd_hda_set_pin_ctl(codec, headphone_nid, 4388 pin_ctl | PIN_HP); 4389 4390 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4391 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE); 4392 else 4393 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO); 4394 break; 4395 case SURROUND_OUT: 4396 codec_dbg(codec, "%s surround\n", __func__); 4397 4398 /* enable line out node */ 4399 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4400 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4401 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4402 pin_ctl | PIN_OUT); 4403 /* Disable headphone out */ 4404 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4405 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4406 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4407 pin_ctl & ~PIN_HP); 4408 /* Enable EAPD on line out */ 4409 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4410 AC_VERB_SET_EAPD_BTLENABLE, 0x01); 4411 /* enable center/lfe out node */ 4412 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0, 4413 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4414 snd_hda_set_pin_ctl(codec, spec->out_pins[2], 4415 pin_ctl | PIN_OUT); 4416 /* Now set rear surround node as out. */ 4417 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0, 4418 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4419 snd_hda_set_pin_ctl(codec, spec->out_pins[3], 4420 pin_ctl | PIN_OUT); 4421 4422 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT); 4423 break; 4424 } 4425 /* 4426 * Surround always sets it's scp command to req 0x04 to FLOAT_EIGHT. 4427 * With this set though, X_BASS cannot be enabled. So, if we have OutFX 4428 * enabled, we need to make sure X_BASS is off, otherwise everything 4429 * sounds all muffled. Running ca0132_effects_set with X_BASS as the 4430 * effect should sort this out. 4431 */ 4432 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4433 ca0132_effects_set(codec, X_BASS, 4434 spec->effects_switch[X_BASS - EFFECT_START_NID]); 4435 4436 /* run through the output dsp commands for the selected output. */ 4437 for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) { 4438 err = dspio_set_uint_param(codec, 4439 alt_out_presets[spec->cur_out_type].mids[i], 4440 alt_out_presets[spec->cur_out_type].reqs[i], 4441 alt_out_presets[spec->cur_out_type].vals[i]); 4442 4443 if (err < 0) 4444 goto exit; 4445 } 4446 4447 exit: 4448 snd_hda_power_down_pm(codec); 4449 4450 return err < 0 ? err : 0; 4451 } 4452 4453 static void ca0132_unsol_hp_delayed(struct work_struct *work) 4454 { 4455 struct ca0132_spec *spec = container_of( 4456 to_delayed_work(work), struct ca0132_spec, unsol_hp_work); 4457 struct hda_jack_tbl *jack; 4458 4459 if (ca0132_use_alt_functions(spec)) 4460 ca0132_alt_select_out(spec->codec); 4461 else 4462 ca0132_select_out(spec->codec); 4463 4464 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp); 4465 if (jack) { 4466 jack->block_report = 0; 4467 snd_hda_jack_report_sync(spec->codec); 4468 } 4469 } 4470 4471 static void ca0132_set_dmic(struct hda_codec *codec, int enable); 4472 static int ca0132_mic_boost_set(struct hda_codec *codec, long val); 4473 static void resume_mic1(struct hda_codec *codec, unsigned int oldval); 4474 static int stop_mic1(struct hda_codec *codec); 4475 static int ca0132_cvoice_switch_set(struct hda_codec *codec); 4476 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val); 4477 4478 /* 4479 * Select the active VIP source 4480 */ 4481 static int ca0132_set_vipsource(struct hda_codec *codec, int val) 4482 { 4483 struct ca0132_spec *spec = codec->spec; 4484 unsigned int tmp; 4485 4486 if (spec->dsp_state != DSP_DOWNLOADED) 4487 return 0; 4488 4489 /* if CrystalVoice if off, vipsource should be 0 */ 4490 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4491 (val == 0)) { 4492 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4493 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4494 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4495 if (spec->cur_mic_type == DIGITAL_MIC) 4496 tmp = FLOAT_TWO; 4497 else 4498 tmp = FLOAT_ONE; 4499 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4500 tmp = FLOAT_ZERO; 4501 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4502 } else { 4503 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4504 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4505 if (spec->cur_mic_type == DIGITAL_MIC) 4506 tmp = FLOAT_TWO; 4507 else 4508 tmp = FLOAT_ONE; 4509 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4510 tmp = FLOAT_ONE; 4511 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4512 msleep(20); 4513 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4514 } 4515 4516 return 1; 4517 } 4518 4519 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val) 4520 { 4521 struct ca0132_spec *spec = codec->spec; 4522 unsigned int tmp; 4523 4524 if (spec->dsp_state != DSP_DOWNLOADED) 4525 return 0; 4526 4527 codec_dbg(codec, "%s\n", __func__); 4528 4529 chipio_set_stream_control(codec, 0x03, 0); 4530 chipio_set_stream_control(codec, 0x04, 0); 4531 4532 /* if CrystalVoice is off, vipsource should be 0 */ 4533 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4534 (val == 0) || spec->in_enum_val == REAR_LINE_IN) { 4535 codec_dbg(codec, "%s: off.", __func__); 4536 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4537 4538 tmp = FLOAT_ZERO; 4539 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4540 4541 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4542 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4543 if (ca0132_quirk(spec) == QUIRK_R3DI) 4544 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4545 4546 4547 if (spec->in_enum_val == REAR_LINE_IN) 4548 tmp = FLOAT_ZERO; 4549 else { 4550 if (ca0132_quirk(spec) == QUIRK_SBZ) 4551 tmp = FLOAT_THREE; 4552 else 4553 tmp = FLOAT_ONE; 4554 } 4555 4556 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4557 4558 } else { 4559 codec_dbg(codec, "%s: on.", __func__); 4560 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4561 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4562 if (ca0132_quirk(spec) == QUIRK_R3DI) 4563 chipio_set_conn_rate(codec, 0x0F, SR_16_000); 4564 4565 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID]) 4566 tmp = FLOAT_TWO; 4567 else 4568 tmp = FLOAT_ONE; 4569 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4570 4571 tmp = FLOAT_ONE; 4572 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4573 4574 msleep(20); 4575 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4576 } 4577 4578 chipio_set_stream_control(codec, 0x03, 1); 4579 chipio_set_stream_control(codec, 0x04, 1); 4580 4581 return 1; 4582 } 4583 4584 /* 4585 * Select the active microphone. 4586 * If autodetect is enabled, mic will be selected based on jack detection. 4587 * If jack inserted, ext.mic will be selected, else built-in mic 4588 * If autodetect is disabled, mic will be selected based on selection. 4589 */ 4590 static int ca0132_select_mic(struct hda_codec *codec) 4591 { 4592 struct ca0132_spec *spec = codec->spec; 4593 int jack_present; 4594 int auto_jack; 4595 4596 codec_dbg(codec, "ca0132_select_mic\n"); 4597 4598 snd_hda_power_up_pm(codec); 4599 4600 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 4601 4602 if (auto_jack) 4603 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1); 4604 else 4605 jack_present = 4606 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID]; 4607 4608 if (jack_present) 4609 spec->cur_mic_type = LINE_MIC_IN; 4610 else 4611 spec->cur_mic_type = DIGITAL_MIC; 4612 4613 if (spec->cur_mic_type == DIGITAL_MIC) { 4614 /* enable digital Mic */ 4615 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000); 4616 ca0132_set_dmic(codec, 1); 4617 ca0132_mic_boost_set(codec, 0); 4618 /* set voice focus */ 4619 ca0132_effects_set(codec, VOICE_FOCUS, 4620 spec->effects_switch 4621 [VOICE_FOCUS - EFFECT_START_NID]); 4622 } else { 4623 /* disable digital Mic */ 4624 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000); 4625 ca0132_set_dmic(codec, 0); 4626 ca0132_mic_boost_set(codec, spec->cur_mic_boost); 4627 /* disable voice focus */ 4628 ca0132_effects_set(codec, VOICE_FOCUS, 0); 4629 } 4630 4631 snd_hda_power_down_pm(codec); 4632 4633 return 0; 4634 } 4635 4636 /* 4637 * Select the active input. 4638 * Mic detection isn't used, because it's kind of pointless on the SBZ. 4639 * The front mic has no jack-detection, so the only way to switch to it 4640 * is to do it manually in alsamixer. 4641 */ 4642 static int ca0132_alt_select_in(struct hda_codec *codec) 4643 { 4644 struct ca0132_spec *spec = codec->spec; 4645 unsigned int tmp; 4646 4647 codec_dbg(codec, "%s\n", __func__); 4648 4649 snd_hda_power_up_pm(codec); 4650 4651 chipio_set_stream_control(codec, 0x03, 0); 4652 chipio_set_stream_control(codec, 0x04, 0); 4653 4654 spec->cur_mic_type = spec->in_enum_val; 4655 4656 switch (spec->cur_mic_type) { 4657 case REAR_MIC: 4658 switch (ca0132_quirk(spec)) { 4659 case QUIRK_SBZ: 4660 case QUIRK_R3D: 4661 ca0113_mmio_gpio_set(codec, 0, false); 4662 tmp = FLOAT_THREE; 4663 break; 4664 case QUIRK_ZXR: 4665 tmp = FLOAT_THREE; 4666 break; 4667 case QUIRK_R3DI: 4668 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 4669 tmp = FLOAT_ONE; 4670 break; 4671 case QUIRK_AE5: 4672 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x00); 4673 tmp = FLOAT_THREE; 4674 break; 4675 default: 4676 tmp = FLOAT_ONE; 4677 break; 4678 } 4679 4680 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4681 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4682 if (ca0132_quirk(spec) == QUIRK_R3DI) 4683 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4684 4685 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4686 4687 chipio_set_stream_control(codec, 0x03, 1); 4688 chipio_set_stream_control(codec, 0x04, 1); 4689 switch (ca0132_quirk(spec)) { 4690 case QUIRK_SBZ: 4691 chipio_write(codec, 0x18B098, 0x0000000C); 4692 chipio_write(codec, 0x18B09C, 0x0000000C); 4693 break; 4694 case QUIRK_ZXR: 4695 chipio_write(codec, 0x18B098, 0x0000000C); 4696 chipio_write(codec, 0x18B09C, 0x000000CC); 4697 break; 4698 case QUIRK_AE5: 4699 chipio_write(codec, 0x18B098, 0x0000000C); 4700 chipio_write(codec, 0x18B09C, 0x0000004C); 4701 break; 4702 default: 4703 break; 4704 } 4705 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 4706 break; 4707 case REAR_LINE_IN: 4708 ca0132_mic_boost_set(codec, 0); 4709 switch (ca0132_quirk(spec)) { 4710 case QUIRK_SBZ: 4711 case QUIRK_R3D: 4712 ca0113_mmio_gpio_set(codec, 0, false); 4713 break; 4714 case QUIRK_R3DI: 4715 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 4716 break; 4717 case QUIRK_AE5: 4718 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x00); 4719 break; 4720 default: 4721 break; 4722 } 4723 4724 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4725 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4726 if (ca0132_quirk(spec) == QUIRK_R3DI) 4727 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4728 4729 tmp = FLOAT_ZERO; 4730 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4731 4732 switch (ca0132_quirk(spec)) { 4733 case QUIRK_SBZ: 4734 case QUIRK_AE5: 4735 chipio_write(codec, 0x18B098, 0x00000000); 4736 chipio_write(codec, 0x18B09C, 0x00000000); 4737 break; 4738 default: 4739 break; 4740 } 4741 chipio_set_stream_control(codec, 0x03, 1); 4742 chipio_set_stream_control(codec, 0x04, 1); 4743 break; 4744 case FRONT_MIC: 4745 switch (ca0132_quirk(spec)) { 4746 case QUIRK_SBZ: 4747 case QUIRK_R3D: 4748 ca0113_mmio_gpio_set(codec, 0, true); 4749 ca0113_mmio_gpio_set(codec, 5, false); 4750 tmp = FLOAT_THREE; 4751 break; 4752 case QUIRK_R3DI: 4753 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC); 4754 tmp = FLOAT_ONE; 4755 break; 4756 case QUIRK_AE5: 4757 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x3f); 4758 tmp = FLOAT_THREE; 4759 break; 4760 default: 4761 tmp = FLOAT_ONE; 4762 break; 4763 } 4764 4765 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4766 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4767 if (ca0132_quirk(spec) == QUIRK_R3DI) 4768 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4769 4770 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4771 4772 chipio_set_stream_control(codec, 0x03, 1); 4773 chipio_set_stream_control(codec, 0x04, 1); 4774 4775 switch (ca0132_quirk(spec)) { 4776 case QUIRK_SBZ: 4777 chipio_write(codec, 0x18B098, 0x0000000C); 4778 chipio_write(codec, 0x18B09C, 0x000000CC); 4779 break; 4780 case QUIRK_AE5: 4781 chipio_write(codec, 0x18B098, 0x0000000C); 4782 chipio_write(codec, 0x18B09C, 0x0000004C); 4783 break; 4784 default: 4785 break; 4786 } 4787 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 4788 break; 4789 } 4790 ca0132_cvoice_switch_set(codec); 4791 4792 snd_hda_power_down_pm(codec); 4793 return 0; 4794 } 4795 4796 /* 4797 * Check if VNODE settings take effect immediately. 4798 */ 4799 static bool ca0132_is_vnode_effective(struct hda_codec *codec, 4800 hda_nid_t vnid, 4801 hda_nid_t *shared_nid) 4802 { 4803 struct ca0132_spec *spec = codec->spec; 4804 hda_nid_t nid; 4805 4806 switch (vnid) { 4807 case VNID_SPK: 4808 nid = spec->shared_out_nid; 4809 break; 4810 case VNID_MIC: 4811 nid = spec->shared_mic_nid; 4812 break; 4813 default: 4814 return false; 4815 } 4816 4817 if (shared_nid) 4818 *shared_nid = nid; 4819 4820 return true; 4821 } 4822 4823 /* 4824 * The following functions are control change helpers. 4825 * They return 0 if no changed. Return 1 if changed. 4826 */ 4827 static int ca0132_voicefx_set(struct hda_codec *codec, int enable) 4828 { 4829 struct ca0132_spec *spec = codec->spec; 4830 unsigned int tmp; 4831 4832 /* based on CrystalVoice state to enable VoiceFX. */ 4833 if (enable) { 4834 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ? 4835 FLOAT_ONE : FLOAT_ZERO; 4836 } else { 4837 tmp = FLOAT_ZERO; 4838 } 4839 4840 dspio_set_uint_param(codec, ca0132_voicefx.mid, 4841 ca0132_voicefx.reqs[0], tmp); 4842 4843 return 1; 4844 } 4845 4846 /* 4847 * Set the effects parameters 4848 */ 4849 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val) 4850 { 4851 struct ca0132_spec *spec = codec->spec; 4852 unsigned int on, tmp; 4853 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 4854 int err = 0; 4855 int idx = nid - EFFECT_START_NID; 4856 4857 if ((idx < 0) || (idx >= num_fx)) 4858 return 0; /* no changed */ 4859 4860 /* for out effect, qualify with PE */ 4861 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) { 4862 /* if PE if off, turn off out effects. */ 4863 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4864 val = 0; 4865 if (spec->cur_out_type == SURROUND_OUT && nid == X_BASS) 4866 val = 0; 4867 } 4868 4869 /* for in effect, qualify with CrystalVoice */ 4870 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) { 4871 /* if CrystalVoice if off, turn off in effects. */ 4872 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 4873 val = 0; 4874 4875 /* Voice Focus applies to 2-ch Mic, Digital Mic */ 4876 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC)) 4877 val = 0; 4878 4879 /* If Voice Focus on SBZ, set to two channel. */ 4880 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec) 4881 && (spec->cur_mic_type != REAR_LINE_IN)) { 4882 if (spec->effects_switch[CRYSTAL_VOICE - 4883 EFFECT_START_NID]) { 4884 4885 if (spec->effects_switch[VOICE_FOCUS - 4886 EFFECT_START_NID]) { 4887 tmp = FLOAT_TWO; 4888 val = 1; 4889 } else 4890 tmp = FLOAT_ONE; 4891 4892 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4893 } 4894 } 4895 /* 4896 * For SBZ noise reduction, there's an extra command 4897 * to module ID 0x47. No clue why. 4898 */ 4899 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec) 4900 && (spec->cur_mic_type != REAR_LINE_IN)) { 4901 if (spec->effects_switch[CRYSTAL_VOICE - 4902 EFFECT_START_NID]) { 4903 if (spec->effects_switch[NOISE_REDUCTION - 4904 EFFECT_START_NID]) 4905 tmp = FLOAT_ONE; 4906 else 4907 tmp = FLOAT_ZERO; 4908 } else 4909 tmp = FLOAT_ZERO; 4910 4911 dspio_set_uint_param(codec, 0x47, 0x00, tmp); 4912 } 4913 4914 /* If rear line in disable effects. */ 4915 if (ca0132_use_alt_functions(spec) && 4916 spec->in_enum_val == REAR_LINE_IN) 4917 val = 0; 4918 } 4919 4920 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n", 4921 nid, val); 4922 4923 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE; 4924 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid, 4925 ca0132_effects[idx].reqs[0], on); 4926 4927 if (err < 0) 4928 return 0; /* no changed */ 4929 4930 return 1; 4931 } 4932 4933 /* 4934 * Turn on/off Playback Enhancements 4935 */ 4936 static int ca0132_pe_switch_set(struct hda_codec *codec) 4937 { 4938 struct ca0132_spec *spec = codec->spec; 4939 hda_nid_t nid; 4940 int i, ret = 0; 4941 4942 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n", 4943 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]); 4944 4945 if (ca0132_use_alt_functions(spec)) 4946 ca0132_alt_select_out(codec); 4947 4948 i = OUT_EFFECT_START_NID - EFFECT_START_NID; 4949 nid = OUT_EFFECT_START_NID; 4950 /* PE affects all out effects */ 4951 for (; nid < OUT_EFFECT_END_NID; nid++, i++) 4952 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 4953 4954 return ret; 4955 } 4956 4957 /* Check if Mic1 is streaming, if so, stop streaming */ 4958 static int stop_mic1(struct hda_codec *codec) 4959 { 4960 struct ca0132_spec *spec = codec->spec; 4961 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0, 4962 AC_VERB_GET_CONV, 0); 4963 if (oldval != 0) 4964 snd_hda_codec_write(codec, spec->adcs[0], 0, 4965 AC_VERB_SET_CHANNEL_STREAMID, 4966 0); 4967 return oldval; 4968 } 4969 4970 /* Resume Mic1 streaming if it was stopped. */ 4971 static void resume_mic1(struct hda_codec *codec, unsigned int oldval) 4972 { 4973 struct ca0132_spec *spec = codec->spec; 4974 /* Restore the previous stream and channel */ 4975 if (oldval != 0) 4976 snd_hda_codec_write(codec, spec->adcs[0], 0, 4977 AC_VERB_SET_CHANNEL_STREAMID, 4978 oldval); 4979 } 4980 4981 /* 4982 * Turn on/off CrystalVoice 4983 */ 4984 static int ca0132_cvoice_switch_set(struct hda_codec *codec) 4985 { 4986 struct ca0132_spec *spec = codec->spec; 4987 hda_nid_t nid; 4988 int i, ret = 0; 4989 unsigned int oldval; 4990 4991 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n", 4992 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]); 4993 4994 i = IN_EFFECT_START_NID - EFFECT_START_NID; 4995 nid = IN_EFFECT_START_NID; 4996 /* CrystalVoice affects all in effects */ 4997 for (; nid < IN_EFFECT_END_NID; nid++, i++) 4998 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 4999 5000 /* including VoiceFX */ 5001 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0)); 5002 5003 /* set correct vipsource */ 5004 oldval = stop_mic1(codec); 5005 if (ca0132_use_alt_functions(spec)) 5006 ret |= ca0132_alt_set_vipsource(codec, 1); 5007 else 5008 ret |= ca0132_set_vipsource(codec, 1); 5009 resume_mic1(codec, oldval); 5010 return ret; 5011 } 5012 5013 static int ca0132_mic_boost_set(struct hda_codec *codec, long val) 5014 { 5015 struct ca0132_spec *spec = codec->spec; 5016 int ret = 0; 5017 5018 if (val) /* on */ 5019 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5020 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3); 5021 else /* off */ 5022 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5023 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0); 5024 5025 return ret; 5026 } 5027 5028 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val) 5029 { 5030 struct ca0132_spec *spec = codec->spec; 5031 int ret = 0; 5032 5033 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5034 HDA_INPUT, 0, HDA_AMP_VOLMASK, val); 5035 return ret; 5036 } 5037 5038 static int ae5_headphone_gain_set(struct hda_codec *codec, long val) 5039 { 5040 unsigned int i; 5041 5042 for (i = 0; i < 4; i++) 5043 ca0113_mmio_command_set(codec, 0x48, 0x11 + i, 5044 ae5_headphone_gain_presets[val].vals[i]); 5045 return 0; 5046 } 5047 5048 /* 5049 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone 5050 * amplifier to handle a 600 ohm load. 5051 */ 5052 static int zxr_headphone_gain_set(struct hda_codec *codec, long val) 5053 { 5054 ca0113_mmio_gpio_set(codec, 1, val); 5055 5056 return 0; 5057 } 5058 5059 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol, 5060 struct snd_ctl_elem_value *ucontrol) 5061 { 5062 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5063 hda_nid_t nid = get_amp_nid(kcontrol); 5064 hda_nid_t shared_nid = 0; 5065 bool effective; 5066 int ret = 0; 5067 struct ca0132_spec *spec = codec->spec; 5068 int auto_jack; 5069 5070 if (nid == VNID_HP_SEL) { 5071 auto_jack = 5072 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 5073 if (!auto_jack) { 5074 if (ca0132_use_alt_functions(spec)) 5075 ca0132_alt_select_out(codec); 5076 else 5077 ca0132_select_out(codec); 5078 } 5079 return 1; 5080 } 5081 5082 if (nid == VNID_AMIC1_SEL) { 5083 auto_jack = 5084 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 5085 if (!auto_jack) 5086 ca0132_select_mic(codec); 5087 return 1; 5088 } 5089 5090 if (nid == VNID_HP_ASEL) { 5091 if (ca0132_use_alt_functions(spec)) 5092 ca0132_alt_select_out(codec); 5093 else 5094 ca0132_select_out(codec); 5095 return 1; 5096 } 5097 5098 if (nid == VNID_AMIC1_ASEL) { 5099 ca0132_select_mic(codec); 5100 return 1; 5101 } 5102 5103 /* if effective conditions, then update hw immediately. */ 5104 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 5105 if (effective) { 5106 int dir = get_amp_direction(kcontrol); 5107 int ch = get_amp_channels(kcontrol); 5108 unsigned long pval; 5109 5110 mutex_lock(&codec->control_mutex); 5111 pval = kcontrol->private_value; 5112 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 5113 0, dir); 5114 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol); 5115 kcontrol->private_value = pval; 5116 mutex_unlock(&codec->control_mutex); 5117 } 5118 5119 return ret; 5120 } 5121 /* End of control change helpers. */ 5122 /* 5123 * Below I've added controls to mess with the effect levels, I've only enabled 5124 * them on the Sound Blaster Z, but they would probably also work on the 5125 * Chromebook. I figured they were probably tuned specifically for it, and left 5126 * out for a reason. 5127 */ 5128 5129 /* Sets DSP effect level from the sliders above the controls */ 5130 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid, 5131 const unsigned int *lookup, int idx) 5132 { 5133 int i = 0; 5134 unsigned int y; 5135 /* 5136 * For X_BASS, req 2 is actually crossover freq instead of 5137 * effect level 5138 */ 5139 if (nid == X_BASS) 5140 y = 2; 5141 else 5142 y = 1; 5143 5144 snd_hda_power_up(codec); 5145 if (nid == XBASS_XOVER) { 5146 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5147 if (ca0132_effects[i].nid == X_BASS) 5148 break; 5149 5150 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5151 ca0132_effects[i].reqs[1], 5152 &(lookup[idx - 1]), sizeof(unsigned int)); 5153 } else { 5154 /* Find the actual effect structure */ 5155 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5156 if (nid == ca0132_effects[i].nid) 5157 break; 5158 5159 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5160 ca0132_effects[i].reqs[y], 5161 &(lookup[idx]), sizeof(unsigned int)); 5162 } 5163 5164 snd_hda_power_down(codec); 5165 5166 return 0; 5167 } 5168 5169 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol, 5170 struct snd_ctl_elem_value *ucontrol) 5171 { 5172 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5173 struct ca0132_spec *spec = codec->spec; 5174 long *valp = ucontrol->value.integer.value; 5175 5176 *valp = spec->xbass_xover_freq; 5177 return 0; 5178 } 5179 5180 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol, 5181 struct snd_ctl_elem_value *ucontrol) 5182 { 5183 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5184 struct ca0132_spec *spec = codec->spec; 5185 hda_nid_t nid = get_amp_nid(kcontrol); 5186 long *valp = ucontrol->value.integer.value; 5187 int idx = nid - OUT_EFFECT_START_NID; 5188 5189 *valp = spec->fx_ctl_val[idx]; 5190 return 0; 5191 } 5192 5193 /* 5194 * The X-bass crossover starts at 10hz, so the min is 1. The 5195 * frequency is set in multiples of 10. 5196 */ 5197 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol, 5198 struct snd_ctl_elem_info *uinfo) 5199 { 5200 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5201 uinfo->count = 1; 5202 uinfo->value.integer.min = 1; 5203 uinfo->value.integer.max = 100; 5204 uinfo->value.integer.step = 1; 5205 5206 return 0; 5207 } 5208 5209 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol, 5210 struct snd_ctl_elem_info *uinfo) 5211 { 5212 int chs = get_amp_channels(kcontrol); 5213 5214 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5215 uinfo->count = chs == 3 ? 2 : 1; 5216 uinfo->value.integer.min = 0; 5217 uinfo->value.integer.max = 100; 5218 uinfo->value.integer.step = 1; 5219 5220 return 0; 5221 } 5222 5223 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol, 5224 struct snd_ctl_elem_value *ucontrol) 5225 { 5226 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5227 struct ca0132_spec *spec = codec->spec; 5228 hda_nid_t nid = get_amp_nid(kcontrol); 5229 long *valp = ucontrol->value.integer.value; 5230 int idx; 5231 5232 /* any change? */ 5233 if (spec->xbass_xover_freq == *valp) 5234 return 0; 5235 5236 spec->xbass_xover_freq = *valp; 5237 5238 idx = *valp; 5239 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx); 5240 5241 return 0; 5242 } 5243 5244 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol, 5245 struct snd_ctl_elem_value *ucontrol) 5246 { 5247 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5248 struct ca0132_spec *spec = codec->spec; 5249 hda_nid_t nid = get_amp_nid(kcontrol); 5250 long *valp = ucontrol->value.integer.value; 5251 int idx; 5252 5253 idx = nid - EFFECT_START_NID; 5254 /* any change? */ 5255 if (spec->fx_ctl_val[idx] == *valp) 5256 return 0; 5257 5258 spec->fx_ctl_val[idx] = *valp; 5259 5260 idx = *valp; 5261 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx); 5262 5263 return 0; 5264 } 5265 5266 5267 /* 5268 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original 5269 * only has off or full 30 dB, and didn't like making a volume slider that has 5270 * traditional 0-100 in alsamixer that goes in big steps. I like enum better. 5271 */ 5272 #define MIC_BOOST_NUM_OF_STEPS 4 5273 #define MIC_BOOST_ENUM_MAX_STRLEN 10 5274 5275 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol, 5276 struct snd_ctl_elem_info *uinfo) 5277 { 5278 char *sfx = "dB"; 5279 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5280 5281 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5282 uinfo->count = 1; 5283 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS; 5284 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS) 5285 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1; 5286 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx); 5287 strcpy(uinfo->value.enumerated.name, namestr); 5288 return 0; 5289 } 5290 5291 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol, 5292 struct snd_ctl_elem_value *ucontrol) 5293 { 5294 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5295 struct ca0132_spec *spec = codec->spec; 5296 5297 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val; 5298 return 0; 5299 } 5300 5301 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol, 5302 struct snd_ctl_elem_value *ucontrol) 5303 { 5304 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5305 struct ca0132_spec *spec = codec->spec; 5306 int sel = ucontrol->value.enumerated.item[0]; 5307 unsigned int items = MIC_BOOST_NUM_OF_STEPS; 5308 5309 if (sel >= items) 5310 return 0; 5311 5312 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n", 5313 sel); 5314 5315 spec->mic_boost_enum_val = sel; 5316 5317 if (spec->in_enum_val != REAR_LINE_IN) 5318 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5319 5320 return 1; 5321 } 5322 5323 /* 5324 * Sound BlasterX AE-5 Headphone Gain Controls. 5325 */ 5326 #define AE5_HEADPHONE_GAIN_MAX 3 5327 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol, 5328 struct snd_ctl_elem_info *uinfo) 5329 { 5330 char *sfx = " Ohms)"; 5331 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5332 5333 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5334 uinfo->count = 1; 5335 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX; 5336 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX) 5337 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1; 5338 sprintf(namestr, "%s %s", 5339 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name, 5340 sfx); 5341 strcpy(uinfo->value.enumerated.name, namestr); 5342 return 0; 5343 } 5344 5345 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol, 5346 struct snd_ctl_elem_value *ucontrol) 5347 { 5348 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5349 struct ca0132_spec *spec = codec->spec; 5350 5351 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val; 5352 return 0; 5353 } 5354 5355 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol, 5356 struct snd_ctl_elem_value *ucontrol) 5357 { 5358 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5359 struct ca0132_spec *spec = codec->spec; 5360 int sel = ucontrol->value.enumerated.item[0]; 5361 unsigned int items = AE5_HEADPHONE_GAIN_MAX; 5362 5363 if (sel >= items) 5364 return 0; 5365 5366 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n", 5367 sel); 5368 5369 spec->ae5_headphone_gain_val = sel; 5370 5371 if (spec->out_enum_val == HEADPHONE_OUT) 5372 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val); 5373 5374 return 1; 5375 } 5376 5377 /* 5378 * Sound BlasterX AE-5 sound filter enumerated control. 5379 */ 5380 #define AE5_SOUND_FILTER_MAX 3 5381 5382 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol, 5383 struct snd_ctl_elem_info *uinfo) 5384 { 5385 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5386 5387 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5388 uinfo->count = 1; 5389 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX; 5390 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX) 5391 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1; 5392 sprintf(namestr, "%s", 5393 ae5_filter_presets[uinfo->value.enumerated.item].name); 5394 strcpy(uinfo->value.enumerated.name, namestr); 5395 return 0; 5396 } 5397 5398 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol, 5399 struct snd_ctl_elem_value *ucontrol) 5400 { 5401 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5402 struct ca0132_spec *spec = codec->spec; 5403 5404 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val; 5405 return 0; 5406 } 5407 5408 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol, 5409 struct snd_ctl_elem_value *ucontrol) 5410 { 5411 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5412 struct ca0132_spec *spec = codec->spec; 5413 int sel = ucontrol->value.enumerated.item[0]; 5414 unsigned int items = AE5_SOUND_FILTER_MAX; 5415 5416 if (sel >= items) 5417 return 0; 5418 5419 codec_dbg(codec, "ae5_sound_filter: %s\n", 5420 ae5_filter_presets[sel].name); 5421 5422 spec->ae5_filter_val = sel; 5423 5424 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 5425 ae5_filter_presets[sel].val); 5426 5427 return 1; 5428 } 5429 5430 /* 5431 * Input Select Control for alternative ca0132 codecs. This exists because 5432 * front microphone has no auto-detect, and we need a way to set the rear 5433 * as line-in 5434 */ 5435 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol, 5436 struct snd_ctl_elem_info *uinfo) 5437 { 5438 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5439 uinfo->count = 1; 5440 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS; 5441 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS) 5442 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1; 5443 strcpy(uinfo->value.enumerated.name, 5444 in_src_str[uinfo->value.enumerated.item]); 5445 return 0; 5446 } 5447 5448 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol, 5449 struct snd_ctl_elem_value *ucontrol) 5450 { 5451 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5452 struct ca0132_spec *spec = codec->spec; 5453 5454 ucontrol->value.enumerated.item[0] = spec->in_enum_val; 5455 return 0; 5456 } 5457 5458 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol, 5459 struct snd_ctl_elem_value *ucontrol) 5460 { 5461 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5462 struct ca0132_spec *spec = codec->spec; 5463 int sel = ucontrol->value.enumerated.item[0]; 5464 unsigned int items = IN_SRC_NUM_OF_INPUTS; 5465 5466 if (sel >= items) 5467 return 0; 5468 5469 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n", 5470 sel, in_src_str[sel]); 5471 5472 spec->in_enum_val = sel; 5473 5474 ca0132_alt_select_in(codec); 5475 5476 return 1; 5477 } 5478 5479 /* Sound Blaster Z Output Select Control */ 5480 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol, 5481 struct snd_ctl_elem_info *uinfo) 5482 { 5483 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5484 uinfo->count = 1; 5485 uinfo->value.enumerated.items = NUM_OF_OUTPUTS; 5486 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS) 5487 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1; 5488 strcpy(uinfo->value.enumerated.name, 5489 alt_out_presets[uinfo->value.enumerated.item].name); 5490 return 0; 5491 } 5492 5493 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol, 5494 struct snd_ctl_elem_value *ucontrol) 5495 { 5496 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5497 struct ca0132_spec *spec = codec->spec; 5498 5499 ucontrol->value.enumerated.item[0] = spec->out_enum_val; 5500 return 0; 5501 } 5502 5503 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol, 5504 struct snd_ctl_elem_value *ucontrol) 5505 { 5506 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5507 struct ca0132_spec *spec = codec->spec; 5508 int sel = ucontrol->value.enumerated.item[0]; 5509 unsigned int items = NUM_OF_OUTPUTS; 5510 unsigned int auto_jack; 5511 5512 if (sel >= items) 5513 return 0; 5514 5515 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n", 5516 sel, alt_out_presets[sel].name); 5517 5518 spec->out_enum_val = sel; 5519 5520 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 5521 5522 if (!auto_jack) 5523 ca0132_alt_select_out(codec); 5524 5525 return 1; 5526 } 5527 5528 /* 5529 * Smart Volume output setting control. Three different settings, Normal, 5530 * which takes the value from the smart volume slider. The two others, loud 5531 * and night, disregard the slider value and have uneditable values. 5532 */ 5533 #define NUM_OF_SVM_SETTINGS 3 5534 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" }; 5535 5536 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol, 5537 struct snd_ctl_elem_info *uinfo) 5538 { 5539 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5540 uinfo->count = 1; 5541 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS; 5542 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS) 5543 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1; 5544 strcpy(uinfo->value.enumerated.name, 5545 out_svm_set_enum_str[uinfo->value.enumerated.item]); 5546 return 0; 5547 } 5548 5549 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol, 5550 struct snd_ctl_elem_value *ucontrol) 5551 { 5552 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5553 struct ca0132_spec *spec = codec->spec; 5554 5555 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting; 5556 return 0; 5557 } 5558 5559 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol, 5560 struct snd_ctl_elem_value *ucontrol) 5561 { 5562 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5563 struct ca0132_spec *spec = codec->spec; 5564 int sel = ucontrol->value.enumerated.item[0]; 5565 unsigned int items = NUM_OF_SVM_SETTINGS; 5566 unsigned int idx = SMART_VOLUME - EFFECT_START_NID; 5567 unsigned int tmp; 5568 5569 if (sel >= items) 5570 return 0; 5571 5572 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n", 5573 sel, out_svm_set_enum_str[sel]); 5574 5575 spec->smart_volume_setting = sel; 5576 5577 switch (sel) { 5578 case 0: 5579 tmp = FLOAT_ZERO; 5580 break; 5581 case 1: 5582 tmp = FLOAT_ONE; 5583 break; 5584 case 2: 5585 tmp = FLOAT_TWO; 5586 break; 5587 default: 5588 tmp = FLOAT_ZERO; 5589 break; 5590 } 5591 /* Req 2 is the Smart Volume Setting req. */ 5592 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 5593 ca0132_effects[idx].reqs[2], tmp); 5594 return 1; 5595 } 5596 5597 /* Sound Blaster Z EQ preset controls */ 5598 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol, 5599 struct snd_ctl_elem_info *uinfo) 5600 { 5601 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 5602 5603 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5604 uinfo->count = 1; 5605 uinfo->value.enumerated.items = items; 5606 if (uinfo->value.enumerated.item >= items) 5607 uinfo->value.enumerated.item = items - 1; 5608 strcpy(uinfo->value.enumerated.name, 5609 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name); 5610 return 0; 5611 } 5612 5613 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol, 5614 struct snd_ctl_elem_value *ucontrol) 5615 { 5616 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5617 struct ca0132_spec *spec = codec->spec; 5618 5619 ucontrol->value.enumerated.item[0] = spec->eq_preset_val; 5620 return 0; 5621 } 5622 5623 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol, 5624 struct snd_ctl_elem_value *ucontrol) 5625 { 5626 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5627 struct ca0132_spec *spec = codec->spec; 5628 int i, err = 0; 5629 int sel = ucontrol->value.enumerated.item[0]; 5630 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 5631 5632 if (sel >= items) 5633 return 0; 5634 5635 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel, 5636 ca0132_alt_eq_presets[sel].name); 5637 /* 5638 * Idx 0 is default. 5639 * Default needs to qualify with CrystalVoice state. 5640 */ 5641 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) { 5642 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid, 5643 ca0132_alt_eq_enum.reqs[i], 5644 ca0132_alt_eq_presets[sel].vals[i]); 5645 if (err < 0) 5646 break; 5647 } 5648 5649 if (err >= 0) 5650 spec->eq_preset_val = sel; 5651 5652 return 1; 5653 } 5654 5655 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol, 5656 struct snd_ctl_elem_info *uinfo) 5657 { 5658 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets); 5659 5660 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5661 uinfo->count = 1; 5662 uinfo->value.enumerated.items = items; 5663 if (uinfo->value.enumerated.item >= items) 5664 uinfo->value.enumerated.item = items - 1; 5665 strcpy(uinfo->value.enumerated.name, 5666 ca0132_voicefx_presets[uinfo->value.enumerated.item].name); 5667 return 0; 5668 } 5669 5670 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol, 5671 struct snd_ctl_elem_value *ucontrol) 5672 { 5673 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5674 struct ca0132_spec *spec = codec->spec; 5675 5676 ucontrol->value.enumerated.item[0] = spec->voicefx_val; 5677 return 0; 5678 } 5679 5680 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol, 5681 struct snd_ctl_elem_value *ucontrol) 5682 { 5683 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5684 struct ca0132_spec *spec = codec->spec; 5685 int i, err = 0; 5686 int sel = ucontrol->value.enumerated.item[0]; 5687 5688 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets)) 5689 return 0; 5690 5691 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n", 5692 sel, ca0132_voicefx_presets[sel].name); 5693 5694 /* 5695 * Idx 0 is default. 5696 * Default needs to qualify with CrystalVoice state. 5697 */ 5698 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) { 5699 err = dspio_set_uint_param(codec, ca0132_voicefx.mid, 5700 ca0132_voicefx.reqs[i], 5701 ca0132_voicefx_presets[sel].vals[i]); 5702 if (err < 0) 5703 break; 5704 } 5705 5706 if (err >= 0) { 5707 spec->voicefx_val = sel; 5708 /* enable voice fx */ 5709 ca0132_voicefx_set(codec, (sel ? 1 : 0)); 5710 } 5711 5712 return 1; 5713 } 5714 5715 static int ca0132_switch_get(struct snd_kcontrol *kcontrol, 5716 struct snd_ctl_elem_value *ucontrol) 5717 { 5718 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5719 struct ca0132_spec *spec = codec->spec; 5720 hda_nid_t nid = get_amp_nid(kcontrol); 5721 int ch = get_amp_channels(kcontrol); 5722 long *valp = ucontrol->value.integer.value; 5723 5724 /* vnode */ 5725 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 5726 if (ch & 1) { 5727 *valp = spec->vnode_lswitch[nid - VNODE_START_NID]; 5728 valp++; 5729 } 5730 if (ch & 2) { 5731 *valp = spec->vnode_rswitch[nid - VNODE_START_NID]; 5732 valp++; 5733 } 5734 return 0; 5735 } 5736 5737 /* effects, include PE and CrystalVoice */ 5738 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) { 5739 *valp = spec->effects_switch[nid - EFFECT_START_NID]; 5740 return 0; 5741 } 5742 5743 /* mic boost */ 5744 if (nid == spec->input_pins[0]) { 5745 *valp = spec->cur_mic_boost; 5746 return 0; 5747 } 5748 5749 return 0; 5750 } 5751 5752 static int ca0132_switch_put(struct snd_kcontrol *kcontrol, 5753 struct snd_ctl_elem_value *ucontrol) 5754 { 5755 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5756 struct ca0132_spec *spec = codec->spec; 5757 hda_nid_t nid = get_amp_nid(kcontrol); 5758 int ch = get_amp_channels(kcontrol); 5759 long *valp = ucontrol->value.integer.value; 5760 int changed = 1; 5761 5762 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n", 5763 nid, *valp); 5764 5765 snd_hda_power_up(codec); 5766 /* vnode */ 5767 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 5768 if (ch & 1) { 5769 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp; 5770 valp++; 5771 } 5772 if (ch & 2) { 5773 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp; 5774 valp++; 5775 } 5776 changed = ca0132_vnode_switch_set(kcontrol, ucontrol); 5777 goto exit; 5778 } 5779 5780 /* PE */ 5781 if (nid == PLAY_ENHANCEMENT) { 5782 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 5783 changed = ca0132_pe_switch_set(codec); 5784 goto exit; 5785 } 5786 5787 /* CrystalVoice */ 5788 if (nid == CRYSTAL_VOICE) { 5789 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 5790 changed = ca0132_cvoice_switch_set(codec); 5791 goto exit; 5792 } 5793 5794 /* out and in effects */ 5795 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) || 5796 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) { 5797 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 5798 changed = ca0132_effects_set(codec, nid, *valp); 5799 goto exit; 5800 } 5801 5802 /* mic boost */ 5803 if (nid == spec->input_pins[0]) { 5804 spec->cur_mic_boost = *valp; 5805 if (ca0132_use_alt_functions(spec)) { 5806 if (spec->in_enum_val != REAR_LINE_IN) 5807 changed = ca0132_mic_boost_set(codec, *valp); 5808 } else { 5809 /* Mic boost does not apply to Digital Mic */ 5810 if (spec->cur_mic_type != DIGITAL_MIC) 5811 changed = ca0132_mic_boost_set(codec, *valp); 5812 } 5813 5814 goto exit; 5815 } 5816 5817 if (nid == ZXR_HEADPHONE_GAIN) { 5818 spec->zxr_gain_set = *valp; 5819 if (spec->cur_out_type == HEADPHONE_OUT) 5820 changed = zxr_headphone_gain_set(codec, *valp); 5821 else 5822 changed = 0; 5823 5824 goto exit; 5825 } 5826 5827 exit: 5828 snd_hda_power_down(codec); 5829 return changed; 5830 } 5831 5832 /* 5833 * Volume related 5834 */ 5835 /* 5836 * Sets the internal DSP decibel level to match the DAC for output, and the 5837 * ADC for input. Currently only the SBZ sets dsp capture volume level, and 5838 * all alternative codecs set DSP playback volume. 5839 */ 5840 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid) 5841 { 5842 struct ca0132_spec *spec = codec->spec; 5843 unsigned int dsp_dir; 5844 unsigned int lookup_val; 5845 5846 if (nid == VNID_SPK) 5847 dsp_dir = DSP_VOL_OUT; 5848 else 5849 dsp_dir = DSP_VOL_IN; 5850 5851 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID]; 5852 5853 dspio_set_uint_param(codec, 5854 ca0132_alt_vol_ctls[dsp_dir].mid, 5855 ca0132_alt_vol_ctls[dsp_dir].reqs[0], 5856 float_vol_db_lookup[lookup_val]); 5857 5858 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID]; 5859 5860 dspio_set_uint_param(codec, 5861 ca0132_alt_vol_ctls[dsp_dir].mid, 5862 ca0132_alt_vol_ctls[dsp_dir].reqs[1], 5863 float_vol_db_lookup[lookup_val]); 5864 5865 dspio_set_uint_param(codec, 5866 ca0132_alt_vol_ctls[dsp_dir].mid, 5867 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO); 5868 } 5869 5870 static int ca0132_volume_info(struct snd_kcontrol *kcontrol, 5871 struct snd_ctl_elem_info *uinfo) 5872 { 5873 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5874 struct ca0132_spec *spec = codec->spec; 5875 hda_nid_t nid = get_amp_nid(kcontrol); 5876 int ch = get_amp_channels(kcontrol); 5877 int dir = get_amp_direction(kcontrol); 5878 unsigned long pval; 5879 int err; 5880 5881 switch (nid) { 5882 case VNID_SPK: 5883 /* follow shared_out info */ 5884 nid = spec->shared_out_nid; 5885 mutex_lock(&codec->control_mutex); 5886 pval = kcontrol->private_value; 5887 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 5888 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 5889 kcontrol->private_value = pval; 5890 mutex_unlock(&codec->control_mutex); 5891 break; 5892 case VNID_MIC: 5893 /* follow shared_mic info */ 5894 nid = spec->shared_mic_nid; 5895 mutex_lock(&codec->control_mutex); 5896 pval = kcontrol->private_value; 5897 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 5898 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 5899 kcontrol->private_value = pval; 5900 mutex_unlock(&codec->control_mutex); 5901 break; 5902 default: 5903 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 5904 } 5905 return err; 5906 } 5907 5908 static int ca0132_volume_get(struct snd_kcontrol *kcontrol, 5909 struct snd_ctl_elem_value *ucontrol) 5910 { 5911 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5912 struct ca0132_spec *spec = codec->spec; 5913 hda_nid_t nid = get_amp_nid(kcontrol); 5914 int ch = get_amp_channels(kcontrol); 5915 long *valp = ucontrol->value.integer.value; 5916 5917 /* store the left and right volume */ 5918 if (ch & 1) { 5919 *valp = spec->vnode_lvol[nid - VNODE_START_NID]; 5920 valp++; 5921 } 5922 if (ch & 2) { 5923 *valp = spec->vnode_rvol[nid - VNODE_START_NID]; 5924 valp++; 5925 } 5926 return 0; 5927 } 5928 5929 static int ca0132_volume_put(struct snd_kcontrol *kcontrol, 5930 struct snd_ctl_elem_value *ucontrol) 5931 { 5932 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5933 struct ca0132_spec *spec = codec->spec; 5934 hda_nid_t nid = get_amp_nid(kcontrol); 5935 int ch = get_amp_channels(kcontrol); 5936 long *valp = ucontrol->value.integer.value; 5937 hda_nid_t shared_nid = 0; 5938 bool effective; 5939 int changed = 1; 5940 5941 /* store the left and right volume */ 5942 if (ch & 1) { 5943 spec->vnode_lvol[nid - VNODE_START_NID] = *valp; 5944 valp++; 5945 } 5946 if (ch & 2) { 5947 spec->vnode_rvol[nid - VNODE_START_NID] = *valp; 5948 valp++; 5949 } 5950 5951 /* if effective conditions, then update hw immediately. */ 5952 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 5953 if (effective) { 5954 int dir = get_amp_direction(kcontrol); 5955 unsigned long pval; 5956 5957 snd_hda_power_up(codec); 5958 mutex_lock(&codec->control_mutex); 5959 pval = kcontrol->private_value; 5960 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 5961 0, dir); 5962 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 5963 kcontrol->private_value = pval; 5964 mutex_unlock(&codec->control_mutex); 5965 snd_hda_power_down(codec); 5966 } 5967 5968 return changed; 5969 } 5970 5971 /* 5972 * This function is the same as the one above, because using an if statement 5973 * inside of the above volume control for the DSP volume would cause too much 5974 * lag. This is a lot more smooth. 5975 */ 5976 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol, 5977 struct snd_ctl_elem_value *ucontrol) 5978 { 5979 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5980 struct ca0132_spec *spec = codec->spec; 5981 hda_nid_t nid = get_amp_nid(kcontrol); 5982 int ch = get_amp_channels(kcontrol); 5983 long *valp = ucontrol->value.integer.value; 5984 hda_nid_t vnid = 0; 5985 int changed; 5986 5987 switch (nid) { 5988 case 0x02: 5989 vnid = VNID_SPK; 5990 break; 5991 case 0x07: 5992 vnid = VNID_MIC; 5993 break; 5994 } 5995 5996 /* store the left and right volume */ 5997 if (ch & 1) { 5998 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp; 5999 valp++; 6000 } 6001 if (ch & 2) { 6002 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp; 6003 valp++; 6004 } 6005 6006 snd_hda_power_up(codec); 6007 ca0132_alt_dsp_volume_put(codec, vnid); 6008 mutex_lock(&codec->control_mutex); 6009 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 6010 mutex_unlock(&codec->control_mutex); 6011 snd_hda_power_down(codec); 6012 6013 return changed; 6014 } 6015 6016 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag, 6017 unsigned int size, unsigned int __user *tlv) 6018 { 6019 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6020 struct ca0132_spec *spec = codec->spec; 6021 hda_nid_t nid = get_amp_nid(kcontrol); 6022 int ch = get_amp_channels(kcontrol); 6023 int dir = get_amp_direction(kcontrol); 6024 unsigned long pval; 6025 int err; 6026 6027 switch (nid) { 6028 case VNID_SPK: 6029 /* follow shared_out tlv */ 6030 nid = spec->shared_out_nid; 6031 mutex_lock(&codec->control_mutex); 6032 pval = kcontrol->private_value; 6033 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6034 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6035 kcontrol->private_value = pval; 6036 mutex_unlock(&codec->control_mutex); 6037 break; 6038 case VNID_MIC: 6039 /* follow shared_mic tlv */ 6040 nid = spec->shared_mic_nid; 6041 mutex_lock(&codec->control_mutex); 6042 pval = kcontrol->private_value; 6043 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6044 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6045 kcontrol->private_value = pval; 6046 mutex_unlock(&codec->control_mutex); 6047 break; 6048 default: 6049 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6050 } 6051 return err; 6052 } 6053 6054 /* Add volume slider control for effect level */ 6055 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid, 6056 const char *pfx, int dir) 6057 { 6058 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6059 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6060 struct snd_kcontrol_new knew = 6061 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 6062 6063 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]); 6064 6065 knew.tlv.c = NULL; 6066 6067 switch (nid) { 6068 case XBASS_XOVER: 6069 knew.info = ca0132_alt_xbass_xover_slider_info; 6070 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 6071 knew.put = ca0132_alt_xbass_xover_slider_put; 6072 break; 6073 default: 6074 knew.info = ca0132_alt_effect_slider_info; 6075 knew.get = ca0132_alt_slider_ctl_get; 6076 knew.put = ca0132_alt_effect_slider_put; 6077 knew.private_value = 6078 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 6079 break; 6080 } 6081 6082 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6083 } 6084 6085 /* 6086 * Added FX: prefix for the alternative codecs, because otherwise the surround 6087 * effect would conflict with the Surround sound volume control. Also seems more 6088 * clear as to what the switches do. Left alone for others. 6089 */ 6090 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid, 6091 const char *pfx, int dir) 6092 { 6093 struct ca0132_spec *spec = codec->spec; 6094 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6095 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6096 struct snd_kcontrol_new knew = 6097 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type); 6098 /* If using alt_controls, add FX: prefix. But, don't add FX: 6099 * prefix to OutFX or InFX enable controls. 6100 */ 6101 if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID)) 6102 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]); 6103 else 6104 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]); 6105 6106 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6107 } 6108 6109 static int add_voicefx(struct hda_codec *codec) 6110 { 6111 struct snd_kcontrol_new knew = 6112 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name, 6113 VOICEFX, 1, 0, HDA_INPUT); 6114 knew.info = ca0132_voicefx_info; 6115 knew.get = ca0132_voicefx_get; 6116 knew.put = ca0132_voicefx_put; 6117 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec)); 6118 } 6119 6120 /* Create the EQ Preset control */ 6121 static int add_ca0132_alt_eq_presets(struct hda_codec *codec) 6122 { 6123 struct snd_kcontrol_new knew = 6124 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name, 6125 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT); 6126 knew.info = ca0132_alt_eq_preset_info; 6127 knew.get = ca0132_alt_eq_preset_get; 6128 knew.put = ca0132_alt_eq_preset_put; 6129 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM, 6130 snd_ctl_new1(&knew, codec)); 6131 } 6132 6133 /* 6134 * Add enumerated control for the three different settings of the smart volume 6135 * output effect. Normal just uses the slider value, and loud and night are 6136 * their own things that ignore that value. 6137 */ 6138 static int ca0132_alt_add_svm_enum(struct hda_codec *codec) 6139 { 6140 struct snd_kcontrol_new knew = 6141 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting", 6142 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT); 6143 knew.info = ca0132_alt_svm_setting_info; 6144 knew.get = ca0132_alt_svm_setting_get; 6145 knew.put = ca0132_alt_svm_setting_put; 6146 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM, 6147 snd_ctl_new1(&knew, codec)); 6148 6149 } 6150 6151 /* 6152 * Create an Output Select enumerated control for codecs with surround 6153 * out capabilities. 6154 */ 6155 static int ca0132_alt_add_output_enum(struct hda_codec *codec) 6156 { 6157 struct snd_kcontrol_new knew = 6158 HDA_CODEC_MUTE_MONO("Output Select", 6159 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT); 6160 knew.info = ca0132_alt_output_select_get_info; 6161 knew.get = ca0132_alt_output_select_get; 6162 knew.put = ca0132_alt_output_select_put; 6163 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM, 6164 snd_ctl_new1(&knew, codec)); 6165 } 6166 6167 /* 6168 * Create an Input Source enumerated control for the alternate ca0132 codecs 6169 * because the front microphone has no auto-detect, and Line-in has to be set 6170 * somehow. 6171 */ 6172 static int ca0132_alt_add_input_enum(struct hda_codec *codec) 6173 { 6174 struct snd_kcontrol_new knew = 6175 HDA_CODEC_MUTE_MONO("Input Source", 6176 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT); 6177 knew.info = ca0132_alt_input_source_info; 6178 knew.get = ca0132_alt_input_source_get; 6179 knew.put = ca0132_alt_input_source_put; 6180 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM, 6181 snd_ctl_new1(&knew, codec)); 6182 } 6183 6184 /* 6185 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds 6186 * more control than the original mic boost, which is either full 30dB or off. 6187 */ 6188 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec) 6189 { 6190 struct snd_kcontrol_new knew = 6191 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch", 6192 MIC_BOOST_ENUM, 1, 0, HDA_INPUT); 6193 knew.info = ca0132_alt_mic_boost_info; 6194 knew.get = ca0132_alt_mic_boost_get; 6195 knew.put = ca0132_alt_mic_boost_put; 6196 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM, 6197 snd_ctl_new1(&knew, codec)); 6198 6199 } 6200 6201 /* 6202 * Add headphone gain enumerated control for the AE-5. This switches between 6203 * three modes, low, medium, and high. When non-headphone outputs are selected, 6204 * it is automatically set to high. This is the same behavior as Windows. 6205 */ 6206 static int ae5_add_headphone_gain_enum(struct hda_codec *codec) 6207 { 6208 struct snd_kcontrol_new knew = 6209 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain", 6210 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT); 6211 knew.info = ae5_headphone_gain_info; 6212 knew.get = ae5_headphone_gain_get; 6213 knew.put = ae5_headphone_gain_put; 6214 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM, 6215 snd_ctl_new1(&knew, codec)); 6216 } 6217 6218 /* 6219 * Add sound filter enumerated control for the AE-5. This adds three different 6220 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've 6221 * read into it, it changes the DAC's interpolation filter. 6222 */ 6223 static int ae5_add_sound_filter_enum(struct hda_codec *codec) 6224 { 6225 struct snd_kcontrol_new knew = 6226 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter", 6227 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT); 6228 knew.info = ae5_sound_filter_info; 6229 knew.get = ae5_sound_filter_get; 6230 knew.put = ae5_sound_filter_put; 6231 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM, 6232 snd_ctl_new1(&knew, codec)); 6233 } 6234 6235 static int zxr_add_headphone_gain_switch(struct hda_codec *codec) 6236 { 6237 struct snd_kcontrol_new knew = 6238 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain", 6239 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT); 6240 6241 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN, 6242 snd_ctl_new1(&knew, codec)); 6243 } 6244 6245 /* 6246 * Need to create slave controls for the alternate codecs that have surround 6247 * capabilities. 6248 */ 6249 static const char * const ca0132_alt_slave_pfxs[] = { 6250 "Front", "Surround", "Center", "LFE", NULL, 6251 }; 6252 6253 /* 6254 * Also need special channel map, because the default one is incorrect. 6255 * I think this has to do with the pin for rear surround being 0x11, 6256 * and the center/lfe being 0x10. Usually the pin order is the opposite. 6257 */ 6258 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = { 6259 { .channels = 2, 6260 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } }, 6261 { .channels = 4, 6262 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6263 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6264 { .channels = 6, 6265 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6266 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE, 6267 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6268 { } 6269 }; 6270 6271 /* Add the correct chmap for streams with 6 channels. */ 6272 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec) 6273 { 6274 int err = 0; 6275 struct hda_pcm *pcm; 6276 6277 list_for_each_entry(pcm, &codec->pcm_list_head, list) { 6278 struct hda_pcm_stream *hinfo = 6279 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 6280 struct snd_pcm_chmap *chmap; 6281 const struct snd_pcm_chmap_elem *elem; 6282 6283 elem = ca0132_alt_chmaps; 6284 if (hinfo->channels_max == 6) { 6285 err = snd_pcm_add_chmap_ctls(pcm->pcm, 6286 SNDRV_PCM_STREAM_PLAYBACK, 6287 elem, hinfo->channels_max, 0, &chmap); 6288 if (err < 0) 6289 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!"); 6290 } 6291 } 6292 } 6293 6294 /* 6295 * When changing Node IDs for Mixer Controls below, make sure to update 6296 * Node IDs in ca0132_config() as well. 6297 */ 6298 static const struct snd_kcontrol_new ca0132_mixer[] = { 6299 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT), 6300 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT), 6301 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 6302 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6303 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT), 6304 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT), 6305 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6306 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6307 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch", 6308 0x12, 1, HDA_INPUT), 6309 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch", 6310 VNID_HP_SEL, 1, HDA_OUTPUT), 6311 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch", 6312 VNID_AMIC1_SEL, 1, HDA_INPUT), 6313 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6314 VNID_HP_ASEL, 1, HDA_OUTPUT), 6315 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch", 6316 VNID_AMIC1_ASEL, 1, HDA_INPUT), 6317 { } /* end */ 6318 }; 6319 6320 /* 6321 * Desktop specific control mixer. Removes auto-detect for mic, and adds 6322 * surround controls. Also sets both the Front Playback and Capture Volume 6323 * controls to alt so they set the DSP's decibel level. 6324 */ 6325 static const struct snd_kcontrol_new desktop_mixer[] = { 6326 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 6327 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 6328 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 6329 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 6330 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 6331 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 6332 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 6333 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 6334 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT), 6335 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6336 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6337 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6338 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6339 VNID_HP_ASEL, 1, HDA_OUTPUT), 6340 { } /* end */ 6341 }; 6342 6343 /* 6344 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture 6345 * because it doesn't set decibel levels for the DSP for capture. 6346 */ 6347 static const struct snd_kcontrol_new r3di_mixer[] = { 6348 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 6349 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 6350 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 6351 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 6352 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 6353 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 6354 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 6355 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 6356 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 6357 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6358 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6359 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6360 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6361 VNID_HP_ASEL, 1, HDA_OUTPUT), 6362 { } /* end */ 6363 }; 6364 6365 static int ca0132_build_controls(struct hda_codec *codec) 6366 { 6367 struct ca0132_spec *spec = codec->spec; 6368 int i, num_fx, num_sliders; 6369 int err = 0; 6370 6371 /* Add Mixer controls */ 6372 for (i = 0; i < spec->num_mixers; i++) { 6373 err = snd_hda_add_new_ctls(codec, spec->mixers[i]); 6374 if (err < 0) 6375 return err; 6376 } 6377 /* Setup vmaster with surround slaves for desktop ca0132 devices */ 6378 if (ca0132_use_alt_functions(spec)) { 6379 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT, 6380 spec->tlv); 6381 snd_hda_add_vmaster(codec, "Master Playback Volume", 6382 spec->tlv, ca0132_alt_slave_pfxs, 6383 "Playback Volume"); 6384 err = __snd_hda_add_vmaster(codec, "Master Playback Switch", 6385 NULL, ca0132_alt_slave_pfxs, 6386 "Playback Switch", 6387 true, &spec->vmaster_mute.sw_kctl); 6388 if (err < 0) 6389 return err; 6390 } 6391 6392 /* Add in and out effects controls. 6393 * VoiceFX, PE and CrystalVoice are added separately. 6394 */ 6395 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 6396 for (i = 0; i < num_fx; i++) { 6397 /* Desktop cards break if Echo Cancellation is used. */ 6398 if (ca0132_use_pci_mmio(spec)) { 6399 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID + 6400 OUT_EFFECTS_COUNT)) 6401 continue; 6402 } 6403 6404 err = add_fx_switch(codec, ca0132_effects[i].nid, 6405 ca0132_effects[i].name, 6406 ca0132_effects[i].direct); 6407 if (err < 0) 6408 return err; 6409 } 6410 /* 6411 * If codec has use_alt_controls set to true, add effect level sliders, 6412 * EQ presets, and Smart Volume presets. Also, change names to add FX 6413 * prefix, and change PlayEnhancement and CrystalVoice to match. 6414 */ 6415 if (ca0132_use_alt_controls(spec)) { 6416 err = ca0132_alt_add_svm_enum(codec); 6417 if (err < 0) 6418 return err; 6419 6420 err = add_ca0132_alt_eq_presets(codec); 6421 if (err < 0) 6422 return err; 6423 6424 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 6425 "Enable OutFX", 0); 6426 if (err < 0) 6427 return err; 6428 6429 err = add_fx_switch(codec, CRYSTAL_VOICE, 6430 "Enable InFX", 1); 6431 if (err < 0) 6432 return err; 6433 6434 num_sliders = OUT_EFFECTS_COUNT - 1; 6435 for (i = 0; i < num_sliders; i++) { 6436 err = ca0132_alt_add_effect_slider(codec, 6437 ca0132_effects[i].nid, 6438 ca0132_effects[i].name, 6439 ca0132_effects[i].direct); 6440 if (err < 0) 6441 return err; 6442 } 6443 6444 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER, 6445 "X-Bass Crossover", EFX_DIR_OUT); 6446 6447 if (err < 0) 6448 return err; 6449 } else { 6450 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 6451 "PlayEnhancement", 0); 6452 if (err < 0) 6453 return err; 6454 6455 err = add_fx_switch(codec, CRYSTAL_VOICE, 6456 "CrystalVoice", 1); 6457 if (err < 0) 6458 return err; 6459 } 6460 err = add_voicefx(codec); 6461 if (err < 0) 6462 return err; 6463 6464 /* 6465 * If the codec uses alt_functions, you need the enumerated controls 6466 * to select the new outputs and inputs, plus add the new mic boost 6467 * setting control. 6468 */ 6469 if (ca0132_use_alt_functions(spec)) { 6470 err = ca0132_alt_add_output_enum(codec); 6471 if (err < 0) 6472 return err; 6473 err = ca0132_alt_add_mic_boost_enum(codec); 6474 if (err < 0) 6475 return err; 6476 /* 6477 * ZxR only has microphone input, there is no front panel 6478 * header on the card, and aux-in is handled by the DBPro board. 6479 */ 6480 if (ca0132_quirk(spec) != QUIRK_ZXR) { 6481 err = ca0132_alt_add_input_enum(codec); 6482 if (err < 0) 6483 return err; 6484 } 6485 } 6486 6487 if (ca0132_quirk(spec) == QUIRK_AE5) { 6488 err = ae5_add_headphone_gain_enum(codec); 6489 if (err < 0) 6490 return err; 6491 err = ae5_add_sound_filter_enum(codec); 6492 if (err < 0) 6493 return err; 6494 } 6495 6496 if (ca0132_quirk(spec) == QUIRK_ZXR) { 6497 err = zxr_add_headphone_gain_switch(codec); 6498 if (err < 0) 6499 return err; 6500 } 6501 #ifdef ENABLE_TUNING_CONTROLS 6502 add_tuning_ctls(codec); 6503 #endif 6504 6505 err = snd_hda_jack_add_kctls(codec, &spec->autocfg); 6506 if (err < 0) 6507 return err; 6508 6509 if (spec->dig_out) { 6510 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 6511 spec->dig_out); 6512 if (err < 0) 6513 return err; 6514 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout); 6515 if (err < 0) 6516 return err; 6517 /* spec->multiout.share_spdif = 1; */ 6518 } 6519 6520 if (spec->dig_in) { 6521 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 6522 if (err < 0) 6523 return err; 6524 } 6525 6526 if (ca0132_use_alt_functions(spec)) 6527 ca0132_alt_add_chmap_ctls(codec); 6528 6529 return 0; 6530 } 6531 6532 static int dbpro_build_controls(struct hda_codec *codec) 6533 { 6534 struct ca0132_spec *spec = codec->spec; 6535 int err = 0; 6536 6537 if (spec->dig_out) { 6538 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 6539 spec->dig_out); 6540 if (err < 0) 6541 return err; 6542 } 6543 6544 if (spec->dig_in) { 6545 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 6546 if (err < 0) 6547 return err; 6548 } 6549 6550 return 0; 6551 } 6552 6553 /* 6554 * PCM 6555 */ 6556 static const struct hda_pcm_stream ca0132_pcm_analog_playback = { 6557 .substreams = 1, 6558 .channels_min = 2, 6559 .channels_max = 6, 6560 .ops = { 6561 .prepare = ca0132_playback_pcm_prepare, 6562 .cleanup = ca0132_playback_pcm_cleanup, 6563 .get_delay = ca0132_playback_pcm_delay, 6564 }, 6565 }; 6566 6567 static const struct hda_pcm_stream ca0132_pcm_analog_capture = { 6568 .substreams = 1, 6569 .channels_min = 2, 6570 .channels_max = 2, 6571 .ops = { 6572 .prepare = ca0132_capture_pcm_prepare, 6573 .cleanup = ca0132_capture_pcm_cleanup, 6574 .get_delay = ca0132_capture_pcm_delay, 6575 }, 6576 }; 6577 6578 static const struct hda_pcm_stream ca0132_pcm_digital_playback = { 6579 .substreams = 1, 6580 .channels_min = 2, 6581 .channels_max = 2, 6582 .ops = { 6583 .open = ca0132_dig_playback_pcm_open, 6584 .close = ca0132_dig_playback_pcm_close, 6585 .prepare = ca0132_dig_playback_pcm_prepare, 6586 .cleanup = ca0132_dig_playback_pcm_cleanup 6587 }, 6588 }; 6589 6590 static const struct hda_pcm_stream ca0132_pcm_digital_capture = { 6591 .substreams = 1, 6592 .channels_min = 2, 6593 .channels_max = 2, 6594 }; 6595 6596 static int ca0132_build_pcms(struct hda_codec *codec) 6597 { 6598 struct ca0132_spec *spec = codec->spec; 6599 struct hda_pcm *info; 6600 6601 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog"); 6602 if (!info) 6603 return -ENOMEM; 6604 if (ca0132_use_alt_functions(spec)) { 6605 info->own_chmap = true; 6606 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap 6607 = ca0132_alt_chmaps; 6608 } 6609 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback; 6610 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0]; 6611 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max = 6612 spec->multiout.max_channels; 6613 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 6614 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 6615 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 6616 6617 /* With the DSP enabled, desktops don't use this ADC. */ 6618 if (!ca0132_use_alt_functions(spec)) { 6619 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2"); 6620 if (!info) 6621 return -ENOMEM; 6622 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 6623 ca0132_pcm_analog_capture; 6624 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 6625 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1]; 6626 } 6627 6628 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear"); 6629 if (!info) 6630 return -ENOMEM; 6631 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 6632 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 6633 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2]; 6634 6635 if (!spec->dig_out && !spec->dig_in) 6636 return 0; 6637 6638 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 6639 if (!info) 6640 return -ENOMEM; 6641 info->pcm_type = HDA_PCM_TYPE_SPDIF; 6642 if (spec->dig_out) { 6643 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 6644 ca0132_pcm_digital_playback; 6645 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 6646 } 6647 if (spec->dig_in) { 6648 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 6649 ca0132_pcm_digital_capture; 6650 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 6651 } 6652 6653 return 0; 6654 } 6655 6656 static int dbpro_build_pcms(struct hda_codec *codec) 6657 { 6658 struct ca0132_spec *spec = codec->spec; 6659 struct hda_pcm *info; 6660 6661 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog"); 6662 if (!info) 6663 return -ENOMEM; 6664 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 6665 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 6666 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 6667 6668 6669 if (!spec->dig_out && !spec->dig_in) 6670 return 0; 6671 6672 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 6673 if (!info) 6674 return -ENOMEM; 6675 info->pcm_type = HDA_PCM_TYPE_SPDIF; 6676 if (spec->dig_out) { 6677 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 6678 ca0132_pcm_digital_playback; 6679 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 6680 } 6681 if (spec->dig_in) { 6682 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 6683 ca0132_pcm_digital_capture; 6684 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 6685 } 6686 6687 return 0; 6688 } 6689 6690 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac) 6691 { 6692 if (pin) { 6693 snd_hda_set_pin_ctl(codec, pin, PIN_HP); 6694 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 6695 snd_hda_codec_write(codec, pin, 0, 6696 AC_VERB_SET_AMP_GAIN_MUTE, 6697 AMP_OUT_UNMUTE); 6698 } 6699 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP)) 6700 snd_hda_codec_write(codec, dac, 0, 6701 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO); 6702 } 6703 6704 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc) 6705 { 6706 if (pin) { 6707 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80); 6708 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP) 6709 snd_hda_codec_write(codec, pin, 0, 6710 AC_VERB_SET_AMP_GAIN_MUTE, 6711 AMP_IN_UNMUTE(0)); 6712 } 6713 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) { 6714 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE, 6715 AMP_IN_UNMUTE(0)); 6716 6717 /* init to 0 dB and unmute. */ 6718 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 6719 HDA_AMP_VOLMASK, 0x5a); 6720 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 6721 HDA_AMP_MUTE, 0); 6722 } 6723 } 6724 6725 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir) 6726 { 6727 unsigned int caps; 6728 6729 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ? 6730 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP); 6731 snd_hda_override_amp_caps(codec, nid, dir, caps); 6732 } 6733 6734 /* 6735 * Switch between Digital built-in mic and analog mic. 6736 */ 6737 static void ca0132_set_dmic(struct hda_codec *codec, int enable) 6738 { 6739 struct ca0132_spec *spec = codec->spec; 6740 unsigned int tmp; 6741 u8 val; 6742 unsigned int oldval; 6743 6744 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable); 6745 6746 oldval = stop_mic1(codec); 6747 ca0132_set_vipsource(codec, 0); 6748 if (enable) { 6749 /* set DMic input as 2-ch */ 6750 tmp = FLOAT_TWO; 6751 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 6752 6753 val = spec->dmic_ctl; 6754 val |= 0x80; 6755 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6756 VENDOR_CHIPIO_DMIC_CTL_SET, val); 6757 6758 if (!(spec->dmic_ctl & 0x20)) 6759 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1); 6760 } else { 6761 /* set AMic input as mono */ 6762 tmp = FLOAT_ONE; 6763 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 6764 6765 val = spec->dmic_ctl; 6766 /* clear bit7 and bit5 to disable dmic */ 6767 val &= 0x5f; 6768 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6769 VENDOR_CHIPIO_DMIC_CTL_SET, val); 6770 6771 if (!(spec->dmic_ctl & 0x20)) 6772 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0); 6773 } 6774 ca0132_set_vipsource(codec, 1); 6775 resume_mic1(codec, oldval); 6776 } 6777 6778 /* 6779 * Initialization for Digital Mic. 6780 */ 6781 static void ca0132_init_dmic(struct hda_codec *codec) 6782 { 6783 struct ca0132_spec *spec = codec->spec; 6784 u8 val; 6785 6786 /* Setup Digital Mic here, but don't enable. 6787 * Enable based on jack detect. 6788 */ 6789 6790 /* MCLK uses MPIO1, set to enable. 6791 * Bit 2-0: MPIO select 6792 * Bit 3: set to disable 6793 * Bit 7-4: reserved 6794 */ 6795 val = 0x01; 6796 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6797 VENDOR_CHIPIO_DMIC_MCLK_SET, val); 6798 6799 /* Data1 uses MPIO3. Data2 not use 6800 * Bit 2-0: Data1 MPIO select 6801 * Bit 3: set disable Data1 6802 * Bit 6-4: Data2 MPIO select 6803 * Bit 7: set disable Data2 6804 */ 6805 val = 0x83; 6806 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6807 VENDOR_CHIPIO_DMIC_PIN_SET, val); 6808 6809 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first. 6810 * Bit 3-0: Channel mask 6811 * Bit 4: set for 48KHz, clear for 32KHz 6812 * Bit 5: mode 6813 * Bit 6: set to select Data2, clear for Data1 6814 * Bit 7: set to enable DMic, clear for AMic 6815 */ 6816 if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4) 6817 val = 0x33; 6818 else 6819 val = 0x23; 6820 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */ 6821 spec->dmic_ctl = val; 6822 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6823 VENDOR_CHIPIO_DMIC_CTL_SET, val); 6824 } 6825 6826 /* 6827 * Initialization for Analog Mic 2 6828 */ 6829 static void ca0132_init_analog_mic2(struct hda_codec *codec) 6830 { 6831 struct ca0132_spec *spec = codec->spec; 6832 6833 mutex_lock(&spec->chipio_mutex); 6834 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6835 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); 6836 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6837 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 6838 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6839 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 6840 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6841 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D); 6842 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6843 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 6844 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6845 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 6846 mutex_unlock(&spec->chipio_mutex); 6847 } 6848 6849 static void ca0132_refresh_widget_caps(struct hda_codec *codec) 6850 { 6851 struct ca0132_spec *spec = codec->spec; 6852 int i; 6853 6854 codec_dbg(codec, "ca0132_refresh_widget_caps.\n"); 6855 snd_hda_codec_update_widgets(codec); 6856 6857 for (i = 0; i < spec->multiout.num_dacs; i++) 6858 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT); 6859 6860 for (i = 0; i < spec->num_outputs; i++) 6861 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT); 6862 6863 for (i = 0; i < spec->num_inputs; i++) { 6864 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT); 6865 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT); 6866 } 6867 } 6868 6869 /* 6870 * Creates a dummy stream to bind the output to. This seems to have to be done 6871 * after changing the main outputs source and destination streams. 6872 */ 6873 static void ca0132_alt_create_dummy_stream(struct hda_codec *codec) 6874 { 6875 struct ca0132_spec *spec = codec->spec; 6876 unsigned int stream_format; 6877 6878 stream_format = snd_hdac_calc_stream_format(48000, 2, 6879 SNDRV_PCM_FORMAT_S32_LE, 32, 0); 6880 6881 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id, 6882 0, stream_format); 6883 6884 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 6885 } 6886 6887 /* 6888 * Initialize mic for non-chromebook ca0132 implementations. 6889 */ 6890 static void ca0132_alt_init_analog_mics(struct hda_codec *codec) 6891 { 6892 struct ca0132_spec *spec = codec->spec; 6893 unsigned int tmp; 6894 6895 /* Mic 1 Setup */ 6896 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 6897 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 6898 if (ca0132_quirk(spec) == QUIRK_R3DI) { 6899 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 6900 tmp = FLOAT_ONE; 6901 } else 6902 tmp = FLOAT_THREE; 6903 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 6904 6905 /* Mic 2 setup (not present on desktop cards) */ 6906 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000); 6907 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000); 6908 if (ca0132_quirk(spec) == QUIRK_R3DI) 6909 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 6910 tmp = FLOAT_ZERO; 6911 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 6912 } 6913 6914 /* 6915 * Sets the source of stream 0x14 to connpointID 0x48, and the destination 6916 * connpointID to 0x91. If this isn't done, the destination is 0x71, and 6917 * you get no sound. I'm guessing this has to do with the Sound Blaster Z 6918 * having an updated DAC, which changes the destination to that DAC. 6919 */ 6920 static void sbz_connect_streams(struct hda_codec *codec) 6921 { 6922 struct ca0132_spec *spec = codec->spec; 6923 6924 mutex_lock(&spec->chipio_mutex); 6925 6926 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n"); 6927 6928 chipio_set_stream_channels(codec, 0x0C, 6); 6929 chipio_set_stream_control(codec, 0x0C, 1); 6930 6931 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */ 6932 chipio_write_no_mutex(codec, 0x18a020, 0x00000043); 6933 6934 /* Setup stream 0x14 with it's source and destination points */ 6935 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91); 6936 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000); 6937 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000); 6938 chipio_set_stream_channels(codec, 0x14, 2); 6939 chipio_set_stream_control(codec, 0x14, 1); 6940 6941 codec_dbg(codec, "Connect Streams exited, mutex released.\n"); 6942 6943 mutex_unlock(&spec->chipio_mutex); 6944 } 6945 6946 /* 6947 * Write data through ChipIO to setup proper stream destinations. 6948 * Not sure how it exactly works, but it seems to direct data 6949 * to different destinations. Example is f8 to c0, e0 to c0. 6950 * All I know is, if you don't set these, you get no sound. 6951 */ 6952 static void sbz_chipio_startup_data(struct hda_codec *codec) 6953 { 6954 struct ca0132_spec *spec = codec->spec; 6955 6956 mutex_lock(&spec->chipio_mutex); 6957 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n"); 6958 6959 /* These control audio output */ 6960 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0); 6961 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1); 6962 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6); 6963 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7); 6964 /* Signal to update I think */ 6965 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 6966 6967 chipio_set_stream_channels(codec, 0x0C, 6); 6968 chipio_set_stream_control(codec, 0x0C, 1); 6969 /* No clue what these control */ 6970 if (ca0132_quirk(spec) == QUIRK_SBZ) { 6971 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0); 6972 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1); 6973 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2); 6974 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3); 6975 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4); 6976 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5); 6977 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6); 6978 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7); 6979 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8); 6980 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9); 6981 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca); 6982 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb); 6983 } else if (ca0132_quirk(spec) == QUIRK_ZXR) { 6984 chipio_write_no_mutex(codec, 0x190038, 0x000140c2); 6985 chipio_write_no_mutex(codec, 0x19003c, 0x000141c3); 6986 chipio_write_no_mutex(codec, 0x190040, 0x000150c4); 6987 chipio_write_no_mutex(codec, 0x190044, 0x000151c5); 6988 chipio_write_no_mutex(codec, 0x190050, 0x000142c8); 6989 chipio_write_no_mutex(codec, 0x190054, 0x000143c9); 6990 chipio_write_no_mutex(codec, 0x190058, 0x000152ca); 6991 chipio_write_no_mutex(codec, 0x19005c, 0x000153cb); 6992 } 6993 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 6994 6995 codec_dbg(codec, "Startup Data exited, mutex released.\n"); 6996 mutex_unlock(&spec->chipio_mutex); 6997 } 6998 6999 /* 7000 * Custom DSP SCP commands where the src value is 0x00 instead of 0x20. This is 7001 * done after the DSP is loaded. 7002 */ 7003 static void ca0132_alt_dsp_scp_startup(struct hda_codec *codec) 7004 { 7005 struct ca0132_spec *spec = codec->spec; 7006 unsigned int tmp, i; 7007 7008 /* 7009 * Gotta run these twice, or else mic works inconsistently. Not clear 7010 * why this is, but multiple tests have confirmed it. 7011 */ 7012 for (i = 0; i < 2; i++) { 7013 switch (ca0132_quirk(spec)) { 7014 case QUIRK_SBZ: 7015 case QUIRK_AE5: 7016 tmp = 0x00000003; 7017 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7018 tmp = 0x00000000; 7019 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp); 7020 tmp = 0x00000001; 7021 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp); 7022 tmp = 0x00000004; 7023 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7024 tmp = 0x00000005; 7025 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7026 tmp = 0x00000000; 7027 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7028 break; 7029 case QUIRK_R3D: 7030 case QUIRK_R3DI: 7031 tmp = 0x00000000; 7032 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp); 7033 tmp = 0x00000001; 7034 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp); 7035 tmp = 0x00000004; 7036 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7037 tmp = 0x00000005; 7038 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7039 tmp = 0x00000000; 7040 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7041 break; 7042 default: 7043 break; 7044 } 7045 msleep(100); 7046 } 7047 } 7048 7049 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec) 7050 { 7051 struct ca0132_spec *spec = codec->spec; 7052 unsigned int tmp; 7053 7054 chipio_set_stream_control(codec, 0x03, 0); 7055 chipio_set_stream_control(codec, 0x04, 0); 7056 7057 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7058 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7059 7060 tmp = FLOAT_THREE; 7061 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7062 7063 chipio_set_stream_control(codec, 0x03, 1); 7064 chipio_set_stream_control(codec, 0x04, 1); 7065 7066 switch (ca0132_quirk(spec)) { 7067 case QUIRK_SBZ: 7068 chipio_write(codec, 0x18b098, 0x0000000c); 7069 chipio_write(codec, 0x18b09C, 0x0000000c); 7070 break; 7071 case QUIRK_AE5: 7072 chipio_write(codec, 0x18b098, 0x0000000c); 7073 chipio_write(codec, 0x18b09c, 0x0000004c); 7074 break; 7075 default: 7076 break; 7077 } 7078 } 7079 7080 static void ae5_post_dsp_register_set(struct hda_codec *codec) 7081 { 7082 struct ca0132_spec *spec = codec->spec; 7083 7084 chipio_8051_write_direct(codec, 0x93, 0x10); 7085 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7086 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44); 7087 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7088 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2); 7089 7090 writeb(0xff, spec->mem_base + 0x304); 7091 writeb(0xff, spec->mem_base + 0x304); 7092 writeb(0xff, spec->mem_base + 0x304); 7093 writeb(0xff, spec->mem_base + 0x304); 7094 writeb(0x00, spec->mem_base + 0x100); 7095 writeb(0xff, spec->mem_base + 0x304); 7096 writeb(0x00, spec->mem_base + 0x100); 7097 writeb(0xff, spec->mem_base + 0x304); 7098 writeb(0x00, spec->mem_base + 0x100); 7099 writeb(0xff, spec->mem_base + 0x304); 7100 writeb(0x00, spec->mem_base + 0x100); 7101 writeb(0xff, spec->mem_base + 0x304); 7102 7103 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f); 7104 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 7105 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7106 } 7107 7108 static void ae5_post_dsp_param_setup(struct hda_codec *codec) 7109 { 7110 /* 7111 * Param3 in the 8051's memory is represented by the ascii string 'mch' 7112 * which seems to be 'multichannel'. This is also mentioned in the 7113 * AE-5's registry values in Windows. 7114 */ 7115 chipio_set_control_param(codec, 3, 0); 7116 /* 7117 * I believe ASI is 'audio serial interface' and that it's used to 7118 * change colors on the external LED strip connected to the AE-5. 7119 */ 7120 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); 7121 7122 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); 7123 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 7124 7125 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7126 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92); 7127 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7128 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa); 7129 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7130 VENDOR_CHIPIO_8051_DATA_WRITE, 0x22); 7131 } 7132 7133 static void ae5_post_dsp_pll_setup(struct hda_codec *codec) 7134 { 7135 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7136 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41); 7137 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7138 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8); 7139 7140 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7141 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x45); 7142 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7143 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcc); 7144 7145 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7146 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x40); 7147 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7148 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcb); 7149 7150 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7151 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43); 7152 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7153 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7); 7154 7155 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7156 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x51); 7157 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7158 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x8d); 7159 } 7160 7161 static void ae5_post_dsp_stream_setup(struct hda_codec *codec) 7162 { 7163 struct ca0132_spec *spec = codec->spec; 7164 7165 mutex_lock(&spec->chipio_mutex); 7166 7167 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); 7168 7169 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); 7170 7171 chipio_set_stream_channels(codec, 0x0C, 6); 7172 chipio_set_stream_control(codec, 0x0C, 1); 7173 7174 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0); 7175 7176 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0); 7177 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 7178 chipio_set_stream_channels(codec, 0x18, 6); 7179 chipio_set_stream_control(codec, 0x18, 1); 7180 7181 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); 7182 7183 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7184 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43); 7185 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7186 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7); 7187 7188 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80); 7189 7190 mutex_unlock(&spec->chipio_mutex); 7191 } 7192 7193 static void ae5_post_dsp_startup_data(struct hda_codec *codec) 7194 { 7195 struct ca0132_spec *spec = codec->spec; 7196 7197 mutex_lock(&spec->chipio_mutex); 7198 7199 chipio_write_no_mutex(codec, 0x189000, 0x0001f101); 7200 chipio_write_no_mutex(codec, 0x189004, 0x0001f101); 7201 chipio_write_no_mutex(codec, 0x189024, 0x00014004); 7202 chipio_write_no_mutex(codec, 0x189028, 0x0002000f); 7203 7204 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 7205 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 7206 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12); 7207 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00); 7208 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48); 7209 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 7210 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7211 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 7212 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 7213 ca0113_mmio_gpio_set(codec, 0, true); 7214 ca0113_mmio_gpio_set(codec, 1, true); 7215 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80); 7216 7217 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012); 7218 7219 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 7220 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 7221 7222 mutex_unlock(&spec->chipio_mutex); 7223 } 7224 7225 /* 7226 * Setup default parameters for DSP 7227 */ 7228 static void ca0132_setup_defaults(struct hda_codec *codec) 7229 { 7230 struct ca0132_spec *spec = codec->spec; 7231 unsigned int tmp; 7232 int num_fx; 7233 int idx, i; 7234 7235 if (spec->dsp_state != DSP_DOWNLOADED) 7236 return; 7237 7238 /* out, in effects + voicefx */ 7239 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 7240 for (idx = 0; idx < num_fx; idx++) { 7241 for (i = 0; i <= ca0132_effects[idx].params; i++) { 7242 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 7243 ca0132_effects[idx].reqs[i], 7244 ca0132_effects[idx].def_vals[i]); 7245 } 7246 } 7247 7248 /*remove DSP headroom*/ 7249 tmp = FLOAT_ZERO; 7250 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 7251 7252 /*set speaker EQ bypass attenuation*/ 7253 dspio_set_uint_param(codec, 0x8f, 0x01, tmp); 7254 7255 /* set AMic1 and AMic2 as mono mic */ 7256 tmp = FLOAT_ONE; 7257 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7258 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 7259 7260 /* set AMic1 as CrystalVoice input */ 7261 tmp = FLOAT_ONE; 7262 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 7263 7264 /* set WUH source */ 7265 tmp = FLOAT_TWO; 7266 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 7267 } 7268 7269 /* 7270 * Setup default parameters for Recon3D/Recon3Di DSP. 7271 */ 7272 7273 static void r3d_setup_defaults(struct hda_codec *codec) 7274 { 7275 struct ca0132_spec *spec = codec->spec; 7276 unsigned int tmp; 7277 int num_fx; 7278 int idx, i; 7279 7280 if (spec->dsp_state != DSP_DOWNLOADED) 7281 return; 7282 7283 ca0132_alt_dsp_scp_startup(codec); 7284 ca0132_alt_init_analog_mics(codec); 7285 7286 /*remove DSP headroom*/ 7287 tmp = FLOAT_ZERO; 7288 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 7289 7290 /* set WUH source */ 7291 tmp = FLOAT_TWO; 7292 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 7293 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7294 7295 /* Set speaker source? */ 7296 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 7297 7298 if (ca0132_quirk(spec) == QUIRK_R3DI) 7299 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED); 7300 7301 /* Setup effect defaults */ 7302 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 7303 for (idx = 0; idx < num_fx; idx++) { 7304 for (i = 0; i <= ca0132_effects[idx].params; i++) { 7305 dspio_set_uint_param(codec, 7306 ca0132_effects[idx].mid, 7307 ca0132_effects[idx].reqs[i], 7308 ca0132_effects[idx].def_vals[i]); 7309 } 7310 } 7311 } 7312 7313 /* 7314 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on 7315 * than the Chromebook setup. 7316 */ 7317 static void sbz_setup_defaults(struct hda_codec *codec) 7318 { 7319 struct ca0132_spec *spec = codec->spec; 7320 unsigned int tmp; 7321 int num_fx; 7322 int idx, i; 7323 7324 if (spec->dsp_state != DSP_DOWNLOADED) 7325 return; 7326 7327 ca0132_alt_dsp_scp_startup(codec); 7328 ca0132_alt_init_analog_mics(codec); 7329 sbz_connect_streams(codec); 7330 sbz_chipio_startup_data(codec); 7331 7332 chipio_set_stream_control(codec, 0x03, 1); 7333 chipio_set_stream_control(codec, 0x04, 1); 7334 7335 /* 7336 * Sets internal input loopback to off, used to have a switch to 7337 * enable input loopback, but turned out to be way too buggy. 7338 */ 7339 tmp = FLOAT_ONE; 7340 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 7341 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 7342 7343 /*remove DSP headroom*/ 7344 tmp = FLOAT_ZERO; 7345 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 7346 7347 /* set WUH source */ 7348 tmp = FLOAT_TWO; 7349 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 7350 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7351 7352 /* Set speaker source? */ 7353 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 7354 7355 ca0132_alt_dsp_initial_mic_setup(codec); 7356 7357 /* out, in effects + voicefx */ 7358 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 7359 for (idx = 0; idx < num_fx; idx++) { 7360 for (i = 0; i <= ca0132_effects[idx].params; i++) { 7361 dspio_set_uint_param(codec, 7362 ca0132_effects[idx].mid, 7363 ca0132_effects[idx].reqs[i], 7364 ca0132_effects[idx].def_vals[i]); 7365 } 7366 } 7367 7368 ca0132_alt_create_dummy_stream(codec); 7369 } 7370 7371 /* 7372 * Setup default parameters for the Sound BlasterX AE-5 DSP. 7373 */ 7374 static void ae5_setup_defaults(struct hda_codec *codec) 7375 { 7376 struct ca0132_spec *spec = codec->spec; 7377 unsigned int tmp; 7378 int num_fx; 7379 int idx, i; 7380 7381 if (spec->dsp_state != DSP_DOWNLOADED) 7382 return; 7383 7384 ca0132_alt_dsp_scp_startup(codec); 7385 ca0132_alt_init_analog_mics(codec); 7386 chipio_set_stream_control(codec, 0x03, 1); 7387 chipio_set_stream_control(codec, 0x04, 1); 7388 7389 /* New, unknown SCP req's */ 7390 tmp = FLOAT_ZERO; 7391 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 7392 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 7393 dspio_set_uint_param(codec, 0x80, 0x0d, tmp); 7394 dspio_set_uint_param(codec, 0x80, 0x0e, tmp); 7395 7396 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 7397 ca0113_mmio_gpio_set(codec, 0, false); 7398 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 7399 7400 /* Internal loopback off */ 7401 tmp = FLOAT_ONE; 7402 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 7403 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 7404 7405 /*remove DSP headroom*/ 7406 tmp = FLOAT_ZERO; 7407 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 7408 7409 /* set WUH source */ 7410 tmp = FLOAT_TWO; 7411 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 7412 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7413 7414 /* Set speaker source? */ 7415 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 7416 7417 ca0132_alt_dsp_initial_mic_setup(codec); 7418 ae5_post_dsp_register_set(codec); 7419 ae5_post_dsp_param_setup(codec); 7420 ae5_post_dsp_pll_setup(codec); 7421 ae5_post_dsp_stream_setup(codec); 7422 ae5_post_dsp_startup_data(codec); 7423 7424 /* out, in effects + voicefx */ 7425 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 7426 for (idx = 0; idx < num_fx; idx++) { 7427 for (i = 0; i <= ca0132_effects[idx].params; i++) { 7428 dspio_set_uint_param(codec, 7429 ca0132_effects[idx].mid, 7430 ca0132_effects[idx].reqs[i], 7431 ca0132_effects[idx].def_vals[i]); 7432 } 7433 } 7434 7435 ca0132_alt_create_dummy_stream(codec); 7436 } 7437 7438 /* 7439 * Initialization of flags in chip 7440 */ 7441 static void ca0132_init_flags(struct hda_codec *codec) 7442 { 7443 struct ca0132_spec *spec = codec->spec; 7444 7445 if (ca0132_use_alt_functions(spec)) { 7446 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1); 7447 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1); 7448 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1); 7449 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1); 7450 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1); 7451 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 7452 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0); 7453 chipio_set_control_flag(codec, 7454 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 7455 chipio_set_control_flag(codec, 7456 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1); 7457 } else { 7458 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 7459 chipio_set_control_flag(codec, 7460 CONTROL_FLAG_PORT_A_COMMON_MODE, 0); 7461 chipio_set_control_flag(codec, 7462 CONTROL_FLAG_PORT_D_COMMON_MODE, 0); 7463 chipio_set_control_flag(codec, 7464 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0); 7465 chipio_set_control_flag(codec, 7466 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 7467 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1); 7468 } 7469 } 7470 7471 /* 7472 * Initialization of parameters in chip 7473 */ 7474 static void ca0132_init_params(struct hda_codec *codec) 7475 { 7476 struct ca0132_spec *spec = codec->spec; 7477 7478 if (ca0132_use_alt_functions(spec)) { 7479 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7480 chipio_set_conn_rate(codec, 0x0B, SR_48_000); 7481 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0); 7482 chipio_set_control_param(codec, 0, 0); 7483 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 7484 } 7485 7486 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6); 7487 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6); 7488 } 7489 7490 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k) 7491 { 7492 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k); 7493 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k); 7494 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k); 7495 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k); 7496 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k); 7497 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k); 7498 7499 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7500 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7501 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7502 } 7503 7504 static bool ca0132_download_dsp_images(struct hda_codec *codec) 7505 { 7506 bool dsp_loaded = false; 7507 struct ca0132_spec *spec = codec->spec; 7508 const struct dsp_image_seg *dsp_os_image; 7509 const struct firmware *fw_entry = NULL; 7510 /* 7511 * Alternate firmwares for different variants. The Recon3Di apparently 7512 * can use the default firmware, but I'll leave the option in case 7513 * it needs it again. 7514 */ 7515 switch (ca0132_quirk(spec)) { 7516 case QUIRK_SBZ: 7517 case QUIRK_R3D: 7518 case QUIRK_AE5: 7519 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE, 7520 codec->card->dev) != 0) 7521 codec_dbg(codec, "Desktop firmware not found."); 7522 else 7523 codec_dbg(codec, "Desktop firmware selected."); 7524 break; 7525 case QUIRK_R3DI: 7526 if (request_firmware(&fw_entry, R3DI_EFX_FILE, 7527 codec->card->dev) != 0) 7528 codec_dbg(codec, "Recon3Di alt firmware not detected."); 7529 else 7530 codec_dbg(codec, "Recon3Di firmware selected."); 7531 break; 7532 default: 7533 break; 7534 } 7535 /* 7536 * Use default ctefx.bin if no alt firmware is detected, or if none 7537 * exists for your particular codec. 7538 */ 7539 if (!fw_entry) { 7540 codec_dbg(codec, "Default firmware selected."); 7541 if (request_firmware(&fw_entry, EFX_FILE, 7542 codec->card->dev) != 0) 7543 return false; 7544 } 7545 7546 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data); 7547 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) { 7548 codec_err(codec, "ca0132 DSP load image failed\n"); 7549 goto exit_download; 7550 } 7551 7552 dsp_loaded = dspload_wait_loaded(codec); 7553 7554 exit_download: 7555 release_firmware(fw_entry); 7556 7557 return dsp_loaded; 7558 } 7559 7560 static void ca0132_download_dsp(struct hda_codec *codec) 7561 { 7562 struct ca0132_spec *spec = codec->spec; 7563 7564 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP 7565 return; /* NOP */ 7566 #endif 7567 7568 if (spec->dsp_state == DSP_DOWNLOAD_FAILED) 7569 return; /* don't retry failures */ 7570 7571 chipio_enable_clocks(codec); 7572 if (spec->dsp_state != DSP_DOWNLOADED) { 7573 spec->dsp_state = DSP_DOWNLOADING; 7574 7575 if (!ca0132_download_dsp_images(codec)) 7576 spec->dsp_state = DSP_DOWNLOAD_FAILED; 7577 else 7578 spec->dsp_state = DSP_DOWNLOADED; 7579 } 7580 7581 /* For codecs using alt functions, this is already done earlier */ 7582 if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec)) 7583 ca0132_set_dsp_msr(codec, true); 7584 } 7585 7586 static void ca0132_process_dsp_response(struct hda_codec *codec, 7587 struct hda_jack_callback *callback) 7588 { 7589 struct ca0132_spec *spec = codec->spec; 7590 7591 codec_dbg(codec, "ca0132_process_dsp_response\n"); 7592 snd_hda_power_up_pm(codec); 7593 if (spec->wait_scp) { 7594 if (dspio_get_response_data(codec) >= 0) 7595 spec->wait_scp = 0; 7596 } 7597 7598 dspio_clear_response_queue(codec); 7599 snd_hda_power_down_pm(codec); 7600 } 7601 7602 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 7603 { 7604 struct ca0132_spec *spec = codec->spec; 7605 struct hda_jack_tbl *tbl; 7606 7607 /* Delay enabling the HP amp, to let the mic-detection 7608 * state machine run. 7609 */ 7610 tbl = snd_hda_jack_tbl_get(codec, cb->nid); 7611 if (tbl) 7612 tbl->block_report = 1; 7613 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500)); 7614 } 7615 7616 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 7617 { 7618 struct ca0132_spec *spec = codec->spec; 7619 7620 if (ca0132_use_alt_functions(spec)) 7621 ca0132_alt_select_in(codec); 7622 else 7623 ca0132_select_mic(codec); 7624 } 7625 7626 static void ca0132_init_unsol(struct hda_codec *codec) 7627 { 7628 struct ca0132_spec *spec = codec->spec; 7629 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback); 7630 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1, 7631 amic_callback); 7632 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP, 7633 ca0132_process_dsp_response); 7634 /* Front headphone jack detection */ 7635 if (ca0132_use_alt_functions(spec)) 7636 snd_hda_jack_detect_enable_callback(codec, 7637 spec->unsol_tag_front_hp, hp_callback); 7638 } 7639 7640 /* 7641 * Verbs tables. 7642 */ 7643 7644 /* Sends before DSP download. */ 7645 static struct hda_verb ca0132_base_init_verbs[] = { 7646 /*enable ct extension*/ 7647 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1}, 7648 {} 7649 }; 7650 7651 /* Send at exit. */ 7652 static struct hda_verb ca0132_base_exit_verbs[] = { 7653 /*set afg to D3*/ 7654 {0x01, AC_VERB_SET_POWER_STATE, 0x03}, 7655 /*disable ct extension*/ 7656 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0}, 7657 {} 7658 }; 7659 7660 /* Other verbs tables. Sends after DSP download. */ 7661 7662 static struct hda_verb ca0132_init_verbs0[] = { 7663 /* chip init verbs */ 7664 {0x15, 0x70D, 0xF0}, 7665 {0x15, 0x70E, 0xFE}, 7666 {0x15, 0x707, 0x75}, 7667 {0x15, 0x707, 0xD3}, 7668 {0x15, 0x707, 0x09}, 7669 {0x15, 0x707, 0x53}, 7670 {0x15, 0x707, 0xD4}, 7671 {0x15, 0x707, 0xEF}, 7672 {0x15, 0x707, 0x75}, 7673 {0x15, 0x707, 0xD3}, 7674 {0x15, 0x707, 0x09}, 7675 {0x15, 0x707, 0x02}, 7676 {0x15, 0x707, 0x37}, 7677 {0x15, 0x707, 0x78}, 7678 {0x15, 0x53C, 0xCE}, 7679 {0x15, 0x575, 0xC9}, 7680 {0x15, 0x53D, 0xCE}, 7681 {0x15, 0x5B7, 0xC9}, 7682 {0x15, 0x70D, 0xE8}, 7683 {0x15, 0x70E, 0xFE}, 7684 {0x15, 0x707, 0x02}, 7685 {0x15, 0x707, 0x68}, 7686 {0x15, 0x707, 0x62}, 7687 {0x15, 0x53A, 0xCE}, 7688 {0x15, 0x546, 0xC9}, 7689 {0x15, 0x53B, 0xCE}, 7690 {0x15, 0x5E8, 0xC9}, 7691 {} 7692 }; 7693 7694 /* Extra init verbs for desktop cards. */ 7695 static struct hda_verb ca0132_init_verbs1[] = { 7696 {0x15, 0x70D, 0x20}, 7697 {0x15, 0x70E, 0x19}, 7698 {0x15, 0x707, 0x00}, 7699 {0x15, 0x539, 0xCE}, 7700 {0x15, 0x546, 0xC9}, 7701 {0x15, 0x70D, 0xB7}, 7702 {0x15, 0x70E, 0x09}, 7703 {0x15, 0x707, 0x10}, 7704 {0x15, 0x70D, 0xAF}, 7705 {0x15, 0x70E, 0x09}, 7706 {0x15, 0x707, 0x01}, 7707 {0x15, 0x707, 0x05}, 7708 {0x15, 0x70D, 0x73}, 7709 {0x15, 0x70E, 0x09}, 7710 {0x15, 0x707, 0x14}, 7711 {0x15, 0x6FF, 0xC4}, 7712 {} 7713 }; 7714 7715 static void ca0132_init_chip(struct hda_codec *codec) 7716 { 7717 struct ca0132_spec *spec = codec->spec; 7718 int num_fx; 7719 int i; 7720 unsigned int on; 7721 7722 mutex_init(&spec->chipio_mutex); 7723 7724 spec->cur_out_type = SPEAKER_OUT; 7725 if (!ca0132_use_alt_functions(spec)) 7726 spec->cur_mic_type = DIGITAL_MIC; 7727 else 7728 spec->cur_mic_type = REAR_MIC; 7729 7730 spec->cur_mic_boost = 0; 7731 7732 for (i = 0; i < VNODES_COUNT; i++) { 7733 spec->vnode_lvol[i] = 0x5a; 7734 spec->vnode_rvol[i] = 0x5a; 7735 spec->vnode_lswitch[i] = 0; 7736 spec->vnode_rswitch[i] = 0; 7737 } 7738 7739 /* 7740 * Default states for effects are in ca0132_effects[]. 7741 */ 7742 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 7743 for (i = 0; i < num_fx; i++) { 7744 on = (unsigned int)ca0132_effects[i].reqs[0]; 7745 spec->effects_switch[i] = on ? 1 : 0; 7746 } 7747 /* 7748 * Sets defaults for the effect slider controls, only for alternative 7749 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz. 7750 */ 7751 if (ca0132_use_alt_controls(spec)) { 7752 spec->xbass_xover_freq = 8; 7753 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++) 7754 spec->fx_ctl_val[i] = effect_slider_defaults[i]; 7755 } 7756 7757 spec->voicefx_val = 0; 7758 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1; 7759 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0; 7760 7761 /* 7762 * The ZxR doesn't have a front panel header, and it's line-in is on 7763 * the daughter board. So, there is no input enum control, and we need 7764 * to make sure that spec->in_enum_val is set properly. 7765 */ 7766 if (ca0132_quirk(spec) == QUIRK_ZXR) 7767 spec->in_enum_val = REAR_MIC; 7768 7769 #ifdef ENABLE_TUNING_CONTROLS 7770 ca0132_init_tuning_defaults(codec); 7771 #endif 7772 } 7773 7774 /* 7775 * Recon3Di exit specific commands. 7776 */ 7777 /* prevents popping noise on shutdown */ 7778 static void r3di_gpio_shutdown(struct hda_codec *codec) 7779 { 7780 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00); 7781 } 7782 7783 /* 7784 * Sound Blaster Z exit specific commands. 7785 */ 7786 static void sbz_region2_exit(struct hda_codec *codec) 7787 { 7788 struct ca0132_spec *spec = codec->spec; 7789 unsigned int i; 7790 7791 for (i = 0; i < 4; i++) 7792 writeb(0x0, spec->mem_base + 0x100); 7793 for (i = 0; i < 8; i++) 7794 writeb(0xb3, spec->mem_base + 0x304); 7795 7796 ca0113_mmio_gpio_set(codec, 0, false); 7797 ca0113_mmio_gpio_set(codec, 1, false); 7798 ca0113_mmio_gpio_set(codec, 4, true); 7799 ca0113_mmio_gpio_set(codec, 5, false); 7800 ca0113_mmio_gpio_set(codec, 7, false); 7801 } 7802 7803 static void sbz_set_pin_ctl_default(struct hda_codec *codec) 7804 { 7805 hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13}; 7806 unsigned int i; 7807 7808 snd_hda_codec_write(codec, 0x11, 0, 7809 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40); 7810 7811 for (i = 0; i < 5; i++) 7812 snd_hda_codec_write(codec, pins[i], 0, 7813 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00); 7814 } 7815 7816 static void ca0132_clear_unsolicited(struct hda_codec *codec) 7817 { 7818 hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13}; 7819 unsigned int i; 7820 7821 for (i = 0; i < 7; i++) { 7822 snd_hda_codec_write(codec, pins[i], 0, 7823 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00); 7824 } 7825 } 7826 7827 /* On shutdown, sends commands in sets of three */ 7828 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir, 7829 int mask, int data) 7830 { 7831 if (dir >= 0) 7832 snd_hda_codec_write(codec, 0x01, 0, 7833 AC_VERB_SET_GPIO_DIRECTION, dir); 7834 if (mask >= 0) 7835 snd_hda_codec_write(codec, 0x01, 0, 7836 AC_VERB_SET_GPIO_MASK, mask); 7837 7838 if (data >= 0) 7839 snd_hda_codec_write(codec, 0x01, 0, 7840 AC_VERB_SET_GPIO_DATA, data); 7841 } 7842 7843 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec) 7844 { 7845 hda_nid_t pins[7] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01}; 7846 unsigned int i; 7847 7848 for (i = 0; i < 7; i++) 7849 snd_hda_codec_write(codec, pins[i], 0, 7850 AC_VERB_SET_POWER_STATE, 0x03); 7851 } 7852 7853 static void sbz_exit_chip(struct hda_codec *codec) 7854 { 7855 chipio_set_stream_control(codec, 0x03, 0); 7856 chipio_set_stream_control(codec, 0x04, 0); 7857 7858 /* Mess with GPIO */ 7859 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1); 7860 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05); 7861 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01); 7862 7863 chipio_set_stream_control(codec, 0x14, 0); 7864 chipio_set_stream_control(codec, 0x0C, 0); 7865 7866 chipio_set_conn_rate(codec, 0x41, SR_192_000); 7867 chipio_set_conn_rate(codec, 0x91, SR_192_000); 7868 7869 chipio_write(codec, 0x18a020, 0x00000083); 7870 7871 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03); 7872 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07); 7873 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06); 7874 7875 chipio_set_stream_control(codec, 0x0C, 0); 7876 7877 chipio_set_control_param(codec, 0x0D, 0x24); 7878 7879 ca0132_clear_unsolicited(codec); 7880 sbz_set_pin_ctl_default(codec); 7881 7882 snd_hda_codec_write(codec, 0x0B, 0, 7883 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 7884 7885 sbz_region2_exit(codec); 7886 } 7887 7888 static void r3d_exit_chip(struct hda_codec *codec) 7889 { 7890 ca0132_clear_unsolicited(codec); 7891 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 7892 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b); 7893 } 7894 7895 static void ae5_exit_chip(struct hda_codec *codec) 7896 { 7897 chipio_set_stream_control(codec, 0x03, 0); 7898 chipio_set_stream_control(codec, 0x04, 0); 7899 7900 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 7901 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7902 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7903 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 7904 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 7905 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00); 7906 ca0113_mmio_gpio_set(codec, 0, false); 7907 ca0113_mmio_gpio_set(codec, 1, false); 7908 7909 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 7910 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 7911 7912 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 7913 7914 chipio_set_stream_control(codec, 0x18, 0); 7915 chipio_set_stream_control(codec, 0x0c, 0); 7916 7917 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83); 7918 } 7919 7920 static void zxr_exit_chip(struct hda_codec *codec) 7921 { 7922 chipio_set_stream_control(codec, 0x03, 0); 7923 chipio_set_stream_control(codec, 0x04, 0); 7924 chipio_set_stream_control(codec, 0x14, 0); 7925 chipio_set_stream_control(codec, 0x0C, 0); 7926 7927 chipio_set_conn_rate(codec, 0x41, SR_192_000); 7928 chipio_set_conn_rate(codec, 0x91, SR_192_000); 7929 7930 chipio_write(codec, 0x18a020, 0x00000083); 7931 7932 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 7933 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 7934 7935 ca0132_clear_unsolicited(codec); 7936 sbz_set_pin_ctl_default(codec); 7937 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00); 7938 7939 ca0113_mmio_gpio_set(codec, 5, false); 7940 ca0113_mmio_gpio_set(codec, 2, false); 7941 ca0113_mmio_gpio_set(codec, 3, false); 7942 ca0113_mmio_gpio_set(codec, 0, false); 7943 ca0113_mmio_gpio_set(codec, 4, true); 7944 ca0113_mmio_gpio_set(codec, 0, true); 7945 ca0113_mmio_gpio_set(codec, 5, true); 7946 ca0113_mmio_gpio_set(codec, 2, false); 7947 ca0113_mmio_gpio_set(codec, 3, false); 7948 } 7949 7950 static void ca0132_exit_chip(struct hda_codec *codec) 7951 { 7952 /* put any chip cleanup stuffs here. */ 7953 7954 if (dspload_is_loaded(codec)) 7955 dsp_reset(codec); 7956 } 7957 7958 /* 7959 * This fixes a problem that was hard to reproduce. Very rarely, I would 7960 * boot up, and there would be no sound, but the DSP indicated it had loaded 7961 * properly. I did a few memory dumps to see if anything was different, and 7962 * there were a few areas of memory uninitialized with a1a2a3a4. This function 7963 * checks if those areas are uninitialized, and if they are, it'll attempt to 7964 * reload the card 3 times. Usually it fixes by the second. 7965 */ 7966 static void sbz_dsp_startup_check(struct hda_codec *codec) 7967 { 7968 struct ca0132_spec *spec = codec->spec; 7969 unsigned int dsp_data_check[4]; 7970 unsigned int cur_address = 0x390; 7971 unsigned int i; 7972 unsigned int failure = 0; 7973 unsigned int reload = 3; 7974 7975 if (spec->startup_check_entered) 7976 return; 7977 7978 spec->startup_check_entered = true; 7979 7980 for (i = 0; i < 4; i++) { 7981 chipio_read(codec, cur_address, &dsp_data_check[i]); 7982 cur_address += 0x4; 7983 } 7984 for (i = 0; i < 4; i++) { 7985 if (dsp_data_check[i] == 0xa1a2a3a4) 7986 failure = 1; 7987 } 7988 7989 codec_dbg(codec, "Startup Check: %d ", failure); 7990 if (failure) 7991 codec_info(codec, "DSP not initialized properly. Attempting to fix."); 7992 /* 7993 * While the failure condition is true, and we haven't reached our 7994 * three reload limit, continue trying to reload the driver and 7995 * fix the issue. 7996 */ 7997 while (failure && (reload != 0)) { 7998 codec_info(codec, "Reloading... Tries left: %d", reload); 7999 sbz_exit_chip(codec); 8000 spec->dsp_state = DSP_DOWNLOAD_INIT; 8001 codec->patch_ops.init(codec); 8002 failure = 0; 8003 for (i = 0; i < 4; i++) { 8004 chipio_read(codec, cur_address, &dsp_data_check[i]); 8005 cur_address += 0x4; 8006 } 8007 for (i = 0; i < 4; i++) { 8008 if (dsp_data_check[i] == 0xa1a2a3a4) 8009 failure = 1; 8010 } 8011 reload--; 8012 } 8013 8014 if (!failure && reload < 3) 8015 codec_info(codec, "DSP fixed."); 8016 8017 if (!failure) 8018 return; 8019 8020 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory."); 8021 } 8022 8023 /* 8024 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add 8025 * extra precision for decibel values. If you had the dB value in floating point 8026 * you would take the value after the decimal point, multiply by 64, and divide 8027 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to 8028 * implement fixed point or floating point dB volumes. For now, I'll set them 8029 * to 0 just incase a value has lingered from a boot into Windows. 8030 */ 8031 static void ca0132_alt_vol_setup(struct hda_codec *codec) 8032 { 8033 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00); 8034 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00); 8035 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00); 8036 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00); 8037 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00); 8038 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00); 8039 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00); 8040 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00); 8041 } 8042 8043 /* 8044 * Extra commands that don't really fit anywhere else. 8045 */ 8046 static void sbz_pre_dsp_setup(struct hda_codec *codec) 8047 { 8048 struct ca0132_spec *spec = codec->spec; 8049 8050 writel(0x00820680, spec->mem_base + 0x01C); 8051 writel(0x00820680, spec->mem_base + 0x01C); 8052 8053 chipio_write(codec, 0x18b0a4, 0x000000c2); 8054 8055 snd_hda_codec_write(codec, 0x11, 0, 8056 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 8057 } 8058 8059 static void r3d_pre_dsp_setup(struct hda_codec *codec) 8060 { 8061 chipio_write(codec, 0x18b0a4, 0x000000c2); 8062 8063 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8064 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E); 8065 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8066 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C); 8067 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8068 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B); 8069 8070 snd_hda_codec_write(codec, 0x11, 0, 8071 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 8072 } 8073 8074 static void r3di_pre_dsp_setup(struct hda_codec *codec) 8075 { 8076 chipio_write(codec, 0x18b0a4, 0x000000c2); 8077 8078 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8079 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E); 8080 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8081 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C); 8082 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8083 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B); 8084 8085 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8086 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); 8087 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8088 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 8089 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8090 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 8091 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8092 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40); 8093 8094 snd_hda_codec_write(codec, 0x11, 0, 8095 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04); 8096 } 8097 8098 /* 8099 * These are sent before the DSP is downloaded. Not sure 8100 * what they do, or if they're necessary. Could possibly 8101 * be removed. Figure they're better to leave in. 8102 */ 8103 static void ca0132_mmio_init(struct hda_codec *codec) 8104 { 8105 struct ca0132_spec *spec = codec->spec; 8106 8107 if (ca0132_quirk(spec) == QUIRK_AE5) 8108 writel(0x00000001, spec->mem_base + 0x400); 8109 else 8110 writel(0x00000000, spec->mem_base + 0x400); 8111 8112 if (ca0132_quirk(spec) == QUIRK_AE5) 8113 writel(0x00000001, spec->mem_base + 0x408); 8114 else 8115 writel(0x00000000, spec->mem_base + 0x408); 8116 8117 if (ca0132_quirk(spec) == QUIRK_AE5) 8118 writel(0x00000001, spec->mem_base + 0x40c); 8119 else 8120 writel(0x00000000, spec->mem_base + 0x40C); 8121 8122 if (ca0132_quirk(spec) == QUIRK_ZXR) 8123 writel(0x00880640, spec->mem_base + 0x01C); 8124 else 8125 writel(0x00880680, spec->mem_base + 0x01C); 8126 8127 if (ca0132_quirk(spec) == QUIRK_AE5) 8128 writel(0x00000080, spec->mem_base + 0xC0C); 8129 else 8130 writel(0x00000083, spec->mem_base + 0xC0C); 8131 8132 writel(0x00000030, spec->mem_base + 0xC00); 8133 writel(0x00000000, spec->mem_base + 0xC04); 8134 8135 if (ca0132_quirk(spec) == QUIRK_AE5) 8136 writel(0x00000000, spec->mem_base + 0xC0C); 8137 else 8138 writel(0x00000003, spec->mem_base + 0xC0C); 8139 8140 writel(0x00000003, spec->mem_base + 0xC0C); 8141 writel(0x00000003, spec->mem_base + 0xC0C); 8142 writel(0x00000003, spec->mem_base + 0xC0C); 8143 8144 if (ca0132_quirk(spec) == QUIRK_AE5) 8145 writel(0x00000001, spec->mem_base + 0xC08); 8146 else 8147 writel(0x000000C1, spec->mem_base + 0xC08); 8148 8149 writel(0x000000F1, spec->mem_base + 0xC08); 8150 writel(0x00000001, spec->mem_base + 0xC08); 8151 writel(0x000000C7, spec->mem_base + 0xC08); 8152 writel(0x000000C1, spec->mem_base + 0xC08); 8153 writel(0x00000080, spec->mem_base + 0xC04); 8154 8155 if (ca0132_quirk(spec) == QUIRK_AE5) { 8156 writel(0x00000000, spec->mem_base + 0x42c); 8157 writel(0x00000000, spec->mem_base + 0x46c); 8158 writel(0x00000000, spec->mem_base + 0x4ac); 8159 writel(0x00000000, spec->mem_base + 0x4ec); 8160 writel(0x00000000, spec->mem_base + 0x43c); 8161 writel(0x00000000, spec->mem_base + 0x47c); 8162 writel(0x00000000, spec->mem_base + 0x4bc); 8163 writel(0x00000000, spec->mem_base + 0x4fc); 8164 writel(0x00000600, spec->mem_base + 0x100); 8165 writel(0x00000014, spec->mem_base + 0x410); 8166 writel(0x0000060f, spec->mem_base + 0x100); 8167 writel(0x0000070f, spec->mem_base + 0x100); 8168 writel(0x00000aff, spec->mem_base + 0x830); 8169 writel(0x00000000, spec->mem_base + 0x86c); 8170 writel(0x0000006b, spec->mem_base + 0x800); 8171 writel(0x00000001, spec->mem_base + 0x86c); 8172 writel(0x0000006b, spec->mem_base + 0x800); 8173 writel(0x00000057, spec->mem_base + 0x804); 8174 writel(0x00800000, spec->mem_base + 0x20c); 8175 } 8176 } 8177 8178 /* 8179 * This function writes to some SFR's, does some region2 writes, and then 8180 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does 8181 * what it does. 8182 */ 8183 static void ae5_register_set(struct hda_codec *codec) 8184 { 8185 struct ca0132_spec *spec = codec->spec; 8186 8187 chipio_8051_write_direct(codec, 0x93, 0x10); 8188 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8189 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44); 8190 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8191 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2); 8192 8193 writeb(0x0f, spec->mem_base + 0x304); 8194 writeb(0x0f, spec->mem_base + 0x304); 8195 writeb(0x0f, spec->mem_base + 0x304); 8196 writeb(0x0f, spec->mem_base + 0x304); 8197 writeb(0x0e, spec->mem_base + 0x100); 8198 writeb(0x1f, spec->mem_base + 0x304); 8199 writeb(0x0c, spec->mem_base + 0x100); 8200 writeb(0x3f, spec->mem_base + 0x304); 8201 writeb(0x08, spec->mem_base + 0x100); 8202 writeb(0x7f, spec->mem_base + 0x304); 8203 writeb(0x00, spec->mem_base + 0x100); 8204 writeb(0xff, spec->mem_base + 0x304); 8205 8206 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 8207 8208 chipio_8051_write_direct(codec, 0x90, 0x00); 8209 chipio_8051_write_direct(codec, 0x90, 0x10); 8210 8211 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8212 8213 chipio_write(codec, 0x18b0a4, 0x000000c2); 8214 8215 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00); 8216 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00); 8217 } 8218 8219 /* 8220 * Extra init functions for alternative ca0132 codecs. Done 8221 * here so they don't clutter up the main ca0132_init function 8222 * anymore than they have to. 8223 */ 8224 static void ca0132_alt_init(struct hda_codec *codec) 8225 { 8226 struct ca0132_spec *spec = codec->spec; 8227 8228 ca0132_alt_vol_setup(codec); 8229 8230 switch (ca0132_quirk(spec)) { 8231 case QUIRK_SBZ: 8232 codec_dbg(codec, "SBZ alt_init"); 8233 ca0132_gpio_init(codec); 8234 sbz_pre_dsp_setup(codec); 8235 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8236 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 8237 break; 8238 case QUIRK_R3DI: 8239 codec_dbg(codec, "R3DI alt_init"); 8240 ca0132_gpio_init(codec); 8241 ca0132_gpio_setup(codec); 8242 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING); 8243 r3di_pre_dsp_setup(codec); 8244 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8245 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4); 8246 break; 8247 case QUIRK_R3D: 8248 r3d_pre_dsp_setup(codec); 8249 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8250 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 8251 break; 8252 case QUIRK_AE5: 8253 ca0132_gpio_init(codec); 8254 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8255 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49); 8256 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8257 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88); 8258 chipio_write(codec, 0x18b030, 0x00000020); 8259 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8260 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 8261 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 8262 break; 8263 case QUIRK_ZXR: 8264 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8265 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 8266 break; 8267 default: 8268 break; 8269 } 8270 } 8271 8272 static int ca0132_init(struct hda_codec *codec) 8273 { 8274 struct ca0132_spec *spec = codec->spec; 8275 struct auto_pin_cfg *cfg = &spec->autocfg; 8276 int i; 8277 bool dsp_loaded; 8278 8279 /* 8280 * If the DSP is already downloaded, and init has been entered again, 8281 * there's only two reasons for it. One, the codec has awaken from a 8282 * suspended state, and in that case dspload_is_loaded will return 8283 * false, and the init will be ran again. The other reason it gets 8284 * re entered is on startup for some reason it triggers a suspend and 8285 * resume state. In this case, it will check if the DSP is downloaded, 8286 * and not run the init function again. For codecs using alt_functions, 8287 * it will check if the DSP is loaded properly. 8288 */ 8289 if (spec->dsp_state == DSP_DOWNLOADED) { 8290 dsp_loaded = dspload_is_loaded(codec); 8291 if (!dsp_loaded) { 8292 spec->dsp_reload = true; 8293 spec->dsp_state = DSP_DOWNLOAD_INIT; 8294 } else { 8295 if (ca0132_quirk(spec) == QUIRK_SBZ) 8296 sbz_dsp_startup_check(codec); 8297 return 0; 8298 } 8299 } 8300 8301 if (spec->dsp_state != DSP_DOWNLOAD_FAILED) 8302 spec->dsp_state = DSP_DOWNLOAD_INIT; 8303 spec->curr_chip_addx = INVALID_CHIP_ADDRESS; 8304 8305 if (ca0132_use_pci_mmio(spec)) 8306 ca0132_mmio_init(codec); 8307 8308 snd_hda_power_up_pm(codec); 8309 8310 if (ca0132_quirk(spec) == QUIRK_AE5) 8311 ae5_register_set(codec); 8312 8313 ca0132_init_unsol(codec); 8314 ca0132_init_params(codec); 8315 ca0132_init_flags(codec); 8316 8317 snd_hda_sequence_write(codec, spec->base_init_verbs); 8318 8319 if (ca0132_use_alt_functions(spec)) 8320 ca0132_alt_init(codec); 8321 8322 ca0132_download_dsp(codec); 8323 8324 ca0132_refresh_widget_caps(codec); 8325 8326 switch (ca0132_quirk(spec)) { 8327 case QUIRK_R3DI: 8328 case QUIRK_R3D: 8329 r3d_setup_defaults(codec); 8330 break; 8331 case QUIRK_SBZ: 8332 case QUIRK_ZXR: 8333 sbz_setup_defaults(codec); 8334 break; 8335 case QUIRK_AE5: 8336 ae5_setup_defaults(codec); 8337 break; 8338 default: 8339 ca0132_setup_defaults(codec); 8340 ca0132_init_analog_mic2(codec); 8341 ca0132_init_dmic(codec); 8342 break; 8343 } 8344 8345 for (i = 0; i < spec->num_outputs; i++) 8346 init_output(codec, spec->out_pins[i], spec->dacs[0]); 8347 8348 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 8349 8350 for (i = 0; i < spec->num_inputs; i++) 8351 init_input(codec, spec->input_pins[i], spec->adcs[i]); 8352 8353 init_input(codec, cfg->dig_in_pin, spec->dig_in); 8354 8355 if (!ca0132_use_alt_functions(spec)) { 8356 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8357 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8358 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D); 8359 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8360 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20); 8361 } 8362 8363 if (ca0132_quirk(spec) == QUIRK_SBZ) 8364 ca0132_gpio_setup(codec); 8365 8366 snd_hda_sequence_write(codec, spec->spec_init_verbs); 8367 if (ca0132_use_alt_functions(spec)) { 8368 ca0132_alt_select_out(codec); 8369 ca0132_alt_select_in(codec); 8370 } else { 8371 ca0132_select_out(codec); 8372 ca0132_select_mic(codec); 8373 } 8374 8375 snd_hda_jack_report_sync(codec); 8376 8377 /* 8378 * Re set the PlayEnhancement switch on a resume event, because the 8379 * controls will not be reloaded. 8380 */ 8381 if (spec->dsp_reload) { 8382 spec->dsp_reload = false; 8383 ca0132_pe_switch_set(codec); 8384 } 8385 8386 snd_hda_power_down_pm(codec); 8387 8388 return 0; 8389 } 8390 8391 static int dbpro_init(struct hda_codec *codec) 8392 { 8393 struct ca0132_spec *spec = codec->spec; 8394 struct auto_pin_cfg *cfg = &spec->autocfg; 8395 unsigned int i; 8396 8397 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 8398 init_input(codec, cfg->dig_in_pin, spec->dig_in); 8399 8400 for (i = 0; i < spec->num_inputs; i++) 8401 init_input(codec, spec->input_pins[i], spec->adcs[i]); 8402 8403 return 0; 8404 } 8405 8406 static void ca0132_free(struct hda_codec *codec) 8407 { 8408 struct ca0132_spec *spec = codec->spec; 8409 8410 cancel_delayed_work_sync(&spec->unsol_hp_work); 8411 snd_hda_power_up(codec); 8412 switch (ca0132_quirk(spec)) { 8413 case QUIRK_SBZ: 8414 sbz_exit_chip(codec); 8415 break; 8416 case QUIRK_ZXR: 8417 zxr_exit_chip(codec); 8418 break; 8419 case QUIRK_R3D: 8420 r3d_exit_chip(codec); 8421 break; 8422 case QUIRK_AE5: 8423 ae5_exit_chip(codec); 8424 break; 8425 case QUIRK_R3DI: 8426 r3di_gpio_shutdown(codec); 8427 break; 8428 default: 8429 break; 8430 } 8431 8432 snd_hda_sequence_write(codec, spec->base_exit_verbs); 8433 ca0132_exit_chip(codec); 8434 8435 snd_hda_power_down(codec); 8436 #ifdef CONFIG_PCI 8437 if (spec->mem_base) 8438 pci_iounmap(codec->bus->pci, spec->mem_base); 8439 #endif 8440 kfree(spec->spec_init_verbs); 8441 kfree(codec->spec); 8442 } 8443 8444 static void dbpro_free(struct hda_codec *codec) 8445 { 8446 struct ca0132_spec *spec = codec->spec; 8447 8448 zxr_dbpro_power_state_shutdown(codec); 8449 8450 kfree(spec->spec_init_verbs); 8451 kfree(codec->spec); 8452 } 8453 8454 static void ca0132_reboot_notify(struct hda_codec *codec) 8455 { 8456 codec->patch_ops.free(codec); 8457 } 8458 8459 #ifdef CONFIG_PM 8460 static int ca0132_suspend(struct hda_codec *codec) 8461 { 8462 struct ca0132_spec *spec = codec->spec; 8463 8464 cancel_delayed_work_sync(&spec->unsol_hp_work); 8465 return 0; 8466 } 8467 #endif 8468 8469 static const struct hda_codec_ops ca0132_patch_ops = { 8470 .build_controls = ca0132_build_controls, 8471 .build_pcms = ca0132_build_pcms, 8472 .init = ca0132_init, 8473 .free = ca0132_free, 8474 .unsol_event = snd_hda_jack_unsol_event, 8475 #ifdef CONFIG_PM 8476 .suspend = ca0132_suspend, 8477 #endif 8478 .reboot_notify = ca0132_reboot_notify, 8479 }; 8480 8481 static const struct hda_codec_ops dbpro_patch_ops = { 8482 .build_controls = dbpro_build_controls, 8483 .build_pcms = dbpro_build_pcms, 8484 .init = dbpro_init, 8485 .free = dbpro_free, 8486 }; 8487 8488 static void ca0132_config(struct hda_codec *codec) 8489 { 8490 struct ca0132_spec *spec = codec->spec; 8491 8492 spec->dacs[0] = 0x2; 8493 spec->dacs[1] = 0x3; 8494 spec->dacs[2] = 0x4; 8495 8496 spec->multiout.dac_nids = spec->dacs; 8497 spec->multiout.num_dacs = 3; 8498 8499 if (!ca0132_use_alt_functions(spec)) 8500 spec->multiout.max_channels = 2; 8501 else 8502 spec->multiout.max_channels = 6; 8503 8504 switch (ca0132_quirk(spec)) { 8505 case QUIRK_ALIENWARE: 8506 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__); 8507 snd_hda_apply_pincfgs(codec, alienware_pincfgs); 8508 break; 8509 case QUIRK_SBZ: 8510 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__); 8511 snd_hda_apply_pincfgs(codec, sbz_pincfgs); 8512 break; 8513 case QUIRK_ZXR: 8514 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__); 8515 snd_hda_apply_pincfgs(codec, zxr_pincfgs); 8516 break; 8517 case QUIRK_R3D: 8518 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__); 8519 snd_hda_apply_pincfgs(codec, r3d_pincfgs); 8520 break; 8521 case QUIRK_R3DI: 8522 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__); 8523 snd_hda_apply_pincfgs(codec, r3di_pincfgs); 8524 break; 8525 case QUIRK_AE5: 8526 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__); 8527 snd_hda_apply_pincfgs(codec, ae5_pincfgs); 8528 break; 8529 default: 8530 break; 8531 } 8532 8533 switch (ca0132_quirk(spec)) { 8534 case QUIRK_ALIENWARE: 8535 spec->num_outputs = 2; 8536 spec->out_pins[0] = 0x0b; /* speaker out */ 8537 spec->out_pins[1] = 0x0f; 8538 spec->shared_out_nid = 0x2; 8539 spec->unsol_tag_hp = 0x0f; 8540 8541 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 8542 spec->adcs[1] = 0x8; /* analog mic2 */ 8543 spec->adcs[2] = 0xa; /* what u hear */ 8544 8545 spec->num_inputs = 3; 8546 spec->input_pins[0] = 0x12; 8547 spec->input_pins[1] = 0x11; 8548 spec->input_pins[2] = 0x13; 8549 spec->shared_mic_nid = 0x7; 8550 spec->unsol_tag_amic1 = 0x11; 8551 break; 8552 case QUIRK_SBZ: 8553 case QUIRK_R3D: 8554 spec->num_outputs = 2; 8555 spec->out_pins[0] = 0x0B; /* Line out */ 8556 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 8557 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 8558 spec->out_pins[3] = 0x11; /* Rear surround */ 8559 spec->shared_out_nid = 0x2; 8560 spec->unsol_tag_hp = spec->out_pins[1]; 8561 spec->unsol_tag_front_hp = spec->out_pins[2]; 8562 8563 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 8564 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 8565 spec->adcs[2] = 0xa; /* what u hear */ 8566 8567 spec->num_inputs = 2; 8568 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 8569 spec->input_pins[1] = 0x13; /* What U Hear */ 8570 spec->shared_mic_nid = 0x7; 8571 spec->unsol_tag_amic1 = spec->input_pins[0]; 8572 8573 /* SPDIF I/O */ 8574 spec->dig_out = 0x05; 8575 spec->multiout.dig_out_nid = spec->dig_out; 8576 spec->dig_in = 0x09; 8577 break; 8578 case QUIRK_ZXR: 8579 spec->num_outputs = 2; 8580 spec->out_pins[0] = 0x0B; /* Line out */ 8581 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 8582 spec->out_pins[2] = 0x10; /* Center/LFE */ 8583 spec->out_pins[3] = 0x11; /* Rear surround */ 8584 spec->shared_out_nid = 0x2; 8585 spec->unsol_tag_hp = spec->out_pins[1]; 8586 spec->unsol_tag_front_hp = spec->out_pins[2]; 8587 8588 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 8589 spec->adcs[1] = 0x8; /* Not connected, no front mic */ 8590 spec->adcs[2] = 0xa; /* what u hear */ 8591 8592 spec->num_inputs = 2; 8593 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 8594 spec->input_pins[1] = 0x13; /* What U Hear */ 8595 spec->shared_mic_nid = 0x7; 8596 spec->unsol_tag_amic1 = spec->input_pins[0]; 8597 break; 8598 case QUIRK_ZXR_DBPRO: 8599 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */ 8600 8601 spec->num_inputs = 1; 8602 spec->input_pins[0] = 0x11; /* RCA Line-in */ 8603 8604 spec->dig_out = 0x05; 8605 spec->multiout.dig_out_nid = spec->dig_out; 8606 8607 spec->dig_in = 0x09; 8608 break; 8609 case QUIRK_AE5: 8610 spec->num_outputs = 2; 8611 spec->out_pins[0] = 0x0B; /* Line out */ 8612 spec->out_pins[1] = 0x11; /* Rear headphone out */ 8613 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 8614 spec->out_pins[3] = 0x0F; /* Rear surround */ 8615 spec->shared_out_nid = 0x2; 8616 spec->unsol_tag_hp = spec->out_pins[1]; 8617 spec->unsol_tag_front_hp = spec->out_pins[2]; 8618 8619 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 8620 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 8621 spec->adcs[2] = 0xa; /* what u hear */ 8622 8623 spec->num_inputs = 2; 8624 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 8625 spec->input_pins[1] = 0x13; /* What U Hear */ 8626 spec->shared_mic_nid = 0x7; 8627 spec->unsol_tag_amic1 = spec->input_pins[0]; 8628 8629 /* SPDIF I/O */ 8630 spec->dig_out = 0x05; 8631 spec->multiout.dig_out_nid = spec->dig_out; 8632 break; 8633 case QUIRK_R3DI: 8634 spec->num_outputs = 2; 8635 spec->out_pins[0] = 0x0B; /* Line out */ 8636 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 8637 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 8638 spec->out_pins[3] = 0x11; /* Rear surround */ 8639 spec->shared_out_nid = 0x2; 8640 spec->unsol_tag_hp = spec->out_pins[1]; 8641 spec->unsol_tag_front_hp = spec->out_pins[2]; 8642 8643 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */ 8644 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */ 8645 spec->adcs[2] = 0x0a; /* what u hear */ 8646 8647 spec->num_inputs = 2; 8648 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 8649 spec->input_pins[1] = 0x13; /* What U Hear */ 8650 spec->shared_mic_nid = 0x7; 8651 spec->unsol_tag_amic1 = spec->input_pins[0]; 8652 8653 /* SPDIF I/O */ 8654 spec->dig_out = 0x05; 8655 spec->multiout.dig_out_nid = spec->dig_out; 8656 break; 8657 default: 8658 spec->num_outputs = 2; 8659 spec->out_pins[0] = 0x0b; /* speaker out */ 8660 spec->out_pins[1] = 0x10; /* headphone out */ 8661 spec->shared_out_nid = 0x2; 8662 spec->unsol_tag_hp = spec->out_pins[1]; 8663 8664 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 8665 spec->adcs[1] = 0x8; /* analog mic2 */ 8666 spec->adcs[2] = 0xa; /* what u hear */ 8667 8668 spec->num_inputs = 3; 8669 spec->input_pins[0] = 0x12; 8670 spec->input_pins[1] = 0x11; 8671 spec->input_pins[2] = 0x13; 8672 spec->shared_mic_nid = 0x7; 8673 spec->unsol_tag_amic1 = spec->input_pins[0]; 8674 8675 /* SPDIF I/O */ 8676 spec->dig_out = 0x05; 8677 spec->multiout.dig_out_nid = spec->dig_out; 8678 spec->dig_in = 0x09; 8679 break; 8680 } 8681 } 8682 8683 static int ca0132_prepare_verbs(struct hda_codec *codec) 8684 { 8685 /* Verbs + terminator (an empty element) */ 8686 #define NUM_SPEC_VERBS 2 8687 struct ca0132_spec *spec = codec->spec; 8688 8689 spec->chip_init_verbs = ca0132_init_verbs0; 8690 /* 8691 * Since desktop cards use pci_mmio, this can be used to determine 8692 * whether or not to use these verbs instead of a separate bool. 8693 */ 8694 if (ca0132_use_pci_mmio(spec)) 8695 spec->desktop_init_verbs = ca0132_init_verbs1; 8696 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS, 8697 sizeof(struct hda_verb), 8698 GFP_KERNEL); 8699 if (!spec->spec_init_verbs) 8700 return -ENOMEM; 8701 8702 /* config EAPD */ 8703 spec->spec_init_verbs[0].nid = 0x0b; 8704 spec->spec_init_verbs[0].param = 0x78D; 8705 spec->spec_init_verbs[0].verb = 0x00; 8706 8707 /* Previously commented configuration */ 8708 /* 8709 spec->spec_init_verbs[2].nid = 0x0b; 8710 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE; 8711 spec->spec_init_verbs[2].verb = 0x02; 8712 8713 spec->spec_init_verbs[3].nid = 0x10; 8714 spec->spec_init_verbs[3].param = 0x78D; 8715 spec->spec_init_verbs[3].verb = 0x02; 8716 8717 spec->spec_init_verbs[4].nid = 0x10; 8718 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE; 8719 spec->spec_init_verbs[4].verb = 0x02; 8720 */ 8721 8722 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */ 8723 return 0; 8724 } 8725 8726 /* 8727 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular 8728 * Sound Blaster Z cards. However, they have different HDA codec subsystem 8729 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro 8730 * daughter boards ID. 8731 */ 8732 static void sbz_detect_quirk(struct hda_codec *codec) 8733 { 8734 struct ca0132_spec *spec = codec->spec; 8735 8736 switch (codec->core.subsystem_id) { 8737 case 0x11020033: 8738 spec->quirk = QUIRK_ZXR; 8739 break; 8740 case 0x1102003f: 8741 spec->quirk = QUIRK_ZXR_DBPRO; 8742 break; 8743 default: 8744 spec->quirk = QUIRK_SBZ; 8745 break; 8746 } 8747 } 8748 8749 static int patch_ca0132(struct hda_codec *codec) 8750 { 8751 struct ca0132_spec *spec; 8752 int err; 8753 const struct snd_pci_quirk *quirk; 8754 8755 codec_dbg(codec, "patch_ca0132\n"); 8756 8757 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 8758 if (!spec) 8759 return -ENOMEM; 8760 codec->spec = spec; 8761 spec->codec = codec; 8762 8763 /* Detect codec quirk */ 8764 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks); 8765 if (quirk) 8766 spec->quirk = quirk->value; 8767 else 8768 spec->quirk = QUIRK_NONE; 8769 if (ca0132_quirk(spec) == QUIRK_SBZ) 8770 sbz_detect_quirk(codec); 8771 8772 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO) 8773 codec->patch_ops = dbpro_patch_ops; 8774 else 8775 codec->patch_ops = ca0132_patch_ops; 8776 8777 codec->pcm_format_first = 1; 8778 codec->no_sticky_stream = 1; 8779 8780 8781 spec->dsp_state = DSP_DOWNLOAD_INIT; 8782 spec->num_mixers = 1; 8783 8784 /* Set which mixers each quirk uses. */ 8785 switch (ca0132_quirk(spec)) { 8786 case QUIRK_SBZ: 8787 spec->mixers[0] = desktop_mixer; 8788 snd_hda_codec_set_name(codec, "Sound Blaster Z"); 8789 break; 8790 case QUIRK_ZXR: 8791 spec->mixers[0] = desktop_mixer; 8792 snd_hda_codec_set_name(codec, "Sound Blaster ZxR"); 8793 break; 8794 case QUIRK_ZXR_DBPRO: 8795 break; 8796 case QUIRK_R3D: 8797 spec->mixers[0] = desktop_mixer; 8798 snd_hda_codec_set_name(codec, "Recon3D"); 8799 break; 8800 case QUIRK_R3DI: 8801 spec->mixers[0] = r3di_mixer; 8802 snd_hda_codec_set_name(codec, "Recon3Di"); 8803 break; 8804 case QUIRK_AE5: 8805 spec->mixers[0] = desktop_mixer; 8806 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5"); 8807 break; 8808 default: 8809 spec->mixers[0] = ca0132_mixer; 8810 break; 8811 } 8812 8813 /* Setup whether or not to use alt functions/controls/pci_mmio */ 8814 switch (ca0132_quirk(spec)) { 8815 case QUIRK_SBZ: 8816 case QUIRK_R3D: 8817 case QUIRK_AE5: 8818 case QUIRK_ZXR: 8819 spec->use_alt_controls = true; 8820 spec->use_alt_functions = true; 8821 spec->use_pci_mmio = true; 8822 break; 8823 case QUIRK_R3DI: 8824 spec->use_alt_controls = true; 8825 spec->use_alt_functions = true; 8826 spec->use_pci_mmio = false; 8827 break; 8828 default: 8829 spec->use_alt_controls = false; 8830 spec->use_alt_functions = false; 8831 spec->use_pci_mmio = false; 8832 break; 8833 } 8834 8835 #ifdef CONFIG_PCI 8836 if (spec->use_pci_mmio) { 8837 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20); 8838 if (spec->mem_base == NULL) { 8839 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE."); 8840 spec->quirk = QUIRK_NONE; 8841 } 8842 } 8843 #endif 8844 8845 spec->base_init_verbs = ca0132_base_init_verbs; 8846 spec->base_exit_verbs = ca0132_base_exit_verbs; 8847 8848 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed); 8849 8850 ca0132_init_chip(codec); 8851 8852 ca0132_config(codec); 8853 8854 err = ca0132_prepare_verbs(codec); 8855 if (err < 0) 8856 goto error; 8857 8858 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL); 8859 if (err < 0) 8860 goto error; 8861 8862 return 0; 8863 8864 error: 8865 ca0132_free(codec); 8866 return err; 8867 } 8868 8869 /* 8870 * patch entries 8871 */ 8872 static struct hda_device_id snd_hda_id_ca0132[] = { 8873 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132), 8874 {} /* terminator */ 8875 }; 8876 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132); 8877 8878 MODULE_LICENSE("GPL"); 8879 MODULE_DESCRIPTION("Creative Sound Core3D codec"); 8880 8881 static struct hda_codec_driver ca0132_driver = { 8882 .id = snd_hda_id_ca0132, 8883 }; 8884 8885 module_hda_codec_driver(ca0132_driver); 8886