1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * HD audio interface patch for Creative CA0132 chip 4 * 5 * Copyright (c) 2011, Creative Technology Ltd. 6 * 7 * Based on patch_ca0110.c 8 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de> 9 */ 10 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/slab.h> 14 #include <linux/mutex.h> 15 #include <linux/module.h> 16 #include <linux/firmware.h> 17 #include <linux/kernel.h> 18 #include <linux/types.h> 19 #include <linux/io.h> 20 #include <linux/pci.h> 21 #include <asm/io.h> 22 #include <sound/core.h> 23 #include <sound/hda_codec.h> 24 #include "hda_local.h" 25 #include "hda_auto_parser.h" 26 #include "hda_jack.h" 27 28 #include "ca0132_regs.h" 29 30 /* Enable this to see controls for tuning purpose. */ 31 /*#define ENABLE_TUNING_CONTROLS*/ 32 33 #ifdef ENABLE_TUNING_CONTROLS 34 #include <sound/tlv.h> 35 #endif 36 37 #define FLOAT_ZERO 0x00000000 38 #define FLOAT_ONE 0x3f800000 39 #define FLOAT_TWO 0x40000000 40 #define FLOAT_THREE 0x40400000 41 #define FLOAT_FIVE 0x40a00000 42 #define FLOAT_SIX 0x40c00000 43 #define FLOAT_EIGHT 0x41000000 44 #define FLOAT_MINUS_5 0xc0a00000 45 46 #define UNSOL_TAG_DSP 0x16 47 48 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18) 49 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15) 50 51 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8 52 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32 53 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2 54 55 #define MASTERCONTROL 0x80 56 #define MASTERCONTROL_ALLOC_DMA_CHAN 10 57 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60 58 59 #define WIDGET_CHIP_CTRL 0x15 60 #define WIDGET_DSP_CTRL 0x16 61 62 #define MEM_CONNID_MICIN1 3 63 #define MEM_CONNID_MICIN2 5 64 #define MEM_CONNID_MICOUT1 12 65 #define MEM_CONNID_MICOUT2 14 66 #define MEM_CONNID_WUH 10 67 #define MEM_CONNID_DSP 16 68 #define MEM_CONNID_DMIC 100 69 70 #define SCP_SET 0 71 #define SCP_GET 1 72 73 #define EFX_FILE "ctefx.bin" 74 #define DESKTOP_EFX_FILE "ctefx-desktop.bin" 75 #define R3DI_EFX_FILE "ctefx-r3di.bin" 76 77 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 78 MODULE_FIRMWARE(EFX_FILE); 79 MODULE_FIRMWARE(DESKTOP_EFX_FILE); 80 MODULE_FIRMWARE(R3DI_EFX_FILE); 81 #endif 82 83 static const char *const dirstr[2] = { "Playback", "Capture" }; 84 85 #define NUM_OF_OUTPUTS 2 86 static const char *const out_type_str[2] = { "Speakers", "Headphone" }; 87 enum { 88 SPEAKER_OUT, 89 HEADPHONE_OUT, 90 }; 91 92 enum { 93 DIGITAL_MIC, 94 LINE_MIC_IN 95 }; 96 97 /* Strings for Input Source Enum Control */ 98 static const char *const in_src_str[3] = { "Microphone", "Line In", "Front Microphone" }; 99 #define IN_SRC_NUM_OF_INPUTS 3 100 enum { 101 REAR_MIC, 102 REAR_LINE_IN, 103 FRONT_MIC, 104 }; 105 106 enum { 107 #define VNODE_START_NID 0x80 108 VNID_SPK = VNODE_START_NID, /* Speaker vnid */ 109 VNID_MIC, 110 VNID_HP_SEL, 111 VNID_AMIC1_SEL, 112 VNID_HP_ASEL, 113 VNID_AMIC1_ASEL, 114 VNODE_END_NID, 115 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID) 116 117 #define EFFECT_START_NID 0x90 118 #define OUT_EFFECT_START_NID EFFECT_START_NID 119 SURROUND = OUT_EFFECT_START_NID, 120 CRYSTALIZER, 121 DIALOG_PLUS, 122 SMART_VOLUME, 123 X_BASS, 124 EQUALIZER, 125 OUT_EFFECT_END_NID, 126 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID) 127 128 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID 129 ECHO_CANCELLATION = IN_EFFECT_START_NID, 130 VOICE_FOCUS, 131 MIC_SVM, 132 NOISE_REDUCTION, 133 IN_EFFECT_END_NID, 134 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID) 135 136 VOICEFX = IN_EFFECT_END_NID, 137 PLAY_ENHANCEMENT, 138 CRYSTAL_VOICE, 139 EFFECT_END_NID, 140 OUTPUT_SOURCE_ENUM, 141 INPUT_SOURCE_ENUM, 142 XBASS_XOVER, 143 EQ_PRESET_ENUM, 144 SMART_VOLUME_ENUM, 145 MIC_BOOST_ENUM, 146 AE5_HEADPHONE_GAIN_ENUM, 147 AE5_SOUND_FILTER_ENUM, 148 ZXR_HEADPHONE_GAIN, 149 SPEAKER_CHANNEL_CFG_ENUM, 150 SPEAKER_FULL_RANGE_FRONT, 151 SPEAKER_FULL_RANGE_REAR, 152 BASS_REDIRECTION, 153 BASS_REDIRECTION_XOVER, 154 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID) 155 }; 156 157 /* Effects values size*/ 158 #define EFFECT_VALS_MAX_COUNT 12 159 160 /* 161 * Default values for the effect slider controls, they are in order of their 162 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then 163 * X-bass. 164 */ 165 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50}; 166 /* Amount of effect level sliders for ca0132_alt controls. */ 167 #define EFFECT_LEVEL_SLIDERS 5 168 169 /* Latency introduced by DSP blocks in milliseconds. */ 170 #define DSP_CAPTURE_INIT_LATENCY 0 171 #define DSP_CRYSTAL_VOICE_LATENCY 124 172 #define DSP_PLAYBACK_INIT_LATENCY 13 173 #define DSP_PLAY_ENHANCEMENT_LATENCY 30 174 #define DSP_SPEAKER_OUT_LATENCY 7 175 176 struct ct_effect { 177 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 178 hda_nid_t nid; 179 int mid; /*effect module ID*/ 180 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/ 181 int direct; /* 0:output; 1:input*/ 182 int params; /* number of default non-on/off params */ 183 /*effect default values, 1st is on/off. */ 184 unsigned int def_vals[EFFECT_VALS_MAX_COUNT]; 185 }; 186 187 #define EFX_DIR_OUT 0 188 #define EFX_DIR_IN 1 189 190 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = { 191 { .name = "Surround", 192 .nid = SURROUND, 193 .mid = 0x96, 194 .reqs = {0, 1}, 195 .direct = EFX_DIR_OUT, 196 .params = 1, 197 .def_vals = {0x3F800000, 0x3F2B851F} 198 }, 199 { .name = "Crystalizer", 200 .nid = CRYSTALIZER, 201 .mid = 0x96, 202 .reqs = {7, 8}, 203 .direct = EFX_DIR_OUT, 204 .params = 1, 205 .def_vals = {0x3F800000, 0x3F266666} 206 }, 207 { .name = "Dialog Plus", 208 .nid = DIALOG_PLUS, 209 .mid = 0x96, 210 .reqs = {2, 3}, 211 .direct = EFX_DIR_OUT, 212 .params = 1, 213 .def_vals = {0x00000000, 0x3F000000} 214 }, 215 { .name = "Smart Volume", 216 .nid = SMART_VOLUME, 217 .mid = 0x96, 218 .reqs = {4, 5, 6}, 219 .direct = EFX_DIR_OUT, 220 .params = 2, 221 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000} 222 }, 223 { .name = "X-Bass", 224 .nid = X_BASS, 225 .mid = 0x96, 226 .reqs = {24, 23, 25}, 227 .direct = EFX_DIR_OUT, 228 .params = 2, 229 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000} 230 }, 231 { .name = "Equalizer", 232 .nid = EQUALIZER, 233 .mid = 0x96, 234 .reqs = {9, 10, 11, 12, 13, 14, 235 15, 16, 17, 18, 19, 20}, 236 .direct = EFX_DIR_OUT, 237 .params = 11, 238 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000, 239 0x00000000, 0x00000000, 0x00000000, 0x00000000, 240 0x00000000, 0x00000000, 0x00000000, 0x00000000} 241 }, 242 { .name = "Echo Cancellation", 243 .nid = ECHO_CANCELLATION, 244 .mid = 0x95, 245 .reqs = {0, 1, 2, 3}, 246 .direct = EFX_DIR_IN, 247 .params = 3, 248 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000} 249 }, 250 { .name = "Voice Focus", 251 .nid = VOICE_FOCUS, 252 .mid = 0x95, 253 .reqs = {6, 7, 8, 9}, 254 .direct = EFX_DIR_IN, 255 .params = 3, 256 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000} 257 }, 258 { .name = "Mic SVM", 259 .nid = MIC_SVM, 260 .mid = 0x95, 261 .reqs = {44, 45}, 262 .direct = EFX_DIR_IN, 263 .params = 1, 264 .def_vals = {0x00000000, 0x3F3D70A4} 265 }, 266 { .name = "Noise Reduction", 267 .nid = NOISE_REDUCTION, 268 .mid = 0x95, 269 .reqs = {4, 5}, 270 .direct = EFX_DIR_IN, 271 .params = 1, 272 .def_vals = {0x3F800000, 0x3F000000} 273 }, 274 { .name = "VoiceFX", 275 .nid = VOICEFX, 276 .mid = 0x95, 277 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}, 278 .direct = EFX_DIR_IN, 279 .params = 8, 280 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000, 281 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000, 282 0x00000000} 283 } 284 }; 285 286 /* Tuning controls */ 287 #ifdef ENABLE_TUNING_CONTROLS 288 289 enum { 290 #define TUNING_CTL_START_NID 0xC0 291 WEDGE_ANGLE = TUNING_CTL_START_NID, 292 SVM_LEVEL, 293 EQUALIZER_BAND_0, 294 EQUALIZER_BAND_1, 295 EQUALIZER_BAND_2, 296 EQUALIZER_BAND_3, 297 EQUALIZER_BAND_4, 298 EQUALIZER_BAND_5, 299 EQUALIZER_BAND_6, 300 EQUALIZER_BAND_7, 301 EQUALIZER_BAND_8, 302 EQUALIZER_BAND_9, 303 TUNING_CTL_END_NID 304 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID) 305 }; 306 307 struct ct_tuning_ctl { 308 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 309 hda_nid_t parent_nid; 310 hda_nid_t nid; 311 int mid; /*effect module ID*/ 312 int req; /*effect module request*/ 313 int direct; /* 0:output; 1:input*/ 314 unsigned int def_val;/*effect default values*/ 315 }; 316 317 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = { 318 { .name = "Wedge Angle", 319 .parent_nid = VOICE_FOCUS, 320 .nid = WEDGE_ANGLE, 321 .mid = 0x95, 322 .req = 8, 323 .direct = EFX_DIR_IN, 324 .def_val = 0x41F00000 325 }, 326 { .name = "SVM Level", 327 .parent_nid = MIC_SVM, 328 .nid = SVM_LEVEL, 329 .mid = 0x95, 330 .req = 45, 331 .direct = EFX_DIR_IN, 332 .def_val = 0x3F3D70A4 333 }, 334 { .name = "EQ Band0", 335 .parent_nid = EQUALIZER, 336 .nid = EQUALIZER_BAND_0, 337 .mid = 0x96, 338 .req = 11, 339 .direct = EFX_DIR_OUT, 340 .def_val = 0x00000000 341 }, 342 { .name = "EQ Band1", 343 .parent_nid = EQUALIZER, 344 .nid = EQUALIZER_BAND_1, 345 .mid = 0x96, 346 .req = 12, 347 .direct = EFX_DIR_OUT, 348 .def_val = 0x00000000 349 }, 350 { .name = "EQ Band2", 351 .parent_nid = EQUALIZER, 352 .nid = EQUALIZER_BAND_2, 353 .mid = 0x96, 354 .req = 13, 355 .direct = EFX_DIR_OUT, 356 .def_val = 0x00000000 357 }, 358 { .name = "EQ Band3", 359 .parent_nid = EQUALIZER, 360 .nid = EQUALIZER_BAND_3, 361 .mid = 0x96, 362 .req = 14, 363 .direct = EFX_DIR_OUT, 364 .def_val = 0x00000000 365 }, 366 { .name = "EQ Band4", 367 .parent_nid = EQUALIZER, 368 .nid = EQUALIZER_BAND_4, 369 .mid = 0x96, 370 .req = 15, 371 .direct = EFX_DIR_OUT, 372 .def_val = 0x00000000 373 }, 374 { .name = "EQ Band5", 375 .parent_nid = EQUALIZER, 376 .nid = EQUALIZER_BAND_5, 377 .mid = 0x96, 378 .req = 16, 379 .direct = EFX_DIR_OUT, 380 .def_val = 0x00000000 381 }, 382 { .name = "EQ Band6", 383 .parent_nid = EQUALIZER, 384 .nid = EQUALIZER_BAND_6, 385 .mid = 0x96, 386 .req = 17, 387 .direct = EFX_DIR_OUT, 388 .def_val = 0x00000000 389 }, 390 { .name = "EQ Band7", 391 .parent_nid = EQUALIZER, 392 .nid = EQUALIZER_BAND_7, 393 .mid = 0x96, 394 .req = 18, 395 .direct = EFX_DIR_OUT, 396 .def_val = 0x00000000 397 }, 398 { .name = "EQ Band8", 399 .parent_nid = EQUALIZER, 400 .nid = EQUALIZER_BAND_8, 401 .mid = 0x96, 402 .req = 19, 403 .direct = EFX_DIR_OUT, 404 .def_val = 0x00000000 405 }, 406 { .name = "EQ Band9", 407 .parent_nid = EQUALIZER, 408 .nid = EQUALIZER_BAND_9, 409 .mid = 0x96, 410 .req = 20, 411 .direct = EFX_DIR_OUT, 412 .def_val = 0x00000000 413 } 414 }; 415 #endif 416 417 /* Voice FX Presets */ 418 #define VOICEFX_MAX_PARAM_COUNT 9 419 420 struct ct_voicefx { 421 char *name; 422 hda_nid_t nid; 423 int mid; 424 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/ 425 }; 426 427 struct ct_voicefx_preset { 428 char *name; /*preset name*/ 429 unsigned int vals[VOICEFX_MAX_PARAM_COUNT]; 430 }; 431 432 static const struct ct_voicefx ca0132_voicefx = { 433 .name = "VoiceFX Capture Switch", 434 .nid = VOICEFX, 435 .mid = 0x95, 436 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18} 437 }; 438 439 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = { 440 { .name = "Neutral", 441 .vals = { 0x00000000, 0x43C80000, 0x44AF0000, 442 0x44FA0000, 0x3F800000, 0x3F800000, 443 0x3F800000, 0x00000000, 0x00000000 } 444 }, 445 { .name = "Female2Male", 446 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 447 0x44FA0000, 0x3F19999A, 0x3F866666, 448 0x3F800000, 0x00000000, 0x00000000 } 449 }, 450 { .name = "Male2Female", 451 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 452 0x450AC000, 0x4017AE14, 0x3F6B851F, 453 0x3F800000, 0x00000000, 0x00000000 } 454 }, 455 { .name = "ScrappyKid", 456 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 457 0x44FA0000, 0x40400000, 0x3F28F5C3, 458 0x3F800000, 0x00000000, 0x00000000 } 459 }, 460 { .name = "Elderly", 461 .vals = { 0x3F800000, 0x44324000, 0x44BB8000, 462 0x44E10000, 0x3FB33333, 0x3FB9999A, 463 0x3F800000, 0x3E3A2E43, 0x00000000 } 464 }, 465 { .name = "Orc", 466 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000, 467 0x45098000, 0x3F266666, 0x3FC00000, 468 0x3F800000, 0x00000000, 0x00000000 } 469 }, 470 { .name = "Elf", 471 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000, 472 0x45193000, 0x3F8E147B, 0x3F75C28F, 473 0x3F800000, 0x00000000, 0x00000000 } 474 }, 475 { .name = "Dwarf", 476 .vals = { 0x3F800000, 0x43930000, 0x44BEE000, 477 0x45007000, 0x3F451EB8, 0x3F7851EC, 478 0x3F800000, 0x00000000, 0x00000000 } 479 }, 480 { .name = "AlienBrute", 481 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF, 482 0x451F6000, 0x3F266666, 0x3FA7D945, 483 0x3F800000, 0x3CF5C28F, 0x00000000 } 484 }, 485 { .name = "Robot", 486 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 487 0x44FA0000, 0x3FB2718B, 0x3F800000, 488 0xBC07010E, 0x00000000, 0x00000000 } 489 }, 490 { .name = "Marine", 491 .vals = { 0x3F800000, 0x43C20000, 0x44906000, 492 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71, 493 0x3F0A3D71, 0x00000000, 0x00000000 } 494 }, 495 { .name = "Emo", 496 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 497 0x44FA0000, 0x3F800000, 0x3F800000, 498 0x3E4CCCCD, 0x00000000, 0x00000000 } 499 }, 500 { .name = "DeepVoice", 501 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF, 502 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA, 503 0x3F800000, 0x00000000, 0x00000000 } 504 }, 505 { .name = "Munchkin", 506 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 507 0x44FA0000, 0x3F800000, 0x3F1A043C, 508 0x3F800000, 0x00000000, 0x00000000 } 509 } 510 }; 511 512 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */ 513 514 #define EQ_PRESET_MAX_PARAM_COUNT 11 515 516 struct ct_eq { 517 char *name; 518 hda_nid_t nid; 519 int mid; 520 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/ 521 }; 522 523 struct ct_eq_preset { 524 char *name; /*preset name*/ 525 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT]; 526 }; 527 528 static const struct ct_eq ca0132_alt_eq_enum = { 529 .name = "FX: Equalizer Preset Switch", 530 .nid = EQ_PRESET_ENUM, 531 .mid = 0x96, 532 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20} 533 }; 534 535 536 static const struct ct_eq_preset ca0132_alt_eq_presets[] = { 537 { .name = "Flat", 538 .vals = { 0x00000000, 0x00000000, 0x00000000, 539 0x00000000, 0x00000000, 0x00000000, 540 0x00000000, 0x00000000, 0x00000000, 541 0x00000000, 0x00000000 } 542 }, 543 { .name = "Acoustic", 544 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD, 545 0x40000000, 0x00000000, 0x00000000, 546 0x00000000, 0x00000000, 0x40000000, 547 0x40000000, 0x40000000 } 548 }, 549 { .name = "Classical", 550 .vals = { 0x00000000, 0x00000000, 0x40C00000, 551 0x40C00000, 0x40466666, 0x00000000, 552 0x00000000, 0x00000000, 0x00000000, 553 0x40466666, 0x40466666 } 554 }, 555 { .name = "Country", 556 .vals = { 0x00000000, 0xBF99999A, 0x00000000, 557 0x3FA66666, 0x3FA66666, 0x3F8CCCCD, 558 0x00000000, 0x00000000, 0x40000000, 559 0x40466666, 0x40800000 } 560 }, 561 { .name = "Dance", 562 .vals = { 0x00000000, 0xBF99999A, 0x40000000, 563 0x40466666, 0x40866666, 0xBF99999A, 564 0xBF99999A, 0x00000000, 0x00000000, 565 0x40800000, 0x40800000 } 566 }, 567 { .name = "Jazz", 568 .vals = { 0x00000000, 0x00000000, 0x00000000, 569 0x3F8CCCCD, 0x40800000, 0x40800000, 570 0x40800000, 0x00000000, 0x3F8CCCCD, 571 0x40466666, 0x40466666 } 572 }, 573 { .name = "New Age", 574 .vals = { 0x00000000, 0x00000000, 0x40000000, 575 0x40000000, 0x00000000, 0x00000000, 576 0x00000000, 0x3F8CCCCD, 0x40000000, 577 0x40000000, 0x40000000 } 578 }, 579 { .name = "Pop", 580 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000, 581 0x40000000, 0x40000000, 0x00000000, 582 0xBF99999A, 0xBF99999A, 0x00000000, 583 0x40466666, 0x40C00000 } 584 }, 585 { .name = "Rock", 586 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A, 587 0x3F8CCCCD, 0x40000000, 0xBF99999A, 588 0xBF99999A, 0x00000000, 0x00000000, 589 0x40800000, 0x40800000 } 590 }, 591 { .name = "Vocal", 592 .vals = { 0x00000000, 0xC0000000, 0xBF99999A, 593 0xBF99999A, 0x00000000, 0x40466666, 594 0x40800000, 0x40466666, 0x00000000, 595 0x00000000, 0x3F8CCCCD } 596 } 597 }; 598 599 /* 600 * DSP reqs for handling full-range speakers/bass redirection. If a speaker is 601 * set as not being full range, and bass redirection is enabled, all 602 * frequencies below the crossover frequency are redirected to the LFE 603 * channel. If the surround configuration has no LFE channel, this can't be 604 * enabled. X-Bass must be disabled when using these. 605 */ 606 enum speaker_range_reqs { 607 SPEAKER_BASS_REDIRECT = 0x15, 608 SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16, 609 /* Between 0x16-0x1a are the X-Bass reqs. */ 610 SPEAKER_FULL_RANGE_FRONT_L_R = 0x1a, 611 SPEAKER_FULL_RANGE_CENTER_LFE = 0x1b, 612 SPEAKER_FULL_RANGE_REAR_L_R = 0x1c, 613 SPEAKER_FULL_RANGE_SURROUND_L_R = 0x1d, 614 SPEAKER_BASS_REDIRECT_SUB_GAIN = 0x1e, 615 }; 616 617 /* 618 * Definitions for the DSP req's to handle speaker tuning. These all belong to 619 * module ID 0x96, the output effects module. 620 */ 621 enum speaker_tuning_reqs { 622 /* 623 * Currently, this value is always set to 0.0f. However, on Windows, 624 * when selecting certain headphone profiles on the new Sound Blaster 625 * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is 626 * sent. This gets the speaker EQ address area, which is then used to 627 * send over (presumably) an equalizer profile for the specific 628 * headphone setup. It is sent using the same method the DSP 629 * firmware is uploaded with, which I believe is why the 'ctspeq.bin' 630 * file exists in linux firmware tree but goes unused. It would also 631 * explain why the QUERY_SPEAKER_EQ_ADDRESS req is defined but unused. 632 * Once this profile is sent over, SPEAKER_TUNING_USE_SPEAKER_EQ is 633 * set to 1.0f. 634 */ 635 SPEAKER_TUNING_USE_SPEAKER_EQ = 0x1f, 636 SPEAKER_TUNING_ENABLE_CENTER_EQ = 0x20, 637 SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL = 0x21, 638 SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL = 0x22, 639 SPEAKER_TUNING_CENTER_VOL_LEVEL = 0x23, 640 SPEAKER_TUNING_LFE_VOL_LEVEL = 0x24, 641 SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL = 0x25, 642 SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL = 0x26, 643 SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL = 0x27, 644 SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28, 645 /* 646 * Inversion is used when setting headphone virtualization to line 647 * out. Not sure why this is, but it's the only place it's ever used. 648 */ 649 SPEAKER_TUNING_FRONT_LEFT_INVERT = 0x29, 650 SPEAKER_TUNING_FRONT_RIGHT_INVERT = 0x2a, 651 SPEAKER_TUNING_CENTER_INVERT = 0x2b, 652 SPEAKER_TUNING_LFE_INVERT = 0x2c, 653 SPEAKER_TUNING_REAR_LEFT_INVERT = 0x2d, 654 SPEAKER_TUNING_REAR_RIGHT_INVERT = 0x2e, 655 SPEAKER_TUNING_SURROUND_LEFT_INVERT = 0x2f, 656 SPEAKER_TUNING_SURROUND_RIGHT_INVERT = 0x30, 657 /* Delay is used when setting surround speaker distance in Windows. */ 658 SPEAKER_TUNING_FRONT_LEFT_DELAY = 0x31, 659 SPEAKER_TUNING_FRONT_RIGHT_DELAY = 0x32, 660 SPEAKER_TUNING_CENTER_DELAY = 0x33, 661 SPEAKER_TUNING_LFE_DELAY = 0x34, 662 SPEAKER_TUNING_REAR_LEFT_DELAY = 0x35, 663 SPEAKER_TUNING_REAR_RIGHT_DELAY = 0x36, 664 SPEAKER_TUNING_SURROUND_LEFT_DELAY = 0x37, 665 SPEAKER_TUNING_SURROUND_RIGHT_DELAY = 0x38, 666 /* Of these two, only mute seems to ever be used. */ 667 SPEAKER_TUNING_MAIN_VOLUME = 0x39, 668 SPEAKER_TUNING_MUTE = 0x3a, 669 }; 670 671 /* Surround output channel count configuration structures. */ 672 #define SPEAKER_CHANNEL_CFG_COUNT 5 673 enum { 674 SPEAKER_CHANNELS_2_0, 675 SPEAKER_CHANNELS_2_1, 676 SPEAKER_CHANNELS_4_0, 677 SPEAKER_CHANNELS_4_1, 678 SPEAKER_CHANNELS_5_1, 679 }; 680 681 struct ca0132_alt_speaker_channel_cfg { 682 char *name; 683 unsigned int val; 684 }; 685 686 static const struct ca0132_alt_speaker_channel_cfg speaker_channel_cfgs[] = { 687 { .name = "2.0", 688 .val = FLOAT_ONE 689 }, 690 { .name = "2.1", 691 .val = FLOAT_TWO 692 }, 693 { .name = "4.0", 694 .val = FLOAT_FIVE 695 }, 696 { .name = "4.1", 697 .val = FLOAT_SIX 698 }, 699 { .name = "5.1", 700 .val = FLOAT_EIGHT 701 } 702 }; 703 704 /* 705 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume, 706 * and I don't know what the third req is, but it's always zero. I assume it's 707 * some sort of update or set command to tell the DSP there's new volume info. 708 */ 709 #define DSP_VOL_OUT 0 710 #define DSP_VOL_IN 1 711 712 struct ct_dsp_volume_ctl { 713 hda_nid_t vnid; 714 int mid; /* module ID*/ 715 unsigned int reqs[3]; /* scp req ID */ 716 }; 717 718 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = { 719 { .vnid = VNID_SPK, 720 .mid = 0x32, 721 .reqs = {3, 4, 2} 722 }, 723 { .vnid = VNID_MIC, 724 .mid = 0x37, 725 .reqs = {2, 3, 1} 726 } 727 }; 728 729 /* Values for ca0113_mmio_command_set for selecting output. */ 730 #define AE_CA0113_OUT_SET_COMMANDS 6 731 struct ae_ca0113_output_set { 732 unsigned int group[AE_CA0113_OUT_SET_COMMANDS]; 733 unsigned int target[AE_CA0113_OUT_SET_COMMANDS]; 734 unsigned int vals[NUM_OF_OUTPUTS][AE_CA0113_OUT_SET_COMMANDS]; 735 }; 736 737 static const struct ae_ca0113_output_set ae5_ca0113_output_presets = { 738 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 739 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 740 /* Speakers. */ 741 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }, 742 /* Headphones. */ 743 { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } }, 744 }; 745 746 static const struct ae_ca0113_output_set ae7_ca0113_output_presets = { 747 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 748 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 749 /* Speakers. */ 750 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }, 751 /* Headphones. */ 752 { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } }, 753 }; 754 755 /* ae5 ca0113 command sequences to set headphone gain levels. */ 756 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4 757 struct ae5_headphone_gain_set { 758 char *name; 759 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS]; 760 }; 761 762 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = { 763 { .name = "Low (16-31", 764 .vals = { 0xff, 0x2c, 0xf5, 0x32 } 765 }, 766 { .name = "Medium (32-149", 767 .vals = { 0x38, 0xa8, 0x3e, 0x4c } 768 }, 769 { .name = "High (150-600", 770 .vals = { 0xff, 0xff, 0xff, 0x7f } 771 } 772 }; 773 774 struct ae5_filter_set { 775 char *name; 776 unsigned int val; 777 }; 778 779 static const struct ae5_filter_set ae5_filter_presets[] = { 780 { .name = "Slow Roll Off", 781 .val = 0xa0 782 }, 783 { .name = "Minimum Phase", 784 .val = 0xc0 785 }, 786 { .name = "Fast Roll Off", 787 .val = 0x80 788 } 789 }; 790 791 /* 792 * Data structures for storing audio router remapping data. These are used to 793 * remap a currently active streams ports. 794 */ 795 struct chipio_stream_remap_data { 796 unsigned int stream_id; 797 unsigned int count; 798 799 unsigned int offset[16]; 800 unsigned int value[16]; 801 }; 802 803 static const struct chipio_stream_remap_data stream_remap_data[] = { 804 { .stream_id = 0x14, 805 .count = 0x04, 806 .offset = { 0x00, 0x04, 0x08, 0x0c }, 807 .value = { 0x0001f8c0, 0x0001f9c1, 0x0001fac6, 0x0001fbc7 }, 808 }, 809 { .stream_id = 0x0c, 810 .count = 0x0c, 811 .offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 812 0x20, 0x24, 0x28, 0x2c }, 813 .value = { 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3, 814 0x0001e2c4, 0x0001e3c5, 0x0001e8c6, 0x0001e9c7, 815 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb }, 816 }, 817 { .stream_id = 0x0c, 818 .count = 0x08, 819 .offset = { 0x08, 0x0c, 0x10, 0x14, 0x20, 0x24, 0x28, 0x2c }, 820 .value = { 0x000140c2, 0x000141c3, 0x000150c4, 0x000151c5, 821 0x000142c8, 0x000143c9, 0x000152ca, 0x000153cb }, 822 } 823 }; 824 825 enum hda_cmd_vendor_io { 826 /* for DspIO node */ 827 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000, 828 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100, 829 830 VENDOR_DSPIO_STATUS = 0xF01, 831 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702, 832 VENDOR_DSPIO_SCP_READ_DATA = 0xF02, 833 VENDOR_DSPIO_DSP_INIT = 0x703, 834 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704, 835 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04, 836 837 /* for ChipIO node */ 838 VENDOR_CHIPIO_ADDRESS_LOW = 0x000, 839 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100, 840 VENDOR_CHIPIO_STREAM_FORMAT = 0x200, 841 VENDOR_CHIPIO_DATA_LOW = 0x300, 842 VENDOR_CHIPIO_DATA_HIGH = 0x400, 843 844 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500, 845 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00, 846 847 VENDOR_CHIPIO_GET_PARAMETER = 0xF00, 848 VENDOR_CHIPIO_STATUS = 0xF01, 849 VENDOR_CHIPIO_HIC_POST_READ = 0x702, 850 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03, 851 852 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707, 853 VENDOR_CHIPIO_8051_DATA_READ = 0xF07, 854 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08, 855 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709, 856 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09, 857 858 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A, 859 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A, 860 861 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C, 862 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C, 863 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D, 864 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E, 865 VENDOR_CHIPIO_FLAG_SET = 0x70F, 866 VENDOR_CHIPIO_FLAGS_GET = 0xF0F, 867 VENDOR_CHIPIO_PARAM_SET = 0x710, 868 VENDOR_CHIPIO_PARAM_GET = 0xF10, 869 870 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711, 871 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712, 872 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12, 873 VENDOR_CHIPIO_PORT_FREE_SET = 0x713, 874 875 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17, 876 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717, 877 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18, 878 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718, 879 880 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788, 881 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88, 882 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789, 883 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89, 884 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A, 885 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A, 886 887 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D 888 }; 889 890 /* 891 * Control flag IDs 892 */ 893 enum control_flag_id { 894 /* Connection manager stream setup is bypassed/enabled */ 895 CONTROL_FLAG_C_MGR = 0, 896 /* DSP DMA is bypassed/enabled */ 897 CONTROL_FLAG_DMA = 1, 898 /* 8051 'idle' mode is disabled/enabled */ 899 CONTROL_FLAG_IDLE_ENABLE = 2, 900 /* Tracker for the SPDIF-in path is bypassed/enabled */ 901 CONTROL_FLAG_TRACKER = 3, 902 /* DigitalOut to Spdif2Out connection is disabled/enabled */ 903 CONTROL_FLAG_SPDIF2OUT = 4, 904 /* Digital Microphone is disabled/enabled */ 905 CONTROL_FLAG_DMIC = 5, 906 /* ADC_B rate is 48 kHz/96 kHz */ 907 CONTROL_FLAG_ADC_B_96KHZ = 6, 908 /* ADC_C rate is 48 kHz/96 kHz */ 909 CONTROL_FLAG_ADC_C_96KHZ = 7, 910 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */ 911 CONTROL_FLAG_DAC_96KHZ = 8, 912 /* DSP rate is 48 kHz/96 kHz */ 913 CONTROL_FLAG_DSP_96KHZ = 9, 914 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */ 915 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10, 916 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */ 917 CONTROL_FLAG_SRC_RATE_96KHZ = 11, 918 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */ 919 CONTROL_FLAG_DECODE_LOOP = 12, 920 /* De-emphasis filter on DAC-1 disabled/enabled */ 921 CONTROL_FLAG_DAC1_DEEMPHASIS = 13, 922 /* De-emphasis filter on DAC-2 disabled/enabled */ 923 CONTROL_FLAG_DAC2_DEEMPHASIS = 14, 924 /* De-emphasis filter on DAC-3 disabled/enabled */ 925 CONTROL_FLAG_DAC3_DEEMPHASIS = 15, 926 /* High-pass filter on ADC_B disabled/enabled */ 927 CONTROL_FLAG_ADC_B_HIGH_PASS = 16, 928 /* High-pass filter on ADC_C disabled/enabled */ 929 CONTROL_FLAG_ADC_C_HIGH_PASS = 17, 930 /* Common mode on Port_A disabled/enabled */ 931 CONTROL_FLAG_PORT_A_COMMON_MODE = 18, 932 /* Common mode on Port_D disabled/enabled */ 933 CONTROL_FLAG_PORT_D_COMMON_MODE = 19, 934 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */ 935 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20, 936 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */ 937 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21, 938 /* ASI rate is 48kHz/96kHz */ 939 CONTROL_FLAG_ASI_96KHZ = 22, 940 /* DAC power settings able to control attached ports no/yes */ 941 CONTROL_FLAG_DACS_CONTROL_PORTS = 23, 942 /* Clock Stop OK reporting is disabled/enabled */ 943 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24, 944 /* Number of control flags */ 945 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1) 946 }; 947 948 /* 949 * Control parameter IDs 950 */ 951 enum control_param_id { 952 /* 0: None, 1: Mic1In*/ 953 CONTROL_PARAM_VIP_SOURCE = 1, 954 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */ 955 CONTROL_PARAM_SPDIF1_SOURCE = 2, 956 /* Port A output stage gain setting to use when 16 Ohm output 957 * impedance is selected*/ 958 CONTROL_PARAM_PORTA_160OHM_GAIN = 8, 959 /* Port D output stage gain setting to use when 16 Ohm output 960 * impedance is selected*/ 961 CONTROL_PARAM_PORTD_160OHM_GAIN = 10, 962 963 /* 964 * This control param name was found in the 8051 memory, and makes 965 * sense given the fact the AE-5 uses it and has the ASI flag set. 966 */ 967 CONTROL_PARAM_ASI = 23, 968 969 /* Stream Control */ 970 971 /* Select stream with the given ID */ 972 CONTROL_PARAM_STREAM_ID = 24, 973 /* Source connection point for the selected stream */ 974 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25, 975 /* Destination connection point for the selected stream */ 976 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26, 977 /* Number of audio channels in the selected stream */ 978 CONTROL_PARAM_STREAMS_CHANNELS = 27, 979 /*Enable control for the selected stream */ 980 CONTROL_PARAM_STREAM_CONTROL = 28, 981 982 /* Connection Point Control */ 983 984 /* Select connection point with the given ID */ 985 CONTROL_PARAM_CONN_POINT_ID = 29, 986 /* Connection point sample rate */ 987 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30, 988 989 /* Node Control */ 990 991 /* Select HDA node with the given ID */ 992 CONTROL_PARAM_NODE_ID = 31 993 }; 994 995 /* 996 * Dsp Io Status codes 997 */ 998 enum hda_vendor_status_dspio { 999 /* Success */ 1000 VENDOR_STATUS_DSPIO_OK = 0x00, 1001 /* Busy, unable to accept new command, the host must retry */ 1002 VENDOR_STATUS_DSPIO_BUSY = 0x01, 1003 /* SCP command queue is full */ 1004 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02, 1005 /* SCP response queue is empty */ 1006 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03 1007 }; 1008 1009 /* 1010 * Chip Io Status codes 1011 */ 1012 enum hda_vendor_status_chipio { 1013 /* Success */ 1014 VENDOR_STATUS_CHIPIO_OK = 0x00, 1015 /* Busy, unable to accept new command, the host must retry */ 1016 VENDOR_STATUS_CHIPIO_BUSY = 0x01 1017 }; 1018 1019 /* 1020 * CA0132 sample rate 1021 */ 1022 enum ca0132_sample_rate { 1023 SR_6_000 = 0x00, 1024 SR_8_000 = 0x01, 1025 SR_9_600 = 0x02, 1026 SR_11_025 = 0x03, 1027 SR_16_000 = 0x04, 1028 SR_22_050 = 0x05, 1029 SR_24_000 = 0x06, 1030 SR_32_000 = 0x07, 1031 SR_44_100 = 0x08, 1032 SR_48_000 = 0x09, 1033 SR_88_200 = 0x0A, 1034 SR_96_000 = 0x0B, 1035 SR_144_000 = 0x0C, 1036 SR_176_400 = 0x0D, 1037 SR_192_000 = 0x0E, 1038 SR_384_000 = 0x0F, 1039 1040 SR_COUNT = 0x10, 1041 1042 SR_RATE_UNKNOWN = 0x1F 1043 }; 1044 1045 enum dsp_download_state { 1046 DSP_DOWNLOAD_FAILED = -1, 1047 DSP_DOWNLOAD_INIT = 0, 1048 DSP_DOWNLOADING = 1, 1049 DSP_DOWNLOADED = 2 1050 }; 1051 1052 /* retrieve parameters from hda format */ 1053 #define get_hdafmt_chs(fmt) (fmt & 0xf) 1054 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7) 1055 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f) 1056 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1) 1057 1058 /* 1059 * CA0132 specific 1060 */ 1061 1062 struct ca0132_spec { 1063 const struct snd_kcontrol_new *mixers[5]; 1064 unsigned int num_mixers; 1065 const struct hda_verb *base_init_verbs; 1066 const struct hda_verb *base_exit_verbs; 1067 const struct hda_verb *chip_init_verbs; 1068 const struct hda_verb *desktop_init_verbs; 1069 struct hda_verb *spec_init_verbs; 1070 struct auto_pin_cfg autocfg; 1071 1072 /* Nodes configurations */ 1073 struct hda_multi_out multiout; 1074 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS]; 1075 hda_nid_t dacs[AUTO_CFG_MAX_OUTS]; 1076 unsigned int num_outputs; 1077 hda_nid_t input_pins[AUTO_PIN_LAST]; 1078 hda_nid_t adcs[AUTO_PIN_LAST]; 1079 hda_nid_t dig_out; 1080 hda_nid_t dig_in; 1081 unsigned int num_inputs; 1082 hda_nid_t shared_mic_nid; 1083 hda_nid_t shared_out_nid; 1084 hda_nid_t unsol_tag_hp; 1085 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */ 1086 hda_nid_t unsol_tag_amic1; 1087 1088 /* chip access */ 1089 struct mutex chipio_mutex; /* chip access mutex */ 1090 u32 curr_chip_addx; 1091 1092 /* DSP download related */ 1093 enum dsp_download_state dsp_state; 1094 unsigned int dsp_stream_id; 1095 unsigned int wait_scp; 1096 unsigned int wait_scp_header; 1097 unsigned int wait_num_data; 1098 unsigned int scp_resp_header; 1099 unsigned int scp_resp_data[4]; 1100 unsigned int scp_resp_count; 1101 bool startup_check_entered; 1102 bool dsp_reload; 1103 1104 /* mixer and effects related */ 1105 unsigned char dmic_ctl; 1106 int cur_out_type; 1107 int cur_mic_type; 1108 long vnode_lvol[VNODES_COUNT]; 1109 long vnode_rvol[VNODES_COUNT]; 1110 long vnode_lswitch[VNODES_COUNT]; 1111 long vnode_rswitch[VNODES_COUNT]; 1112 long effects_switch[EFFECTS_COUNT]; 1113 long voicefx_val; 1114 long cur_mic_boost; 1115 /* ca0132_alt control related values */ 1116 unsigned char in_enum_val; 1117 unsigned char out_enum_val; 1118 unsigned char channel_cfg_val; 1119 unsigned char speaker_range_val[2]; 1120 unsigned char mic_boost_enum_val; 1121 unsigned char smart_volume_setting; 1122 unsigned char bass_redirection_val; 1123 long bass_redirect_xover_freq; 1124 long fx_ctl_val[EFFECT_LEVEL_SLIDERS]; 1125 long xbass_xover_freq; 1126 long eq_preset_val; 1127 unsigned int tlv[4]; 1128 struct hda_vmaster_mute_hook vmaster_mute; 1129 /* AE-5 Control values */ 1130 unsigned char ae5_headphone_gain_val; 1131 unsigned char ae5_filter_val; 1132 /* ZxR Control Values */ 1133 unsigned char zxr_gain_set; 1134 1135 struct hda_codec *codec; 1136 struct delayed_work unsol_hp_work; 1137 int quirk; 1138 1139 #ifdef ENABLE_TUNING_CONTROLS 1140 long cur_ctl_vals[TUNING_CTLS_COUNT]; 1141 #endif 1142 /* 1143 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster 1144 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown 1145 * things. 1146 */ 1147 bool use_pci_mmio; 1148 void __iomem *mem_base; 1149 1150 /* 1151 * Whether or not to use the alt functions like alt_select_out, 1152 * alt_select_in, etc. Only used on desktop codecs for now, because of 1153 * surround sound support. 1154 */ 1155 bool use_alt_functions; 1156 1157 /* 1158 * Whether or not to use alt controls: volume effect sliders, EQ 1159 * presets, smart volume presets, and new control names with FX prefix. 1160 * Renames PlayEnhancement and CrystalVoice too. 1161 */ 1162 bool use_alt_controls; 1163 }; 1164 1165 /* 1166 * CA0132 quirks table 1167 */ 1168 enum { 1169 QUIRK_NONE, 1170 QUIRK_ALIENWARE, 1171 QUIRK_ALIENWARE_M17XR4, 1172 QUIRK_SBZ, 1173 QUIRK_ZXR, 1174 QUIRK_ZXR_DBPRO, 1175 QUIRK_R3DI, 1176 QUIRK_R3D, 1177 QUIRK_AE5, 1178 QUIRK_AE7, 1179 }; 1180 1181 #ifdef CONFIG_PCI 1182 #define ca0132_quirk(spec) ((spec)->quirk) 1183 #define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio) 1184 #define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions) 1185 #define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls) 1186 #else 1187 #define ca0132_quirk(spec) ({ (void)(spec); QUIRK_NONE; }) 1188 #define ca0132_use_alt_functions(spec) ({ (void)(spec); false; }) 1189 #define ca0132_use_pci_mmio(spec) ({ (void)(spec); false; }) 1190 #define ca0132_use_alt_controls(spec) ({ (void)(spec); false; }) 1191 #endif 1192 1193 static const struct hda_pintbl alienware_pincfgs[] = { 1194 { 0x0b, 0x90170110 }, /* Builtin Speaker */ 1195 { 0x0c, 0x411111f0 }, /* N/A */ 1196 { 0x0d, 0x411111f0 }, /* N/A */ 1197 { 0x0e, 0x411111f0 }, /* N/A */ 1198 { 0x0f, 0x0321101f }, /* HP */ 1199 { 0x10, 0x411111f0 }, /* Headset? disabled for now */ 1200 { 0x11, 0x03a11021 }, /* Mic */ 1201 { 0x12, 0xd5a30140 }, /* Builtin Mic */ 1202 { 0x13, 0x411111f0 }, /* N/A */ 1203 { 0x18, 0x411111f0 }, /* N/A */ 1204 {} 1205 }; 1206 1207 /* Sound Blaster Z pin configs taken from Windows Driver */ 1208 static const struct hda_pintbl sbz_pincfgs[] = { 1209 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1210 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1211 { 0x0d, 0x014510f0 }, /* Digital Out */ 1212 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1213 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */ 1214 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1215 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1216 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1217 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1218 { 0x18, 0x50d000f0 }, /* N/A */ 1219 {} 1220 }; 1221 1222 /* Sound Blaster ZxR pin configs taken from Windows Driver */ 1223 static const struct hda_pintbl zxr_pincfgs[] = { 1224 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */ 1225 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/ 1226 { 0x0d, 0x014510f0 }, /* Digital Out */ 1227 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/ 1228 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */ 1229 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */ 1230 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */ 1231 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */ 1232 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1233 { 0x18, 0x50d000f0 }, /* N/A */ 1234 {} 1235 }; 1236 1237 /* Recon3D pin configs taken from Windows Driver */ 1238 static const struct hda_pintbl r3d_pincfgs[] = { 1239 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1240 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1241 { 0x0d, 0x014510f0 }, /* Digital Out */ 1242 { 0x0e, 0x01c520f0 }, /* SPDIF In */ 1243 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1244 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1245 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1246 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1247 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1248 { 0x18, 0x50d000f0 }, /* N/A */ 1249 {} 1250 }; 1251 1252 /* Sound Blaster AE-5 pin configs taken from Windows Driver */ 1253 static const struct hda_pintbl ae5_pincfgs[] = { 1254 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1255 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1256 { 0x0d, 0x014510f0 }, /* Digital Out */ 1257 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1258 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */ 1259 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1260 { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */ 1261 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1262 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1263 { 0x18, 0x50d000f0 }, /* N/A */ 1264 {} 1265 }; 1266 1267 /* Recon3D integrated pin configs taken from Windows Driver */ 1268 static const struct hda_pintbl r3di_pincfgs[] = { 1269 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1270 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1271 { 0x0d, 0x014510f0 }, /* Digital Out */ 1272 { 0x0e, 0x41c520f0 }, /* SPDIF In */ 1273 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1274 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1275 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1276 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1277 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1278 { 0x18, 0x500000f0 }, /* N/A */ 1279 {} 1280 }; 1281 1282 static const struct hda_pintbl ae7_pincfgs[] = { 1283 { 0x0b, 0x01017010 }, 1284 { 0x0c, 0x014510f0 }, 1285 { 0x0d, 0x414510f0 }, 1286 { 0x0e, 0x01c520f0 }, 1287 { 0x0f, 0x01017114 }, 1288 { 0x10, 0x01017011 }, 1289 { 0x11, 0x018170ff }, 1290 { 0x12, 0x01a170f0 }, 1291 { 0x13, 0x908700f0 }, 1292 { 0x18, 0x500000f0 }, 1293 {} 1294 }; 1295 1296 static const struct snd_pci_quirk ca0132_quirks[] = { 1297 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4), 1298 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE), 1299 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE), 1300 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE), 1301 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ), 1302 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ), 1303 SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ), 1304 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ), 1305 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI), 1306 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI), 1307 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI), 1308 SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI), 1309 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D), 1310 SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D), 1311 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5), 1312 SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7), 1313 {} 1314 }; 1315 1316 /* Output selection quirk info structures. */ 1317 #define MAX_QUIRK_MMIO_GPIO_SET_VALS 3 1318 #define MAX_QUIRK_SCP_SET_VALS 2 1319 struct ca0132_alt_out_set_info { 1320 unsigned int dac2port; /* ParamID 0x0d value. */ 1321 1322 bool has_hda_gpio; 1323 char hda_gpio_pin; 1324 char hda_gpio_set; 1325 1326 unsigned int mmio_gpio_count; 1327 char mmio_gpio_pin[MAX_QUIRK_MMIO_GPIO_SET_VALS]; 1328 char mmio_gpio_set[MAX_QUIRK_MMIO_GPIO_SET_VALS]; 1329 1330 unsigned int scp_cmds_count; 1331 unsigned int scp_cmd_mid[MAX_QUIRK_SCP_SET_VALS]; 1332 unsigned int scp_cmd_req[MAX_QUIRK_SCP_SET_VALS]; 1333 unsigned int scp_cmd_val[MAX_QUIRK_SCP_SET_VALS]; 1334 1335 bool has_chipio_write; 1336 unsigned int chipio_write_addr; 1337 unsigned int chipio_write_data; 1338 }; 1339 1340 struct ca0132_alt_out_set_quirk_data { 1341 int quirk_id; 1342 1343 bool has_headphone_gain; 1344 bool is_ae_series; 1345 1346 struct ca0132_alt_out_set_info out_set_info[NUM_OF_OUTPUTS]; 1347 }; 1348 1349 static const struct ca0132_alt_out_set_quirk_data quirk_out_set_data[] = { 1350 { .quirk_id = QUIRK_R3DI, 1351 .has_headphone_gain = false, 1352 .is_ae_series = false, 1353 .out_set_info = { 1354 /* Speakers. */ 1355 { .dac2port = 0x24, 1356 .has_hda_gpio = true, 1357 .hda_gpio_pin = 2, 1358 .hda_gpio_set = 1, 1359 .mmio_gpio_count = 0, 1360 .scp_cmds_count = 0, 1361 .has_chipio_write = false, 1362 }, 1363 /* Headphones. */ 1364 { .dac2port = 0x21, 1365 .has_hda_gpio = true, 1366 .hda_gpio_pin = 2, 1367 .hda_gpio_set = 0, 1368 .mmio_gpio_count = 0, 1369 .scp_cmds_count = 0, 1370 .has_chipio_write = false, 1371 } }, 1372 }, 1373 { .quirk_id = QUIRK_R3D, 1374 .has_headphone_gain = false, 1375 .is_ae_series = false, 1376 .out_set_info = { 1377 /* Speakers. */ 1378 { .dac2port = 0x24, 1379 .has_hda_gpio = false, 1380 .mmio_gpio_count = 1, 1381 .mmio_gpio_pin = { 1 }, 1382 .mmio_gpio_set = { 1 }, 1383 .scp_cmds_count = 0, 1384 .has_chipio_write = false, 1385 }, 1386 /* Headphones. */ 1387 { .dac2port = 0x21, 1388 .has_hda_gpio = false, 1389 .mmio_gpio_count = 1, 1390 .mmio_gpio_pin = { 1 }, 1391 .mmio_gpio_set = { 0 }, 1392 .scp_cmds_count = 0, 1393 .has_chipio_write = false, 1394 } }, 1395 }, 1396 { .quirk_id = QUIRK_SBZ, 1397 .has_headphone_gain = false, 1398 .is_ae_series = false, 1399 .out_set_info = { 1400 /* Speakers. */ 1401 { .dac2port = 0x18, 1402 .has_hda_gpio = false, 1403 .mmio_gpio_count = 3, 1404 .mmio_gpio_pin = { 7, 4, 1 }, 1405 .mmio_gpio_set = { 0, 1, 1 }, 1406 .scp_cmds_count = 0, 1407 .has_chipio_write = false, }, 1408 /* Headphones. */ 1409 { .dac2port = 0x12, 1410 .has_hda_gpio = false, 1411 .mmio_gpio_count = 3, 1412 .mmio_gpio_pin = { 7, 4, 1 }, 1413 .mmio_gpio_set = { 1, 1, 0 }, 1414 .scp_cmds_count = 0, 1415 .has_chipio_write = false, 1416 } }, 1417 }, 1418 { .quirk_id = QUIRK_ZXR, 1419 .has_headphone_gain = true, 1420 .is_ae_series = false, 1421 .out_set_info = { 1422 /* Speakers. */ 1423 { .dac2port = 0x24, 1424 .has_hda_gpio = false, 1425 .mmio_gpio_count = 3, 1426 .mmio_gpio_pin = { 2, 3, 5 }, 1427 .mmio_gpio_set = { 1, 1, 0 }, 1428 .scp_cmds_count = 0, 1429 .has_chipio_write = false, 1430 }, 1431 /* Headphones. */ 1432 { .dac2port = 0x21, 1433 .has_hda_gpio = false, 1434 .mmio_gpio_count = 3, 1435 .mmio_gpio_pin = { 2, 3, 5 }, 1436 .mmio_gpio_set = { 0, 1, 1 }, 1437 .scp_cmds_count = 0, 1438 .has_chipio_write = false, 1439 } }, 1440 }, 1441 { .quirk_id = QUIRK_AE5, 1442 .has_headphone_gain = true, 1443 .is_ae_series = true, 1444 .out_set_info = { 1445 /* Speakers. */ 1446 { .dac2port = 0xa4, 1447 .has_hda_gpio = false, 1448 .mmio_gpio_count = 0, 1449 .scp_cmds_count = 2, 1450 .scp_cmd_mid = { 0x96, 0x96 }, 1451 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1452 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1453 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO }, 1454 .has_chipio_write = true, 1455 .chipio_write_addr = 0x0018b03c, 1456 .chipio_write_data = 0x00000012 1457 }, 1458 /* Headphones. */ 1459 { .dac2port = 0xa1, 1460 .has_hda_gpio = false, 1461 .mmio_gpio_count = 0, 1462 .scp_cmds_count = 2, 1463 .scp_cmd_mid = { 0x96, 0x96 }, 1464 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1465 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1466 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE }, 1467 .has_chipio_write = true, 1468 .chipio_write_addr = 0x0018b03c, 1469 .chipio_write_data = 0x00000012 1470 } }, 1471 }, 1472 { .quirk_id = QUIRK_AE7, 1473 .has_headphone_gain = true, 1474 .is_ae_series = true, 1475 .out_set_info = { 1476 /* Speakers. */ 1477 { .dac2port = 0x58, 1478 .has_hda_gpio = false, 1479 .mmio_gpio_count = 1, 1480 .mmio_gpio_pin = { 0 }, 1481 .mmio_gpio_set = { 1 }, 1482 .scp_cmds_count = 2, 1483 .scp_cmd_mid = { 0x96, 0x96 }, 1484 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1485 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1486 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO }, 1487 .has_chipio_write = true, 1488 .chipio_write_addr = 0x0018b03c, 1489 .chipio_write_data = 0x00000000 1490 }, 1491 /* Headphones. */ 1492 { .dac2port = 0x58, 1493 .has_hda_gpio = false, 1494 .mmio_gpio_count = 1, 1495 .mmio_gpio_pin = { 0 }, 1496 .mmio_gpio_set = { 1 }, 1497 .scp_cmds_count = 2, 1498 .scp_cmd_mid = { 0x96, 0x96 }, 1499 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1500 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1501 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE }, 1502 .has_chipio_write = true, 1503 .chipio_write_addr = 0x0018b03c, 1504 .chipio_write_data = 0x00000010 1505 } }, 1506 } 1507 }; 1508 1509 /* 1510 * CA0132 codec access 1511 */ 1512 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid, 1513 unsigned int verb, unsigned int parm, unsigned int *res) 1514 { 1515 unsigned int response; 1516 response = snd_hda_codec_read(codec, nid, 0, verb, parm); 1517 *res = response; 1518 1519 return ((response == -1) ? -1 : 0); 1520 } 1521 1522 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid, 1523 unsigned short converter_format, unsigned int *res) 1524 { 1525 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT, 1526 converter_format & 0xffff, res); 1527 } 1528 1529 static int codec_set_converter_stream_channel(struct hda_codec *codec, 1530 hda_nid_t nid, unsigned char stream, 1531 unsigned char channel, unsigned int *res) 1532 { 1533 unsigned char converter_stream_channel = 0; 1534 1535 converter_stream_channel = (stream << 4) | (channel & 0x0f); 1536 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID, 1537 converter_stream_channel, res); 1538 } 1539 1540 /* Chip access helper function */ 1541 static int chipio_send(struct hda_codec *codec, 1542 unsigned int reg, 1543 unsigned int data) 1544 { 1545 unsigned int res; 1546 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1547 1548 /* send bits of data specified by reg */ 1549 do { 1550 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1551 reg, data); 1552 if (res == VENDOR_STATUS_CHIPIO_OK) 1553 return 0; 1554 msleep(20); 1555 } while (time_before(jiffies, timeout)); 1556 1557 return -EIO; 1558 } 1559 1560 /* 1561 * Write chip address through the vendor widget -- NOT protected by the Mutex! 1562 */ 1563 static int chipio_write_address(struct hda_codec *codec, 1564 unsigned int chip_addx) 1565 { 1566 struct ca0132_spec *spec = codec->spec; 1567 int res; 1568 1569 if (spec->curr_chip_addx == chip_addx) 1570 return 0; 1571 1572 /* send low 16 bits of the address */ 1573 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW, 1574 chip_addx & 0xffff); 1575 1576 if (res != -EIO) { 1577 /* send high 16 bits of the address */ 1578 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH, 1579 chip_addx >> 16); 1580 } 1581 1582 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx; 1583 1584 return res; 1585 } 1586 1587 /* 1588 * Write data through the vendor widget -- NOT protected by the Mutex! 1589 */ 1590 static int chipio_write_data(struct hda_codec *codec, unsigned int data) 1591 { 1592 struct ca0132_spec *spec = codec->spec; 1593 int res; 1594 1595 /* send low 16 bits of the data */ 1596 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff); 1597 1598 if (res != -EIO) { 1599 /* send high 16 bits of the data */ 1600 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH, 1601 data >> 16); 1602 } 1603 1604 /*If no error encountered, automatically increment the address 1605 as per chip behaviour*/ 1606 spec->curr_chip_addx = (res != -EIO) ? 1607 (spec->curr_chip_addx + 4) : ~0U; 1608 return res; 1609 } 1610 1611 /* 1612 * Write multiple data through the vendor widget -- NOT protected by the Mutex! 1613 */ 1614 static int chipio_write_data_multiple(struct hda_codec *codec, 1615 const u32 *data, 1616 unsigned int count) 1617 { 1618 int status = 0; 1619 1620 if (data == NULL) { 1621 codec_dbg(codec, "chipio_write_data null ptr\n"); 1622 return -EINVAL; 1623 } 1624 1625 while ((count-- != 0) && (status == 0)) 1626 status = chipio_write_data(codec, *data++); 1627 1628 return status; 1629 } 1630 1631 1632 /* 1633 * Read data through the vendor widget -- NOT protected by the Mutex! 1634 */ 1635 static int chipio_read_data(struct hda_codec *codec, unsigned int *data) 1636 { 1637 struct ca0132_spec *spec = codec->spec; 1638 int res; 1639 1640 /* post read */ 1641 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0); 1642 1643 if (res != -EIO) { 1644 /* read status */ 1645 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 1646 } 1647 1648 if (res != -EIO) { 1649 /* read data */ 1650 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1651 VENDOR_CHIPIO_HIC_READ_DATA, 1652 0); 1653 } 1654 1655 /*If no error encountered, automatically increment the address 1656 as per chip behaviour*/ 1657 spec->curr_chip_addx = (res != -EIO) ? 1658 (spec->curr_chip_addx + 4) : ~0U; 1659 return res; 1660 } 1661 1662 /* 1663 * Write given value to the given address through the chip I/O widget. 1664 * protected by the Mutex 1665 */ 1666 static int chipio_write(struct hda_codec *codec, 1667 unsigned int chip_addx, const unsigned int data) 1668 { 1669 struct ca0132_spec *spec = codec->spec; 1670 int err; 1671 1672 mutex_lock(&spec->chipio_mutex); 1673 1674 /* write the address, and if successful proceed to write data */ 1675 err = chipio_write_address(codec, chip_addx); 1676 if (err < 0) 1677 goto exit; 1678 1679 err = chipio_write_data(codec, data); 1680 if (err < 0) 1681 goto exit; 1682 1683 exit: 1684 mutex_unlock(&spec->chipio_mutex); 1685 return err; 1686 } 1687 1688 /* 1689 * Write given value to the given address through the chip I/O widget. 1690 * not protected by the Mutex 1691 */ 1692 static int chipio_write_no_mutex(struct hda_codec *codec, 1693 unsigned int chip_addx, const unsigned int data) 1694 { 1695 int err; 1696 1697 1698 /* write the address, and if successful proceed to write data */ 1699 err = chipio_write_address(codec, chip_addx); 1700 if (err < 0) 1701 goto exit; 1702 1703 err = chipio_write_data(codec, data); 1704 if (err < 0) 1705 goto exit; 1706 1707 exit: 1708 return err; 1709 } 1710 1711 /* 1712 * Write multiple values to the given address through the chip I/O widget. 1713 * protected by the Mutex 1714 */ 1715 static int chipio_write_multiple(struct hda_codec *codec, 1716 u32 chip_addx, 1717 const u32 *data, 1718 unsigned int count) 1719 { 1720 struct ca0132_spec *spec = codec->spec; 1721 int status; 1722 1723 mutex_lock(&spec->chipio_mutex); 1724 status = chipio_write_address(codec, chip_addx); 1725 if (status < 0) 1726 goto error; 1727 1728 status = chipio_write_data_multiple(codec, data, count); 1729 error: 1730 mutex_unlock(&spec->chipio_mutex); 1731 1732 return status; 1733 } 1734 1735 /* 1736 * Read the given address through the chip I/O widget 1737 * protected by the Mutex 1738 */ 1739 static int chipio_read(struct hda_codec *codec, 1740 unsigned int chip_addx, unsigned int *data) 1741 { 1742 struct ca0132_spec *spec = codec->spec; 1743 int err; 1744 1745 mutex_lock(&spec->chipio_mutex); 1746 1747 /* write the address, and if successful proceed to write data */ 1748 err = chipio_write_address(codec, chip_addx); 1749 if (err < 0) 1750 goto exit; 1751 1752 err = chipio_read_data(codec, data); 1753 if (err < 0) 1754 goto exit; 1755 1756 exit: 1757 mutex_unlock(&spec->chipio_mutex); 1758 return err; 1759 } 1760 1761 /* 1762 * Set chip control flags through the chip I/O widget. 1763 */ 1764 static void chipio_set_control_flag(struct hda_codec *codec, 1765 enum control_flag_id flag_id, 1766 bool flag_state) 1767 { 1768 unsigned int val; 1769 unsigned int flag_bit; 1770 1771 flag_bit = (flag_state ? 1 : 0); 1772 val = (flag_bit << 7) | (flag_id); 1773 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1774 VENDOR_CHIPIO_FLAG_SET, val); 1775 } 1776 1777 /* 1778 * Set chip parameters through the chip I/O widget. 1779 */ 1780 static void chipio_set_control_param(struct hda_codec *codec, 1781 enum control_param_id param_id, int param_val) 1782 { 1783 struct ca0132_spec *spec = codec->spec; 1784 int val; 1785 1786 if ((param_id < 32) && (param_val < 8)) { 1787 val = (param_val << 5) | (param_id); 1788 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1789 VENDOR_CHIPIO_PARAM_SET, val); 1790 } else { 1791 mutex_lock(&spec->chipio_mutex); 1792 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1793 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1794 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1795 param_id); 1796 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1797 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1798 param_val); 1799 } 1800 mutex_unlock(&spec->chipio_mutex); 1801 } 1802 } 1803 1804 /* 1805 * Set chip parameters through the chip I/O widget. NO MUTEX. 1806 */ 1807 static void chipio_set_control_param_no_mutex(struct hda_codec *codec, 1808 enum control_param_id param_id, int param_val) 1809 { 1810 int val; 1811 1812 if ((param_id < 32) && (param_val < 8)) { 1813 val = (param_val << 5) | (param_id); 1814 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1815 VENDOR_CHIPIO_PARAM_SET, val); 1816 } else { 1817 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1818 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1819 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1820 param_id); 1821 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1822 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1823 param_val); 1824 } 1825 } 1826 } 1827 /* 1828 * Connect stream to a source point, and then connect 1829 * that source point to a destination point. 1830 */ 1831 static void chipio_set_stream_source_dest(struct hda_codec *codec, 1832 int streamid, int source_point, int dest_point) 1833 { 1834 chipio_set_control_param_no_mutex(codec, 1835 CONTROL_PARAM_STREAM_ID, streamid); 1836 chipio_set_control_param_no_mutex(codec, 1837 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point); 1838 chipio_set_control_param_no_mutex(codec, 1839 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point); 1840 } 1841 1842 /* 1843 * Set number of channels in the selected stream. 1844 */ 1845 static void chipio_set_stream_channels(struct hda_codec *codec, 1846 int streamid, unsigned int channels) 1847 { 1848 chipio_set_control_param_no_mutex(codec, 1849 CONTROL_PARAM_STREAM_ID, streamid); 1850 chipio_set_control_param_no_mutex(codec, 1851 CONTROL_PARAM_STREAMS_CHANNELS, channels); 1852 } 1853 1854 /* 1855 * Enable/Disable audio stream. 1856 */ 1857 static void chipio_set_stream_control(struct hda_codec *codec, 1858 int streamid, int enable) 1859 { 1860 chipio_set_control_param_no_mutex(codec, 1861 CONTROL_PARAM_STREAM_ID, streamid); 1862 chipio_set_control_param_no_mutex(codec, 1863 CONTROL_PARAM_STREAM_CONTROL, enable); 1864 } 1865 1866 /* 1867 * Get ChipIO audio stream's status. 1868 */ 1869 static void chipio_get_stream_control(struct hda_codec *codec, 1870 int streamid, unsigned int *enable) 1871 { 1872 chipio_set_control_param_no_mutex(codec, 1873 CONTROL_PARAM_STREAM_ID, streamid); 1874 *enable = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1875 VENDOR_CHIPIO_PARAM_GET, 1876 CONTROL_PARAM_STREAM_CONTROL); 1877 } 1878 1879 /* 1880 * Set sampling rate of the connection point. NO MUTEX. 1881 */ 1882 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec, 1883 int connid, enum ca0132_sample_rate rate) 1884 { 1885 chipio_set_control_param_no_mutex(codec, 1886 CONTROL_PARAM_CONN_POINT_ID, connid); 1887 chipio_set_control_param_no_mutex(codec, 1888 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate); 1889 } 1890 1891 /* 1892 * Set sampling rate of the connection point. 1893 */ 1894 static void chipio_set_conn_rate(struct hda_codec *codec, 1895 int connid, enum ca0132_sample_rate rate) 1896 { 1897 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid); 1898 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, 1899 rate); 1900 } 1901 1902 /* 1903 * Writes to the 8051's internal address space directly instead of indirectly, 1904 * giving access to the special function registers located at addresses 1905 * 0x80-0xFF. 1906 */ 1907 static void chipio_8051_write_direct(struct hda_codec *codec, 1908 unsigned int addr, unsigned int data) 1909 { 1910 unsigned int verb; 1911 1912 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data; 1913 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr); 1914 } 1915 1916 /* 1917 * Writes to the 8051's exram, which has 16-bits of address space. 1918 * Data at addresses 0x2000-0x7fff is mirrored to 0x8000-0xdfff. 1919 * Data at 0x8000-0xdfff can also be used as program memory for the 8051 by 1920 * setting the pmem bank selection SFR. 1921 * 0xe000-0xffff is always mapped as program memory, with only 0xf000-0xffff 1922 * being writable. 1923 */ 1924 static void chipio_8051_set_address(struct hda_codec *codec, unsigned int addr) 1925 { 1926 unsigned int tmp; 1927 1928 /* Lower 8-bits. */ 1929 tmp = addr & 0xff; 1930 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1931 VENDOR_CHIPIO_8051_ADDRESS_LOW, tmp); 1932 1933 /* Upper 8-bits. */ 1934 tmp = (addr >> 8) & 0xff; 1935 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1936 VENDOR_CHIPIO_8051_ADDRESS_HIGH, tmp); 1937 } 1938 1939 static void chipio_8051_set_data(struct hda_codec *codec, unsigned int data) 1940 { 1941 /* 8-bits of data. */ 1942 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1943 VENDOR_CHIPIO_8051_DATA_WRITE, data & 0xff); 1944 } 1945 1946 static unsigned int chipio_8051_get_data(struct hda_codec *codec) 1947 { 1948 return snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1949 VENDOR_CHIPIO_8051_DATA_READ, 0); 1950 } 1951 1952 /* PLL_PMU writes share the lower address register of the 8051 exram writes. */ 1953 static void chipio_8051_set_data_pll(struct hda_codec *codec, unsigned int data) 1954 { 1955 /* 8-bits of data. */ 1956 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1957 VENDOR_CHIPIO_PLL_PMU_WRITE, data & 0xff); 1958 } 1959 1960 static void chipio_8051_write_exram(struct hda_codec *codec, 1961 unsigned int addr, unsigned int data) 1962 { 1963 struct ca0132_spec *spec = codec->spec; 1964 1965 mutex_lock(&spec->chipio_mutex); 1966 1967 chipio_8051_set_address(codec, addr); 1968 chipio_8051_set_data(codec, data); 1969 1970 mutex_unlock(&spec->chipio_mutex); 1971 } 1972 1973 static void chipio_8051_write_exram_no_mutex(struct hda_codec *codec, 1974 unsigned int addr, unsigned int data) 1975 { 1976 chipio_8051_set_address(codec, addr); 1977 chipio_8051_set_data(codec, data); 1978 } 1979 1980 /* Readback data from the 8051's exram. No mutex. */ 1981 static void chipio_8051_read_exram(struct hda_codec *codec, 1982 unsigned int addr, unsigned int *data) 1983 { 1984 chipio_8051_set_address(codec, addr); 1985 *data = chipio_8051_get_data(codec); 1986 } 1987 1988 static void chipio_8051_write_pll_pmu(struct hda_codec *codec, 1989 unsigned int addr, unsigned int data) 1990 { 1991 struct ca0132_spec *spec = codec->spec; 1992 1993 mutex_lock(&spec->chipio_mutex); 1994 1995 chipio_8051_set_address(codec, addr & 0xff); 1996 chipio_8051_set_data_pll(codec, data); 1997 1998 mutex_unlock(&spec->chipio_mutex); 1999 } 2000 2001 static void chipio_8051_write_pll_pmu_no_mutex(struct hda_codec *codec, 2002 unsigned int addr, unsigned int data) 2003 { 2004 chipio_8051_set_address(codec, addr & 0xff); 2005 chipio_8051_set_data_pll(codec, data); 2006 } 2007 2008 /* 2009 * Enable clocks. 2010 */ 2011 static void chipio_enable_clocks(struct hda_codec *codec) 2012 { 2013 struct ca0132_spec *spec = codec->spec; 2014 2015 mutex_lock(&spec->chipio_mutex); 2016 2017 chipio_8051_write_pll_pmu_no_mutex(codec, 0x00, 0xff); 2018 chipio_8051_write_pll_pmu_no_mutex(codec, 0x05, 0x0b); 2019 chipio_8051_write_pll_pmu_no_mutex(codec, 0x06, 0xff); 2020 2021 mutex_unlock(&spec->chipio_mutex); 2022 } 2023 2024 /* 2025 * CA0132 DSP IO stuffs 2026 */ 2027 static int dspio_send(struct hda_codec *codec, unsigned int reg, 2028 unsigned int data) 2029 { 2030 int res; 2031 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2032 2033 /* send bits of data specified by reg to dsp */ 2034 do { 2035 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data); 2036 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY)) 2037 return res; 2038 msleep(20); 2039 } while (time_before(jiffies, timeout)); 2040 2041 return -EIO; 2042 } 2043 2044 /* 2045 * Wait for DSP to be ready for commands 2046 */ 2047 static void dspio_write_wait(struct hda_codec *codec) 2048 { 2049 int status; 2050 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2051 2052 do { 2053 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 2054 VENDOR_DSPIO_STATUS, 0); 2055 if ((status == VENDOR_STATUS_DSPIO_OK) || 2056 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)) 2057 break; 2058 msleep(1); 2059 } while (time_before(jiffies, timeout)); 2060 } 2061 2062 /* 2063 * Write SCP data to DSP 2064 */ 2065 static int dspio_write(struct hda_codec *codec, unsigned int scp_data) 2066 { 2067 struct ca0132_spec *spec = codec->spec; 2068 int status; 2069 2070 dspio_write_wait(codec); 2071 2072 mutex_lock(&spec->chipio_mutex); 2073 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW, 2074 scp_data & 0xffff); 2075 if (status < 0) 2076 goto error; 2077 2078 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH, 2079 scp_data >> 16); 2080 if (status < 0) 2081 goto error; 2082 2083 /* OK, now check if the write itself has executed*/ 2084 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 2085 VENDOR_DSPIO_STATUS, 0); 2086 error: 2087 mutex_unlock(&spec->chipio_mutex); 2088 2089 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ? 2090 -EIO : 0; 2091 } 2092 2093 /* 2094 * Write multiple SCP data to DSP 2095 */ 2096 static int dspio_write_multiple(struct hda_codec *codec, 2097 unsigned int *buffer, unsigned int size) 2098 { 2099 int status = 0; 2100 unsigned int count; 2101 2102 if (buffer == NULL) 2103 return -EINVAL; 2104 2105 count = 0; 2106 while (count < size) { 2107 status = dspio_write(codec, *buffer++); 2108 if (status != 0) 2109 break; 2110 count++; 2111 } 2112 2113 return status; 2114 } 2115 2116 static int dspio_read(struct hda_codec *codec, unsigned int *data) 2117 { 2118 int status; 2119 2120 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0); 2121 if (status == -EIO) 2122 return status; 2123 2124 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0); 2125 if (status == -EIO || 2126 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY) 2127 return -EIO; 2128 2129 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 2130 VENDOR_DSPIO_SCP_READ_DATA, 0); 2131 2132 return 0; 2133 } 2134 2135 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer, 2136 unsigned int *buf_size, unsigned int size_count) 2137 { 2138 int status = 0; 2139 unsigned int size = *buf_size; 2140 unsigned int count; 2141 unsigned int skip_count; 2142 unsigned int dummy; 2143 2144 if (buffer == NULL) 2145 return -1; 2146 2147 count = 0; 2148 while (count < size && count < size_count) { 2149 status = dspio_read(codec, buffer++); 2150 if (status != 0) 2151 break; 2152 count++; 2153 } 2154 2155 skip_count = count; 2156 if (status == 0) { 2157 while (skip_count < size) { 2158 status = dspio_read(codec, &dummy); 2159 if (status != 0) 2160 break; 2161 skip_count++; 2162 } 2163 } 2164 *buf_size = count; 2165 2166 return status; 2167 } 2168 2169 /* 2170 * Construct the SCP header using corresponding fields 2171 */ 2172 static inline unsigned int 2173 make_scp_header(unsigned int target_id, unsigned int source_id, 2174 unsigned int get_flag, unsigned int req, 2175 unsigned int device_flag, unsigned int resp_flag, 2176 unsigned int error_flag, unsigned int data_size) 2177 { 2178 unsigned int header = 0; 2179 2180 header = (data_size & 0x1f) << 27; 2181 header |= (error_flag & 0x01) << 26; 2182 header |= (resp_flag & 0x01) << 25; 2183 header |= (device_flag & 0x01) << 24; 2184 header |= (req & 0x7f) << 17; 2185 header |= (get_flag & 0x01) << 16; 2186 header |= (source_id & 0xff) << 8; 2187 header |= target_id & 0xff; 2188 2189 return header; 2190 } 2191 2192 /* 2193 * Extract corresponding fields from SCP header 2194 */ 2195 static inline void 2196 extract_scp_header(unsigned int header, 2197 unsigned int *target_id, unsigned int *source_id, 2198 unsigned int *get_flag, unsigned int *req, 2199 unsigned int *device_flag, unsigned int *resp_flag, 2200 unsigned int *error_flag, unsigned int *data_size) 2201 { 2202 if (data_size) 2203 *data_size = (header >> 27) & 0x1f; 2204 if (error_flag) 2205 *error_flag = (header >> 26) & 0x01; 2206 if (resp_flag) 2207 *resp_flag = (header >> 25) & 0x01; 2208 if (device_flag) 2209 *device_flag = (header >> 24) & 0x01; 2210 if (req) 2211 *req = (header >> 17) & 0x7f; 2212 if (get_flag) 2213 *get_flag = (header >> 16) & 0x01; 2214 if (source_id) 2215 *source_id = (header >> 8) & 0xff; 2216 if (target_id) 2217 *target_id = header & 0xff; 2218 } 2219 2220 #define SCP_MAX_DATA_WORDS (16) 2221 2222 /* Structure to contain any SCP message */ 2223 struct scp_msg { 2224 unsigned int hdr; 2225 unsigned int data[SCP_MAX_DATA_WORDS]; 2226 }; 2227 2228 static void dspio_clear_response_queue(struct hda_codec *codec) 2229 { 2230 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2231 unsigned int dummy = 0; 2232 int status; 2233 2234 /* clear all from the response queue */ 2235 do { 2236 status = dspio_read(codec, &dummy); 2237 } while (status == 0 && time_before(jiffies, timeout)); 2238 } 2239 2240 static int dspio_get_response_data(struct hda_codec *codec) 2241 { 2242 struct ca0132_spec *spec = codec->spec; 2243 unsigned int data = 0; 2244 unsigned int count; 2245 2246 if (dspio_read(codec, &data) < 0) 2247 return -EIO; 2248 2249 if ((data & 0x00ffffff) == spec->wait_scp_header) { 2250 spec->scp_resp_header = data; 2251 spec->scp_resp_count = data >> 27; 2252 count = spec->wait_num_data; 2253 dspio_read_multiple(codec, spec->scp_resp_data, 2254 &spec->scp_resp_count, count); 2255 return 0; 2256 } 2257 2258 return -EIO; 2259 } 2260 2261 /* 2262 * Send SCP message to DSP 2263 */ 2264 static int dspio_send_scp_message(struct hda_codec *codec, 2265 unsigned char *send_buf, 2266 unsigned int send_buf_size, 2267 unsigned char *return_buf, 2268 unsigned int return_buf_size, 2269 unsigned int *bytes_returned) 2270 { 2271 struct ca0132_spec *spec = codec->spec; 2272 int status = -1; 2273 unsigned int scp_send_size = 0; 2274 unsigned int total_size; 2275 bool waiting_for_resp = false; 2276 unsigned int header; 2277 struct scp_msg *ret_msg; 2278 unsigned int resp_src_id, resp_target_id; 2279 unsigned int data_size, src_id, target_id, get_flag, device_flag; 2280 2281 if (bytes_returned) 2282 *bytes_returned = 0; 2283 2284 /* get scp header from buffer */ 2285 header = *((unsigned int *)send_buf); 2286 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL, 2287 &device_flag, NULL, NULL, &data_size); 2288 scp_send_size = data_size + 1; 2289 total_size = (scp_send_size * 4); 2290 2291 if (send_buf_size < total_size) 2292 return -EINVAL; 2293 2294 if (get_flag || device_flag) { 2295 if (!return_buf || return_buf_size < 4 || !bytes_returned) 2296 return -EINVAL; 2297 2298 spec->wait_scp_header = *((unsigned int *)send_buf); 2299 2300 /* swap source id with target id */ 2301 resp_target_id = src_id; 2302 resp_src_id = target_id; 2303 spec->wait_scp_header &= 0xffff0000; 2304 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id); 2305 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1; 2306 spec->wait_scp = 1; 2307 waiting_for_resp = true; 2308 } 2309 2310 status = dspio_write_multiple(codec, (unsigned int *)send_buf, 2311 scp_send_size); 2312 if (status < 0) { 2313 spec->wait_scp = 0; 2314 return status; 2315 } 2316 2317 if (waiting_for_resp) { 2318 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2319 memset(return_buf, 0, return_buf_size); 2320 do { 2321 msleep(20); 2322 } while (spec->wait_scp && time_before(jiffies, timeout)); 2323 waiting_for_resp = false; 2324 if (!spec->wait_scp) { 2325 ret_msg = (struct scp_msg *)return_buf; 2326 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4); 2327 memcpy(&ret_msg->data, spec->scp_resp_data, 2328 spec->wait_num_data); 2329 *bytes_returned = (spec->scp_resp_count + 1) * 4; 2330 status = 0; 2331 } else { 2332 status = -EIO; 2333 } 2334 spec->wait_scp = 0; 2335 } 2336 2337 return status; 2338 } 2339 2340 /** 2341 * dspio_scp - Prepare and send the SCP message to DSP 2342 * @codec: the HDA codec 2343 * @mod_id: ID of the DSP module to send the command 2344 * @src_id: ID of the source 2345 * @req: ID of request to send to the DSP module 2346 * @dir: SET or GET 2347 * @data: pointer to the data to send with the request, request specific 2348 * @len: length of the data, in bytes 2349 * @reply: point to the buffer to hold data returned for a reply 2350 * @reply_len: length of the reply buffer returned from GET 2351 * 2352 * Returns zero or a negative error code. 2353 */ 2354 static int dspio_scp(struct hda_codec *codec, 2355 int mod_id, int src_id, int req, int dir, const void *data, 2356 unsigned int len, void *reply, unsigned int *reply_len) 2357 { 2358 int status = 0; 2359 struct scp_msg scp_send, scp_reply; 2360 unsigned int ret_bytes, send_size, ret_size; 2361 unsigned int send_get_flag, reply_resp_flag, reply_error_flag; 2362 unsigned int reply_data_size; 2363 2364 memset(&scp_send, 0, sizeof(scp_send)); 2365 memset(&scp_reply, 0, sizeof(scp_reply)); 2366 2367 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS)) 2368 return -EINVAL; 2369 2370 if (dir == SCP_GET && reply == NULL) { 2371 codec_dbg(codec, "dspio_scp get but has no buffer\n"); 2372 return -EINVAL; 2373 } 2374 2375 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) { 2376 codec_dbg(codec, "dspio_scp bad resp buf len parms\n"); 2377 return -EINVAL; 2378 } 2379 2380 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req, 2381 0, 0, 0, len/sizeof(unsigned int)); 2382 if (data != NULL && len > 0) { 2383 len = min((unsigned int)(sizeof(scp_send.data)), len); 2384 memcpy(scp_send.data, data, len); 2385 } 2386 2387 ret_bytes = 0; 2388 send_size = sizeof(unsigned int) + len; 2389 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send, 2390 send_size, (unsigned char *)&scp_reply, 2391 sizeof(scp_reply), &ret_bytes); 2392 2393 if (status < 0) { 2394 codec_dbg(codec, "dspio_scp: send scp msg failed\n"); 2395 return status; 2396 } 2397 2398 /* extract send and reply headers members */ 2399 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag, 2400 NULL, NULL, NULL, NULL, NULL); 2401 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL, 2402 &reply_resp_flag, &reply_error_flag, 2403 &reply_data_size); 2404 2405 if (!send_get_flag) 2406 return 0; 2407 2408 if (reply_resp_flag && !reply_error_flag) { 2409 ret_size = (ret_bytes - sizeof(scp_reply.hdr)) 2410 / sizeof(unsigned int); 2411 2412 if (*reply_len < ret_size*sizeof(unsigned int)) { 2413 codec_dbg(codec, "reply too long for buf\n"); 2414 return -EINVAL; 2415 } else if (ret_size != reply_data_size) { 2416 codec_dbg(codec, "RetLen and HdrLen .NE.\n"); 2417 return -EINVAL; 2418 } else if (!reply) { 2419 codec_dbg(codec, "NULL reply\n"); 2420 return -EINVAL; 2421 } else { 2422 *reply_len = ret_size*sizeof(unsigned int); 2423 memcpy(reply, scp_reply.data, *reply_len); 2424 } 2425 } else { 2426 codec_dbg(codec, "reply ill-formed or errflag set\n"); 2427 return -EIO; 2428 } 2429 2430 return status; 2431 } 2432 2433 /* 2434 * Set DSP parameters 2435 */ 2436 static int dspio_set_param(struct hda_codec *codec, int mod_id, 2437 int src_id, int req, const void *data, unsigned int len) 2438 { 2439 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL, 2440 NULL); 2441 } 2442 2443 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id, 2444 int req, const unsigned int data) 2445 { 2446 return dspio_set_param(codec, mod_id, 0x20, req, &data, 2447 sizeof(unsigned int)); 2448 } 2449 2450 /* 2451 * Allocate a DSP DMA channel via an SCP message 2452 */ 2453 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan) 2454 { 2455 int status = 0; 2456 unsigned int size = sizeof(dma_chan); 2457 2458 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n"); 2459 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2460 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0, 2461 dma_chan, &size); 2462 2463 if (status < 0) { 2464 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n"); 2465 return status; 2466 } 2467 2468 if ((*dma_chan + 1) == 0) { 2469 codec_dbg(codec, "no free dma channels to allocate\n"); 2470 return -EBUSY; 2471 } 2472 2473 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan); 2474 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n"); 2475 2476 return status; 2477 } 2478 2479 /* 2480 * Free a DSP DMA via an SCP message 2481 */ 2482 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan) 2483 { 2484 int status = 0; 2485 unsigned int dummy = 0; 2486 2487 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n"); 2488 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan); 2489 2490 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2491 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan, 2492 sizeof(dma_chan), NULL, &dummy); 2493 2494 if (status < 0) { 2495 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n"); 2496 return status; 2497 } 2498 2499 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n"); 2500 2501 return status; 2502 } 2503 2504 /* 2505 * (Re)start the DSP 2506 */ 2507 static int dsp_set_run_state(struct hda_codec *codec) 2508 { 2509 unsigned int dbg_ctrl_reg; 2510 unsigned int halt_state; 2511 int err; 2512 2513 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg); 2514 if (err < 0) 2515 return err; 2516 2517 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >> 2518 DSP_DBGCNTL_STATE_LOBIT; 2519 2520 if (halt_state != 0) { 2521 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) & 2522 DSP_DBGCNTL_SS_MASK); 2523 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2524 dbg_ctrl_reg); 2525 if (err < 0) 2526 return err; 2527 2528 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) & 2529 DSP_DBGCNTL_EXEC_MASK; 2530 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2531 dbg_ctrl_reg); 2532 if (err < 0) 2533 return err; 2534 } 2535 2536 return 0; 2537 } 2538 2539 /* 2540 * Reset the DSP 2541 */ 2542 static int dsp_reset(struct hda_codec *codec) 2543 { 2544 unsigned int res; 2545 int retry = 20; 2546 2547 codec_dbg(codec, "dsp_reset\n"); 2548 do { 2549 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0); 2550 retry--; 2551 } while (res == -EIO && retry); 2552 2553 if (!retry) { 2554 codec_dbg(codec, "dsp_reset timeout\n"); 2555 return -EIO; 2556 } 2557 2558 return 0; 2559 } 2560 2561 /* 2562 * Convert chip address to DSP address 2563 */ 2564 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx, 2565 bool *code, bool *yram) 2566 { 2567 *code = *yram = false; 2568 2569 if (UC_RANGE(chip_addx, 1)) { 2570 *code = true; 2571 return UC_OFF(chip_addx); 2572 } else if (X_RANGE_ALL(chip_addx, 1)) { 2573 return X_OFF(chip_addx); 2574 } else if (Y_RANGE_ALL(chip_addx, 1)) { 2575 *yram = true; 2576 return Y_OFF(chip_addx); 2577 } 2578 2579 return INVALID_CHIP_ADDRESS; 2580 } 2581 2582 /* 2583 * Check if the DSP DMA is active 2584 */ 2585 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan) 2586 { 2587 unsigned int dma_chnlstart_reg; 2588 2589 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg); 2590 2591 return ((dma_chnlstart_reg & (1 << 2592 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0); 2593 } 2594 2595 static int dsp_dma_setup_common(struct hda_codec *codec, 2596 unsigned int chip_addx, 2597 unsigned int dma_chan, 2598 unsigned int port_map_mask, 2599 bool ovly) 2600 { 2601 int status = 0; 2602 unsigned int chnl_prop; 2603 unsigned int dsp_addx; 2604 unsigned int active; 2605 bool code, yram; 2606 2607 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n"); 2608 2609 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) { 2610 codec_dbg(codec, "dma chan num invalid\n"); 2611 return -EINVAL; 2612 } 2613 2614 if (dsp_is_dma_active(codec, dma_chan)) { 2615 codec_dbg(codec, "dma already active\n"); 2616 return -EBUSY; 2617 } 2618 2619 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2620 2621 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2622 codec_dbg(codec, "invalid chip addr\n"); 2623 return -ENXIO; 2624 } 2625 2626 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK; 2627 active = 0; 2628 2629 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n"); 2630 2631 if (ovly) { 2632 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET, 2633 &chnl_prop); 2634 2635 if (status < 0) { 2636 codec_dbg(codec, "read CHNLPROP Reg fail\n"); 2637 return status; 2638 } 2639 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n"); 2640 } 2641 2642 if (!code) 2643 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2644 else 2645 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2646 2647 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan)); 2648 2649 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop); 2650 if (status < 0) { 2651 codec_dbg(codec, "write CHNLPROP Reg fail\n"); 2652 return status; 2653 } 2654 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n"); 2655 2656 if (ovly) { 2657 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET, 2658 &active); 2659 2660 if (status < 0) { 2661 codec_dbg(codec, "read ACTIVE Reg fail\n"); 2662 return status; 2663 } 2664 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n"); 2665 } 2666 2667 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) & 2668 DSPDMAC_ACTIVE_AAR_MASK; 2669 2670 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active); 2671 if (status < 0) { 2672 codec_dbg(codec, "write ACTIVE Reg fail\n"); 2673 return status; 2674 } 2675 2676 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n"); 2677 2678 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan), 2679 port_map_mask); 2680 if (status < 0) { 2681 codec_dbg(codec, "write AUDCHSEL Reg fail\n"); 2682 return status; 2683 } 2684 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n"); 2685 2686 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan), 2687 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK); 2688 if (status < 0) { 2689 codec_dbg(codec, "write IRQCNT Reg fail\n"); 2690 return status; 2691 } 2692 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n"); 2693 2694 codec_dbg(codec, 2695 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, " 2696 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n", 2697 chip_addx, dsp_addx, dma_chan, 2698 port_map_mask, chnl_prop, active); 2699 2700 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n"); 2701 2702 return 0; 2703 } 2704 2705 /* 2706 * Setup the DSP DMA per-transfer-specific registers 2707 */ 2708 static int dsp_dma_setup(struct hda_codec *codec, 2709 unsigned int chip_addx, 2710 unsigned int count, 2711 unsigned int dma_chan) 2712 { 2713 int status = 0; 2714 bool code, yram; 2715 unsigned int dsp_addx; 2716 unsigned int addr_field; 2717 unsigned int incr_field; 2718 unsigned int base_cnt; 2719 unsigned int cur_cnt; 2720 unsigned int dma_cfg = 0; 2721 unsigned int adr_ofs = 0; 2722 unsigned int xfr_cnt = 0; 2723 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT - 2724 DSPDMAC_XFRCNT_BCNT_LOBIT + 1); 2725 2726 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n"); 2727 2728 if (count > max_dma_count) { 2729 codec_dbg(codec, "count too big\n"); 2730 return -EINVAL; 2731 } 2732 2733 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2734 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2735 codec_dbg(codec, "invalid chip addr\n"); 2736 return -ENXIO; 2737 } 2738 2739 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n"); 2740 2741 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT; 2742 incr_field = 0; 2743 2744 if (!code) { 2745 addr_field <<= 1; 2746 if (yram) 2747 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT); 2748 2749 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT); 2750 } 2751 2752 dma_cfg = addr_field + incr_field; 2753 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan), 2754 dma_cfg); 2755 if (status < 0) { 2756 codec_dbg(codec, "write DMACFG Reg fail\n"); 2757 return status; 2758 } 2759 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n"); 2760 2761 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT + 2762 (code ? 0 : 1)); 2763 2764 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan), 2765 adr_ofs); 2766 if (status < 0) { 2767 codec_dbg(codec, "write DSPADROFS Reg fail\n"); 2768 return status; 2769 } 2770 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n"); 2771 2772 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT; 2773 2774 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT; 2775 2776 xfr_cnt = base_cnt | cur_cnt; 2777 2778 status = chipio_write(codec, 2779 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt); 2780 if (status < 0) { 2781 codec_dbg(codec, "write XFRCNT Reg fail\n"); 2782 return status; 2783 } 2784 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n"); 2785 2786 codec_dbg(codec, 2787 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, " 2788 "ADROFS=0x%x, XFRCNT=0x%x\n", 2789 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt); 2790 2791 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n"); 2792 2793 return 0; 2794 } 2795 2796 /* 2797 * Start the DSP DMA 2798 */ 2799 static int dsp_dma_start(struct hda_codec *codec, 2800 unsigned int dma_chan, bool ovly) 2801 { 2802 unsigned int reg = 0; 2803 int status = 0; 2804 2805 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n"); 2806 2807 if (ovly) { 2808 status = chipio_read(codec, 2809 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2810 2811 if (status < 0) { 2812 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2813 return status; 2814 } 2815 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n"); 2816 2817 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2818 DSPDMAC_CHNLSTART_DIS_MASK); 2819 } 2820 2821 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2822 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT))); 2823 if (status < 0) { 2824 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2825 return status; 2826 } 2827 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n"); 2828 2829 return status; 2830 } 2831 2832 /* 2833 * Stop the DSP DMA 2834 */ 2835 static int dsp_dma_stop(struct hda_codec *codec, 2836 unsigned int dma_chan, bool ovly) 2837 { 2838 unsigned int reg = 0; 2839 int status = 0; 2840 2841 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n"); 2842 2843 if (ovly) { 2844 status = chipio_read(codec, 2845 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2846 2847 if (status < 0) { 2848 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2849 return status; 2850 } 2851 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n"); 2852 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2853 DSPDMAC_CHNLSTART_DIS_MASK); 2854 } 2855 2856 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2857 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT))); 2858 if (status < 0) { 2859 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2860 return status; 2861 } 2862 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n"); 2863 2864 return status; 2865 } 2866 2867 /** 2868 * dsp_allocate_router_ports - Allocate router ports 2869 * 2870 * @codec: the HDA codec 2871 * @num_chans: number of channels in the stream 2872 * @ports_per_channel: number of ports per channel 2873 * @start_device: start device 2874 * @port_map: pointer to the port list to hold the allocated ports 2875 * 2876 * Returns zero or a negative error code. 2877 */ 2878 static int dsp_allocate_router_ports(struct hda_codec *codec, 2879 unsigned int num_chans, 2880 unsigned int ports_per_channel, 2881 unsigned int start_device, 2882 unsigned int *port_map) 2883 { 2884 int status = 0; 2885 int res; 2886 u8 val; 2887 2888 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2889 if (status < 0) 2890 return status; 2891 2892 val = start_device << 6; 2893 val |= (ports_per_channel - 1) << 4; 2894 val |= num_chans - 1; 2895 2896 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2897 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET, 2898 val); 2899 2900 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2901 VENDOR_CHIPIO_PORT_ALLOC_SET, 2902 MEM_CONNID_DSP); 2903 2904 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2905 if (status < 0) 2906 return status; 2907 2908 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 2909 VENDOR_CHIPIO_PORT_ALLOC_GET, 0); 2910 2911 *port_map = res; 2912 2913 return (res < 0) ? res : 0; 2914 } 2915 2916 /* 2917 * Free router ports 2918 */ 2919 static int dsp_free_router_ports(struct hda_codec *codec) 2920 { 2921 int status = 0; 2922 2923 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2924 if (status < 0) 2925 return status; 2926 2927 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2928 VENDOR_CHIPIO_PORT_FREE_SET, 2929 MEM_CONNID_DSP); 2930 2931 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2932 2933 return status; 2934 } 2935 2936 /* 2937 * Allocate DSP ports for the download stream 2938 */ 2939 static int dsp_allocate_ports(struct hda_codec *codec, 2940 unsigned int num_chans, 2941 unsigned int rate_multi, unsigned int *port_map) 2942 { 2943 int status; 2944 2945 codec_dbg(codec, " dsp_allocate_ports() -- begin\n"); 2946 2947 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2948 codec_dbg(codec, "bad rate multiple\n"); 2949 return -EINVAL; 2950 } 2951 2952 status = dsp_allocate_router_ports(codec, num_chans, 2953 rate_multi, 0, port_map); 2954 2955 codec_dbg(codec, " dsp_allocate_ports() -- complete\n"); 2956 2957 return status; 2958 } 2959 2960 static int dsp_allocate_ports_format(struct hda_codec *codec, 2961 const unsigned short fmt, 2962 unsigned int *port_map) 2963 { 2964 int status; 2965 unsigned int num_chans; 2966 2967 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1; 2968 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1; 2969 unsigned int rate_multi = sample_rate_mul / sample_rate_div; 2970 2971 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2972 codec_dbg(codec, "bad rate multiple\n"); 2973 return -EINVAL; 2974 } 2975 2976 num_chans = get_hdafmt_chs(fmt) + 1; 2977 2978 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map); 2979 2980 return status; 2981 } 2982 2983 /* 2984 * free DSP ports 2985 */ 2986 static int dsp_free_ports(struct hda_codec *codec) 2987 { 2988 int status; 2989 2990 codec_dbg(codec, " dsp_free_ports() -- begin\n"); 2991 2992 status = dsp_free_router_ports(codec); 2993 if (status < 0) { 2994 codec_dbg(codec, "free router ports fail\n"); 2995 return status; 2996 } 2997 codec_dbg(codec, " dsp_free_ports() -- complete\n"); 2998 2999 return status; 3000 } 3001 3002 /* 3003 * HDA DMA engine stuffs for DSP code download 3004 */ 3005 struct dma_engine { 3006 struct hda_codec *codec; 3007 unsigned short m_converter_format; 3008 struct snd_dma_buffer *dmab; 3009 unsigned int buf_size; 3010 }; 3011 3012 3013 enum dma_state { 3014 DMA_STATE_STOP = 0, 3015 DMA_STATE_RUN = 1 3016 }; 3017 3018 static int dma_convert_to_hda_format(struct hda_codec *codec, 3019 unsigned int sample_rate, 3020 unsigned short channels, 3021 unsigned short *hda_format) 3022 { 3023 unsigned int format_val; 3024 3025 format_val = snd_hdac_calc_stream_format(sample_rate, 3026 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0); 3027 3028 if (hda_format) 3029 *hda_format = (unsigned short)format_val; 3030 3031 return 0; 3032 } 3033 3034 /* 3035 * Reset DMA for DSP download 3036 */ 3037 static int dma_reset(struct dma_engine *dma) 3038 { 3039 struct hda_codec *codec = dma->codec; 3040 struct ca0132_spec *spec = codec->spec; 3041 int status; 3042 3043 if (dma->dmab->area) 3044 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab); 3045 3046 status = snd_hda_codec_load_dsp_prepare(codec, 3047 dma->m_converter_format, 3048 dma->buf_size, 3049 dma->dmab); 3050 if (status < 0) 3051 return status; 3052 spec->dsp_stream_id = status; 3053 return 0; 3054 } 3055 3056 static int dma_set_state(struct dma_engine *dma, enum dma_state state) 3057 { 3058 bool cmd; 3059 3060 switch (state) { 3061 case DMA_STATE_STOP: 3062 cmd = false; 3063 break; 3064 case DMA_STATE_RUN: 3065 cmd = true; 3066 break; 3067 default: 3068 return 0; 3069 } 3070 3071 snd_hda_codec_load_dsp_trigger(dma->codec, cmd); 3072 return 0; 3073 } 3074 3075 static unsigned int dma_get_buffer_size(struct dma_engine *dma) 3076 { 3077 return dma->dmab->bytes; 3078 } 3079 3080 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma) 3081 { 3082 return dma->dmab->area; 3083 } 3084 3085 static int dma_xfer(struct dma_engine *dma, 3086 const unsigned int *data, 3087 unsigned int count) 3088 { 3089 memcpy(dma->dmab->area, data, count); 3090 return 0; 3091 } 3092 3093 static void dma_get_converter_format( 3094 struct dma_engine *dma, 3095 unsigned short *format) 3096 { 3097 if (format) 3098 *format = dma->m_converter_format; 3099 } 3100 3101 static unsigned int dma_get_stream_id(struct dma_engine *dma) 3102 { 3103 struct ca0132_spec *spec = dma->codec->spec; 3104 3105 return spec->dsp_stream_id; 3106 } 3107 3108 struct dsp_image_seg { 3109 u32 magic; 3110 u32 chip_addr; 3111 u32 count; 3112 u32 data[]; 3113 }; 3114 3115 static const u32 g_magic_value = 0x4c46584d; 3116 static const u32 g_chip_addr_magic_value = 0xFFFFFF01; 3117 3118 static bool is_valid(const struct dsp_image_seg *p) 3119 { 3120 return p->magic == g_magic_value; 3121 } 3122 3123 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p) 3124 { 3125 return g_chip_addr_magic_value == p->chip_addr; 3126 } 3127 3128 static bool is_last(const struct dsp_image_seg *p) 3129 { 3130 return p->count == 0; 3131 } 3132 3133 static size_t dsp_sizeof(const struct dsp_image_seg *p) 3134 { 3135 return struct_size(p, data, p->count); 3136 } 3137 3138 static const struct dsp_image_seg *get_next_seg_ptr( 3139 const struct dsp_image_seg *p) 3140 { 3141 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p)); 3142 } 3143 3144 /* 3145 * CA0132 chip DSP transfer stuffs. For DSP download. 3146 */ 3147 #define INVALID_DMA_CHANNEL (~0U) 3148 3149 /* 3150 * Program a list of address/data pairs via the ChipIO widget. 3151 * The segment data is in the format of successive pairs of words. 3152 * These are repeated as indicated by the segment's count field. 3153 */ 3154 static int dspxfr_hci_write(struct hda_codec *codec, 3155 const struct dsp_image_seg *fls) 3156 { 3157 int status; 3158 const u32 *data; 3159 unsigned int count; 3160 3161 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) { 3162 codec_dbg(codec, "hci_write invalid params\n"); 3163 return -EINVAL; 3164 } 3165 3166 count = fls->count; 3167 data = (u32 *)(fls->data); 3168 while (count >= 2) { 3169 status = chipio_write(codec, data[0], data[1]); 3170 if (status < 0) { 3171 codec_dbg(codec, "hci_write chipio failed\n"); 3172 return status; 3173 } 3174 count -= 2; 3175 data += 2; 3176 } 3177 return 0; 3178 } 3179 3180 /** 3181 * dspxfr_one_seg - Write a block of data into DSP code or data RAM using pre-allocated DMA engine. 3182 * 3183 * @codec: the HDA codec 3184 * @fls: pointer to a fast load image 3185 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3186 * no relocation 3187 * @dma_engine: pointer to DMA engine to be used for DSP download 3188 * @dma_chan: The number of DMA channels used for DSP download 3189 * @port_map_mask: port mapping 3190 * @ovly: TRUE if overlay format is required 3191 * 3192 * Returns zero or a negative error code. 3193 */ 3194 static int dspxfr_one_seg(struct hda_codec *codec, 3195 const struct dsp_image_seg *fls, 3196 unsigned int reloc, 3197 struct dma_engine *dma_engine, 3198 unsigned int dma_chan, 3199 unsigned int port_map_mask, 3200 bool ovly) 3201 { 3202 int status = 0; 3203 bool comm_dma_setup_done = false; 3204 const unsigned int *data; 3205 unsigned int chip_addx; 3206 unsigned int words_to_write; 3207 unsigned int buffer_size_words; 3208 unsigned char *buffer_addx; 3209 unsigned short hda_format; 3210 unsigned int sample_rate_div; 3211 unsigned int sample_rate_mul; 3212 unsigned int num_chans; 3213 unsigned int hda_frame_size_words; 3214 unsigned int remainder_words; 3215 const u32 *data_remainder; 3216 u32 chip_addx_remainder; 3217 unsigned int run_size_words; 3218 const struct dsp_image_seg *hci_write = NULL; 3219 unsigned long timeout; 3220 bool dma_active; 3221 3222 if (fls == NULL) 3223 return -EINVAL; 3224 if (is_hci_prog_list_seg(fls)) { 3225 hci_write = fls; 3226 fls = get_next_seg_ptr(fls); 3227 } 3228 3229 if (hci_write && (!fls || is_last(fls))) { 3230 codec_dbg(codec, "hci_write\n"); 3231 return dspxfr_hci_write(codec, hci_write); 3232 } 3233 3234 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) { 3235 codec_dbg(codec, "Invalid Params\n"); 3236 return -EINVAL; 3237 } 3238 3239 data = fls->data; 3240 chip_addx = fls->chip_addr; 3241 words_to_write = fls->count; 3242 3243 if (!words_to_write) 3244 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0; 3245 if (reloc) 3246 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2); 3247 3248 if (!UC_RANGE(chip_addx, words_to_write) && 3249 !X_RANGE_ALL(chip_addx, words_to_write) && 3250 !Y_RANGE_ALL(chip_addx, words_to_write)) { 3251 codec_dbg(codec, "Invalid chip_addx Params\n"); 3252 return -EINVAL; 3253 } 3254 3255 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) / 3256 sizeof(u32); 3257 3258 buffer_addx = dma_get_buffer_addr(dma_engine); 3259 3260 if (buffer_addx == NULL) { 3261 codec_dbg(codec, "dma_engine buffer NULL\n"); 3262 return -EINVAL; 3263 } 3264 3265 dma_get_converter_format(dma_engine, &hda_format); 3266 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1; 3267 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1; 3268 num_chans = get_hdafmt_chs(hda_format) + 1; 3269 3270 hda_frame_size_words = ((sample_rate_div == 0) ? 0 : 3271 (num_chans * sample_rate_mul / sample_rate_div)); 3272 3273 if (hda_frame_size_words == 0) { 3274 codec_dbg(codec, "frmsz zero\n"); 3275 return -EINVAL; 3276 } 3277 3278 buffer_size_words = min(buffer_size_words, 3279 (unsigned int)(UC_RANGE(chip_addx, 1) ? 3280 65536 : 32768)); 3281 buffer_size_words -= buffer_size_words % hda_frame_size_words; 3282 codec_dbg(codec, 3283 "chpadr=0x%08x frmsz=%u nchan=%u " 3284 "rate_mul=%u div=%u bufsz=%u\n", 3285 chip_addx, hda_frame_size_words, num_chans, 3286 sample_rate_mul, sample_rate_div, buffer_size_words); 3287 3288 if (buffer_size_words < hda_frame_size_words) { 3289 codec_dbg(codec, "dspxfr_one_seg:failed\n"); 3290 return -EINVAL; 3291 } 3292 3293 remainder_words = words_to_write % hda_frame_size_words; 3294 data_remainder = data; 3295 chip_addx_remainder = chip_addx; 3296 3297 data += remainder_words; 3298 chip_addx += remainder_words*sizeof(u32); 3299 words_to_write -= remainder_words; 3300 3301 while (words_to_write != 0) { 3302 run_size_words = min(buffer_size_words, words_to_write); 3303 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n", 3304 words_to_write, run_size_words, remainder_words); 3305 dma_xfer(dma_engine, data, run_size_words*sizeof(u32)); 3306 if (!comm_dma_setup_done) { 3307 status = dsp_dma_stop(codec, dma_chan, ovly); 3308 if (status < 0) 3309 return status; 3310 status = dsp_dma_setup_common(codec, chip_addx, 3311 dma_chan, port_map_mask, ovly); 3312 if (status < 0) 3313 return status; 3314 comm_dma_setup_done = true; 3315 } 3316 3317 status = dsp_dma_setup(codec, chip_addx, 3318 run_size_words, dma_chan); 3319 if (status < 0) 3320 return status; 3321 status = dsp_dma_start(codec, dma_chan, ovly); 3322 if (status < 0) 3323 return status; 3324 if (!dsp_is_dma_active(codec, dma_chan)) { 3325 codec_dbg(codec, "dspxfr:DMA did not start\n"); 3326 return -EIO; 3327 } 3328 status = dma_set_state(dma_engine, DMA_STATE_RUN); 3329 if (status < 0) 3330 return status; 3331 if (remainder_words != 0) { 3332 status = chipio_write_multiple(codec, 3333 chip_addx_remainder, 3334 data_remainder, 3335 remainder_words); 3336 if (status < 0) 3337 return status; 3338 remainder_words = 0; 3339 } 3340 if (hci_write) { 3341 status = dspxfr_hci_write(codec, hci_write); 3342 if (status < 0) 3343 return status; 3344 hci_write = NULL; 3345 } 3346 3347 timeout = jiffies + msecs_to_jiffies(2000); 3348 do { 3349 dma_active = dsp_is_dma_active(codec, dma_chan); 3350 if (!dma_active) 3351 break; 3352 msleep(20); 3353 } while (time_before(jiffies, timeout)); 3354 if (dma_active) 3355 break; 3356 3357 codec_dbg(codec, "+++++ DMA complete\n"); 3358 dma_set_state(dma_engine, DMA_STATE_STOP); 3359 status = dma_reset(dma_engine); 3360 3361 if (status < 0) 3362 return status; 3363 3364 data += run_size_words; 3365 chip_addx += run_size_words*sizeof(u32); 3366 words_to_write -= run_size_words; 3367 } 3368 3369 if (remainder_words != 0) { 3370 status = chipio_write_multiple(codec, chip_addx_remainder, 3371 data_remainder, remainder_words); 3372 } 3373 3374 return status; 3375 } 3376 3377 /** 3378 * dspxfr_image - Write the entire DSP image of a DSP code/data overlay to DSP memories 3379 * 3380 * @codec: the HDA codec 3381 * @fls_data: pointer to a fast load image 3382 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3383 * no relocation 3384 * @sample_rate: sampling rate of the stream used for DSP download 3385 * @channels: channels of the stream used for DSP download 3386 * @ovly: TRUE if overlay format is required 3387 * 3388 * Returns zero or a negative error code. 3389 */ 3390 static int dspxfr_image(struct hda_codec *codec, 3391 const struct dsp_image_seg *fls_data, 3392 unsigned int reloc, 3393 unsigned int sample_rate, 3394 unsigned short channels, 3395 bool ovly) 3396 { 3397 struct ca0132_spec *spec = codec->spec; 3398 int status; 3399 unsigned short hda_format = 0; 3400 unsigned int response; 3401 unsigned char stream_id = 0; 3402 struct dma_engine *dma_engine; 3403 unsigned int dma_chan; 3404 unsigned int port_map_mask; 3405 3406 if (fls_data == NULL) 3407 return -EINVAL; 3408 3409 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL); 3410 if (!dma_engine) 3411 return -ENOMEM; 3412 3413 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL); 3414 if (!dma_engine->dmab) { 3415 kfree(dma_engine); 3416 return -ENOMEM; 3417 } 3418 3419 dma_engine->codec = codec; 3420 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format); 3421 dma_engine->m_converter_format = hda_format; 3422 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY : 3423 DSP_DMA_WRITE_BUFLEN_INIT) * 2; 3424 3425 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0; 3426 3427 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL, 3428 hda_format, &response); 3429 3430 if (status < 0) { 3431 codec_dbg(codec, "set converter format fail\n"); 3432 goto exit; 3433 } 3434 3435 status = snd_hda_codec_load_dsp_prepare(codec, 3436 dma_engine->m_converter_format, 3437 dma_engine->buf_size, 3438 dma_engine->dmab); 3439 if (status < 0) 3440 goto exit; 3441 spec->dsp_stream_id = status; 3442 3443 if (ovly) { 3444 status = dspio_alloc_dma_chan(codec, &dma_chan); 3445 if (status < 0) { 3446 codec_dbg(codec, "alloc dmachan fail\n"); 3447 dma_chan = INVALID_DMA_CHANNEL; 3448 goto exit; 3449 } 3450 } 3451 3452 port_map_mask = 0; 3453 status = dsp_allocate_ports_format(codec, hda_format, 3454 &port_map_mask); 3455 if (status < 0) { 3456 codec_dbg(codec, "alloc ports fail\n"); 3457 goto exit; 3458 } 3459 3460 stream_id = dma_get_stream_id(dma_engine); 3461 status = codec_set_converter_stream_channel(codec, 3462 WIDGET_CHIP_CTRL, stream_id, 0, &response); 3463 if (status < 0) { 3464 codec_dbg(codec, "set stream chan fail\n"); 3465 goto exit; 3466 } 3467 3468 while ((fls_data != NULL) && !is_last(fls_data)) { 3469 if (!is_valid(fls_data)) { 3470 codec_dbg(codec, "FLS check fail\n"); 3471 status = -EINVAL; 3472 goto exit; 3473 } 3474 status = dspxfr_one_seg(codec, fls_data, reloc, 3475 dma_engine, dma_chan, 3476 port_map_mask, ovly); 3477 if (status < 0) 3478 break; 3479 3480 if (is_hci_prog_list_seg(fls_data)) 3481 fls_data = get_next_seg_ptr(fls_data); 3482 3483 if ((fls_data != NULL) && !is_last(fls_data)) 3484 fls_data = get_next_seg_ptr(fls_data); 3485 } 3486 3487 if (port_map_mask != 0) 3488 status = dsp_free_ports(codec); 3489 3490 if (status < 0) 3491 goto exit; 3492 3493 status = codec_set_converter_stream_channel(codec, 3494 WIDGET_CHIP_CTRL, 0, 0, &response); 3495 3496 exit: 3497 if (ovly && (dma_chan != INVALID_DMA_CHANNEL)) 3498 dspio_free_dma_chan(codec, dma_chan); 3499 3500 if (dma_engine->dmab->area) 3501 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab); 3502 kfree(dma_engine->dmab); 3503 kfree(dma_engine); 3504 3505 return status; 3506 } 3507 3508 /* 3509 * CA0132 DSP download stuffs. 3510 */ 3511 static void dspload_post_setup(struct hda_codec *codec) 3512 { 3513 struct ca0132_spec *spec = codec->spec; 3514 codec_dbg(codec, "---- dspload_post_setup ------\n"); 3515 if (!ca0132_use_alt_functions(spec)) { 3516 /*set DSP speaker to 2.0 configuration*/ 3517 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080); 3518 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000); 3519 3520 /*update write pointer*/ 3521 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002); 3522 } 3523 } 3524 3525 /** 3526 * dspload_image - Download DSP from a DSP Image Fast Load structure. 3527 * 3528 * @codec: the HDA codec 3529 * @fls: pointer to a fast load image 3530 * @ovly: TRUE if overlay format is required 3531 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3532 * no relocation 3533 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE 3534 * @router_chans: number of audio router channels to be allocated (0 means use 3535 * internal defaults; max is 32) 3536 * 3537 * Download DSP from a DSP Image Fast Load structure. This structure is a 3538 * linear, non-constant sized element array of structures, each of which 3539 * contain the count of the data to be loaded, the data itself, and the 3540 * corresponding starting chip address of the starting data location. 3541 * Returns zero or a negative error code. 3542 */ 3543 static int dspload_image(struct hda_codec *codec, 3544 const struct dsp_image_seg *fls, 3545 bool ovly, 3546 unsigned int reloc, 3547 bool autostart, 3548 int router_chans) 3549 { 3550 int status = 0; 3551 unsigned int sample_rate; 3552 unsigned short channels; 3553 3554 codec_dbg(codec, "---- dspload_image begin ------\n"); 3555 if (router_chans == 0) { 3556 if (!ovly) 3557 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS; 3558 else 3559 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS; 3560 } 3561 3562 sample_rate = 48000; 3563 channels = (unsigned short)router_chans; 3564 3565 while (channels > 16) { 3566 sample_rate *= 2; 3567 channels /= 2; 3568 } 3569 3570 do { 3571 codec_dbg(codec, "Ready to program DMA\n"); 3572 if (!ovly) 3573 status = dsp_reset(codec); 3574 3575 if (status < 0) 3576 break; 3577 3578 codec_dbg(codec, "dsp_reset() complete\n"); 3579 status = dspxfr_image(codec, fls, reloc, sample_rate, channels, 3580 ovly); 3581 3582 if (status < 0) 3583 break; 3584 3585 codec_dbg(codec, "dspxfr_image() complete\n"); 3586 if (autostart && !ovly) { 3587 dspload_post_setup(codec); 3588 status = dsp_set_run_state(codec); 3589 } 3590 3591 codec_dbg(codec, "LOAD FINISHED\n"); 3592 } while (0); 3593 3594 return status; 3595 } 3596 3597 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 3598 static bool dspload_is_loaded(struct hda_codec *codec) 3599 { 3600 unsigned int data = 0; 3601 int status = 0; 3602 3603 status = chipio_read(codec, 0x40004, &data); 3604 if ((status < 0) || (data != 1)) 3605 return false; 3606 3607 return true; 3608 } 3609 #else 3610 #define dspload_is_loaded(codec) false 3611 #endif 3612 3613 static bool dspload_wait_loaded(struct hda_codec *codec) 3614 { 3615 unsigned long timeout = jiffies + msecs_to_jiffies(2000); 3616 3617 do { 3618 if (dspload_is_loaded(codec)) { 3619 codec_info(codec, "ca0132 DSP downloaded and running\n"); 3620 return true; 3621 } 3622 msleep(20); 3623 } while (time_before(jiffies, timeout)); 3624 3625 codec_err(codec, "ca0132 failed to download DSP\n"); 3626 return false; 3627 } 3628 3629 /* 3630 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e 3631 * based cards, and has a second mmio region, region2, that's used for special 3632 * commands. 3633 */ 3634 3635 /* 3636 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5) 3637 * the mmio address 0x320 is used to set GPIO pins. The format for the data 3638 * The first eight bits are just the number of the pin. So far, I've only seen 3639 * this number go to 7. 3640 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value 3641 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and 3642 * then off to send that bit. 3643 */ 3644 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin, 3645 bool enable) 3646 { 3647 struct ca0132_spec *spec = codec->spec; 3648 unsigned short gpio_data; 3649 3650 gpio_data = gpio_pin & 0xF; 3651 gpio_data |= ((enable << 8) & 0x100); 3652 3653 writew(gpio_data, spec->mem_base + 0x320); 3654 } 3655 3656 /* 3657 * Special pci region2 commands that are only used by the AE-5. They follow 3658 * a set format, and require reads at certain points to seemingly 'clear' 3659 * the response data. My first tests didn't do these reads, and would cause 3660 * the card to get locked up until the memory was read. These commands 3661 * seem to work with three distinct values that I've taken to calling group, 3662 * target-id, and value. 3663 */ 3664 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group, 3665 unsigned int target, unsigned int value) 3666 { 3667 struct ca0132_spec *spec = codec->spec; 3668 unsigned int write_val; 3669 3670 writel(0x0000007e, spec->mem_base + 0x210); 3671 readl(spec->mem_base + 0x210); 3672 writel(0x0000005a, spec->mem_base + 0x210); 3673 readl(spec->mem_base + 0x210); 3674 readl(spec->mem_base + 0x210); 3675 3676 writel(0x00800005, spec->mem_base + 0x20c); 3677 writel(group, spec->mem_base + 0x804); 3678 3679 writel(0x00800005, spec->mem_base + 0x20c); 3680 write_val = (target & 0xff); 3681 write_val |= (value << 8); 3682 3683 3684 writel(write_val, spec->mem_base + 0x204); 3685 /* 3686 * Need delay here or else it goes too fast and works inconsistently. 3687 */ 3688 msleep(20); 3689 3690 readl(spec->mem_base + 0x860); 3691 readl(spec->mem_base + 0x854); 3692 readl(spec->mem_base + 0x840); 3693 3694 writel(0x00800004, spec->mem_base + 0x20c); 3695 writel(0x00000000, spec->mem_base + 0x210); 3696 readl(spec->mem_base + 0x210); 3697 readl(spec->mem_base + 0x210); 3698 } 3699 3700 /* 3701 * This second type of command is used for setting the sound filter type. 3702 */ 3703 static void ca0113_mmio_command_set_type2(struct hda_codec *codec, 3704 unsigned int group, unsigned int target, unsigned int value) 3705 { 3706 struct ca0132_spec *spec = codec->spec; 3707 unsigned int write_val; 3708 3709 writel(0x0000007e, spec->mem_base + 0x210); 3710 readl(spec->mem_base + 0x210); 3711 writel(0x0000005a, spec->mem_base + 0x210); 3712 readl(spec->mem_base + 0x210); 3713 readl(spec->mem_base + 0x210); 3714 3715 writel(0x00800003, spec->mem_base + 0x20c); 3716 writel(group, spec->mem_base + 0x804); 3717 3718 writel(0x00800005, spec->mem_base + 0x20c); 3719 write_val = (target & 0xff); 3720 write_val |= (value << 8); 3721 3722 3723 writel(write_val, spec->mem_base + 0x204); 3724 msleep(20); 3725 readl(spec->mem_base + 0x860); 3726 readl(spec->mem_base + 0x854); 3727 readl(spec->mem_base + 0x840); 3728 3729 writel(0x00800004, spec->mem_base + 0x20c); 3730 writel(0x00000000, spec->mem_base + 0x210); 3731 readl(spec->mem_base + 0x210); 3732 readl(spec->mem_base + 0x210); 3733 } 3734 3735 /* 3736 * Setup GPIO for the other variants of Core3D. 3737 */ 3738 3739 /* 3740 * Sets up the GPIO pins so that they are discoverable. If this isn't done, 3741 * the card shows as having no GPIO pins. 3742 */ 3743 static void ca0132_gpio_init(struct hda_codec *codec) 3744 { 3745 struct ca0132_spec *spec = codec->spec; 3746 3747 switch (ca0132_quirk(spec)) { 3748 case QUIRK_SBZ: 3749 case QUIRK_AE5: 3750 case QUIRK_AE7: 3751 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3752 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 3753 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23); 3754 break; 3755 case QUIRK_R3DI: 3756 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3757 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B); 3758 break; 3759 default: 3760 break; 3761 } 3762 3763 } 3764 3765 /* Sets the GPIO for audio output. */ 3766 static void ca0132_gpio_setup(struct hda_codec *codec) 3767 { 3768 struct ca0132_spec *spec = codec->spec; 3769 3770 switch (ca0132_quirk(spec)) { 3771 case QUIRK_SBZ: 3772 snd_hda_codec_write(codec, 0x01, 0, 3773 AC_VERB_SET_GPIO_DIRECTION, 0x07); 3774 snd_hda_codec_write(codec, 0x01, 0, 3775 AC_VERB_SET_GPIO_MASK, 0x07); 3776 snd_hda_codec_write(codec, 0x01, 0, 3777 AC_VERB_SET_GPIO_DATA, 0x04); 3778 snd_hda_codec_write(codec, 0x01, 0, 3779 AC_VERB_SET_GPIO_DATA, 0x06); 3780 break; 3781 case QUIRK_R3DI: 3782 snd_hda_codec_write(codec, 0x01, 0, 3783 AC_VERB_SET_GPIO_DIRECTION, 0x1E); 3784 snd_hda_codec_write(codec, 0x01, 0, 3785 AC_VERB_SET_GPIO_MASK, 0x1F); 3786 snd_hda_codec_write(codec, 0x01, 0, 3787 AC_VERB_SET_GPIO_DATA, 0x0C); 3788 break; 3789 default: 3790 break; 3791 } 3792 } 3793 3794 /* 3795 * GPIO control functions for the Recon3D integrated. 3796 */ 3797 3798 enum r3di_gpio_bit { 3799 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */ 3800 R3DI_MIC_SELECT_BIT = 1, 3801 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */ 3802 R3DI_OUT_SELECT_BIT = 2, 3803 /* 3804 * I dunno what this actually does, but it stays on until the dsp 3805 * is downloaded. 3806 */ 3807 R3DI_GPIO_DSP_DOWNLOADING = 3, 3808 /* 3809 * Same as above, no clue what it does, but it comes on after the dsp 3810 * is downloaded. 3811 */ 3812 R3DI_GPIO_DSP_DOWNLOADED = 4 3813 }; 3814 3815 enum r3di_mic_select { 3816 /* Set GPIO bit 1 to 0 for rear mic */ 3817 R3DI_REAR_MIC = 0, 3818 /* Set GPIO bit 1 to 1 for front microphone*/ 3819 R3DI_FRONT_MIC = 1 3820 }; 3821 3822 enum r3di_out_select { 3823 /* Set GPIO bit 2 to 0 for headphone */ 3824 R3DI_HEADPHONE_OUT = 0, 3825 /* Set GPIO bit 2 to 1 for speaker */ 3826 R3DI_LINE_OUT = 1 3827 }; 3828 enum r3di_dsp_status { 3829 /* Set GPIO bit 3 to 1 until DSP is downloaded */ 3830 R3DI_DSP_DOWNLOADING = 0, 3831 /* Set GPIO bit 4 to 1 once DSP is downloaded */ 3832 R3DI_DSP_DOWNLOADED = 1 3833 }; 3834 3835 3836 static void r3di_gpio_mic_set(struct hda_codec *codec, 3837 enum r3di_mic_select cur_mic) 3838 { 3839 unsigned int cur_gpio; 3840 3841 /* Get the current GPIO Data setup */ 3842 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3843 3844 switch (cur_mic) { 3845 case R3DI_REAR_MIC: 3846 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT); 3847 break; 3848 case R3DI_FRONT_MIC: 3849 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT); 3850 break; 3851 } 3852 snd_hda_codec_write(codec, codec->core.afg, 0, 3853 AC_VERB_SET_GPIO_DATA, cur_gpio); 3854 } 3855 3856 static void r3di_gpio_dsp_status_set(struct hda_codec *codec, 3857 enum r3di_dsp_status dsp_status) 3858 { 3859 unsigned int cur_gpio; 3860 3861 /* Get the current GPIO Data setup */ 3862 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3863 3864 switch (dsp_status) { 3865 case R3DI_DSP_DOWNLOADING: 3866 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING); 3867 snd_hda_codec_write(codec, codec->core.afg, 0, 3868 AC_VERB_SET_GPIO_DATA, cur_gpio); 3869 break; 3870 case R3DI_DSP_DOWNLOADED: 3871 /* Set DOWNLOADING bit to 0. */ 3872 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING); 3873 3874 snd_hda_codec_write(codec, codec->core.afg, 0, 3875 AC_VERB_SET_GPIO_DATA, cur_gpio); 3876 3877 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED); 3878 break; 3879 } 3880 3881 snd_hda_codec_write(codec, codec->core.afg, 0, 3882 AC_VERB_SET_GPIO_DATA, cur_gpio); 3883 } 3884 3885 /* 3886 * PCM callbacks 3887 */ 3888 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3889 struct hda_codec *codec, 3890 unsigned int stream_tag, 3891 unsigned int format, 3892 struct snd_pcm_substream *substream) 3893 { 3894 struct ca0132_spec *spec = codec->spec; 3895 3896 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format); 3897 3898 return 0; 3899 } 3900 3901 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3902 struct hda_codec *codec, 3903 struct snd_pcm_substream *substream) 3904 { 3905 struct ca0132_spec *spec = codec->spec; 3906 3907 if (spec->dsp_state == DSP_DOWNLOADING) 3908 return 0; 3909 3910 /*If Playback effects are on, allow stream some time to flush 3911 *effects tail*/ 3912 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 3913 msleep(50); 3914 3915 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 3916 3917 return 0; 3918 } 3919 3920 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info, 3921 struct hda_codec *codec, 3922 struct snd_pcm_substream *substream) 3923 { 3924 struct ca0132_spec *spec = codec->spec; 3925 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY; 3926 struct snd_pcm_runtime *runtime = substream->runtime; 3927 3928 if (spec->dsp_state != DSP_DOWNLOADED) 3929 return 0; 3930 3931 /* Add latency if playback enhancement and either effect is enabled. */ 3932 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) { 3933 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) || 3934 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID])) 3935 latency += DSP_PLAY_ENHANCEMENT_LATENCY; 3936 } 3937 3938 /* Applying Speaker EQ adds latency as well. */ 3939 if (spec->cur_out_type == SPEAKER_OUT) 3940 latency += DSP_SPEAKER_OUT_LATENCY; 3941 3942 return (latency * runtime->rate) / 1000; 3943 } 3944 3945 /* 3946 * Digital out 3947 */ 3948 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo, 3949 struct hda_codec *codec, 3950 struct snd_pcm_substream *substream) 3951 { 3952 struct ca0132_spec *spec = codec->spec; 3953 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3954 } 3955 3956 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3957 struct hda_codec *codec, 3958 unsigned int stream_tag, 3959 unsigned int format, 3960 struct snd_pcm_substream *substream) 3961 { 3962 struct ca0132_spec *spec = codec->spec; 3963 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3964 stream_tag, format, substream); 3965 } 3966 3967 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3968 struct hda_codec *codec, 3969 struct snd_pcm_substream *substream) 3970 { 3971 struct ca0132_spec *spec = codec->spec; 3972 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout); 3973 } 3974 3975 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo, 3976 struct hda_codec *codec, 3977 struct snd_pcm_substream *substream) 3978 { 3979 struct ca0132_spec *spec = codec->spec; 3980 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3981 } 3982 3983 /* 3984 * Analog capture 3985 */ 3986 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo, 3987 struct hda_codec *codec, 3988 unsigned int stream_tag, 3989 unsigned int format, 3990 struct snd_pcm_substream *substream) 3991 { 3992 snd_hda_codec_setup_stream(codec, hinfo->nid, 3993 stream_tag, 0, format); 3994 3995 return 0; 3996 } 3997 3998 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo, 3999 struct hda_codec *codec, 4000 struct snd_pcm_substream *substream) 4001 { 4002 struct ca0132_spec *spec = codec->spec; 4003 4004 if (spec->dsp_state == DSP_DOWNLOADING) 4005 return 0; 4006 4007 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 4008 return 0; 4009 } 4010 4011 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info, 4012 struct hda_codec *codec, 4013 struct snd_pcm_substream *substream) 4014 { 4015 struct ca0132_spec *spec = codec->spec; 4016 unsigned int latency = DSP_CAPTURE_INIT_LATENCY; 4017 struct snd_pcm_runtime *runtime = substream->runtime; 4018 4019 if (spec->dsp_state != DSP_DOWNLOADED) 4020 return 0; 4021 4022 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 4023 latency += DSP_CRYSTAL_VOICE_LATENCY; 4024 4025 return (latency * runtime->rate) / 1000; 4026 } 4027 4028 /* 4029 * Controls stuffs. 4030 */ 4031 4032 /* 4033 * Mixer controls helpers. 4034 */ 4035 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \ 4036 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4037 .name = xname, \ 4038 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 4039 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 4040 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 4041 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 4042 .info = ca0132_volume_info, \ 4043 .get = ca0132_volume_get, \ 4044 .put = ca0132_volume_put, \ 4045 .tlv = { .c = ca0132_volume_tlv }, \ 4046 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 4047 4048 /* 4049 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the 4050 * volume put, which is used for setting the DSP volume. This was done because 4051 * the ca0132 functions were taking too much time and causing lag. 4052 */ 4053 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \ 4054 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4055 .name = xname, \ 4056 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 4057 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 4058 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 4059 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 4060 .info = snd_hda_mixer_amp_volume_info, \ 4061 .get = snd_hda_mixer_amp_volume_get, \ 4062 .put = ca0132_alt_volume_put, \ 4063 .tlv = { .c = snd_hda_mixer_amp_tlv }, \ 4064 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 4065 4066 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \ 4067 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4068 .name = xname, \ 4069 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 4070 .info = snd_hda_mixer_amp_switch_info, \ 4071 .get = ca0132_switch_get, \ 4072 .put = ca0132_switch_put, \ 4073 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 4074 4075 /* stereo */ 4076 #define CA0132_CODEC_VOL(xname, nid, dir) \ 4077 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir) 4078 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \ 4079 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir) 4080 #define CA0132_CODEC_MUTE(xname, nid, dir) \ 4081 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir) 4082 4083 /* lookup tables */ 4084 /* 4085 * Lookup table with decibel values for the DSP. When volume is changed in 4086 * Windows, the DSP is also sent the dB value in floating point. In Windows, 4087 * these values have decimal points, probably because the Windows driver 4088 * actually uses floating point. We can't here, so I made a lookup table of 4089 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the 4090 * DAC's, and 9 is the maximum. 4091 */ 4092 static const unsigned int float_vol_db_lookup[] = { 4093 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000, 4094 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000, 4095 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000, 4096 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000, 4097 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000, 4098 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000, 4099 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000, 4100 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000, 4101 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000, 4102 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000, 4103 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000, 4104 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 4105 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 4106 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 4107 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 4108 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 4109 0x40C00000, 0x40E00000, 0x41000000, 0x41100000 4110 }; 4111 4112 /* 4113 * This table counts from float 0 to 1 in increments of .01, which is 4114 * useful for a few different sliders. 4115 */ 4116 static const unsigned int float_zero_to_one_lookup[] = { 4117 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 4118 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 4119 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 4120 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 4121 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 4122 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 4123 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 4124 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 4125 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 4126 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 4127 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 4128 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 4129 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 4130 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 4131 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 4132 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 4133 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 4134 }; 4135 4136 /* 4137 * This table counts from float 10 to 1000, which is the range of the x-bass 4138 * crossover slider in Windows. 4139 */ 4140 static const unsigned int float_xbass_xover_lookup[] = { 4141 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000, 4142 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000, 4143 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000, 4144 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000, 4145 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000, 4146 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000, 4147 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000, 4148 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000, 4149 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000, 4150 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000, 4151 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000, 4152 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000, 4153 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000, 4154 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000, 4155 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000, 4156 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000, 4157 0x44728000, 0x44750000, 0x44778000, 0x447A0000 4158 }; 4159 4160 /* The following are for tuning of products */ 4161 #ifdef ENABLE_TUNING_CONTROLS 4162 4163 static const unsigned int voice_focus_vals_lookup[] = { 4164 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000, 4165 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000, 4166 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000, 4167 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000, 4168 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000, 4169 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000, 4170 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000, 4171 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000, 4172 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000, 4173 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000, 4174 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000, 4175 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000, 4176 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000, 4177 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000, 4178 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000, 4179 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000, 4180 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000, 4181 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000, 4182 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000, 4183 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000, 4184 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000, 4185 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000, 4186 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000, 4187 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000, 4188 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000, 4189 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000, 4190 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000 4191 }; 4192 4193 static const unsigned int mic_svm_vals_lookup[] = { 4194 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 4195 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 4196 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 4197 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 4198 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 4199 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 4200 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 4201 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 4202 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 4203 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 4204 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 4205 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 4206 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 4207 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 4208 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 4209 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 4210 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 4211 }; 4212 4213 static const unsigned int equalizer_vals_lookup[] = { 4214 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 4215 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 4216 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 4217 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 4218 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 4219 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000, 4220 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000, 4221 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 4222 0x41C00000 4223 }; 4224 4225 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid, 4226 const unsigned int *lookup, int idx) 4227 { 4228 int i = 0; 4229 4230 for (i = 0; i < TUNING_CTLS_COUNT; i++) 4231 if (nid == ca0132_tuning_ctls[i].nid) 4232 break; 4233 4234 snd_hda_power_up(codec); 4235 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20, 4236 ca0132_tuning_ctls[i].req, 4237 &(lookup[idx]), sizeof(unsigned int)); 4238 snd_hda_power_down(codec); 4239 4240 return 1; 4241 } 4242 4243 static int tuning_ctl_get(struct snd_kcontrol *kcontrol, 4244 struct snd_ctl_elem_value *ucontrol) 4245 { 4246 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4247 struct ca0132_spec *spec = codec->spec; 4248 hda_nid_t nid = get_amp_nid(kcontrol); 4249 long *valp = ucontrol->value.integer.value; 4250 int idx = nid - TUNING_CTL_START_NID; 4251 4252 *valp = spec->cur_ctl_vals[idx]; 4253 return 0; 4254 } 4255 4256 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol, 4257 struct snd_ctl_elem_info *uinfo) 4258 { 4259 int chs = get_amp_channels(kcontrol); 4260 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4261 uinfo->count = chs == 3 ? 2 : 1; 4262 uinfo->value.integer.min = 20; 4263 uinfo->value.integer.max = 180; 4264 uinfo->value.integer.step = 1; 4265 4266 return 0; 4267 } 4268 4269 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol, 4270 struct snd_ctl_elem_value *ucontrol) 4271 { 4272 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4273 struct ca0132_spec *spec = codec->spec; 4274 hda_nid_t nid = get_amp_nid(kcontrol); 4275 long *valp = ucontrol->value.integer.value; 4276 int idx; 4277 4278 idx = nid - TUNING_CTL_START_NID; 4279 /* any change? */ 4280 if (spec->cur_ctl_vals[idx] == *valp) 4281 return 0; 4282 4283 spec->cur_ctl_vals[idx] = *valp; 4284 4285 idx = *valp - 20; 4286 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx); 4287 4288 return 1; 4289 } 4290 4291 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol, 4292 struct snd_ctl_elem_info *uinfo) 4293 { 4294 int chs = get_amp_channels(kcontrol); 4295 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4296 uinfo->count = chs == 3 ? 2 : 1; 4297 uinfo->value.integer.min = 0; 4298 uinfo->value.integer.max = 100; 4299 uinfo->value.integer.step = 1; 4300 4301 return 0; 4302 } 4303 4304 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol, 4305 struct snd_ctl_elem_value *ucontrol) 4306 { 4307 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4308 struct ca0132_spec *spec = codec->spec; 4309 hda_nid_t nid = get_amp_nid(kcontrol); 4310 long *valp = ucontrol->value.integer.value; 4311 int idx; 4312 4313 idx = nid - TUNING_CTL_START_NID; 4314 /* any change? */ 4315 if (spec->cur_ctl_vals[idx] == *valp) 4316 return 0; 4317 4318 spec->cur_ctl_vals[idx] = *valp; 4319 4320 idx = *valp; 4321 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx); 4322 4323 return 0; 4324 } 4325 4326 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol, 4327 struct snd_ctl_elem_info *uinfo) 4328 { 4329 int chs = get_amp_channels(kcontrol); 4330 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4331 uinfo->count = chs == 3 ? 2 : 1; 4332 uinfo->value.integer.min = 0; 4333 uinfo->value.integer.max = 48; 4334 uinfo->value.integer.step = 1; 4335 4336 return 0; 4337 } 4338 4339 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol, 4340 struct snd_ctl_elem_value *ucontrol) 4341 { 4342 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4343 struct ca0132_spec *spec = codec->spec; 4344 hda_nid_t nid = get_amp_nid(kcontrol); 4345 long *valp = ucontrol->value.integer.value; 4346 int idx; 4347 4348 idx = nid - TUNING_CTL_START_NID; 4349 /* any change? */ 4350 if (spec->cur_ctl_vals[idx] == *valp) 4351 return 0; 4352 4353 spec->cur_ctl_vals[idx] = *valp; 4354 4355 idx = *valp; 4356 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx); 4357 4358 return 1; 4359 } 4360 4361 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0); 4362 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0); 4363 4364 static int add_tuning_control(struct hda_codec *codec, 4365 hda_nid_t pnid, hda_nid_t nid, 4366 const char *name, int dir) 4367 { 4368 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 4369 int type = dir ? HDA_INPUT : HDA_OUTPUT; 4370 struct snd_kcontrol_new knew = 4371 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 4372 4373 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 4374 SNDRV_CTL_ELEM_ACCESS_TLV_READ; 4375 knew.tlv.c = 0; 4376 knew.tlv.p = 0; 4377 switch (pnid) { 4378 case VOICE_FOCUS: 4379 knew.info = voice_focus_ctl_info; 4380 knew.get = tuning_ctl_get; 4381 knew.put = voice_focus_ctl_put; 4382 knew.tlv.p = voice_focus_db_scale; 4383 break; 4384 case MIC_SVM: 4385 knew.info = mic_svm_ctl_info; 4386 knew.get = tuning_ctl_get; 4387 knew.put = mic_svm_ctl_put; 4388 break; 4389 case EQUALIZER: 4390 knew.info = equalizer_ctl_info; 4391 knew.get = tuning_ctl_get; 4392 knew.put = equalizer_ctl_put; 4393 knew.tlv.p = eq_db_scale; 4394 break; 4395 default: 4396 return 0; 4397 } 4398 knew.private_value = 4399 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 4400 sprintf(namestr, "%s %s Volume", name, dirstr[dir]); 4401 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 4402 } 4403 4404 static int add_tuning_ctls(struct hda_codec *codec) 4405 { 4406 int i; 4407 int err; 4408 4409 for (i = 0; i < TUNING_CTLS_COUNT; i++) { 4410 err = add_tuning_control(codec, 4411 ca0132_tuning_ctls[i].parent_nid, 4412 ca0132_tuning_ctls[i].nid, 4413 ca0132_tuning_ctls[i].name, 4414 ca0132_tuning_ctls[i].direct); 4415 if (err < 0) 4416 return err; 4417 } 4418 4419 return 0; 4420 } 4421 4422 static void ca0132_init_tuning_defaults(struct hda_codec *codec) 4423 { 4424 struct ca0132_spec *spec = codec->spec; 4425 int i; 4426 4427 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */ 4428 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10; 4429 /* SVM level defaults to 0.74. */ 4430 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74; 4431 4432 /* EQ defaults to 0dB. */ 4433 for (i = 2; i < TUNING_CTLS_COUNT; i++) 4434 spec->cur_ctl_vals[i] = 24; 4435 } 4436 #endif /*ENABLE_TUNING_CONTROLS*/ 4437 4438 /* 4439 * Select the active output. 4440 * If autodetect is enabled, output will be selected based on jack detection. 4441 * If jack inserted, headphone will be selected, else built-in speakers 4442 * If autodetect is disabled, output will be selected based on selection. 4443 */ 4444 static int ca0132_select_out(struct hda_codec *codec) 4445 { 4446 struct ca0132_spec *spec = codec->spec; 4447 unsigned int pin_ctl; 4448 int jack_present; 4449 int auto_jack; 4450 unsigned int tmp; 4451 int err; 4452 4453 codec_dbg(codec, "ca0132_select_out\n"); 4454 4455 snd_hda_power_up_pm(codec); 4456 4457 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4458 4459 if (auto_jack) 4460 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp); 4461 else 4462 jack_present = 4463 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID]; 4464 4465 if (jack_present) 4466 spec->cur_out_type = HEADPHONE_OUT; 4467 else 4468 spec->cur_out_type = SPEAKER_OUT; 4469 4470 if (spec->cur_out_type == SPEAKER_OUT) { 4471 codec_dbg(codec, "ca0132_select_out speaker\n"); 4472 /*speaker out config*/ 4473 tmp = FLOAT_ONE; 4474 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4475 if (err < 0) 4476 goto exit; 4477 /*enable speaker EQ*/ 4478 tmp = FLOAT_ONE; 4479 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4480 if (err < 0) 4481 goto exit; 4482 4483 /* Setup EAPD */ 4484 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4485 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4486 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4487 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4488 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4489 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4490 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4491 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4492 4493 /* disable headphone node */ 4494 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4495 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4496 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4497 pin_ctl & ~PIN_HP); 4498 /* enable speaker node */ 4499 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4500 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4501 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4502 pin_ctl | PIN_OUT); 4503 } else { 4504 codec_dbg(codec, "ca0132_select_out hp\n"); 4505 /*headphone out config*/ 4506 tmp = FLOAT_ZERO; 4507 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4508 if (err < 0) 4509 goto exit; 4510 /*disable speaker EQ*/ 4511 tmp = FLOAT_ZERO; 4512 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4513 if (err < 0) 4514 goto exit; 4515 4516 /* Setup EAPD */ 4517 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4518 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4519 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4520 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4521 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4522 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4523 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4524 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4525 4526 /* disable speaker*/ 4527 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4528 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4529 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4530 pin_ctl & ~PIN_HP); 4531 /* enable headphone*/ 4532 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4533 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4534 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4535 pin_ctl | PIN_HP); 4536 } 4537 4538 exit: 4539 snd_hda_power_down_pm(codec); 4540 4541 return err < 0 ? err : 0; 4542 } 4543 4544 static int ae5_headphone_gain_set(struct hda_codec *codec, long val); 4545 static int zxr_headphone_gain_set(struct hda_codec *codec, long val); 4546 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val); 4547 4548 static void ae5_mmio_select_out(struct hda_codec *codec) 4549 { 4550 struct ca0132_spec *spec = codec->spec; 4551 const struct ae_ca0113_output_set *out_cmds; 4552 unsigned int i; 4553 4554 if (ca0132_quirk(spec) == QUIRK_AE5) 4555 out_cmds = &ae5_ca0113_output_presets; 4556 else 4557 out_cmds = &ae7_ca0113_output_presets; 4558 4559 for (i = 0; i < AE_CA0113_OUT_SET_COMMANDS; i++) 4560 ca0113_mmio_command_set(codec, out_cmds->group[i], 4561 out_cmds->target[i], 4562 out_cmds->vals[spec->cur_out_type][i]); 4563 } 4564 4565 static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec) 4566 { 4567 struct ca0132_spec *spec = codec->spec; 4568 int quirk = ca0132_quirk(spec); 4569 unsigned int tmp; 4570 int err; 4571 4572 /* 2.0/4.0 setup has no LFE channel, so setting full-range does nothing. */ 4573 if (spec->channel_cfg_val == SPEAKER_CHANNELS_4_0 4574 || spec->channel_cfg_val == SPEAKER_CHANNELS_2_0) 4575 return 0; 4576 4577 /* Set front L/R full range. Zero for full-range, one for redirection. */ 4578 tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE; 4579 err = dspio_set_uint_param(codec, 0x96, 4580 SPEAKER_FULL_RANGE_FRONT_L_R, tmp); 4581 if (err < 0) 4582 return err; 4583 4584 /* When setting full-range rear, both rear and center/lfe are set. */ 4585 tmp = spec->speaker_range_val[1] ? FLOAT_ZERO : FLOAT_ONE; 4586 err = dspio_set_uint_param(codec, 0x96, 4587 SPEAKER_FULL_RANGE_CENTER_LFE, tmp); 4588 if (err < 0) 4589 return err; 4590 4591 err = dspio_set_uint_param(codec, 0x96, 4592 SPEAKER_FULL_RANGE_REAR_L_R, tmp); 4593 if (err < 0) 4594 return err; 4595 4596 /* 4597 * Only the AE series cards set this value when setting full-range, 4598 * and it's always 1.0f. 4599 */ 4600 if (quirk == QUIRK_AE5 || quirk == QUIRK_AE7) { 4601 err = dspio_set_uint_param(codec, 0x96, 4602 SPEAKER_FULL_RANGE_SURROUND_L_R, FLOAT_ONE); 4603 if (err < 0) 4604 return err; 4605 } 4606 4607 return 0; 4608 } 4609 4610 static int ca0132_alt_surround_set_bass_redirection(struct hda_codec *codec, 4611 bool val) 4612 { 4613 struct ca0132_spec *spec = codec->spec; 4614 unsigned int tmp; 4615 int err; 4616 4617 if (val && spec->channel_cfg_val != SPEAKER_CHANNELS_4_0 && 4618 spec->channel_cfg_val != SPEAKER_CHANNELS_2_0) 4619 tmp = FLOAT_ONE; 4620 else 4621 tmp = FLOAT_ZERO; 4622 4623 err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp); 4624 if (err < 0) 4625 return err; 4626 4627 /* If it is enabled, make sure to set the crossover frequency. */ 4628 if (tmp) { 4629 tmp = float_xbass_xover_lookup[spec->xbass_xover_freq]; 4630 err = dspio_set_uint_param(codec, 0x96, 4631 SPEAKER_BASS_REDIRECT_XOVER_FREQ, tmp); 4632 if (err < 0) 4633 return err; 4634 } 4635 4636 return 0; 4637 } 4638 4639 /* 4640 * These are the commands needed to setup output on each of the different card 4641 * types. 4642 */ 4643 static void ca0132_alt_select_out_get_quirk_data(struct hda_codec *codec, 4644 const struct ca0132_alt_out_set_quirk_data **quirk_data) 4645 { 4646 struct ca0132_spec *spec = codec->spec; 4647 int quirk = ca0132_quirk(spec); 4648 unsigned int i; 4649 4650 *quirk_data = NULL; 4651 for (i = 0; i < ARRAY_SIZE(quirk_out_set_data); i++) { 4652 if (quirk_out_set_data[i].quirk_id == quirk) { 4653 *quirk_data = &quirk_out_set_data[i]; 4654 return; 4655 } 4656 } 4657 } 4658 4659 static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec) 4660 { 4661 const struct ca0132_alt_out_set_quirk_data *quirk_data; 4662 const struct ca0132_alt_out_set_info *out_info; 4663 struct ca0132_spec *spec = codec->spec; 4664 unsigned int i, gpio_data; 4665 int err; 4666 4667 ca0132_alt_select_out_get_quirk_data(codec, &quirk_data); 4668 if (!quirk_data) 4669 return 0; 4670 4671 out_info = &quirk_data->out_set_info[spec->cur_out_type]; 4672 if (quirk_data->is_ae_series) 4673 ae5_mmio_select_out(codec); 4674 4675 if (out_info->has_hda_gpio) { 4676 gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0, 4677 AC_VERB_GET_GPIO_DATA, 0); 4678 4679 if (out_info->hda_gpio_set) 4680 gpio_data |= (1 << out_info->hda_gpio_pin); 4681 else 4682 gpio_data &= ~(1 << out_info->hda_gpio_pin); 4683 4684 snd_hda_codec_write(codec, codec->core.afg, 0, 4685 AC_VERB_SET_GPIO_DATA, gpio_data); 4686 } 4687 4688 if (out_info->mmio_gpio_count) { 4689 for (i = 0; i < out_info->mmio_gpio_count; i++) { 4690 ca0113_mmio_gpio_set(codec, out_info->mmio_gpio_pin[i], 4691 out_info->mmio_gpio_set[i]); 4692 } 4693 } 4694 4695 if (out_info->scp_cmds_count) { 4696 for (i = 0; i < out_info->scp_cmds_count; i++) { 4697 err = dspio_set_uint_param(codec, 4698 out_info->scp_cmd_mid[i], 4699 out_info->scp_cmd_req[i], 4700 out_info->scp_cmd_val[i]); 4701 if (err < 0) 4702 return err; 4703 } 4704 } 4705 4706 chipio_set_control_param(codec, 0x0d, out_info->dac2port); 4707 4708 if (out_info->has_chipio_write) { 4709 chipio_write(codec, out_info->chipio_write_addr, 4710 out_info->chipio_write_data); 4711 } 4712 4713 if (quirk_data->has_headphone_gain) { 4714 if (spec->cur_out_type != HEADPHONE_OUT) { 4715 if (quirk_data->is_ae_series) 4716 ae5_headphone_gain_set(codec, 2); 4717 else 4718 zxr_headphone_gain_set(codec, 0); 4719 } else { 4720 if (quirk_data->is_ae_series) 4721 ae5_headphone_gain_set(codec, 4722 spec->ae5_headphone_gain_val); 4723 else 4724 zxr_headphone_gain_set(codec, 4725 spec->zxr_gain_set); 4726 } 4727 } 4728 4729 return 0; 4730 } 4731 4732 static void ca0132_set_out_node_pincfg(struct hda_codec *codec, hda_nid_t nid, 4733 bool out_enable, bool hp_enable) 4734 { 4735 unsigned int pin_ctl; 4736 4737 pin_ctl = snd_hda_codec_read(codec, nid, 0, 4738 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4739 4740 pin_ctl = hp_enable ? pin_ctl | PIN_HP_AMP : pin_ctl & ~PIN_HP_AMP; 4741 pin_ctl = out_enable ? pin_ctl | PIN_OUT : pin_ctl & ~PIN_OUT; 4742 snd_hda_set_pin_ctl(codec, nid, pin_ctl); 4743 } 4744 4745 /* 4746 * This function behaves similarly to the ca0132_select_out funciton above, 4747 * except with a few differences. It adds the ability to select the current 4748 * output with an enumerated control "output source" if the auto detect 4749 * mute switch is set to off. If the auto detect mute switch is enabled, it 4750 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection. 4751 * It also adds the ability to auto-detect the front headphone port. 4752 */ 4753 static int ca0132_alt_select_out(struct hda_codec *codec) 4754 { 4755 struct ca0132_spec *spec = codec->spec; 4756 unsigned int tmp, outfx_set; 4757 int jack_present; 4758 int auto_jack; 4759 int err; 4760 /* Default Headphone is rear headphone */ 4761 hda_nid_t headphone_nid = spec->out_pins[1]; 4762 4763 codec_dbg(codec, "%s\n", __func__); 4764 4765 snd_hda_power_up_pm(codec); 4766 4767 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4768 4769 /* 4770 * If headphone rear or front is plugged in, set to headphone. 4771 * If neither is plugged in, set to rear line out. Only if 4772 * hp/speaker auto detect is enabled. 4773 */ 4774 if (auto_jack) { 4775 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) || 4776 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp); 4777 4778 if (jack_present) 4779 spec->cur_out_type = HEADPHONE_OUT; 4780 else 4781 spec->cur_out_type = SPEAKER_OUT; 4782 } else 4783 spec->cur_out_type = spec->out_enum_val; 4784 4785 outfx_set = spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]; 4786 4787 /* Begin DSP output switch, mute DSP volume. */ 4788 err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE); 4789 if (err < 0) 4790 goto exit; 4791 4792 if (ca0132_alt_select_out_quirk_set(codec) < 0) 4793 goto exit; 4794 4795 switch (spec->cur_out_type) { 4796 case SPEAKER_OUT: 4797 codec_dbg(codec, "%s speaker\n", __func__); 4798 4799 /* Enable EAPD */ 4800 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4801 AC_VERB_SET_EAPD_BTLENABLE, 0x01); 4802 4803 /* Disable headphone node. */ 4804 ca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0); 4805 /* Set front L-R to output. */ 4806 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0); 4807 /* Set Center/LFE to output. */ 4808 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0); 4809 /* Set rear surround to output. */ 4810 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0); 4811 4812 /* 4813 * Without PlayEnhancement being enabled, if we've got a 2.0 4814 * setup, set it to floating point eight to disable any DSP 4815 * processing effects. 4816 */ 4817 if (!outfx_set && spec->channel_cfg_val == SPEAKER_CHANNELS_2_0) 4818 tmp = FLOAT_EIGHT; 4819 else 4820 tmp = speaker_channel_cfgs[spec->channel_cfg_val].val; 4821 4822 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4823 if (err < 0) 4824 goto exit; 4825 4826 break; 4827 case HEADPHONE_OUT: 4828 codec_dbg(codec, "%s hp\n", __func__); 4829 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4830 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4831 4832 /* Disable all speaker nodes. */ 4833 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0); 4834 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0); 4835 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0); 4836 4837 /* enable headphone, either front or rear */ 4838 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp)) 4839 headphone_nid = spec->out_pins[2]; 4840 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp)) 4841 headphone_nid = spec->out_pins[1]; 4842 4843 ca0132_set_out_node_pincfg(codec, headphone_nid, 1, 1); 4844 4845 if (outfx_set) 4846 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE); 4847 else 4848 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO); 4849 4850 if (err < 0) 4851 goto exit; 4852 break; 4853 } 4854 /* 4855 * If output effects are enabled, set the X-Bass effect value again to 4856 * make sure that it's properly enabled/disabled for speaker 4857 * configurations with an LFE channel. 4858 */ 4859 if (outfx_set) 4860 ca0132_effects_set(codec, X_BASS, 4861 spec->effects_switch[X_BASS - EFFECT_START_NID]); 4862 4863 /* Set speaker EQ bypass attenuation to 0. */ 4864 err = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO); 4865 if (err < 0) 4866 goto exit; 4867 4868 /* 4869 * Although unused on all cards but the AE series, this is always set 4870 * to zero when setting the output. 4871 */ 4872 err = dspio_set_uint_param(codec, 0x96, 4873 SPEAKER_TUNING_USE_SPEAKER_EQ, FLOAT_ZERO); 4874 if (err < 0) 4875 goto exit; 4876 4877 if (spec->cur_out_type == SPEAKER_OUT) 4878 err = ca0132_alt_surround_set_bass_redirection(codec, 4879 spec->bass_redirection_val); 4880 else 4881 err = ca0132_alt_surround_set_bass_redirection(codec, 0); 4882 4883 /* Unmute DSP now that we're done with output selection. */ 4884 err = dspio_set_uint_param(codec, 0x96, 4885 SPEAKER_TUNING_MUTE, FLOAT_ZERO); 4886 if (err < 0) 4887 goto exit; 4888 4889 if (spec->cur_out_type == SPEAKER_OUT) { 4890 err = ca0132_alt_set_full_range_speaker(codec); 4891 if (err < 0) 4892 goto exit; 4893 } 4894 4895 exit: 4896 snd_hda_power_down_pm(codec); 4897 4898 return err < 0 ? err : 0; 4899 } 4900 4901 static void ca0132_unsol_hp_delayed(struct work_struct *work) 4902 { 4903 struct ca0132_spec *spec = container_of( 4904 to_delayed_work(work), struct ca0132_spec, unsol_hp_work); 4905 struct hda_jack_tbl *jack; 4906 4907 if (ca0132_use_alt_functions(spec)) 4908 ca0132_alt_select_out(spec->codec); 4909 else 4910 ca0132_select_out(spec->codec); 4911 4912 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp); 4913 if (jack) { 4914 jack->block_report = 0; 4915 snd_hda_jack_report_sync(spec->codec); 4916 } 4917 } 4918 4919 static void ca0132_set_dmic(struct hda_codec *codec, int enable); 4920 static int ca0132_mic_boost_set(struct hda_codec *codec, long val); 4921 static void resume_mic1(struct hda_codec *codec, unsigned int oldval); 4922 static int stop_mic1(struct hda_codec *codec); 4923 static int ca0132_cvoice_switch_set(struct hda_codec *codec); 4924 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val); 4925 4926 /* 4927 * Select the active VIP source 4928 */ 4929 static int ca0132_set_vipsource(struct hda_codec *codec, int val) 4930 { 4931 struct ca0132_spec *spec = codec->spec; 4932 unsigned int tmp; 4933 4934 if (spec->dsp_state != DSP_DOWNLOADED) 4935 return 0; 4936 4937 /* if CrystalVoice if off, vipsource should be 0 */ 4938 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4939 (val == 0)) { 4940 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4941 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4942 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4943 if (spec->cur_mic_type == DIGITAL_MIC) 4944 tmp = FLOAT_TWO; 4945 else 4946 tmp = FLOAT_ONE; 4947 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4948 tmp = FLOAT_ZERO; 4949 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4950 } else { 4951 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4952 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4953 if (spec->cur_mic_type == DIGITAL_MIC) 4954 tmp = FLOAT_TWO; 4955 else 4956 tmp = FLOAT_ONE; 4957 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4958 tmp = FLOAT_ONE; 4959 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4960 msleep(20); 4961 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4962 } 4963 4964 return 1; 4965 } 4966 4967 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val) 4968 { 4969 struct ca0132_spec *spec = codec->spec; 4970 unsigned int tmp; 4971 4972 if (spec->dsp_state != DSP_DOWNLOADED) 4973 return 0; 4974 4975 codec_dbg(codec, "%s\n", __func__); 4976 4977 chipio_set_stream_control(codec, 0x03, 0); 4978 chipio_set_stream_control(codec, 0x04, 0); 4979 4980 /* if CrystalVoice is off, vipsource should be 0 */ 4981 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4982 (val == 0) || spec->in_enum_val == REAR_LINE_IN) { 4983 codec_dbg(codec, "%s: off.", __func__); 4984 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4985 4986 tmp = FLOAT_ZERO; 4987 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4988 4989 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4990 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4991 if (ca0132_quirk(spec) == QUIRK_R3DI) 4992 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4993 4994 4995 if (spec->in_enum_val == REAR_LINE_IN) 4996 tmp = FLOAT_ZERO; 4997 else { 4998 if (ca0132_quirk(spec) == QUIRK_SBZ) 4999 tmp = FLOAT_THREE; 5000 else 5001 tmp = FLOAT_ONE; 5002 } 5003 5004 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5005 5006 } else { 5007 codec_dbg(codec, "%s: on.", __func__); 5008 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 5009 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 5010 if (ca0132_quirk(spec) == QUIRK_R3DI) 5011 chipio_set_conn_rate(codec, 0x0F, SR_16_000); 5012 5013 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID]) 5014 tmp = FLOAT_TWO; 5015 else 5016 tmp = FLOAT_ONE; 5017 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5018 5019 tmp = FLOAT_ONE; 5020 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 5021 5022 msleep(20); 5023 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 5024 } 5025 5026 chipio_set_stream_control(codec, 0x03, 1); 5027 chipio_set_stream_control(codec, 0x04, 1); 5028 5029 return 1; 5030 } 5031 5032 /* 5033 * Select the active microphone. 5034 * If autodetect is enabled, mic will be selected based on jack detection. 5035 * If jack inserted, ext.mic will be selected, else built-in mic 5036 * If autodetect is disabled, mic will be selected based on selection. 5037 */ 5038 static int ca0132_select_mic(struct hda_codec *codec) 5039 { 5040 struct ca0132_spec *spec = codec->spec; 5041 int jack_present; 5042 int auto_jack; 5043 5044 codec_dbg(codec, "ca0132_select_mic\n"); 5045 5046 snd_hda_power_up_pm(codec); 5047 5048 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 5049 5050 if (auto_jack) 5051 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1); 5052 else 5053 jack_present = 5054 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID]; 5055 5056 if (jack_present) 5057 spec->cur_mic_type = LINE_MIC_IN; 5058 else 5059 spec->cur_mic_type = DIGITAL_MIC; 5060 5061 if (spec->cur_mic_type == DIGITAL_MIC) { 5062 /* enable digital Mic */ 5063 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000); 5064 ca0132_set_dmic(codec, 1); 5065 ca0132_mic_boost_set(codec, 0); 5066 /* set voice focus */ 5067 ca0132_effects_set(codec, VOICE_FOCUS, 5068 spec->effects_switch 5069 [VOICE_FOCUS - EFFECT_START_NID]); 5070 } else { 5071 /* disable digital Mic */ 5072 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000); 5073 ca0132_set_dmic(codec, 0); 5074 ca0132_mic_boost_set(codec, spec->cur_mic_boost); 5075 /* disable voice focus */ 5076 ca0132_effects_set(codec, VOICE_FOCUS, 0); 5077 } 5078 5079 snd_hda_power_down_pm(codec); 5080 5081 return 0; 5082 } 5083 5084 /* 5085 * Select the active input. 5086 * Mic detection isn't used, because it's kind of pointless on the SBZ. 5087 * The front mic has no jack-detection, so the only way to switch to it 5088 * is to do it manually in alsamixer. 5089 */ 5090 static int ca0132_alt_select_in(struct hda_codec *codec) 5091 { 5092 struct ca0132_spec *spec = codec->spec; 5093 unsigned int tmp; 5094 5095 codec_dbg(codec, "%s\n", __func__); 5096 5097 snd_hda_power_up_pm(codec); 5098 5099 chipio_set_stream_control(codec, 0x03, 0); 5100 chipio_set_stream_control(codec, 0x04, 0); 5101 5102 spec->cur_mic_type = spec->in_enum_val; 5103 5104 switch (spec->cur_mic_type) { 5105 case REAR_MIC: 5106 switch (ca0132_quirk(spec)) { 5107 case QUIRK_SBZ: 5108 case QUIRK_R3D: 5109 ca0113_mmio_gpio_set(codec, 0, false); 5110 tmp = FLOAT_THREE; 5111 break; 5112 case QUIRK_ZXR: 5113 tmp = FLOAT_THREE; 5114 break; 5115 case QUIRK_R3DI: 5116 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 5117 tmp = FLOAT_ONE; 5118 break; 5119 case QUIRK_AE5: 5120 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5121 tmp = FLOAT_THREE; 5122 break; 5123 case QUIRK_AE7: 5124 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5125 tmp = FLOAT_THREE; 5126 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, 5127 SR_96_000); 5128 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, 5129 SR_96_000); 5130 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO); 5131 break; 5132 default: 5133 tmp = FLOAT_ONE; 5134 break; 5135 } 5136 5137 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5138 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5139 if (ca0132_quirk(spec) == QUIRK_R3DI) 5140 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5141 5142 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5143 5144 chipio_set_stream_control(codec, 0x03, 1); 5145 chipio_set_stream_control(codec, 0x04, 1); 5146 switch (ca0132_quirk(spec)) { 5147 case QUIRK_SBZ: 5148 chipio_write(codec, 0x18B098, 0x0000000C); 5149 chipio_write(codec, 0x18B09C, 0x0000000C); 5150 break; 5151 case QUIRK_ZXR: 5152 chipio_write(codec, 0x18B098, 0x0000000C); 5153 chipio_write(codec, 0x18B09C, 0x000000CC); 5154 break; 5155 case QUIRK_AE5: 5156 chipio_write(codec, 0x18B098, 0x0000000C); 5157 chipio_write(codec, 0x18B09C, 0x0000004C); 5158 break; 5159 default: 5160 break; 5161 } 5162 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5163 break; 5164 case REAR_LINE_IN: 5165 ca0132_mic_boost_set(codec, 0); 5166 switch (ca0132_quirk(spec)) { 5167 case QUIRK_SBZ: 5168 case QUIRK_R3D: 5169 ca0113_mmio_gpio_set(codec, 0, false); 5170 break; 5171 case QUIRK_R3DI: 5172 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 5173 break; 5174 case QUIRK_AE5: 5175 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5176 break; 5177 case QUIRK_AE7: 5178 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f); 5179 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, 5180 SR_96_000); 5181 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, 5182 SR_96_000); 5183 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO); 5184 break; 5185 default: 5186 break; 5187 } 5188 5189 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5190 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5191 if (ca0132_quirk(spec) == QUIRK_R3DI) 5192 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5193 5194 if (ca0132_quirk(spec) == QUIRK_AE7) 5195 tmp = FLOAT_THREE; 5196 else 5197 tmp = FLOAT_ZERO; 5198 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5199 5200 switch (ca0132_quirk(spec)) { 5201 case QUIRK_SBZ: 5202 case QUIRK_AE5: 5203 chipio_write(codec, 0x18B098, 0x00000000); 5204 chipio_write(codec, 0x18B09C, 0x00000000); 5205 break; 5206 default: 5207 break; 5208 } 5209 chipio_set_stream_control(codec, 0x03, 1); 5210 chipio_set_stream_control(codec, 0x04, 1); 5211 break; 5212 case FRONT_MIC: 5213 switch (ca0132_quirk(spec)) { 5214 case QUIRK_SBZ: 5215 case QUIRK_R3D: 5216 ca0113_mmio_gpio_set(codec, 0, true); 5217 ca0113_mmio_gpio_set(codec, 5, false); 5218 tmp = FLOAT_THREE; 5219 break; 5220 case QUIRK_R3DI: 5221 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC); 5222 tmp = FLOAT_ONE; 5223 break; 5224 case QUIRK_AE5: 5225 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f); 5226 tmp = FLOAT_THREE; 5227 break; 5228 default: 5229 tmp = FLOAT_ONE; 5230 break; 5231 } 5232 5233 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5234 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5235 if (ca0132_quirk(spec) == QUIRK_R3DI) 5236 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5237 5238 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5239 5240 chipio_set_stream_control(codec, 0x03, 1); 5241 chipio_set_stream_control(codec, 0x04, 1); 5242 5243 switch (ca0132_quirk(spec)) { 5244 case QUIRK_SBZ: 5245 chipio_write(codec, 0x18B098, 0x0000000C); 5246 chipio_write(codec, 0x18B09C, 0x000000CC); 5247 break; 5248 case QUIRK_AE5: 5249 chipio_write(codec, 0x18B098, 0x0000000C); 5250 chipio_write(codec, 0x18B09C, 0x0000004C); 5251 break; 5252 default: 5253 break; 5254 } 5255 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5256 break; 5257 } 5258 ca0132_cvoice_switch_set(codec); 5259 5260 snd_hda_power_down_pm(codec); 5261 return 0; 5262 } 5263 5264 /* 5265 * Check if VNODE settings take effect immediately. 5266 */ 5267 static bool ca0132_is_vnode_effective(struct hda_codec *codec, 5268 hda_nid_t vnid, 5269 hda_nid_t *shared_nid) 5270 { 5271 struct ca0132_spec *spec = codec->spec; 5272 hda_nid_t nid; 5273 5274 switch (vnid) { 5275 case VNID_SPK: 5276 nid = spec->shared_out_nid; 5277 break; 5278 case VNID_MIC: 5279 nid = spec->shared_mic_nid; 5280 break; 5281 default: 5282 return false; 5283 } 5284 5285 if (shared_nid) 5286 *shared_nid = nid; 5287 5288 return true; 5289 } 5290 5291 /* 5292 * The following functions are control change helpers. 5293 * They return 0 if no changed. Return 1 if changed. 5294 */ 5295 static int ca0132_voicefx_set(struct hda_codec *codec, int enable) 5296 { 5297 struct ca0132_spec *spec = codec->spec; 5298 unsigned int tmp; 5299 5300 /* based on CrystalVoice state to enable VoiceFX. */ 5301 if (enable) { 5302 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ? 5303 FLOAT_ONE : FLOAT_ZERO; 5304 } else { 5305 tmp = FLOAT_ZERO; 5306 } 5307 5308 dspio_set_uint_param(codec, ca0132_voicefx.mid, 5309 ca0132_voicefx.reqs[0], tmp); 5310 5311 return 1; 5312 } 5313 5314 /* 5315 * Set the effects parameters 5316 */ 5317 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val) 5318 { 5319 struct ca0132_spec *spec = codec->spec; 5320 unsigned int on, tmp, channel_cfg; 5321 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 5322 int err = 0; 5323 int idx = nid - EFFECT_START_NID; 5324 5325 if ((idx < 0) || (idx >= num_fx)) 5326 return 0; /* no changed */ 5327 5328 /* for out effect, qualify with PE */ 5329 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) { 5330 /* if PE if off, turn off out effects. */ 5331 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 5332 val = 0; 5333 if (spec->cur_out_type == SPEAKER_OUT && nid == X_BASS) { 5334 channel_cfg = spec->channel_cfg_val; 5335 if (channel_cfg != SPEAKER_CHANNELS_2_0 && 5336 channel_cfg != SPEAKER_CHANNELS_4_0) 5337 val = 0; 5338 } 5339 } 5340 5341 /* for in effect, qualify with CrystalVoice */ 5342 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) { 5343 /* if CrystalVoice if off, turn off in effects. */ 5344 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 5345 val = 0; 5346 5347 /* Voice Focus applies to 2-ch Mic, Digital Mic */ 5348 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC)) 5349 val = 0; 5350 5351 /* If Voice Focus on SBZ, set to two channel. */ 5352 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec) 5353 && (spec->cur_mic_type != REAR_LINE_IN)) { 5354 if (spec->effects_switch[CRYSTAL_VOICE - 5355 EFFECT_START_NID]) { 5356 5357 if (spec->effects_switch[VOICE_FOCUS - 5358 EFFECT_START_NID]) { 5359 tmp = FLOAT_TWO; 5360 val = 1; 5361 } else 5362 tmp = FLOAT_ONE; 5363 5364 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5365 } 5366 } 5367 /* 5368 * For SBZ noise reduction, there's an extra command 5369 * to module ID 0x47. No clue why. 5370 */ 5371 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec) 5372 && (spec->cur_mic_type != REAR_LINE_IN)) { 5373 if (spec->effects_switch[CRYSTAL_VOICE - 5374 EFFECT_START_NID]) { 5375 if (spec->effects_switch[NOISE_REDUCTION - 5376 EFFECT_START_NID]) 5377 tmp = FLOAT_ONE; 5378 else 5379 tmp = FLOAT_ZERO; 5380 } else 5381 tmp = FLOAT_ZERO; 5382 5383 dspio_set_uint_param(codec, 0x47, 0x00, tmp); 5384 } 5385 5386 /* If rear line in disable effects. */ 5387 if (ca0132_use_alt_functions(spec) && 5388 spec->in_enum_val == REAR_LINE_IN) 5389 val = 0; 5390 } 5391 5392 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n", 5393 nid, val); 5394 5395 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE; 5396 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid, 5397 ca0132_effects[idx].reqs[0], on); 5398 5399 if (err < 0) 5400 return 0; /* no changed */ 5401 5402 return 1; 5403 } 5404 5405 /* 5406 * Turn on/off Playback Enhancements 5407 */ 5408 static int ca0132_pe_switch_set(struct hda_codec *codec) 5409 { 5410 struct ca0132_spec *spec = codec->spec; 5411 hda_nid_t nid; 5412 int i, ret = 0; 5413 5414 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n", 5415 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]); 5416 5417 if (ca0132_use_alt_functions(spec)) 5418 ca0132_alt_select_out(codec); 5419 5420 i = OUT_EFFECT_START_NID - EFFECT_START_NID; 5421 nid = OUT_EFFECT_START_NID; 5422 /* PE affects all out effects */ 5423 for (; nid < OUT_EFFECT_END_NID; nid++, i++) 5424 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 5425 5426 return ret; 5427 } 5428 5429 /* Check if Mic1 is streaming, if so, stop streaming */ 5430 static int stop_mic1(struct hda_codec *codec) 5431 { 5432 struct ca0132_spec *spec = codec->spec; 5433 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0, 5434 AC_VERB_GET_CONV, 0); 5435 if (oldval != 0) 5436 snd_hda_codec_write(codec, spec->adcs[0], 0, 5437 AC_VERB_SET_CHANNEL_STREAMID, 5438 0); 5439 return oldval; 5440 } 5441 5442 /* Resume Mic1 streaming if it was stopped. */ 5443 static void resume_mic1(struct hda_codec *codec, unsigned int oldval) 5444 { 5445 struct ca0132_spec *spec = codec->spec; 5446 /* Restore the previous stream and channel */ 5447 if (oldval != 0) 5448 snd_hda_codec_write(codec, spec->adcs[0], 0, 5449 AC_VERB_SET_CHANNEL_STREAMID, 5450 oldval); 5451 } 5452 5453 /* 5454 * Turn on/off CrystalVoice 5455 */ 5456 static int ca0132_cvoice_switch_set(struct hda_codec *codec) 5457 { 5458 struct ca0132_spec *spec = codec->spec; 5459 hda_nid_t nid; 5460 int i, ret = 0; 5461 unsigned int oldval; 5462 5463 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n", 5464 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]); 5465 5466 i = IN_EFFECT_START_NID - EFFECT_START_NID; 5467 nid = IN_EFFECT_START_NID; 5468 /* CrystalVoice affects all in effects */ 5469 for (; nid < IN_EFFECT_END_NID; nid++, i++) 5470 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 5471 5472 /* including VoiceFX */ 5473 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0)); 5474 5475 /* set correct vipsource */ 5476 oldval = stop_mic1(codec); 5477 if (ca0132_use_alt_functions(spec)) 5478 ret |= ca0132_alt_set_vipsource(codec, 1); 5479 else 5480 ret |= ca0132_set_vipsource(codec, 1); 5481 resume_mic1(codec, oldval); 5482 return ret; 5483 } 5484 5485 static int ca0132_mic_boost_set(struct hda_codec *codec, long val) 5486 { 5487 struct ca0132_spec *spec = codec->spec; 5488 int ret = 0; 5489 5490 if (val) /* on */ 5491 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5492 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3); 5493 else /* off */ 5494 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5495 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0); 5496 5497 return ret; 5498 } 5499 5500 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val) 5501 { 5502 struct ca0132_spec *spec = codec->spec; 5503 int ret = 0; 5504 5505 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5506 HDA_INPUT, 0, HDA_AMP_VOLMASK, val); 5507 return ret; 5508 } 5509 5510 static int ae5_headphone_gain_set(struct hda_codec *codec, long val) 5511 { 5512 unsigned int i; 5513 5514 for (i = 0; i < 4; i++) 5515 ca0113_mmio_command_set(codec, 0x48, 0x11 + i, 5516 ae5_headphone_gain_presets[val].vals[i]); 5517 return 0; 5518 } 5519 5520 /* 5521 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone 5522 * amplifier to handle a 600 ohm load. 5523 */ 5524 static int zxr_headphone_gain_set(struct hda_codec *codec, long val) 5525 { 5526 ca0113_mmio_gpio_set(codec, 1, val); 5527 5528 return 0; 5529 } 5530 5531 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol, 5532 struct snd_ctl_elem_value *ucontrol) 5533 { 5534 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5535 hda_nid_t nid = get_amp_nid(kcontrol); 5536 hda_nid_t shared_nid = 0; 5537 bool effective; 5538 int ret = 0; 5539 struct ca0132_spec *spec = codec->spec; 5540 int auto_jack; 5541 5542 if (nid == VNID_HP_SEL) { 5543 auto_jack = 5544 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 5545 if (!auto_jack) { 5546 if (ca0132_use_alt_functions(spec)) 5547 ca0132_alt_select_out(codec); 5548 else 5549 ca0132_select_out(codec); 5550 } 5551 return 1; 5552 } 5553 5554 if (nid == VNID_AMIC1_SEL) { 5555 auto_jack = 5556 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 5557 if (!auto_jack) 5558 ca0132_select_mic(codec); 5559 return 1; 5560 } 5561 5562 if (nid == VNID_HP_ASEL) { 5563 if (ca0132_use_alt_functions(spec)) 5564 ca0132_alt_select_out(codec); 5565 else 5566 ca0132_select_out(codec); 5567 return 1; 5568 } 5569 5570 if (nid == VNID_AMIC1_ASEL) { 5571 ca0132_select_mic(codec); 5572 return 1; 5573 } 5574 5575 /* if effective conditions, then update hw immediately. */ 5576 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 5577 if (effective) { 5578 int dir = get_amp_direction(kcontrol); 5579 int ch = get_amp_channels(kcontrol); 5580 unsigned long pval; 5581 5582 mutex_lock(&codec->control_mutex); 5583 pval = kcontrol->private_value; 5584 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 5585 0, dir); 5586 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol); 5587 kcontrol->private_value = pval; 5588 mutex_unlock(&codec->control_mutex); 5589 } 5590 5591 return ret; 5592 } 5593 /* End of control change helpers. */ 5594 5595 static void ca0132_alt_bass_redirection_xover_set(struct hda_codec *codec, 5596 long idx) 5597 { 5598 snd_hda_power_up(codec); 5599 5600 dspio_set_param(codec, 0x96, 0x20, SPEAKER_BASS_REDIRECT_XOVER_FREQ, 5601 &(float_xbass_xover_lookup[idx]), sizeof(unsigned int)); 5602 5603 snd_hda_power_down(codec); 5604 } 5605 5606 /* 5607 * Below I've added controls to mess with the effect levels, I've only enabled 5608 * them on the Sound Blaster Z, but they would probably also work on the 5609 * Chromebook. I figured they were probably tuned specifically for it, and left 5610 * out for a reason. 5611 */ 5612 5613 /* Sets DSP effect level from the sliders above the controls */ 5614 5615 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid, 5616 const unsigned int *lookup, int idx) 5617 { 5618 int i = 0; 5619 unsigned int y; 5620 /* 5621 * For X_BASS, req 2 is actually crossover freq instead of 5622 * effect level 5623 */ 5624 if (nid == X_BASS) 5625 y = 2; 5626 else 5627 y = 1; 5628 5629 snd_hda_power_up(codec); 5630 if (nid == XBASS_XOVER) { 5631 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5632 if (ca0132_effects[i].nid == X_BASS) 5633 break; 5634 5635 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5636 ca0132_effects[i].reqs[1], 5637 &(lookup[idx - 1]), sizeof(unsigned int)); 5638 } else { 5639 /* Find the actual effect structure */ 5640 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5641 if (nid == ca0132_effects[i].nid) 5642 break; 5643 5644 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5645 ca0132_effects[i].reqs[y], 5646 &(lookup[idx]), sizeof(unsigned int)); 5647 } 5648 5649 snd_hda_power_down(codec); 5650 5651 return 0; 5652 } 5653 5654 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol, 5655 struct snd_ctl_elem_value *ucontrol) 5656 { 5657 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5658 struct ca0132_spec *spec = codec->spec; 5659 long *valp = ucontrol->value.integer.value; 5660 hda_nid_t nid = get_amp_nid(kcontrol); 5661 5662 if (nid == BASS_REDIRECTION_XOVER) 5663 *valp = spec->bass_redirect_xover_freq; 5664 else 5665 *valp = spec->xbass_xover_freq; 5666 5667 return 0; 5668 } 5669 5670 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol, 5671 struct snd_ctl_elem_value *ucontrol) 5672 { 5673 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5674 struct ca0132_spec *spec = codec->spec; 5675 hda_nid_t nid = get_amp_nid(kcontrol); 5676 long *valp = ucontrol->value.integer.value; 5677 int idx = nid - OUT_EFFECT_START_NID; 5678 5679 *valp = spec->fx_ctl_val[idx]; 5680 return 0; 5681 } 5682 5683 /* 5684 * The X-bass crossover starts at 10hz, so the min is 1. The 5685 * frequency is set in multiples of 10. 5686 */ 5687 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol, 5688 struct snd_ctl_elem_info *uinfo) 5689 { 5690 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5691 uinfo->count = 1; 5692 uinfo->value.integer.min = 1; 5693 uinfo->value.integer.max = 100; 5694 uinfo->value.integer.step = 1; 5695 5696 return 0; 5697 } 5698 5699 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol, 5700 struct snd_ctl_elem_info *uinfo) 5701 { 5702 int chs = get_amp_channels(kcontrol); 5703 5704 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5705 uinfo->count = chs == 3 ? 2 : 1; 5706 uinfo->value.integer.min = 0; 5707 uinfo->value.integer.max = 100; 5708 uinfo->value.integer.step = 1; 5709 5710 return 0; 5711 } 5712 5713 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol, 5714 struct snd_ctl_elem_value *ucontrol) 5715 { 5716 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5717 struct ca0132_spec *spec = codec->spec; 5718 hda_nid_t nid = get_amp_nid(kcontrol); 5719 long *valp = ucontrol->value.integer.value; 5720 long *cur_val; 5721 int idx; 5722 5723 if (nid == BASS_REDIRECTION_XOVER) 5724 cur_val = &spec->bass_redirect_xover_freq; 5725 else 5726 cur_val = &spec->xbass_xover_freq; 5727 5728 /* any change? */ 5729 if (*cur_val == *valp) 5730 return 0; 5731 5732 *cur_val = *valp; 5733 5734 idx = *valp; 5735 if (nid == BASS_REDIRECTION_XOVER) 5736 ca0132_alt_bass_redirection_xover_set(codec, *cur_val); 5737 else 5738 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx); 5739 5740 return 0; 5741 } 5742 5743 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol, 5744 struct snd_ctl_elem_value *ucontrol) 5745 { 5746 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5747 struct ca0132_spec *spec = codec->spec; 5748 hda_nid_t nid = get_amp_nid(kcontrol); 5749 long *valp = ucontrol->value.integer.value; 5750 int idx; 5751 5752 idx = nid - EFFECT_START_NID; 5753 /* any change? */ 5754 if (spec->fx_ctl_val[idx] == *valp) 5755 return 0; 5756 5757 spec->fx_ctl_val[idx] = *valp; 5758 5759 idx = *valp; 5760 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx); 5761 5762 return 0; 5763 } 5764 5765 5766 /* 5767 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original 5768 * only has off or full 30 dB, and didn't like making a volume slider that has 5769 * traditional 0-100 in alsamixer that goes in big steps. I like enum better. 5770 */ 5771 #define MIC_BOOST_NUM_OF_STEPS 4 5772 #define MIC_BOOST_ENUM_MAX_STRLEN 10 5773 5774 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol, 5775 struct snd_ctl_elem_info *uinfo) 5776 { 5777 char *sfx = "dB"; 5778 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5779 5780 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5781 uinfo->count = 1; 5782 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS; 5783 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS) 5784 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1; 5785 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx); 5786 strcpy(uinfo->value.enumerated.name, namestr); 5787 return 0; 5788 } 5789 5790 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol, 5791 struct snd_ctl_elem_value *ucontrol) 5792 { 5793 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5794 struct ca0132_spec *spec = codec->spec; 5795 5796 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val; 5797 return 0; 5798 } 5799 5800 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol, 5801 struct snd_ctl_elem_value *ucontrol) 5802 { 5803 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5804 struct ca0132_spec *spec = codec->spec; 5805 int sel = ucontrol->value.enumerated.item[0]; 5806 unsigned int items = MIC_BOOST_NUM_OF_STEPS; 5807 5808 if (sel >= items) 5809 return 0; 5810 5811 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n", 5812 sel); 5813 5814 spec->mic_boost_enum_val = sel; 5815 5816 if (spec->in_enum_val != REAR_LINE_IN) 5817 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5818 5819 return 1; 5820 } 5821 5822 /* 5823 * Sound BlasterX AE-5 Headphone Gain Controls. 5824 */ 5825 #define AE5_HEADPHONE_GAIN_MAX 3 5826 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol, 5827 struct snd_ctl_elem_info *uinfo) 5828 { 5829 char *sfx = " Ohms)"; 5830 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5831 5832 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5833 uinfo->count = 1; 5834 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX; 5835 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX) 5836 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1; 5837 sprintf(namestr, "%s %s", 5838 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name, 5839 sfx); 5840 strcpy(uinfo->value.enumerated.name, namestr); 5841 return 0; 5842 } 5843 5844 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol, 5845 struct snd_ctl_elem_value *ucontrol) 5846 { 5847 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5848 struct ca0132_spec *spec = codec->spec; 5849 5850 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val; 5851 return 0; 5852 } 5853 5854 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol, 5855 struct snd_ctl_elem_value *ucontrol) 5856 { 5857 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5858 struct ca0132_spec *spec = codec->spec; 5859 int sel = ucontrol->value.enumerated.item[0]; 5860 unsigned int items = AE5_HEADPHONE_GAIN_MAX; 5861 5862 if (sel >= items) 5863 return 0; 5864 5865 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n", 5866 sel); 5867 5868 spec->ae5_headphone_gain_val = sel; 5869 5870 if (spec->out_enum_val == HEADPHONE_OUT) 5871 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val); 5872 5873 return 1; 5874 } 5875 5876 /* 5877 * Sound BlasterX AE-5 sound filter enumerated control. 5878 */ 5879 #define AE5_SOUND_FILTER_MAX 3 5880 5881 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol, 5882 struct snd_ctl_elem_info *uinfo) 5883 { 5884 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5885 5886 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5887 uinfo->count = 1; 5888 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX; 5889 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX) 5890 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1; 5891 sprintf(namestr, "%s", 5892 ae5_filter_presets[uinfo->value.enumerated.item].name); 5893 strcpy(uinfo->value.enumerated.name, namestr); 5894 return 0; 5895 } 5896 5897 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol, 5898 struct snd_ctl_elem_value *ucontrol) 5899 { 5900 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5901 struct ca0132_spec *spec = codec->spec; 5902 5903 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val; 5904 return 0; 5905 } 5906 5907 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol, 5908 struct snd_ctl_elem_value *ucontrol) 5909 { 5910 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5911 struct ca0132_spec *spec = codec->spec; 5912 int sel = ucontrol->value.enumerated.item[0]; 5913 unsigned int items = AE5_SOUND_FILTER_MAX; 5914 5915 if (sel >= items) 5916 return 0; 5917 5918 codec_dbg(codec, "ae5_sound_filter: %s\n", 5919 ae5_filter_presets[sel].name); 5920 5921 spec->ae5_filter_val = sel; 5922 5923 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 5924 ae5_filter_presets[sel].val); 5925 5926 return 1; 5927 } 5928 5929 /* 5930 * Input Select Control for alternative ca0132 codecs. This exists because 5931 * front microphone has no auto-detect, and we need a way to set the rear 5932 * as line-in 5933 */ 5934 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol, 5935 struct snd_ctl_elem_info *uinfo) 5936 { 5937 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5938 uinfo->count = 1; 5939 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS; 5940 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS) 5941 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1; 5942 strcpy(uinfo->value.enumerated.name, 5943 in_src_str[uinfo->value.enumerated.item]); 5944 return 0; 5945 } 5946 5947 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol, 5948 struct snd_ctl_elem_value *ucontrol) 5949 { 5950 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5951 struct ca0132_spec *spec = codec->spec; 5952 5953 ucontrol->value.enumerated.item[0] = spec->in_enum_val; 5954 return 0; 5955 } 5956 5957 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol, 5958 struct snd_ctl_elem_value *ucontrol) 5959 { 5960 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5961 struct ca0132_spec *spec = codec->spec; 5962 int sel = ucontrol->value.enumerated.item[0]; 5963 unsigned int items = IN_SRC_NUM_OF_INPUTS; 5964 5965 /* 5966 * The AE-7 has no front microphone, so limit items to 2: rear mic and 5967 * line-in. 5968 */ 5969 if (ca0132_quirk(spec) == QUIRK_AE7) 5970 items = 2; 5971 5972 if (sel >= items) 5973 return 0; 5974 5975 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n", 5976 sel, in_src_str[sel]); 5977 5978 spec->in_enum_val = sel; 5979 5980 ca0132_alt_select_in(codec); 5981 5982 return 1; 5983 } 5984 5985 /* Sound Blaster Z Output Select Control */ 5986 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol, 5987 struct snd_ctl_elem_info *uinfo) 5988 { 5989 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5990 uinfo->count = 1; 5991 uinfo->value.enumerated.items = NUM_OF_OUTPUTS; 5992 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS) 5993 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1; 5994 strcpy(uinfo->value.enumerated.name, 5995 out_type_str[uinfo->value.enumerated.item]); 5996 return 0; 5997 } 5998 5999 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol, 6000 struct snd_ctl_elem_value *ucontrol) 6001 { 6002 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6003 struct ca0132_spec *spec = codec->spec; 6004 6005 ucontrol->value.enumerated.item[0] = spec->out_enum_val; 6006 return 0; 6007 } 6008 6009 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol, 6010 struct snd_ctl_elem_value *ucontrol) 6011 { 6012 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6013 struct ca0132_spec *spec = codec->spec; 6014 int sel = ucontrol->value.enumerated.item[0]; 6015 unsigned int items = NUM_OF_OUTPUTS; 6016 unsigned int auto_jack; 6017 6018 if (sel >= items) 6019 return 0; 6020 6021 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n", 6022 sel, out_type_str[sel]); 6023 6024 spec->out_enum_val = sel; 6025 6026 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 6027 6028 if (!auto_jack) 6029 ca0132_alt_select_out(codec); 6030 6031 return 1; 6032 } 6033 6034 /* Select surround output type: 2.1, 4.0, 4.1, or 5.1. */ 6035 static int ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol *kcontrol, 6036 struct snd_ctl_elem_info *uinfo) 6037 { 6038 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT; 6039 6040 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6041 uinfo->count = 1; 6042 uinfo->value.enumerated.items = items; 6043 if (uinfo->value.enumerated.item >= items) 6044 uinfo->value.enumerated.item = items - 1; 6045 strcpy(uinfo->value.enumerated.name, 6046 speaker_channel_cfgs[uinfo->value.enumerated.item].name); 6047 return 0; 6048 } 6049 6050 static int ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol *kcontrol, 6051 struct snd_ctl_elem_value *ucontrol) 6052 { 6053 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6054 struct ca0132_spec *spec = codec->spec; 6055 6056 ucontrol->value.enumerated.item[0] = spec->channel_cfg_val; 6057 return 0; 6058 } 6059 6060 static int ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol *kcontrol, 6061 struct snd_ctl_elem_value *ucontrol) 6062 { 6063 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6064 struct ca0132_spec *spec = codec->spec; 6065 int sel = ucontrol->value.enumerated.item[0]; 6066 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT; 6067 6068 if (sel >= items) 6069 return 0; 6070 6071 codec_dbg(codec, "ca0132_alt_speaker_channels: sel=%d, channels=%s\n", 6072 sel, speaker_channel_cfgs[sel].name); 6073 6074 spec->channel_cfg_val = sel; 6075 6076 if (spec->out_enum_val == SPEAKER_OUT) 6077 ca0132_alt_select_out(codec); 6078 6079 return 1; 6080 } 6081 6082 /* 6083 * Smart Volume output setting control. Three different settings, Normal, 6084 * which takes the value from the smart volume slider. The two others, loud 6085 * and night, disregard the slider value and have uneditable values. 6086 */ 6087 #define NUM_OF_SVM_SETTINGS 3 6088 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" }; 6089 6090 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol, 6091 struct snd_ctl_elem_info *uinfo) 6092 { 6093 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6094 uinfo->count = 1; 6095 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS; 6096 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS) 6097 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1; 6098 strcpy(uinfo->value.enumerated.name, 6099 out_svm_set_enum_str[uinfo->value.enumerated.item]); 6100 return 0; 6101 } 6102 6103 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol, 6104 struct snd_ctl_elem_value *ucontrol) 6105 { 6106 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6107 struct ca0132_spec *spec = codec->spec; 6108 6109 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting; 6110 return 0; 6111 } 6112 6113 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol, 6114 struct snd_ctl_elem_value *ucontrol) 6115 { 6116 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6117 struct ca0132_spec *spec = codec->spec; 6118 int sel = ucontrol->value.enumerated.item[0]; 6119 unsigned int items = NUM_OF_SVM_SETTINGS; 6120 unsigned int idx = SMART_VOLUME - EFFECT_START_NID; 6121 unsigned int tmp; 6122 6123 if (sel >= items) 6124 return 0; 6125 6126 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n", 6127 sel, out_svm_set_enum_str[sel]); 6128 6129 spec->smart_volume_setting = sel; 6130 6131 switch (sel) { 6132 case 0: 6133 tmp = FLOAT_ZERO; 6134 break; 6135 case 1: 6136 tmp = FLOAT_ONE; 6137 break; 6138 case 2: 6139 tmp = FLOAT_TWO; 6140 break; 6141 default: 6142 tmp = FLOAT_ZERO; 6143 break; 6144 } 6145 /* Req 2 is the Smart Volume Setting req. */ 6146 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 6147 ca0132_effects[idx].reqs[2], tmp); 6148 return 1; 6149 } 6150 6151 /* Sound Blaster Z EQ preset controls */ 6152 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol, 6153 struct snd_ctl_elem_info *uinfo) 6154 { 6155 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 6156 6157 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6158 uinfo->count = 1; 6159 uinfo->value.enumerated.items = items; 6160 if (uinfo->value.enumerated.item >= items) 6161 uinfo->value.enumerated.item = items - 1; 6162 strcpy(uinfo->value.enumerated.name, 6163 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name); 6164 return 0; 6165 } 6166 6167 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol, 6168 struct snd_ctl_elem_value *ucontrol) 6169 { 6170 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6171 struct ca0132_spec *spec = codec->spec; 6172 6173 ucontrol->value.enumerated.item[0] = spec->eq_preset_val; 6174 return 0; 6175 } 6176 6177 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol, 6178 struct snd_ctl_elem_value *ucontrol) 6179 { 6180 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6181 struct ca0132_spec *spec = codec->spec; 6182 int i, err = 0; 6183 int sel = ucontrol->value.enumerated.item[0]; 6184 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 6185 6186 if (sel >= items) 6187 return 0; 6188 6189 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel, 6190 ca0132_alt_eq_presets[sel].name); 6191 /* 6192 * Idx 0 is default. 6193 * Default needs to qualify with CrystalVoice state. 6194 */ 6195 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) { 6196 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid, 6197 ca0132_alt_eq_enum.reqs[i], 6198 ca0132_alt_eq_presets[sel].vals[i]); 6199 if (err < 0) 6200 break; 6201 } 6202 6203 if (err >= 0) 6204 spec->eq_preset_val = sel; 6205 6206 return 1; 6207 } 6208 6209 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol, 6210 struct snd_ctl_elem_info *uinfo) 6211 { 6212 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets); 6213 6214 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6215 uinfo->count = 1; 6216 uinfo->value.enumerated.items = items; 6217 if (uinfo->value.enumerated.item >= items) 6218 uinfo->value.enumerated.item = items - 1; 6219 strcpy(uinfo->value.enumerated.name, 6220 ca0132_voicefx_presets[uinfo->value.enumerated.item].name); 6221 return 0; 6222 } 6223 6224 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol, 6225 struct snd_ctl_elem_value *ucontrol) 6226 { 6227 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6228 struct ca0132_spec *spec = codec->spec; 6229 6230 ucontrol->value.enumerated.item[0] = spec->voicefx_val; 6231 return 0; 6232 } 6233 6234 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol, 6235 struct snd_ctl_elem_value *ucontrol) 6236 { 6237 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6238 struct ca0132_spec *spec = codec->spec; 6239 int i, err = 0; 6240 int sel = ucontrol->value.enumerated.item[0]; 6241 6242 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets)) 6243 return 0; 6244 6245 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n", 6246 sel, ca0132_voicefx_presets[sel].name); 6247 6248 /* 6249 * Idx 0 is default. 6250 * Default needs to qualify with CrystalVoice state. 6251 */ 6252 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) { 6253 err = dspio_set_uint_param(codec, ca0132_voicefx.mid, 6254 ca0132_voicefx.reqs[i], 6255 ca0132_voicefx_presets[sel].vals[i]); 6256 if (err < 0) 6257 break; 6258 } 6259 6260 if (err >= 0) { 6261 spec->voicefx_val = sel; 6262 /* enable voice fx */ 6263 ca0132_voicefx_set(codec, (sel ? 1 : 0)); 6264 } 6265 6266 return 1; 6267 } 6268 6269 static int ca0132_switch_get(struct snd_kcontrol *kcontrol, 6270 struct snd_ctl_elem_value *ucontrol) 6271 { 6272 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6273 struct ca0132_spec *spec = codec->spec; 6274 hda_nid_t nid = get_amp_nid(kcontrol); 6275 int ch = get_amp_channels(kcontrol); 6276 long *valp = ucontrol->value.integer.value; 6277 6278 /* vnode */ 6279 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 6280 if (ch & 1) { 6281 *valp = spec->vnode_lswitch[nid - VNODE_START_NID]; 6282 valp++; 6283 } 6284 if (ch & 2) { 6285 *valp = spec->vnode_rswitch[nid - VNODE_START_NID]; 6286 valp++; 6287 } 6288 return 0; 6289 } 6290 6291 /* effects, include PE and CrystalVoice */ 6292 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) { 6293 *valp = spec->effects_switch[nid - EFFECT_START_NID]; 6294 return 0; 6295 } 6296 6297 /* mic boost */ 6298 if (nid == spec->input_pins[0]) { 6299 *valp = spec->cur_mic_boost; 6300 return 0; 6301 } 6302 6303 if (nid == ZXR_HEADPHONE_GAIN) { 6304 *valp = spec->zxr_gain_set; 6305 return 0; 6306 } 6307 6308 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) { 6309 *valp = spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT]; 6310 return 0; 6311 } 6312 6313 if (nid == BASS_REDIRECTION) { 6314 *valp = spec->bass_redirection_val; 6315 return 0; 6316 } 6317 6318 return 0; 6319 } 6320 6321 static int ca0132_switch_put(struct snd_kcontrol *kcontrol, 6322 struct snd_ctl_elem_value *ucontrol) 6323 { 6324 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6325 struct ca0132_spec *spec = codec->spec; 6326 hda_nid_t nid = get_amp_nid(kcontrol); 6327 int ch = get_amp_channels(kcontrol); 6328 long *valp = ucontrol->value.integer.value; 6329 int changed = 1; 6330 6331 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n", 6332 nid, *valp); 6333 6334 snd_hda_power_up(codec); 6335 /* vnode */ 6336 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 6337 if (ch & 1) { 6338 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp; 6339 valp++; 6340 } 6341 if (ch & 2) { 6342 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp; 6343 valp++; 6344 } 6345 changed = ca0132_vnode_switch_set(kcontrol, ucontrol); 6346 goto exit; 6347 } 6348 6349 /* PE */ 6350 if (nid == PLAY_ENHANCEMENT) { 6351 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6352 changed = ca0132_pe_switch_set(codec); 6353 goto exit; 6354 } 6355 6356 /* CrystalVoice */ 6357 if (nid == CRYSTAL_VOICE) { 6358 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6359 changed = ca0132_cvoice_switch_set(codec); 6360 goto exit; 6361 } 6362 6363 /* out and in effects */ 6364 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) || 6365 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) { 6366 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6367 changed = ca0132_effects_set(codec, nid, *valp); 6368 goto exit; 6369 } 6370 6371 /* mic boost */ 6372 if (nid == spec->input_pins[0]) { 6373 spec->cur_mic_boost = *valp; 6374 if (ca0132_use_alt_functions(spec)) { 6375 if (spec->in_enum_val != REAR_LINE_IN) 6376 changed = ca0132_mic_boost_set(codec, *valp); 6377 } else { 6378 /* Mic boost does not apply to Digital Mic */ 6379 if (spec->cur_mic_type != DIGITAL_MIC) 6380 changed = ca0132_mic_boost_set(codec, *valp); 6381 } 6382 6383 goto exit; 6384 } 6385 6386 if (nid == ZXR_HEADPHONE_GAIN) { 6387 spec->zxr_gain_set = *valp; 6388 if (spec->cur_out_type == HEADPHONE_OUT) 6389 changed = zxr_headphone_gain_set(codec, *valp); 6390 else 6391 changed = 0; 6392 6393 goto exit; 6394 } 6395 6396 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) { 6397 spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT] = *valp; 6398 if (spec->cur_out_type == SPEAKER_OUT) 6399 ca0132_alt_set_full_range_speaker(codec); 6400 6401 changed = 0; 6402 } 6403 6404 if (nid == BASS_REDIRECTION) { 6405 spec->bass_redirection_val = *valp; 6406 if (spec->cur_out_type == SPEAKER_OUT) 6407 ca0132_alt_surround_set_bass_redirection(codec, *valp); 6408 6409 changed = 0; 6410 } 6411 6412 exit: 6413 snd_hda_power_down(codec); 6414 return changed; 6415 } 6416 6417 /* 6418 * Volume related 6419 */ 6420 /* 6421 * Sets the internal DSP decibel level to match the DAC for output, and the 6422 * ADC for input. Currently only the SBZ sets dsp capture volume level, and 6423 * all alternative codecs set DSP playback volume. 6424 */ 6425 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid) 6426 { 6427 struct ca0132_spec *spec = codec->spec; 6428 unsigned int dsp_dir; 6429 unsigned int lookup_val; 6430 6431 if (nid == VNID_SPK) 6432 dsp_dir = DSP_VOL_OUT; 6433 else 6434 dsp_dir = DSP_VOL_IN; 6435 6436 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID]; 6437 6438 dspio_set_uint_param(codec, 6439 ca0132_alt_vol_ctls[dsp_dir].mid, 6440 ca0132_alt_vol_ctls[dsp_dir].reqs[0], 6441 float_vol_db_lookup[lookup_val]); 6442 6443 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID]; 6444 6445 dspio_set_uint_param(codec, 6446 ca0132_alt_vol_ctls[dsp_dir].mid, 6447 ca0132_alt_vol_ctls[dsp_dir].reqs[1], 6448 float_vol_db_lookup[lookup_val]); 6449 6450 dspio_set_uint_param(codec, 6451 ca0132_alt_vol_ctls[dsp_dir].mid, 6452 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO); 6453 } 6454 6455 static int ca0132_volume_info(struct snd_kcontrol *kcontrol, 6456 struct snd_ctl_elem_info *uinfo) 6457 { 6458 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6459 struct ca0132_spec *spec = codec->spec; 6460 hda_nid_t nid = get_amp_nid(kcontrol); 6461 int ch = get_amp_channels(kcontrol); 6462 int dir = get_amp_direction(kcontrol); 6463 unsigned long pval; 6464 int err; 6465 6466 switch (nid) { 6467 case VNID_SPK: 6468 /* follow shared_out info */ 6469 nid = spec->shared_out_nid; 6470 mutex_lock(&codec->control_mutex); 6471 pval = kcontrol->private_value; 6472 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6473 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6474 kcontrol->private_value = pval; 6475 mutex_unlock(&codec->control_mutex); 6476 break; 6477 case VNID_MIC: 6478 /* follow shared_mic info */ 6479 nid = spec->shared_mic_nid; 6480 mutex_lock(&codec->control_mutex); 6481 pval = kcontrol->private_value; 6482 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6483 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6484 kcontrol->private_value = pval; 6485 mutex_unlock(&codec->control_mutex); 6486 break; 6487 default: 6488 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6489 } 6490 return err; 6491 } 6492 6493 static int ca0132_volume_get(struct snd_kcontrol *kcontrol, 6494 struct snd_ctl_elem_value *ucontrol) 6495 { 6496 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6497 struct ca0132_spec *spec = codec->spec; 6498 hda_nid_t nid = get_amp_nid(kcontrol); 6499 int ch = get_amp_channels(kcontrol); 6500 long *valp = ucontrol->value.integer.value; 6501 6502 /* store the left and right volume */ 6503 if (ch & 1) { 6504 *valp = spec->vnode_lvol[nid - VNODE_START_NID]; 6505 valp++; 6506 } 6507 if (ch & 2) { 6508 *valp = spec->vnode_rvol[nid - VNODE_START_NID]; 6509 valp++; 6510 } 6511 return 0; 6512 } 6513 6514 static int ca0132_volume_put(struct snd_kcontrol *kcontrol, 6515 struct snd_ctl_elem_value *ucontrol) 6516 { 6517 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6518 struct ca0132_spec *spec = codec->spec; 6519 hda_nid_t nid = get_amp_nid(kcontrol); 6520 int ch = get_amp_channels(kcontrol); 6521 long *valp = ucontrol->value.integer.value; 6522 hda_nid_t shared_nid = 0; 6523 bool effective; 6524 int changed = 1; 6525 6526 /* store the left and right volume */ 6527 if (ch & 1) { 6528 spec->vnode_lvol[nid - VNODE_START_NID] = *valp; 6529 valp++; 6530 } 6531 if (ch & 2) { 6532 spec->vnode_rvol[nid - VNODE_START_NID] = *valp; 6533 valp++; 6534 } 6535 6536 /* if effective conditions, then update hw immediately. */ 6537 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 6538 if (effective) { 6539 int dir = get_amp_direction(kcontrol); 6540 unsigned long pval; 6541 6542 snd_hda_power_up(codec); 6543 mutex_lock(&codec->control_mutex); 6544 pval = kcontrol->private_value; 6545 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 6546 0, dir); 6547 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 6548 kcontrol->private_value = pval; 6549 mutex_unlock(&codec->control_mutex); 6550 snd_hda_power_down(codec); 6551 } 6552 6553 return changed; 6554 } 6555 6556 /* 6557 * This function is the same as the one above, because using an if statement 6558 * inside of the above volume control for the DSP volume would cause too much 6559 * lag. This is a lot more smooth. 6560 */ 6561 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol, 6562 struct snd_ctl_elem_value *ucontrol) 6563 { 6564 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6565 struct ca0132_spec *spec = codec->spec; 6566 hda_nid_t nid = get_amp_nid(kcontrol); 6567 int ch = get_amp_channels(kcontrol); 6568 long *valp = ucontrol->value.integer.value; 6569 hda_nid_t vnid = 0; 6570 int changed; 6571 6572 switch (nid) { 6573 case 0x02: 6574 vnid = VNID_SPK; 6575 break; 6576 case 0x07: 6577 vnid = VNID_MIC; 6578 break; 6579 } 6580 6581 /* store the left and right volume */ 6582 if (ch & 1) { 6583 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp; 6584 valp++; 6585 } 6586 if (ch & 2) { 6587 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp; 6588 valp++; 6589 } 6590 6591 snd_hda_power_up(codec); 6592 ca0132_alt_dsp_volume_put(codec, vnid); 6593 mutex_lock(&codec->control_mutex); 6594 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 6595 mutex_unlock(&codec->control_mutex); 6596 snd_hda_power_down(codec); 6597 6598 return changed; 6599 } 6600 6601 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag, 6602 unsigned int size, unsigned int __user *tlv) 6603 { 6604 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6605 struct ca0132_spec *spec = codec->spec; 6606 hda_nid_t nid = get_amp_nid(kcontrol); 6607 int ch = get_amp_channels(kcontrol); 6608 int dir = get_amp_direction(kcontrol); 6609 unsigned long pval; 6610 int err; 6611 6612 switch (nid) { 6613 case VNID_SPK: 6614 /* follow shared_out tlv */ 6615 nid = spec->shared_out_nid; 6616 mutex_lock(&codec->control_mutex); 6617 pval = kcontrol->private_value; 6618 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6619 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6620 kcontrol->private_value = pval; 6621 mutex_unlock(&codec->control_mutex); 6622 break; 6623 case VNID_MIC: 6624 /* follow shared_mic tlv */ 6625 nid = spec->shared_mic_nid; 6626 mutex_lock(&codec->control_mutex); 6627 pval = kcontrol->private_value; 6628 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6629 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6630 kcontrol->private_value = pval; 6631 mutex_unlock(&codec->control_mutex); 6632 break; 6633 default: 6634 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6635 } 6636 return err; 6637 } 6638 6639 /* Add volume slider control for effect level */ 6640 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid, 6641 const char *pfx, int dir) 6642 { 6643 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6644 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6645 struct snd_kcontrol_new knew = 6646 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 6647 6648 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]); 6649 6650 knew.tlv.c = NULL; 6651 6652 switch (nid) { 6653 case XBASS_XOVER: 6654 knew.info = ca0132_alt_xbass_xover_slider_info; 6655 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 6656 knew.put = ca0132_alt_xbass_xover_slider_put; 6657 break; 6658 default: 6659 knew.info = ca0132_alt_effect_slider_info; 6660 knew.get = ca0132_alt_slider_ctl_get; 6661 knew.put = ca0132_alt_effect_slider_put; 6662 knew.private_value = 6663 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 6664 break; 6665 } 6666 6667 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6668 } 6669 6670 /* 6671 * Added FX: prefix for the alternative codecs, because otherwise the surround 6672 * effect would conflict with the Surround sound volume control. Also seems more 6673 * clear as to what the switches do. Left alone for others. 6674 */ 6675 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid, 6676 const char *pfx, int dir) 6677 { 6678 struct ca0132_spec *spec = codec->spec; 6679 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6680 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6681 struct snd_kcontrol_new knew = 6682 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type); 6683 /* If using alt_controls, add FX: prefix. But, don't add FX: 6684 * prefix to OutFX or InFX enable controls. 6685 */ 6686 if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID)) 6687 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]); 6688 else 6689 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]); 6690 6691 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6692 } 6693 6694 static int add_voicefx(struct hda_codec *codec) 6695 { 6696 struct snd_kcontrol_new knew = 6697 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name, 6698 VOICEFX, 1, 0, HDA_INPUT); 6699 knew.info = ca0132_voicefx_info; 6700 knew.get = ca0132_voicefx_get; 6701 knew.put = ca0132_voicefx_put; 6702 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec)); 6703 } 6704 6705 /* Create the EQ Preset control */ 6706 static int add_ca0132_alt_eq_presets(struct hda_codec *codec) 6707 { 6708 struct snd_kcontrol_new knew = 6709 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name, 6710 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT); 6711 knew.info = ca0132_alt_eq_preset_info; 6712 knew.get = ca0132_alt_eq_preset_get; 6713 knew.put = ca0132_alt_eq_preset_put; 6714 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM, 6715 snd_ctl_new1(&knew, codec)); 6716 } 6717 6718 /* 6719 * Add enumerated control for the three different settings of the smart volume 6720 * output effect. Normal just uses the slider value, and loud and night are 6721 * their own things that ignore that value. 6722 */ 6723 static int ca0132_alt_add_svm_enum(struct hda_codec *codec) 6724 { 6725 struct snd_kcontrol_new knew = 6726 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting", 6727 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT); 6728 knew.info = ca0132_alt_svm_setting_info; 6729 knew.get = ca0132_alt_svm_setting_get; 6730 knew.put = ca0132_alt_svm_setting_put; 6731 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM, 6732 snd_ctl_new1(&knew, codec)); 6733 6734 } 6735 6736 /* 6737 * Create an Output Select enumerated control for codecs with surround 6738 * out capabilities. 6739 */ 6740 static int ca0132_alt_add_output_enum(struct hda_codec *codec) 6741 { 6742 struct snd_kcontrol_new knew = 6743 HDA_CODEC_MUTE_MONO("Output Select", 6744 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT); 6745 knew.info = ca0132_alt_output_select_get_info; 6746 knew.get = ca0132_alt_output_select_get; 6747 knew.put = ca0132_alt_output_select_put; 6748 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM, 6749 snd_ctl_new1(&knew, codec)); 6750 } 6751 6752 /* 6753 * Add a control for selecting channel count on speaker output. Setting this 6754 * allows the DSP to do bass redirection and channel upmixing on surround 6755 * configurations. 6756 */ 6757 static int ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec *codec) 6758 { 6759 struct snd_kcontrol_new knew = 6760 HDA_CODEC_MUTE_MONO("Surround Channel Config", 6761 SPEAKER_CHANNEL_CFG_ENUM, 1, 0, HDA_OUTPUT); 6762 knew.info = ca0132_alt_speaker_channel_cfg_get_info; 6763 knew.get = ca0132_alt_speaker_channel_cfg_get; 6764 knew.put = ca0132_alt_speaker_channel_cfg_put; 6765 return snd_hda_ctl_add(codec, SPEAKER_CHANNEL_CFG_ENUM, 6766 snd_ctl_new1(&knew, codec)); 6767 } 6768 6769 /* 6770 * Full range front stereo and rear surround switches. When these are set to 6771 * full range, the lower frequencies from these channels are no longer 6772 * redirected to the LFE channel. 6773 */ 6774 static int ca0132_alt_add_front_full_range_switch(struct hda_codec *codec) 6775 { 6776 struct snd_kcontrol_new knew = 6777 CA0132_CODEC_MUTE_MONO("Full-Range Front Speakers", 6778 SPEAKER_FULL_RANGE_FRONT, 1, HDA_OUTPUT); 6779 6780 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_FRONT, 6781 snd_ctl_new1(&knew, codec)); 6782 } 6783 6784 static int ca0132_alt_add_rear_full_range_switch(struct hda_codec *codec) 6785 { 6786 struct snd_kcontrol_new knew = 6787 CA0132_CODEC_MUTE_MONO("Full-Range Rear Speakers", 6788 SPEAKER_FULL_RANGE_REAR, 1, HDA_OUTPUT); 6789 6790 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_REAR, 6791 snd_ctl_new1(&knew, codec)); 6792 } 6793 6794 /* 6795 * Bass redirection redirects audio below the crossover frequency to the LFE 6796 * channel on speakers that are set as not being full-range. On configurations 6797 * without an LFE channel, it does nothing. Bass redirection seems to be the 6798 * replacement for X-Bass on configurations with an LFE channel. 6799 */ 6800 static int ca0132_alt_add_bass_redirection_crossover(struct hda_codec *codec) 6801 { 6802 const char *namestr = "Bass Redirection Crossover"; 6803 struct snd_kcontrol_new knew = 6804 HDA_CODEC_VOLUME_MONO(namestr, BASS_REDIRECTION_XOVER, 1, 0, 6805 HDA_OUTPUT); 6806 6807 knew.tlv.c = NULL; 6808 knew.info = ca0132_alt_xbass_xover_slider_info; 6809 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 6810 knew.put = ca0132_alt_xbass_xover_slider_put; 6811 6812 return snd_hda_ctl_add(codec, BASS_REDIRECTION_XOVER, 6813 snd_ctl_new1(&knew, codec)); 6814 } 6815 6816 static int ca0132_alt_add_bass_redirection_switch(struct hda_codec *codec) 6817 { 6818 const char *namestr = "Bass Redirection"; 6819 struct snd_kcontrol_new knew = 6820 CA0132_CODEC_MUTE_MONO(namestr, BASS_REDIRECTION, 1, 6821 HDA_OUTPUT); 6822 6823 return snd_hda_ctl_add(codec, BASS_REDIRECTION, 6824 snd_ctl_new1(&knew, codec)); 6825 } 6826 6827 /* 6828 * Create an Input Source enumerated control for the alternate ca0132 codecs 6829 * because the front microphone has no auto-detect, and Line-in has to be set 6830 * somehow. 6831 */ 6832 static int ca0132_alt_add_input_enum(struct hda_codec *codec) 6833 { 6834 struct snd_kcontrol_new knew = 6835 HDA_CODEC_MUTE_MONO("Input Source", 6836 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT); 6837 knew.info = ca0132_alt_input_source_info; 6838 knew.get = ca0132_alt_input_source_get; 6839 knew.put = ca0132_alt_input_source_put; 6840 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM, 6841 snd_ctl_new1(&knew, codec)); 6842 } 6843 6844 /* 6845 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds 6846 * more control than the original mic boost, which is either full 30dB or off. 6847 */ 6848 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec) 6849 { 6850 struct snd_kcontrol_new knew = 6851 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch", 6852 MIC_BOOST_ENUM, 1, 0, HDA_INPUT); 6853 knew.info = ca0132_alt_mic_boost_info; 6854 knew.get = ca0132_alt_mic_boost_get; 6855 knew.put = ca0132_alt_mic_boost_put; 6856 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM, 6857 snd_ctl_new1(&knew, codec)); 6858 6859 } 6860 6861 /* 6862 * Add headphone gain enumerated control for the AE-5. This switches between 6863 * three modes, low, medium, and high. When non-headphone outputs are selected, 6864 * it is automatically set to high. This is the same behavior as Windows. 6865 */ 6866 static int ae5_add_headphone_gain_enum(struct hda_codec *codec) 6867 { 6868 struct snd_kcontrol_new knew = 6869 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain", 6870 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT); 6871 knew.info = ae5_headphone_gain_info; 6872 knew.get = ae5_headphone_gain_get; 6873 knew.put = ae5_headphone_gain_put; 6874 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM, 6875 snd_ctl_new1(&knew, codec)); 6876 } 6877 6878 /* 6879 * Add sound filter enumerated control for the AE-5. This adds three different 6880 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've 6881 * read into it, it changes the DAC's interpolation filter. 6882 */ 6883 static int ae5_add_sound_filter_enum(struct hda_codec *codec) 6884 { 6885 struct snd_kcontrol_new knew = 6886 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter", 6887 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT); 6888 knew.info = ae5_sound_filter_info; 6889 knew.get = ae5_sound_filter_get; 6890 knew.put = ae5_sound_filter_put; 6891 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM, 6892 snd_ctl_new1(&knew, codec)); 6893 } 6894 6895 static int zxr_add_headphone_gain_switch(struct hda_codec *codec) 6896 { 6897 struct snd_kcontrol_new knew = 6898 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain", 6899 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT); 6900 6901 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN, 6902 snd_ctl_new1(&knew, codec)); 6903 } 6904 6905 /* 6906 * Need to create follower controls for the alternate codecs that have surround 6907 * capabilities. 6908 */ 6909 static const char * const ca0132_alt_follower_pfxs[] = { 6910 "Front", "Surround", "Center", "LFE", NULL, 6911 }; 6912 6913 /* 6914 * Also need special channel map, because the default one is incorrect. 6915 * I think this has to do with the pin for rear surround being 0x11, 6916 * and the center/lfe being 0x10. Usually the pin order is the opposite. 6917 */ 6918 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = { 6919 { .channels = 2, 6920 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } }, 6921 { .channels = 4, 6922 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6923 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6924 { .channels = 6, 6925 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6926 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE, 6927 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6928 { } 6929 }; 6930 6931 /* Add the correct chmap for streams with 6 channels. */ 6932 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec) 6933 { 6934 int err = 0; 6935 struct hda_pcm *pcm; 6936 6937 list_for_each_entry(pcm, &codec->pcm_list_head, list) { 6938 struct hda_pcm_stream *hinfo = 6939 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 6940 struct snd_pcm_chmap *chmap; 6941 const struct snd_pcm_chmap_elem *elem; 6942 6943 elem = ca0132_alt_chmaps; 6944 if (hinfo->channels_max == 6) { 6945 err = snd_pcm_add_chmap_ctls(pcm->pcm, 6946 SNDRV_PCM_STREAM_PLAYBACK, 6947 elem, hinfo->channels_max, 0, &chmap); 6948 if (err < 0) 6949 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!"); 6950 } 6951 } 6952 } 6953 6954 /* 6955 * When changing Node IDs for Mixer Controls below, make sure to update 6956 * Node IDs in ca0132_config() as well. 6957 */ 6958 static const struct snd_kcontrol_new ca0132_mixer[] = { 6959 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT), 6960 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT), 6961 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 6962 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6963 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT), 6964 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT), 6965 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6966 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6967 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch", 6968 0x12, 1, HDA_INPUT), 6969 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch", 6970 VNID_HP_SEL, 1, HDA_OUTPUT), 6971 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch", 6972 VNID_AMIC1_SEL, 1, HDA_INPUT), 6973 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6974 VNID_HP_ASEL, 1, HDA_OUTPUT), 6975 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch", 6976 VNID_AMIC1_ASEL, 1, HDA_INPUT), 6977 { } /* end */ 6978 }; 6979 6980 /* 6981 * Desktop specific control mixer. Removes auto-detect for mic, and adds 6982 * surround controls. Also sets both the Front Playback and Capture Volume 6983 * controls to alt so they set the DSP's decibel level. 6984 */ 6985 static const struct snd_kcontrol_new desktop_mixer[] = { 6986 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 6987 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 6988 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 6989 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 6990 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 6991 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 6992 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 6993 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 6994 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT), 6995 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6996 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6997 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6998 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6999 VNID_HP_ASEL, 1, HDA_OUTPUT), 7000 { } /* end */ 7001 }; 7002 7003 /* 7004 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture 7005 * because it doesn't set decibel levels for the DSP for capture. 7006 */ 7007 static const struct snd_kcontrol_new r3di_mixer[] = { 7008 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 7009 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 7010 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 7011 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 7012 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 7013 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 7014 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 7015 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 7016 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 7017 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 7018 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 7019 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 7020 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 7021 VNID_HP_ASEL, 1, HDA_OUTPUT), 7022 { } /* end */ 7023 }; 7024 7025 static int ca0132_build_controls(struct hda_codec *codec) 7026 { 7027 struct ca0132_spec *spec = codec->spec; 7028 int i, num_fx, num_sliders; 7029 int err = 0; 7030 7031 /* Add Mixer controls */ 7032 for (i = 0; i < spec->num_mixers; i++) { 7033 err = snd_hda_add_new_ctls(codec, spec->mixers[i]); 7034 if (err < 0) 7035 return err; 7036 } 7037 /* Setup vmaster with surround followers for desktop ca0132 devices */ 7038 if (ca0132_use_alt_functions(spec)) { 7039 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT, 7040 spec->tlv); 7041 snd_hda_add_vmaster(codec, "Master Playback Volume", 7042 spec->tlv, ca0132_alt_follower_pfxs, 7043 "Playback Volume"); 7044 err = __snd_hda_add_vmaster(codec, "Master Playback Switch", 7045 NULL, ca0132_alt_follower_pfxs, 7046 "Playback Switch", 7047 true, &spec->vmaster_mute.sw_kctl); 7048 if (err < 0) 7049 return err; 7050 } 7051 7052 /* Add in and out effects controls. 7053 * VoiceFX, PE and CrystalVoice are added separately. 7054 */ 7055 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 7056 for (i = 0; i < num_fx; i++) { 7057 /* Desktop cards break if Echo Cancellation is used. */ 7058 if (ca0132_use_pci_mmio(spec)) { 7059 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID + 7060 OUT_EFFECTS_COUNT)) 7061 continue; 7062 } 7063 7064 err = add_fx_switch(codec, ca0132_effects[i].nid, 7065 ca0132_effects[i].name, 7066 ca0132_effects[i].direct); 7067 if (err < 0) 7068 return err; 7069 } 7070 /* 7071 * If codec has use_alt_controls set to true, add effect level sliders, 7072 * EQ presets, and Smart Volume presets. Also, change names to add FX 7073 * prefix, and change PlayEnhancement and CrystalVoice to match. 7074 */ 7075 if (ca0132_use_alt_controls(spec)) { 7076 err = ca0132_alt_add_svm_enum(codec); 7077 if (err < 0) 7078 return err; 7079 7080 err = add_ca0132_alt_eq_presets(codec); 7081 if (err < 0) 7082 return err; 7083 7084 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 7085 "Enable OutFX", 0); 7086 if (err < 0) 7087 return err; 7088 7089 err = add_fx_switch(codec, CRYSTAL_VOICE, 7090 "Enable InFX", 1); 7091 if (err < 0) 7092 return err; 7093 7094 num_sliders = OUT_EFFECTS_COUNT - 1; 7095 for (i = 0; i < num_sliders; i++) { 7096 err = ca0132_alt_add_effect_slider(codec, 7097 ca0132_effects[i].nid, 7098 ca0132_effects[i].name, 7099 ca0132_effects[i].direct); 7100 if (err < 0) 7101 return err; 7102 } 7103 7104 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER, 7105 "X-Bass Crossover", EFX_DIR_OUT); 7106 7107 if (err < 0) 7108 return err; 7109 } else { 7110 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 7111 "PlayEnhancement", 0); 7112 if (err < 0) 7113 return err; 7114 7115 err = add_fx_switch(codec, CRYSTAL_VOICE, 7116 "CrystalVoice", 1); 7117 if (err < 0) 7118 return err; 7119 } 7120 err = add_voicefx(codec); 7121 if (err < 0) 7122 return err; 7123 7124 /* 7125 * If the codec uses alt_functions, you need the enumerated controls 7126 * to select the new outputs and inputs, plus add the new mic boost 7127 * setting control. 7128 */ 7129 if (ca0132_use_alt_functions(spec)) { 7130 err = ca0132_alt_add_output_enum(codec); 7131 if (err < 0) 7132 return err; 7133 err = ca0132_alt_add_speaker_channel_cfg_enum(codec); 7134 if (err < 0) 7135 return err; 7136 err = ca0132_alt_add_front_full_range_switch(codec); 7137 if (err < 0) 7138 return err; 7139 err = ca0132_alt_add_rear_full_range_switch(codec); 7140 if (err < 0) 7141 return err; 7142 err = ca0132_alt_add_bass_redirection_crossover(codec); 7143 if (err < 0) 7144 return err; 7145 err = ca0132_alt_add_bass_redirection_switch(codec); 7146 if (err < 0) 7147 return err; 7148 err = ca0132_alt_add_mic_boost_enum(codec); 7149 if (err < 0) 7150 return err; 7151 /* 7152 * ZxR only has microphone input, there is no front panel 7153 * header on the card, and aux-in is handled by the DBPro board. 7154 */ 7155 if (ca0132_quirk(spec) != QUIRK_ZXR) { 7156 err = ca0132_alt_add_input_enum(codec); 7157 if (err < 0) 7158 return err; 7159 } 7160 } 7161 7162 switch (ca0132_quirk(spec)) { 7163 case QUIRK_AE5: 7164 case QUIRK_AE7: 7165 err = ae5_add_headphone_gain_enum(codec); 7166 if (err < 0) 7167 return err; 7168 err = ae5_add_sound_filter_enum(codec); 7169 if (err < 0) 7170 return err; 7171 break; 7172 case QUIRK_ZXR: 7173 err = zxr_add_headphone_gain_switch(codec); 7174 if (err < 0) 7175 return err; 7176 break; 7177 default: 7178 break; 7179 } 7180 7181 #ifdef ENABLE_TUNING_CONTROLS 7182 add_tuning_ctls(codec); 7183 #endif 7184 7185 err = snd_hda_jack_add_kctls(codec, &spec->autocfg); 7186 if (err < 0) 7187 return err; 7188 7189 if (spec->dig_out) { 7190 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 7191 spec->dig_out); 7192 if (err < 0) 7193 return err; 7194 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout); 7195 if (err < 0) 7196 return err; 7197 /* spec->multiout.share_spdif = 1; */ 7198 } 7199 7200 if (spec->dig_in) { 7201 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 7202 if (err < 0) 7203 return err; 7204 } 7205 7206 if (ca0132_use_alt_functions(spec)) 7207 ca0132_alt_add_chmap_ctls(codec); 7208 7209 return 0; 7210 } 7211 7212 static int dbpro_build_controls(struct hda_codec *codec) 7213 { 7214 struct ca0132_spec *spec = codec->spec; 7215 int err = 0; 7216 7217 if (spec->dig_out) { 7218 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 7219 spec->dig_out); 7220 if (err < 0) 7221 return err; 7222 } 7223 7224 if (spec->dig_in) { 7225 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 7226 if (err < 0) 7227 return err; 7228 } 7229 7230 return 0; 7231 } 7232 7233 /* 7234 * PCM 7235 */ 7236 static const struct hda_pcm_stream ca0132_pcm_analog_playback = { 7237 .substreams = 1, 7238 .channels_min = 2, 7239 .channels_max = 6, 7240 .ops = { 7241 .prepare = ca0132_playback_pcm_prepare, 7242 .cleanup = ca0132_playback_pcm_cleanup, 7243 .get_delay = ca0132_playback_pcm_delay, 7244 }, 7245 }; 7246 7247 static const struct hda_pcm_stream ca0132_pcm_analog_capture = { 7248 .substreams = 1, 7249 .channels_min = 2, 7250 .channels_max = 2, 7251 .ops = { 7252 .prepare = ca0132_capture_pcm_prepare, 7253 .cleanup = ca0132_capture_pcm_cleanup, 7254 .get_delay = ca0132_capture_pcm_delay, 7255 }, 7256 }; 7257 7258 static const struct hda_pcm_stream ca0132_pcm_digital_playback = { 7259 .substreams = 1, 7260 .channels_min = 2, 7261 .channels_max = 2, 7262 .ops = { 7263 .open = ca0132_dig_playback_pcm_open, 7264 .close = ca0132_dig_playback_pcm_close, 7265 .prepare = ca0132_dig_playback_pcm_prepare, 7266 .cleanup = ca0132_dig_playback_pcm_cleanup 7267 }, 7268 }; 7269 7270 static const struct hda_pcm_stream ca0132_pcm_digital_capture = { 7271 .substreams = 1, 7272 .channels_min = 2, 7273 .channels_max = 2, 7274 }; 7275 7276 static int ca0132_build_pcms(struct hda_codec *codec) 7277 { 7278 struct ca0132_spec *spec = codec->spec; 7279 struct hda_pcm *info; 7280 7281 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog"); 7282 if (!info) 7283 return -ENOMEM; 7284 if (ca0132_use_alt_functions(spec)) { 7285 info->own_chmap = true; 7286 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap 7287 = ca0132_alt_chmaps; 7288 } 7289 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback; 7290 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0]; 7291 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max = 7292 spec->multiout.max_channels; 7293 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7294 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7295 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 7296 7297 /* With the DSP enabled, desktops don't use this ADC. */ 7298 if (!ca0132_use_alt_functions(spec)) { 7299 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2"); 7300 if (!info) 7301 return -ENOMEM; 7302 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7303 ca0132_pcm_analog_capture; 7304 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7305 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1]; 7306 } 7307 7308 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear"); 7309 if (!info) 7310 return -ENOMEM; 7311 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7312 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7313 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2]; 7314 7315 if (!spec->dig_out && !spec->dig_in) 7316 return 0; 7317 7318 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 7319 if (!info) 7320 return -ENOMEM; 7321 info->pcm_type = HDA_PCM_TYPE_SPDIF; 7322 if (spec->dig_out) { 7323 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 7324 ca0132_pcm_digital_playback; 7325 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 7326 } 7327 if (spec->dig_in) { 7328 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7329 ca0132_pcm_digital_capture; 7330 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 7331 } 7332 7333 return 0; 7334 } 7335 7336 static int dbpro_build_pcms(struct hda_codec *codec) 7337 { 7338 struct ca0132_spec *spec = codec->spec; 7339 struct hda_pcm *info; 7340 7341 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog"); 7342 if (!info) 7343 return -ENOMEM; 7344 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7345 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7346 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 7347 7348 7349 if (!spec->dig_out && !spec->dig_in) 7350 return 0; 7351 7352 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 7353 if (!info) 7354 return -ENOMEM; 7355 info->pcm_type = HDA_PCM_TYPE_SPDIF; 7356 if (spec->dig_out) { 7357 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 7358 ca0132_pcm_digital_playback; 7359 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 7360 } 7361 if (spec->dig_in) { 7362 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7363 ca0132_pcm_digital_capture; 7364 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 7365 } 7366 7367 return 0; 7368 } 7369 7370 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac) 7371 { 7372 if (pin) { 7373 snd_hda_set_pin_ctl(codec, pin, PIN_HP); 7374 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 7375 snd_hda_codec_write(codec, pin, 0, 7376 AC_VERB_SET_AMP_GAIN_MUTE, 7377 AMP_OUT_UNMUTE); 7378 } 7379 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP)) 7380 snd_hda_codec_write(codec, dac, 0, 7381 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO); 7382 } 7383 7384 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc) 7385 { 7386 if (pin) { 7387 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80); 7388 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP) 7389 snd_hda_codec_write(codec, pin, 0, 7390 AC_VERB_SET_AMP_GAIN_MUTE, 7391 AMP_IN_UNMUTE(0)); 7392 } 7393 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) { 7394 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE, 7395 AMP_IN_UNMUTE(0)); 7396 7397 /* init to 0 dB and unmute. */ 7398 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 7399 HDA_AMP_VOLMASK, 0x5a); 7400 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 7401 HDA_AMP_MUTE, 0); 7402 } 7403 } 7404 7405 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir) 7406 { 7407 unsigned int caps; 7408 7409 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ? 7410 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP); 7411 snd_hda_override_amp_caps(codec, nid, dir, caps); 7412 } 7413 7414 /* 7415 * Switch between Digital built-in mic and analog mic. 7416 */ 7417 static void ca0132_set_dmic(struct hda_codec *codec, int enable) 7418 { 7419 struct ca0132_spec *spec = codec->spec; 7420 unsigned int tmp; 7421 u8 val; 7422 unsigned int oldval; 7423 7424 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable); 7425 7426 oldval = stop_mic1(codec); 7427 ca0132_set_vipsource(codec, 0); 7428 if (enable) { 7429 /* set DMic input as 2-ch */ 7430 tmp = FLOAT_TWO; 7431 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7432 7433 val = spec->dmic_ctl; 7434 val |= 0x80; 7435 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7436 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7437 7438 if (!(spec->dmic_ctl & 0x20)) 7439 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1); 7440 } else { 7441 /* set AMic input as mono */ 7442 tmp = FLOAT_ONE; 7443 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7444 7445 val = spec->dmic_ctl; 7446 /* clear bit7 and bit5 to disable dmic */ 7447 val &= 0x5f; 7448 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7449 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7450 7451 if (!(spec->dmic_ctl & 0x20)) 7452 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0); 7453 } 7454 ca0132_set_vipsource(codec, 1); 7455 resume_mic1(codec, oldval); 7456 } 7457 7458 /* 7459 * Initialization for Digital Mic. 7460 */ 7461 static void ca0132_init_dmic(struct hda_codec *codec) 7462 { 7463 struct ca0132_spec *spec = codec->spec; 7464 u8 val; 7465 7466 /* Setup Digital Mic here, but don't enable. 7467 * Enable based on jack detect. 7468 */ 7469 7470 /* MCLK uses MPIO1, set to enable. 7471 * Bit 2-0: MPIO select 7472 * Bit 3: set to disable 7473 * Bit 7-4: reserved 7474 */ 7475 val = 0x01; 7476 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7477 VENDOR_CHIPIO_DMIC_MCLK_SET, val); 7478 7479 /* Data1 uses MPIO3. Data2 not use 7480 * Bit 2-0: Data1 MPIO select 7481 * Bit 3: set disable Data1 7482 * Bit 6-4: Data2 MPIO select 7483 * Bit 7: set disable Data2 7484 */ 7485 val = 0x83; 7486 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7487 VENDOR_CHIPIO_DMIC_PIN_SET, val); 7488 7489 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first. 7490 * Bit 3-0: Channel mask 7491 * Bit 4: set for 48KHz, clear for 32KHz 7492 * Bit 5: mode 7493 * Bit 6: set to select Data2, clear for Data1 7494 * Bit 7: set to enable DMic, clear for AMic 7495 */ 7496 if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4) 7497 val = 0x33; 7498 else 7499 val = 0x23; 7500 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */ 7501 spec->dmic_ctl = val; 7502 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7503 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7504 } 7505 7506 /* 7507 * Initialization for Analog Mic 2 7508 */ 7509 static void ca0132_init_analog_mic2(struct hda_codec *codec) 7510 { 7511 struct ca0132_spec *spec = codec->spec; 7512 7513 mutex_lock(&spec->chipio_mutex); 7514 7515 chipio_8051_write_exram_no_mutex(codec, 0x1920, 0x00); 7516 chipio_8051_write_exram_no_mutex(codec, 0x192d, 0x00); 7517 7518 mutex_unlock(&spec->chipio_mutex); 7519 } 7520 7521 static void ca0132_refresh_widget_caps(struct hda_codec *codec) 7522 { 7523 struct ca0132_spec *spec = codec->spec; 7524 int i; 7525 7526 codec_dbg(codec, "ca0132_refresh_widget_caps.\n"); 7527 snd_hda_codec_update_widgets(codec); 7528 7529 for (i = 0; i < spec->multiout.num_dacs; i++) 7530 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT); 7531 7532 for (i = 0; i < spec->num_outputs; i++) 7533 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT); 7534 7535 for (i = 0; i < spec->num_inputs; i++) { 7536 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT); 7537 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT); 7538 } 7539 } 7540 7541 7542 /* If there is an active channel for some reason, find it and free it. */ 7543 static void ca0132_alt_free_active_dma_channels(struct hda_codec *codec) 7544 { 7545 unsigned int i, tmp; 7546 int status; 7547 7548 /* Read active DSPDMAC channel register. */ 7549 status = chipio_read(codec, DSPDMAC_CHNLSTART_MODULE_OFFSET, &tmp); 7550 if (status >= 0) { 7551 /* AND against 0xfff to get the active channel bits. */ 7552 tmp = tmp & 0xfff; 7553 7554 /* If there are no active channels, nothing to free. */ 7555 if (!tmp) 7556 return; 7557 } else { 7558 codec_dbg(codec, "%s: Failed to read active DSP DMA channel register.\n", 7559 __func__); 7560 return; 7561 } 7562 7563 /* 7564 * Check each DSP DMA channel for activity, and if the channel is 7565 * active, free it. 7566 */ 7567 for (i = 0; i < DSPDMAC_DMA_CFG_CHANNEL_COUNT; i++) { 7568 if (dsp_is_dma_active(codec, i)) { 7569 status = dspio_free_dma_chan(codec, i); 7570 if (status < 0) 7571 codec_dbg(codec, "%s: Failed to free active DSP DMA channel %d.\n", 7572 __func__, i); 7573 } 7574 } 7575 } 7576 7577 /* 7578 * In the case of CT_EXTENSIONS_ENABLE being set to 1, and the DSP being in 7579 * use, audio is no longer routed directly to the DAC/ADC from the HDA stream. 7580 * Instead, audio is now routed through the DSP's DMA controllers, which 7581 * the DSP is tasked with setting up itself. Through debugging, it seems the 7582 * cause of most of the no-audio on startup issues were due to improperly 7583 * configured DSP DMA channels. 7584 * 7585 * Normally, the DSP configures these the first time an HDA audio stream is 7586 * started post DSP firmware download. That is why creating a 'dummy' stream 7587 * worked in fixing the audio in some cases. This works most of the time, but 7588 * sometimes if a stream is started/stopped before the DSP can setup the DMA 7589 * configuration registers, it ends up in a broken state. Issues can also 7590 * arise if streams are started in an unusual order, i.e the audio output dma 7591 * channel being sandwiched between the mic1 and mic2 dma channels. 7592 * 7593 * The solution to this is to make sure that the DSP has no DMA channels 7594 * in use post DSP firmware download, and then to manually start each default 7595 * DSP stream that uses the DMA channels. These are 0x0c, the audio output 7596 * stream, 0x03, analog mic 1, and 0x04, analog mic 2. 7597 */ 7598 static void ca0132_alt_start_dsp_audio_streams(struct hda_codec *codec) 7599 { 7600 const unsigned int dsp_dma_stream_ids[] = { 0x0c, 0x03, 0x04 }; 7601 struct ca0132_spec *spec = codec->spec; 7602 unsigned int i, tmp; 7603 7604 /* 7605 * Check if any of the default streams are active, and if they are, 7606 * stop them. 7607 */ 7608 mutex_lock(&spec->chipio_mutex); 7609 7610 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) { 7611 chipio_get_stream_control(codec, dsp_dma_stream_ids[i], &tmp); 7612 7613 if (tmp) { 7614 chipio_set_stream_control(codec, 7615 dsp_dma_stream_ids[i], 0); 7616 } 7617 } 7618 7619 mutex_unlock(&spec->chipio_mutex); 7620 7621 /* 7622 * If all DSP streams are inactive, there should be no active DSP DMA 7623 * channels. Check and make sure this is the case, and if it isn't, 7624 * free any active channels. 7625 */ 7626 ca0132_alt_free_active_dma_channels(codec); 7627 7628 mutex_lock(&spec->chipio_mutex); 7629 7630 /* Make sure stream 0x0c is six channels. */ 7631 chipio_set_stream_channels(codec, 0x0c, 6); 7632 7633 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) { 7634 chipio_set_stream_control(codec, 7635 dsp_dma_stream_ids[i], 1); 7636 7637 /* Give the DSP some time to setup the DMA channel. */ 7638 msleep(75); 7639 } 7640 7641 mutex_unlock(&spec->chipio_mutex); 7642 } 7643 7644 /* 7645 * The region of ChipIO memory from 0x190000-0x1903fc is a sort of 'audio 7646 * router', where each entry represents a 48khz audio channel, with a format 7647 * of an 8-bit destination, an 8-bit source, and an unknown 2-bit number 7648 * value. The 2-bit number value is seemingly 0 if inactive, 1 if active, 7649 * and 3 if it's using Sample Rate Converter ports. 7650 * An example is: 7651 * 0x0001f8c0 7652 * In this case, f8 is the destination, and c0 is the source. The number value 7653 * is 1. 7654 * This region of memory is normally managed internally by the 8051, where 7655 * the region of exram memory from 0x1477-0x1575 has each byte represent an 7656 * entry within the 0x190000 range, and when a range of entries is in use, the 7657 * ending value is overwritten with 0xff. 7658 * 0x1578 in exram is a table of 0x25 entries, corresponding to the ChipIO 7659 * streamID's, where each entry is a starting 0x190000 port offset. 7660 * 0x159d in exram is the same as 0x1578, except it contains the ending port 7661 * offset for the corresponding streamID. 7662 * 7663 * On certain cards, such as the SBZ/ZxR/AE7, these are originally setup by 7664 * the 8051, then manually overwritten to remap the ports to work with the 7665 * new DACs. 7666 * 7667 * Currently known portID's: 7668 * 0x00-0x1f: HDA audio stream input/output ports. 7669 * 0x80-0xbf: Sample rate converter input/outputs. Only valid ports seem to 7670 * have the lower-nibble set to 0x1, 0x2, and 0x9. 7671 * 0xc0-0xdf: DSP DMA input/output ports. Dynamically assigned. 7672 * 0xe0-0xff: DAC/ADC audio input/output ports. 7673 * 7674 * Currently known streamID's: 7675 * 0x03: Mic1 ADC to DSP. 7676 * 0x04: Mic2 ADC to DSP. 7677 * 0x05: HDA node 0x02 audio stream to DSP. 7678 * 0x0f: DSP Mic exit to HDA node 0x07. 7679 * 0x0c: DSP processed audio to DACs. 7680 * 0x14: DAC0, front L/R. 7681 * 7682 * It is possible to route the HDA audio streams directly to the DAC and 7683 * bypass the DSP entirely, with the only downside being that since the DSP 7684 * does volume control, the only volume control you'll get is through PCM on 7685 * the PC side, in the same way volume is handled for optical out. This may be 7686 * useful for debugging. 7687 */ 7688 static void chipio_remap_stream(struct hda_codec *codec, 7689 const struct chipio_stream_remap_data *remap_data) 7690 { 7691 unsigned int i, stream_offset; 7692 7693 /* Get the starting port for the stream to be remapped. */ 7694 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id, 7695 &stream_offset); 7696 7697 /* 7698 * Check if the stream's port value is 0xff, because the 8051 may not 7699 * have gotten around to setting up the stream yet. Wait until it's 7700 * setup to remap it's ports. 7701 */ 7702 if (stream_offset == 0xff) { 7703 for (i = 0; i < 5; i++) { 7704 msleep(25); 7705 7706 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id, 7707 &stream_offset); 7708 7709 if (stream_offset != 0xff) 7710 break; 7711 } 7712 } 7713 7714 if (stream_offset == 0xff) { 7715 codec_info(codec, "%s: Stream 0x%02x ports aren't allocated, remap failed!\n", 7716 __func__, remap_data->stream_id); 7717 return; 7718 } 7719 7720 /* Offset isn't in bytes, its in 32-bit words, so multiply it by 4. */ 7721 stream_offset *= 0x04; 7722 stream_offset += 0x190000; 7723 7724 for (i = 0; i < remap_data->count; i++) { 7725 chipio_write_no_mutex(codec, 7726 stream_offset + remap_data->offset[i], 7727 remap_data->value[i]); 7728 } 7729 7730 /* Update stream map configuration. */ 7731 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 7732 } 7733 7734 /* 7735 * Default speaker tuning values setup for alternative codecs. 7736 */ 7737 static const unsigned int sbz_default_delay_values[] = { 7738 /* Non-zero values are floating point 0.000198. */ 7739 0x394f9e38, 0x394f9e38, 0x00000000, 0x00000000, 0x00000000, 0x00000000 7740 }; 7741 7742 static const unsigned int zxr_default_delay_values[] = { 7743 /* Non-zero values are floating point 0.000220. */ 7744 0x00000000, 0x00000000, 0x3966afcd, 0x3966afcd, 0x3966afcd, 0x3966afcd 7745 }; 7746 7747 static const unsigned int ae5_default_delay_values[] = { 7748 /* Non-zero values are floating point 0.000100. */ 7749 0x00000000, 0x00000000, 0x38d1b717, 0x38d1b717, 0x38d1b717, 0x38d1b717 7750 }; 7751 7752 /* 7753 * If we never change these, probably only need them on initialization. 7754 */ 7755 static void ca0132_alt_init_speaker_tuning(struct hda_codec *codec) 7756 { 7757 struct ca0132_spec *spec = codec->spec; 7758 unsigned int i, tmp, start_req, end_req; 7759 const unsigned int *values; 7760 7761 switch (ca0132_quirk(spec)) { 7762 case QUIRK_SBZ: 7763 values = sbz_default_delay_values; 7764 break; 7765 case QUIRK_ZXR: 7766 values = zxr_default_delay_values; 7767 break; 7768 case QUIRK_AE5: 7769 case QUIRK_AE7: 7770 values = ae5_default_delay_values; 7771 break; 7772 default: 7773 values = sbz_default_delay_values; 7774 break; 7775 } 7776 7777 tmp = FLOAT_ZERO; 7778 dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_ENABLE_CENTER_EQ, tmp); 7779 7780 start_req = SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL; 7781 end_req = SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL; 7782 for (i = start_req; i < end_req + 1; i++) 7783 dspio_set_uint_param(codec, 0x96, i, tmp); 7784 7785 start_req = SPEAKER_TUNING_FRONT_LEFT_INVERT; 7786 end_req = SPEAKER_TUNING_REAR_RIGHT_INVERT; 7787 for (i = start_req; i < end_req + 1; i++) 7788 dspio_set_uint_param(codec, 0x96, i, tmp); 7789 7790 7791 for (i = 0; i < 6; i++) 7792 dspio_set_uint_param(codec, 0x96, 7793 SPEAKER_TUNING_FRONT_LEFT_DELAY + i, values[i]); 7794 } 7795 7796 /* 7797 * Initialize mic for non-chromebook ca0132 implementations. 7798 */ 7799 static void ca0132_alt_init_analog_mics(struct hda_codec *codec) 7800 { 7801 struct ca0132_spec *spec = codec->spec; 7802 unsigned int tmp; 7803 7804 /* Mic 1 Setup */ 7805 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7806 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7807 if (ca0132_quirk(spec) == QUIRK_R3DI) { 7808 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 7809 tmp = FLOAT_ONE; 7810 } else 7811 tmp = FLOAT_THREE; 7812 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7813 7814 /* Mic 2 setup (not present on desktop cards) */ 7815 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000); 7816 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000); 7817 if (ca0132_quirk(spec) == QUIRK_R3DI) 7818 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 7819 tmp = FLOAT_ZERO; 7820 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 7821 } 7822 7823 /* 7824 * Sets the source of stream 0x14 to connpointID 0x48, and the destination 7825 * connpointID to 0x91. If this isn't done, the destination is 0x71, and 7826 * you get no sound. I'm guessing this has to do with the Sound Blaster Z 7827 * having an updated DAC, which changes the destination to that DAC. 7828 */ 7829 static void sbz_connect_streams(struct hda_codec *codec) 7830 { 7831 struct ca0132_spec *spec = codec->spec; 7832 7833 mutex_lock(&spec->chipio_mutex); 7834 7835 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n"); 7836 7837 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */ 7838 chipio_write_no_mutex(codec, 0x18a020, 0x00000043); 7839 7840 /* Setup stream 0x14 with it's source and destination points */ 7841 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91); 7842 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000); 7843 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000); 7844 chipio_set_stream_channels(codec, 0x14, 2); 7845 chipio_set_stream_control(codec, 0x14, 1); 7846 7847 codec_dbg(codec, "Connect Streams exited, mutex released.\n"); 7848 7849 mutex_unlock(&spec->chipio_mutex); 7850 } 7851 7852 /* 7853 * Write data through ChipIO to setup proper stream destinations. 7854 * Not sure how it exactly works, but it seems to direct data 7855 * to different destinations. Example is f8 to c0, e0 to c0. 7856 * All I know is, if you don't set these, you get no sound. 7857 */ 7858 static void sbz_chipio_startup_data(struct hda_codec *codec) 7859 { 7860 const struct chipio_stream_remap_data *dsp_out_remap_data; 7861 struct ca0132_spec *spec = codec->spec; 7862 7863 mutex_lock(&spec->chipio_mutex); 7864 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n"); 7865 7866 /* Remap DAC0's output ports. */ 7867 chipio_remap_stream(codec, &stream_remap_data[0]); 7868 7869 /* Remap DSP audio output stream ports. */ 7870 switch (ca0132_quirk(spec)) { 7871 case QUIRK_SBZ: 7872 dsp_out_remap_data = &stream_remap_data[1]; 7873 break; 7874 7875 case QUIRK_ZXR: 7876 dsp_out_remap_data = &stream_remap_data[2]; 7877 break; 7878 7879 default: 7880 dsp_out_remap_data = NULL; 7881 break; 7882 } 7883 7884 if (dsp_out_remap_data) 7885 chipio_remap_stream(codec, dsp_out_remap_data); 7886 7887 codec_dbg(codec, "Startup Data exited, mutex released.\n"); 7888 mutex_unlock(&spec->chipio_mutex); 7889 } 7890 7891 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec) 7892 { 7893 struct ca0132_spec *spec = codec->spec; 7894 unsigned int tmp; 7895 7896 chipio_set_stream_control(codec, 0x03, 0); 7897 chipio_set_stream_control(codec, 0x04, 0); 7898 7899 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7900 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7901 7902 tmp = FLOAT_THREE; 7903 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7904 7905 chipio_set_stream_control(codec, 0x03, 1); 7906 chipio_set_stream_control(codec, 0x04, 1); 7907 7908 switch (ca0132_quirk(spec)) { 7909 case QUIRK_SBZ: 7910 chipio_write(codec, 0x18b098, 0x0000000c); 7911 chipio_write(codec, 0x18b09C, 0x0000000c); 7912 break; 7913 case QUIRK_AE5: 7914 chipio_write(codec, 0x18b098, 0x0000000c); 7915 chipio_write(codec, 0x18b09c, 0x0000004c); 7916 break; 7917 default: 7918 break; 7919 } 7920 } 7921 7922 static void ae5_post_dsp_register_set(struct hda_codec *codec) 7923 { 7924 struct ca0132_spec *spec = codec->spec; 7925 7926 chipio_8051_write_direct(codec, 0x93, 0x10); 7927 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); 7928 7929 writeb(0xff, spec->mem_base + 0x304); 7930 writeb(0xff, spec->mem_base + 0x304); 7931 writeb(0xff, spec->mem_base + 0x304); 7932 writeb(0xff, spec->mem_base + 0x304); 7933 writeb(0x00, spec->mem_base + 0x100); 7934 writeb(0xff, spec->mem_base + 0x304); 7935 writeb(0x00, spec->mem_base + 0x100); 7936 writeb(0xff, spec->mem_base + 0x304); 7937 writeb(0x00, spec->mem_base + 0x100); 7938 writeb(0xff, spec->mem_base + 0x304); 7939 writeb(0x00, spec->mem_base + 0x100); 7940 writeb(0xff, spec->mem_base + 0x304); 7941 7942 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f); 7943 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 7944 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7945 } 7946 7947 static void ae5_post_dsp_param_setup(struct hda_codec *codec) 7948 { 7949 /* 7950 * Param3 in the 8051's memory is represented by the ascii string 'mch' 7951 * which seems to be 'multichannel'. This is also mentioned in the 7952 * AE-5's registry values in Windows. 7953 */ 7954 chipio_set_control_param(codec, 3, 0); 7955 /* 7956 * I believe ASI is 'audio serial interface' and that it's used to 7957 * change colors on the external LED strip connected to the AE-5. 7958 */ 7959 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); 7960 7961 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); 7962 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 7963 7964 chipio_8051_write_exram(codec, 0xfa92, 0x22); 7965 } 7966 7967 static void ae5_post_dsp_pll_setup(struct hda_codec *codec) 7968 { 7969 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8); 7970 chipio_8051_write_pll_pmu(codec, 0x45, 0xcc); 7971 chipio_8051_write_pll_pmu(codec, 0x40, 0xcb); 7972 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7); 7973 chipio_8051_write_pll_pmu(codec, 0x51, 0x8d); 7974 } 7975 7976 static void ae5_post_dsp_stream_setup(struct hda_codec *codec) 7977 { 7978 struct ca0132_spec *spec = codec->spec; 7979 7980 mutex_lock(&spec->chipio_mutex); 7981 7982 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); 7983 7984 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); 7985 7986 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0); 7987 7988 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0); 7989 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 7990 chipio_set_stream_channels(codec, 0x18, 6); 7991 chipio_set_stream_control(codec, 0x18, 1); 7992 7993 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); 7994 7995 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7); 7996 7997 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80); 7998 7999 mutex_unlock(&spec->chipio_mutex); 8000 } 8001 8002 static void ae5_post_dsp_startup_data(struct hda_codec *codec) 8003 { 8004 struct ca0132_spec *spec = codec->spec; 8005 8006 mutex_lock(&spec->chipio_mutex); 8007 8008 chipio_write_no_mutex(codec, 0x189000, 0x0001f101); 8009 chipio_write_no_mutex(codec, 0x189004, 0x0001f101); 8010 chipio_write_no_mutex(codec, 0x189024, 0x00014004); 8011 chipio_write_no_mutex(codec, 0x189028, 0x0002000f); 8012 8013 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 8014 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 8015 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12); 8016 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00); 8017 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48); 8018 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 8019 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8020 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8021 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8022 ca0113_mmio_gpio_set(codec, 0, true); 8023 ca0113_mmio_gpio_set(codec, 1, true); 8024 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80); 8025 8026 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012); 8027 8028 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8029 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8030 8031 mutex_unlock(&spec->chipio_mutex); 8032 } 8033 8034 static void ae7_post_dsp_setup_ports(struct hda_codec *codec) 8035 { 8036 struct ca0132_spec *spec = codec->spec; 8037 8038 mutex_lock(&spec->chipio_mutex); 8039 8040 /* Seems to share the same port remapping as the SBZ. */ 8041 chipio_remap_stream(codec, &stream_remap_data[1]); 8042 8043 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 8044 ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40); 8045 ca0113_mmio_command_set(codec, 0x48, 0x17, 0x00); 8046 ca0113_mmio_command_set(codec, 0x48, 0x19, 0x00); 8047 ca0113_mmio_command_set(codec, 0x48, 0x11, 0xff); 8048 ca0113_mmio_command_set(codec, 0x48, 0x12, 0xff); 8049 ca0113_mmio_command_set(codec, 0x48, 0x13, 0xff); 8050 ca0113_mmio_command_set(codec, 0x48, 0x14, 0x7f); 8051 8052 mutex_unlock(&spec->chipio_mutex); 8053 } 8054 8055 static void ae7_post_dsp_asi_stream_setup(struct hda_codec *codec) 8056 { 8057 struct ca0132_spec *spec = codec->spec; 8058 8059 mutex_lock(&spec->chipio_mutex); 8060 8061 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); 8062 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 8063 8064 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); 8065 8066 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00); 8067 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0); 8068 8069 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 8070 chipio_set_stream_channels(codec, 0x18, 6); 8071 chipio_set_stream_control(codec, 0x18, 1); 8072 8073 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); 8074 8075 mutex_unlock(&spec->chipio_mutex); 8076 } 8077 8078 static void ae7_post_dsp_pll_setup(struct hda_codec *codec) 8079 { 8080 static const unsigned int addr[] = { 8081 0x41, 0x45, 0x40, 0x43, 0x51 8082 }; 8083 static const unsigned int data[] = { 8084 0xc8, 0xcc, 0xcb, 0xc7, 0x8d 8085 }; 8086 unsigned int i; 8087 8088 for (i = 0; i < ARRAY_SIZE(addr); i++) 8089 chipio_8051_write_pll_pmu_no_mutex(codec, addr[i], data[i]); 8090 } 8091 8092 static void ae7_post_dsp_asi_setup_ports(struct hda_codec *codec) 8093 { 8094 struct ca0132_spec *spec = codec->spec; 8095 static const unsigned int target[] = { 8096 0x0b, 0x04, 0x06, 0x0a, 0x0c, 0x11, 0x12, 0x13, 0x14 8097 }; 8098 static const unsigned int data[] = { 8099 0x12, 0x00, 0x48, 0x05, 0x5f, 0xff, 0xff, 0xff, 0x7f 8100 }; 8101 unsigned int i; 8102 8103 mutex_lock(&spec->chipio_mutex); 8104 8105 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7); 8106 8107 chipio_write_no_mutex(codec, 0x189000, 0x0001f101); 8108 chipio_write_no_mutex(codec, 0x189004, 0x0001f101); 8109 chipio_write_no_mutex(codec, 0x189024, 0x00014004); 8110 chipio_write_no_mutex(codec, 0x189028, 0x0002000f); 8111 8112 ae7_post_dsp_pll_setup(codec); 8113 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 8114 8115 for (i = 0; i < ARRAY_SIZE(target); i++) 8116 ca0113_mmio_command_set(codec, 0x48, target[i], data[i]); 8117 8118 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8119 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8120 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8121 8122 chipio_set_stream_source_dest(codec, 0x21, 0x64, 0x56); 8123 chipio_set_stream_channels(codec, 0x21, 2); 8124 chipio_set_conn_rate_no_mutex(codec, 0x56, SR_8_000); 8125 8126 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_NODE_ID, 0x09); 8127 /* 8128 * In the 8051's memory, this param is referred to as 'n2sid', which I 8129 * believe is 'node to streamID'. It seems to be a way to assign a 8130 * stream to a given HDA node. 8131 */ 8132 chipio_set_control_param_no_mutex(codec, 0x20, 0x21); 8133 8134 chipio_write_no_mutex(codec, 0x18b038, 0x00000088); 8135 8136 /* 8137 * Now, at this point on Windows, an actual stream is setup and 8138 * seemingly sends data to the HDA node 0x09, which is the digital 8139 * audio input node. This is left out here, because obviously I don't 8140 * know what data is being sent. Interestingly, the AE-5 seems to go 8141 * through the motions of getting here and never actually takes this 8142 * step, but the AE-7 does. 8143 */ 8144 8145 ca0113_mmio_gpio_set(codec, 0, 1); 8146 ca0113_mmio_gpio_set(codec, 1, 1); 8147 8148 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8149 chipio_write_no_mutex(codec, 0x18b03c, 0x00000000); 8150 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8151 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8152 8153 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00); 8154 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0); 8155 8156 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 8157 chipio_set_stream_channels(codec, 0x18, 6); 8158 8159 /* 8160 * Runs again, this has been repeated a few times, but I'm just 8161 * following what the Windows driver does. 8162 */ 8163 ae7_post_dsp_pll_setup(codec); 8164 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 8165 8166 mutex_unlock(&spec->chipio_mutex); 8167 } 8168 8169 /* 8170 * The Windows driver has commands that seem to setup ASI, which I believe to 8171 * be some sort of audio serial interface. My current speculation is that it's 8172 * related to communicating with the new DAC. 8173 */ 8174 static void ae7_post_dsp_asi_setup(struct hda_codec *codec) 8175 { 8176 chipio_8051_write_direct(codec, 0x93, 0x10); 8177 8178 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); 8179 8180 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8181 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8182 8183 chipio_set_control_param(codec, 3, 3); 8184 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); 8185 8186 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); 8187 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 8188 snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00); 8189 8190 chipio_8051_write_exram(codec, 0xfa92, 0x22); 8191 8192 ae7_post_dsp_pll_setup(codec); 8193 ae7_post_dsp_asi_stream_setup(codec); 8194 8195 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7); 8196 8197 ae7_post_dsp_asi_setup_ports(codec); 8198 } 8199 8200 /* 8201 * Setup default parameters for DSP 8202 */ 8203 static void ca0132_setup_defaults(struct hda_codec *codec) 8204 { 8205 struct ca0132_spec *spec = codec->spec; 8206 unsigned int tmp; 8207 int num_fx; 8208 int idx, i; 8209 8210 if (spec->dsp_state != DSP_DOWNLOADED) 8211 return; 8212 8213 /* out, in effects + voicefx */ 8214 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8215 for (idx = 0; idx < num_fx; idx++) { 8216 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8217 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 8218 ca0132_effects[idx].reqs[i], 8219 ca0132_effects[idx].def_vals[i]); 8220 } 8221 } 8222 8223 /*remove DSP headroom*/ 8224 tmp = FLOAT_ZERO; 8225 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8226 8227 /*set speaker EQ bypass attenuation*/ 8228 dspio_set_uint_param(codec, 0x8f, 0x01, tmp); 8229 8230 /* set AMic1 and AMic2 as mono mic */ 8231 tmp = FLOAT_ONE; 8232 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 8233 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 8234 8235 /* set AMic1 as CrystalVoice input */ 8236 tmp = FLOAT_ONE; 8237 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 8238 8239 /* set WUH source */ 8240 tmp = FLOAT_TWO; 8241 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8242 } 8243 8244 /* 8245 * Setup default parameters for Recon3D/Recon3Di DSP. 8246 */ 8247 8248 static void r3d_setup_defaults(struct hda_codec *codec) 8249 { 8250 struct ca0132_spec *spec = codec->spec; 8251 unsigned int tmp; 8252 int num_fx; 8253 int idx, i; 8254 8255 if (spec->dsp_state != DSP_DOWNLOADED) 8256 return; 8257 8258 ca0132_alt_init_analog_mics(codec); 8259 ca0132_alt_start_dsp_audio_streams(codec); 8260 8261 /*remove DSP headroom*/ 8262 tmp = FLOAT_ZERO; 8263 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8264 8265 /* set WUH source */ 8266 tmp = FLOAT_TWO; 8267 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8268 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8269 8270 /* Set speaker source? */ 8271 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8272 8273 if (ca0132_quirk(spec) == QUIRK_R3DI) 8274 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED); 8275 8276 /* Disable mute on Center/LFE. */ 8277 if (ca0132_quirk(spec) == QUIRK_R3D) { 8278 ca0113_mmio_gpio_set(codec, 2, false); 8279 ca0113_mmio_gpio_set(codec, 4, true); 8280 } 8281 8282 /* Setup effect defaults */ 8283 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8284 for (idx = 0; idx < num_fx; idx++) { 8285 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8286 dspio_set_uint_param(codec, 8287 ca0132_effects[idx].mid, 8288 ca0132_effects[idx].reqs[i], 8289 ca0132_effects[idx].def_vals[i]); 8290 } 8291 } 8292 } 8293 8294 /* 8295 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on 8296 * than the Chromebook setup. 8297 */ 8298 static void sbz_setup_defaults(struct hda_codec *codec) 8299 { 8300 struct ca0132_spec *spec = codec->spec; 8301 unsigned int tmp; 8302 int num_fx; 8303 int idx, i; 8304 8305 if (spec->dsp_state != DSP_DOWNLOADED) 8306 return; 8307 8308 ca0132_alt_init_analog_mics(codec); 8309 ca0132_alt_start_dsp_audio_streams(codec); 8310 sbz_connect_streams(codec); 8311 sbz_chipio_startup_data(codec); 8312 8313 /* 8314 * Sets internal input loopback to off, used to have a switch to 8315 * enable input loopback, but turned out to be way too buggy. 8316 */ 8317 tmp = FLOAT_ONE; 8318 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8319 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8320 8321 /*remove DSP headroom*/ 8322 tmp = FLOAT_ZERO; 8323 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8324 8325 /* set WUH source */ 8326 tmp = FLOAT_TWO; 8327 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8328 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8329 8330 /* Set speaker source? */ 8331 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8332 8333 ca0132_alt_dsp_initial_mic_setup(codec); 8334 8335 /* out, in effects + voicefx */ 8336 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8337 for (idx = 0; idx < num_fx; idx++) { 8338 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8339 dspio_set_uint_param(codec, 8340 ca0132_effects[idx].mid, 8341 ca0132_effects[idx].reqs[i], 8342 ca0132_effects[idx].def_vals[i]); 8343 } 8344 } 8345 8346 ca0132_alt_init_speaker_tuning(codec); 8347 } 8348 8349 /* 8350 * Setup default parameters for the Sound BlasterX AE-5 DSP. 8351 */ 8352 static void ae5_setup_defaults(struct hda_codec *codec) 8353 { 8354 struct ca0132_spec *spec = codec->spec; 8355 unsigned int tmp; 8356 int num_fx; 8357 int idx, i; 8358 8359 if (spec->dsp_state != DSP_DOWNLOADED) 8360 return; 8361 8362 ca0132_alt_init_analog_mics(codec); 8363 ca0132_alt_start_dsp_audio_streams(codec); 8364 8365 /* New, unknown SCP req's */ 8366 tmp = FLOAT_ZERO; 8367 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 8368 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 8369 dspio_set_uint_param(codec, 0x80, 0x0d, tmp); 8370 dspio_set_uint_param(codec, 0x80, 0x0e, tmp); 8371 8372 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8373 ca0113_mmio_gpio_set(codec, 0, false); 8374 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 8375 8376 /* Internal loopback off */ 8377 tmp = FLOAT_ONE; 8378 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8379 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8380 8381 /*remove DSP headroom*/ 8382 tmp = FLOAT_ZERO; 8383 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8384 8385 /* set WUH source */ 8386 tmp = FLOAT_TWO; 8387 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8388 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8389 8390 /* Set speaker source? */ 8391 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8392 8393 ca0132_alt_dsp_initial_mic_setup(codec); 8394 ae5_post_dsp_register_set(codec); 8395 ae5_post_dsp_param_setup(codec); 8396 ae5_post_dsp_pll_setup(codec); 8397 ae5_post_dsp_stream_setup(codec); 8398 ae5_post_dsp_startup_data(codec); 8399 8400 /* out, in effects + voicefx */ 8401 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8402 for (idx = 0; idx < num_fx; idx++) { 8403 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8404 dspio_set_uint_param(codec, 8405 ca0132_effects[idx].mid, 8406 ca0132_effects[idx].reqs[i], 8407 ca0132_effects[idx].def_vals[i]); 8408 } 8409 } 8410 8411 ca0132_alt_init_speaker_tuning(codec); 8412 } 8413 8414 /* 8415 * Setup default parameters for the Sound Blaster AE-7 DSP. 8416 */ 8417 static void ae7_setup_defaults(struct hda_codec *codec) 8418 { 8419 struct ca0132_spec *spec = codec->spec; 8420 unsigned int tmp; 8421 int num_fx; 8422 int idx, i; 8423 8424 if (spec->dsp_state != DSP_DOWNLOADED) 8425 return; 8426 8427 ca0132_alt_init_analog_mics(codec); 8428 ca0132_alt_start_dsp_audio_streams(codec); 8429 ae7_post_dsp_setup_ports(codec); 8430 8431 tmp = FLOAT_ZERO; 8432 dspio_set_uint_param(codec, 0x96, 8433 SPEAKER_TUNING_FRONT_LEFT_INVERT, tmp); 8434 dspio_set_uint_param(codec, 0x96, 8435 SPEAKER_TUNING_FRONT_RIGHT_INVERT, tmp); 8436 8437 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8438 8439 /* New, unknown SCP req's */ 8440 dspio_set_uint_param(codec, 0x80, 0x0d, tmp); 8441 dspio_set_uint_param(codec, 0x80, 0x0e, tmp); 8442 8443 ca0113_mmio_gpio_set(codec, 0, false); 8444 8445 /* Internal loopback off */ 8446 tmp = FLOAT_ONE; 8447 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8448 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8449 8450 /*remove DSP headroom*/ 8451 tmp = FLOAT_ZERO; 8452 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8453 8454 /* set WUH source */ 8455 tmp = FLOAT_TWO; 8456 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8457 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8458 8459 /* Set speaker source? */ 8460 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8461 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 8462 8463 /* 8464 * This is the second time we've called this, but this is seemingly 8465 * what Windows does. 8466 */ 8467 ca0132_alt_init_analog_mics(codec); 8468 8469 ae7_post_dsp_asi_setup(codec); 8470 8471 /* 8472 * Not sure why, but these are both set to 1. They're only set to 0 8473 * upon shutdown. 8474 */ 8475 ca0113_mmio_gpio_set(codec, 0, true); 8476 ca0113_mmio_gpio_set(codec, 1, true); 8477 8478 /* Volume control related. */ 8479 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x04); 8480 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x04); 8481 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x80); 8482 8483 /* out, in effects + voicefx */ 8484 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8485 for (idx = 0; idx < num_fx; idx++) { 8486 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8487 dspio_set_uint_param(codec, 8488 ca0132_effects[idx].mid, 8489 ca0132_effects[idx].reqs[i], 8490 ca0132_effects[idx].def_vals[i]); 8491 } 8492 } 8493 8494 ca0132_alt_init_speaker_tuning(codec); 8495 } 8496 8497 /* 8498 * Initialization of flags in chip 8499 */ 8500 static void ca0132_init_flags(struct hda_codec *codec) 8501 { 8502 struct ca0132_spec *spec = codec->spec; 8503 8504 if (ca0132_use_alt_functions(spec)) { 8505 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1); 8506 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1); 8507 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1); 8508 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1); 8509 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1); 8510 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8511 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0); 8512 chipio_set_control_flag(codec, 8513 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 8514 chipio_set_control_flag(codec, 8515 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1); 8516 } else { 8517 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8518 chipio_set_control_flag(codec, 8519 CONTROL_FLAG_PORT_A_COMMON_MODE, 0); 8520 chipio_set_control_flag(codec, 8521 CONTROL_FLAG_PORT_D_COMMON_MODE, 0); 8522 chipio_set_control_flag(codec, 8523 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0); 8524 chipio_set_control_flag(codec, 8525 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 8526 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1); 8527 } 8528 } 8529 8530 /* 8531 * Initialization of parameters in chip 8532 */ 8533 static void ca0132_init_params(struct hda_codec *codec) 8534 { 8535 struct ca0132_spec *spec = codec->spec; 8536 8537 if (ca0132_use_alt_functions(spec)) { 8538 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8539 chipio_set_conn_rate(codec, 0x0B, SR_48_000); 8540 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0); 8541 chipio_set_control_param(codec, 0, 0); 8542 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 8543 } 8544 8545 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6); 8546 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6); 8547 } 8548 8549 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k) 8550 { 8551 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k); 8552 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k); 8553 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k); 8554 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k); 8555 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k); 8556 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k); 8557 8558 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 8559 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 8560 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8561 } 8562 8563 static bool ca0132_download_dsp_images(struct hda_codec *codec) 8564 { 8565 bool dsp_loaded = false; 8566 struct ca0132_spec *spec = codec->spec; 8567 const struct dsp_image_seg *dsp_os_image; 8568 const struct firmware *fw_entry = NULL; 8569 /* 8570 * Alternate firmwares for different variants. The Recon3Di apparently 8571 * can use the default firmware, but I'll leave the option in case 8572 * it needs it again. 8573 */ 8574 switch (ca0132_quirk(spec)) { 8575 case QUIRK_SBZ: 8576 case QUIRK_R3D: 8577 case QUIRK_AE5: 8578 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE, 8579 codec->card->dev) != 0) 8580 codec_dbg(codec, "Desktop firmware not found."); 8581 else 8582 codec_dbg(codec, "Desktop firmware selected."); 8583 break; 8584 case QUIRK_R3DI: 8585 if (request_firmware(&fw_entry, R3DI_EFX_FILE, 8586 codec->card->dev) != 0) 8587 codec_dbg(codec, "Recon3Di alt firmware not detected."); 8588 else 8589 codec_dbg(codec, "Recon3Di firmware selected."); 8590 break; 8591 default: 8592 break; 8593 } 8594 /* 8595 * Use default ctefx.bin if no alt firmware is detected, or if none 8596 * exists for your particular codec. 8597 */ 8598 if (!fw_entry) { 8599 codec_dbg(codec, "Default firmware selected."); 8600 if (request_firmware(&fw_entry, EFX_FILE, 8601 codec->card->dev) != 0) 8602 return false; 8603 } 8604 8605 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data); 8606 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) { 8607 codec_err(codec, "ca0132 DSP load image failed\n"); 8608 goto exit_download; 8609 } 8610 8611 dsp_loaded = dspload_wait_loaded(codec); 8612 8613 exit_download: 8614 release_firmware(fw_entry); 8615 8616 return dsp_loaded; 8617 } 8618 8619 static void ca0132_download_dsp(struct hda_codec *codec) 8620 { 8621 struct ca0132_spec *spec = codec->spec; 8622 8623 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP 8624 return; /* NOP */ 8625 #endif 8626 8627 if (spec->dsp_state == DSP_DOWNLOAD_FAILED) 8628 return; /* don't retry failures */ 8629 8630 chipio_enable_clocks(codec); 8631 if (spec->dsp_state != DSP_DOWNLOADED) { 8632 spec->dsp_state = DSP_DOWNLOADING; 8633 8634 if (!ca0132_download_dsp_images(codec)) 8635 spec->dsp_state = DSP_DOWNLOAD_FAILED; 8636 else 8637 spec->dsp_state = DSP_DOWNLOADED; 8638 } 8639 8640 /* For codecs using alt functions, this is already done earlier */ 8641 if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec)) 8642 ca0132_set_dsp_msr(codec, true); 8643 } 8644 8645 static void ca0132_process_dsp_response(struct hda_codec *codec, 8646 struct hda_jack_callback *callback) 8647 { 8648 struct ca0132_spec *spec = codec->spec; 8649 8650 codec_dbg(codec, "ca0132_process_dsp_response\n"); 8651 snd_hda_power_up_pm(codec); 8652 if (spec->wait_scp) { 8653 if (dspio_get_response_data(codec) >= 0) 8654 spec->wait_scp = 0; 8655 } 8656 8657 dspio_clear_response_queue(codec); 8658 snd_hda_power_down_pm(codec); 8659 } 8660 8661 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 8662 { 8663 struct ca0132_spec *spec = codec->spec; 8664 struct hda_jack_tbl *tbl; 8665 8666 /* Delay enabling the HP amp, to let the mic-detection 8667 * state machine run. 8668 */ 8669 tbl = snd_hda_jack_tbl_get(codec, cb->nid); 8670 if (tbl) 8671 tbl->block_report = 1; 8672 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500)); 8673 } 8674 8675 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 8676 { 8677 struct ca0132_spec *spec = codec->spec; 8678 8679 if (ca0132_use_alt_functions(spec)) 8680 ca0132_alt_select_in(codec); 8681 else 8682 ca0132_select_mic(codec); 8683 } 8684 8685 static void ca0132_setup_unsol(struct hda_codec *codec) 8686 { 8687 struct ca0132_spec *spec = codec->spec; 8688 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback); 8689 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1, 8690 amic_callback); 8691 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP, 8692 ca0132_process_dsp_response); 8693 /* Front headphone jack detection */ 8694 if (ca0132_use_alt_functions(spec)) 8695 snd_hda_jack_detect_enable_callback(codec, 8696 spec->unsol_tag_front_hp, hp_callback); 8697 } 8698 8699 /* 8700 * Verbs tables. 8701 */ 8702 8703 /* Sends before DSP download. */ 8704 static const struct hda_verb ca0132_base_init_verbs[] = { 8705 /*enable ct extension*/ 8706 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1}, 8707 {} 8708 }; 8709 8710 /* Send at exit. */ 8711 static const struct hda_verb ca0132_base_exit_verbs[] = { 8712 /*set afg to D3*/ 8713 {0x01, AC_VERB_SET_POWER_STATE, 0x03}, 8714 /*disable ct extension*/ 8715 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0}, 8716 {} 8717 }; 8718 8719 /* Other verbs tables. Sends after DSP download. */ 8720 8721 static const struct hda_verb ca0132_init_verbs0[] = { 8722 /* chip init verbs */ 8723 {0x15, 0x70D, 0xF0}, 8724 {0x15, 0x70E, 0xFE}, 8725 {0x15, 0x707, 0x75}, 8726 {0x15, 0x707, 0xD3}, 8727 {0x15, 0x707, 0x09}, 8728 {0x15, 0x707, 0x53}, 8729 {0x15, 0x707, 0xD4}, 8730 {0x15, 0x707, 0xEF}, 8731 {0x15, 0x707, 0x75}, 8732 {0x15, 0x707, 0xD3}, 8733 {0x15, 0x707, 0x09}, 8734 {0x15, 0x707, 0x02}, 8735 {0x15, 0x707, 0x37}, 8736 {0x15, 0x707, 0x78}, 8737 {0x15, 0x53C, 0xCE}, 8738 {0x15, 0x575, 0xC9}, 8739 {0x15, 0x53D, 0xCE}, 8740 {0x15, 0x5B7, 0xC9}, 8741 {0x15, 0x70D, 0xE8}, 8742 {0x15, 0x70E, 0xFE}, 8743 {0x15, 0x707, 0x02}, 8744 {0x15, 0x707, 0x68}, 8745 {0x15, 0x707, 0x62}, 8746 {0x15, 0x53A, 0xCE}, 8747 {0x15, 0x546, 0xC9}, 8748 {0x15, 0x53B, 0xCE}, 8749 {0x15, 0x5E8, 0xC9}, 8750 {} 8751 }; 8752 8753 /* Extra init verbs for desktop cards. */ 8754 static const struct hda_verb ca0132_init_verbs1[] = { 8755 {0x15, 0x70D, 0x20}, 8756 {0x15, 0x70E, 0x19}, 8757 {0x15, 0x707, 0x00}, 8758 {0x15, 0x539, 0xCE}, 8759 {0x15, 0x546, 0xC9}, 8760 {0x15, 0x70D, 0xB7}, 8761 {0x15, 0x70E, 0x09}, 8762 {0x15, 0x707, 0x10}, 8763 {0x15, 0x70D, 0xAF}, 8764 {0x15, 0x70E, 0x09}, 8765 {0x15, 0x707, 0x01}, 8766 {0x15, 0x707, 0x05}, 8767 {0x15, 0x70D, 0x73}, 8768 {0x15, 0x70E, 0x09}, 8769 {0x15, 0x707, 0x14}, 8770 {0x15, 0x6FF, 0xC4}, 8771 {} 8772 }; 8773 8774 static void ca0132_init_chip(struct hda_codec *codec) 8775 { 8776 struct ca0132_spec *spec = codec->spec; 8777 int num_fx; 8778 int i; 8779 unsigned int on; 8780 8781 mutex_init(&spec->chipio_mutex); 8782 8783 /* 8784 * The Windows driver always does this upon startup, which seems to 8785 * clear out any previous configuration. This should help issues where 8786 * a boot into Windows prior to a boot into Linux breaks things. Also, 8787 * Windows always sends the reset twice. 8788 */ 8789 if (ca0132_use_alt_functions(spec)) { 8790 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8791 chipio_write_no_mutex(codec, 0x18b0a4, 0x000000c2); 8792 8793 snd_hda_codec_write(codec, codec->core.afg, 0, 8794 AC_VERB_SET_CODEC_RESET, 0); 8795 snd_hda_codec_write(codec, codec->core.afg, 0, 8796 AC_VERB_SET_CODEC_RESET, 0); 8797 } 8798 8799 spec->cur_out_type = SPEAKER_OUT; 8800 if (!ca0132_use_alt_functions(spec)) 8801 spec->cur_mic_type = DIGITAL_MIC; 8802 else 8803 spec->cur_mic_type = REAR_MIC; 8804 8805 spec->cur_mic_boost = 0; 8806 8807 for (i = 0; i < VNODES_COUNT; i++) { 8808 spec->vnode_lvol[i] = 0x5a; 8809 spec->vnode_rvol[i] = 0x5a; 8810 spec->vnode_lswitch[i] = 0; 8811 spec->vnode_rswitch[i] = 0; 8812 } 8813 8814 /* 8815 * Default states for effects are in ca0132_effects[]. 8816 */ 8817 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 8818 for (i = 0; i < num_fx; i++) { 8819 on = (unsigned int)ca0132_effects[i].reqs[0]; 8820 spec->effects_switch[i] = on ? 1 : 0; 8821 } 8822 /* 8823 * Sets defaults for the effect slider controls, only for alternative 8824 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz. 8825 */ 8826 if (ca0132_use_alt_controls(spec)) { 8827 /* Set speakers to default to full range. */ 8828 spec->speaker_range_val[0] = 1; 8829 spec->speaker_range_val[1] = 1; 8830 8831 spec->xbass_xover_freq = 8; 8832 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++) 8833 spec->fx_ctl_val[i] = effect_slider_defaults[i]; 8834 8835 spec->bass_redirect_xover_freq = 8; 8836 } 8837 8838 spec->voicefx_val = 0; 8839 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1; 8840 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0; 8841 8842 /* 8843 * The ZxR doesn't have a front panel header, and it's line-in is on 8844 * the daughter board. So, there is no input enum control, and we need 8845 * to make sure that spec->in_enum_val is set properly. 8846 */ 8847 if (ca0132_quirk(spec) == QUIRK_ZXR) 8848 spec->in_enum_val = REAR_MIC; 8849 8850 #ifdef ENABLE_TUNING_CONTROLS 8851 ca0132_init_tuning_defaults(codec); 8852 #endif 8853 } 8854 8855 /* 8856 * Recon3Di exit specific commands. 8857 */ 8858 /* prevents popping noise on shutdown */ 8859 static void r3di_gpio_shutdown(struct hda_codec *codec) 8860 { 8861 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00); 8862 } 8863 8864 /* 8865 * Sound Blaster Z exit specific commands. 8866 */ 8867 static void sbz_region2_exit(struct hda_codec *codec) 8868 { 8869 struct ca0132_spec *spec = codec->spec; 8870 unsigned int i; 8871 8872 for (i = 0; i < 4; i++) 8873 writeb(0x0, spec->mem_base + 0x100); 8874 for (i = 0; i < 8; i++) 8875 writeb(0xb3, spec->mem_base + 0x304); 8876 8877 ca0113_mmio_gpio_set(codec, 0, false); 8878 ca0113_mmio_gpio_set(codec, 1, false); 8879 ca0113_mmio_gpio_set(codec, 4, true); 8880 ca0113_mmio_gpio_set(codec, 5, false); 8881 ca0113_mmio_gpio_set(codec, 7, false); 8882 } 8883 8884 static void sbz_set_pin_ctl_default(struct hda_codec *codec) 8885 { 8886 static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13}; 8887 unsigned int i; 8888 8889 snd_hda_codec_write(codec, 0x11, 0, 8890 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40); 8891 8892 for (i = 0; i < ARRAY_SIZE(pins); i++) 8893 snd_hda_codec_write(codec, pins[i], 0, 8894 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00); 8895 } 8896 8897 static void ca0132_clear_unsolicited(struct hda_codec *codec) 8898 { 8899 static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13}; 8900 unsigned int i; 8901 8902 for (i = 0; i < ARRAY_SIZE(pins); i++) { 8903 snd_hda_codec_write(codec, pins[i], 0, 8904 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00); 8905 } 8906 } 8907 8908 /* On shutdown, sends commands in sets of three */ 8909 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir, 8910 int mask, int data) 8911 { 8912 if (dir >= 0) 8913 snd_hda_codec_write(codec, 0x01, 0, 8914 AC_VERB_SET_GPIO_DIRECTION, dir); 8915 if (mask >= 0) 8916 snd_hda_codec_write(codec, 0x01, 0, 8917 AC_VERB_SET_GPIO_MASK, mask); 8918 8919 if (data >= 0) 8920 snd_hda_codec_write(codec, 0x01, 0, 8921 AC_VERB_SET_GPIO_DATA, data); 8922 } 8923 8924 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec) 8925 { 8926 static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01}; 8927 unsigned int i; 8928 8929 for (i = 0; i < ARRAY_SIZE(pins); i++) 8930 snd_hda_codec_write(codec, pins[i], 0, 8931 AC_VERB_SET_POWER_STATE, 0x03); 8932 } 8933 8934 static void sbz_exit_chip(struct hda_codec *codec) 8935 { 8936 chipio_set_stream_control(codec, 0x03, 0); 8937 chipio_set_stream_control(codec, 0x04, 0); 8938 8939 /* Mess with GPIO */ 8940 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1); 8941 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05); 8942 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01); 8943 8944 chipio_set_stream_control(codec, 0x14, 0); 8945 chipio_set_stream_control(codec, 0x0C, 0); 8946 8947 chipio_set_conn_rate(codec, 0x41, SR_192_000); 8948 chipio_set_conn_rate(codec, 0x91, SR_192_000); 8949 8950 chipio_write(codec, 0x18a020, 0x00000083); 8951 8952 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03); 8953 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07); 8954 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06); 8955 8956 chipio_set_stream_control(codec, 0x0C, 0); 8957 8958 chipio_set_control_param(codec, 0x0D, 0x24); 8959 8960 ca0132_clear_unsolicited(codec); 8961 sbz_set_pin_ctl_default(codec); 8962 8963 snd_hda_codec_write(codec, 0x0B, 0, 8964 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 8965 8966 sbz_region2_exit(codec); 8967 } 8968 8969 static void r3d_exit_chip(struct hda_codec *codec) 8970 { 8971 ca0132_clear_unsolicited(codec); 8972 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 8973 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b); 8974 } 8975 8976 static void ae5_exit_chip(struct hda_codec *codec) 8977 { 8978 chipio_set_stream_control(codec, 0x03, 0); 8979 chipio_set_stream_control(codec, 0x04, 0); 8980 8981 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 8982 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8983 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8984 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 8985 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 8986 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00); 8987 ca0113_mmio_gpio_set(codec, 0, false); 8988 ca0113_mmio_gpio_set(codec, 1, false); 8989 8990 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 8991 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 8992 8993 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 8994 8995 chipio_set_stream_control(codec, 0x18, 0); 8996 chipio_set_stream_control(codec, 0x0c, 0); 8997 8998 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83); 8999 } 9000 9001 static void ae7_exit_chip(struct hda_codec *codec) 9002 { 9003 chipio_set_stream_control(codec, 0x18, 0); 9004 chipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8); 9005 chipio_set_stream_channels(codec, 0x21, 0); 9006 chipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09); 9007 chipio_set_control_param(codec, 0x20, 0x01); 9008 9009 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 9010 9011 chipio_set_stream_control(codec, 0x18, 0); 9012 chipio_set_stream_control(codec, 0x0c, 0); 9013 9014 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 9015 snd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83); 9016 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 9017 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 9018 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00); 9019 ca0113_mmio_gpio_set(codec, 0, false); 9020 ca0113_mmio_gpio_set(codec, 1, false); 9021 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9022 9023 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 9024 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 9025 } 9026 9027 static void zxr_exit_chip(struct hda_codec *codec) 9028 { 9029 chipio_set_stream_control(codec, 0x03, 0); 9030 chipio_set_stream_control(codec, 0x04, 0); 9031 chipio_set_stream_control(codec, 0x14, 0); 9032 chipio_set_stream_control(codec, 0x0C, 0); 9033 9034 chipio_set_conn_rate(codec, 0x41, SR_192_000); 9035 chipio_set_conn_rate(codec, 0x91, SR_192_000); 9036 9037 chipio_write(codec, 0x18a020, 0x00000083); 9038 9039 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 9040 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 9041 9042 ca0132_clear_unsolicited(codec); 9043 sbz_set_pin_ctl_default(codec); 9044 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00); 9045 9046 ca0113_mmio_gpio_set(codec, 5, false); 9047 ca0113_mmio_gpio_set(codec, 2, false); 9048 ca0113_mmio_gpio_set(codec, 3, false); 9049 ca0113_mmio_gpio_set(codec, 0, false); 9050 ca0113_mmio_gpio_set(codec, 4, true); 9051 ca0113_mmio_gpio_set(codec, 0, true); 9052 ca0113_mmio_gpio_set(codec, 5, true); 9053 ca0113_mmio_gpio_set(codec, 2, false); 9054 ca0113_mmio_gpio_set(codec, 3, false); 9055 } 9056 9057 static void ca0132_exit_chip(struct hda_codec *codec) 9058 { 9059 /* put any chip cleanup stuffs here. */ 9060 9061 if (dspload_is_loaded(codec)) 9062 dsp_reset(codec); 9063 } 9064 9065 /* 9066 * This fixes a problem that was hard to reproduce. Very rarely, I would 9067 * boot up, and there would be no sound, but the DSP indicated it had loaded 9068 * properly. I did a few memory dumps to see if anything was different, and 9069 * there were a few areas of memory uninitialized with a1a2a3a4. This function 9070 * checks if those areas are uninitialized, and if they are, it'll attempt to 9071 * reload the card 3 times. Usually it fixes by the second. 9072 */ 9073 static void sbz_dsp_startup_check(struct hda_codec *codec) 9074 { 9075 struct ca0132_spec *spec = codec->spec; 9076 unsigned int dsp_data_check[4]; 9077 unsigned int cur_address = 0x390; 9078 unsigned int i; 9079 unsigned int failure = 0; 9080 unsigned int reload = 3; 9081 9082 if (spec->startup_check_entered) 9083 return; 9084 9085 spec->startup_check_entered = true; 9086 9087 for (i = 0; i < 4; i++) { 9088 chipio_read(codec, cur_address, &dsp_data_check[i]); 9089 cur_address += 0x4; 9090 } 9091 for (i = 0; i < 4; i++) { 9092 if (dsp_data_check[i] == 0xa1a2a3a4) 9093 failure = 1; 9094 } 9095 9096 codec_dbg(codec, "Startup Check: %d ", failure); 9097 if (failure) 9098 codec_info(codec, "DSP not initialized properly. Attempting to fix."); 9099 /* 9100 * While the failure condition is true, and we haven't reached our 9101 * three reload limit, continue trying to reload the driver and 9102 * fix the issue. 9103 */ 9104 while (failure && (reload != 0)) { 9105 codec_info(codec, "Reloading... Tries left: %d", reload); 9106 sbz_exit_chip(codec); 9107 spec->dsp_state = DSP_DOWNLOAD_INIT; 9108 codec->patch_ops.init(codec); 9109 failure = 0; 9110 for (i = 0; i < 4; i++) { 9111 chipio_read(codec, cur_address, &dsp_data_check[i]); 9112 cur_address += 0x4; 9113 } 9114 for (i = 0; i < 4; i++) { 9115 if (dsp_data_check[i] == 0xa1a2a3a4) 9116 failure = 1; 9117 } 9118 reload--; 9119 } 9120 9121 if (!failure && reload < 3) 9122 codec_info(codec, "DSP fixed."); 9123 9124 if (!failure) 9125 return; 9126 9127 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory."); 9128 } 9129 9130 /* 9131 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add 9132 * extra precision for decibel values. If you had the dB value in floating point 9133 * you would take the value after the decimal point, multiply by 64, and divide 9134 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to 9135 * implement fixed point or floating point dB volumes. For now, I'll set them 9136 * to 0 just incase a value has lingered from a boot into Windows. 9137 */ 9138 static void ca0132_alt_vol_setup(struct hda_codec *codec) 9139 { 9140 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00); 9141 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00); 9142 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00); 9143 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00); 9144 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00); 9145 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00); 9146 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00); 9147 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00); 9148 } 9149 9150 /* 9151 * Extra commands that don't really fit anywhere else. 9152 */ 9153 static void sbz_pre_dsp_setup(struct hda_codec *codec) 9154 { 9155 struct ca0132_spec *spec = codec->spec; 9156 9157 writel(0x00820680, spec->mem_base + 0x01C); 9158 writel(0x00820680, spec->mem_base + 0x01C); 9159 9160 chipio_write(codec, 0x18b0a4, 0x000000c2); 9161 9162 snd_hda_codec_write(codec, 0x11, 0, 9163 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 9164 } 9165 9166 static void r3d_pre_dsp_setup(struct hda_codec *codec) 9167 { 9168 chipio_write(codec, 0x18b0a4, 0x000000c2); 9169 9170 chipio_8051_write_exram(codec, 0x1c1e, 0x5b); 9171 9172 snd_hda_codec_write(codec, 0x11, 0, 9173 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 9174 } 9175 9176 static void r3di_pre_dsp_setup(struct hda_codec *codec) 9177 { 9178 chipio_write(codec, 0x18b0a4, 0x000000c2); 9179 9180 chipio_8051_write_exram(codec, 0x1c1e, 0x5b); 9181 chipio_8051_write_exram(codec, 0x1920, 0x00); 9182 chipio_8051_write_exram(codec, 0x1921, 0x40); 9183 9184 snd_hda_codec_write(codec, 0x11, 0, 9185 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04); 9186 } 9187 9188 /* 9189 * The ZxR seems to use alternative DAC's for the surround channels, which 9190 * require PLL PMU setup for the clock rate, I'm guessing. Without setting 9191 * this up, we get no audio out of the surround jacks. 9192 */ 9193 static void zxr_pre_dsp_setup(struct hda_codec *codec) 9194 { 9195 static const unsigned int addr[] = { 0x43, 0x40, 0x41, 0x42, 0x45 }; 9196 static const unsigned int data[] = { 0x08, 0x0c, 0x0b, 0x07, 0x0d }; 9197 unsigned int i; 9198 9199 chipio_write(codec, 0x189000, 0x0001f100); 9200 msleep(50); 9201 chipio_write(codec, 0x18900c, 0x0001f100); 9202 msleep(50); 9203 9204 /* 9205 * This writes a RET instruction at the entry point of the function at 9206 * 0xfa92 in exram. This function seems to have something to do with 9207 * ASI. Might be some way to prevent the card from reconfiguring the 9208 * ASI stuff itself. 9209 */ 9210 chipio_8051_write_exram(codec, 0xfa92, 0x22); 9211 9212 chipio_8051_write_pll_pmu(codec, 0x51, 0x98); 9213 9214 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x82); 9215 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 3); 9216 9217 chipio_write(codec, 0x18902c, 0x00000000); 9218 msleep(50); 9219 chipio_write(codec, 0x18902c, 0x00000003); 9220 msleep(50); 9221 9222 for (i = 0; i < ARRAY_SIZE(addr); i++) 9223 chipio_8051_write_pll_pmu(codec, addr[i], data[i]); 9224 } 9225 9226 /* 9227 * These are sent before the DSP is downloaded. Not sure 9228 * what they do, or if they're necessary. Could possibly 9229 * be removed. Figure they're better to leave in. 9230 */ 9231 static const unsigned int ca0113_mmio_init_address_sbz[] = { 9232 0x400, 0x408, 0x40c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 9233 0xc0c, 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04 9234 }; 9235 9236 static const unsigned int ca0113_mmio_init_data_sbz[] = { 9237 0x00000030, 0x00000000, 0x00000003, 0x00000003, 0x00000003, 9238 0x00000003, 0x000000c1, 0x000000f1, 0x00000001, 0x000000c7, 9239 0x000000c1, 0x00000080 9240 }; 9241 9242 static const unsigned int ca0113_mmio_init_data_zxr[] = { 9243 0x00000030, 0x00000000, 0x00000000, 0x00000003, 0x00000003, 9244 0x00000003, 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 9245 0x000000c1, 0x00000080 9246 }; 9247 9248 static const unsigned int ca0113_mmio_init_address_ae5[] = { 9249 0x400, 0x42c, 0x46c, 0x4ac, 0x4ec, 0x43c, 0x47c, 0x4bc, 0x4fc, 0x408, 9250 0x100, 0x410, 0x40c, 0x100, 0x100, 0x830, 0x86c, 0x800, 0x86c, 0x800, 9251 0x804, 0x20c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 0xc0c, 9252 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04, 0x01c 9253 }; 9254 9255 static const unsigned int ca0113_mmio_init_data_ae5[] = { 9256 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 9257 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 9258 0x00000600, 0x00000014, 0x00000001, 0x0000060f, 0x0000070f, 9259 0x00000aff, 0x00000000, 0x0000006b, 0x00000001, 0x0000006b, 9260 0x00000057, 0x00800000, 0x00880680, 0x00000080, 0x00000030, 9261 0x00000000, 0x00000000, 0x00000003, 0x00000003, 0x00000003, 9262 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1, 9263 0x00000080, 0x00880680 9264 }; 9265 9266 static void ca0132_mmio_init_sbz(struct hda_codec *codec) 9267 { 9268 struct ca0132_spec *spec = codec->spec; 9269 unsigned int tmp[2], i, count, cur_addr; 9270 const unsigned int *addr, *data; 9271 9272 addr = ca0113_mmio_init_address_sbz; 9273 for (i = 0; i < 3; i++) 9274 writel(0x00000000, spec->mem_base + addr[i]); 9275 9276 cur_addr = i; 9277 switch (ca0132_quirk(spec)) { 9278 case QUIRK_ZXR: 9279 tmp[0] = 0x00880480; 9280 tmp[1] = 0x00000080; 9281 break; 9282 case QUIRK_SBZ: 9283 tmp[0] = 0x00820680; 9284 tmp[1] = 0x00000083; 9285 break; 9286 case QUIRK_R3D: 9287 tmp[0] = 0x00880680; 9288 tmp[1] = 0x00000083; 9289 break; 9290 default: 9291 tmp[0] = 0x00000000; 9292 tmp[1] = 0x00000000; 9293 break; 9294 } 9295 9296 for (i = 0; i < 2; i++) 9297 writel(tmp[i], spec->mem_base + addr[cur_addr + i]); 9298 9299 cur_addr += i; 9300 9301 switch (ca0132_quirk(spec)) { 9302 case QUIRK_ZXR: 9303 count = ARRAY_SIZE(ca0113_mmio_init_data_zxr); 9304 data = ca0113_mmio_init_data_zxr; 9305 break; 9306 default: 9307 count = ARRAY_SIZE(ca0113_mmio_init_data_sbz); 9308 data = ca0113_mmio_init_data_sbz; 9309 break; 9310 } 9311 9312 for (i = 0; i < count; i++) 9313 writel(data[i], spec->mem_base + addr[cur_addr + i]); 9314 } 9315 9316 static void ca0132_mmio_init_ae5(struct hda_codec *codec) 9317 { 9318 struct ca0132_spec *spec = codec->spec; 9319 const unsigned int *addr, *data; 9320 unsigned int i, count; 9321 9322 addr = ca0113_mmio_init_address_ae5; 9323 data = ca0113_mmio_init_data_ae5; 9324 count = ARRAY_SIZE(ca0113_mmio_init_data_ae5); 9325 9326 if (ca0132_quirk(spec) == QUIRK_AE7) { 9327 writel(0x00000680, spec->mem_base + 0x1c); 9328 writel(0x00880680, spec->mem_base + 0x1c); 9329 } 9330 9331 for (i = 0; i < count; i++) { 9332 /* 9333 * AE-7 shares all writes with the AE-5, except that it writes 9334 * a different value to 0x20c. 9335 */ 9336 if (i == 21 && ca0132_quirk(spec) == QUIRK_AE7) { 9337 writel(0x00800001, spec->mem_base + addr[i]); 9338 continue; 9339 } 9340 9341 writel(data[i], spec->mem_base + addr[i]); 9342 } 9343 9344 if (ca0132_quirk(spec) == QUIRK_AE5) 9345 writel(0x00880680, spec->mem_base + 0x1c); 9346 } 9347 9348 static void ca0132_mmio_init(struct hda_codec *codec) 9349 { 9350 struct ca0132_spec *spec = codec->spec; 9351 9352 switch (ca0132_quirk(spec)) { 9353 case QUIRK_R3D: 9354 case QUIRK_SBZ: 9355 case QUIRK_ZXR: 9356 ca0132_mmio_init_sbz(codec); 9357 break; 9358 case QUIRK_AE5: 9359 ca0132_mmio_init_ae5(codec); 9360 break; 9361 default: 9362 break; 9363 } 9364 } 9365 9366 static const unsigned int ca0132_ae5_register_set_addresses[] = { 9367 0x304, 0x304, 0x304, 0x304, 0x100, 0x304, 0x100, 0x304, 0x100, 0x304, 9368 0x100, 0x304, 0x86c, 0x800, 0x86c, 0x800, 0x804 9369 }; 9370 9371 static const unsigned char ca0132_ae5_register_set_data[] = { 9372 0x0f, 0x0e, 0x1f, 0x0c, 0x3f, 0x08, 0x7f, 0x00, 0xff, 0x00, 0x6b, 9373 0x01, 0x6b, 0x57 9374 }; 9375 9376 /* 9377 * This function writes to some SFR's, does some region2 writes, and then 9378 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does 9379 * what it does. 9380 */ 9381 static void ae5_register_set(struct hda_codec *codec) 9382 { 9383 struct ca0132_spec *spec = codec->spec; 9384 unsigned int count = ARRAY_SIZE(ca0132_ae5_register_set_addresses); 9385 const unsigned int *addr = ca0132_ae5_register_set_addresses; 9386 const unsigned char *data = ca0132_ae5_register_set_data; 9387 unsigned int i, cur_addr; 9388 unsigned char tmp[3]; 9389 9390 if (ca0132_quirk(spec) == QUIRK_AE7) 9391 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8); 9392 9393 chipio_8051_write_direct(codec, 0x93, 0x10); 9394 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); 9395 9396 if (ca0132_quirk(spec) == QUIRK_AE7) { 9397 tmp[0] = 0x03; 9398 tmp[1] = 0x03; 9399 tmp[2] = 0x07; 9400 } else { 9401 tmp[0] = 0x0f; 9402 tmp[1] = 0x0f; 9403 tmp[2] = 0x0f; 9404 } 9405 9406 for (i = cur_addr = 0; i < 3; i++, cur_addr++) 9407 writeb(tmp[i], spec->mem_base + addr[cur_addr]); 9408 9409 /* 9410 * First writes are in single bytes, final are in 4 bytes. So, we use 9411 * writeb, then writel. 9412 */ 9413 for (i = 0; cur_addr < 12; i++, cur_addr++) 9414 writeb(data[i], spec->mem_base + addr[cur_addr]); 9415 9416 for (; cur_addr < count; i++, cur_addr++) 9417 writel(data[i], spec->mem_base + addr[cur_addr]); 9418 9419 writel(0x00800001, spec->mem_base + 0x20c); 9420 9421 if (ca0132_quirk(spec) == QUIRK_AE7) { 9422 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 9423 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 9424 } else { 9425 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 9426 } 9427 9428 chipio_8051_write_direct(codec, 0x90, 0x00); 9429 chipio_8051_write_direct(codec, 0x90, 0x10); 9430 9431 if (ca0132_quirk(spec) == QUIRK_AE5) 9432 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 9433 } 9434 9435 /* 9436 * Extra init functions for alternative ca0132 codecs. Done 9437 * here so they don't clutter up the main ca0132_init function 9438 * anymore than they have to. 9439 */ 9440 static void ca0132_alt_init(struct hda_codec *codec) 9441 { 9442 struct ca0132_spec *spec = codec->spec; 9443 9444 ca0132_alt_vol_setup(codec); 9445 9446 switch (ca0132_quirk(spec)) { 9447 case QUIRK_SBZ: 9448 codec_dbg(codec, "SBZ alt_init"); 9449 ca0132_gpio_init(codec); 9450 sbz_pre_dsp_setup(codec); 9451 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9452 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9453 break; 9454 case QUIRK_R3DI: 9455 codec_dbg(codec, "R3DI alt_init"); 9456 ca0132_gpio_init(codec); 9457 ca0132_gpio_setup(codec); 9458 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING); 9459 r3di_pre_dsp_setup(codec); 9460 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9461 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4); 9462 break; 9463 case QUIRK_R3D: 9464 r3d_pre_dsp_setup(codec); 9465 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9466 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9467 break; 9468 case QUIRK_AE5: 9469 ca0132_gpio_init(codec); 9470 chipio_8051_write_pll_pmu(codec, 0x49, 0x88); 9471 chipio_write(codec, 0x18b030, 0x00000020); 9472 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9473 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9474 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9475 break; 9476 case QUIRK_AE7: 9477 ca0132_gpio_init(codec); 9478 chipio_8051_write_pll_pmu(codec, 0x49, 0x88); 9479 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9480 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9481 chipio_write(codec, 0x18b008, 0x000000f8); 9482 chipio_write(codec, 0x18b008, 0x000000f0); 9483 chipio_write(codec, 0x18b030, 0x00000020); 9484 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9485 break; 9486 case QUIRK_ZXR: 9487 chipio_8051_write_pll_pmu(codec, 0x49, 0x88); 9488 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9489 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9490 zxr_pre_dsp_setup(codec); 9491 break; 9492 default: 9493 break; 9494 } 9495 } 9496 9497 static int ca0132_init(struct hda_codec *codec) 9498 { 9499 struct ca0132_spec *spec = codec->spec; 9500 struct auto_pin_cfg *cfg = &spec->autocfg; 9501 int i; 9502 bool dsp_loaded; 9503 9504 /* 9505 * If the DSP is already downloaded, and init has been entered again, 9506 * there's only two reasons for it. One, the codec has awaken from a 9507 * suspended state, and in that case dspload_is_loaded will return 9508 * false, and the init will be ran again. The other reason it gets 9509 * re entered is on startup for some reason it triggers a suspend and 9510 * resume state. In this case, it will check if the DSP is downloaded, 9511 * and not run the init function again. For codecs using alt_functions, 9512 * it will check if the DSP is loaded properly. 9513 */ 9514 if (spec->dsp_state == DSP_DOWNLOADED) { 9515 dsp_loaded = dspload_is_loaded(codec); 9516 if (!dsp_loaded) { 9517 spec->dsp_reload = true; 9518 spec->dsp_state = DSP_DOWNLOAD_INIT; 9519 } else { 9520 if (ca0132_quirk(spec) == QUIRK_SBZ) 9521 sbz_dsp_startup_check(codec); 9522 return 0; 9523 } 9524 } 9525 9526 if (spec->dsp_state != DSP_DOWNLOAD_FAILED) 9527 spec->dsp_state = DSP_DOWNLOAD_INIT; 9528 spec->curr_chip_addx = INVALID_CHIP_ADDRESS; 9529 9530 if (ca0132_use_pci_mmio(spec)) 9531 ca0132_mmio_init(codec); 9532 9533 snd_hda_power_up_pm(codec); 9534 9535 if (ca0132_quirk(spec) == QUIRK_AE5 || ca0132_quirk(spec) == QUIRK_AE7) 9536 ae5_register_set(codec); 9537 9538 ca0132_init_params(codec); 9539 ca0132_init_flags(codec); 9540 9541 snd_hda_sequence_write(codec, spec->base_init_verbs); 9542 9543 if (ca0132_use_alt_functions(spec)) 9544 ca0132_alt_init(codec); 9545 9546 ca0132_download_dsp(codec); 9547 9548 ca0132_refresh_widget_caps(codec); 9549 9550 switch (ca0132_quirk(spec)) { 9551 case QUIRK_R3DI: 9552 case QUIRK_R3D: 9553 r3d_setup_defaults(codec); 9554 break; 9555 case QUIRK_SBZ: 9556 case QUIRK_ZXR: 9557 sbz_setup_defaults(codec); 9558 break; 9559 case QUIRK_AE5: 9560 ae5_setup_defaults(codec); 9561 break; 9562 case QUIRK_AE7: 9563 ae7_setup_defaults(codec); 9564 break; 9565 default: 9566 ca0132_setup_defaults(codec); 9567 ca0132_init_analog_mic2(codec); 9568 ca0132_init_dmic(codec); 9569 break; 9570 } 9571 9572 for (i = 0; i < spec->num_outputs; i++) 9573 init_output(codec, spec->out_pins[i], spec->dacs[0]); 9574 9575 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 9576 9577 for (i = 0; i < spec->num_inputs; i++) 9578 init_input(codec, spec->input_pins[i], spec->adcs[i]); 9579 9580 init_input(codec, cfg->dig_in_pin, spec->dig_in); 9581 9582 if (!ca0132_use_alt_functions(spec)) { 9583 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9584 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9585 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D); 9586 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9587 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20); 9588 } 9589 9590 if (ca0132_quirk(spec) == QUIRK_SBZ) 9591 ca0132_gpio_setup(codec); 9592 9593 snd_hda_sequence_write(codec, spec->spec_init_verbs); 9594 if (ca0132_use_alt_functions(spec)) { 9595 ca0132_alt_select_out(codec); 9596 ca0132_alt_select_in(codec); 9597 } else { 9598 ca0132_select_out(codec); 9599 ca0132_select_mic(codec); 9600 } 9601 9602 snd_hda_jack_report_sync(codec); 9603 9604 /* 9605 * Re set the PlayEnhancement switch on a resume event, because the 9606 * controls will not be reloaded. 9607 */ 9608 if (spec->dsp_reload) { 9609 spec->dsp_reload = false; 9610 ca0132_pe_switch_set(codec); 9611 } 9612 9613 snd_hda_power_down_pm(codec); 9614 9615 return 0; 9616 } 9617 9618 static int dbpro_init(struct hda_codec *codec) 9619 { 9620 struct ca0132_spec *spec = codec->spec; 9621 struct auto_pin_cfg *cfg = &spec->autocfg; 9622 unsigned int i; 9623 9624 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 9625 init_input(codec, cfg->dig_in_pin, spec->dig_in); 9626 9627 for (i = 0; i < spec->num_inputs; i++) 9628 init_input(codec, spec->input_pins[i], spec->adcs[i]); 9629 9630 return 0; 9631 } 9632 9633 static void ca0132_free(struct hda_codec *codec) 9634 { 9635 struct ca0132_spec *spec = codec->spec; 9636 9637 cancel_delayed_work_sync(&spec->unsol_hp_work); 9638 snd_hda_power_up(codec); 9639 switch (ca0132_quirk(spec)) { 9640 case QUIRK_SBZ: 9641 sbz_exit_chip(codec); 9642 break; 9643 case QUIRK_ZXR: 9644 zxr_exit_chip(codec); 9645 break; 9646 case QUIRK_R3D: 9647 r3d_exit_chip(codec); 9648 break; 9649 case QUIRK_AE5: 9650 ae5_exit_chip(codec); 9651 break; 9652 case QUIRK_AE7: 9653 ae7_exit_chip(codec); 9654 break; 9655 case QUIRK_R3DI: 9656 r3di_gpio_shutdown(codec); 9657 break; 9658 default: 9659 break; 9660 } 9661 9662 snd_hda_sequence_write(codec, spec->base_exit_verbs); 9663 ca0132_exit_chip(codec); 9664 9665 snd_hda_power_down(codec); 9666 #ifdef CONFIG_PCI 9667 if (spec->mem_base) 9668 pci_iounmap(codec->bus->pci, spec->mem_base); 9669 #endif 9670 kfree(spec->spec_init_verbs); 9671 kfree(codec->spec); 9672 } 9673 9674 static void dbpro_free(struct hda_codec *codec) 9675 { 9676 struct ca0132_spec *spec = codec->spec; 9677 9678 zxr_dbpro_power_state_shutdown(codec); 9679 9680 kfree(spec->spec_init_verbs); 9681 kfree(codec->spec); 9682 } 9683 9684 static void ca0132_reboot_notify(struct hda_codec *codec) 9685 { 9686 codec->patch_ops.free(codec); 9687 } 9688 9689 #ifdef CONFIG_PM 9690 static int ca0132_suspend(struct hda_codec *codec) 9691 { 9692 struct ca0132_spec *spec = codec->spec; 9693 9694 cancel_delayed_work_sync(&spec->unsol_hp_work); 9695 return 0; 9696 } 9697 #endif 9698 9699 static const struct hda_codec_ops ca0132_patch_ops = { 9700 .build_controls = ca0132_build_controls, 9701 .build_pcms = ca0132_build_pcms, 9702 .init = ca0132_init, 9703 .free = ca0132_free, 9704 .unsol_event = snd_hda_jack_unsol_event, 9705 #ifdef CONFIG_PM 9706 .suspend = ca0132_suspend, 9707 #endif 9708 .reboot_notify = ca0132_reboot_notify, 9709 }; 9710 9711 static const struct hda_codec_ops dbpro_patch_ops = { 9712 .build_controls = dbpro_build_controls, 9713 .build_pcms = dbpro_build_pcms, 9714 .init = dbpro_init, 9715 .free = dbpro_free, 9716 }; 9717 9718 static void ca0132_config(struct hda_codec *codec) 9719 { 9720 struct ca0132_spec *spec = codec->spec; 9721 9722 spec->dacs[0] = 0x2; 9723 spec->dacs[1] = 0x3; 9724 spec->dacs[2] = 0x4; 9725 9726 spec->multiout.dac_nids = spec->dacs; 9727 spec->multiout.num_dacs = 3; 9728 9729 if (!ca0132_use_alt_functions(spec)) 9730 spec->multiout.max_channels = 2; 9731 else 9732 spec->multiout.max_channels = 6; 9733 9734 switch (ca0132_quirk(spec)) { 9735 case QUIRK_ALIENWARE: 9736 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__); 9737 snd_hda_apply_pincfgs(codec, alienware_pincfgs); 9738 break; 9739 case QUIRK_SBZ: 9740 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__); 9741 snd_hda_apply_pincfgs(codec, sbz_pincfgs); 9742 break; 9743 case QUIRK_ZXR: 9744 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__); 9745 snd_hda_apply_pincfgs(codec, zxr_pincfgs); 9746 break; 9747 case QUIRK_R3D: 9748 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__); 9749 snd_hda_apply_pincfgs(codec, r3d_pincfgs); 9750 break; 9751 case QUIRK_R3DI: 9752 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__); 9753 snd_hda_apply_pincfgs(codec, r3di_pincfgs); 9754 break; 9755 case QUIRK_AE5: 9756 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__); 9757 snd_hda_apply_pincfgs(codec, ae5_pincfgs); 9758 break; 9759 case QUIRK_AE7: 9760 codec_dbg(codec, "%s: QUIRK_AE7 applied.\n", __func__); 9761 snd_hda_apply_pincfgs(codec, ae7_pincfgs); 9762 break; 9763 default: 9764 break; 9765 } 9766 9767 switch (ca0132_quirk(spec)) { 9768 case QUIRK_ALIENWARE: 9769 spec->num_outputs = 2; 9770 spec->out_pins[0] = 0x0b; /* speaker out */ 9771 spec->out_pins[1] = 0x0f; 9772 spec->shared_out_nid = 0x2; 9773 spec->unsol_tag_hp = 0x0f; 9774 9775 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 9776 spec->adcs[1] = 0x8; /* analog mic2 */ 9777 spec->adcs[2] = 0xa; /* what u hear */ 9778 9779 spec->num_inputs = 3; 9780 spec->input_pins[0] = 0x12; 9781 spec->input_pins[1] = 0x11; 9782 spec->input_pins[2] = 0x13; 9783 spec->shared_mic_nid = 0x7; 9784 spec->unsol_tag_amic1 = 0x11; 9785 break; 9786 case QUIRK_SBZ: 9787 case QUIRK_R3D: 9788 spec->num_outputs = 2; 9789 spec->out_pins[0] = 0x0B; /* Line out */ 9790 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9791 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9792 spec->out_pins[3] = 0x11; /* Rear surround */ 9793 spec->shared_out_nid = 0x2; 9794 spec->unsol_tag_hp = spec->out_pins[1]; 9795 spec->unsol_tag_front_hp = spec->out_pins[2]; 9796 9797 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9798 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 9799 spec->adcs[2] = 0xa; /* what u hear */ 9800 9801 spec->num_inputs = 2; 9802 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9803 spec->input_pins[1] = 0x13; /* What U Hear */ 9804 spec->shared_mic_nid = 0x7; 9805 spec->unsol_tag_amic1 = spec->input_pins[0]; 9806 9807 /* SPDIF I/O */ 9808 spec->dig_out = 0x05; 9809 spec->multiout.dig_out_nid = spec->dig_out; 9810 spec->dig_in = 0x09; 9811 break; 9812 case QUIRK_ZXR: 9813 spec->num_outputs = 2; 9814 spec->out_pins[0] = 0x0B; /* Line out */ 9815 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9816 spec->out_pins[2] = 0x10; /* Center/LFE */ 9817 spec->out_pins[3] = 0x11; /* Rear surround */ 9818 spec->shared_out_nid = 0x2; 9819 spec->unsol_tag_hp = spec->out_pins[1]; 9820 spec->unsol_tag_front_hp = spec->out_pins[2]; 9821 9822 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9823 spec->adcs[1] = 0x8; /* Not connected, no front mic */ 9824 spec->adcs[2] = 0xa; /* what u hear */ 9825 9826 spec->num_inputs = 2; 9827 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9828 spec->input_pins[1] = 0x13; /* What U Hear */ 9829 spec->shared_mic_nid = 0x7; 9830 spec->unsol_tag_amic1 = spec->input_pins[0]; 9831 break; 9832 case QUIRK_ZXR_DBPRO: 9833 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */ 9834 9835 spec->num_inputs = 1; 9836 spec->input_pins[0] = 0x11; /* RCA Line-in */ 9837 9838 spec->dig_out = 0x05; 9839 spec->multiout.dig_out_nid = spec->dig_out; 9840 9841 spec->dig_in = 0x09; 9842 break; 9843 case QUIRK_AE5: 9844 case QUIRK_AE7: 9845 spec->num_outputs = 2; 9846 spec->out_pins[0] = 0x0B; /* Line out */ 9847 spec->out_pins[1] = 0x11; /* Rear headphone out */ 9848 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9849 spec->out_pins[3] = 0x0F; /* Rear surround */ 9850 spec->shared_out_nid = 0x2; 9851 spec->unsol_tag_hp = spec->out_pins[1]; 9852 spec->unsol_tag_front_hp = spec->out_pins[2]; 9853 9854 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9855 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 9856 spec->adcs[2] = 0xa; /* what u hear */ 9857 9858 spec->num_inputs = 2; 9859 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9860 spec->input_pins[1] = 0x13; /* What U Hear */ 9861 spec->shared_mic_nid = 0x7; 9862 spec->unsol_tag_amic1 = spec->input_pins[0]; 9863 9864 /* SPDIF I/O */ 9865 spec->dig_out = 0x05; 9866 spec->multiout.dig_out_nid = spec->dig_out; 9867 break; 9868 case QUIRK_R3DI: 9869 spec->num_outputs = 2; 9870 spec->out_pins[0] = 0x0B; /* Line out */ 9871 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9872 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9873 spec->out_pins[3] = 0x11; /* Rear surround */ 9874 spec->shared_out_nid = 0x2; 9875 spec->unsol_tag_hp = spec->out_pins[1]; 9876 spec->unsol_tag_front_hp = spec->out_pins[2]; 9877 9878 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */ 9879 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */ 9880 spec->adcs[2] = 0x0a; /* what u hear */ 9881 9882 spec->num_inputs = 2; 9883 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9884 spec->input_pins[1] = 0x13; /* What U Hear */ 9885 spec->shared_mic_nid = 0x7; 9886 spec->unsol_tag_amic1 = spec->input_pins[0]; 9887 9888 /* SPDIF I/O */ 9889 spec->dig_out = 0x05; 9890 spec->multiout.dig_out_nid = spec->dig_out; 9891 break; 9892 default: 9893 spec->num_outputs = 2; 9894 spec->out_pins[0] = 0x0b; /* speaker out */ 9895 spec->out_pins[1] = 0x10; /* headphone out */ 9896 spec->shared_out_nid = 0x2; 9897 spec->unsol_tag_hp = spec->out_pins[1]; 9898 9899 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 9900 spec->adcs[1] = 0x8; /* analog mic2 */ 9901 spec->adcs[2] = 0xa; /* what u hear */ 9902 9903 spec->num_inputs = 3; 9904 spec->input_pins[0] = 0x12; 9905 spec->input_pins[1] = 0x11; 9906 spec->input_pins[2] = 0x13; 9907 spec->shared_mic_nid = 0x7; 9908 spec->unsol_tag_amic1 = spec->input_pins[0]; 9909 9910 /* SPDIF I/O */ 9911 spec->dig_out = 0x05; 9912 spec->multiout.dig_out_nid = spec->dig_out; 9913 spec->dig_in = 0x09; 9914 break; 9915 } 9916 } 9917 9918 static int ca0132_prepare_verbs(struct hda_codec *codec) 9919 { 9920 /* Verbs + terminator (an empty element) */ 9921 #define NUM_SPEC_VERBS 2 9922 struct ca0132_spec *spec = codec->spec; 9923 9924 spec->chip_init_verbs = ca0132_init_verbs0; 9925 /* 9926 * Since desktop cards use pci_mmio, this can be used to determine 9927 * whether or not to use these verbs instead of a separate bool. 9928 */ 9929 if (ca0132_use_pci_mmio(spec)) 9930 spec->desktop_init_verbs = ca0132_init_verbs1; 9931 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS, 9932 sizeof(struct hda_verb), 9933 GFP_KERNEL); 9934 if (!spec->spec_init_verbs) 9935 return -ENOMEM; 9936 9937 /* config EAPD */ 9938 spec->spec_init_verbs[0].nid = 0x0b; 9939 spec->spec_init_verbs[0].param = 0x78D; 9940 spec->spec_init_verbs[0].verb = 0x00; 9941 9942 /* Previously commented configuration */ 9943 /* 9944 spec->spec_init_verbs[2].nid = 0x0b; 9945 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE; 9946 spec->spec_init_verbs[2].verb = 0x02; 9947 9948 spec->spec_init_verbs[3].nid = 0x10; 9949 spec->spec_init_verbs[3].param = 0x78D; 9950 spec->spec_init_verbs[3].verb = 0x02; 9951 9952 spec->spec_init_verbs[4].nid = 0x10; 9953 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE; 9954 spec->spec_init_verbs[4].verb = 0x02; 9955 */ 9956 9957 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */ 9958 return 0; 9959 } 9960 9961 /* 9962 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular 9963 * Sound Blaster Z cards. However, they have different HDA codec subsystem 9964 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro 9965 * daughter boards ID. 9966 */ 9967 static void sbz_detect_quirk(struct hda_codec *codec) 9968 { 9969 struct ca0132_spec *spec = codec->spec; 9970 9971 switch (codec->core.subsystem_id) { 9972 case 0x11020033: 9973 spec->quirk = QUIRK_ZXR; 9974 break; 9975 case 0x1102003f: 9976 spec->quirk = QUIRK_ZXR_DBPRO; 9977 break; 9978 default: 9979 spec->quirk = QUIRK_SBZ; 9980 break; 9981 } 9982 } 9983 9984 static int patch_ca0132(struct hda_codec *codec) 9985 { 9986 struct ca0132_spec *spec; 9987 int err; 9988 const struct snd_pci_quirk *quirk; 9989 9990 codec_dbg(codec, "patch_ca0132\n"); 9991 9992 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 9993 if (!spec) 9994 return -ENOMEM; 9995 codec->spec = spec; 9996 spec->codec = codec; 9997 9998 /* Detect codec quirk */ 9999 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks); 10000 if (quirk) 10001 spec->quirk = quirk->value; 10002 else 10003 spec->quirk = QUIRK_NONE; 10004 if (ca0132_quirk(spec) == QUIRK_SBZ) 10005 sbz_detect_quirk(codec); 10006 10007 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO) 10008 codec->patch_ops = dbpro_patch_ops; 10009 else 10010 codec->patch_ops = ca0132_patch_ops; 10011 10012 codec->pcm_format_first = 1; 10013 codec->no_sticky_stream = 1; 10014 10015 10016 spec->dsp_state = DSP_DOWNLOAD_INIT; 10017 spec->num_mixers = 1; 10018 10019 /* Set which mixers each quirk uses. */ 10020 switch (ca0132_quirk(spec)) { 10021 case QUIRK_SBZ: 10022 spec->mixers[0] = desktop_mixer; 10023 snd_hda_codec_set_name(codec, "Sound Blaster Z"); 10024 break; 10025 case QUIRK_ZXR: 10026 spec->mixers[0] = desktop_mixer; 10027 snd_hda_codec_set_name(codec, "Sound Blaster ZxR"); 10028 break; 10029 case QUIRK_ZXR_DBPRO: 10030 break; 10031 case QUIRK_R3D: 10032 spec->mixers[0] = desktop_mixer; 10033 snd_hda_codec_set_name(codec, "Recon3D"); 10034 break; 10035 case QUIRK_R3DI: 10036 spec->mixers[0] = r3di_mixer; 10037 snd_hda_codec_set_name(codec, "Recon3Di"); 10038 break; 10039 case QUIRK_AE5: 10040 spec->mixers[0] = desktop_mixer; 10041 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5"); 10042 break; 10043 case QUIRK_AE7: 10044 spec->mixers[0] = desktop_mixer; 10045 snd_hda_codec_set_name(codec, "Sound Blaster AE-7"); 10046 break; 10047 default: 10048 spec->mixers[0] = ca0132_mixer; 10049 break; 10050 } 10051 10052 /* Setup whether or not to use alt functions/controls/pci_mmio */ 10053 switch (ca0132_quirk(spec)) { 10054 case QUIRK_SBZ: 10055 case QUIRK_R3D: 10056 case QUIRK_AE5: 10057 case QUIRK_AE7: 10058 case QUIRK_ZXR: 10059 spec->use_alt_controls = true; 10060 spec->use_alt_functions = true; 10061 spec->use_pci_mmio = true; 10062 break; 10063 case QUIRK_R3DI: 10064 spec->use_alt_controls = true; 10065 spec->use_alt_functions = true; 10066 spec->use_pci_mmio = false; 10067 break; 10068 default: 10069 spec->use_alt_controls = false; 10070 spec->use_alt_functions = false; 10071 spec->use_pci_mmio = false; 10072 break; 10073 } 10074 10075 #ifdef CONFIG_PCI 10076 if (spec->use_pci_mmio) { 10077 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20); 10078 if (spec->mem_base == NULL) { 10079 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE."); 10080 spec->quirk = QUIRK_NONE; 10081 } 10082 } 10083 #endif 10084 10085 spec->base_init_verbs = ca0132_base_init_verbs; 10086 spec->base_exit_verbs = ca0132_base_exit_verbs; 10087 10088 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed); 10089 10090 ca0132_init_chip(codec); 10091 10092 ca0132_config(codec); 10093 10094 err = ca0132_prepare_verbs(codec); 10095 if (err < 0) 10096 goto error; 10097 10098 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL); 10099 if (err < 0) 10100 goto error; 10101 10102 ca0132_setup_unsol(codec); 10103 10104 return 0; 10105 10106 error: 10107 ca0132_free(codec); 10108 return err; 10109 } 10110 10111 /* 10112 * patch entries 10113 */ 10114 static const struct hda_device_id snd_hda_id_ca0132[] = { 10115 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132), 10116 {} /* terminator */ 10117 }; 10118 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132); 10119 10120 MODULE_LICENSE("GPL"); 10121 MODULE_DESCRIPTION("Creative Sound Core3D codec"); 10122 10123 static struct hda_codec_driver ca0132_driver = { 10124 .id = snd_hda_id_ca0132, 10125 }; 10126 10127 module_hda_codec_driver(ca0132_driver); 10128