1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * HD audio interface patch for Creative CA0132 chip 4 * 5 * Copyright (c) 2011, Creative Technology Ltd. 6 * 7 * Based on patch_ca0110.c 8 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de> 9 */ 10 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/slab.h> 14 #include <linux/mutex.h> 15 #include <linux/module.h> 16 #include <linux/firmware.h> 17 #include <linux/kernel.h> 18 #include <linux/types.h> 19 #include <linux/io.h> 20 #include <linux/pci.h> 21 #include <asm/io.h> 22 #include <sound/core.h> 23 #include <sound/hda_codec.h> 24 #include "hda_local.h" 25 #include "hda_auto_parser.h" 26 #include "hda_jack.h" 27 28 #include "ca0132_regs.h" 29 30 /* Enable this to see controls for tuning purpose. */ 31 /*#define ENABLE_TUNING_CONTROLS*/ 32 33 #ifdef ENABLE_TUNING_CONTROLS 34 #include <sound/tlv.h> 35 #endif 36 37 #define FLOAT_ZERO 0x00000000 38 #define FLOAT_ONE 0x3f800000 39 #define FLOAT_TWO 0x40000000 40 #define FLOAT_THREE 0x40400000 41 #define FLOAT_EIGHT 0x41000000 42 #define FLOAT_MINUS_5 0xc0a00000 43 44 #define UNSOL_TAG_DSP 0x16 45 46 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18) 47 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15) 48 49 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8 50 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32 51 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2 52 53 #define MASTERCONTROL 0x80 54 #define MASTERCONTROL_ALLOC_DMA_CHAN 10 55 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60 56 57 #define WIDGET_CHIP_CTRL 0x15 58 #define WIDGET_DSP_CTRL 0x16 59 60 #define MEM_CONNID_MICIN1 3 61 #define MEM_CONNID_MICIN2 5 62 #define MEM_CONNID_MICOUT1 12 63 #define MEM_CONNID_MICOUT2 14 64 #define MEM_CONNID_WUH 10 65 #define MEM_CONNID_DSP 16 66 #define MEM_CONNID_DMIC 100 67 68 #define SCP_SET 0 69 #define SCP_GET 1 70 71 #define EFX_FILE "ctefx.bin" 72 #define DESKTOP_EFX_FILE "ctefx-desktop.bin" 73 #define R3DI_EFX_FILE "ctefx-r3di.bin" 74 75 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 76 MODULE_FIRMWARE(EFX_FILE); 77 MODULE_FIRMWARE(DESKTOP_EFX_FILE); 78 MODULE_FIRMWARE(R3DI_EFX_FILE); 79 #endif 80 81 static const char *const dirstr[2] = { "Playback", "Capture" }; 82 83 #define NUM_OF_OUTPUTS 3 84 enum { 85 SPEAKER_OUT, 86 HEADPHONE_OUT, 87 SURROUND_OUT 88 }; 89 90 enum { 91 DIGITAL_MIC, 92 LINE_MIC_IN 93 }; 94 95 /* Strings for Input Source Enum Control */ 96 static const char *const in_src_str[3] = {"Rear Mic", "Line", "Front Mic" }; 97 #define IN_SRC_NUM_OF_INPUTS 3 98 enum { 99 REAR_MIC, 100 REAR_LINE_IN, 101 FRONT_MIC, 102 }; 103 104 enum { 105 #define VNODE_START_NID 0x80 106 VNID_SPK = VNODE_START_NID, /* Speaker vnid */ 107 VNID_MIC, 108 VNID_HP_SEL, 109 VNID_AMIC1_SEL, 110 VNID_HP_ASEL, 111 VNID_AMIC1_ASEL, 112 VNODE_END_NID, 113 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID) 114 115 #define EFFECT_START_NID 0x90 116 #define OUT_EFFECT_START_NID EFFECT_START_NID 117 SURROUND = OUT_EFFECT_START_NID, 118 CRYSTALIZER, 119 DIALOG_PLUS, 120 SMART_VOLUME, 121 X_BASS, 122 EQUALIZER, 123 OUT_EFFECT_END_NID, 124 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID) 125 126 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID 127 ECHO_CANCELLATION = IN_EFFECT_START_NID, 128 VOICE_FOCUS, 129 MIC_SVM, 130 NOISE_REDUCTION, 131 IN_EFFECT_END_NID, 132 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID) 133 134 VOICEFX = IN_EFFECT_END_NID, 135 PLAY_ENHANCEMENT, 136 CRYSTAL_VOICE, 137 EFFECT_END_NID, 138 OUTPUT_SOURCE_ENUM, 139 INPUT_SOURCE_ENUM, 140 XBASS_XOVER, 141 EQ_PRESET_ENUM, 142 SMART_VOLUME_ENUM, 143 MIC_BOOST_ENUM, 144 AE5_HEADPHONE_GAIN_ENUM, 145 AE5_SOUND_FILTER_ENUM, 146 ZXR_HEADPHONE_GAIN 147 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID) 148 }; 149 150 /* Effects values size*/ 151 #define EFFECT_VALS_MAX_COUNT 12 152 153 /* 154 * Default values for the effect slider controls, they are in order of their 155 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then 156 * X-bass. 157 */ 158 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50}; 159 /* Amount of effect level sliders for ca0132_alt controls. */ 160 #define EFFECT_LEVEL_SLIDERS 5 161 162 /* Latency introduced by DSP blocks in milliseconds. */ 163 #define DSP_CAPTURE_INIT_LATENCY 0 164 #define DSP_CRYSTAL_VOICE_LATENCY 124 165 #define DSP_PLAYBACK_INIT_LATENCY 13 166 #define DSP_PLAY_ENHANCEMENT_LATENCY 30 167 #define DSP_SPEAKER_OUT_LATENCY 7 168 169 struct ct_effect { 170 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 171 hda_nid_t nid; 172 int mid; /*effect module ID*/ 173 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/ 174 int direct; /* 0:output; 1:input*/ 175 int params; /* number of default non-on/off params */ 176 /*effect default values, 1st is on/off. */ 177 unsigned int def_vals[EFFECT_VALS_MAX_COUNT]; 178 }; 179 180 #define EFX_DIR_OUT 0 181 #define EFX_DIR_IN 1 182 183 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = { 184 { .name = "Surround", 185 .nid = SURROUND, 186 .mid = 0x96, 187 .reqs = {0, 1}, 188 .direct = EFX_DIR_OUT, 189 .params = 1, 190 .def_vals = {0x3F800000, 0x3F2B851F} 191 }, 192 { .name = "Crystalizer", 193 .nid = CRYSTALIZER, 194 .mid = 0x96, 195 .reqs = {7, 8}, 196 .direct = EFX_DIR_OUT, 197 .params = 1, 198 .def_vals = {0x3F800000, 0x3F266666} 199 }, 200 { .name = "Dialog Plus", 201 .nid = DIALOG_PLUS, 202 .mid = 0x96, 203 .reqs = {2, 3}, 204 .direct = EFX_DIR_OUT, 205 .params = 1, 206 .def_vals = {0x00000000, 0x3F000000} 207 }, 208 { .name = "Smart Volume", 209 .nid = SMART_VOLUME, 210 .mid = 0x96, 211 .reqs = {4, 5, 6}, 212 .direct = EFX_DIR_OUT, 213 .params = 2, 214 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000} 215 }, 216 { .name = "X-Bass", 217 .nid = X_BASS, 218 .mid = 0x96, 219 .reqs = {24, 23, 25}, 220 .direct = EFX_DIR_OUT, 221 .params = 2, 222 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000} 223 }, 224 { .name = "Equalizer", 225 .nid = EQUALIZER, 226 .mid = 0x96, 227 .reqs = {9, 10, 11, 12, 13, 14, 228 15, 16, 17, 18, 19, 20}, 229 .direct = EFX_DIR_OUT, 230 .params = 11, 231 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000, 232 0x00000000, 0x00000000, 0x00000000, 0x00000000, 233 0x00000000, 0x00000000, 0x00000000, 0x00000000} 234 }, 235 { .name = "Echo Cancellation", 236 .nid = ECHO_CANCELLATION, 237 .mid = 0x95, 238 .reqs = {0, 1, 2, 3}, 239 .direct = EFX_DIR_IN, 240 .params = 3, 241 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000} 242 }, 243 { .name = "Voice Focus", 244 .nid = VOICE_FOCUS, 245 .mid = 0x95, 246 .reqs = {6, 7, 8, 9}, 247 .direct = EFX_DIR_IN, 248 .params = 3, 249 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000} 250 }, 251 { .name = "Mic SVM", 252 .nid = MIC_SVM, 253 .mid = 0x95, 254 .reqs = {44, 45}, 255 .direct = EFX_DIR_IN, 256 .params = 1, 257 .def_vals = {0x00000000, 0x3F3D70A4} 258 }, 259 { .name = "Noise Reduction", 260 .nid = NOISE_REDUCTION, 261 .mid = 0x95, 262 .reqs = {4, 5}, 263 .direct = EFX_DIR_IN, 264 .params = 1, 265 .def_vals = {0x3F800000, 0x3F000000} 266 }, 267 { .name = "VoiceFX", 268 .nid = VOICEFX, 269 .mid = 0x95, 270 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}, 271 .direct = EFX_DIR_IN, 272 .params = 8, 273 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000, 274 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000, 275 0x00000000} 276 } 277 }; 278 279 /* Tuning controls */ 280 #ifdef ENABLE_TUNING_CONTROLS 281 282 enum { 283 #define TUNING_CTL_START_NID 0xC0 284 WEDGE_ANGLE = TUNING_CTL_START_NID, 285 SVM_LEVEL, 286 EQUALIZER_BAND_0, 287 EQUALIZER_BAND_1, 288 EQUALIZER_BAND_2, 289 EQUALIZER_BAND_3, 290 EQUALIZER_BAND_4, 291 EQUALIZER_BAND_5, 292 EQUALIZER_BAND_6, 293 EQUALIZER_BAND_7, 294 EQUALIZER_BAND_8, 295 EQUALIZER_BAND_9, 296 TUNING_CTL_END_NID 297 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID) 298 }; 299 300 struct ct_tuning_ctl { 301 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 302 hda_nid_t parent_nid; 303 hda_nid_t nid; 304 int mid; /*effect module ID*/ 305 int req; /*effect module request*/ 306 int direct; /* 0:output; 1:input*/ 307 unsigned int def_val;/*effect default values*/ 308 }; 309 310 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = { 311 { .name = "Wedge Angle", 312 .parent_nid = VOICE_FOCUS, 313 .nid = WEDGE_ANGLE, 314 .mid = 0x95, 315 .req = 8, 316 .direct = EFX_DIR_IN, 317 .def_val = 0x41F00000 318 }, 319 { .name = "SVM Level", 320 .parent_nid = MIC_SVM, 321 .nid = SVM_LEVEL, 322 .mid = 0x95, 323 .req = 45, 324 .direct = EFX_DIR_IN, 325 .def_val = 0x3F3D70A4 326 }, 327 { .name = "EQ Band0", 328 .parent_nid = EQUALIZER, 329 .nid = EQUALIZER_BAND_0, 330 .mid = 0x96, 331 .req = 11, 332 .direct = EFX_DIR_OUT, 333 .def_val = 0x00000000 334 }, 335 { .name = "EQ Band1", 336 .parent_nid = EQUALIZER, 337 .nid = EQUALIZER_BAND_1, 338 .mid = 0x96, 339 .req = 12, 340 .direct = EFX_DIR_OUT, 341 .def_val = 0x00000000 342 }, 343 { .name = "EQ Band2", 344 .parent_nid = EQUALIZER, 345 .nid = EQUALIZER_BAND_2, 346 .mid = 0x96, 347 .req = 13, 348 .direct = EFX_DIR_OUT, 349 .def_val = 0x00000000 350 }, 351 { .name = "EQ Band3", 352 .parent_nid = EQUALIZER, 353 .nid = EQUALIZER_BAND_3, 354 .mid = 0x96, 355 .req = 14, 356 .direct = EFX_DIR_OUT, 357 .def_val = 0x00000000 358 }, 359 { .name = "EQ Band4", 360 .parent_nid = EQUALIZER, 361 .nid = EQUALIZER_BAND_4, 362 .mid = 0x96, 363 .req = 15, 364 .direct = EFX_DIR_OUT, 365 .def_val = 0x00000000 366 }, 367 { .name = "EQ Band5", 368 .parent_nid = EQUALIZER, 369 .nid = EQUALIZER_BAND_5, 370 .mid = 0x96, 371 .req = 16, 372 .direct = EFX_DIR_OUT, 373 .def_val = 0x00000000 374 }, 375 { .name = "EQ Band6", 376 .parent_nid = EQUALIZER, 377 .nid = EQUALIZER_BAND_6, 378 .mid = 0x96, 379 .req = 17, 380 .direct = EFX_DIR_OUT, 381 .def_val = 0x00000000 382 }, 383 { .name = "EQ Band7", 384 .parent_nid = EQUALIZER, 385 .nid = EQUALIZER_BAND_7, 386 .mid = 0x96, 387 .req = 18, 388 .direct = EFX_DIR_OUT, 389 .def_val = 0x00000000 390 }, 391 { .name = "EQ Band8", 392 .parent_nid = EQUALIZER, 393 .nid = EQUALIZER_BAND_8, 394 .mid = 0x96, 395 .req = 19, 396 .direct = EFX_DIR_OUT, 397 .def_val = 0x00000000 398 }, 399 { .name = "EQ Band9", 400 .parent_nid = EQUALIZER, 401 .nid = EQUALIZER_BAND_9, 402 .mid = 0x96, 403 .req = 20, 404 .direct = EFX_DIR_OUT, 405 .def_val = 0x00000000 406 } 407 }; 408 #endif 409 410 /* Voice FX Presets */ 411 #define VOICEFX_MAX_PARAM_COUNT 9 412 413 struct ct_voicefx { 414 char *name; 415 hda_nid_t nid; 416 int mid; 417 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/ 418 }; 419 420 struct ct_voicefx_preset { 421 char *name; /*preset name*/ 422 unsigned int vals[VOICEFX_MAX_PARAM_COUNT]; 423 }; 424 425 static const struct ct_voicefx ca0132_voicefx = { 426 .name = "VoiceFX Capture Switch", 427 .nid = VOICEFX, 428 .mid = 0x95, 429 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18} 430 }; 431 432 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = { 433 { .name = "Neutral", 434 .vals = { 0x00000000, 0x43C80000, 0x44AF0000, 435 0x44FA0000, 0x3F800000, 0x3F800000, 436 0x3F800000, 0x00000000, 0x00000000 } 437 }, 438 { .name = "Female2Male", 439 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 440 0x44FA0000, 0x3F19999A, 0x3F866666, 441 0x3F800000, 0x00000000, 0x00000000 } 442 }, 443 { .name = "Male2Female", 444 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 445 0x450AC000, 0x4017AE14, 0x3F6B851F, 446 0x3F800000, 0x00000000, 0x00000000 } 447 }, 448 { .name = "ScrappyKid", 449 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 450 0x44FA0000, 0x40400000, 0x3F28F5C3, 451 0x3F800000, 0x00000000, 0x00000000 } 452 }, 453 { .name = "Elderly", 454 .vals = { 0x3F800000, 0x44324000, 0x44BB8000, 455 0x44E10000, 0x3FB33333, 0x3FB9999A, 456 0x3F800000, 0x3E3A2E43, 0x00000000 } 457 }, 458 { .name = "Orc", 459 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000, 460 0x45098000, 0x3F266666, 0x3FC00000, 461 0x3F800000, 0x00000000, 0x00000000 } 462 }, 463 { .name = "Elf", 464 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000, 465 0x45193000, 0x3F8E147B, 0x3F75C28F, 466 0x3F800000, 0x00000000, 0x00000000 } 467 }, 468 { .name = "Dwarf", 469 .vals = { 0x3F800000, 0x43930000, 0x44BEE000, 470 0x45007000, 0x3F451EB8, 0x3F7851EC, 471 0x3F800000, 0x00000000, 0x00000000 } 472 }, 473 { .name = "AlienBrute", 474 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF, 475 0x451F6000, 0x3F266666, 0x3FA7D945, 476 0x3F800000, 0x3CF5C28F, 0x00000000 } 477 }, 478 { .name = "Robot", 479 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 480 0x44FA0000, 0x3FB2718B, 0x3F800000, 481 0xBC07010E, 0x00000000, 0x00000000 } 482 }, 483 { .name = "Marine", 484 .vals = { 0x3F800000, 0x43C20000, 0x44906000, 485 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71, 486 0x3F0A3D71, 0x00000000, 0x00000000 } 487 }, 488 { .name = "Emo", 489 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 490 0x44FA0000, 0x3F800000, 0x3F800000, 491 0x3E4CCCCD, 0x00000000, 0x00000000 } 492 }, 493 { .name = "DeepVoice", 494 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF, 495 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA, 496 0x3F800000, 0x00000000, 0x00000000 } 497 }, 498 { .name = "Munchkin", 499 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 500 0x44FA0000, 0x3F800000, 0x3F1A043C, 501 0x3F800000, 0x00000000, 0x00000000 } 502 } 503 }; 504 505 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */ 506 507 #define EQ_PRESET_MAX_PARAM_COUNT 11 508 509 struct ct_eq { 510 char *name; 511 hda_nid_t nid; 512 int mid; 513 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/ 514 }; 515 516 struct ct_eq_preset { 517 char *name; /*preset name*/ 518 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT]; 519 }; 520 521 static const struct ct_eq ca0132_alt_eq_enum = { 522 .name = "FX: Equalizer Preset Switch", 523 .nid = EQ_PRESET_ENUM, 524 .mid = 0x96, 525 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20} 526 }; 527 528 529 static const struct ct_eq_preset ca0132_alt_eq_presets[] = { 530 { .name = "Flat", 531 .vals = { 0x00000000, 0x00000000, 0x00000000, 532 0x00000000, 0x00000000, 0x00000000, 533 0x00000000, 0x00000000, 0x00000000, 534 0x00000000, 0x00000000 } 535 }, 536 { .name = "Acoustic", 537 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD, 538 0x40000000, 0x00000000, 0x00000000, 539 0x00000000, 0x00000000, 0x40000000, 540 0x40000000, 0x40000000 } 541 }, 542 { .name = "Classical", 543 .vals = { 0x00000000, 0x00000000, 0x40C00000, 544 0x40C00000, 0x40466666, 0x00000000, 545 0x00000000, 0x00000000, 0x00000000, 546 0x40466666, 0x40466666 } 547 }, 548 { .name = "Country", 549 .vals = { 0x00000000, 0xBF99999A, 0x00000000, 550 0x3FA66666, 0x3FA66666, 0x3F8CCCCD, 551 0x00000000, 0x00000000, 0x40000000, 552 0x40466666, 0x40800000 } 553 }, 554 { .name = "Dance", 555 .vals = { 0x00000000, 0xBF99999A, 0x40000000, 556 0x40466666, 0x40866666, 0xBF99999A, 557 0xBF99999A, 0x00000000, 0x00000000, 558 0x40800000, 0x40800000 } 559 }, 560 { .name = "Jazz", 561 .vals = { 0x00000000, 0x00000000, 0x00000000, 562 0x3F8CCCCD, 0x40800000, 0x40800000, 563 0x40800000, 0x00000000, 0x3F8CCCCD, 564 0x40466666, 0x40466666 } 565 }, 566 { .name = "New Age", 567 .vals = { 0x00000000, 0x00000000, 0x40000000, 568 0x40000000, 0x00000000, 0x00000000, 569 0x00000000, 0x3F8CCCCD, 0x40000000, 570 0x40000000, 0x40000000 } 571 }, 572 { .name = "Pop", 573 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000, 574 0x40000000, 0x40000000, 0x00000000, 575 0xBF99999A, 0xBF99999A, 0x00000000, 576 0x40466666, 0x40C00000 } 577 }, 578 { .name = "Rock", 579 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A, 580 0x3F8CCCCD, 0x40000000, 0xBF99999A, 581 0xBF99999A, 0x00000000, 0x00000000, 582 0x40800000, 0x40800000 } 583 }, 584 { .name = "Vocal", 585 .vals = { 0x00000000, 0xC0000000, 0xBF99999A, 586 0xBF99999A, 0x00000000, 0x40466666, 587 0x40800000, 0x40466666, 0x00000000, 588 0x00000000, 0x3F8CCCCD } 589 } 590 }; 591 592 /* DSP command sequences for ca0132_alt_select_out */ 593 #define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */ 594 struct ca0132_alt_out_set { 595 char *name; /*preset name*/ 596 unsigned char commands; 597 unsigned int mids[ALT_OUT_SET_MAX_COMMANDS]; 598 unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS]; 599 unsigned int vals[ALT_OUT_SET_MAX_COMMANDS]; 600 }; 601 602 static const struct ca0132_alt_out_set alt_out_presets[] = { 603 { .name = "Line Out", 604 .commands = 7, 605 .mids = { 0x96, 0x96, 0x96, 0x8F, 606 0x96, 0x96, 0x96 }, 607 .reqs = { 0x19, 0x17, 0x18, 0x01, 608 0x1F, 0x15, 0x3A }, 609 .vals = { 0x3F000000, 0x42A00000, 0x00000000, 610 0x00000000, 0x00000000, 0x00000000, 611 0x00000000 } 612 }, 613 { .name = "Headphone", 614 .commands = 7, 615 .mids = { 0x96, 0x96, 0x96, 0x8F, 616 0x96, 0x96, 0x96 }, 617 .reqs = { 0x19, 0x17, 0x18, 0x01, 618 0x1F, 0x15, 0x3A }, 619 .vals = { 0x3F000000, 0x42A00000, 0x00000000, 620 0x00000000, 0x00000000, 0x00000000, 621 0x00000000 } 622 }, 623 { .name = "Surround", 624 .commands = 8, 625 .mids = { 0x96, 0x8F, 0x96, 0x96, 626 0x96, 0x96, 0x96, 0x96 }, 627 .reqs = { 0x18, 0x01, 0x1F, 0x15, 628 0x3A, 0x1A, 0x1B, 0x1C }, 629 .vals = { 0x00000000, 0x00000000, 0x00000000, 630 0x00000000, 0x00000000, 0x00000000, 631 0x00000000, 0x00000000 } 632 } 633 }; 634 635 /* 636 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume, 637 * and I don't know what the third req is, but it's always zero. I assume it's 638 * some sort of update or set command to tell the DSP there's new volume info. 639 */ 640 #define DSP_VOL_OUT 0 641 #define DSP_VOL_IN 1 642 643 struct ct_dsp_volume_ctl { 644 hda_nid_t vnid; 645 int mid; /* module ID*/ 646 unsigned int reqs[3]; /* scp req ID */ 647 }; 648 649 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = { 650 { .vnid = VNID_SPK, 651 .mid = 0x32, 652 .reqs = {3, 4, 2} 653 }, 654 { .vnid = VNID_MIC, 655 .mid = 0x37, 656 .reqs = {2, 3, 1} 657 } 658 }; 659 660 /* Values for ca0113_mmio_command_set for selecting output. */ 661 #define AE5_CA0113_OUT_SET_COMMANDS 6 662 struct ae5_ca0113_output_set { 663 unsigned int group[AE5_CA0113_OUT_SET_COMMANDS]; 664 unsigned int target[AE5_CA0113_OUT_SET_COMMANDS]; 665 unsigned int vals[AE5_CA0113_OUT_SET_COMMANDS]; 666 }; 667 668 static const struct ae5_ca0113_output_set ae5_ca0113_output_presets[] = { 669 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 670 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 671 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f } 672 }, 673 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 674 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 675 .vals = { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } 676 }, 677 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 678 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 679 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f } 680 } 681 }; 682 683 /* ae5 ca0113 command sequences to set headphone gain levels. */ 684 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4 685 struct ae5_headphone_gain_set { 686 char *name; 687 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS]; 688 }; 689 690 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = { 691 { .name = "Low (16-31", 692 .vals = { 0xff, 0x2c, 0xf5, 0x32 } 693 }, 694 { .name = "Medium (32-149", 695 .vals = { 0x38, 0xa8, 0x3e, 0x4c } 696 }, 697 { .name = "High (150-600", 698 .vals = { 0xff, 0xff, 0xff, 0x7f } 699 } 700 }; 701 702 struct ae5_filter_set { 703 char *name; 704 unsigned int val; 705 }; 706 707 static const struct ae5_filter_set ae5_filter_presets[] = { 708 { .name = "Slow Roll Off", 709 .val = 0xa0 710 }, 711 { .name = "Minimum Phase", 712 .val = 0xc0 713 }, 714 { .name = "Fast Roll Off", 715 .val = 0x80 716 } 717 }; 718 719 enum hda_cmd_vendor_io { 720 /* for DspIO node */ 721 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000, 722 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100, 723 724 VENDOR_DSPIO_STATUS = 0xF01, 725 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702, 726 VENDOR_DSPIO_SCP_READ_DATA = 0xF02, 727 VENDOR_DSPIO_DSP_INIT = 0x703, 728 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704, 729 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04, 730 731 /* for ChipIO node */ 732 VENDOR_CHIPIO_ADDRESS_LOW = 0x000, 733 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100, 734 VENDOR_CHIPIO_STREAM_FORMAT = 0x200, 735 VENDOR_CHIPIO_DATA_LOW = 0x300, 736 VENDOR_CHIPIO_DATA_HIGH = 0x400, 737 738 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500, 739 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00, 740 741 VENDOR_CHIPIO_GET_PARAMETER = 0xF00, 742 VENDOR_CHIPIO_STATUS = 0xF01, 743 VENDOR_CHIPIO_HIC_POST_READ = 0x702, 744 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03, 745 746 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707, 747 VENDOR_CHIPIO_8051_DATA_READ = 0xF07, 748 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08, 749 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709, 750 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09, 751 752 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A, 753 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A, 754 755 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C, 756 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C, 757 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D, 758 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E, 759 VENDOR_CHIPIO_FLAG_SET = 0x70F, 760 VENDOR_CHIPIO_FLAGS_GET = 0xF0F, 761 VENDOR_CHIPIO_PARAM_SET = 0x710, 762 VENDOR_CHIPIO_PARAM_GET = 0xF10, 763 764 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711, 765 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712, 766 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12, 767 VENDOR_CHIPIO_PORT_FREE_SET = 0x713, 768 769 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17, 770 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717, 771 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18, 772 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718, 773 774 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788, 775 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88, 776 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789, 777 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89, 778 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A, 779 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A, 780 781 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D 782 }; 783 784 /* 785 * Control flag IDs 786 */ 787 enum control_flag_id { 788 /* Connection manager stream setup is bypassed/enabled */ 789 CONTROL_FLAG_C_MGR = 0, 790 /* DSP DMA is bypassed/enabled */ 791 CONTROL_FLAG_DMA = 1, 792 /* 8051 'idle' mode is disabled/enabled */ 793 CONTROL_FLAG_IDLE_ENABLE = 2, 794 /* Tracker for the SPDIF-in path is bypassed/enabled */ 795 CONTROL_FLAG_TRACKER = 3, 796 /* DigitalOut to Spdif2Out connection is disabled/enabled */ 797 CONTROL_FLAG_SPDIF2OUT = 4, 798 /* Digital Microphone is disabled/enabled */ 799 CONTROL_FLAG_DMIC = 5, 800 /* ADC_B rate is 48 kHz/96 kHz */ 801 CONTROL_FLAG_ADC_B_96KHZ = 6, 802 /* ADC_C rate is 48 kHz/96 kHz */ 803 CONTROL_FLAG_ADC_C_96KHZ = 7, 804 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */ 805 CONTROL_FLAG_DAC_96KHZ = 8, 806 /* DSP rate is 48 kHz/96 kHz */ 807 CONTROL_FLAG_DSP_96KHZ = 9, 808 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */ 809 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10, 810 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */ 811 CONTROL_FLAG_SRC_RATE_96KHZ = 11, 812 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */ 813 CONTROL_FLAG_DECODE_LOOP = 12, 814 /* De-emphasis filter on DAC-1 disabled/enabled */ 815 CONTROL_FLAG_DAC1_DEEMPHASIS = 13, 816 /* De-emphasis filter on DAC-2 disabled/enabled */ 817 CONTROL_FLAG_DAC2_DEEMPHASIS = 14, 818 /* De-emphasis filter on DAC-3 disabled/enabled */ 819 CONTROL_FLAG_DAC3_DEEMPHASIS = 15, 820 /* High-pass filter on ADC_B disabled/enabled */ 821 CONTROL_FLAG_ADC_B_HIGH_PASS = 16, 822 /* High-pass filter on ADC_C disabled/enabled */ 823 CONTROL_FLAG_ADC_C_HIGH_PASS = 17, 824 /* Common mode on Port_A disabled/enabled */ 825 CONTROL_FLAG_PORT_A_COMMON_MODE = 18, 826 /* Common mode on Port_D disabled/enabled */ 827 CONTROL_FLAG_PORT_D_COMMON_MODE = 19, 828 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */ 829 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20, 830 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */ 831 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21, 832 /* ASI rate is 48kHz/96kHz */ 833 CONTROL_FLAG_ASI_96KHZ = 22, 834 /* DAC power settings able to control attached ports no/yes */ 835 CONTROL_FLAG_DACS_CONTROL_PORTS = 23, 836 /* Clock Stop OK reporting is disabled/enabled */ 837 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24, 838 /* Number of control flags */ 839 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1) 840 }; 841 842 /* 843 * Control parameter IDs 844 */ 845 enum control_param_id { 846 /* 0: None, 1: Mic1In*/ 847 CONTROL_PARAM_VIP_SOURCE = 1, 848 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */ 849 CONTROL_PARAM_SPDIF1_SOURCE = 2, 850 /* Port A output stage gain setting to use when 16 Ohm output 851 * impedance is selected*/ 852 CONTROL_PARAM_PORTA_160OHM_GAIN = 8, 853 /* Port D output stage gain setting to use when 16 Ohm output 854 * impedance is selected*/ 855 CONTROL_PARAM_PORTD_160OHM_GAIN = 10, 856 857 /* 858 * This control param name was found in the 8051 memory, and makes 859 * sense given the fact the AE-5 uses it and has the ASI flag set. 860 */ 861 CONTROL_PARAM_ASI = 23, 862 863 /* Stream Control */ 864 865 /* Select stream with the given ID */ 866 CONTROL_PARAM_STREAM_ID = 24, 867 /* Source connection point for the selected stream */ 868 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25, 869 /* Destination connection point for the selected stream */ 870 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26, 871 /* Number of audio channels in the selected stream */ 872 CONTROL_PARAM_STREAMS_CHANNELS = 27, 873 /*Enable control for the selected stream */ 874 CONTROL_PARAM_STREAM_CONTROL = 28, 875 876 /* Connection Point Control */ 877 878 /* Select connection point with the given ID */ 879 CONTROL_PARAM_CONN_POINT_ID = 29, 880 /* Connection point sample rate */ 881 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30, 882 883 /* Node Control */ 884 885 /* Select HDA node with the given ID */ 886 CONTROL_PARAM_NODE_ID = 31 887 }; 888 889 /* 890 * Dsp Io Status codes 891 */ 892 enum hda_vendor_status_dspio { 893 /* Success */ 894 VENDOR_STATUS_DSPIO_OK = 0x00, 895 /* Busy, unable to accept new command, the host must retry */ 896 VENDOR_STATUS_DSPIO_BUSY = 0x01, 897 /* SCP command queue is full */ 898 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02, 899 /* SCP response queue is empty */ 900 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03 901 }; 902 903 /* 904 * Chip Io Status codes 905 */ 906 enum hda_vendor_status_chipio { 907 /* Success */ 908 VENDOR_STATUS_CHIPIO_OK = 0x00, 909 /* Busy, unable to accept new command, the host must retry */ 910 VENDOR_STATUS_CHIPIO_BUSY = 0x01 911 }; 912 913 /* 914 * CA0132 sample rate 915 */ 916 enum ca0132_sample_rate { 917 SR_6_000 = 0x00, 918 SR_8_000 = 0x01, 919 SR_9_600 = 0x02, 920 SR_11_025 = 0x03, 921 SR_16_000 = 0x04, 922 SR_22_050 = 0x05, 923 SR_24_000 = 0x06, 924 SR_32_000 = 0x07, 925 SR_44_100 = 0x08, 926 SR_48_000 = 0x09, 927 SR_88_200 = 0x0A, 928 SR_96_000 = 0x0B, 929 SR_144_000 = 0x0C, 930 SR_176_400 = 0x0D, 931 SR_192_000 = 0x0E, 932 SR_384_000 = 0x0F, 933 934 SR_COUNT = 0x10, 935 936 SR_RATE_UNKNOWN = 0x1F 937 }; 938 939 enum dsp_download_state { 940 DSP_DOWNLOAD_FAILED = -1, 941 DSP_DOWNLOAD_INIT = 0, 942 DSP_DOWNLOADING = 1, 943 DSP_DOWNLOADED = 2 944 }; 945 946 /* retrieve parameters from hda format */ 947 #define get_hdafmt_chs(fmt) (fmt & 0xf) 948 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7) 949 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f) 950 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1) 951 952 /* 953 * CA0132 specific 954 */ 955 956 struct ca0132_spec { 957 const struct snd_kcontrol_new *mixers[5]; 958 unsigned int num_mixers; 959 const struct hda_verb *base_init_verbs; 960 const struct hda_verb *base_exit_verbs; 961 const struct hda_verb *chip_init_verbs; 962 const struct hda_verb *desktop_init_verbs; 963 struct hda_verb *spec_init_verbs; 964 struct auto_pin_cfg autocfg; 965 966 /* Nodes configurations */ 967 struct hda_multi_out multiout; 968 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS]; 969 hda_nid_t dacs[AUTO_CFG_MAX_OUTS]; 970 unsigned int num_outputs; 971 hda_nid_t input_pins[AUTO_PIN_LAST]; 972 hda_nid_t adcs[AUTO_PIN_LAST]; 973 hda_nid_t dig_out; 974 hda_nid_t dig_in; 975 unsigned int num_inputs; 976 hda_nid_t shared_mic_nid; 977 hda_nid_t shared_out_nid; 978 hda_nid_t unsol_tag_hp; 979 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */ 980 hda_nid_t unsol_tag_amic1; 981 982 /* chip access */ 983 struct mutex chipio_mutex; /* chip access mutex */ 984 u32 curr_chip_addx; 985 986 /* DSP download related */ 987 enum dsp_download_state dsp_state; 988 unsigned int dsp_stream_id; 989 unsigned int wait_scp; 990 unsigned int wait_scp_header; 991 unsigned int wait_num_data; 992 unsigned int scp_resp_header; 993 unsigned int scp_resp_data[4]; 994 unsigned int scp_resp_count; 995 bool startup_check_entered; 996 bool dsp_reload; 997 998 /* mixer and effects related */ 999 unsigned char dmic_ctl; 1000 int cur_out_type; 1001 int cur_mic_type; 1002 long vnode_lvol[VNODES_COUNT]; 1003 long vnode_rvol[VNODES_COUNT]; 1004 long vnode_lswitch[VNODES_COUNT]; 1005 long vnode_rswitch[VNODES_COUNT]; 1006 long effects_switch[EFFECTS_COUNT]; 1007 long voicefx_val; 1008 long cur_mic_boost; 1009 /* ca0132_alt control related values */ 1010 unsigned char in_enum_val; 1011 unsigned char out_enum_val; 1012 unsigned char mic_boost_enum_val; 1013 unsigned char smart_volume_setting; 1014 long fx_ctl_val[EFFECT_LEVEL_SLIDERS]; 1015 long xbass_xover_freq; 1016 long eq_preset_val; 1017 unsigned int tlv[4]; 1018 struct hda_vmaster_mute_hook vmaster_mute; 1019 /* AE-5 Control values */ 1020 unsigned char ae5_headphone_gain_val; 1021 unsigned char ae5_filter_val; 1022 /* ZxR Control Values */ 1023 unsigned char zxr_gain_set; 1024 1025 struct hda_codec *codec; 1026 struct delayed_work unsol_hp_work; 1027 int quirk; 1028 1029 #ifdef ENABLE_TUNING_CONTROLS 1030 long cur_ctl_vals[TUNING_CTLS_COUNT]; 1031 #endif 1032 /* 1033 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster 1034 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown 1035 * things. 1036 */ 1037 bool use_pci_mmio; 1038 void __iomem *mem_base; 1039 1040 /* 1041 * Whether or not to use the alt functions like alt_select_out, 1042 * alt_select_in, etc. Only used on desktop codecs for now, because of 1043 * surround sound support. 1044 */ 1045 bool use_alt_functions; 1046 1047 /* 1048 * Whether or not to use alt controls: volume effect sliders, EQ 1049 * presets, smart volume presets, and new control names with FX prefix. 1050 * Renames PlayEnhancement and CrystalVoice too. 1051 */ 1052 bool use_alt_controls; 1053 }; 1054 1055 /* 1056 * CA0132 quirks table 1057 */ 1058 enum { 1059 QUIRK_NONE, 1060 QUIRK_ALIENWARE, 1061 QUIRK_ALIENWARE_M17XR4, 1062 QUIRK_SBZ, 1063 QUIRK_ZXR, 1064 QUIRK_ZXR_DBPRO, 1065 QUIRK_R3DI, 1066 QUIRK_R3D, 1067 QUIRK_AE5, 1068 }; 1069 1070 #ifdef CONFIG_PCI 1071 #define ca0132_quirk(spec) ((spec)->quirk) 1072 #define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio) 1073 #define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions) 1074 #define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls) 1075 #else 1076 #define ca0132_quirk(spec) ({ (void)(spec); QUIRK_NONE; }) 1077 #define ca0132_use_alt_functions(spec) ({ (void)(spec); false; }) 1078 #define ca0132_use_pci_mmio(spec) ({ (void)(spec); false; }) 1079 #define ca0132_use_alt_controls(spec) ({ (void)(spec); false; }) 1080 #endif 1081 1082 static const struct hda_pintbl alienware_pincfgs[] = { 1083 { 0x0b, 0x90170110 }, /* Builtin Speaker */ 1084 { 0x0c, 0x411111f0 }, /* N/A */ 1085 { 0x0d, 0x411111f0 }, /* N/A */ 1086 { 0x0e, 0x411111f0 }, /* N/A */ 1087 { 0x0f, 0x0321101f }, /* HP */ 1088 { 0x10, 0x411111f0 }, /* Headset? disabled for now */ 1089 { 0x11, 0x03a11021 }, /* Mic */ 1090 { 0x12, 0xd5a30140 }, /* Builtin Mic */ 1091 { 0x13, 0x411111f0 }, /* N/A */ 1092 { 0x18, 0x411111f0 }, /* N/A */ 1093 {} 1094 }; 1095 1096 /* Sound Blaster Z pin configs taken from Windows Driver */ 1097 static const struct hda_pintbl sbz_pincfgs[] = { 1098 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1099 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1100 { 0x0d, 0x014510f0 }, /* Digital Out */ 1101 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1102 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */ 1103 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1104 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1105 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1106 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1107 { 0x18, 0x50d000f0 }, /* N/A */ 1108 {} 1109 }; 1110 1111 /* Sound Blaster ZxR pin configs taken from Windows Driver */ 1112 static const struct hda_pintbl zxr_pincfgs[] = { 1113 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */ 1114 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/ 1115 { 0x0d, 0x014510f0 }, /* Digital Out */ 1116 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/ 1117 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */ 1118 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */ 1119 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */ 1120 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */ 1121 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1122 { 0x18, 0x50d000f0 }, /* N/A */ 1123 {} 1124 }; 1125 1126 /* Recon3D pin configs taken from Windows Driver */ 1127 static const struct hda_pintbl r3d_pincfgs[] = { 1128 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1129 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1130 { 0x0d, 0x014510f0 }, /* Digital Out */ 1131 { 0x0e, 0x01c520f0 }, /* SPDIF In */ 1132 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1133 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1134 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1135 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1136 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1137 { 0x18, 0x50d000f0 }, /* N/A */ 1138 {} 1139 }; 1140 1141 /* Sound Blaster AE-5 pin configs taken from Windows Driver */ 1142 static const struct hda_pintbl ae5_pincfgs[] = { 1143 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1144 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1145 { 0x0d, 0x014510f0 }, /* Digital Out */ 1146 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1147 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */ 1148 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1149 { 0x11, 0x01a170ff }, /* Port B -- LineMicIn2 / Rear Headphone */ 1150 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1151 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1152 { 0x18, 0x50d000f0 }, /* N/A */ 1153 {} 1154 }; 1155 1156 /* Recon3D integrated pin configs taken from Windows Driver */ 1157 static const struct hda_pintbl r3di_pincfgs[] = { 1158 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1159 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1160 { 0x0d, 0x014510f0 }, /* Digital Out */ 1161 { 0x0e, 0x41c520f0 }, /* SPDIF In */ 1162 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1163 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1164 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1165 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1166 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1167 { 0x18, 0x500000f0 }, /* N/A */ 1168 {} 1169 }; 1170 1171 static const struct snd_pci_quirk ca0132_quirks[] = { 1172 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4), 1173 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE), 1174 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE), 1175 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE), 1176 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ), 1177 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ), 1178 SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ), 1179 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ), 1180 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI), 1181 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI), 1182 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI), 1183 SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI), 1184 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D), 1185 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5), 1186 {} 1187 }; 1188 1189 /* 1190 * CA0132 codec access 1191 */ 1192 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid, 1193 unsigned int verb, unsigned int parm, unsigned int *res) 1194 { 1195 unsigned int response; 1196 response = snd_hda_codec_read(codec, nid, 0, verb, parm); 1197 *res = response; 1198 1199 return ((response == -1) ? -1 : 0); 1200 } 1201 1202 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid, 1203 unsigned short converter_format, unsigned int *res) 1204 { 1205 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT, 1206 converter_format & 0xffff, res); 1207 } 1208 1209 static int codec_set_converter_stream_channel(struct hda_codec *codec, 1210 hda_nid_t nid, unsigned char stream, 1211 unsigned char channel, unsigned int *res) 1212 { 1213 unsigned char converter_stream_channel = 0; 1214 1215 converter_stream_channel = (stream << 4) | (channel & 0x0f); 1216 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID, 1217 converter_stream_channel, res); 1218 } 1219 1220 /* Chip access helper function */ 1221 static int chipio_send(struct hda_codec *codec, 1222 unsigned int reg, 1223 unsigned int data) 1224 { 1225 unsigned int res; 1226 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1227 1228 /* send bits of data specified by reg */ 1229 do { 1230 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1231 reg, data); 1232 if (res == VENDOR_STATUS_CHIPIO_OK) 1233 return 0; 1234 msleep(20); 1235 } while (time_before(jiffies, timeout)); 1236 1237 return -EIO; 1238 } 1239 1240 /* 1241 * Write chip address through the vendor widget -- NOT protected by the Mutex! 1242 */ 1243 static int chipio_write_address(struct hda_codec *codec, 1244 unsigned int chip_addx) 1245 { 1246 struct ca0132_spec *spec = codec->spec; 1247 int res; 1248 1249 if (spec->curr_chip_addx == chip_addx) 1250 return 0; 1251 1252 /* send low 16 bits of the address */ 1253 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW, 1254 chip_addx & 0xffff); 1255 1256 if (res != -EIO) { 1257 /* send high 16 bits of the address */ 1258 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH, 1259 chip_addx >> 16); 1260 } 1261 1262 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx; 1263 1264 return res; 1265 } 1266 1267 /* 1268 * Write data through the vendor widget -- NOT protected by the Mutex! 1269 */ 1270 static int chipio_write_data(struct hda_codec *codec, unsigned int data) 1271 { 1272 struct ca0132_spec *spec = codec->spec; 1273 int res; 1274 1275 /* send low 16 bits of the data */ 1276 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff); 1277 1278 if (res != -EIO) { 1279 /* send high 16 bits of the data */ 1280 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH, 1281 data >> 16); 1282 } 1283 1284 /*If no error encountered, automatically increment the address 1285 as per chip behaviour*/ 1286 spec->curr_chip_addx = (res != -EIO) ? 1287 (spec->curr_chip_addx + 4) : ~0U; 1288 return res; 1289 } 1290 1291 /* 1292 * Write multiple data through the vendor widget -- NOT protected by the Mutex! 1293 */ 1294 static int chipio_write_data_multiple(struct hda_codec *codec, 1295 const u32 *data, 1296 unsigned int count) 1297 { 1298 int status = 0; 1299 1300 if (data == NULL) { 1301 codec_dbg(codec, "chipio_write_data null ptr\n"); 1302 return -EINVAL; 1303 } 1304 1305 while ((count-- != 0) && (status == 0)) 1306 status = chipio_write_data(codec, *data++); 1307 1308 return status; 1309 } 1310 1311 1312 /* 1313 * Read data through the vendor widget -- NOT protected by the Mutex! 1314 */ 1315 static int chipio_read_data(struct hda_codec *codec, unsigned int *data) 1316 { 1317 struct ca0132_spec *spec = codec->spec; 1318 int res; 1319 1320 /* post read */ 1321 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0); 1322 1323 if (res != -EIO) { 1324 /* read status */ 1325 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 1326 } 1327 1328 if (res != -EIO) { 1329 /* read data */ 1330 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1331 VENDOR_CHIPIO_HIC_READ_DATA, 1332 0); 1333 } 1334 1335 /*If no error encountered, automatically increment the address 1336 as per chip behaviour*/ 1337 spec->curr_chip_addx = (res != -EIO) ? 1338 (spec->curr_chip_addx + 4) : ~0U; 1339 return res; 1340 } 1341 1342 /* 1343 * Write given value to the given address through the chip I/O widget. 1344 * protected by the Mutex 1345 */ 1346 static int chipio_write(struct hda_codec *codec, 1347 unsigned int chip_addx, const unsigned int data) 1348 { 1349 struct ca0132_spec *spec = codec->spec; 1350 int err; 1351 1352 mutex_lock(&spec->chipio_mutex); 1353 1354 /* write the address, and if successful proceed to write data */ 1355 err = chipio_write_address(codec, chip_addx); 1356 if (err < 0) 1357 goto exit; 1358 1359 err = chipio_write_data(codec, data); 1360 if (err < 0) 1361 goto exit; 1362 1363 exit: 1364 mutex_unlock(&spec->chipio_mutex); 1365 return err; 1366 } 1367 1368 /* 1369 * Write given value to the given address through the chip I/O widget. 1370 * not protected by the Mutex 1371 */ 1372 static int chipio_write_no_mutex(struct hda_codec *codec, 1373 unsigned int chip_addx, const unsigned int data) 1374 { 1375 int err; 1376 1377 1378 /* write the address, and if successful proceed to write data */ 1379 err = chipio_write_address(codec, chip_addx); 1380 if (err < 0) 1381 goto exit; 1382 1383 err = chipio_write_data(codec, data); 1384 if (err < 0) 1385 goto exit; 1386 1387 exit: 1388 return err; 1389 } 1390 1391 /* 1392 * Write multiple values to the given address through the chip I/O widget. 1393 * protected by the Mutex 1394 */ 1395 static int chipio_write_multiple(struct hda_codec *codec, 1396 u32 chip_addx, 1397 const u32 *data, 1398 unsigned int count) 1399 { 1400 struct ca0132_spec *spec = codec->spec; 1401 int status; 1402 1403 mutex_lock(&spec->chipio_mutex); 1404 status = chipio_write_address(codec, chip_addx); 1405 if (status < 0) 1406 goto error; 1407 1408 status = chipio_write_data_multiple(codec, data, count); 1409 error: 1410 mutex_unlock(&spec->chipio_mutex); 1411 1412 return status; 1413 } 1414 1415 /* 1416 * Read the given address through the chip I/O widget 1417 * protected by the Mutex 1418 */ 1419 static int chipio_read(struct hda_codec *codec, 1420 unsigned int chip_addx, unsigned int *data) 1421 { 1422 struct ca0132_spec *spec = codec->spec; 1423 int err; 1424 1425 mutex_lock(&spec->chipio_mutex); 1426 1427 /* write the address, and if successful proceed to write data */ 1428 err = chipio_write_address(codec, chip_addx); 1429 if (err < 0) 1430 goto exit; 1431 1432 err = chipio_read_data(codec, data); 1433 if (err < 0) 1434 goto exit; 1435 1436 exit: 1437 mutex_unlock(&spec->chipio_mutex); 1438 return err; 1439 } 1440 1441 /* 1442 * Set chip control flags through the chip I/O widget. 1443 */ 1444 static void chipio_set_control_flag(struct hda_codec *codec, 1445 enum control_flag_id flag_id, 1446 bool flag_state) 1447 { 1448 unsigned int val; 1449 unsigned int flag_bit; 1450 1451 flag_bit = (flag_state ? 1 : 0); 1452 val = (flag_bit << 7) | (flag_id); 1453 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1454 VENDOR_CHIPIO_FLAG_SET, val); 1455 } 1456 1457 /* 1458 * Set chip parameters through the chip I/O widget. 1459 */ 1460 static void chipio_set_control_param(struct hda_codec *codec, 1461 enum control_param_id param_id, int param_val) 1462 { 1463 struct ca0132_spec *spec = codec->spec; 1464 int val; 1465 1466 if ((param_id < 32) && (param_val < 8)) { 1467 val = (param_val << 5) | (param_id); 1468 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1469 VENDOR_CHIPIO_PARAM_SET, val); 1470 } else { 1471 mutex_lock(&spec->chipio_mutex); 1472 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1473 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1474 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1475 param_id); 1476 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1477 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1478 param_val); 1479 } 1480 mutex_unlock(&spec->chipio_mutex); 1481 } 1482 } 1483 1484 /* 1485 * Set chip parameters through the chip I/O widget. NO MUTEX. 1486 */ 1487 static void chipio_set_control_param_no_mutex(struct hda_codec *codec, 1488 enum control_param_id param_id, int param_val) 1489 { 1490 int val; 1491 1492 if ((param_id < 32) && (param_val < 8)) { 1493 val = (param_val << 5) | (param_id); 1494 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1495 VENDOR_CHIPIO_PARAM_SET, val); 1496 } else { 1497 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1498 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1499 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1500 param_id); 1501 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1502 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1503 param_val); 1504 } 1505 } 1506 } 1507 /* 1508 * Connect stream to a source point, and then connect 1509 * that source point to a destination point. 1510 */ 1511 static void chipio_set_stream_source_dest(struct hda_codec *codec, 1512 int streamid, int source_point, int dest_point) 1513 { 1514 chipio_set_control_param_no_mutex(codec, 1515 CONTROL_PARAM_STREAM_ID, streamid); 1516 chipio_set_control_param_no_mutex(codec, 1517 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point); 1518 chipio_set_control_param_no_mutex(codec, 1519 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point); 1520 } 1521 1522 /* 1523 * Set number of channels in the selected stream. 1524 */ 1525 static void chipio_set_stream_channels(struct hda_codec *codec, 1526 int streamid, unsigned int channels) 1527 { 1528 chipio_set_control_param_no_mutex(codec, 1529 CONTROL_PARAM_STREAM_ID, streamid); 1530 chipio_set_control_param_no_mutex(codec, 1531 CONTROL_PARAM_STREAMS_CHANNELS, channels); 1532 } 1533 1534 /* 1535 * Enable/Disable audio stream. 1536 */ 1537 static void chipio_set_stream_control(struct hda_codec *codec, 1538 int streamid, int enable) 1539 { 1540 chipio_set_control_param_no_mutex(codec, 1541 CONTROL_PARAM_STREAM_ID, streamid); 1542 chipio_set_control_param_no_mutex(codec, 1543 CONTROL_PARAM_STREAM_CONTROL, enable); 1544 } 1545 1546 1547 /* 1548 * Set sampling rate of the connection point. NO MUTEX. 1549 */ 1550 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec, 1551 int connid, enum ca0132_sample_rate rate) 1552 { 1553 chipio_set_control_param_no_mutex(codec, 1554 CONTROL_PARAM_CONN_POINT_ID, connid); 1555 chipio_set_control_param_no_mutex(codec, 1556 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate); 1557 } 1558 1559 /* 1560 * Set sampling rate of the connection point. 1561 */ 1562 static void chipio_set_conn_rate(struct hda_codec *codec, 1563 int connid, enum ca0132_sample_rate rate) 1564 { 1565 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid); 1566 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, 1567 rate); 1568 } 1569 1570 /* 1571 * Writes to the 8051's internal address space directly instead of indirectly, 1572 * giving access to the special function registers located at addresses 1573 * 0x80-0xFF. 1574 */ 1575 static void chipio_8051_write_direct(struct hda_codec *codec, 1576 unsigned int addr, unsigned int data) 1577 { 1578 unsigned int verb; 1579 1580 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data; 1581 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr); 1582 } 1583 1584 /* 1585 * Enable clocks. 1586 */ 1587 static void chipio_enable_clocks(struct hda_codec *codec) 1588 { 1589 struct ca0132_spec *spec = codec->spec; 1590 1591 mutex_lock(&spec->chipio_mutex); 1592 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1593 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0); 1594 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1595 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); 1596 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1597 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5); 1598 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1599 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b); 1600 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1601 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6); 1602 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1603 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); 1604 mutex_unlock(&spec->chipio_mutex); 1605 } 1606 1607 /* 1608 * CA0132 DSP IO stuffs 1609 */ 1610 static int dspio_send(struct hda_codec *codec, unsigned int reg, 1611 unsigned int data) 1612 { 1613 int res; 1614 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1615 1616 /* send bits of data specified by reg to dsp */ 1617 do { 1618 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data); 1619 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY)) 1620 return res; 1621 msleep(20); 1622 } while (time_before(jiffies, timeout)); 1623 1624 return -EIO; 1625 } 1626 1627 /* 1628 * Wait for DSP to be ready for commands 1629 */ 1630 static void dspio_write_wait(struct hda_codec *codec) 1631 { 1632 int status; 1633 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1634 1635 do { 1636 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1637 VENDOR_DSPIO_STATUS, 0); 1638 if ((status == VENDOR_STATUS_DSPIO_OK) || 1639 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)) 1640 break; 1641 msleep(1); 1642 } while (time_before(jiffies, timeout)); 1643 } 1644 1645 /* 1646 * Write SCP data to DSP 1647 */ 1648 static int dspio_write(struct hda_codec *codec, unsigned int scp_data) 1649 { 1650 struct ca0132_spec *spec = codec->spec; 1651 int status; 1652 1653 dspio_write_wait(codec); 1654 1655 mutex_lock(&spec->chipio_mutex); 1656 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW, 1657 scp_data & 0xffff); 1658 if (status < 0) 1659 goto error; 1660 1661 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH, 1662 scp_data >> 16); 1663 if (status < 0) 1664 goto error; 1665 1666 /* OK, now check if the write itself has executed*/ 1667 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1668 VENDOR_DSPIO_STATUS, 0); 1669 error: 1670 mutex_unlock(&spec->chipio_mutex); 1671 1672 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ? 1673 -EIO : 0; 1674 } 1675 1676 /* 1677 * Write multiple SCP data to DSP 1678 */ 1679 static int dspio_write_multiple(struct hda_codec *codec, 1680 unsigned int *buffer, unsigned int size) 1681 { 1682 int status = 0; 1683 unsigned int count; 1684 1685 if (buffer == NULL) 1686 return -EINVAL; 1687 1688 count = 0; 1689 while (count < size) { 1690 status = dspio_write(codec, *buffer++); 1691 if (status != 0) 1692 break; 1693 count++; 1694 } 1695 1696 return status; 1697 } 1698 1699 static int dspio_read(struct hda_codec *codec, unsigned int *data) 1700 { 1701 int status; 1702 1703 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0); 1704 if (status == -EIO) 1705 return status; 1706 1707 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0); 1708 if (status == -EIO || 1709 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY) 1710 return -EIO; 1711 1712 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1713 VENDOR_DSPIO_SCP_READ_DATA, 0); 1714 1715 return 0; 1716 } 1717 1718 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer, 1719 unsigned int *buf_size, unsigned int size_count) 1720 { 1721 int status = 0; 1722 unsigned int size = *buf_size; 1723 unsigned int count; 1724 unsigned int skip_count; 1725 unsigned int dummy; 1726 1727 if (buffer == NULL) 1728 return -1; 1729 1730 count = 0; 1731 while (count < size && count < size_count) { 1732 status = dspio_read(codec, buffer++); 1733 if (status != 0) 1734 break; 1735 count++; 1736 } 1737 1738 skip_count = count; 1739 if (status == 0) { 1740 while (skip_count < size) { 1741 status = dspio_read(codec, &dummy); 1742 if (status != 0) 1743 break; 1744 skip_count++; 1745 } 1746 } 1747 *buf_size = count; 1748 1749 return status; 1750 } 1751 1752 /* 1753 * Construct the SCP header using corresponding fields 1754 */ 1755 static inline unsigned int 1756 make_scp_header(unsigned int target_id, unsigned int source_id, 1757 unsigned int get_flag, unsigned int req, 1758 unsigned int device_flag, unsigned int resp_flag, 1759 unsigned int error_flag, unsigned int data_size) 1760 { 1761 unsigned int header = 0; 1762 1763 header = (data_size & 0x1f) << 27; 1764 header |= (error_flag & 0x01) << 26; 1765 header |= (resp_flag & 0x01) << 25; 1766 header |= (device_flag & 0x01) << 24; 1767 header |= (req & 0x7f) << 17; 1768 header |= (get_flag & 0x01) << 16; 1769 header |= (source_id & 0xff) << 8; 1770 header |= target_id & 0xff; 1771 1772 return header; 1773 } 1774 1775 /* 1776 * Extract corresponding fields from SCP header 1777 */ 1778 static inline void 1779 extract_scp_header(unsigned int header, 1780 unsigned int *target_id, unsigned int *source_id, 1781 unsigned int *get_flag, unsigned int *req, 1782 unsigned int *device_flag, unsigned int *resp_flag, 1783 unsigned int *error_flag, unsigned int *data_size) 1784 { 1785 if (data_size) 1786 *data_size = (header >> 27) & 0x1f; 1787 if (error_flag) 1788 *error_flag = (header >> 26) & 0x01; 1789 if (resp_flag) 1790 *resp_flag = (header >> 25) & 0x01; 1791 if (device_flag) 1792 *device_flag = (header >> 24) & 0x01; 1793 if (req) 1794 *req = (header >> 17) & 0x7f; 1795 if (get_flag) 1796 *get_flag = (header >> 16) & 0x01; 1797 if (source_id) 1798 *source_id = (header >> 8) & 0xff; 1799 if (target_id) 1800 *target_id = header & 0xff; 1801 } 1802 1803 #define SCP_MAX_DATA_WORDS (16) 1804 1805 /* Structure to contain any SCP message */ 1806 struct scp_msg { 1807 unsigned int hdr; 1808 unsigned int data[SCP_MAX_DATA_WORDS]; 1809 }; 1810 1811 static void dspio_clear_response_queue(struct hda_codec *codec) 1812 { 1813 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1814 unsigned int dummy = 0; 1815 int status; 1816 1817 /* clear all from the response queue */ 1818 do { 1819 status = dspio_read(codec, &dummy); 1820 } while (status == 0 && time_before(jiffies, timeout)); 1821 } 1822 1823 static int dspio_get_response_data(struct hda_codec *codec) 1824 { 1825 struct ca0132_spec *spec = codec->spec; 1826 unsigned int data = 0; 1827 unsigned int count; 1828 1829 if (dspio_read(codec, &data) < 0) 1830 return -EIO; 1831 1832 if ((data & 0x00ffffff) == spec->wait_scp_header) { 1833 spec->scp_resp_header = data; 1834 spec->scp_resp_count = data >> 27; 1835 count = spec->wait_num_data; 1836 dspio_read_multiple(codec, spec->scp_resp_data, 1837 &spec->scp_resp_count, count); 1838 return 0; 1839 } 1840 1841 return -EIO; 1842 } 1843 1844 /* 1845 * Send SCP message to DSP 1846 */ 1847 static int dspio_send_scp_message(struct hda_codec *codec, 1848 unsigned char *send_buf, 1849 unsigned int send_buf_size, 1850 unsigned char *return_buf, 1851 unsigned int return_buf_size, 1852 unsigned int *bytes_returned) 1853 { 1854 struct ca0132_spec *spec = codec->spec; 1855 int status = -1; 1856 unsigned int scp_send_size = 0; 1857 unsigned int total_size; 1858 bool waiting_for_resp = false; 1859 unsigned int header; 1860 struct scp_msg *ret_msg; 1861 unsigned int resp_src_id, resp_target_id; 1862 unsigned int data_size, src_id, target_id, get_flag, device_flag; 1863 1864 if (bytes_returned) 1865 *bytes_returned = 0; 1866 1867 /* get scp header from buffer */ 1868 header = *((unsigned int *)send_buf); 1869 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL, 1870 &device_flag, NULL, NULL, &data_size); 1871 scp_send_size = data_size + 1; 1872 total_size = (scp_send_size * 4); 1873 1874 if (send_buf_size < total_size) 1875 return -EINVAL; 1876 1877 if (get_flag || device_flag) { 1878 if (!return_buf || return_buf_size < 4 || !bytes_returned) 1879 return -EINVAL; 1880 1881 spec->wait_scp_header = *((unsigned int *)send_buf); 1882 1883 /* swap source id with target id */ 1884 resp_target_id = src_id; 1885 resp_src_id = target_id; 1886 spec->wait_scp_header &= 0xffff0000; 1887 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id); 1888 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1; 1889 spec->wait_scp = 1; 1890 waiting_for_resp = true; 1891 } 1892 1893 status = dspio_write_multiple(codec, (unsigned int *)send_buf, 1894 scp_send_size); 1895 if (status < 0) { 1896 spec->wait_scp = 0; 1897 return status; 1898 } 1899 1900 if (waiting_for_resp) { 1901 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1902 memset(return_buf, 0, return_buf_size); 1903 do { 1904 msleep(20); 1905 } while (spec->wait_scp && time_before(jiffies, timeout)); 1906 waiting_for_resp = false; 1907 if (!spec->wait_scp) { 1908 ret_msg = (struct scp_msg *)return_buf; 1909 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4); 1910 memcpy(&ret_msg->data, spec->scp_resp_data, 1911 spec->wait_num_data); 1912 *bytes_returned = (spec->scp_resp_count + 1) * 4; 1913 status = 0; 1914 } else { 1915 status = -EIO; 1916 } 1917 spec->wait_scp = 0; 1918 } 1919 1920 return status; 1921 } 1922 1923 /** 1924 * Prepare and send the SCP message to DSP 1925 * @codec: the HDA codec 1926 * @mod_id: ID of the DSP module to send the command 1927 * @src_id: ID of the source 1928 * @req: ID of request to send to the DSP module 1929 * @dir: SET or GET 1930 * @data: pointer to the data to send with the request, request specific 1931 * @len: length of the data, in bytes 1932 * @reply: point to the buffer to hold data returned for a reply 1933 * @reply_len: length of the reply buffer returned from GET 1934 * 1935 * Returns zero or a negative error code. 1936 */ 1937 static int dspio_scp(struct hda_codec *codec, 1938 int mod_id, int src_id, int req, int dir, const void *data, 1939 unsigned int len, void *reply, unsigned int *reply_len) 1940 { 1941 int status = 0; 1942 struct scp_msg scp_send, scp_reply; 1943 unsigned int ret_bytes, send_size, ret_size; 1944 unsigned int send_get_flag, reply_resp_flag, reply_error_flag; 1945 unsigned int reply_data_size; 1946 1947 memset(&scp_send, 0, sizeof(scp_send)); 1948 memset(&scp_reply, 0, sizeof(scp_reply)); 1949 1950 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS)) 1951 return -EINVAL; 1952 1953 if (dir == SCP_GET && reply == NULL) { 1954 codec_dbg(codec, "dspio_scp get but has no buffer\n"); 1955 return -EINVAL; 1956 } 1957 1958 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) { 1959 codec_dbg(codec, "dspio_scp bad resp buf len parms\n"); 1960 return -EINVAL; 1961 } 1962 1963 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req, 1964 0, 0, 0, len/sizeof(unsigned int)); 1965 if (data != NULL && len > 0) { 1966 len = min((unsigned int)(sizeof(scp_send.data)), len); 1967 memcpy(scp_send.data, data, len); 1968 } 1969 1970 ret_bytes = 0; 1971 send_size = sizeof(unsigned int) + len; 1972 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send, 1973 send_size, (unsigned char *)&scp_reply, 1974 sizeof(scp_reply), &ret_bytes); 1975 1976 if (status < 0) { 1977 codec_dbg(codec, "dspio_scp: send scp msg failed\n"); 1978 return status; 1979 } 1980 1981 /* extract send and reply headers members */ 1982 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag, 1983 NULL, NULL, NULL, NULL, NULL); 1984 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL, 1985 &reply_resp_flag, &reply_error_flag, 1986 &reply_data_size); 1987 1988 if (!send_get_flag) 1989 return 0; 1990 1991 if (reply_resp_flag && !reply_error_flag) { 1992 ret_size = (ret_bytes - sizeof(scp_reply.hdr)) 1993 / sizeof(unsigned int); 1994 1995 if (*reply_len < ret_size*sizeof(unsigned int)) { 1996 codec_dbg(codec, "reply too long for buf\n"); 1997 return -EINVAL; 1998 } else if (ret_size != reply_data_size) { 1999 codec_dbg(codec, "RetLen and HdrLen .NE.\n"); 2000 return -EINVAL; 2001 } else if (!reply) { 2002 codec_dbg(codec, "NULL reply\n"); 2003 return -EINVAL; 2004 } else { 2005 *reply_len = ret_size*sizeof(unsigned int); 2006 memcpy(reply, scp_reply.data, *reply_len); 2007 } 2008 } else { 2009 codec_dbg(codec, "reply ill-formed or errflag set\n"); 2010 return -EIO; 2011 } 2012 2013 return status; 2014 } 2015 2016 /* 2017 * Set DSP parameters 2018 */ 2019 static int dspio_set_param(struct hda_codec *codec, int mod_id, 2020 int src_id, int req, const void *data, unsigned int len) 2021 { 2022 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL, 2023 NULL); 2024 } 2025 2026 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id, 2027 int req, const unsigned int data) 2028 { 2029 return dspio_set_param(codec, mod_id, 0x20, req, &data, 2030 sizeof(unsigned int)); 2031 } 2032 2033 static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id, 2034 int req, const unsigned int data) 2035 { 2036 return dspio_set_param(codec, mod_id, 0x00, req, &data, 2037 sizeof(unsigned int)); 2038 } 2039 2040 /* 2041 * Allocate a DSP DMA channel via an SCP message 2042 */ 2043 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan) 2044 { 2045 int status = 0; 2046 unsigned int size = sizeof(dma_chan); 2047 2048 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n"); 2049 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2050 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0, 2051 dma_chan, &size); 2052 2053 if (status < 0) { 2054 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n"); 2055 return status; 2056 } 2057 2058 if ((*dma_chan + 1) == 0) { 2059 codec_dbg(codec, "no free dma channels to allocate\n"); 2060 return -EBUSY; 2061 } 2062 2063 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan); 2064 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n"); 2065 2066 return status; 2067 } 2068 2069 /* 2070 * Free a DSP DMA via an SCP message 2071 */ 2072 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan) 2073 { 2074 int status = 0; 2075 unsigned int dummy = 0; 2076 2077 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n"); 2078 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan); 2079 2080 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2081 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan, 2082 sizeof(dma_chan), NULL, &dummy); 2083 2084 if (status < 0) { 2085 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n"); 2086 return status; 2087 } 2088 2089 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n"); 2090 2091 return status; 2092 } 2093 2094 /* 2095 * (Re)start the DSP 2096 */ 2097 static int dsp_set_run_state(struct hda_codec *codec) 2098 { 2099 unsigned int dbg_ctrl_reg; 2100 unsigned int halt_state; 2101 int err; 2102 2103 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg); 2104 if (err < 0) 2105 return err; 2106 2107 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >> 2108 DSP_DBGCNTL_STATE_LOBIT; 2109 2110 if (halt_state != 0) { 2111 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) & 2112 DSP_DBGCNTL_SS_MASK); 2113 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2114 dbg_ctrl_reg); 2115 if (err < 0) 2116 return err; 2117 2118 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) & 2119 DSP_DBGCNTL_EXEC_MASK; 2120 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2121 dbg_ctrl_reg); 2122 if (err < 0) 2123 return err; 2124 } 2125 2126 return 0; 2127 } 2128 2129 /* 2130 * Reset the DSP 2131 */ 2132 static int dsp_reset(struct hda_codec *codec) 2133 { 2134 unsigned int res; 2135 int retry = 20; 2136 2137 codec_dbg(codec, "dsp_reset\n"); 2138 do { 2139 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0); 2140 retry--; 2141 } while (res == -EIO && retry); 2142 2143 if (!retry) { 2144 codec_dbg(codec, "dsp_reset timeout\n"); 2145 return -EIO; 2146 } 2147 2148 return 0; 2149 } 2150 2151 /* 2152 * Convert chip address to DSP address 2153 */ 2154 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx, 2155 bool *code, bool *yram) 2156 { 2157 *code = *yram = false; 2158 2159 if (UC_RANGE(chip_addx, 1)) { 2160 *code = true; 2161 return UC_OFF(chip_addx); 2162 } else if (X_RANGE_ALL(chip_addx, 1)) { 2163 return X_OFF(chip_addx); 2164 } else if (Y_RANGE_ALL(chip_addx, 1)) { 2165 *yram = true; 2166 return Y_OFF(chip_addx); 2167 } 2168 2169 return INVALID_CHIP_ADDRESS; 2170 } 2171 2172 /* 2173 * Check if the DSP DMA is active 2174 */ 2175 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan) 2176 { 2177 unsigned int dma_chnlstart_reg; 2178 2179 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg); 2180 2181 return ((dma_chnlstart_reg & (1 << 2182 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0); 2183 } 2184 2185 static int dsp_dma_setup_common(struct hda_codec *codec, 2186 unsigned int chip_addx, 2187 unsigned int dma_chan, 2188 unsigned int port_map_mask, 2189 bool ovly) 2190 { 2191 int status = 0; 2192 unsigned int chnl_prop; 2193 unsigned int dsp_addx; 2194 unsigned int active; 2195 bool code, yram; 2196 2197 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n"); 2198 2199 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) { 2200 codec_dbg(codec, "dma chan num invalid\n"); 2201 return -EINVAL; 2202 } 2203 2204 if (dsp_is_dma_active(codec, dma_chan)) { 2205 codec_dbg(codec, "dma already active\n"); 2206 return -EBUSY; 2207 } 2208 2209 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2210 2211 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2212 codec_dbg(codec, "invalid chip addr\n"); 2213 return -ENXIO; 2214 } 2215 2216 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK; 2217 active = 0; 2218 2219 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n"); 2220 2221 if (ovly) { 2222 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET, 2223 &chnl_prop); 2224 2225 if (status < 0) { 2226 codec_dbg(codec, "read CHNLPROP Reg fail\n"); 2227 return status; 2228 } 2229 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n"); 2230 } 2231 2232 if (!code) 2233 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2234 else 2235 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2236 2237 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan)); 2238 2239 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop); 2240 if (status < 0) { 2241 codec_dbg(codec, "write CHNLPROP Reg fail\n"); 2242 return status; 2243 } 2244 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n"); 2245 2246 if (ovly) { 2247 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET, 2248 &active); 2249 2250 if (status < 0) { 2251 codec_dbg(codec, "read ACTIVE Reg fail\n"); 2252 return status; 2253 } 2254 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n"); 2255 } 2256 2257 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) & 2258 DSPDMAC_ACTIVE_AAR_MASK; 2259 2260 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active); 2261 if (status < 0) { 2262 codec_dbg(codec, "write ACTIVE Reg fail\n"); 2263 return status; 2264 } 2265 2266 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n"); 2267 2268 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan), 2269 port_map_mask); 2270 if (status < 0) { 2271 codec_dbg(codec, "write AUDCHSEL Reg fail\n"); 2272 return status; 2273 } 2274 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n"); 2275 2276 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan), 2277 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK); 2278 if (status < 0) { 2279 codec_dbg(codec, "write IRQCNT Reg fail\n"); 2280 return status; 2281 } 2282 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n"); 2283 2284 codec_dbg(codec, 2285 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, " 2286 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n", 2287 chip_addx, dsp_addx, dma_chan, 2288 port_map_mask, chnl_prop, active); 2289 2290 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n"); 2291 2292 return 0; 2293 } 2294 2295 /* 2296 * Setup the DSP DMA per-transfer-specific registers 2297 */ 2298 static int dsp_dma_setup(struct hda_codec *codec, 2299 unsigned int chip_addx, 2300 unsigned int count, 2301 unsigned int dma_chan) 2302 { 2303 int status = 0; 2304 bool code, yram; 2305 unsigned int dsp_addx; 2306 unsigned int addr_field; 2307 unsigned int incr_field; 2308 unsigned int base_cnt; 2309 unsigned int cur_cnt; 2310 unsigned int dma_cfg = 0; 2311 unsigned int adr_ofs = 0; 2312 unsigned int xfr_cnt = 0; 2313 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT - 2314 DSPDMAC_XFRCNT_BCNT_LOBIT + 1); 2315 2316 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n"); 2317 2318 if (count > max_dma_count) { 2319 codec_dbg(codec, "count too big\n"); 2320 return -EINVAL; 2321 } 2322 2323 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2324 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2325 codec_dbg(codec, "invalid chip addr\n"); 2326 return -ENXIO; 2327 } 2328 2329 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n"); 2330 2331 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT; 2332 incr_field = 0; 2333 2334 if (!code) { 2335 addr_field <<= 1; 2336 if (yram) 2337 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT); 2338 2339 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT); 2340 } 2341 2342 dma_cfg = addr_field + incr_field; 2343 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan), 2344 dma_cfg); 2345 if (status < 0) { 2346 codec_dbg(codec, "write DMACFG Reg fail\n"); 2347 return status; 2348 } 2349 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n"); 2350 2351 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT + 2352 (code ? 0 : 1)); 2353 2354 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan), 2355 adr_ofs); 2356 if (status < 0) { 2357 codec_dbg(codec, "write DSPADROFS Reg fail\n"); 2358 return status; 2359 } 2360 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n"); 2361 2362 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT; 2363 2364 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT; 2365 2366 xfr_cnt = base_cnt | cur_cnt; 2367 2368 status = chipio_write(codec, 2369 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt); 2370 if (status < 0) { 2371 codec_dbg(codec, "write XFRCNT Reg fail\n"); 2372 return status; 2373 } 2374 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n"); 2375 2376 codec_dbg(codec, 2377 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, " 2378 "ADROFS=0x%x, XFRCNT=0x%x\n", 2379 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt); 2380 2381 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n"); 2382 2383 return 0; 2384 } 2385 2386 /* 2387 * Start the DSP DMA 2388 */ 2389 static int dsp_dma_start(struct hda_codec *codec, 2390 unsigned int dma_chan, bool ovly) 2391 { 2392 unsigned int reg = 0; 2393 int status = 0; 2394 2395 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n"); 2396 2397 if (ovly) { 2398 status = chipio_read(codec, 2399 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2400 2401 if (status < 0) { 2402 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2403 return status; 2404 } 2405 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n"); 2406 2407 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2408 DSPDMAC_CHNLSTART_DIS_MASK); 2409 } 2410 2411 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2412 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT))); 2413 if (status < 0) { 2414 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2415 return status; 2416 } 2417 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n"); 2418 2419 return status; 2420 } 2421 2422 /* 2423 * Stop the DSP DMA 2424 */ 2425 static int dsp_dma_stop(struct hda_codec *codec, 2426 unsigned int dma_chan, bool ovly) 2427 { 2428 unsigned int reg = 0; 2429 int status = 0; 2430 2431 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n"); 2432 2433 if (ovly) { 2434 status = chipio_read(codec, 2435 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2436 2437 if (status < 0) { 2438 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2439 return status; 2440 } 2441 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n"); 2442 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2443 DSPDMAC_CHNLSTART_DIS_MASK); 2444 } 2445 2446 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2447 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT))); 2448 if (status < 0) { 2449 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2450 return status; 2451 } 2452 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n"); 2453 2454 return status; 2455 } 2456 2457 /** 2458 * Allocate router ports 2459 * 2460 * @codec: the HDA codec 2461 * @num_chans: number of channels in the stream 2462 * @ports_per_channel: number of ports per channel 2463 * @start_device: start device 2464 * @port_map: pointer to the port list to hold the allocated ports 2465 * 2466 * Returns zero or a negative error code. 2467 */ 2468 static int dsp_allocate_router_ports(struct hda_codec *codec, 2469 unsigned int num_chans, 2470 unsigned int ports_per_channel, 2471 unsigned int start_device, 2472 unsigned int *port_map) 2473 { 2474 int status = 0; 2475 int res; 2476 u8 val; 2477 2478 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2479 if (status < 0) 2480 return status; 2481 2482 val = start_device << 6; 2483 val |= (ports_per_channel - 1) << 4; 2484 val |= num_chans - 1; 2485 2486 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2487 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET, 2488 val); 2489 2490 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2491 VENDOR_CHIPIO_PORT_ALLOC_SET, 2492 MEM_CONNID_DSP); 2493 2494 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2495 if (status < 0) 2496 return status; 2497 2498 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 2499 VENDOR_CHIPIO_PORT_ALLOC_GET, 0); 2500 2501 *port_map = res; 2502 2503 return (res < 0) ? res : 0; 2504 } 2505 2506 /* 2507 * Free router ports 2508 */ 2509 static int dsp_free_router_ports(struct hda_codec *codec) 2510 { 2511 int status = 0; 2512 2513 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2514 if (status < 0) 2515 return status; 2516 2517 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2518 VENDOR_CHIPIO_PORT_FREE_SET, 2519 MEM_CONNID_DSP); 2520 2521 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2522 2523 return status; 2524 } 2525 2526 /* 2527 * Allocate DSP ports for the download stream 2528 */ 2529 static int dsp_allocate_ports(struct hda_codec *codec, 2530 unsigned int num_chans, 2531 unsigned int rate_multi, unsigned int *port_map) 2532 { 2533 int status; 2534 2535 codec_dbg(codec, " dsp_allocate_ports() -- begin\n"); 2536 2537 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2538 codec_dbg(codec, "bad rate multiple\n"); 2539 return -EINVAL; 2540 } 2541 2542 status = dsp_allocate_router_ports(codec, num_chans, 2543 rate_multi, 0, port_map); 2544 2545 codec_dbg(codec, " dsp_allocate_ports() -- complete\n"); 2546 2547 return status; 2548 } 2549 2550 static int dsp_allocate_ports_format(struct hda_codec *codec, 2551 const unsigned short fmt, 2552 unsigned int *port_map) 2553 { 2554 int status; 2555 unsigned int num_chans; 2556 2557 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1; 2558 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1; 2559 unsigned int rate_multi = sample_rate_mul / sample_rate_div; 2560 2561 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2562 codec_dbg(codec, "bad rate multiple\n"); 2563 return -EINVAL; 2564 } 2565 2566 num_chans = get_hdafmt_chs(fmt) + 1; 2567 2568 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map); 2569 2570 return status; 2571 } 2572 2573 /* 2574 * free DSP ports 2575 */ 2576 static int dsp_free_ports(struct hda_codec *codec) 2577 { 2578 int status; 2579 2580 codec_dbg(codec, " dsp_free_ports() -- begin\n"); 2581 2582 status = dsp_free_router_ports(codec); 2583 if (status < 0) { 2584 codec_dbg(codec, "free router ports fail\n"); 2585 return status; 2586 } 2587 codec_dbg(codec, " dsp_free_ports() -- complete\n"); 2588 2589 return status; 2590 } 2591 2592 /* 2593 * HDA DMA engine stuffs for DSP code download 2594 */ 2595 struct dma_engine { 2596 struct hda_codec *codec; 2597 unsigned short m_converter_format; 2598 struct snd_dma_buffer *dmab; 2599 unsigned int buf_size; 2600 }; 2601 2602 2603 enum dma_state { 2604 DMA_STATE_STOP = 0, 2605 DMA_STATE_RUN = 1 2606 }; 2607 2608 static int dma_convert_to_hda_format(struct hda_codec *codec, 2609 unsigned int sample_rate, 2610 unsigned short channels, 2611 unsigned short *hda_format) 2612 { 2613 unsigned int format_val; 2614 2615 format_val = snd_hdac_calc_stream_format(sample_rate, 2616 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0); 2617 2618 if (hda_format) 2619 *hda_format = (unsigned short)format_val; 2620 2621 return 0; 2622 } 2623 2624 /* 2625 * Reset DMA for DSP download 2626 */ 2627 static int dma_reset(struct dma_engine *dma) 2628 { 2629 struct hda_codec *codec = dma->codec; 2630 struct ca0132_spec *spec = codec->spec; 2631 int status; 2632 2633 if (dma->dmab->area) 2634 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab); 2635 2636 status = snd_hda_codec_load_dsp_prepare(codec, 2637 dma->m_converter_format, 2638 dma->buf_size, 2639 dma->dmab); 2640 if (status < 0) 2641 return status; 2642 spec->dsp_stream_id = status; 2643 return 0; 2644 } 2645 2646 static int dma_set_state(struct dma_engine *dma, enum dma_state state) 2647 { 2648 bool cmd; 2649 2650 switch (state) { 2651 case DMA_STATE_STOP: 2652 cmd = false; 2653 break; 2654 case DMA_STATE_RUN: 2655 cmd = true; 2656 break; 2657 default: 2658 return 0; 2659 } 2660 2661 snd_hda_codec_load_dsp_trigger(dma->codec, cmd); 2662 return 0; 2663 } 2664 2665 static unsigned int dma_get_buffer_size(struct dma_engine *dma) 2666 { 2667 return dma->dmab->bytes; 2668 } 2669 2670 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma) 2671 { 2672 return dma->dmab->area; 2673 } 2674 2675 static int dma_xfer(struct dma_engine *dma, 2676 const unsigned int *data, 2677 unsigned int count) 2678 { 2679 memcpy(dma->dmab->area, data, count); 2680 return 0; 2681 } 2682 2683 static void dma_get_converter_format( 2684 struct dma_engine *dma, 2685 unsigned short *format) 2686 { 2687 if (format) 2688 *format = dma->m_converter_format; 2689 } 2690 2691 static unsigned int dma_get_stream_id(struct dma_engine *dma) 2692 { 2693 struct ca0132_spec *spec = dma->codec->spec; 2694 2695 return spec->dsp_stream_id; 2696 } 2697 2698 struct dsp_image_seg { 2699 u32 magic; 2700 u32 chip_addr; 2701 u32 count; 2702 u32 data[]; 2703 }; 2704 2705 static const u32 g_magic_value = 0x4c46584d; 2706 static const u32 g_chip_addr_magic_value = 0xFFFFFF01; 2707 2708 static bool is_valid(const struct dsp_image_seg *p) 2709 { 2710 return p->magic == g_magic_value; 2711 } 2712 2713 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p) 2714 { 2715 return g_chip_addr_magic_value == p->chip_addr; 2716 } 2717 2718 static bool is_last(const struct dsp_image_seg *p) 2719 { 2720 return p->count == 0; 2721 } 2722 2723 static size_t dsp_sizeof(const struct dsp_image_seg *p) 2724 { 2725 return struct_size(p, data, p->count); 2726 } 2727 2728 static const struct dsp_image_seg *get_next_seg_ptr( 2729 const struct dsp_image_seg *p) 2730 { 2731 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p)); 2732 } 2733 2734 /* 2735 * CA0132 chip DSP transfer stuffs. For DSP download. 2736 */ 2737 #define INVALID_DMA_CHANNEL (~0U) 2738 2739 /* 2740 * Program a list of address/data pairs via the ChipIO widget. 2741 * The segment data is in the format of successive pairs of words. 2742 * These are repeated as indicated by the segment's count field. 2743 */ 2744 static int dspxfr_hci_write(struct hda_codec *codec, 2745 const struct dsp_image_seg *fls) 2746 { 2747 int status; 2748 const u32 *data; 2749 unsigned int count; 2750 2751 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) { 2752 codec_dbg(codec, "hci_write invalid params\n"); 2753 return -EINVAL; 2754 } 2755 2756 count = fls->count; 2757 data = (u32 *)(fls->data); 2758 while (count >= 2) { 2759 status = chipio_write(codec, data[0], data[1]); 2760 if (status < 0) { 2761 codec_dbg(codec, "hci_write chipio failed\n"); 2762 return status; 2763 } 2764 count -= 2; 2765 data += 2; 2766 } 2767 return 0; 2768 } 2769 2770 /** 2771 * Write a block of data into DSP code or data RAM using pre-allocated 2772 * DMA engine. 2773 * 2774 * @codec: the HDA codec 2775 * @fls: pointer to a fast load image 2776 * @reloc: Relocation address for loading single-segment overlays, or 0 for 2777 * no relocation 2778 * @dma_engine: pointer to DMA engine to be used for DSP download 2779 * @dma_chan: The number of DMA channels used for DSP download 2780 * @port_map_mask: port mapping 2781 * @ovly: TRUE if overlay format is required 2782 * 2783 * Returns zero or a negative error code. 2784 */ 2785 static int dspxfr_one_seg(struct hda_codec *codec, 2786 const struct dsp_image_seg *fls, 2787 unsigned int reloc, 2788 struct dma_engine *dma_engine, 2789 unsigned int dma_chan, 2790 unsigned int port_map_mask, 2791 bool ovly) 2792 { 2793 int status = 0; 2794 bool comm_dma_setup_done = false; 2795 const unsigned int *data; 2796 unsigned int chip_addx; 2797 unsigned int words_to_write; 2798 unsigned int buffer_size_words; 2799 unsigned char *buffer_addx; 2800 unsigned short hda_format; 2801 unsigned int sample_rate_div; 2802 unsigned int sample_rate_mul; 2803 unsigned int num_chans; 2804 unsigned int hda_frame_size_words; 2805 unsigned int remainder_words; 2806 const u32 *data_remainder; 2807 u32 chip_addx_remainder; 2808 unsigned int run_size_words; 2809 const struct dsp_image_seg *hci_write = NULL; 2810 unsigned long timeout; 2811 bool dma_active; 2812 2813 if (fls == NULL) 2814 return -EINVAL; 2815 if (is_hci_prog_list_seg(fls)) { 2816 hci_write = fls; 2817 fls = get_next_seg_ptr(fls); 2818 } 2819 2820 if (hci_write && (!fls || is_last(fls))) { 2821 codec_dbg(codec, "hci_write\n"); 2822 return dspxfr_hci_write(codec, hci_write); 2823 } 2824 2825 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) { 2826 codec_dbg(codec, "Invalid Params\n"); 2827 return -EINVAL; 2828 } 2829 2830 data = fls->data; 2831 chip_addx = fls->chip_addr, 2832 words_to_write = fls->count; 2833 2834 if (!words_to_write) 2835 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0; 2836 if (reloc) 2837 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2); 2838 2839 if (!UC_RANGE(chip_addx, words_to_write) && 2840 !X_RANGE_ALL(chip_addx, words_to_write) && 2841 !Y_RANGE_ALL(chip_addx, words_to_write)) { 2842 codec_dbg(codec, "Invalid chip_addx Params\n"); 2843 return -EINVAL; 2844 } 2845 2846 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) / 2847 sizeof(u32); 2848 2849 buffer_addx = dma_get_buffer_addr(dma_engine); 2850 2851 if (buffer_addx == NULL) { 2852 codec_dbg(codec, "dma_engine buffer NULL\n"); 2853 return -EINVAL; 2854 } 2855 2856 dma_get_converter_format(dma_engine, &hda_format); 2857 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1; 2858 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1; 2859 num_chans = get_hdafmt_chs(hda_format) + 1; 2860 2861 hda_frame_size_words = ((sample_rate_div == 0) ? 0 : 2862 (num_chans * sample_rate_mul / sample_rate_div)); 2863 2864 if (hda_frame_size_words == 0) { 2865 codec_dbg(codec, "frmsz zero\n"); 2866 return -EINVAL; 2867 } 2868 2869 buffer_size_words = min(buffer_size_words, 2870 (unsigned int)(UC_RANGE(chip_addx, 1) ? 2871 65536 : 32768)); 2872 buffer_size_words -= buffer_size_words % hda_frame_size_words; 2873 codec_dbg(codec, 2874 "chpadr=0x%08x frmsz=%u nchan=%u " 2875 "rate_mul=%u div=%u bufsz=%u\n", 2876 chip_addx, hda_frame_size_words, num_chans, 2877 sample_rate_mul, sample_rate_div, buffer_size_words); 2878 2879 if (buffer_size_words < hda_frame_size_words) { 2880 codec_dbg(codec, "dspxfr_one_seg:failed\n"); 2881 return -EINVAL; 2882 } 2883 2884 remainder_words = words_to_write % hda_frame_size_words; 2885 data_remainder = data; 2886 chip_addx_remainder = chip_addx; 2887 2888 data += remainder_words; 2889 chip_addx += remainder_words*sizeof(u32); 2890 words_to_write -= remainder_words; 2891 2892 while (words_to_write != 0) { 2893 run_size_words = min(buffer_size_words, words_to_write); 2894 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n", 2895 words_to_write, run_size_words, remainder_words); 2896 dma_xfer(dma_engine, data, run_size_words*sizeof(u32)); 2897 if (!comm_dma_setup_done) { 2898 status = dsp_dma_stop(codec, dma_chan, ovly); 2899 if (status < 0) 2900 return status; 2901 status = dsp_dma_setup_common(codec, chip_addx, 2902 dma_chan, port_map_mask, ovly); 2903 if (status < 0) 2904 return status; 2905 comm_dma_setup_done = true; 2906 } 2907 2908 status = dsp_dma_setup(codec, chip_addx, 2909 run_size_words, dma_chan); 2910 if (status < 0) 2911 return status; 2912 status = dsp_dma_start(codec, dma_chan, ovly); 2913 if (status < 0) 2914 return status; 2915 if (!dsp_is_dma_active(codec, dma_chan)) { 2916 codec_dbg(codec, "dspxfr:DMA did not start\n"); 2917 return -EIO; 2918 } 2919 status = dma_set_state(dma_engine, DMA_STATE_RUN); 2920 if (status < 0) 2921 return status; 2922 if (remainder_words != 0) { 2923 status = chipio_write_multiple(codec, 2924 chip_addx_remainder, 2925 data_remainder, 2926 remainder_words); 2927 if (status < 0) 2928 return status; 2929 remainder_words = 0; 2930 } 2931 if (hci_write) { 2932 status = dspxfr_hci_write(codec, hci_write); 2933 if (status < 0) 2934 return status; 2935 hci_write = NULL; 2936 } 2937 2938 timeout = jiffies + msecs_to_jiffies(2000); 2939 do { 2940 dma_active = dsp_is_dma_active(codec, dma_chan); 2941 if (!dma_active) 2942 break; 2943 msleep(20); 2944 } while (time_before(jiffies, timeout)); 2945 if (dma_active) 2946 break; 2947 2948 codec_dbg(codec, "+++++ DMA complete\n"); 2949 dma_set_state(dma_engine, DMA_STATE_STOP); 2950 status = dma_reset(dma_engine); 2951 2952 if (status < 0) 2953 return status; 2954 2955 data += run_size_words; 2956 chip_addx += run_size_words*sizeof(u32); 2957 words_to_write -= run_size_words; 2958 } 2959 2960 if (remainder_words != 0) { 2961 status = chipio_write_multiple(codec, chip_addx_remainder, 2962 data_remainder, remainder_words); 2963 } 2964 2965 return status; 2966 } 2967 2968 /** 2969 * Write the entire DSP image of a DSP code/data overlay to DSP memories 2970 * 2971 * @codec: the HDA codec 2972 * @fls_data: pointer to a fast load image 2973 * @reloc: Relocation address for loading single-segment overlays, or 0 for 2974 * no relocation 2975 * @sample_rate: sampling rate of the stream used for DSP download 2976 * @channels: channels of the stream used for DSP download 2977 * @ovly: TRUE if overlay format is required 2978 * 2979 * Returns zero or a negative error code. 2980 */ 2981 static int dspxfr_image(struct hda_codec *codec, 2982 const struct dsp_image_seg *fls_data, 2983 unsigned int reloc, 2984 unsigned int sample_rate, 2985 unsigned short channels, 2986 bool ovly) 2987 { 2988 struct ca0132_spec *spec = codec->spec; 2989 int status; 2990 unsigned short hda_format = 0; 2991 unsigned int response; 2992 unsigned char stream_id = 0; 2993 struct dma_engine *dma_engine; 2994 unsigned int dma_chan; 2995 unsigned int port_map_mask; 2996 2997 if (fls_data == NULL) 2998 return -EINVAL; 2999 3000 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL); 3001 if (!dma_engine) 3002 return -ENOMEM; 3003 3004 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL); 3005 if (!dma_engine->dmab) { 3006 kfree(dma_engine); 3007 return -ENOMEM; 3008 } 3009 3010 dma_engine->codec = codec; 3011 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format); 3012 dma_engine->m_converter_format = hda_format; 3013 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY : 3014 DSP_DMA_WRITE_BUFLEN_INIT) * 2; 3015 3016 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0; 3017 3018 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL, 3019 hda_format, &response); 3020 3021 if (status < 0) { 3022 codec_dbg(codec, "set converter format fail\n"); 3023 goto exit; 3024 } 3025 3026 status = snd_hda_codec_load_dsp_prepare(codec, 3027 dma_engine->m_converter_format, 3028 dma_engine->buf_size, 3029 dma_engine->dmab); 3030 if (status < 0) 3031 goto exit; 3032 spec->dsp_stream_id = status; 3033 3034 if (ovly) { 3035 status = dspio_alloc_dma_chan(codec, &dma_chan); 3036 if (status < 0) { 3037 codec_dbg(codec, "alloc dmachan fail\n"); 3038 dma_chan = INVALID_DMA_CHANNEL; 3039 goto exit; 3040 } 3041 } 3042 3043 port_map_mask = 0; 3044 status = dsp_allocate_ports_format(codec, hda_format, 3045 &port_map_mask); 3046 if (status < 0) { 3047 codec_dbg(codec, "alloc ports fail\n"); 3048 goto exit; 3049 } 3050 3051 stream_id = dma_get_stream_id(dma_engine); 3052 status = codec_set_converter_stream_channel(codec, 3053 WIDGET_CHIP_CTRL, stream_id, 0, &response); 3054 if (status < 0) { 3055 codec_dbg(codec, "set stream chan fail\n"); 3056 goto exit; 3057 } 3058 3059 while ((fls_data != NULL) && !is_last(fls_data)) { 3060 if (!is_valid(fls_data)) { 3061 codec_dbg(codec, "FLS check fail\n"); 3062 status = -EINVAL; 3063 goto exit; 3064 } 3065 status = dspxfr_one_seg(codec, fls_data, reloc, 3066 dma_engine, dma_chan, 3067 port_map_mask, ovly); 3068 if (status < 0) 3069 break; 3070 3071 if (is_hci_prog_list_seg(fls_data)) 3072 fls_data = get_next_seg_ptr(fls_data); 3073 3074 if ((fls_data != NULL) && !is_last(fls_data)) 3075 fls_data = get_next_seg_ptr(fls_data); 3076 } 3077 3078 if (port_map_mask != 0) 3079 status = dsp_free_ports(codec); 3080 3081 if (status < 0) 3082 goto exit; 3083 3084 status = codec_set_converter_stream_channel(codec, 3085 WIDGET_CHIP_CTRL, 0, 0, &response); 3086 3087 exit: 3088 if (ovly && (dma_chan != INVALID_DMA_CHANNEL)) 3089 dspio_free_dma_chan(codec, dma_chan); 3090 3091 if (dma_engine->dmab->area) 3092 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab); 3093 kfree(dma_engine->dmab); 3094 kfree(dma_engine); 3095 3096 return status; 3097 } 3098 3099 /* 3100 * CA0132 DSP download stuffs. 3101 */ 3102 static void dspload_post_setup(struct hda_codec *codec) 3103 { 3104 struct ca0132_spec *spec = codec->spec; 3105 codec_dbg(codec, "---- dspload_post_setup ------\n"); 3106 if (!ca0132_use_alt_functions(spec)) { 3107 /*set DSP speaker to 2.0 configuration*/ 3108 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080); 3109 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000); 3110 3111 /*update write pointer*/ 3112 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002); 3113 } 3114 } 3115 3116 /** 3117 * dspload_image - Download DSP from a DSP Image Fast Load structure. 3118 * 3119 * @codec: the HDA codec 3120 * @fls: pointer to a fast load image 3121 * @ovly: TRUE if overlay format is required 3122 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3123 * no relocation 3124 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE 3125 * @router_chans: number of audio router channels to be allocated (0 means use 3126 * internal defaults; max is 32) 3127 * 3128 * Download DSP from a DSP Image Fast Load structure. This structure is a 3129 * linear, non-constant sized element array of structures, each of which 3130 * contain the count of the data to be loaded, the data itself, and the 3131 * corresponding starting chip address of the starting data location. 3132 * Returns zero or a negative error code. 3133 */ 3134 static int dspload_image(struct hda_codec *codec, 3135 const struct dsp_image_seg *fls, 3136 bool ovly, 3137 unsigned int reloc, 3138 bool autostart, 3139 int router_chans) 3140 { 3141 int status = 0; 3142 unsigned int sample_rate; 3143 unsigned short channels; 3144 3145 codec_dbg(codec, "---- dspload_image begin ------\n"); 3146 if (router_chans == 0) { 3147 if (!ovly) 3148 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS; 3149 else 3150 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS; 3151 } 3152 3153 sample_rate = 48000; 3154 channels = (unsigned short)router_chans; 3155 3156 while (channels > 16) { 3157 sample_rate *= 2; 3158 channels /= 2; 3159 } 3160 3161 do { 3162 codec_dbg(codec, "Ready to program DMA\n"); 3163 if (!ovly) 3164 status = dsp_reset(codec); 3165 3166 if (status < 0) 3167 break; 3168 3169 codec_dbg(codec, "dsp_reset() complete\n"); 3170 status = dspxfr_image(codec, fls, reloc, sample_rate, channels, 3171 ovly); 3172 3173 if (status < 0) 3174 break; 3175 3176 codec_dbg(codec, "dspxfr_image() complete\n"); 3177 if (autostart && !ovly) { 3178 dspload_post_setup(codec); 3179 status = dsp_set_run_state(codec); 3180 } 3181 3182 codec_dbg(codec, "LOAD FINISHED\n"); 3183 } while (0); 3184 3185 return status; 3186 } 3187 3188 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 3189 static bool dspload_is_loaded(struct hda_codec *codec) 3190 { 3191 unsigned int data = 0; 3192 int status = 0; 3193 3194 status = chipio_read(codec, 0x40004, &data); 3195 if ((status < 0) || (data != 1)) 3196 return false; 3197 3198 return true; 3199 } 3200 #else 3201 #define dspload_is_loaded(codec) false 3202 #endif 3203 3204 static bool dspload_wait_loaded(struct hda_codec *codec) 3205 { 3206 unsigned long timeout = jiffies + msecs_to_jiffies(2000); 3207 3208 do { 3209 if (dspload_is_loaded(codec)) { 3210 codec_info(codec, "ca0132 DSP downloaded and running\n"); 3211 return true; 3212 } 3213 msleep(20); 3214 } while (time_before(jiffies, timeout)); 3215 3216 codec_err(codec, "ca0132 failed to download DSP\n"); 3217 return false; 3218 } 3219 3220 /* 3221 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e 3222 * based cards, and has a second mmio region, region2, that's used for special 3223 * commands. 3224 */ 3225 3226 /* 3227 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5) 3228 * the mmio address 0x320 is used to set GPIO pins. The format for the data 3229 * The first eight bits are just the number of the pin. So far, I've only seen 3230 * this number go to 7. 3231 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value 3232 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and 3233 * then off to send that bit. 3234 */ 3235 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin, 3236 bool enable) 3237 { 3238 struct ca0132_spec *spec = codec->spec; 3239 unsigned short gpio_data; 3240 3241 gpio_data = gpio_pin & 0xF; 3242 gpio_data |= ((enable << 8) & 0x100); 3243 3244 writew(gpio_data, spec->mem_base + 0x320); 3245 } 3246 3247 /* 3248 * Special pci region2 commands that are only used by the AE-5. They follow 3249 * a set format, and require reads at certain points to seemingly 'clear' 3250 * the response data. My first tests didn't do these reads, and would cause 3251 * the card to get locked up until the memory was read. These commands 3252 * seem to work with three distinct values that I've taken to calling group, 3253 * target-id, and value. 3254 */ 3255 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group, 3256 unsigned int target, unsigned int value) 3257 { 3258 struct ca0132_spec *spec = codec->spec; 3259 unsigned int write_val; 3260 3261 writel(0x0000007e, spec->mem_base + 0x210); 3262 readl(spec->mem_base + 0x210); 3263 writel(0x0000005a, spec->mem_base + 0x210); 3264 readl(spec->mem_base + 0x210); 3265 readl(spec->mem_base + 0x210); 3266 3267 writel(0x00800005, spec->mem_base + 0x20c); 3268 writel(group, spec->mem_base + 0x804); 3269 3270 writel(0x00800005, spec->mem_base + 0x20c); 3271 write_val = (target & 0xff); 3272 write_val |= (value << 8); 3273 3274 3275 writel(write_val, spec->mem_base + 0x204); 3276 /* 3277 * Need delay here or else it goes too fast and works inconsistently. 3278 */ 3279 msleep(20); 3280 3281 readl(spec->mem_base + 0x860); 3282 readl(spec->mem_base + 0x854); 3283 readl(spec->mem_base + 0x840); 3284 3285 writel(0x00800004, spec->mem_base + 0x20c); 3286 writel(0x00000000, spec->mem_base + 0x210); 3287 readl(spec->mem_base + 0x210); 3288 readl(spec->mem_base + 0x210); 3289 } 3290 3291 /* 3292 * This second type of command is used for setting the sound filter type. 3293 */ 3294 static void ca0113_mmio_command_set_type2(struct hda_codec *codec, 3295 unsigned int group, unsigned int target, unsigned int value) 3296 { 3297 struct ca0132_spec *spec = codec->spec; 3298 unsigned int write_val; 3299 3300 writel(0x0000007e, spec->mem_base + 0x210); 3301 readl(spec->mem_base + 0x210); 3302 writel(0x0000005a, spec->mem_base + 0x210); 3303 readl(spec->mem_base + 0x210); 3304 readl(spec->mem_base + 0x210); 3305 3306 writel(0x00800003, spec->mem_base + 0x20c); 3307 writel(group, spec->mem_base + 0x804); 3308 3309 writel(0x00800005, spec->mem_base + 0x20c); 3310 write_val = (target & 0xff); 3311 write_val |= (value << 8); 3312 3313 3314 writel(write_val, spec->mem_base + 0x204); 3315 msleep(20); 3316 readl(spec->mem_base + 0x860); 3317 readl(spec->mem_base + 0x854); 3318 readl(spec->mem_base + 0x840); 3319 3320 writel(0x00800004, spec->mem_base + 0x20c); 3321 writel(0x00000000, spec->mem_base + 0x210); 3322 readl(spec->mem_base + 0x210); 3323 readl(spec->mem_base + 0x210); 3324 } 3325 3326 /* 3327 * Setup GPIO for the other variants of Core3D. 3328 */ 3329 3330 /* 3331 * Sets up the GPIO pins so that they are discoverable. If this isn't done, 3332 * the card shows as having no GPIO pins. 3333 */ 3334 static void ca0132_gpio_init(struct hda_codec *codec) 3335 { 3336 struct ca0132_spec *spec = codec->spec; 3337 3338 switch (ca0132_quirk(spec)) { 3339 case QUIRK_SBZ: 3340 case QUIRK_AE5: 3341 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3342 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 3343 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23); 3344 break; 3345 case QUIRK_R3DI: 3346 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3347 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B); 3348 break; 3349 default: 3350 break; 3351 } 3352 3353 } 3354 3355 /* Sets the GPIO for audio output. */ 3356 static void ca0132_gpio_setup(struct hda_codec *codec) 3357 { 3358 struct ca0132_spec *spec = codec->spec; 3359 3360 switch (ca0132_quirk(spec)) { 3361 case QUIRK_SBZ: 3362 snd_hda_codec_write(codec, 0x01, 0, 3363 AC_VERB_SET_GPIO_DIRECTION, 0x07); 3364 snd_hda_codec_write(codec, 0x01, 0, 3365 AC_VERB_SET_GPIO_MASK, 0x07); 3366 snd_hda_codec_write(codec, 0x01, 0, 3367 AC_VERB_SET_GPIO_DATA, 0x04); 3368 snd_hda_codec_write(codec, 0x01, 0, 3369 AC_VERB_SET_GPIO_DATA, 0x06); 3370 break; 3371 case QUIRK_R3DI: 3372 snd_hda_codec_write(codec, 0x01, 0, 3373 AC_VERB_SET_GPIO_DIRECTION, 0x1E); 3374 snd_hda_codec_write(codec, 0x01, 0, 3375 AC_VERB_SET_GPIO_MASK, 0x1F); 3376 snd_hda_codec_write(codec, 0x01, 0, 3377 AC_VERB_SET_GPIO_DATA, 0x0C); 3378 break; 3379 default: 3380 break; 3381 } 3382 } 3383 3384 /* 3385 * GPIO control functions for the Recon3D integrated. 3386 */ 3387 3388 enum r3di_gpio_bit { 3389 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */ 3390 R3DI_MIC_SELECT_BIT = 1, 3391 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */ 3392 R3DI_OUT_SELECT_BIT = 2, 3393 /* 3394 * I dunno what this actually does, but it stays on until the dsp 3395 * is downloaded. 3396 */ 3397 R3DI_GPIO_DSP_DOWNLOADING = 3, 3398 /* 3399 * Same as above, no clue what it does, but it comes on after the dsp 3400 * is downloaded. 3401 */ 3402 R3DI_GPIO_DSP_DOWNLOADED = 4 3403 }; 3404 3405 enum r3di_mic_select { 3406 /* Set GPIO bit 1 to 0 for rear mic */ 3407 R3DI_REAR_MIC = 0, 3408 /* Set GPIO bit 1 to 1 for front microphone*/ 3409 R3DI_FRONT_MIC = 1 3410 }; 3411 3412 enum r3di_out_select { 3413 /* Set GPIO bit 2 to 0 for headphone */ 3414 R3DI_HEADPHONE_OUT = 0, 3415 /* Set GPIO bit 2 to 1 for speaker */ 3416 R3DI_LINE_OUT = 1 3417 }; 3418 enum r3di_dsp_status { 3419 /* Set GPIO bit 3 to 1 until DSP is downloaded */ 3420 R3DI_DSP_DOWNLOADING = 0, 3421 /* Set GPIO bit 4 to 1 once DSP is downloaded */ 3422 R3DI_DSP_DOWNLOADED = 1 3423 }; 3424 3425 3426 static void r3di_gpio_mic_set(struct hda_codec *codec, 3427 enum r3di_mic_select cur_mic) 3428 { 3429 unsigned int cur_gpio; 3430 3431 /* Get the current GPIO Data setup */ 3432 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3433 3434 switch (cur_mic) { 3435 case R3DI_REAR_MIC: 3436 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT); 3437 break; 3438 case R3DI_FRONT_MIC: 3439 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT); 3440 break; 3441 } 3442 snd_hda_codec_write(codec, codec->core.afg, 0, 3443 AC_VERB_SET_GPIO_DATA, cur_gpio); 3444 } 3445 3446 static void r3di_gpio_out_set(struct hda_codec *codec, 3447 enum r3di_out_select cur_out) 3448 { 3449 unsigned int cur_gpio; 3450 3451 /* Get the current GPIO Data setup */ 3452 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3453 3454 switch (cur_out) { 3455 case R3DI_HEADPHONE_OUT: 3456 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT); 3457 break; 3458 case R3DI_LINE_OUT: 3459 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT); 3460 break; 3461 } 3462 snd_hda_codec_write(codec, codec->core.afg, 0, 3463 AC_VERB_SET_GPIO_DATA, cur_gpio); 3464 } 3465 3466 static void r3di_gpio_dsp_status_set(struct hda_codec *codec, 3467 enum r3di_dsp_status dsp_status) 3468 { 3469 unsigned int cur_gpio; 3470 3471 /* Get the current GPIO Data setup */ 3472 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3473 3474 switch (dsp_status) { 3475 case R3DI_DSP_DOWNLOADING: 3476 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING); 3477 snd_hda_codec_write(codec, codec->core.afg, 0, 3478 AC_VERB_SET_GPIO_DATA, cur_gpio); 3479 break; 3480 case R3DI_DSP_DOWNLOADED: 3481 /* Set DOWNLOADING bit to 0. */ 3482 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING); 3483 3484 snd_hda_codec_write(codec, codec->core.afg, 0, 3485 AC_VERB_SET_GPIO_DATA, cur_gpio); 3486 3487 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED); 3488 break; 3489 } 3490 3491 snd_hda_codec_write(codec, codec->core.afg, 0, 3492 AC_VERB_SET_GPIO_DATA, cur_gpio); 3493 } 3494 3495 /* 3496 * PCM callbacks 3497 */ 3498 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3499 struct hda_codec *codec, 3500 unsigned int stream_tag, 3501 unsigned int format, 3502 struct snd_pcm_substream *substream) 3503 { 3504 struct ca0132_spec *spec = codec->spec; 3505 3506 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format); 3507 3508 return 0; 3509 } 3510 3511 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3512 struct hda_codec *codec, 3513 struct snd_pcm_substream *substream) 3514 { 3515 struct ca0132_spec *spec = codec->spec; 3516 3517 if (spec->dsp_state == DSP_DOWNLOADING) 3518 return 0; 3519 3520 /*If Playback effects are on, allow stream some time to flush 3521 *effects tail*/ 3522 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 3523 msleep(50); 3524 3525 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 3526 3527 return 0; 3528 } 3529 3530 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info, 3531 struct hda_codec *codec, 3532 struct snd_pcm_substream *substream) 3533 { 3534 struct ca0132_spec *spec = codec->spec; 3535 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY; 3536 struct snd_pcm_runtime *runtime = substream->runtime; 3537 3538 if (spec->dsp_state != DSP_DOWNLOADED) 3539 return 0; 3540 3541 /* Add latency if playback enhancement and either effect is enabled. */ 3542 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) { 3543 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) || 3544 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID])) 3545 latency += DSP_PLAY_ENHANCEMENT_LATENCY; 3546 } 3547 3548 /* Applying Speaker EQ adds latency as well. */ 3549 if (spec->cur_out_type == SPEAKER_OUT) 3550 latency += DSP_SPEAKER_OUT_LATENCY; 3551 3552 return (latency * runtime->rate) / 1000; 3553 } 3554 3555 /* 3556 * Digital out 3557 */ 3558 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo, 3559 struct hda_codec *codec, 3560 struct snd_pcm_substream *substream) 3561 { 3562 struct ca0132_spec *spec = codec->spec; 3563 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3564 } 3565 3566 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3567 struct hda_codec *codec, 3568 unsigned int stream_tag, 3569 unsigned int format, 3570 struct snd_pcm_substream *substream) 3571 { 3572 struct ca0132_spec *spec = codec->spec; 3573 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3574 stream_tag, format, substream); 3575 } 3576 3577 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3578 struct hda_codec *codec, 3579 struct snd_pcm_substream *substream) 3580 { 3581 struct ca0132_spec *spec = codec->spec; 3582 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout); 3583 } 3584 3585 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo, 3586 struct hda_codec *codec, 3587 struct snd_pcm_substream *substream) 3588 { 3589 struct ca0132_spec *spec = codec->spec; 3590 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3591 } 3592 3593 /* 3594 * Analog capture 3595 */ 3596 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo, 3597 struct hda_codec *codec, 3598 unsigned int stream_tag, 3599 unsigned int format, 3600 struct snd_pcm_substream *substream) 3601 { 3602 snd_hda_codec_setup_stream(codec, hinfo->nid, 3603 stream_tag, 0, format); 3604 3605 return 0; 3606 } 3607 3608 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo, 3609 struct hda_codec *codec, 3610 struct snd_pcm_substream *substream) 3611 { 3612 struct ca0132_spec *spec = codec->spec; 3613 3614 if (spec->dsp_state == DSP_DOWNLOADING) 3615 return 0; 3616 3617 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 3618 return 0; 3619 } 3620 3621 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info, 3622 struct hda_codec *codec, 3623 struct snd_pcm_substream *substream) 3624 { 3625 struct ca0132_spec *spec = codec->spec; 3626 unsigned int latency = DSP_CAPTURE_INIT_LATENCY; 3627 struct snd_pcm_runtime *runtime = substream->runtime; 3628 3629 if (spec->dsp_state != DSP_DOWNLOADED) 3630 return 0; 3631 3632 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 3633 latency += DSP_CRYSTAL_VOICE_LATENCY; 3634 3635 return (latency * runtime->rate) / 1000; 3636 } 3637 3638 /* 3639 * Controls stuffs. 3640 */ 3641 3642 /* 3643 * Mixer controls helpers. 3644 */ 3645 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \ 3646 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3647 .name = xname, \ 3648 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3649 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3650 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 3651 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 3652 .info = ca0132_volume_info, \ 3653 .get = ca0132_volume_get, \ 3654 .put = ca0132_volume_put, \ 3655 .tlv = { .c = ca0132_volume_tlv }, \ 3656 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3657 3658 /* 3659 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the 3660 * volume put, which is used for setting the DSP volume. This was done because 3661 * the ca0132 functions were taking too much time and causing lag. 3662 */ 3663 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \ 3664 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3665 .name = xname, \ 3666 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3667 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3668 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 3669 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 3670 .info = snd_hda_mixer_amp_volume_info, \ 3671 .get = snd_hda_mixer_amp_volume_get, \ 3672 .put = ca0132_alt_volume_put, \ 3673 .tlv = { .c = snd_hda_mixer_amp_tlv }, \ 3674 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3675 3676 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \ 3677 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3678 .name = xname, \ 3679 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3680 .info = snd_hda_mixer_amp_switch_info, \ 3681 .get = ca0132_switch_get, \ 3682 .put = ca0132_switch_put, \ 3683 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3684 3685 /* stereo */ 3686 #define CA0132_CODEC_VOL(xname, nid, dir) \ 3687 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir) 3688 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \ 3689 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir) 3690 #define CA0132_CODEC_MUTE(xname, nid, dir) \ 3691 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir) 3692 3693 /* lookup tables */ 3694 /* 3695 * Lookup table with decibel values for the DSP. When volume is changed in 3696 * Windows, the DSP is also sent the dB value in floating point. In Windows, 3697 * these values have decimal points, probably because the Windows driver 3698 * actually uses floating point. We can't here, so I made a lookup table of 3699 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the 3700 * DAC's, and 9 is the maximum. 3701 */ 3702 static const unsigned int float_vol_db_lookup[] = { 3703 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000, 3704 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000, 3705 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000, 3706 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000, 3707 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000, 3708 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000, 3709 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000, 3710 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000, 3711 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000, 3712 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000, 3713 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000, 3714 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 3715 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 3716 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 3717 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 3718 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 3719 0x40C00000, 0x40E00000, 0x41000000, 0x41100000 3720 }; 3721 3722 /* 3723 * This table counts from float 0 to 1 in increments of .01, which is 3724 * useful for a few different sliders. 3725 */ 3726 static const unsigned int float_zero_to_one_lookup[] = { 3727 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 3728 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 3729 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 3730 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 3731 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 3732 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 3733 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 3734 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 3735 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 3736 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 3737 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 3738 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 3739 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 3740 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 3741 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 3742 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 3743 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 3744 }; 3745 3746 /* 3747 * This table counts from float 10 to 1000, which is the range of the x-bass 3748 * crossover slider in Windows. 3749 */ 3750 static const unsigned int float_xbass_xover_lookup[] = { 3751 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000, 3752 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000, 3753 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000, 3754 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000, 3755 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000, 3756 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000, 3757 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000, 3758 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000, 3759 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000, 3760 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000, 3761 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000, 3762 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000, 3763 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000, 3764 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000, 3765 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000, 3766 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000, 3767 0x44728000, 0x44750000, 0x44778000, 0x447A0000 3768 }; 3769 3770 /* The following are for tuning of products */ 3771 #ifdef ENABLE_TUNING_CONTROLS 3772 3773 static const unsigned int voice_focus_vals_lookup[] = { 3774 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000, 3775 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000, 3776 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000, 3777 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000, 3778 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000, 3779 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000, 3780 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000, 3781 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000, 3782 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000, 3783 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000, 3784 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000, 3785 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000, 3786 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000, 3787 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000, 3788 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000, 3789 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000, 3790 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000, 3791 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000, 3792 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000, 3793 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000, 3794 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000, 3795 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000, 3796 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000, 3797 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000, 3798 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000, 3799 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000, 3800 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000 3801 }; 3802 3803 static const unsigned int mic_svm_vals_lookup[] = { 3804 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 3805 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 3806 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 3807 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 3808 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 3809 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 3810 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 3811 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 3812 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 3813 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 3814 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 3815 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 3816 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 3817 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 3818 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 3819 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 3820 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 3821 }; 3822 3823 static const unsigned int equalizer_vals_lookup[] = { 3824 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 3825 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 3826 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 3827 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 3828 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 3829 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000, 3830 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000, 3831 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 3832 0x41C00000 3833 }; 3834 3835 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid, 3836 const unsigned int *lookup, int idx) 3837 { 3838 int i = 0; 3839 3840 for (i = 0; i < TUNING_CTLS_COUNT; i++) 3841 if (nid == ca0132_tuning_ctls[i].nid) 3842 break; 3843 3844 snd_hda_power_up(codec); 3845 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20, 3846 ca0132_tuning_ctls[i].req, 3847 &(lookup[idx]), sizeof(unsigned int)); 3848 snd_hda_power_down(codec); 3849 3850 return 1; 3851 } 3852 3853 static int tuning_ctl_get(struct snd_kcontrol *kcontrol, 3854 struct snd_ctl_elem_value *ucontrol) 3855 { 3856 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3857 struct ca0132_spec *spec = codec->spec; 3858 hda_nid_t nid = get_amp_nid(kcontrol); 3859 long *valp = ucontrol->value.integer.value; 3860 int idx = nid - TUNING_CTL_START_NID; 3861 3862 *valp = spec->cur_ctl_vals[idx]; 3863 return 0; 3864 } 3865 3866 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol, 3867 struct snd_ctl_elem_info *uinfo) 3868 { 3869 int chs = get_amp_channels(kcontrol); 3870 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3871 uinfo->count = chs == 3 ? 2 : 1; 3872 uinfo->value.integer.min = 20; 3873 uinfo->value.integer.max = 180; 3874 uinfo->value.integer.step = 1; 3875 3876 return 0; 3877 } 3878 3879 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol, 3880 struct snd_ctl_elem_value *ucontrol) 3881 { 3882 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3883 struct ca0132_spec *spec = codec->spec; 3884 hda_nid_t nid = get_amp_nid(kcontrol); 3885 long *valp = ucontrol->value.integer.value; 3886 int idx; 3887 3888 idx = nid - TUNING_CTL_START_NID; 3889 /* any change? */ 3890 if (spec->cur_ctl_vals[idx] == *valp) 3891 return 0; 3892 3893 spec->cur_ctl_vals[idx] = *valp; 3894 3895 idx = *valp - 20; 3896 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx); 3897 3898 return 1; 3899 } 3900 3901 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol, 3902 struct snd_ctl_elem_info *uinfo) 3903 { 3904 int chs = get_amp_channels(kcontrol); 3905 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3906 uinfo->count = chs == 3 ? 2 : 1; 3907 uinfo->value.integer.min = 0; 3908 uinfo->value.integer.max = 100; 3909 uinfo->value.integer.step = 1; 3910 3911 return 0; 3912 } 3913 3914 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol, 3915 struct snd_ctl_elem_value *ucontrol) 3916 { 3917 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3918 struct ca0132_spec *spec = codec->spec; 3919 hda_nid_t nid = get_amp_nid(kcontrol); 3920 long *valp = ucontrol->value.integer.value; 3921 int idx; 3922 3923 idx = nid - TUNING_CTL_START_NID; 3924 /* any change? */ 3925 if (spec->cur_ctl_vals[idx] == *valp) 3926 return 0; 3927 3928 spec->cur_ctl_vals[idx] = *valp; 3929 3930 idx = *valp; 3931 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx); 3932 3933 return 0; 3934 } 3935 3936 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol, 3937 struct snd_ctl_elem_info *uinfo) 3938 { 3939 int chs = get_amp_channels(kcontrol); 3940 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3941 uinfo->count = chs == 3 ? 2 : 1; 3942 uinfo->value.integer.min = 0; 3943 uinfo->value.integer.max = 48; 3944 uinfo->value.integer.step = 1; 3945 3946 return 0; 3947 } 3948 3949 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol, 3950 struct snd_ctl_elem_value *ucontrol) 3951 { 3952 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3953 struct ca0132_spec *spec = codec->spec; 3954 hda_nid_t nid = get_amp_nid(kcontrol); 3955 long *valp = ucontrol->value.integer.value; 3956 int idx; 3957 3958 idx = nid - TUNING_CTL_START_NID; 3959 /* any change? */ 3960 if (spec->cur_ctl_vals[idx] == *valp) 3961 return 0; 3962 3963 spec->cur_ctl_vals[idx] = *valp; 3964 3965 idx = *valp; 3966 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx); 3967 3968 return 1; 3969 } 3970 3971 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0); 3972 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0); 3973 3974 static int add_tuning_control(struct hda_codec *codec, 3975 hda_nid_t pnid, hda_nid_t nid, 3976 const char *name, int dir) 3977 { 3978 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 3979 int type = dir ? HDA_INPUT : HDA_OUTPUT; 3980 struct snd_kcontrol_new knew = 3981 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 3982 3983 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 3984 SNDRV_CTL_ELEM_ACCESS_TLV_READ; 3985 knew.tlv.c = 0; 3986 knew.tlv.p = 0; 3987 switch (pnid) { 3988 case VOICE_FOCUS: 3989 knew.info = voice_focus_ctl_info; 3990 knew.get = tuning_ctl_get; 3991 knew.put = voice_focus_ctl_put; 3992 knew.tlv.p = voice_focus_db_scale; 3993 break; 3994 case MIC_SVM: 3995 knew.info = mic_svm_ctl_info; 3996 knew.get = tuning_ctl_get; 3997 knew.put = mic_svm_ctl_put; 3998 break; 3999 case EQUALIZER: 4000 knew.info = equalizer_ctl_info; 4001 knew.get = tuning_ctl_get; 4002 knew.put = equalizer_ctl_put; 4003 knew.tlv.p = eq_db_scale; 4004 break; 4005 default: 4006 return 0; 4007 } 4008 knew.private_value = 4009 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 4010 sprintf(namestr, "%s %s Volume", name, dirstr[dir]); 4011 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 4012 } 4013 4014 static int add_tuning_ctls(struct hda_codec *codec) 4015 { 4016 int i; 4017 int err; 4018 4019 for (i = 0; i < TUNING_CTLS_COUNT; i++) { 4020 err = add_tuning_control(codec, 4021 ca0132_tuning_ctls[i].parent_nid, 4022 ca0132_tuning_ctls[i].nid, 4023 ca0132_tuning_ctls[i].name, 4024 ca0132_tuning_ctls[i].direct); 4025 if (err < 0) 4026 return err; 4027 } 4028 4029 return 0; 4030 } 4031 4032 static void ca0132_init_tuning_defaults(struct hda_codec *codec) 4033 { 4034 struct ca0132_spec *spec = codec->spec; 4035 int i; 4036 4037 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */ 4038 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10; 4039 /* SVM level defaults to 0.74. */ 4040 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74; 4041 4042 /* EQ defaults to 0dB. */ 4043 for (i = 2; i < TUNING_CTLS_COUNT; i++) 4044 spec->cur_ctl_vals[i] = 24; 4045 } 4046 #endif /*ENABLE_TUNING_CONTROLS*/ 4047 4048 /* 4049 * Select the active output. 4050 * If autodetect is enabled, output will be selected based on jack detection. 4051 * If jack inserted, headphone will be selected, else built-in speakers 4052 * If autodetect is disabled, output will be selected based on selection. 4053 */ 4054 static int ca0132_select_out(struct hda_codec *codec) 4055 { 4056 struct ca0132_spec *spec = codec->spec; 4057 unsigned int pin_ctl; 4058 int jack_present; 4059 int auto_jack; 4060 unsigned int tmp; 4061 int err; 4062 4063 codec_dbg(codec, "ca0132_select_out\n"); 4064 4065 snd_hda_power_up_pm(codec); 4066 4067 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4068 4069 if (auto_jack) 4070 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp); 4071 else 4072 jack_present = 4073 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID]; 4074 4075 if (jack_present) 4076 spec->cur_out_type = HEADPHONE_OUT; 4077 else 4078 spec->cur_out_type = SPEAKER_OUT; 4079 4080 if (spec->cur_out_type == SPEAKER_OUT) { 4081 codec_dbg(codec, "ca0132_select_out speaker\n"); 4082 /*speaker out config*/ 4083 tmp = FLOAT_ONE; 4084 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4085 if (err < 0) 4086 goto exit; 4087 /*enable speaker EQ*/ 4088 tmp = FLOAT_ONE; 4089 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4090 if (err < 0) 4091 goto exit; 4092 4093 /* Setup EAPD */ 4094 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4095 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4096 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4097 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4098 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4099 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4100 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4101 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4102 4103 /* disable headphone node */ 4104 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4105 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4106 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4107 pin_ctl & ~PIN_HP); 4108 /* enable speaker node */ 4109 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4110 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4111 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4112 pin_ctl | PIN_OUT); 4113 } else { 4114 codec_dbg(codec, "ca0132_select_out hp\n"); 4115 /*headphone out config*/ 4116 tmp = FLOAT_ZERO; 4117 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4118 if (err < 0) 4119 goto exit; 4120 /*disable speaker EQ*/ 4121 tmp = FLOAT_ZERO; 4122 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4123 if (err < 0) 4124 goto exit; 4125 4126 /* Setup EAPD */ 4127 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4128 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4129 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4130 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4131 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4132 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4133 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4134 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4135 4136 /* disable speaker*/ 4137 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4138 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4139 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4140 pin_ctl & ~PIN_HP); 4141 /* enable headphone*/ 4142 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4143 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4144 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4145 pin_ctl | PIN_HP); 4146 } 4147 4148 exit: 4149 snd_hda_power_down_pm(codec); 4150 4151 return err < 0 ? err : 0; 4152 } 4153 4154 static int ae5_headphone_gain_set(struct hda_codec *codec, long val); 4155 static int zxr_headphone_gain_set(struct hda_codec *codec, long val); 4156 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val); 4157 4158 static void ae5_mmio_select_out(struct hda_codec *codec) 4159 { 4160 struct ca0132_spec *spec = codec->spec; 4161 unsigned int i; 4162 4163 for (i = 0; i < AE5_CA0113_OUT_SET_COMMANDS; i++) 4164 ca0113_mmio_command_set(codec, 4165 ae5_ca0113_output_presets[spec->cur_out_type].group[i], 4166 ae5_ca0113_output_presets[spec->cur_out_type].target[i], 4167 ae5_ca0113_output_presets[spec->cur_out_type].vals[i]); 4168 } 4169 4170 /* 4171 * These are the commands needed to setup output on each of the different card 4172 * types. 4173 */ 4174 static void ca0132_alt_select_out_quirk_handler(struct hda_codec *codec) 4175 { 4176 struct ca0132_spec *spec = codec->spec; 4177 unsigned int tmp; 4178 4179 switch (spec->cur_out_type) { 4180 case SPEAKER_OUT: 4181 switch (ca0132_quirk(spec)) { 4182 case QUIRK_SBZ: 4183 ca0113_mmio_gpio_set(codec, 7, false); 4184 ca0113_mmio_gpio_set(codec, 4, true); 4185 ca0113_mmio_gpio_set(codec, 1, true); 4186 chipio_set_control_param(codec, 0x0d, 0x18); 4187 break; 4188 case QUIRK_ZXR: 4189 ca0113_mmio_gpio_set(codec, 2, true); 4190 ca0113_mmio_gpio_set(codec, 3, true); 4191 ca0113_mmio_gpio_set(codec, 5, false); 4192 zxr_headphone_gain_set(codec, 0); 4193 chipio_set_control_param(codec, 0x0d, 0x24); 4194 break; 4195 case QUIRK_R3DI: 4196 chipio_set_control_param(codec, 0x0d, 0x24); 4197 r3di_gpio_out_set(codec, R3DI_LINE_OUT); 4198 break; 4199 case QUIRK_R3D: 4200 chipio_set_control_param(codec, 0x0d, 0x24); 4201 ca0113_mmio_gpio_set(codec, 1, true); 4202 break; 4203 case QUIRK_AE5: 4204 ae5_mmio_select_out(codec); 4205 ae5_headphone_gain_set(codec, 2); 4206 tmp = FLOAT_ZERO; 4207 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 4208 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 4209 chipio_set_control_param(codec, 0x0d, 0xa4); 4210 chipio_write(codec, 0x18b03c, 0x00000012); 4211 break; 4212 default: 4213 break; 4214 } 4215 break; 4216 case HEADPHONE_OUT: 4217 switch (ca0132_quirk(spec)) { 4218 case QUIRK_SBZ: 4219 ca0113_mmio_gpio_set(codec, 7, true); 4220 ca0113_mmio_gpio_set(codec, 4, true); 4221 ca0113_mmio_gpio_set(codec, 1, false); 4222 chipio_set_control_param(codec, 0x0d, 0x12); 4223 break; 4224 case QUIRK_ZXR: 4225 ca0113_mmio_gpio_set(codec, 2, false); 4226 ca0113_mmio_gpio_set(codec, 3, false); 4227 ca0113_mmio_gpio_set(codec, 5, true); 4228 zxr_headphone_gain_set(codec, spec->zxr_gain_set); 4229 chipio_set_control_param(codec, 0x0d, 0x21); 4230 break; 4231 case QUIRK_R3DI: 4232 chipio_set_control_param(codec, 0x0d, 0x21); 4233 r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT); 4234 break; 4235 case QUIRK_R3D: 4236 chipio_set_control_param(codec, 0x0d, 0x21); 4237 ca0113_mmio_gpio_set(codec, 0x1, false); 4238 break; 4239 case QUIRK_AE5: 4240 ae5_mmio_select_out(codec); 4241 ae5_headphone_gain_set(codec, 4242 spec->ae5_headphone_gain_val); 4243 tmp = FLOAT_ONE; 4244 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 4245 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 4246 chipio_set_control_param(codec, 0x0d, 0xa1); 4247 chipio_write(codec, 0x18b03c, 0x00000012); 4248 break; 4249 default: 4250 break; 4251 } 4252 break; 4253 case SURROUND_OUT: 4254 switch (ca0132_quirk(spec)) { 4255 case QUIRK_SBZ: 4256 ca0113_mmio_gpio_set(codec, 7, false); 4257 ca0113_mmio_gpio_set(codec, 4, true); 4258 ca0113_mmio_gpio_set(codec, 1, true); 4259 chipio_set_control_param(codec, 0x0d, 0x18); 4260 break; 4261 case QUIRK_ZXR: 4262 ca0113_mmio_gpio_set(codec, 2, true); 4263 ca0113_mmio_gpio_set(codec, 3, true); 4264 ca0113_mmio_gpio_set(codec, 5, false); 4265 zxr_headphone_gain_set(codec, 0); 4266 chipio_set_control_param(codec, 0x0d, 0x24); 4267 break; 4268 case QUIRK_R3DI: 4269 chipio_set_control_param(codec, 0x0d, 0x24); 4270 r3di_gpio_out_set(codec, R3DI_LINE_OUT); 4271 break; 4272 case QUIRK_R3D: 4273 ca0113_mmio_gpio_set(codec, 1, true); 4274 chipio_set_control_param(codec, 0x0d, 0x24); 4275 break; 4276 case QUIRK_AE5: 4277 ae5_mmio_select_out(codec); 4278 ae5_headphone_gain_set(codec, 2); 4279 tmp = FLOAT_ZERO; 4280 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 4281 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 4282 chipio_set_control_param(codec, 0x0d, 0xa4); 4283 chipio_write(codec, 0x18b03c, 0x00000012); 4284 break; 4285 default: 4286 break; 4287 } 4288 break; 4289 } 4290 } 4291 4292 /* 4293 * This function behaves similarly to the ca0132_select_out funciton above, 4294 * except with a few differences. It adds the ability to select the current 4295 * output with an enumerated control "output source" if the auto detect 4296 * mute switch is set to off. If the auto detect mute switch is enabled, it 4297 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection. 4298 * It also adds the ability to auto-detect the front headphone port. The only 4299 * way to select surround is to disable auto detect, and set Surround with the 4300 * enumerated control. 4301 */ 4302 static int ca0132_alt_select_out(struct hda_codec *codec) 4303 { 4304 struct ca0132_spec *spec = codec->spec; 4305 unsigned int pin_ctl; 4306 int jack_present; 4307 int auto_jack; 4308 unsigned int i; 4309 unsigned int tmp; 4310 int err; 4311 /* Default Headphone is rear headphone */ 4312 hda_nid_t headphone_nid = spec->out_pins[1]; 4313 4314 codec_dbg(codec, "%s\n", __func__); 4315 4316 snd_hda_power_up_pm(codec); 4317 4318 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4319 4320 /* 4321 * If headphone rear or front is plugged in, set to headphone. 4322 * If neither is plugged in, set to rear line out. Only if 4323 * hp/speaker auto detect is enabled. 4324 */ 4325 if (auto_jack) { 4326 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) || 4327 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp); 4328 4329 if (jack_present) 4330 spec->cur_out_type = HEADPHONE_OUT; 4331 else 4332 spec->cur_out_type = SPEAKER_OUT; 4333 } else 4334 spec->cur_out_type = spec->out_enum_val; 4335 4336 /* Begin DSP output switch */ 4337 tmp = FLOAT_ONE; 4338 err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp); 4339 if (err < 0) 4340 goto exit; 4341 4342 ca0132_alt_select_out_quirk_handler(codec); 4343 4344 switch (spec->cur_out_type) { 4345 case SPEAKER_OUT: 4346 codec_dbg(codec, "%s speaker\n", __func__); 4347 4348 /* disable headphone node */ 4349 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4350 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4351 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4352 pin_ctl & ~PIN_HP); 4353 /* enable line-out node */ 4354 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4355 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4356 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4357 pin_ctl | PIN_OUT); 4358 /* Enable EAPD */ 4359 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4360 AC_VERB_SET_EAPD_BTLENABLE, 0x01); 4361 4362 /* If PlayEnhancement is enabled, set different source */ 4363 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4364 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE); 4365 else 4366 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT); 4367 break; 4368 case HEADPHONE_OUT: 4369 codec_dbg(codec, "%s hp\n", __func__); 4370 4371 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4372 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4373 4374 /* disable speaker*/ 4375 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4376 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4377 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4378 pin_ctl & ~PIN_HP); 4379 4380 /* enable headphone, either front or rear */ 4381 4382 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp)) 4383 headphone_nid = spec->out_pins[2]; 4384 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp)) 4385 headphone_nid = spec->out_pins[1]; 4386 4387 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0, 4388 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4389 snd_hda_set_pin_ctl(codec, headphone_nid, 4390 pin_ctl | PIN_HP); 4391 4392 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4393 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE); 4394 else 4395 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO); 4396 break; 4397 case SURROUND_OUT: 4398 codec_dbg(codec, "%s surround\n", __func__); 4399 4400 /* enable line out node */ 4401 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4402 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4403 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4404 pin_ctl | PIN_OUT); 4405 /* Disable headphone out */ 4406 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4407 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4408 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4409 pin_ctl & ~PIN_HP); 4410 /* Enable EAPD on line out */ 4411 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4412 AC_VERB_SET_EAPD_BTLENABLE, 0x01); 4413 /* enable center/lfe out node */ 4414 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0, 4415 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4416 snd_hda_set_pin_ctl(codec, spec->out_pins[2], 4417 pin_ctl | PIN_OUT); 4418 /* Now set rear surround node as out. */ 4419 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0, 4420 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4421 snd_hda_set_pin_ctl(codec, spec->out_pins[3], 4422 pin_ctl | PIN_OUT); 4423 4424 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT); 4425 break; 4426 } 4427 /* 4428 * Surround always sets it's scp command to req 0x04 to FLOAT_EIGHT. 4429 * With this set though, X_BASS cannot be enabled. So, if we have OutFX 4430 * enabled, we need to make sure X_BASS is off, otherwise everything 4431 * sounds all muffled. Running ca0132_effects_set with X_BASS as the 4432 * effect should sort this out. 4433 */ 4434 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4435 ca0132_effects_set(codec, X_BASS, 4436 spec->effects_switch[X_BASS - EFFECT_START_NID]); 4437 4438 /* run through the output dsp commands for the selected output. */ 4439 for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) { 4440 err = dspio_set_uint_param(codec, 4441 alt_out_presets[spec->cur_out_type].mids[i], 4442 alt_out_presets[spec->cur_out_type].reqs[i], 4443 alt_out_presets[spec->cur_out_type].vals[i]); 4444 4445 if (err < 0) 4446 goto exit; 4447 } 4448 4449 exit: 4450 snd_hda_power_down_pm(codec); 4451 4452 return err < 0 ? err : 0; 4453 } 4454 4455 static void ca0132_unsol_hp_delayed(struct work_struct *work) 4456 { 4457 struct ca0132_spec *spec = container_of( 4458 to_delayed_work(work), struct ca0132_spec, unsol_hp_work); 4459 struct hda_jack_tbl *jack; 4460 4461 if (ca0132_use_alt_functions(spec)) 4462 ca0132_alt_select_out(spec->codec); 4463 else 4464 ca0132_select_out(spec->codec); 4465 4466 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp); 4467 if (jack) { 4468 jack->block_report = 0; 4469 snd_hda_jack_report_sync(spec->codec); 4470 } 4471 } 4472 4473 static void ca0132_set_dmic(struct hda_codec *codec, int enable); 4474 static int ca0132_mic_boost_set(struct hda_codec *codec, long val); 4475 static void resume_mic1(struct hda_codec *codec, unsigned int oldval); 4476 static int stop_mic1(struct hda_codec *codec); 4477 static int ca0132_cvoice_switch_set(struct hda_codec *codec); 4478 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val); 4479 4480 /* 4481 * Select the active VIP source 4482 */ 4483 static int ca0132_set_vipsource(struct hda_codec *codec, int val) 4484 { 4485 struct ca0132_spec *spec = codec->spec; 4486 unsigned int tmp; 4487 4488 if (spec->dsp_state != DSP_DOWNLOADED) 4489 return 0; 4490 4491 /* if CrystalVoice if off, vipsource should be 0 */ 4492 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4493 (val == 0)) { 4494 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4495 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4496 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4497 if (spec->cur_mic_type == DIGITAL_MIC) 4498 tmp = FLOAT_TWO; 4499 else 4500 tmp = FLOAT_ONE; 4501 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4502 tmp = FLOAT_ZERO; 4503 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4504 } else { 4505 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4506 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4507 if (spec->cur_mic_type == DIGITAL_MIC) 4508 tmp = FLOAT_TWO; 4509 else 4510 tmp = FLOAT_ONE; 4511 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4512 tmp = FLOAT_ONE; 4513 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4514 msleep(20); 4515 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4516 } 4517 4518 return 1; 4519 } 4520 4521 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val) 4522 { 4523 struct ca0132_spec *spec = codec->spec; 4524 unsigned int tmp; 4525 4526 if (spec->dsp_state != DSP_DOWNLOADED) 4527 return 0; 4528 4529 codec_dbg(codec, "%s\n", __func__); 4530 4531 chipio_set_stream_control(codec, 0x03, 0); 4532 chipio_set_stream_control(codec, 0x04, 0); 4533 4534 /* if CrystalVoice is off, vipsource should be 0 */ 4535 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4536 (val == 0) || spec->in_enum_val == REAR_LINE_IN) { 4537 codec_dbg(codec, "%s: off.", __func__); 4538 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4539 4540 tmp = FLOAT_ZERO; 4541 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4542 4543 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4544 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4545 if (ca0132_quirk(spec) == QUIRK_R3DI) 4546 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4547 4548 4549 if (spec->in_enum_val == REAR_LINE_IN) 4550 tmp = FLOAT_ZERO; 4551 else { 4552 if (ca0132_quirk(spec) == QUIRK_SBZ) 4553 tmp = FLOAT_THREE; 4554 else 4555 tmp = FLOAT_ONE; 4556 } 4557 4558 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4559 4560 } else { 4561 codec_dbg(codec, "%s: on.", __func__); 4562 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4563 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4564 if (ca0132_quirk(spec) == QUIRK_R3DI) 4565 chipio_set_conn_rate(codec, 0x0F, SR_16_000); 4566 4567 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID]) 4568 tmp = FLOAT_TWO; 4569 else 4570 tmp = FLOAT_ONE; 4571 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4572 4573 tmp = FLOAT_ONE; 4574 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4575 4576 msleep(20); 4577 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4578 } 4579 4580 chipio_set_stream_control(codec, 0x03, 1); 4581 chipio_set_stream_control(codec, 0x04, 1); 4582 4583 return 1; 4584 } 4585 4586 /* 4587 * Select the active microphone. 4588 * If autodetect is enabled, mic will be selected based on jack detection. 4589 * If jack inserted, ext.mic will be selected, else built-in mic 4590 * If autodetect is disabled, mic will be selected based on selection. 4591 */ 4592 static int ca0132_select_mic(struct hda_codec *codec) 4593 { 4594 struct ca0132_spec *spec = codec->spec; 4595 int jack_present; 4596 int auto_jack; 4597 4598 codec_dbg(codec, "ca0132_select_mic\n"); 4599 4600 snd_hda_power_up_pm(codec); 4601 4602 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 4603 4604 if (auto_jack) 4605 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1); 4606 else 4607 jack_present = 4608 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID]; 4609 4610 if (jack_present) 4611 spec->cur_mic_type = LINE_MIC_IN; 4612 else 4613 spec->cur_mic_type = DIGITAL_MIC; 4614 4615 if (spec->cur_mic_type == DIGITAL_MIC) { 4616 /* enable digital Mic */ 4617 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000); 4618 ca0132_set_dmic(codec, 1); 4619 ca0132_mic_boost_set(codec, 0); 4620 /* set voice focus */ 4621 ca0132_effects_set(codec, VOICE_FOCUS, 4622 spec->effects_switch 4623 [VOICE_FOCUS - EFFECT_START_NID]); 4624 } else { 4625 /* disable digital Mic */ 4626 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000); 4627 ca0132_set_dmic(codec, 0); 4628 ca0132_mic_boost_set(codec, spec->cur_mic_boost); 4629 /* disable voice focus */ 4630 ca0132_effects_set(codec, VOICE_FOCUS, 0); 4631 } 4632 4633 snd_hda_power_down_pm(codec); 4634 4635 return 0; 4636 } 4637 4638 /* 4639 * Select the active input. 4640 * Mic detection isn't used, because it's kind of pointless on the SBZ. 4641 * The front mic has no jack-detection, so the only way to switch to it 4642 * is to do it manually in alsamixer. 4643 */ 4644 static int ca0132_alt_select_in(struct hda_codec *codec) 4645 { 4646 struct ca0132_spec *spec = codec->spec; 4647 unsigned int tmp; 4648 4649 codec_dbg(codec, "%s\n", __func__); 4650 4651 snd_hda_power_up_pm(codec); 4652 4653 chipio_set_stream_control(codec, 0x03, 0); 4654 chipio_set_stream_control(codec, 0x04, 0); 4655 4656 spec->cur_mic_type = spec->in_enum_val; 4657 4658 switch (spec->cur_mic_type) { 4659 case REAR_MIC: 4660 switch (ca0132_quirk(spec)) { 4661 case QUIRK_SBZ: 4662 case QUIRK_R3D: 4663 ca0113_mmio_gpio_set(codec, 0, false); 4664 tmp = FLOAT_THREE; 4665 break; 4666 case QUIRK_ZXR: 4667 tmp = FLOAT_THREE; 4668 break; 4669 case QUIRK_R3DI: 4670 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 4671 tmp = FLOAT_ONE; 4672 break; 4673 case QUIRK_AE5: 4674 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x00); 4675 tmp = FLOAT_THREE; 4676 break; 4677 default: 4678 tmp = FLOAT_ONE; 4679 break; 4680 } 4681 4682 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4683 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4684 if (ca0132_quirk(spec) == QUIRK_R3DI) 4685 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4686 4687 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4688 4689 chipio_set_stream_control(codec, 0x03, 1); 4690 chipio_set_stream_control(codec, 0x04, 1); 4691 switch (ca0132_quirk(spec)) { 4692 case QUIRK_SBZ: 4693 chipio_write(codec, 0x18B098, 0x0000000C); 4694 chipio_write(codec, 0x18B09C, 0x0000000C); 4695 break; 4696 case QUIRK_ZXR: 4697 chipio_write(codec, 0x18B098, 0x0000000C); 4698 chipio_write(codec, 0x18B09C, 0x000000CC); 4699 break; 4700 case QUIRK_AE5: 4701 chipio_write(codec, 0x18B098, 0x0000000C); 4702 chipio_write(codec, 0x18B09C, 0x0000004C); 4703 break; 4704 default: 4705 break; 4706 } 4707 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 4708 break; 4709 case REAR_LINE_IN: 4710 ca0132_mic_boost_set(codec, 0); 4711 switch (ca0132_quirk(spec)) { 4712 case QUIRK_SBZ: 4713 case QUIRK_R3D: 4714 ca0113_mmio_gpio_set(codec, 0, false); 4715 break; 4716 case QUIRK_R3DI: 4717 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 4718 break; 4719 case QUIRK_AE5: 4720 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x00); 4721 break; 4722 default: 4723 break; 4724 } 4725 4726 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4727 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4728 if (ca0132_quirk(spec) == QUIRK_R3DI) 4729 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4730 4731 tmp = FLOAT_ZERO; 4732 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4733 4734 switch (ca0132_quirk(spec)) { 4735 case QUIRK_SBZ: 4736 case QUIRK_AE5: 4737 chipio_write(codec, 0x18B098, 0x00000000); 4738 chipio_write(codec, 0x18B09C, 0x00000000); 4739 break; 4740 default: 4741 break; 4742 } 4743 chipio_set_stream_control(codec, 0x03, 1); 4744 chipio_set_stream_control(codec, 0x04, 1); 4745 break; 4746 case FRONT_MIC: 4747 switch (ca0132_quirk(spec)) { 4748 case QUIRK_SBZ: 4749 case QUIRK_R3D: 4750 ca0113_mmio_gpio_set(codec, 0, true); 4751 ca0113_mmio_gpio_set(codec, 5, false); 4752 tmp = FLOAT_THREE; 4753 break; 4754 case QUIRK_R3DI: 4755 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC); 4756 tmp = FLOAT_ONE; 4757 break; 4758 case QUIRK_AE5: 4759 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x3f); 4760 tmp = FLOAT_THREE; 4761 break; 4762 default: 4763 tmp = FLOAT_ONE; 4764 break; 4765 } 4766 4767 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4768 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4769 if (ca0132_quirk(spec) == QUIRK_R3DI) 4770 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4771 4772 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4773 4774 chipio_set_stream_control(codec, 0x03, 1); 4775 chipio_set_stream_control(codec, 0x04, 1); 4776 4777 switch (ca0132_quirk(spec)) { 4778 case QUIRK_SBZ: 4779 chipio_write(codec, 0x18B098, 0x0000000C); 4780 chipio_write(codec, 0x18B09C, 0x000000CC); 4781 break; 4782 case QUIRK_AE5: 4783 chipio_write(codec, 0x18B098, 0x0000000C); 4784 chipio_write(codec, 0x18B09C, 0x0000004C); 4785 break; 4786 default: 4787 break; 4788 } 4789 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 4790 break; 4791 } 4792 ca0132_cvoice_switch_set(codec); 4793 4794 snd_hda_power_down_pm(codec); 4795 return 0; 4796 } 4797 4798 /* 4799 * Check if VNODE settings take effect immediately. 4800 */ 4801 static bool ca0132_is_vnode_effective(struct hda_codec *codec, 4802 hda_nid_t vnid, 4803 hda_nid_t *shared_nid) 4804 { 4805 struct ca0132_spec *spec = codec->spec; 4806 hda_nid_t nid; 4807 4808 switch (vnid) { 4809 case VNID_SPK: 4810 nid = spec->shared_out_nid; 4811 break; 4812 case VNID_MIC: 4813 nid = spec->shared_mic_nid; 4814 break; 4815 default: 4816 return false; 4817 } 4818 4819 if (shared_nid) 4820 *shared_nid = nid; 4821 4822 return true; 4823 } 4824 4825 /* 4826 * The following functions are control change helpers. 4827 * They return 0 if no changed. Return 1 if changed. 4828 */ 4829 static int ca0132_voicefx_set(struct hda_codec *codec, int enable) 4830 { 4831 struct ca0132_spec *spec = codec->spec; 4832 unsigned int tmp; 4833 4834 /* based on CrystalVoice state to enable VoiceFX. */ 4835 if (enable) { 4836 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ? 4837 FLOAT_ONE : FLOAT_ZERO; 4838 } else { 4839 tmp = FLOAT_ZERO; 4840 } 4841 4842 dspio_set_uint_param(codec, ca0132_voicefx.mid, 4843 ca0132_voicefx.reqs[0], tmp); 4844 4845 return 1; 4846 } 4847 4848 /* 4849 * Set the effects parameters 4850 */ 4851 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val) 4852 { 4853 struct ca0132_spec *spec = codec->spec; 4854 unsigned int on, tmp; 4855 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 4856 int err = 0; 4857 int idx = nid - EFFECT_START_NID; 4858 4859 if ((idx < 0) || (idx >= num_fx)) 4860 return 0; /* no changed */ 4861 4862 /* for out effect, qualify with PE */ 4863 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) { 4864 /* if PE if off, turn off out effects. */ 4865 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4866 val = 0; 4867 if (spec->cur_out_type == SURROUND_OUT && nid == X_BASS) 4868 val = 0; 4869 } 4870 4871 /* for in effect, qualify with CrystalVoice */ 4872 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) { 4873 /* if CrystalVoice if off, turn off in effects. */ 4874 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 4875 val = 0; 4876 4877 /* Voice Focus applies to 2-ch Mic, Digital Mic */ 4878 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC)) 4879 val = 0; 4880 4881 /* If Voice Focus on SBZ, set to two channel. */ 4882 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec) 4883 && (spec->cur_mic_type != REAR_LINE_IN)) { 4884 if (spec->effects_switch[CRYSTAL_VOICE - 4885 EFFECT_START_NID]) { 4886 4887 if (spec->effects_switch[VOICE_FOCUS - 4888 EFFECT_START_NID]) { 4889 tmp = FLOAT_TWO; 4890 val = 1; 4891 } else 4892 tmp = FLOAT_ONE; 4893 4894 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4895 } 4896 } 4897 /* 4898 * For SBZ noise reduction, there's an extra command 4899 * to module ID 0x47. No clue why. 4900 */ 4901 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec) 4902 && (spec->cur_mic_type != REAR_LINE_IN)) { 4903 if (spec->effects_switch[CRYSTAL_VOICE - 4904 EFFECT_START_NID]) { 4905 if (spec->effects_switch[NOISE_REDUCTION - 4906 EFFECT_START_NID]) 4907 tmp = FLOAT_ONE; 4908 else 4909 tmp = FLOAT_ZERO; 4910 } else 4911 tmp = FLOAT_ZERO; 4912 4913 dspio_set_uint_param(codec, 0x47, 0x00, tmp); 4914 } 4915 4916 /* If rear line in disable effects. */ 4917 if (ca0132_use_alt_functions(spec) && 4918 spec->in_enum_val == REAR_LINE_IN) 4919 val = 0; 4920 } 4921 4922 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n", 4923 nid, val); 4924 4925 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE; 4926 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid, 4927 ca0132_effects[idx].reqs[0], on); 4928 4929 if (err < 0) 4930 return 0; /* no changed */ 4931 4932 return 1; 4933 } 4934 4935 /* 4936 * Turn on/off Playback Enhancements 4937 */ 4938 static int ca0132_pe_switch_set(struct hda_codec *codec) 4939 { 4940 struct ca0132_spec *spec = codec->spec; 4941 hda_nid_t nid; 4942 int i, ret = 0; 4943 4944 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n", 4945 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]); 4946 4947 if (ca0132_use_alt_functions(spec)) 4948 ca0132_alt_select_out(codec); 4949 4950 i = OUT_EFFECT_START_NID - EFFECT_START_NID; 4951 nid = OUT_EFFECT_START_NID; 4952 /* PE affects all out effects */ 4953 for (; nid < OUT_EFFECT_END_NID; nid++, i++) 4954 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 4955 4956 return ret; 4957 } 4958 4959 /* Check if Mic1 is streaming, if so, stop streaming */ 4960 static int stop_mic1(struct hda_codec *codec) 4961 { 4962 struct ca0132_spec *spec = codec->spec; 4963 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0, 4964 AC_VERB_GET_CONV, 0); 4965 if (oldval != 0) 4966 snd_hda_codec_write(codec, spec->adcs[0], 0, 4967 AC_VERB_SET_CHANNEL_STREAMID, 4968 0); 4969 return oldval; 4970 } 4971 4972 /* Resume Mic1 streaming if it was stopped. */ 4973 static void resume_mic1(struct hda_codec *codec, unsigned int oldval) 4974 { 4975 struct ca0132_spec *spec = codec->spec; 4976 /* Restore the previous stream and channel */ 4977 if (oldval != 0) 4978 snd_hda_codec_write(codec, spec->adcs[0], 0, 4979 AC_VERB_SET_CHANNEL_STREAMID, 4980 oldval); 4981 } 4982 4983 /* 4984 * Turn on/off CrystalVoice 4985 */ 4986 static int ca0132_cvoice_switch_set(struct hda_codec *codec) 4987 { 4988 struct ca0132_spec *spec = codec->spec; 4989 hda_nid_t nid; 4990 int i, ret = 0; 4991 unsigned int oldval; 4992 4993 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n", 4994 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]); 4995 4996 i = IN_EFFECT_START_NID - EFFECT_START_NID; 4997 nid = IN_EFFECT_START_NID; 4998 /* CrystalVoice affects all in effects */ 4999 for (; nid < IN_EFFECT_END_NID; nid++, i++) 5000 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 5001 5002 /* including VoiceFX */ 5003 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0)); 5004 5005 /* set correct vipsource */ 5006 oldval = stop_mic1(codec); 5007 if (ca0132_use_alt_functions(spec)) 5008 ret |= ca0132_alt_set_vipsource(codec, 1); 5009 else 5010 ret |= ca0132_set_vipsource(codec, 1); 5011 resume_mic1(codec, oldval); 5012 return ret; 5013 } 5014 5015 static int ca0132_mic_boost_set(struct hda_codec *codec, long val) 5016 { 5017 struct ca0132_spec *spec = codec->spec; 5018 int ret = 0; 5019 5020 if (val) /* on */ 5021 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5022 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3); 5023 else /* off */ 5024 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5025 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0); 5026 5027 return ret; 5028 } 5029 5030 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val) 5031 { 5032 struct ca0132_spec *spec = codec->spec; 5033 int ret = 0; 5034 5035 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5036 HDA_INPUT, 0, HDA_AMP_VOLMASK, val); 5037 return ret; 5038 } 5039 5040 static int ae5_headphone_gain_set(struct hda_codec *codec, long val) 5041 { 5042 unsigned int i; 5043 5044 for (i = 0; i < 4; i++) 5045 ca0113_mmio_command_set(codec, 0x48, 0x11 + i, 5046 ae5_headphone_gain_presets[val].vals[i]); 5047 return 0; 5048 } 5049 5050 /* 5051 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone 5052 * amplifier to handle a 600 ohm load. 5053 */ 5054 static int zxr_headphone_gain_set(struct hda_codec *codec, long val) 5055 { 5056 ca0113_mmio_gpio_set(codec, 1, val); 5057 5058 return 0; 5059 } 5060 5061 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol, 5062 struct snd_ctl_elem_value *ucontrol) 5063 { 5064 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5065 hda_nid_t nid = get_amp_nid(kcontrol); 5066 hda_nid_t shared_nid = 0; 5067 bool effective; 5068 int ret = 0; 5069 struct ca0132_spec *spec = codec->spec; 5070 int auto_jack; 5071 5072 if (nid == VNID_HP_SEL) { 5073 auto_jack = 5074 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 5075 if (!auto_jack) { 5076 if (ca0132_use_alt_functions(spec)) 5077 ca0132_alt_select_out(codec); 5078 else 5079 ca0132_select_out(codec); 5080 } 5081 return 1; 5082 } 5083 5084 if (nid == VNID_AMIC1_SEL) { 5085 auto_jack = 5086 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 5087 if (!auto_jack) 5088 ca0132_select_mic(codec); 5089 return 1; 5090 } 5091 5092 if (nid == VNID_HP_ASEL) { 5093 if (ca0132_use_alt_functions(spec)) 5094 ca0132_alt_select_out(codec); 5095 else 5096 ca0132_select_out(codec); 5097 return 1; 5098 } 5099 5100 if (nid == VNID_AMIC1_ASEL) { 5101 ca0132_select_mic(codec); 5102 return 1; 5103 } 5104 5105 /* if effective conditions, then update hw immediately. */ 5106 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 5107 if (effective) { 5108 int dir = get_amp_direction(kcontrol); 5109 int ch = get_amp_channels(kcontrol); 5110 unsigned long pval; 5111 5112 mutex_lock(&codec->control_mutex); 5113 pval = kcontrol->private_value; 5114 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 5115 0, dir); 5116 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol); 5117 kcontrol->private_value = pval; 5118 mutex_unlock(&codec->control_mutex); 5119 } 5120 5121 return ret; 5122 } 5123 /* End of control change helpers. */ 5124 /* 5125 * Below I've added controls to mess with the effect levels, I've only enabled 5126 * them on the Sound Blaster Z, but they would probably also work on the 5127 * Chromebook. I figured they were probably tuned specifically for it, and left 5128 * out for a reason. 5129 */ 5130 5131 /* Sets DSP effect level from the sliders above the controls */ 5132 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid, 5133 const unsigned int *lookup, int idx) 5134 { 5135 int i = 0; 5136 unsigned int y; 5137 /* 5138 * For X_BASS, req 2 is actually crossover freq instead of 5139 * effect level 5140 */ 5141 if (nid == X_BASS) 5142 y = 2; 5143 else 5144 y = 1; 5145 5146 snd_hda_power_up(codec); 5147 if (nid == XBASS_XOVER) { 5148 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5149 if (ca0132_effects[i].nid == X_BASS) 5150 break; 5151 5152 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5153 ca0132_effects[i].reqs[1], 5154 &(lookup[idx - 1]), sizeof(unsigned int)); 5155 } else { 5156 /* Find the actual effect structure */ 5157 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5158 if (nid == ca0132_effects[i].nid) 5159 break; 5160 5161 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5162 ca0132_effects[i].reqs[y], 5163 &(lookup[idx]), sizeof(unsigned int)); 5164 } 5165 5166 snd_hda_power_down(codec); 5167 5168 return 0; 5169 } 5170 5171 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol, 5172 struct snd_ctl_elem_value *ucontrol) 5173 { 5174 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5175 struct ca0132_spec *spec = codec->spec; 5176 long *valp = ucontrol->value.integer.value; 5177 5178 *valp = spec->xbass_xover_freq; 5179 return 0; 5180 } 5181 5182 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol, 5183 struct snd_ctl_elem_value *ucontrol) 5184 { 5185 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5186 struct ca0132_spec *spec = codec->spec; 5187 hda_nid_t nid = get_amp_nid(kcontrol); 5188 long *valp = ucontrol->value.integer.value; 5189 int idx = nid - OUT_EFFECT_START_NID; 5190 5191 *valp = spec->fx_ctl_val[idx]; 5192 return 0; 5193 } 5194 5195 /* 5196 * The X-bass crossover starts at 10hz, so the min is 1. The 5197 * frequency is set in multiples of 10. 5198 */ 5199 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol, 5200 struct snd_ctl_elem_info *uinfo) 5201 { 5202 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5203 uinfo->count = 1; 5204 uinfo->value.integer.min = 1; 5205 uinfo->value.integer.max = 100; 5206 uinfo->value.integer.step = 1; 5207 5208 return 0; 5209 } 5210 5211 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol, 5212 struct snd_ctl_elem_info *uinfo) 5213 { 5214 int chs = get_amp_channels(kcontrol); 5215 5216 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5217 uinfo->count = chs == 3 ? 2 : 1; 5218 uinfo->value.integer.min = 0; 5219 uinfo->value.integer.max = 100; 5220 uinfo->value.integer.step = 1; 5221 5222 return 0; 5223 } 5224 5225 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol, 5226 struct snd_ctl_elem_value *ucontrol) 5227 { 5228 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5229 struct ca0132_spec *spec = codec->spec; 5230 hda_nid_t nid = get_amp_nid(kcontrol); 5231 long *valp = ucontrol->value.integer.value; 5232 int idx; 5233 5234 /* any change? */ 5235 if (spec->xbass_xover_freq == *valp) 5236 return 0; 5237 5238 spec->xbass_xover_freq = *valp; 5239 5240 idx = *valp; 5241 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx); 5242 5243 return 0; 5244 } 5245 5246 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol, 5247 struct snd_ctl_elem_value *ucontrol) 5248 { 5249 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5250 struct ca0132_spec *spec = codec->spec; 5251 hda_nid_t nid = get_amp_nid(kcontrol); 5252 long *valp = ucontrol->value.integer.value; 5253 int idx; 5254 5255 idx = nid - EFFECT_START_NID; 5256 /* any change? */ 5257 if (spec->fx_ctl_val[idx] == *valp) 5258 return 0; 5259 5260 spec->fx_ctl_val[idx] = *valp; 5261 5262 idx = *valp; 5263 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx); 5264 5265 return 0; 5266 } 5267 5268 5269 /* 5270 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original 5271 * only has off or full 30 dB, and didn't like making a volume slider that has 5272 * traditional 0-100 in alsamixer that goes in big steps. I like enum better. 5273 */ 5274 #define MIC_BOOST_NUM_OF_STEPS 4 5275 #define MIC_BOOST_ENUM_MAX_STRLEN 10 5276 5277 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol, 5278 struct snd_ctl_elem_info *uinfo) 5279 { 5280 char *sfx = "dB"; 5281 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5282 5283 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5284 uinfo->count = 1; 5285 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS; 5286 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS) 5287 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1; 5288 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx); 5289 strcpy(uinfo->value.enumerated.name, namestr); 5290 return 0; 5291 } 5292 5293 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol, 5294 struct snd_ctl_elem_value *ucontrol) 5295 { 5296 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5297 struct ca0132_spec *spec = codec->spec; 5298 5299 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val; 5300 return 0; 5301 } 5302 5303 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol, 5304 struct snd_ctl_elem_value *ucontrol) 5305 { 5306 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5307 struct ca0132_spec *spec = codec->spec; 5308 int sel = ucontrol->value.enumerated.item[0]; 5309 unsigned int items = MIC_BOOST_NUM_OF_STEPS; 5310 5311 if (sel >= items) 5312 return 0; 5313 5314 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n", 5315 sel); 5316 5317 spec->mic_boost_enum_val = sel; 5318 5319 if (spec->in_enum_val != REAR_LINE_IN) 5320 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5321 5322 return 1; 5323 } 5324 5325 /* 5326 * Sound BlasterX AE-5 Headphone Gain Controls. 5327 */ 5328 #define AE5_HEADPHONE_GAIN_MAX 3 5329 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol, 5330 struct snd_ctl_elem_info *uinfo) 5331 { 5332 char *sfx = " Ohms)"; 5333 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5334 5335 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5336 uinfo->count = 1; 5337 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX; 5338 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX) 5339 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1; 5340 sprintf(namestr, "%s %s", 5341 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name, 5342 sfx); 5343 strcpy(uinfo->value.enumerated.name, namestr); 5344 return 0; 5345 } 5346 5347 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol, 5348 struct snd_ctl_elem_value *ucontrol) 5349 { 5350 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5351 struct ca0132_spec *spec = codec->spec; 5352 5353 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val; 5354 return 0; 5355 } 5356 5357 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol, 5358 struct snd_ctl_elem_value *ucontrol) 5359 { 5360 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5361 struct ca0132_spec *spec = codec->spec; 5362 int sel = ucontrol->value.enumerated.item[0]; 5363 unsigned int items = AE5_HEADPHONE_GAIN_MAX; 5364 5365 if (sel >= items) 5366 return 0; 5367 5368 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n", 5369 sel); 5370 5371 spec->ae5_headphone_gain_val = sel; 5372 5373 if (spec->out_enum_val == HEADPHONE_OUT) 5374 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val); 5375 5376 return 1; 5377 } 5378 5379 /* 5380 * Sound BlasterX AE-5 sound filter enumerated control. 5381 */ 5382 #define AE5_SOUND_FILTER_MAX 3 5383 5384 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol, 5385 struct snd_ctl_elem_info *uinfo) 5386 { 5387 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5388 5389 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5390 uinfo->count = 1; 5391 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX; 5392 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX) 5393 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1; 5394 sprintf(namestr, "%s", 5395 ae5_filter_presets[uinfo->value.enumerated.item].name); 5396 strcpy(uinfo->value.enumerated.name, namestr); 5397 return 0; 5398 } 5399 5400 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol, 5401 struct snd_ctl_elem_value *ucontrol) 5402 { 5403 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5404 struct ca0132_spec *spec = codec->spec; 5405 5406 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val; 5407 return 0; 5408 } 5409 5410 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol, 5411 struct snd_ctl_elem_value *ucontrol) 5412 { 5413 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5414 struct ca0132_spec *spec = codec->spec; 5415 int sel = ucontrol->value.enumerated.item[0]; 5416 unsigned int items = AE5_SOUND_FILTER_MAX; 5417 5418 if (sel >= items) 5419 return 0; 5420 5421 codec_dbg(codec, "ae5_sound_filter: %s\n", 5422 ae5_filter_presets[sel].name); 5423 5424 spec->ae5_filter_val = sel; 5425 5426 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 5427 ae5_filter_presets[sel].val); 5428 5429 return 1; 5430 } 5431 5432 /* 5433 * Input Select Control for alternative ca0132 codecs. This exists because 5434 * front microphone has no auto-detect, and we need a way to set the rear 5435 * as line-in 5436 */ 5437 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol, 5438 struct snd_ctl_elem_info *uinfo) 5439 { 5440 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5441 uinfo->count = 1; 5442 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS; 5443 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS) 5444 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1; 5445 strcpy(uinfo->value.enumerated.name, 5446 in_src_str[uinfo->value.enumerated.item]); 5447 return 0; 5448 } 5449 5450 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol, 5451 struct snd_ctl_elem_value *ucontrol) 5452 { 5453 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5454 struct ca0132_spec *spec = codec->spec; 5455 5456 ucontrol->value.enumerated.item[0] = spec->in_enum_val; 5457 return 0; 5458 } 5459 5460 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol, 5461 struct snd_ctl_elem_value *ucontrol) 5462 { 5463 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5464 struct ca0132_spec *spec = codec->spec; 5465 int sel = ucontrol->value.enumerated.item[0]; 5466 unsigned int items = IN_SRC_NUM_OF_INPUTS; 5467 5468 if (sel >= items) 5469 return 0; 5470 5471 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n", 5472 sel, in_src_str[sel]); 5473 5474 spec->in_enum_val = sel; 5475 5476 ca0132_alt_select_in(codec); 5477 5478 return 1; 5479 } 5480 5481 /* Sound Blaster Z Output Select Control */ 5482 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol, 5483 struct snd_ctl_elem_info *uinfo) 5484 { 5485 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5486 uinfo->count = 1; 5487 uinfo->value.enumerated.items = NUM_OF_OUTPUTS; 5488 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS) 5489 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1; 5490 strcpy(uinfo->value.enumerated.name, 5491 alt_out_presets[uinfo->value.enumerated.item].name); 5492 return 0; 5493 } 5494 5495 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol, 5496 struct snd_ctl_elem_value *ucontrol) 5497 { 5498 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5499 struct ca0132_spec *spec = codec->spec; 5500 5501 ucontrol->value.enumerated.item[0] = spec->out_enum_val; 5502 return 0; 5503 } 5504 5505 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol, 5506 struct snd_ctl_elem_value *ucontrol) 5507 { 5508 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5509 struct ca0132_spec *spec = codec->spec; 5510 int sel = ucontrol->value.enumerated.item[0]; 5511 unsigned int items = NUM_OF_OUTPUTS; 5512 unsigned int auto_jack; 5513 5514 if (sel >= items) 5515 return 0; 5516 5517 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n", 5518 sel, alt_out_presets[sel].name); 5519 5520 spec->out_enum_val = sel; 5521 5522 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 5523 5524 if (!auto_jack) 5525 ca0132_alt_select_out(codec); 5526 5527 return 1; 5528 } 5529 5530 /* 5531 * Smart Volume output setting control. Three different settings, Normal, 5532 * which takes the value from the smart volume slider. The two others, loud 5533 * and night, disregard the slider value and have uneditable values. 5534 */ 5535 #define NUM_OF_SVM_SETTINGS 3 5536 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" }; 5537 5538 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol, 5539 struct snd_ctl_elem_info *uinfo) 5540 { 5541 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5542 uinfo->count = 1; 5543 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS; 5544 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS) 5545 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1; 5546 strcpy(uinfo->value.enumerated.name, 5547 out_svm_set_enum_str[uinfo->value.enumerated.item]); 5548 return 0; 5549 } 5550 5551 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol, 5552 struct snd_ctl_elem_value *ucontrol) 5553 { 5554 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5555 struct ca0132_spec *spec = codec->spec; 5556 5557 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting; 5558 return 0; 5559 } 5560 5561 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol, 5562 struct snd_ctl_elem_value *ucontrol) 5563 { 5564 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5565 struct ca0132_spec *spec = codec->spec; 5566 int sel = ucontrol->value.enumerated.item[0]; 5567 unsigned int items = NUM_OF_SVM_SETTINGS; 5568 unsigned int idx = SMART_VOLUME - EFFECT_START_NID; 5569 unsigned int tmp; 5570 5571 if (sel >= items) 5572 return 0; 5573 5574 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n", 5575 sel, out_svm_set_enum_str[sel]); 5576 5577 spec->smart_volume_setting = sel; 5578 5579 switch (sel) { 5580 case 0: 5581 tmp = FLOAT_ZERO; 5582 break; 5583 case 1: 5584 tmp = FLOAT_ONE; 5585 break; 5586 case 2: 5587 tmp = FLOAT_TWO; 5588 break; 5589 default: 5590 tmp = FLOAT_ZERO; 5591 break; 5592 } 5593 /* Req 2 is the Smart Volume Setting req. */ 5594 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 5595 ca0132_effects[idx].reqs[2], tmp); 5596 return 1; 5597 } 5598 5599 /* Sound Blaster Z EQ preset controls */ 5600 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol, 5601 struct snd_ctl_elem_info *uinfo) 5602 { 5603 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 5604 5605 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5606 uinfo->count = 1; 5607 uinfo->value.enumerated.items = items; 5608 if (uinfo->value.enumerated.item >= items) 5609 uinfo->value.enumerated.item = items - 1; 5610 strcpy(uinfo->value.enumerated.name, 5611 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name); 5612 return 0; 5613 } 5614 5615 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol, 5616 struct snd_ctl_elem_value *ucontrol) 5617 { 5618 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5619 struct ca0132_spec *spec = codec->spec; 5620 5621 ucontrol->value.enumerated.item[0] = spec->eq_preset_val; 5622 return 0; 5623 } 5624 5625 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol, 5626 struct snd_ctl_elem_value *ucontrol) 5627 { 5628 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5629 struct ca0132_spec *spec = codec->spec; 5630 int i, err = 0; 5631 int sel = ucontrol->value.enumerated.item[0]; 5632 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 5633 5634 if (sel >= items) 5635 return 0; 5636 5637 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel, 5638 ca0132_alt_eq_presets[sel].name); 5639 /* 5640 * Idx 0 is default. 5641 * Default needs to qualify with CrystalVoice state. 5642 */ 5643 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) { 5644 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid, 5645 ca0132_alt_eq_enum.reqs[i], 5646 ca0132_alt_eq_presets[sel].vals[i]); 5647 if (err < 0) 5648 break; 5649 } 5650 5651 if (err >= 0) 5652 spec->eq_preset_val = sel; 5653 5654 return 1; 5655 } 5656 5657 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol, 5658 struct snd_ctl_elem_info *uinfo) 5659 { 5660 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets); 5661 5662 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5663 uinfo->count = 1; 5664 uinfo->value.enumerated.items = items; 5665 if (uinfo->value.enumerated.item >= items) 5666 uinfo->value.enumerated.item = items - 1; 5667 strcpy(uinfo->value.enumerated.name, 5668 ca0132_voicefx_presets[uinfo->value.enumerated.item].name); 5669 return 0; 5670 } 5671 5672 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol, 5673 struct snd_ctl_elem_value *ucontrol) 5674 { 5675 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5676 struct ca0132_spec *spec = codec->spec; 5677 5678 ucontrol->value.enumerated.item[0] = spec->voicefx_val; 5679 return 0; 5680 } 5681 5682 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol, 5683 struct snd_ctl_elem_value *ucontrol) 5684 { 5685 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5686 struct ca0132_spec *spec = codec->spec; 5687 int i, err = 0; 5688 int sel = ucontrol->value.enumerated.item[0]; 5689 5690 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets)) 5691 return 0; 5692 5693 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n", 5694 sel, ca0132_voicefx_presets[sel].name); 5695 5696 /* 5697 * Idx 0 is default. 5698 * Default needs to qualify with CrystalVoice state. 5699 */ 5700 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) { 5701 err = dspio_set_uint_param(codec, ca0132_voicefx.mid, 5702 ca0132_voicefx.reqs[i], 5703 ca0132_voicefx_presets[sel].vals[i]); 5704 if (err < 0) 5705 break; 5706 } 5707 5708 if (err >= 0) { 5709 spec->voicefx_val = sel; 5710 /* enable voice fx */ 5711 ca0132_voicefx_set(codec, (sel ? 1 : 0)); 5712 } 5713 5714 return 1; 5715 } 5716 5717 static int ca0132_switch_get(struct snd_kcontrol *kcontrol, 5718 struct snd_ctl_elem_value *ucontrol) 5719 { 5720 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5721 struct ca0132_spec *spec = codec->spec; 5722 hda_nid_t nid = get_amp_nid(kcontrol); 5723 int ch = get_amp_channels(kcontrol); 5724 long *valp = ucontrol->value.integer.value; 5725 5726 /* vnode */ 5727 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 5728 if (ch & 1) { 5729 *valp = spec->vnode_lswitch[nid - VNODE_START_NID]; 5730 valp++; 5731 } 5732 if (ch & 2) { 5733 *valp = spec->vnode_rswitch[nid - VNODE_START_NID]; 5734 valp++; 5735 } 5736 return 0; 5737 } 5738 5739 /* effects, include PE and CrystalVoice */ 5740 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) { 5741 *valp = spec->effects_switch[nid - EFFECT_START_NID]; 5742 return 0; 5743 } 5744 5745 /* mic boost */ 5746 if (nid == spec->input_pins[0]) { 5747 *valp = spec->cur_mic_boost; 5748 return 0; 5749 } 5750 5751 return 0; 5752 } 5753 5754 static int ca0132_switch_put(struct snd_kcontrol *kcontrol, 5755 struct snd_ctl_elem_value *ucontrol) 5756 { 5757 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5758 struct ca0132_spec *spec = codec->spec; 5759 hda_nid_t nid = get_amp_nid(kcontrol); 5760 int ch = get_amp_channels(kcontrol); 5761 long *valp = ucontrol->value.integer.value; 5762 int changed = 1; 5763 5764 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n", 5765 nid, *valp); 5766 5767 snd_hda_power_up(codec); 5768 /* vnode */ 5769 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 5770 if (ch & 1) { 5771 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp; 5772 valp++; 5773 } 5774 if (ch & 2) { 5775 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp; 5776 valp++; 5777 } 5778 changed = ca0132_vnode_switch_set(kcontrol, ucontrol); 5779 goto exit; 5780 } 5781 5782 /* PE */ 5783 if (nid == PLAY_ENHANCEMENT) { 5784 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 5785 changed = ca0132_pe_switch_set(codec); 5786 goto exit; 5787 } 5788 5789 /* CrystalVoice */ 5790 if (nid == CRYSTAL_VOICE) { 5791 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 5792 changed = ca0132_cvoice_switch_set(codec); 5793 goto exit; 5794 } 5795 5796 /* out and in effects */ 5797 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) || 5798 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) { 5799 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 5800 changed = ca0132_effects_set(codec, nid, *valp); 5801 goto exit; 5802 } 5803 5804 /* mic boost */ 5805 if (nid == spec->input_pins[0]) { 5806 spec->cur_mic_boost = *valp; 5807 if (ca0132_use_alt_functions(spec)) { 5808 if (spec->in_enum_val != REAR_LINE_IN) 5809 changed = ca0132_mic_boost_set(codec, *valp); 5810 } else { 5811 /* Mic boost does not apply to Digital Mic */ 5812 if (spec->cur_mic_type != DIGITAL_MIC) 5813 changed = ca0132_mic_boost_set(codec, *valp); 5814 } 5815 5816 goto exit; 5817 } 5818 5819 if (nid == ZXR_HEADPHONE_GAIN) { 5820 spec->zxr_gain_set = *valp; 5821 if (spec->cur_out_type == HEADPHONE_OUT) 5822 changed = zxr_headphone_gain_set(codec, *valp); 5823 else 5824 changed = 0; 5825 5826 goto exit; 5827 } 5828 5829 exit: 5830 snd_hda_power_down(codec); 5831 return changed; 5832 } 5833 5834 /* 5835 * Volume related 5836 */ 5837 /* 5838 * Sets the internal DSP decibel level to match the DAC for output, and the 5839 * ADC for input. Currently only the SBZ sets dsp capture volume level, and 5840 * all alternative codecs set DSP playback volume. 5841 */ 5842 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid) 5843 { 5844 struct ca0132_spec *spec = codec->spec; 5845 unsigned int dsp_dir; 5846 unsigned int lookup_val; 5847 5848 if (nid == VNID_SPK) 5849 dsp_dir = DSP_VOL_OUT; 5850 else 5851 dsp_dir = DSP_VOL_IN; 5852 5853 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID]; 5854 5855 dspio_set_uint_param(codec, 5856 ca0132_alt_vol_ctls[dsp_dir].mid, 5857 ca0132_alt_vol_ctls[dsp_dir].reqs[0], 5858 float_vol_db_lookup[lookup_val]); 5859 5860 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID]; 5861 5862 dspio_set_uint_param(codec, 5863 ca0132_alt_vol_ctls[dsp_dir].mid, 5864 ca0132_alt_vol_ctls[dsp_dir].reqs[1], 5865 float_vol_db_lookup[lookup_val]); 5866 5867 dspio_set_uint_param(codec, 5868 ca0132_alt_vol_ctls[dsp_dir].mid, 5869 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO); 5870 } 5871 5872 static int ca0132_volume_info(struct snd_kcontrol *kcontrol, 5873 struct snd_ctl_elem_info *uinfo) 5874 { 5875 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5876 struct ca0132_spec *spec = codec->spec; 5877 hda_nid_t nid = get_amp_nid(kcontrol); 5878 int ch = get_amp_channels(kcontrol); 5879 int dir = get_amp_direction(kcontrol); 5880 unsigned long pval; 5881 int err; 5882 5883 switch (nid) { 5884 case VNID_SPK: 5885 /* follow shared_out info */ 5886 nid = spec->shared_out_nid; 5887 mutex_lock(&codec->control_mutex); 5888 pval = kcontrol->private_value; 5889 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 5890 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 5891 kcontrol->private_value = pval; 5892 mutex_unlock(&codec->control_mutex); 5893 break; 5894 case VNID_MIC: 5895 /* follow shared_mic info */ 5896 nid = spec->shared_mic_nid; 5897 mutex_lock(&codec->control_mutex); 5898 pval = kcontrol->private_value; 5899 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 5900 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 5901 kcontrol->private_value = pval; 5902 mutex_unlock(&codec->control_mutex); 5903 break; 5904 default: 5905 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 5906 } 5907 return err; 5908 } 5909 5910 static int ca0132_volume_get(struct snd_kcontrol *kcontrol, 5911 struct snd_ctl_elem_value *ucontrol) 5912 { 5913 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5914 struct ca0132_spec *spec = codec->spec; 5915 hda_nid_t nid = get_amp_nid(kcontrol); 5916 int ch = get_amp_channels(kcontrol); 5917 long *valp = ucontrol->value.integer.value; 5918 5919 /* store the left and right volume */ 5920 if (ch & 1) { 5921 *valp = spec->vnode_lvol[nid - VNODE_START_NID]; 5922 valp++; 5923 } 5924 if (ch & 2) { 5925 *valp = spec->vnode_rvol[nid - VNODE_START_NID]; 5926 valp++; 5927 } 5928 return 0; 5929 } 5930 5931 static int ca0132_volume_put(struct snd_kcontrol *kcontrol, 5932 struct snd_ctl_elem_value *ucontrol) 5933 { 5934 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5935 struct ca0132_spec *spec = codec->spec; 5936 hda_nid_t nid = get_amp_nid(kcontrol); 5937 int ch = get_amp_channels(kcontrol); 5938 long *valp = ucontrol->value.integer.value; 5939 hda_nid_t shared_nid = 0; 5940 bool effective; 5941 int changed = 1; 5942 5943 /* store the left and right volume */ 5944 if (ch & 1) { 5945 spec->vnode_lvol[nid - VNODE_START_NID] = *valp; 5946 valp++; 5947 } 5948 if (ch & 2) { 5949 spec->vnode_rvol[nid - VNODE_START_NID] = *valp; 5950 valp++; 5951 } 5952 5953 /* if effective conditions, then update hw immediately. */ 5954 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 5955 if (effective) { 5956 int dir = get_amp_direction(kcontrol); 5957 unsigned long pval; 5958 5959 snd_hda_power_up(codec); 5960 mutex_lock(&codec->control_mutex); 5961 pval = kcontrol->private_value; 5962 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 5963 0, dir); 5964 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 5965 kcontrol->private_value = pval; 5966 mutex_unlock(&codec->control_mutex); 5967 snd_hda_power_down(codec); 5968 } 5969 5970 return changed; 5971 } 5972 5973 /* 5974 * This function is the same as the one above, because using an if statement 5975 * inside of the above volume control for the DSP volume would cause too much 5976 * lag. This is a lot more smooth. 5977 */ 5978 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol, 5979 struct snd_ctl_elem_value *ucontrol) 5980 { 5981 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5982 struct ca0132_spec *spec = codec->spec; 5983 hda_nid_t nid = get_amp_nid(kcontrol); 5984 int ch = get_amp_channels(kcontrol); 5985 long *valp = ucontrol->value.integer.value; 5986 hda_nid_t vnid = 0; 5987 int changed; 5988 5989 switch (nid) { 5990 case 0x02: 5991 vnid = VNID_SPK; 5992 break; 5993 case 0x07: 5994 vnid = VNID_MIC; 5995 break; 5996 } 5997 5998 /* store the left and right volume */ 5999 if (ch & 1) { 6000 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp; 6001 valp++; 6002 } 6003 if (ch & 2) { 6004 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp; 6005 valp++; 6006 } 6007 6008 snd_hda_power_up(codec); 6009 ca0132_alt_dsp_volume_put(codec, vnid); 6010 mutex_lock(&codec->control_mutex); 6011 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 6012 mutex_unlock(&codec->control_mutex); 6013 snd_hda_power_down(codec); 6014 6015 return changed; 6016 } 6017 6018 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag, 6019 unsigned int size, unsigned int __user *tlv) 6020 { 6021 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6022 struct ca0132_spec *spec = codec->spec; 6023 hda_nid_t nid = get_amp_nid(kcontrol); 6024 int ch = get_amp_channels(kcontrol); 6025 int dir = get_amp_direction(kcontrol); 6026 unsigned long pval; 6027 int err; 6028 6029 switch (nid) { 6030 case VNID_SPK: 6031 /* follow shared_out tlv */ 6032 nid = spec->shared_out_nid; 6033 mutex_lock(&codec->control_mutex); 6034 pval = kcontrol->private_value; 6035 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6036 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6037 kcontrol->private_value = pval; 6038 mutex_unlock(&codec->control_mutex); 6039 break; 6040 case VNID_MIC: 6041 /* follow shared_mic tlv */ 6042 nid = spec->shared_mic_nid; 6043 mutex_lock(&codec->control_mutex); 6044 pval = kcontrol->private_value; 6045 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6046 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6047 kcontrol->private_value = pval; 6048 mutex_unlock(&codec->control_mutex); 6049 break; 6050 default: 6051 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6052 } 6053 return err; 6054 } 6055 6056 /* Add volume slider control for effect level */ 6057 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid, 6058 const char *pfx, int dir) 6059 { 6060 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6061 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6062 struct snd_kcontrol_new knew = 6063 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 6064 6065 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]); 6066 6067 knew.tlv.c = NULL; 6068 6069 switch (nid) { 6070 case XBASS_XOVER: 6071 knew.info = ca0132_alt_xbass_xover_slider_info; 6072 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 6073 knew.put = ca0132_alt_xbass_xover_slider_put; 6074 break; 6075 default: 6076 knew.info = ca0132_alt_effect_slider_info; 6077 knew.get = ca0132_alt_slider_ctl_get; 6078 knew.put = ca0132_alt_effect_slider_put; 6079 knew.private_value = 6080 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 6081 break; 6082 } 6083 6084 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6085 } 6086 6087 /* 6088 * Added FX: prefix for the alternative codecs, because otherwise the surround 6089 * effect would conflict with the Surround sound volume control. Also seems more 6090 * clear as to what the switches do. Left alone for others. 6091 */ 6092 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid, 6093 const char *pfx, int dir) 6094 { 6095 struct ca0132_spec *spec = codec->spec; 6096 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6097 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6098 struct snd_kcontrol_new knew = 6099 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type); 6100 /* If using alt_controls, add FX: prefix. But, don't add FX: 6101 * prefix to OutFX or InFX enable controls. 6102 */ 6103 if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID)) 6104 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]); 6105 else 6106 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]); 6107 6108 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6109 } 6110 6111 static int add_voicefx(struct hda_codec *codec) 6112 { 6113 struct snd_kcontrol_new knew = 6114 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name, 6115 VOICEFX, 1, 0, HDA_INPUT); 6116 knew.info = ca0132_voicefx_info; 6117 knew.get = ca0132_voicefx_get; 6118 knew.put = ca0132_voicefx_put; 6119 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec)); 6120 } 6121 6122 /* Create the EQ Preset control */ 6123 static int add_ca0132_alt_eq_presets(struct hda_codec *codec) 6124 { 6125 struct snd_kcontrol_new knew = 6126 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name, 6127 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT); 6128 knew.info = ca0132_alt_eq_preset_info; 6129 knew.get = ca0132_alt_eq_preset_get; 6130 knew.put = ca0132_alt_eq_preset_put; 6131 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM, 6132 snd_ctl_new1(&knew, codec)); 6133 } 6134 6135 /* 6136 * Add enumerated control for the three different settings of the smart volume 6137 * output effect. Normal just uses the slider value, and loud and night are 6138 * their own things that ignore that value. 6139 */ 6140 static int ca0132_alt_add_svm_enum(struct hda_codec *codec) 6141 { 6142 struct snd_kcontrol_new knew = 6143 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting", 6144 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT); 6145 knew.info = ca0132_alt_svm_setting_info; 6146 knew.get = ca0132_alt_svm_setting_get; 6147 knew.put = ca0132_alt_svm_setting_put; 6148 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM, 6149 snd_ctl_new1(&knew, codec)); 6150 6151 } 6152 6153 /* 6154 * Create an Output Select enumerated control for codecs with surround 6155 * out capabilities. 6156 */ 6157 static int ca0132_alt_add_output_enum(struct hda_codec *codec) 6158 { 6159 struct snd_kcontrol_new knew = 6160 HDA_CODEC_MUTE_MONO("Output Select", 6161 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT); 6162 knew.info = ca0132_alt_output_select_get_info; 6163 knew.get = ca0132_alt_output_select_get; 6164 knew.put = ca0132_alt_output_select_put; 6165 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM, 6166 snd_ctl_new1(&knew, codec)); 6167 } 6168 6169 /* 6170 * Create an Input Source enumerated control for the alternate ca0132 codecs 6171 * because the front microphone has no auto-detect, and Line-in has to be set 6172 * somehow. 6173 */ 6174 static int ca0132_alt_add_input_enum(struct hda_codec *codec) 6175 { 6176 struct snd_kcontrol_new knew = 6177 HDA_CODEC_MUTE_MONO("Input Source", 6178 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT); 6179 knew.info = ca0132_alt_input_source_info; 6180 knew.get = ca0132_alt_input_source_get; 6181 knew.put = ca0132_alt_input_source_put; 6182 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM, 6183 snd_ctl_new1(&knew, codec)); 6184 } 6185 6186 /* 6187 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds 6188 * more control than the original mic boost, which is either full 30dB or off. 6189 */ 6190 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec) 6191 { 6192 struct snd_kcontrol_new knew = 6193 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch", 6194 MIC_BOOST_ENUM, 1, 0, HDA_INPUT); 6195 knew.info = ca0132_alt_mic_boost_info; 6196 knew.get = ca0132_alt_mic_boost_get; 6197 knew.put = ca0132_alt_mic_boost_put; 6198 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM, 6199 snd_ctl_new1(&knew, codec)); 6200 6201 } 6202 6203 /* 6204 * Add headphone gain enumerated control for the AE-5. This switches between 6205 * three modes, low, medium, and high. When non-headphone outputs are selected, 6206 * it is automatically set to high. This is the same behavior as Windows. 6207 */ 6208 static int ae5_add_headphone_gain_enum(struct hda_codec *codec) 6209 { 6210 struct snd_kcontrol_new knew = 6211 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain", 6212 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT); 6213 knew.info = ae5_headphone_gain_info; 6214 knew.get = ae5_headphone_gain_get; 6215 knew.put = ae5_headphone_gain_put; 6216 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM, 6217 snd_ctl_new1(&knew, codec)); 6218 } 6219 6220 /* 6221 * Add sound filter enumerated control for the AE-5. This adds three different 6222 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've 6223 * read into it, it changes the DAC's interpolation filter. 6224 */ 6225 static int ae5_add_sound_filter_enum(struct hda_codec *codec) 6226 { 6227 struct snd_kcontrol_new knew = 6228 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter", 6229 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT); 6230 knew.info = ae5_sound_filter_info; 6231 knew.get = ae5_sound_filter_get; 6232 knew.put = ae5_sound_filter_put; 6233 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM, 6234 snd_ctl_new1(&knew, codec)); 6235 } 6236 6237 static int zxr_add_headphone_gain_switch(struct hda_codec *codec) 6238 { 6239 struct snd_kcontrol_new knew = 6240 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain", 6241 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT); 6242 6243 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN, 6244 snd_ctl_new1(&knew, codec)); 6245 } 6246 6247 /* 6248 * Need to create slave controls for the alternate codecs that have surround 6249 * capabilities. 6250 */ 6251 static const char * const ca0132_alt_slave_pfxs[] = { 6252 "Front", "Surround", "Center", "LFE", NULL, 6253 }; 6254 6255 /* 6256 * Also need special channel map, because the default one is incorrect. 6257 * I think this has to do with the pin for rear surround being 0x11, 6258 * and the center/lfe being 0x10. Usually the pin order is the opposite. 6259 */ 6260 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = { 6261 { .channels = 2, 6262 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } }, 6263 { .channels = 4, 6264 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6265 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6266 { .channels = 6, 6267 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6268 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE, 6269 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6270 { } 6271 }; 6272 6273 /* Add the correct chmap for streams with 6 channels. */ 6274 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec) 6275 { 6276 int err = 0; 6277 struct hda_pcm *pcm; 6278 6279 list_for_each_entry(pcm, &codec->pcm_list_head, list) { 6280 struct hda_pcm_stream *hinfo = 6281 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 6282 struct snd_pcm_chmap *chmap; 6283 const struct snd_pcm_chmap_elem *elem; 6284 6285 elem = ca0132_alt_chmaps; 6286 if (hinfo->channels_max == 6) { 6287 err = snd_pcm_add_chmap_ctls(pcm->pcm, 6288 SNDRV_PCM_STREAM_PLAYBACK, 6289 elem, hinfo->channels_max, 0, &chmap); 6290 if (err < 0) 6291 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!"); 6292 } 6293 } 6294 } 6295 6296 /* 6297 * When changing Node IDs for Mixer Controls below, make sure to update 6298 * Node IDs in ca0132_config() as well. 6299 */ 6300 static const struct snd_kcontrol_new ca0132_mixer[] = { 6301 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT), 6302 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT), 6303 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 6304 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6305 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT), 6306 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT), 6307 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6308 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6309 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch", 6310 0x12, 1, HDA_INPUT), 6311 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch", 6312 VNID_HP_SEL, 1, HDA_OUTPUT), 6313 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch", 6314 VNID_AMIC1_SEL, 1, HDA_INPUT), 6315 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6316 VNID_HP_ASEL, 1, HDA_OUTPUT), 6317 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch", 6318 VNID_AMIC1_ASEL, 1, HDA_INPUT), 6319 { } /* end */ 6320 }; 6321 6322 /* 6323 * Desktop specific control mixer. Removes auto-detect for mic, and adds 6324 * surround controls. Also sets both the Front Playback and Capture Volume 6325 * controls to alt so they set the DSP's decibel level. 6326 */ 6327 static const struct snd_kcontrol_new desktop_mixer[] = { 6328 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 6329 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 6330 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 6331 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 6332 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 6333 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 6334 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 6335 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 6336 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT), 6337 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6338 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6339 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6340 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6341 VNID_HP_ASEL, 1, HDA_OUTPUT), 6342 { } /* end */ 6343 }; 6344 6345 /* 6346 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture 6347 * because it doesn't set decibel levels for the DSP for capture. 6348 */ 6349 static const struct snd_kcontrol_new r3di_mixer[] = { 6350 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 6351 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 6352 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 6353 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 6354 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 6355 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 6356 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 6357 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 6358 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 6359 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6360 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6361 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6362 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6363 VNID_HP_ASEL, 1, HDA_OUTPUT), 6364 { } /* end */ 6365 }; 6366 6367 static int ca0132_build_controls(struct hda_codec *codec) 6368 { 6369 struct ca0132_spec *spec = codec->spec; 6370 int i, num_fx, num_sliders; 6371 int err = 0; 6372 6373 /* Add Mixer controls */ 6374 for (i = 0; i < spec->num_mixers; i++) { 6375 err = snd_hda_add_new_ctls(codec, spec->mixers[i]); 6376 if (err < 0) 6377 return err; 6378 } 6379 /* Setup vmaster with surround slaves for desktop ca0132 devices */ 6380 if (ca0132_use_alt_functions(spec)) { 6381 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT, 6382 spec->tlv); 6383 snd_hda_add_vmaster(codec, "Master Playback Volume", 6384 spec->tlv, ca0132_alt_slave_pfxs, 6385 "Playback Volume"); 6386 err = __snd_hda_add_vmaster(codec, "Master Playback Switch", 6387 NULL, ca0132_alt_slave_pfxs, 6388 "Playback Switch", 6389 true, &spec->vmaster_mute.sw_kctl); 6390 if (err < 0) 6391 return err; 6392 } 6393 6394 /* Add in and out effects controls. 6395 * VoiceFX, PE and CrystalVoice are added separately. 6396 */ 6397 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 6398 for (i = 0; i < num_fx; i++) { 6399 /* Desktop cards break if Echo Cancellation is used. */ 6400 if (ca0132_use_pci_mmio(spec)) { 6401 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID + 6402 OUT_EFFECTS_COUNT)) 6403 continue; 6404 } 6405 6406 err = add_fx_switch(codec, ca0132_effects[i].nid, 6407 ca0132_effects[i].name, 6408 ca0132_effects[i].direct); 6409 if (err < 0) 6410 return err; 6411 } 6412 /* 6413 * If codec has use_alt_controls set to true, add effect level sliders, 6414 * EQ presets, and Smart Volume presets. Also, change names to add FX 6415 * prefix, and change PlayEnhancement and CrystalVoice to match. 6416 */ 6417 if (ca0132_use_alt_controls(spec)) { 6418 err = ca0132_alt_add_svm_enum(codec); 6419 if (err < 0) 6420 return err; 6421 6422 err = add_ca0132_alt_eq_presets(codec); 6423 if (err < 0) 6424 return err; 6425 6426 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 6427 "Enable OutFX", 0); 6428 if (err < 0) 6429 return err; 6430 6431 err = add_fx_switch(codec, CRYSTAL_VOICE, 6432 "Enable InFX", 1); 6433 if (err < 0) 6434 return err; 6435 6436 num_sliders = OUT_EFFECTS_COUNT - 1; 6437 for (i = 0; i < num_sliders; i++) { 6438 err = ca0132_alt_add_effect_slider(codec, 6439 ca0132_effects[i].nid, 6440 ca0132_effects[i].name, 6441 ca0132_effects[i].direct); 6442 if (err < 0) 6443 return err; 6444 } 6445 6446 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER, 6447 "X-Bass Crossover", EFX_DIR_OUT); 6448 6449 if (err < 0) 6450 return err; 6451 } else { 6452 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 6453 "PlayEnhancement", 0); 6454 if (err < 0) 6455 return err; 6456 6457 err = add_fx_switch(codec, CRYSTAL_VOICE, 6458 "CrystalVoice", 1); 6459 if (err < 0) 6460 return err; 6461 } 6462 err = add_voicefx(codec); 6463 if (err < 0) 6464 return err; 6465 6466 /* 6467 * If the codec uses alt_functions, you need the enumerated controls 6468 * to select the new outputs and inputs, plus add the new mic boost 6469 * setting control. 6470 */ 6471 if (ca0132_use_alt_functions(spec)) { 6472 err = ca0132_alt_add_output_enum(codec); 6473 if (err < 0) 6474 return err; 6475 err = ca0132_alt_add_mic_boost_enum(codec); 6476 if (err < 0) 6477 return err; 6478 /* 6479 * ZxR only has microphone input, there is no front panel 6480 * header on the card, and aux-in is handled by the DBPro board. 6481 */ 6482 if (ca0132_quirk(spec) != QUIRK_ZXR) { 6483 err = ca0132_alt_add_input_enum(codec); 6484 if (err < 0) 6485 return err; 6486 } 6487 } 6488 6489 if (ca0132_quirk(spec) == QUIRK_AE5) { 6490 err = ae5_add_headphone_gain_enum(codec); 6491 if (err < 0) 6492 return err; 6493 err = ae5_add_sound_filter_enum(codec); 6494 if (err < 0) 6495 return err; 6496 } 6497 6498 if (ca0132_quirk(spec) == QUIRK_ZXR) { 6499 err = zxr_add_headphone_gain_switch(codec); 6500 if (err < 0) 6501 return err; 6502 } 6503 #ifdef ENABLE_TUNING_CONTROLS 6504 add_tuning_ctls(codec); 6505 #endif 6506 6507 err = snd_hda_jack_add_kctls(codec, &spec->autocfg); 6508 if (err < 0) 6509 return err; 6510 6511 if (spec->dig_out) { 6512 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 6513 spec->dig_out); 6514 if (err < 0) 6515 return err; 6516 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout); 6517 if (err < 0) 6518 return err; 6519 /* spec->multiout.share_spdif = 1; */ 6520 } 6521 6522 if (spec->dig_in) { 6523 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 6524 if (err < 0) 6525 return err; 6526 } 6527 6528 if (ca0132_use_alt_functions(spec)) 6529 ca0132_alt_add_chmap_ctls(codec); 6530 6531 return 0; 6532 } 6533 6534 static int dbpro_build_controls(struct hda_codec *codec) 6535 { 6536 struct ca0132_spec *spec = codec->spec; 6537 int err = 0; 6538 6539 if (spec->dig_out) { 6540 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 6541 spec->dig_out); 6542 if (err < 0) 6543 return err; 6544 } 6545 6546 if (spec->dig_in) { 6547 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 6548 if (err < 0) 6549 return err; 6550 } 6551 6552 return 0; 6553 } 6554 6555 /* 6556 * PCM 6557 */ 6558 static const struct hda_pcm_stream ca0132_pcm_analog_playback = { 6559 .substreams = 1, 6560 .channels_min = 2, 6561 .channels_max = 6, 6562 .ops = { 6563 .prepare = ca0132_playback_pcm_prepare, 6564 .cleanup = ca0132_playback_pcm_cleanup, 6565 .get_delay = ca0132_playback_pcm_delay, 6566 }, 6567 }; 6568 6569 static const struct hda_pcm_stream ca0132_pcm_analog_capture = { 6570 .substreams = 1, 6571 .channels_min = 2, 6572 .channels_max = 2, 6573 .ops = { 6574 .prepare = ca0132_capture_pcm_prepare, 6575 .cleanup = ca0132_capture_pcm_cleanup, 6576 .get_delay = ca0132_capture_pcm_delay, 6577 }, 6578 }; 6579 6580 static const struct hda_pcm_stream ca0132_pcm_digital_playback = { 6581 .substreams = 1, 6582 .channels_min = 2, 6583 .channels_max = 2, 6584 .ops = { 6585 .open = ca0132_dig_playback_pcm_open, 6586 .close = ca0132_dig_playback_pcm_close, 6587 .prepare = ca0132_dig_playback_pcm_prepare, 6588 .cleanup = ca0132_dig_playback_pcm_cleanup 6589 }, 6590 }; 6591 6592 static const struct hda_pcm_stream ca0132_pcm_digital_capture = { 6593 .substreams = 1, 6594 .channels_min = 2, 6595 .channels_max = 2, 6596 }; 6597 6598 static int ca0132_build_pcms(struct hda_codec *codec) 6599 { 6600 struct ca0132_spec *spec = codec->spec; 6601 struct hda_pcm *info; 6602 6603 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog"); 6604 if (!info) 6605 return -ENOMEM; 6606 if (ca0132_use_alt_functions(spec)) { 6607 info->own_chmap = true; 6608 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap 6609 = ca0132_alt_chmaps; 6610 } 6611 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback; 6612 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0]; 6613 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max = 6614 spec->multiout.max_channels; 6615 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 6616 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 6617 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 6618 6619 /* With the DSP enabled, desktops don't use this ADC. */ 6620 if (!ca0132_use_alt_functions(spec)) { 6621 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2"); 6622 if (!info) 6623 return -ENOMEM; 6624 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 6625 ca0132_pcm_analog_capture; 6626 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 6627 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1]; 6628 } 6629 6630 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear"); 6631 if (!info) 6632 return -ENOMEM; 6633 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 6634 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 6635 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2]; 6636 6637 if (!spec->dig_out && !spec->dig_in) 6638 return 0; 6639 6640 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 6641 if (!info) 6642 return -ENOMEM; 6643 info->pcm_type = HDA_PCM_TYPE_SPDIF; 6644 if (spec->dig_out) { 6645 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 6646 ca0132_pcm_digital_playback; 6647 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 6648 } 6649 if (spec->dig_in) { 6650 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 6651 ca0132_pcm_digital_capture; 6652 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 6653 } 6654 6655 return 0; 6656 } 6657 6658 static int dbpro_build_pcms(struct hda_codec *codec) 6659 { 6660 struct ca0132_spec *spec = codec->spec; 6661 struct hda_pcm *info; 6662 6663 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog"); 6664 if (!info) 6665 return -ENOMEM; 6666 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 6667 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 6668 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 6669 6670 6671 if (!spec->dig_out && !spec->dig_in) 6672 return 0; 6673 6674 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 6675 if (!info) 6676 return -ENOMEM; 6677 info->pcm_type = HDA_PCM_TYPE_SPDIF; 6678 if (spec->dig_out) { 6679 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 6680 ca0132_pcm_digital_playback; 6681 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 6682 } 6683 if (spec->dig_in) { 6684 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 6685 ca0132_pcm_digital_capture; 6686 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 6687 } 6688 6689 return 0; 6690 } 6691 6692 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac) 6693 { 6694 if (pin) { 6695 snd_hda_set_pin_ctl(codec, pin, PIN_HP); 6696 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 6697 snd_hda_codec_write(codec, pin, 0, 6698 AC_VERB_SET_AMP_GAIN_MUTE, 6699 AMP_OUT_UNMUTE); 6700 } 6701 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP)) 6702 snd_hda_codec_write(codec, dac, 0, 6703 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO); 6704 } 6705 6706 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc) 6707 { 6708 if (pin) { 6709 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80); 6710 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP) 6711 snd_hda_codec_write(codec, pin, 0, 6712 AC_VERB_SET_AMP_GAIN_MUTE, 6713 AMP_IN_UNMUTE(0)); 6714 } 6715 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) { 6716 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE, 6717 AMP_IN_UNMUTE(0)); 6718 6719 /* init to 0 dB and unmute. */ 6720 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 6721 HDA_AMP_VOLMASK, 0x5a); 6722 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 6723 HDA_AMP_MUTE, 0); 6724 } 6725 } 6726 6727 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir) 6728 { 6729 unsigned int caps; 6730 6731 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ? 6732 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP); 6733 snd_hda_override_amp_caps(codec, nid, dir, caps); 6734 } 6735 6736 /* 6737 * Switch between Digital built-in mic and analog mic. 6738 */ 6739 static void ca0132_set_dmic(struct hda_codec *codec, int enable) 6740 { 6741 struct ca0132_spec *spec = codec->spec; 6742 unsigned int tmp; 6743 u8 val; 6744 unsigned int oldval; 6745 6746 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable); 6747 6748 oldval = stop_mic1(codec); 6749 ca0132_set_vipsource(codec, 0); 6750 if (enable) { 6751 /* set DMic input as 2-ch */ 6752 tmp = FLOAT_TWO; 6753 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 6754 6755 val = spec->dmic_ctl; 6756 val |= 0x80; 6757 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6758 VENDOR_CHIPIO_DMIC_CTL_SET, val); 6759 6760 if (!(spec->dmic_ctl & 0x20)) 6761 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1); 6762 } else { 6763 /* set AMic input as mono */ 6764 tmp = FLOAT_ONE; 6765 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 6766 6767 val = spec->dmic_ctl; 6768 /* clear bit7 and bit5 to disable dmic */ 6769 val &= 0x5f; 6770 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6771 VENDOR_CHIPIO_DMIC_CTL_SET, val); 6772 6773 if (!(spec->dmic_ctl & 0x20)) 6774 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0); 6775 } 6776 ca0132_set_vipsource(codec, 1); 6777 resume_mic1(codec, oldval); 6778 } 6779 6780 /* 6781 * Initialization for Digital Mic. 6782 */ 6783 static void ca0132_init_dmic(struct hda_codec *codec) 6784 { 6785 struct ca0132_spec *spec = codec->spec; 6786 u8 val; 6787 6788 /* Setup Digital Mic here, but don't enable. 6789 * Enable based on jack detect. 6790 */ 6791 6792 /* MCLK uses MPIO1, set to enable. 6793 * Bit 2-0: MPIO select 6794 * Bit 3: set to disable 6795 * Bit 7-4: reserved 6796 */ 6797 val = 0x01; 6798 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6799 VENDOR_CHIPIO_DMIC_MCLK_SET, val); 6800 6801 /* Data1 uses MPIO3. Data2 not use 6802 * Bit 2-0: Data1 MPIO select 6803 * Bit 3: set disable Data1 6804 * Bit 6-4: Data2 MPIO select 6805 * Bit 7: set disable Data2 6806 */ 6807 val = 0x83; 6808 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6809 VENDOR_CHIPIO_DMIC_PIN_SET, val); 6810 6811 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first. 6812 * Bit 3-0: Channel mask 6813 * Bit 4: set for 48KHz, clear for 32KHz 6814 * Bit 5: mode 6815 * Bit 6: set to select Data2, clear for Data1 6816 * Bit 7: set to enable DMic, clear for AMic 6817 */ 6818 if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4) 6819 val = 0x33; 6820 else 6821 val = 0x23; 6822 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */ 6823 spec->dmic_ctl = val; 6824 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6825 VENDOR_CHIPIO_DMIC_CTL_SET, val); 6826 } 6827 6828 /* 6829 * Initialization for Analog Mic 2 6830 */ 6831 static void ca0132_init_analog_mic2(struct hda_codec *codec) 6832 { 6833 struct ca0132_spec *spec = codec->spec; 6834 6835 mutex_lock(&spec->chipio_mutex); 6836 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6837 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); 6838 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6839 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 6840 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6841 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 6842 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6843 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D); 6844 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6845 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 6846 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6847 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 6848 mutex_unlock(&spec->chipio_mutex); 6849 } 6850 6851 static void ca0132_refresh_widget_caps(struct hda_codec *codec) 6852 { 6853 struct ca0132_spec *spec = codec->spec; 6854 int i; 6855 6856 codec_dbg(codec, "ca0132_refresh_widget_caps.\n"); 6857 snd_hda_codec_update_widgets(codec); 6858 6859 for (i = 0; i < spec->multiout.num_dacs; i++) 6860 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT); 6861 6862 for (i = 0; i < spec->num_outputs; i++) 6863 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT); 6864 6865 for (i = 0; i < spec->num_inputs; i++) { 6866 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT); 6867 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT); 6868 } 6869 } 6870 6871 /* 6872 * Creates a dummy stream to bind the output to. This seems to have to be done 6873 * after changing the main outputs source and destination streams. 6874 */ 6875 static void ca0132_alt_create_dummy_stream(struct hda_codec *codec) 6876 { 6877 struct ca0132_spec *spec = codec->spec; 6878 unsigned int stream_format; 6879 6880 stream_format = snd_hdac_calc_stream_format(48000, 2, 6881 SNDRV_PCM_FORMAT_S32_LE, 32, 0); 6882 6883 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id, 6884 0, stream_format); 6885 6886 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 6887 } 6888 6889 /* 6890 * Initialize mic for non-chromebook ca0132 implementations. 6891 */ 6892 static void ca0132_alt_init_analog_mics(struct hda_codec *codec) 6893 { 6894 struct ca0132_spec *spec = codec->spec; 6895 unsigned int tmp; 6896 6897 /* Mic 1 Setup */ 6898 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 6899 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 6900 if (ca0132_quirk(spec) == QUIRK_R3DI) { 6901 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 6902 tmp = FLOAT_ONE; 6903 } else 6904 tmp = FLOAT_THREE; 6905 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 6906 6907 /* Mic 2 setup (not present on desktop cards) */ 6908 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000); 6909 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000); 6910 if (ca0132_quirk(spec) == QUIRK_R3DI) 6911 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 6912 tmp = FLOAT_ZERO; 6913 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 6914 } 6915 6916 /* 6917 * Sets the source of stream 0x14 to connpointID 0x48, and the destination 6918 * connpointID to 0x91. If this isn't done, the destination is 0x71, and 6919 * you get no sound. I'm guessing this has to do with the Sound Blaster Z 6920 * having an updated DAC, which changes the destination to that DAC. 6921 */ 6922 static void sbz_connect_streams(struct hda_codec *codec) 6923 { 6924 struct ca0132_spec *spec = codec->spec; 6925 6926 mutex_lock(&spec->chipio_mutex); 6927 6928 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n"); 6929 6930 chipio_set_stream_channels(codec, 0x0C, 6); 6931 chipio_set_stream_control(codec, 0x0C, 1); 6932 6933 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */ 6934 chipio_write_no_mutex(codec, 0x18a020, 0x00000043); 6935 6936 /* Setup stream 0x14 with it's source and destination points */ 6937 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91); 6938 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000); 6939 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000); 6940 chipio_set_stream_channels(codec, 0x14, 2); 6941 chipio_set_stream_control(codec, 0x14, 1); 6942 6943 codec_dbg(codec, "Connect Streams exited, mutex released.\n"); 6944 6945 mutex_unlock(&spec->chipio_mutex); 6946 } 6947 6948 /* 6949 * Write data through ChipIO to setup proper stream destinations. 6950 * Not sure how it exactly works, but it seems to direct data 6951 * to different destinations. Example is f8 to c0, e0 to c0. 6952 * All I know is, if you don't set these, you get no sound. 6953 */ 6954 static void sbz_chipio_startup_data(struct hda_codec *codec) 6955 { 6956 struct ca0132_spec *spec = codec->spec; 6957 6958 mutex_lock(&spec->chipio_mutex); 6959 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n"); 6960 6961 /* These control audio output */ 6962 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0); 6963 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1); 6964 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6); 6965 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7); 6966 /* Signal to update I think */ 6967 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 6968 6969 chipio_set_stream_channels(codec, 0x0C, 6); 6970 chipio_set_stream_control(codec, 0x0C, 1); 6971 /* No clue what these control */ 6972 if (ca0132_quirk(spec) == QUIRK_SBZ) { 6973 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0); 6974 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1); 6975 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2); 6976 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3); 6977 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4); 6978 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5); 6979 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6); 6980 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7); 6981 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8); 6982 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9); 6983 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca); 6984 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb); 6985 } else if (ca0132_quirk(spec) == QUIRK_ZXR) { 6986 chipio_write_no_mutex(codec, 0x190038, 0x000140c2); 6987 chipio_write_no_mutex(codec, 0x19003c, 0x000141c3); 6988 chipio_write_no_mutex(codec, 0x190040, 0x000150c4); 6989 chipio_write_no_mutex(codec, 0x190044, 0x000151c5); 6990 chipio_write_no_mutex(codec, 0x190050, 0x000142c8); 6991 chipio_write_no_mutex(codec, 0x190054, 0x000143c9); 6992 chipio_write_no_mutex(codec, 0x190058, 0x000152ca); 6993 chipio_write_no_mutex(codec, 0x19005c, 0x000153cb); 6994 } 6995 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 6996 6997 codec_dbg(codec, "Startup Data exited, mutex released.\n"); 6998 mutex_unlock(&spec->chipio_mutex); 6999 } 7000 7001 /* 7002 * Custom DSP SCP commands where the src value is 0x00 instead of 0x20. This is 7003 * done after the DSP is loaded. 7004 */ 7005 static void ca0132_alt_dsp_scp_startup(struct hda_codec *codec) 7006 { 7007 struct ca0132_spec *spec = codec->spec; 7008 unsigned int tmp, i; 7009 7010 /* 7011 * Gotta run these twice, or else mic works inconsistently. Not clear 7012 * why this is, but multiple tests have confirmed it. 7013 */ 7014 for (i = 0; i < 2; i++) { 7015 switch (ca0132_quirk(spec)) { 7016 case QUIRK_SBZ: 7017 case QUIRK_AE5: 7018 tmp = 0x00000003; 7019 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7020 tmp = 0x00000000; 7021 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp); 7022 tmp = 0x00000001; 7023 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp); 7024 tmp = 0x00000004; 7025 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7026 tmp = 0x00000005; 7027 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7028 tmp = 0x00000000; 7029 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7030 break; 7031 case QUIRK_R3D: 7032 case QUIRK_R3DI: 7033 tmp = 0x00000000; 7034 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp); 7035 tmp = 0x00000001; 7036 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp); 7037 tmp = 0x00000004; 7038 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7039 tmp = 0x00000005; 7040 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7041 tmp = 0x00000000; 7042 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7043 break; 7044 default: 7045 break; 7046 } 7047 msleep(100); 7048 } 7049 } 7050 7051 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec) 7052 { 7053 struct ca0132_spec *spec = codec->spec; 7054 unsigned int tmp; 7055 7056 chipio_set_stream_control(codec, 0x03, 0); 7057 chipio_set_stream_control(codec, 0x04, 0); 7058 7059 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7060 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7061 7062 tmp = FLOAT_THREE; 7063 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7064 7065 chipio_set_stream_control(codec, 0x03, 1); 7066 chipio_set_stream_control(codec, 0x04, 1); 7067 7068 switch (ca0132_quirk(spec)) { 7069 case QUIRK_SBZ: 7070 chipio_write(codec, 0x18b098, 0x0000000c); 7071 chipio_write(codec, 0x18b09C, 0x0000000c); 7072 break; 7073 case QUIRK_AE5: 7074 chipio_write(codec, 0x18b098, 0x0000000c); 7075 chipio_write(codec, 0x18b09c, 0x0000004c); 7076 break; 7077 default: 7078 break; 7079 } 7080 } 7081 7082 static void ae5_post_dsp_register_set(struct hda_codec *codec) 7083 { 7084 struct ca0132_spec *spec = codec->spec; 7085 7086 chipio_8051_write_direct(codec, 0x93, 0x10); 7087 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7088 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44); 7089 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7090 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2); 7091 7092 writeb(0xff, spec->mem_base + 0x304); 7093 writeb(0xff, spec->mem_base + 0x304); 7094 writeb(0xff, spec->mem_base + 0x304); 7095 writeb(0xff, spec->mem_base + 0x304); 7096 writeb(0x00, spec->mem_base + 0x100); 7097 writeb(0xff, spec->mem_base + 0x304); 7098 writeb(0x00, spec->mem_base + 0x100); 7099 writeb(0xff, spec->mem_base + 0x304); 7100 writeb(0x00, spec->mem_base + 0x100); 7101 writeb(0xff, spec->mem_base + 0x304); 7102 writeb(0x00, spec->mem_base + 0x100); 7103 writeb(0xff, spec->mem_base + 0x304); 7104 7105 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f); 7106 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 7107 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7108 } 7109 7110 static void ae5_post_dsp_param_setup(struct hda_codec *codec) 7111 { 7112 /* 7113 * Param3 in the 8051's memory is represented by the ascii string 'mch' 7114 * which seems to be 'multichannel'. This is also mentioned in the 7115 * AE-5's registry values in Windows. 7116 */ 7117 chipio_set_control_param(codec, 3, 0); 7118 /* 7119 * I believe ASI is 'audio serial interface' and that it's used to 7120 * change colors on the external LED strip connected to the AE-5. 7121 */ 7122 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); 7123 7124 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); 7125 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 7126 7127 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7128 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92); 7129 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7130 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa); 7131 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7132 VENDOR_CHIPIO_8051_DATA_WRITE, 0x22); 7133 } 7134 7135 static void ae5_post_dsp_pll_setup(struct hda_codec *codec) 7136 { 7137 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7138 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41); 7139 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7140 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8); 7141 7142 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7143 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x45); 7144 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7145 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcc); 7146 7147 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7148 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x40); 7149 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7150 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcb); 7151 7152 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7153 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43); 7154 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7155 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7); 7156 7157 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7158 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x51); 7159 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7160 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x8d); 7161 } 7162 7163 static void ae5_post_dsp_stream_setup(struct hda_codec *codec) 7164 { 7165 struct ca0132_spec *spec = codec->spec; 7166 7167 mutex_lock(&spec->chipio_mutex); 7168 7169 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); 7170 7171 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); 7172 7173 chipio_set_stream_channels(codec, 0x0C, 6); 7174 chipio_set_stream_control(codec, 0x0C, 1); 7175 7176 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0); 7177 7178 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0); 7179 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 7180 chipio_set_stream_channels(codec, 0x18, 6); 7181 chipio_set_stream_control(codec, 0x18, 1); 7182 7183 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); 7184 7185 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7186 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43); 7187 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7188 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7); 7189 7190 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80); 7191 7192 mutex_unlock(&spec->chipio_mutex); 7193 } 7194 7195 static void ae5_post_dsp_startup_data(struct hda_codec *codec) 7196 { 7197 struct ca0132_spec *spec = codec->spec; 7198 7199 mutex_lock(&spec->chipio_mutex); 7200 7201 chipio_write_no_mutex(codec, 0x189000, 0x0001f101); 7202 chipio_write_no_mutex(codec, 0x189004, 0x0001f101); 7203 chipio_write_no_mutex(codec, 0x189024, 0x00014004); 7204 chipio_write_no_mutex(codec, 0x189028, 0x0002000f); 7205 7206 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 7207 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 7208 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12); 7209 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00); 7210 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48); 7211 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 7212 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7213 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 7214 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 7215 ca0113_mmio_gpio_set(codec, 0, true); 7216 ca0113_mmio_gpio_set(codec, 1, true); 7217 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80); 7218 7219 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012); 7220 7221 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 7222 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 7223 7224 mutex_unlock(&spec->chipio_mutex); 7225 } 7226 7227 /* 7228 * Setup default parameters for DSP 7229 */ 7230 static void ca0132_setup_defaults(struct hda_codec *codec) 7231 { 7232 struct ca0132_spec *spec = codec->spec; 7233 unsigned int tmp; 7234 int num_fx; 7235 int idx, i; 7236 7237 if (spec->dsp_state != DSP_DOWNLOADED) 7238 return; 7239 7240 /* out, in effects + voicefx */ 7241 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 7242 for (idx = 0; idx < num_fx; idx++) { 7243 for (i = 0; i <= ca0132_effects[idx].params; i++) { 7244 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 7245 ca0132_effects[idx].reqs[i], 7246 ca0132_effects[idx].def_vals[i]); 7247 } 7248 } 7249 7250 /*remove DSP headroom*/ 7251 tmp = FLOAT_ZERO; 7252 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 7253 7254 /*set speaker EQ bypass attenuation*/ 7255 dspio_set_uint_param(codec, 0x8f, 0x01, tmp); 7256 7257 /* set AMic1 and AMic2 as mono mic */ 7258 tmp = FLOAT_ONE; 7259 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7260 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 7261 7262 /* set AMic1 as CrystalVoice input */ 7263 tmp = FLOAT_ONE; 7264 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 7265 7266 /* set WUH source */ 7267 tmp = FLOAT_TWO; 7268 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 7269 } 7270 7271 /* 7272 * Setup default parameters for Recon3D/Recon3Di DSP. 7273 */ 7274 7275 static void r3d_setup_defaults(struct hda_codec *codec) 7276 { 7277 struct ca0132_spec *spec = codec->spec; 7278 unsigned int tmp; 7279 int num_fx; 7280 int idx, i; 7281 7282 if (spec->dsp_state != DSP_DOWNLOADED) 7283 return; 7284 7285 ca0132_alt_dsp_scp_startup(codec); 7286 ca0132_alt_init_analog_mics(codec); 7287 7288 /*remove DSP headroom*/ 7289 tmp = FLOAT_ZERO; 7290 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 7291 7292 /* set WUH source */ 7293 tmp = FLOAT_TWO; 7294 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 7295 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7296 7297 /* Set speaker source? */ 7298 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 7299 7300 if (ca0132_quirk(spec) == QUIRK_R3DI) 7301 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED); 7302 7303 /* Setup effect defaults */ 7304 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 7305 for (idx = 0; idx < num_fx; idx++) { 7306 for (i = 0; i <= ca0132_effects[idx].params; i++) { 7307 dspio_set_uint_param(codec, 7308 ca0132_effects[idx].mid, 7309 ca0132_effects[idx].reqs[i], 7310 ca0132_effects[idx].def_vals[i]); 7311 } 7312 } 7313 } 7314 7315 /* 7316 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on 7317 * than the Chromebook setup. 7318 */ 7319 static void sbz_setup_defaults(struct hda_codec *codec) 7320 { 7321 struct ca0132_spec *spec = codec->spec; 7322 unsigned int tmp; 7323 int num_fx; 7324 int idx, i; 7325 7326 if (spec->dsp_state != DSP_DOWNLOADED) 7327 return; 7328 7329 ca0132_alt_dsp_scp_startup(codec); 7330 ca0132_alt_init_analog_mics(codec); 7331 sbz_connect_streams(codec); 7332 sbz_chipio_startup_data(codec); 7333 7334 chipio_set_stream_control(codec, 0x03, 1); 7335 chipio_set_stream_control(codec, 0x04, 1); 7336 7337 /* 7338 * Sets internal input loopback to off, used to have a switch to 7339 * enable input loopback, but turned out to be way too buggy. 7340 */ 7341 tmp = FLOAT_ONE; 7342 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 7343 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 7344 7345 /*remove DSP headroom*/ 7346 tmp = FLOAT_ZERO; 7347 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 7348 7349 /* set WUH source */ 7350 tmp = FLOAT_TWO; 7351 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 7352 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7353 7354 /* Set speaker source? */ 7355 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 7356 7357 ca0132_alt_dsp_initial_mic_setup(codec); 7358 7359 /* out, in effects + voicefx */ 7360 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 7361 for (idx = 0; idx < num_fx; idx++) { 7362 for (i = 0; i <= ca0132_effects[idx].params; i++) { 7363 dspio_set_uint_param(codec, 7364 ca0132_effects[idx].mid, 7365 ca0132_effects[idx].reqs[i], 7366 ca0132_effects[idx].def_vals[i]); 7367 } 7368 } 7369 7370 ca0132_alt_create_dummy_stream(codec); 7371 } 7372 7373 /* 7374 * Setup default parameters for the Sound BlasterX AE-5 DSP. 7375 */ 7376 static void ae5_setup_defaults(struct hda_codec *codec) 7377 { 7378 struct ca0132_spec *spec = codec->spec; 7379 unsigned int tmp; 7380 int num_fx; 7381 int idx, i; 7382 7383 if (spec->dsp_state != DSP_DOWNLOADED) 7384 return; 7385 7386 ca0132_alt_dsp_scp_startup(codec); 7387 ca0132_alt_init_analog_mics(codec); 7388 chipio_set_stream_control(codec, 0x03, 1); 7389 chipio_set_stream_control(codec, 0x04, 1); 7390 7391 /* New, unknown SCP req's */ 7392 tmp = FLOAT_ZERO; 7393 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 7394 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 7395 dspio_set_uint_param(codec, 0x80, 0x0d, tmp); 7396 dspio_set_uint_param(codec, 0x80, 0x0e, tmp); 7397 7398 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 7399 ca0113_mmio_gpio_set(codec, 0, false); 7400 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 7401 7402 /* Internal loopback off */ 7403 tmp = FLOAT_ONE; 7404 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 7405 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 7406 7407 /*remove DSP headroom*/ 7408 tmp = FLOAT_ZERO; 7409 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 7410 7411 /* set WUH source */ 7412 tmp = FLOAT_TWO; 7413 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 7414 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7415 7416 /* Set speaker source? */ 7417 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 7418 7419 ca0132_alt_dsp_initial_mic_setup(codec); 7420 ae5_post_dsp_register_set(codec); 7421 ae5_post_dsp_param_setup(codec); 7422 ae5_post_dsp_pll_setup(codec); 7423 ae5_post_dsp_stream_setup(codec); 7424 ae5_post_dsp_startup_data(codec); 7425 7426 /* out, in effects + voicefx */ 7427 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 7428 for (idx = 0; idx < num_fx; idx++) { 7429 for (i = 0; i <= ca0132_effects[idx].params; i++) { 7430 dspio_set_uint_param(codec, 7431 ca0132_effects[idx].mid, 7432 ca0132_effects[idx].reqs[i], 7433 ca0132_effects[idx].def_vals[i]); 7434 } 7435 } 7436 7437 ca0132_alt_create_dummy_stream(codec); 7438 } 7439 7440 /* 7441 * Initialization of flags in chip 7442 */ 7443 static void ca0132_init_flags(struct hda_codec *codec) 7444 { 7445 struct ca0132_spec *spec = codec->spec; 7446 7447 if (ca0132_use_alt_functions(spec)) { 7448 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1); 7449 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1); 7450 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1); 7451 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1); 7452 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1); 7453 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 7454 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0); 7455 chipio_set_control_flag(codec, 7456 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 7457 chipio_set_control_flag(codec, 7458 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1); 7459 } else { 7460 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 7461 chipio_set_control_flag(codec, 7462 CONTROL_FLAG_PORT_A_COMMON_MODE, 0); 7463 chipio_set_control_flag(codec, 7464 CONTROL_FLAG_PORT_D_COMMON_MODE, 0); 7465 chipio_set_control_flag(codec, 7466 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0); 7467 chipio_set_control_flag(codec, 7468 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 7469 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1); 7470 } 7471 } 7472 7473 /* 7474 * Initialization of parameters in chip 7475 */ 7476 static void ca0132_init_params(struct hda_codec *codec) 7477 { 7478 struct ca0132_spec *spec = codec->spec; 7479 7480 if (ca0132_use_alt_functions(spec)) { 7481 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7482 chipio_set_conn_rate(codec, 0x0B, SR_48_000); 7483 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0); 7484 chipio_set_control_param(codec, 0, 0); 7485 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 7486 } 7487 7488 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6); 7489 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6); 7490 } 7491 7492 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k) 7493 { 7494 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k); 7495 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k); 7496 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k); 7497 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k); 7498 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k); 7499 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k); 7500 7501 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7502 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7503 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7504 } 7505 7506 static bool ca0132_download_dsp_images(struct hda_codec *codec) 7507 { 7508 bool dsp_loaded = false; 7509 struct ca0132_spec *spec = codec->spec; 7510 const struct dsp_image_seg *dsp_os_image; 7511 const struct firmware *fw_entry = NULL; 7512 /* 7513 * Alternate firmwares for different variants. The Recon3Di apparently 7514 * can use the default firmware, but I'll leave the option in case 7515 * it needs it again. 7516 */ 7517 switch (ca0132_quirk(spec)) { 7518 case QUIRK_SBZ: 7519 case QUIRK_R3D: 7520 case QUIRK_AE5: 7521 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE, 7522 codec->card->dev) != 0) 7523 codec_dbg(codec, "Desktop firmware not found."); 7524 else 7525 codec_dbg(codec, "Desktop firmware selected."); 7526 break; 7527 case QUIRK_R3DI: 7528 if (request_firmware(&fw_entry, R3DI_EFX_FILE, 7529 codec->card->dev) != 0) 7530 codec_dbg(codec, "Recon3Di alt firmware not detected."); 7531 else 7532 codec_dbg(codec, "Recon3Di firmware selected."); 7533 break; 7534 default: 7535 break; 7536 } 7537 /* 7538 * Use default ctefx.bin if no alt firmware is detected, or if none 7539 * exists for your particular codec. 7540 */ 7541 if (!fw_entry) { 7542 codec_dbg(codec, "Default firmware selected."); 7543 if (request_firmware(&fw_entry, EFX_FILE, 7544 codec->card->dev) != 0) 7545 return false; 7546 } 7547 7548 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data); 7549 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) { 7550 codec_err(codec, "ca0132 DSP load image failed\n"); 7551 goto exit_download; 7552 } 7553 7554 dsp_loaded = dspload_wait_loaded(codec); 7555 7556 exit_download: 7557 release_firmware(fw_entry); 7558 7559 return dsp_loaded; 7560 } 7561 7562 static void ca0132_download_dsp(struct hda_codec *codec) 7563 { 7564 struct ca0132_spec *spec = codec->spec; 7565 7566 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP 7567 return; /* NOP */ 7568 #endif 7569 7570 if (spec->dsp_state == DSP_DOWNLOAD_FAILED) 7571 return; /* don't retry failures */ 7572 7573 chipio_enable_clocks(codec); 7574 if (spec->dsp_state != DSP_DOWNLOADED) { 7575 spec->dsp_state = DSP_DOWNLOADING; 7576 7577 if (!ca0132_download_dsp_images(codec)) 7578 spec->dsp_state = DSP_DOWNLOAD_FAILED; 7579 else 7580 spec->dsp_state = DSP_DOWNLOADED; 7581 } 7582 7583 /* For codecs using alt functions, this is already done earlier */ 7584 if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec)) 7585 ca0132_set_dsp_msr(codec, true); 7586 } 7587 7588 static void ca0132_process_dsp_response(struct hda_codec *codec, 7589 struct hda_jack_callback *callback) 7590 { 7591 struct ca0132_spec *spec = codec->spec; 7592 7593 codec_dbg(codec, "ca0132_process_dsp_response\n"); 7594 snd_hda_power_up_pm(codec); 7595 if (spec->wait_scp) { 7596 if (dspio_get_response_data(codec) >= 0) 7597 spec->wait_scp = 0; 7598 } 7599 7600 dspio_clear_response_queue(codec); 7601 snd_hda_power_down_pm(codec); 7602 } 7603 7604 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 7605 { 7606 struct ca0132_spec *spec = codec->spec; 7607 struct hda_jack_tbl *tbl; 7608 7609 /* Delay enabling the HP amp, to let the mic-detection 7610 * state machine run. 7611 */ 7612 tbl = snd_hda_jack_tbl_get(codec, cb->nid); 7613 if (tbl) 7614 tbl->block_report = 1; 7615 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500)); 7616 } 7617 7618 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 7619 { 7620 struct ca0132_spec *spec = codec->spec; 7621 7622 if (ca0132_use_alt_functions(spec)) 7623 ca0132_alt_select_in(codec); 7624 else 7625 ca0132_select_mic(codec); 7626 } 7627 7628 static void ca0132_init_unsol(struct hda_codec *codec) 7629 { 7630 struct ca0132_spec *spec = codec->spec; 7631 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback); 7632 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1, 7633 amic_callback); 7634 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP, 7635 ca0132_process_dsp_response); 7636 /* Front headphone jack detection */ 7637 if (ca0132_use_alt_functions(spec)) 7638 snd_hda_jack_detect_enable_callback(codec, 7639 spec->unsol_tag_front_hp, hp_callback); 7640 } 7641 7642 /* 7643 * Verbs tables. 7644 */ 7645 7646 /* Sends before DSP download. */ 7647 static const struct hda_verb ca0132_base_init_verbs[] = { 7648 /*enable ct extension*/ 7649 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1}, 7650 {} 7651 }; 7652 7653 /* Send at exit. */ 7654 static const struct hda_verb ca0132_base_exit_verbs[] = { 7655 /*set afg to D3*/ 7656 {0x01, AC_VERB_SET_POWER_STATE, 0x03}, 7657 /*disable ct extension*/ 7658 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0}, 7659 {} 7660 }; 7661 7662 /* Other verbs tables. Sends after DSP download. */ 7663 7664 static const struct hda_verb ca0132_init_verbs0[] = { 7665 /* chip init verbs */ 7666 {0x15, 0x70D, 0xF0}, 7667 {0x15, 0x70E, 0xFE}, 7668 {0x15, 0x707, 0x75}, 7669 {0x15, 0x707, 0xD3}, 7670 {0x15, 0x707, 0x09}, 7671 {0x15, 0x707, 0x53}, 7672 {0x15, 0x707, 0xD4}, 7673 {0x15, 0x707, 0xEF}, 7674 {0x15, 0x707, 0x75}, 7675 {0x15, 0x707, 0xD3}, 7676 {0x15, 0x707, 0x09}, 7677 {0x15, 0x707, 0x02}, 7678 {0x15, 0x707, 0x37}, 7679 {0x15, 0x707, 0x78}, 7680 {0x15, 0x53C, 0xCE}, 7681 {0x15, 0x575, 0xC9}, 7682 {0x15, 0x53D, 0xCE}, 7683 {0x15, 0x5B7, 0xC9}, 7684 {0x15, 0x70D, 0xE8}, 7685 {0x15, 0x70E, 0xFE}, 7686 {0x15, 0x707, 0x02}, 7687 {0x15, 0x707, 0x68}, 7688 {0x15, 0x707, 0x62}, 7689 {0x15, 0x53A, 0xCE}, 7690 {0x15, 0x546, 0xC9}, 7691 {0x15, 0x53B, 0xCE}, 7692 {0x15, 0x5E8, 0xC9}, 7693 {} 7694 }; 7695 7696 /* Extra init verbs for desktop cards. */ 7697 static const struct hda_verb ca0132_init_verbs1[] = { 7698 {0x15, 0x70D, 0x20}, 7699 {0x15, 0x70E, 0x19}, 7700 {0x15, 0x707, 0x00}, 7701 {0x15, 0x539, 0xCE}, 7702 {0x15, 0x546, 0xC9}, 7703 {0x15, 0x70D, 0xB7}, 7704 {0x15, 0x70E, 0x09}, 7705 {0x15, 0x707, 0x10}, 7706 {0x15, 0x70D, 0xAF}, 7707 {0x15, 0x70E, 0x09}, 7708 {0x15, 0x707, 0x01}, 7709 {0x15, 0x707, 0x05}, 7710 {0x15, 0x70D, 0x73}, 7711 {0x15, 0x70E, 0x09}, 7712 {0x15, 0x707, 0x14}, 7713 {0x15, 0x6FF, 0xC4}, 7714 {} 7715 }; 7716 7717 static void ca0132_init_chip(struct hda_codec *codec) 7718 { 7719 struct ca0132_spec *spec = codec->spec; 7720 int num_fx; 7721 int i; 7722 unsigned int on; 7723 7724 mutex_init(&spec->chipio_mutex); 7725 7726 spec->cur_out_type = SPEAKER_OUT; 7727 if (!ca0132_use_alt_functions(spec)) 7728 spec->cur_mic_type = DIGITAL_MIC; 7729 else 7730 spec->cur_mic_type = REAR_MIC; 7731 7732 spec->cur_mic_boost = 0; 7733 7734 for (i = 0; i < VNODES_COUNT; i++) { 7735 spec->vnode_lvol[i] = 0x5a; 7736 spec->vnode_rvol[i] = 0x5a; 7737 spec->vnode_lswitch[i] = 0; 7738 spec->vnode_rswitch[i] = 0; 7739 } 7740 7741 /* 7742 * Default states for effects are in ca0132_effects[]. 7743 */ 7744 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 7745 for (i = 0; i < num_fx; i++) { 7746 on = (unsigned int)ca0132_effects[i].reqs[0]; 7747 spec->effects_switch[i] = on ? 1 : 0; 7748 } 7749 /* 7750 * Sets defaults for the effect slider controls, only for alternative 7751 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz. 7752 */ 7753 if (ca0132_use_alt_controls(spec)) { 7754 spec->xbass_xover_freq = 8; 7755 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++) 7756 spec->fx_ctl_val[i] = effect_slider_defaults[i]; 7757 } 7758 7759 spec->voicefx_val = 0; 7760 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1; 7761 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0; 7762 7763 /* 7764 * The ZxR doesn't have a front panel header, and it's line-in is on 7765 * the daughter board. So, there is no input enum control, and we need 7766 * to make sure that spec->in_enum_val is set properly. 7767 */ 7768 if (ca0132_quirk(spec) == QUIRK_ZXR) 7769 spec->in_enum_val = REAR_MIC; 7770 7771 #ifdef ENABLE_TUNING_CONTROLS 7772 ca0132_init_tuning_defaults(codec); 7773 #endif 7774 } 7775 7776 /* 7777 * Recon3Di exit specific commands. 7778 */ 7779 /* prevents popping noise on shutdown */ 7780 static void r3di_gpio_shutdown(struct hda_codec *codec) 7781 { 7782 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00); 7783 } 7784 7785 /* 7786 * Sound Blaster Z exit specific commands. 7787 */ 7788 static void sbz_region2_exit(struct hda_codec *codec) 7789 { 7790 struct ca0132_spec *spec = codec->spec; 7791 unsigned int i; 7792 7793 for (i = 0; i < 4; i++) 7794 writeb(0x0, spec->mem_base + 0x100); 7795 for (i = 0; i < 8; i++) 7796 writeb(0xb3, spec->mem_base + 0x304); 7797 7798 ca0113_mmio_gpio_set(codec, 0, false); 7799 ca0113_mmio_gpio_set(codec, 1, false); 7800 ca0113_mmio_gpio_set(codec, 4, true); 7801 ca0113_mmio_gpio_set(codec, 5, false); 7802 ca0113_mmio_gpio_set(codec, 7, false); 7803 } 7804 7805 static void sbz_set_pin_ctl_default(struct hda_codec *codec) 7806 { 7807 static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13}; 7808 unsigned int i; 7809 7810 snd_hda_codec_write(codec, 0x11, 0, 7811 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40); 7812 7813 for (i = 0; i < ARRAY_SIZE(pins); i++) 7814 snd_hda_codec_write(codec, pins[i], 0, 7815 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00); 7816 } 7817 7818 static void ca0132_clear_unsolicited(struct hda_codec *codec) 7819 { 7820 static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13}; 7821 unsigned int i; 7822 7823 for (i = 0; i < ARRAY_SIZE(pins); i++) { 7824 snd_hda_codec_write(codec, pins[i], 0, 7825 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00); 7826 } 7827 } 7828 7829 /* On shutdown, sends commands in sets of three */ 7830 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir, 7831 int mask, int data) 7832 { 7833 if (dir >= 0) 7834 snd_hda_codec_write(codec, 0x01, 0, 7835 AC_VERB_SET_GPIO_DIRECTION, dir); 7836 if (mask >= 0) 7837 snd_hda_codec_write(codec, 0x01, 0, 7838 AC_VERB_SET_GPIO_MASK, mask); 7839 7840 if (data >= 0) 7841 snd_hda_codec_write(codec, 0x01, 0, 7842 AC_VERB_SET_GPIO_DATA, data); 7843 } 7844 7845 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec) 7846 { 7847 static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01}; 7848 unsigned int i; 7849 7850 for (i = 0; i < ARRAY_SIZE(pins); i++) 7851 snd_hda_codec_write(codec, pins[i], 0, 7852 AC_VERB_SET_POWER_STATE, 0x03); 7853 } 7854 7855 static void sbz_exit_chip(struct hda_codec *codec) 7856 { 7857 chipio_set_stream_control(codec, 0x03, 0); 7858 chipio_set_stream_control(codec, 0x04, 0); 7859 7860 /* Mess with GPIO */ 7861 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1); 7862 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05); 7863 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01); 7864 7865 chipio_set_stream_control(codec, 0x14, 0); 7866 chipio_set_stream_control(codec, 0x0C, 0); 7867 7868 chipio_set_conn_rate(codec, 0x41, SR_192_000); 7869 chipio_set_conn_rate(codec, 0x91, SR_192_000); 7870 7871 chipio_write(codec, 0x18a020, 0x00000083); 7872 7873 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03); 7874 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07); 7875 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06); 7876 7877 chipio_set_stream_control(codec, 0x0C, 0); 7878 7879 chipio_set_control_param(codec, 0x0D, 0x24); 7880 7881 ca0132_clear_unsolicited(codec); 7882 sbz_set_pin_ctl_default(codec); 7883 7884 snd_hda_codec_write(codec, 0x0B, 0, 7885 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 7886 7887 sbz_region2_exit(codec); 7888 } 7889 7890 static void r3d_exit_chip(struct hda_codec *codec) 7891 { 7892 ca0132_clear_unsolicited(codec); 7893 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 7894 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b); 7895 } 7896 7897 static void ae5_exit_chip(struct hda_codec *codec) 7898 { 7899 chipio_set_stream_control(codec, 0x03, 0); 7900 chipio_set_stream_control(codec, 0x04, 0); 7901 7902 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 7903 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7904 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7905 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 7906 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 7907 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00); 7908 ca0113_mmio_gpio_set(codec, 0, false); 7909 ca0113_mmio_gpio_set(codec, 1, false); 7910 7911 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 7912 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 7913 7914 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 7915 7916 chipio_set_stream_control(codec, 0x18, 0); 7917 chipio_set_stream_control(codec, 0x0c, 0); 7918 7919 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83); 7920 } 7921 7922 static void zxr_exit_chip(struct hda_codec *codec) 7923 { 7924 chipio_set_stream_control(codec, 0x03, 0); 7925 chipio_set_stream_control(codec, 0x04, 0); 7926 chipio_set_stream_control(codec, 0x14, 0); 7927 chipio_set_stream_control(codec, 0x0C, 0); 7928 7929 chipio_set_conn_rate(codec, 0x41, SR_192_000); 7930 chipio_set_conn_rate(codec, 0x91, SR_192_000); 7931 7932 chipio_write(codec, 0x18a020, 0x00000083); 7933 7934 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 7935 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 7936 7937 ca0132_clear_unsolicited(codec); 7938 sbz_set_pin_ctl_default(codec); 7939 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00); 7940 7941 ca0113_mmio_gpio_set(codec, 5, false); 7942 ca0113_mmio_gpio_set(codec, 2, false); 7943 ca0113_mmio_gpio_set(codec, 3, false); 7944 ca0113_mmio_gpio_set(codec, 0, false); 7945 ca0113_mmio_gpio_set(codec, 4, true); 7946 ca0113_mmio_gpio_set(codec, 0, true); 7947 ca0113_mmio_gpio_set(codec, 5, true); 7948 ca0113_mmio_gpio_set(codec, 2, false); 7949 ca0113_mmio_gpio_set(codec, 3, false); 7950 } 7951 7952 static void ca0132_exit_chip(struct hda_codec *codec) 7953 { 7954 /* put any chip cleanup stuffs here. */ 7955 7956 if (dspload_is_loaded(codec)) 7957 dsp_reset(codec); 7958 } 7959 7960 /* 7961 * This fixes a problem that was hard to reproduce. Very rarely, I would 7962 * boot up, and there would be no sound, but the DSP indicated it had loaded 7963 * properly. I did a few memory dumps to see if anything was different, and 7964 * there were a few areas of memory uninitialized with a1a2a3a4. This function 7965 * checks if those areas are uninitialized, and if they are, it'll attempt to 7966 * reload the card 3 times. Usually it fixes by the second. 7967 */ 7968 static void sbz_dsp_startup_check(struct hda_codec *codec) 7969 { 7970 struct ca0132_spec *spec = codec->spec; 7971 unsigned int dsp_data_check[4]; 7972 unsigned int cur_address = 0x390; 7973 unsigned int i; 7974 unsigned int failure = 0; 7975 unsigned int reload = 3; 7976 7977 if (spec->startup_check_entered) 7978 return; 7979 7980 spec->startup_check_entered = true; 7981 7982 for (i = 0; i < 4; i++) { 7983 chipio_read(codec, cur_address, &dsp_data_check[i]); 7984 cur_address += 0x4; 7985 } 7986 for (i = 0; i < 4; i++) { 7987 if (dsp_data_check[i] == 0xa1a2a3a4) 7988 failure = 1; 7989 } 7990 7991 codec_dbg(codec, "Startup Check: %d ", failure); 7992 if (failure) 7993 codec_info(codec, "DSP not initialized properly. Attempting to fix."); 7994 /* 7995 * While the failure condition is true, and we haven't reached our 7996 * three reload limit, continue trying to reload the driver and 7997 * fix the issue. 7998 */ 7999 while (failure && (reload != 0)) { 8000 codec_info(codec, "Reloading... Tries left: %d", reload); 8001 sbz_exit_chip(codec); 8002 spec->dsp_state = DSP_DOWNLOAD_INIT; 8003 codec->patch_ops.init(codec); 8004 failure = 0; 8005 for (i = 0; i < 4; i++) { 8006 chipio_read(codec, cur_address, &dsp_data_check[i]); 8007 cur_address += 0x4; 8008 } 8009 for (i = 0; i < 4; i++) { 8010 if (dsp_data_check[i] == 0xa1a2a3a4) 8011 failure = 1; 8012 } 8013 reload--; 8014 } 8015 8016 if (!failure && reload < 3) 8017 codec_info(codec, "DSP fixed."); 8018 8019 if (!failure) 8020 return; 8021 8022 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory."); 8023 } 8024 8025 /* 8026 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add 8027 * extra precision for decibel values. If you had the dB value in floating point 8028 * you would take the value after the decimal point, multiply by 64, and divide 8029 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to 8030 * implement fixed point or floating point dB volumes. For now, I'll set them 8031 * to 0 just incase a value has lingered from a boot into Windows. 8032 */ 8033 static void ca0132_alt_vol_setup(struct hda_codec *codec) 8034 { 8035 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00); 8036 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00); 8037 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00); 8038 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00); 8039 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00); 8040 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00); 8041 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00); 8042 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00); 8043 } 8044 8045 /* 8046 * Extra commands that don't really fit anywhere else. 8047 */ 8048 static void sbz_pre_dsp_setup(struct hda_codec *codec) 8049 { 8050 struct ca0132_spec *spec = codec->spec; 8051 8052 writel(0x00820680, spec->mem_base + 0x01C); 8053 writel(0x00820680, spec->mem_base + 0x01C); 8054 8055 chipio_write(codec, 0x18b0a4, 0x000000c2); 8056 8057 snd_hda_codec_write(codec, 0x11, 0, 8058 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 8059 } 8060 8061 static void r3d_pre_dsp_setup(struct hda_codec *codec) 8062 { 8063 chipio_write(codec, 0x18b0a4, 0x000000c2); 8064 8065 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8066 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E); 8067 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8068 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C); 8069 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8070 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B); 8071 8072 snd_hda_codec_write(codec, 0x11, 0, 8073 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 8074 } 8075 8076 static void r3di_pre_dsp_setup(struct hda_codec *codec) 8077 { 8078 chipio_write(codec, 0x18b0a4, 0x000000c2); 8079 8080 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8081 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E); 8082 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8083 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C); 8084 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8085 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B); 8086 8087 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8088 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); 8089 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8090 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 8091 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8092 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 8093 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8094 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40); 8095 8096 snd_hda_codec_write(codec, 0x11, 0, 8097 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04); 8098 } 8099 8100 /* 8101 * These are sent before the DSP is downloaded. Not sure 8102 * what they do, or if they're necessary. Could possibly 8103 * be removed. Figure they're better to leave in. 8104 */ 8105 static void ca0132_mmio_init(struct hda_codec *codec) 8106 { 8107 struct ca0132_spec *spec = codec->spec; 8108 8109 if (ca0132_quirk(spec) == QUIRK_AE5) 8110 writel(0x00000001, spec->mem_base + 0x400); 8111 else 8112 writel(0x00000000, spec->mem_base + 0x400); 8113 8114 if (ca0132_quirk(spec) == QUIRK_AE5) 8115 writel(0x00000001, spec->mem_base + 0x408); 8116 else 8117 writel(0x00000000, spec->mem_base + 0x408); 8118 8119 if (ca0132_quirk(spec) == QUIRK_AE5) 8120 writel(0x00000001, spec->mem_base + 0x40c); 8121 else 8122 writel(0x00000000, spec->mem_base + 0x40C); 8123 8124 if (ca0132_quirk(spec) == QUIRK_ZXR) 8125 writel(0x00880640, spec->mem_base + 0x01C); 8126 else 8127 writel(0x00880680, spec->mem_base + 0x01C); 8128 8129 if (ca0132_quirk(spec) == QUIRK_AE5) 8130 writel(0x00000080, spec->mem_base + 0xC0C); 8131 else 8132 writel(0x00000083, spec->mem_base + 0xC0C); 8133 8134 writel(0x00000030, spec->mem_base + 0xC00); 8135 writel(0x00000000, spec->mem_base + 0xC04); 8136 8137 if (ca0132_quirk(spec) == QUIRK_AE5) 8138 writel(0x00000000, spec->mem_base + 0xC0C); 8139 else 8140 writel(0x00000003, spec->mem_base + 0xC0C); 8141 8142 writel(0x00000003, spec->mem_base + 0xC0C); 8143 writel(0x00000003, spec->mem_base + 0xC0C); 8144 writel(0x00000003, spec->mem_base + 0xC0C); 8145 8146 if (ca0132_quirk(spec) == QUIRK_AE5) 8147 writel(0x00000001, spec->mem_base + 0xC08); 8148 else 8149 writel(0x000000C1, spec->mem_base + 0xC08); 8150 8151 writel(0x000000F1, spec->mem_base + 0xC08); 8152 writel(0x00000001, spec->mem_base + 0xC08); 8153 writel(0x000000C7, spec->mem_base + 0xC08); 8154 writel(0x000000C1, spec->mem_base + 0xC08); 8155 writel(0x00000080, spec->mem_base + 0xC04); 8156 8157 if (ca0132_quirk(spec) == QUIRK_AE5) { 8158 writel(0x00000000, spec->mem_base + 0x42c); 8159 writel(0x00000000, spec->mem_base + 0x46c); 8160 writel(0x00000000, spec->mem_base + 0x4ac); 8161 writel(0x00000000, spec->mem_base + 0x4ec); 8162 writel(0x00000000, spec->mem_base + 0x43c); 8163 writel(0x00000000, spec->mem_base + 0x47c); 8164 writel(0x00000000, spec->mem_base + 0x4bc); 8165 writel(0x00000000, spec->mem_base + 0x4fc); 8166 writel(0x00000600, spec->mem_base + 0x100); 8167 writel(0x00000014, spec->mem_base + 0x410); 8168 writel(0x0000060f, spec->mem_base + 0x100); 8169 writel(0x0000070f, spec->mem_base + 0x100); 8170 writel(0x00000aff, spec->mem_base + 0x830); 8171 writel(0x00000000, spec->mem_base + 0x86c); 8172 writel(0x0000006b, spec->mem_base + 0x800); 8173 writel(0x00000001, spec->mem_base + 0x86c); 8174 writel(0x0000006b, spec->mem_base + 0x800); 8175 writel(0x00000057, spec->mem_base + 0x804); 8176 writel(0x00800000, spec->mem_base + 0x20c); 8177 } 8178 } 8179 8180 /* 8181 * This function writes to some SFR's, does some region2 writes, and then 8182 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does 8183 * what it does. 8184 */ 8185 static void ae5_register_set(struct hda_codec *codec) 8186 { 8187 struct ca0132_spec *spec = codec->spec; 8188 8189 chipio_8051_write_direct(codec, 0x93, 0x10); 8190 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8191 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44); 8192 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8193 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2); 8194 8195 writeb(0x0f, spec->mem_base + 0x304); 8196 writeb(0x0f, spec->mem_base + 0x304); 8197 writeb(0x0f, spec->mem_base + 0x304); 8198 writeb(0x0f, spec->mem_base + 0x304); 8199 writeb(0x0e, spec->mem_base + 0x100); 8200 writeb(0x1f, spec->mem_base + 0x304); 8201 writeb(0x0c, spec->mem_base + 0x100); 8202 writeb(0x3f, spec->mem_base + 0x304); 8203 writeb(0x08, spec->mem_base + 0x100); 8204 writeb(0x7f, spec->mem_base + 0x304); 8205 writeb(0x00, spec->mem_base + 0x100); 8206 writeb(0xff, spec->mem_base + 0x304); 8207 8208 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 8209 8210 chipio_8051_write_direct(codec, 0x90, 0x00); 8211 chipio_8051_write_direct(codec, 0x90, 0x10); 8212 8213 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8214 8215 chipio_write(codec, 0x18b0a4, 0x000000c2); 8216 8217 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00); 8218 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00); 8219 } 8220 8221 /* 8222 * Extra init functions for alternative ca0132 codecs. Done 8223 * here so they don't clutter up the main ca0132_init function 8224 * anymore than they have to. 8225 */ 8226 static void ca0132_alt_init(struct hda_codec *codec) 8227 { 8228 struct ca0132_spec *spec = codec->spec; 8229 8230 ca0132_alt_vol_setup(codec); 8231 8232 switch (ca0132_quirk(spec)) { 8233 case QUIRK_SBZ: 8234 codec_dbg(codec, "SBZ alt_init"); 8235 ca0132_gpio_init(codec); 8236 sbz_pre_dsp_setup(codec); 8237 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8238 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 8239 break; 8240 case QUIRK_R3DI: 8241 codec_dbg(codec, "R3DI alt_init"); 8242 ca0132_gpio_init(codec); 8243 ca0132_gpio_setup(codec); 8244 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING); 8245 r3di_pre_dsp_setup(codec); 8246 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8247 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4); 8248 break; 8249 case QUIRK_R3D: 8250 r3d_pre_dsp_setup(codec); 8251 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8252 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 8253 break; 8254 case QUIRK_AE5: 8255 ca0132_gpio_init(codec); 8256 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8257 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49); 8258 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8259 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88); 8260 chipio_write(codec, 0x18b030, 0x00000020); 8261 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8262 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 8263 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 8264 break; 8265 case QUIRK_ZXR: 8266 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8267 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 8268 break; 8269 default: 8270 break; 8271 } 8272 } 8273 8274 static int ca0132_init(struct hda_codec *codec) 8275 { 8276 struct ca0132_spec *spec = codec->spec; 8277 struct auto_pin_cfg *cfg = &spec->autocfg; 8278 int i; 8279 bool dsp_loaded; 8280 8281 /* 8282 * If the DSP is already downloaded, and init has been entered again, 8283 * there's only two reasons for it. One, the codec has awaken from a 8284 * suspended state, and in that case dspload_is_loaded will return 8285 * false, and the init will be ran again. The other reason it gets 8286 * re entered is on startup for some reason it triggers a suspend and 8287 * resume state. In this case, it will check if the DSP is downloaded, 8288 * and not run the init function again. For codecs using alt_functions, 8289 * it will check if the DSP is loaded properly. 8290 */ 8291 if (spec->dsp_state == DSP_DOWNLOADED) { 8292 dsp_loaded = dspload_is_loaded(codec); 8293 if (!dsp_loaded) { 8294 spec->dsp_reload = true; 8295 spec->dsp_state = DSP_DOWNLOAD_INIT; 8296 } else { 8297 if (ca0132_quirk(spec) == QUIRK_SBZ) 8298 sbz_dsp_startup_check(codec); 8299 return 0; 8300 } 8301 } 8302 8303 if (spec->dsp_state != DSP_DOWNLOAD_FAILED) 8304 spec->dsp_state = DSP_DOWNLOAD_INIT; 8305 spec->curr_chip_addx = INVALID_CHIP_ADDRESS; 8306 8307 if (ca0132_use_pci_mmio(spec)) 8308 ca0132_mmio_init(codec); 8309 8310 snd_hda_power_up_pm(codec); 8311 8312 if (ca0132_quirk(spec) == QUIRK_AE5) 8313 ae5_register_set(codec); 8314 8315 ca0132_init_unsol(codec); 8316 ca0132_init_params(codec); 8317 ca0132_init_flags(codec); 8318 8319 snd_hda_sequence_write(codec, spec->base_init_verbs); 8320 8321 if (ca0132_use_alt_functions(spec)) 8322 ca0132_alt_init(codec); 8323 8324 ca0132_download_dsp(codec); 8325 8326 ca0132_refresh_widget_caps(codec); 8327 8328 switch (ca0132_quirk(spec)) { 8329 case QUIRK_R3DI: 8330 case QUIRK_R3D: 8331 r3d_setup_defaults(codec); 8332 break; 8333 case QUIRK_SBZ: 8334 case QUIRK_ZXR: 8335 sbz_setup_defaults(codec); 8336 break; 8337 case QUIRK_AE5: 8338 ae5_setup_defaults(codec); 8339 break; 8340 default: 8341 ca0132_setup_defaults(codec); 8342 ca0132_init_analog_mic2(codec); 8343 ca0132_init_dmic(codec); 8344 break; 8345 } 8346 8347 for (i = 0; i < spec->num_outputs; i++) 8348 init_output(codec, spec->out_pins[i], spec->dacs[0]); 8349 8350 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 8351 8352 for (i = 0; i < spec->num_inputs; i++) 8353 init_input(codec, spec->input_pins[i], spec->adcs[i]); 8354 8355 init_input(codec, cfg->dig_in_pin, spec->dig_in); 8356 8357 if (!ca0132_use_alt_functions(spec)) { 8358 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8359 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8360 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D); 8361 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8362 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20); 8363 } 8364 8365 if (ca0132_quirk(spec) == QUIRK_SBZ) 8366 ca0132_gpio_setup(codec); 8367 8368 snd_hda_sequence_write(codec, spec->spec_init_verbs); 8369 if (ca0132_use_alt_functions(spec)) { 8370 ca0132_alt_select_out(codec); 8371 ca0132_alt_select_in(codec); 8372 } else { 8373 ca0132_select_out(codec); 8374 ca0132_select_mic(codec); 8375 } 8376 8377 snd_hda_jack_report_sync(codec); 8378 8379 /* 8380 * Re set the PlayEnhancement switch on a resume event, because the 8381 * controls will not be reloaded. 8382 */ 8383 if (spec->dsp_reload) { 8384 spec->dsp_reload = false; 8385 ca0132_pe_switch_set(codec); 8386 } 8387 8388 snd_hda_power_down_pm(codec); 8389 8390 return 0; 8391 } 8392 8393 static int dbpro_init(struct hda_codec *codec) 8394 { 8395 struct ca0132_spec *spec = codec->spec; 8396 struct auto_pin_cfg *cfg = &spec->autocfg; 8397 unsigned int i; 8398 8399 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 8400 init_input(codec, cfg->dig_in_pin, spec->dig_in); 8401 8402 for (i = 0; i < spec->num_inputs; i++) 8403 init_input(codec, spec->input_pins[i], spec->adcs[i]); 8404 8405 return 0; 8406 } 8407 8408 static void ca0132_free(struct hda_codec *codec) 8409 { 8410 struct ca0132_spec *spec = codec->spec; 8411 8412 cancel_delayed_work_sync(&spec->unsol_hp_work); 8413 snd_hda_power_up(codec); 8414 switch (ca0132_quirk(spec)) { 8415 case QUIRK_SBZ: 8416 sbz_exit_chip(codec); 8417 break; 8418 case QUIRK_ZXR: 8419 zxr_exit_chip(codec); 8420 break; 8421 case QUIRK_R3D: 8422 r3d_exit_chip(codec); 8423 break; 8424 case QUIRK_AE5: 8425 ae5_exit_chip(codec); 8426 break; 8427 case QUIRK_R3DI: 8428 r3di_gpio_shutdown(codec); 8429 break; 8430 default: 8431 break; 8432 } 8433 8434 snd_hda_sequence_write(codec, spec->base_exit_verbs); 8435 ca0132_exit_chip(codec); 8436 8437 snd_hda_power_down(codec); 8438 #ifdef CONFIG_PCI 8439 if (spec->mem_base) 8440 pci_iounmap(codec->bus->pci, spec->mem_base); 8441 #endif 8442 kfree(spec->spec_init_verbs); 8443 kfree(codec->spec); 8444 } 8445 8446 static void dbpro_free(struct hda_codec *codec) 8447 { 8448 struct ca0132_spec *spec = codec->spec; 8449 8450 zxr_dbpro_power_state_shutdown(codec); 8451 8452 kfree(spec->spec_init_verbs); 8453 kfree(codec->spec); 8454 } 8455 8456 static void ca0132_reboot_notify(struct hda_codec *codec) 8457 { 8458 codec->patch_ops.free(codec); 8459 } 8460 8461 #ifdef CONFIG_PM 8462 static int ca0132_suspend(struct hda_codec *codec) 8463 { 8464 struct ca0132_spec *spec = codec->spec; 8465 8466 cancel_delayed_work_sync(&spec->unsol_hp_work); 8467 return 0; 8468 } 8469 #endif 8470 8471 static const struct hda_codec_ops ca0132_patch_ops = { 8472 .build_controls = ca0132_build_controls, 8473 .build_pcms = ca0132_build_pcms, 8474 .init = ca0132_init, 8475 .free = ca0132_free, 8476 .unsol_event = snd_hda_jack_unsol_event, 8477 #ifdef CONFIG_PM 8478 .suspend = ca0132_suspend, 8479 #endif 8480 .reboot_notify = ca0132_reboot_notify, 8481 }; 8482 8483 static const struct hda_codec_ops dbpro_patch_ops = { 8484 .build_controls = dbpro_build_controls, 8485 .build_pcms = dbpro_build_pcms, 8486 .init = dbpro_init, 8487 .free = dbpro_free, 8488 }; 8489 8490 static void ca0132_config(struct hda_codec *codec) 8491 { 8492 struct ca0132_spec *spec = codec->spec; 8493 8494 spec->dacs[0] = 0x2; 8495 spec->dacs[1] = 0x3; 8496 spec->dacs[2] = 0x4; 8497 8498 spec->multiout.dac_nids = spec->dacs; 8499 spec->multiout.num_dacs = 3; 8500 8501 if (!ca0132_use_alt_functions(spec)) 8502 spec->multiout.max_channels = 2; 8503 else 8504 spec->multiout.max_channels = 6; 8505 8506 switch (ca0132_quirk(spec)) { 8507 case QUIRK_ALIENWARE: 8508 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__); 8509 snd_hda_apply_pincfgs(codec, alienware_pincfgs); 8510 break; 8511 case QUIRK_SBZ: 8512 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__); 8513 snd_hda_apply_pincfgs(codec, sbz_pincfgs); 8514 break; 8515 case QUIRK_ZXR: 8516 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__); 8517 snd_hda_apply_pincfgs(codec, zxr_pincfgs); 8518 break; 8519 case QUIRK_R3D: 8520 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__); 8521 snd_hda_apply_pincfgs(codec, r3d_pincfgs); 8522 break; 8523 case QUIRK_R3DI: 8524 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__); 8525 snd_hda_apply_pincfgs(codec, r3di_pincfgs); 8526 break; 8527 case QUIRK_AE5: 8528 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__); 8529 snd_hda_apply_pincfgs(codec, ae5_pincfgs); 8530 break; 8531 default: 8532 break; 8533 } 8534 8535 switch (ca0132_quirk(spec)) { 8536 case QUIRK_ALIENWARE: 8537 spec->num_outputs = 2; 8538 spec->out_pins[0] = 0x0b; /* speaker out */ 8539 spec->out_pins[1] = 0x0f; 8540 spec->shared_out_nid = 0x2; 8541 spec->unsol_tag_hp = 0x0f; 8542 8543 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 8544 spec->adcs[1] = 0x8; /* analog mic2 */ 8545 spec->adcs[2] = 0xa; /* what u hear */ 8546 8547 spec->num_inputs = 3; 8548 spec->input_pins[0] = 0x12; 8549 spec->input_pins[1] = 0x11; 8550 spec->input_pins[2] = 0x13; 8551 spec->shared_mic_nid = 0x7; 8552 spec->unsol_tag_amic1 = 0x11; 8553 break; 8554 case QUIRK_SBZ: 8555 case QUIRK_R3D: 8556 spec->num_outputs = 2; 8557 spec->out_pins[0] = 0x0B; /* Line out */ 8558 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 8559 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 8560 spec->out_pins[3] = 0x11; /* Rear surround */ 8561 spec->shared_out_nid = 0x2; 8562 spec->unsol_tag_hp = spec->out_pins[1]; 8563 spec->unsol_tag_front_hp = spec->out_pins[2]; 8564 8565 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 8566 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 8567 spec->adcs[2] = 0xa; /* what u hear */ 8568 8569 spec->num_inputs = 2; 8570 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 8571 spec->input_pins[1] = 0x13; /* What U Hear */ 8572 spec->shared_mic_nid = 0x7; 8573 spec->unsol_tag_amic1 = spec->input_pins[0]; 8574 8575 /* SPDIF I/O */ 8576 spec->dig_out = 0x05; 8577 spec->multiout.dig_out_nid = spec->dig_out; 8578 spec->dig_in = 0x09; 8579 break; 8580 case QUIRK_ZXR: 8581 spec->num_outputs = 2; 8582 spec->out_pins[0] = 0x0B; /* Line out */ 8583 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 8584 spec->out_pins[2] = 0x10; /* Center/LFE */ 8585 spec->out_pins[3] = 0x11; /* Rear surround */ 8586 spec->shared_out_nid = 0x2; 8587 spec->unsol_tag_hp = spec->out_pins[1]; 8588 spec->unsol_tag_front_hp = spec->out_pins[2]; 8589 8590 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 8591 spec->adcs[1] = 0x8; /* Not connected, no front mic */ 8592 spec->adcs[2] = 0xa; /* what u hear */ 8593 8594 spec->num_inputs = 2; 8595 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 8596 spec->input_pins[1] = 0x13; /* What U Hear */ 8597 spec->shared_mic_nid = 0x7; 8598 spec->unsol_tag_amic1 = spec->input_pins[0]; 8599 break; 8600 case QUIRK_ZXR_DBPRO: 8601 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */ 8602 8603 spec->num_inputs = 1; 8604 spec->input_pins[0] = 0x11; /* RCA Line-in */ 8605 8606 spec->dig_out = 0x05; 8607 spec->multiout.dig_out_nid = spec->dig_out; 8608 8609 spec->dig_in = 0x09; 8610 break; 8611 case QUIRK_AE5: 8612 spec->num_outputs = 2; 8613 spec->out_pins[0] = 0x0B; /* Line out */ 8614 spec->out_pins[1] = 0x11; /* Rear headphone out */ 8615 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 8616 spec->out_pins[3] = 0x0F; /* Rear surround */ 8617 spec->shared_out_nid = 0x2; 8618 spec->unsol_tag_hp = spec->out_pins[1]; 8619 spec->unsol_tag_front_hp = spec->out_pins[2]; 8620 8621 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 8622 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 8623 spec->adcs[2] = 0xa; /* what u hear */ 8624 8625 spec->num_inputs = 2; 8626 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 8627 spec->input_pins[1] = 0x13; /* What U Hear */ 8628 spec->shared_mic_nid = 0x7; 8629 spec->unsol_tag_amic1 = spec->input_pins[0]; 8630 8631 /* SPDIF I/O */ 8632 spec->dig_out = 0x05; 8633 spec->multiout.dig_out_nid = spec->dig_out; 8634 break; 8635 case QUIRK_R3DI: 8636 spec->num_outputs = 2; 8637 spec->out_pins[0] = 0x0B; /* Line out */ 8638 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 8639 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 8640 spec->out_pins[3] = 0x11; /* Rear surround */ 8641 spec->shared_out_nid = 0x2; 8642 spec->unsol_tag_hp = spec->out_pins[1]; 8643 spec->unsol_tag_front_hp = spec->out_pins[2]; 8644 8645 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */ 8646 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */ 8647 spec->adcs[2] = 0x0a; /* what u hear */ 8648 8649 spec->num_inputs = 2; 8650 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 8651 spec->input_pins[1] = 0x13; /* What U Hear */ 8652 spec->shared_mic_nid = 0x7; 8653 spec->unsol_tag_amic1 = spec->input_pins[0]; 8654 8655 /* SPDIF I/O */ 8656 spec->dig_out = 0x05; 8657 spec->multiout.dig_out_nid = spec->dig_out; 8658 break; 8659 default: 8660 spec->num_outputs = 2; 8661 spec->out_pins[0] = 0x0b; /* speaker out */ 8662 spec->out_pins[1] = 0x10; /* headphone out */ 8663 spec->shared_out_nid = 0x2; 8664 spec->unsol_tag_hp = spec->out_pins[1]; 8665 8666 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 8667 spec->adcs[1] = 0x8; /* analog mic2 */ 8668 spec->adcs[2] = 0xa; /* what u hear */ 8669 8670 spec->num_inputs = 3; 8671 spec->input_pins[0] = 0x12; 8672 spec->input_pins[1] = 0x11; 8673 spec->input_pins[2] = 0x13; 8674 spec->shared_mic_nid = 0x7; 8675 spec->unsol_tag_amic1 = spec->input_pins[0]; 8676 8677 /* SPDIF I/O */ 8678 spec->dig_out = 0x05; 8679 spec->multiout.dig_out_nid = spec->dig_out; 8680 spec->dig_in = 0x09; 8681 break; 8682 } 8683 } 8684 8685 static int ca0132_prepare_verbs(struct hda_codec *codec) 8686 { 8687 /* Verbs + terminator (an empty element) */ 8688 #define NUM_SPEC_VERBS 2 8689 struct ca0132_spec *spec = codec->spec; 8690 8691 spec->chip_init_verbs = ca0132_init_verbs0; 8692 /* 8693 * Since desktop cards use pci_mmio, this can be used to determine 8694 * whether or not to use these verbs instead of a separate bool. 8695 */ 8696 if (ca0132_use_pci_mmio(spec)) 8697 spec->desktop_init_verbs = ca0132_init_verbs1; 8698 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS, 8699 sizeof(struct hda_verb), 8700 GFP_KERNEL); 8701 if (!spec->spec_init_verbs) 8702 return -ENOMEM; 8703 8704 /* config EAPD */ 8705 spec->spec_init_verbs[0].nid = 0x0b; 8706 spec->spec_init_verbs[0].param = 0x78D; 8707 spec->spec_init_verbs[0].verb = 0x00; 8708 8709 /* Previously commented configuration */ 8710 /* 8711 spec->spec_init_verbs[2].nid = 0x0b; 8712 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE; 8713 spec->spec_init_verbs[2].verb = 0x02; 8714 8715 spec->spec_init_verbs[3].nid = 0x10; 8716 spec->spec_init_verbs[3].param = 0x78D; 8717 spec->spec_init_verbs[3].verb = 0x02; 8718 8719 spec->spec_init_verbs[4].nid = 0x10; 8720 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE; 8721 spec->spec_init_verbs[4].verb = 0x02; 8722 */ 8723 8724 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */ 8725 return 0; 8726 } 8727 8728 /* 8729 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular 8730 * Sound Blaster Z cards. However, they have different HDA codec subsystem 8731 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro 8732 * daughter boards ID. 8733 */ 8734 static void sbz_detect_quirk(struct hda_codec *codec) 8735 { 8736 struct ca0132_spec *spec = codec->spec; 8737 8738 switch (codec->core.subsystem_id) { 8739 case 0x11020033: 8740 spec->quirk = QUIRK_ZXR; 8741 break; 8742 case 0x1102003f: 8743 spec->quirk = QUIRK_ZXR_DBPRO; 8744 break; 8745 default: 8746 spec->quirk = QUIRK_SBZ; 8747 break; 8748 } 8749 } 8750 8751 static int patch_ca0132(struct hda_codec *codec) 8752 { 8753 struct ca0132_spec *spec; 8754 int err; 8755 const struct snd_pci_quirk *quirk; 8756 8757 codec_dbg(codec, "patch_ca0132\n"); 8758 8759 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 8760 if (!spec) 8761 return -ENOMEM; 8762 codec->spec = spec; 8763 spec->codec = codec; 8764 8765 /* Detect codec quirk */ 8766 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks); 8767 if (quirk) 8768 spec->quirk = quirk->value; 8769 else 8770 spec->quirk = QUIRK_NONE; 8771 if (ca0132_quirk(spec) == QUIRK_SBZ) 8772 sbz_detect_quirk(codec); 8773 8774 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO) 8775 codec->patch_ops = dbpro_patch_ops; 8776 else 8777 codec->patch_ops = ca0132_patch_ops; 8778 8779 codec->pcm_format_first = 1; 8780 codec->no_sticky_stream = 1; 8781 8782 8783 spec->dsp_state = DSP_DOWNLOAD_INIT; 8784 spec->num_mixers = 1; 8785 8786 /* Set which mixers each quirk uses. */ 8787 switch (ca0132_quirk(spec)) { 8788 case QUIRK_SBZ: 8789 spec->mixers[0] = desktop_mixer; 8790 snd_hda_codec_set_name(codec, "Sound Blaster Z"); 8791 break; 8792 case QUIRK_ZXR: 8793 spec->mixers[0] = desktop_mixer; 8794 snd_hda_codec_set_name(codec, "Sound Blaster ZxR"); 8795 break; 8796 case QUIRK_ZXR_DBPRO: 8797 break; 8798 case QUIRK_R3D: 8799 spec->mixers[0] = desktop_mixer; 8800 snd_hda_codec_set_name(codec, "Recon3D"); 8801 break; 8802 case QUIRK_R3DI: 8803 spec->mixers[0] = r3di_mixer; 8804 snd_hda_codec_set_name(codec, "Recon3Di"); 8805 break; 8806 case QUIRK_AE5: 8807 spec->mixers[0] = desktop_mixer; 8808 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5"); 8809 break; 8810 default: 8811 spec->mixers[0] = ca0132_mixer; 8812 break; 8813 } 8814 8815 /* Setup whether or not to use alt functions/controls/pci_mmio */ 8816 switch (ca0132_quirk(spec)) { 8817 case QUIRK_SBZ: 8818 case QUIRK_R3D: 8819 case QUIRK_AE5: 8820 case QUIRK_ZXR: 8821 spec->use_alt_controls = true; 8822 spec->use_alt_functions = true; 8823 spec->use_pci_mmio = true; 8824 break; 8825 case QUIRK_R3DI: 8826 spec->use_alt_controls = true; 8827 spec->use_alt_functions = true; 8828 spec->use_pci_mmio = false; 8829 break; 8830 default: 8831 spec->use_alt_controls = false; 8832 spec->use_alt_functions = false; 8833 spec->use_pci_mmio = false; 8834 break; 8835 } 8836 8837 #ifdef CONFIG_PCI 8838 if (spec->use_pci_mmio) { 8839 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20); 8840 if (spec->mem_base == NULL) { 8841 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE."); 8842 spec->quirk = QUIRK_NONE; 8843 } 8844 } 8845 #endif 8846 8847 spec->base_init_verbs = ca0132_base_init_verbs; 8848 spec->base_exit_verbs = ca0132_base_exit_verbs; 8849 8850 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed); 8851 8852 ca0132_init_chip(codec); 8853 8854 ca0132_config(codec); 8855 8856 err = ca0132_prepare_verbs(codec); 8857 if (err < 0) 8858 goto error; 8859 8860 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL); 8861 if (err < 0) 8862 goto error; 8863 8864 return 0; 8865 8866 error: 8867 ca0132_free(codec); 8868 return err; 8869 } 8870 8871 /* 8872 * patch entries 8873 */ 8874 static const struct hda_device_id snd_hda_id_ca0132[] = { 8875 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132), 8876 {} /* terminator */ 8877 }; 8878 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132); 8879 8880 MODULE_LICENSE("GPL"); 8881 MODULE_DESCRIPTION("Creative Sound Core3D codec"); 8882 8883 static struct hda_codec_driver ca0132_driver = { 8884 .id = snd_hda_id_ca0132, 8885 }; 8886 8887 module_hda_codec_driver(ca0132_driver); 8888