1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * HD audio interface patch for Creative CA0132 chip 4 * 5 * Copyright (c) 2011, Creative Technology Ltd. 6 * 7 * Based on patch_ca0110.c 8 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de> 9 */ 10 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/slab.h> 14 #include <linux/mutex.h> 15 #include <linux/module.h> 16 #include <linux/firmware.h> 17 #include <linux/kernel.h> 18 #include <linux/types.h> 19 #include <linux/io.h> 20 #include <linux/pci.h> 21 #include <asm/io.h> 22 #include <sound/core.h> 23 #include <sound/hda_codec.h> 24 #include "hda_local.h" 25 #include "hda_auto_parser.h" 26 #include "hda_jack.h" 27 28 #include "ca0132_regs.h" 29 30 /* Enable this to see controls for tuning purpose. */ 31 /*#define ENABLE_TUNING_CONTROLS*/ 32 33 #ifdef ENABLE_TUNING_CONTROLS 34 #include <sound/tlv.h> 35 #endif 36 37 #define FLOAT_ZERO 0x00000000 38 #define FLOAT_ONE 0x3f800000 39 #define FLOAT_TWO 0x40000000 40 #define FLOAT_THREE 0x40400000 41 #define FLOAT_FIVE 0x40a00000 42 #define FLOAT_SIX 0x40c00000 43 #define FLOAT_EIGHT 0x41000000 44 #define FLOAT_MINUS_5 0xc0a00000 45 46 #define UNSOL_TAG_DSP 0x16 47 48 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18) 49 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15) 50 51 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8 52 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32 53 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2 54 55 #define MASTERCONTROL 0x80 56 #define MASTERCONTROL_ALLOC_DMA_CHAN 10 57 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60 58 59 #define WIDGET_CHIP_CTRL 0x15 60 #define WIDGET_DSP_CTRL 0x16 61 62 #define MEM_CONNID_MICIN1 3 63 #define MEM_CONNID_MICIN2 5 64 #define MEM_CONNID_MICOUT1 12 65 #define MEM_CONNID_MICOUT2 14 66 #define MEM_CONNID_WUH 10 67 #define MEM_CONNID_DSP 16 68 #define MEM_CONNID_DMIC 100 69 70 #define SCP_SET 0 71 #define SCP_GET 1 72 73 #define EFX_FILE "ctefx.bin" 74 #define DESKTOP_EFX_FILE "ctefx-desktop.bin" 75 #define R3DI_EFX_FILE "ctefx-r3di.bin" 76 77 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 78 MODULE_FIRMWARE(EFX_FILE); 79 MODULE_FIRMWARE(DESKTOP_EFX_FILE); 80 MODULE_FIRMWARE(R3DI_EFX_FILE); 81 #endif 82 83 static const char *const dirstr[2] = { "Playback", "Capture" }; 84 85 #define NUM_OF_OUTPUTS 2 86 static const char *const out_type_str[2] = { "Speakers", "Headphone" }; 87 enum { 88 SPEAKER_OUT, 89 HEADPHONE_OUT, 90 }; 91 92 enum { 93 DIGITAL_MIC, 94 LINE_MIC_IN 95 }; 96 97 /* Strings for Input Source Enum Control */ 98 static const char *const in_src_str[3] = { "Microphone", "Line In", "Front Microphone" }; 99 #define IN_SRC_NUM_OF_INPUTS 3 100 enum { 101 REAR_MIC, 102 REAR_LINE_IN, 103 FRONT_MIC, 104 }; 105 106 enum { 107 #define VNODE_START_NID 0x80 108 VNID_SPK = VNODE_START_NID, /* Speaker vnid */ 109 VNID_MIC, 110 VNID_HP_SEL, 111 VNID_AMIC1_SEL, 112 VNID_HP_ASEL, 113 VNID_AMIC1_ASEL, 114 VNODE_END_NID, 115 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID) 116 117 #define EFFECT_START_NID 0x90 118 #define OUT_EFFECT_START_NID EFFECT_START_NID 119 SURROUND = OUT_EFFECT_START_NID, 120 CRYSTALIZER, 121 DIALOG_PLUS, 122 SMART_VOLUME, 123 X_BASS, 124 EQUALIZER, 125 OUT_EFFECT_END_NID, 126 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID) 127 128 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID 129 ECHO_CANCELLATION = IN_EFFECT_START_NID, 130 VOICE_FOCUS, 131 MIC_SVM, 132 NOISE_REDUCTION, 133 IN_EFFECT_END_NID, 134 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID) 135 136 VOICEFX = IN_EFFECT_END_NID, 137 PLAY_ENHANCEMENT, 138 CRYSTAL_VOICE, 139 EFFECT_END_NID, 140 OUTPUT_SOURCE_ENUM, 141 INPUT_SOURCE_ENUM, 142 XBASS_XOVER, 143 EQ_PRESET_ENUM, 144 SMART_VOLUME_ENUM, 145 MIC_BOOST_ENUM, 146 AE5_HEADPHONE_GAIN_ENUM, 147 AE5_SOUND_FILTER_ENUM, 148 ZXR_HEADPHONE_GAIN, 149 SPEAKER_CHANNEL_CFG_ENUM, 150 SPEAKER_FULL_RANGE_FRONT, 151 SPEAKER_FULL_RANGE_REAR, 152 BASS_REDIRECTION, 153 BASS_REDIRECTION_XOVER, 154 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID) 155 }; 156 157 /* Effects values size*/ 158 #define EFFECT_VALS_MAX_COUNT 12 159 160 /* 161 * Default values for the effect slider controls, they are in order of their 162 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then 163 * X-bass. 164 */ 165 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50}; 166 /* Amount of effect level sliders for ca0132_alt controls. */ 167 #define EFFECT_LEVEL_SLIDERS 5 168 169 /* Latency introduced by DSP blocks in milliseconds. */ 170 #define DSP_CAPTURE_INIT_LATENCY 0 171 #define DSP_CRYSTAL_VOICE_LATENCY 124 172 #define DSP_PLAYBACK_INIT_LATENCY 13 173 #define DSP_PLAY_ENHANCEMENT_LATENCY 30 174 #define DSP_SPEAKER_OUT_LATENCY 7 175 176 struct ct_effect { 177 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 178 hda_nid_t nid; 179 int mid; /*effect module ID*/ 180 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/ 181 int direct; /* 0:output; 1:input*/ 182 int params; /* number of default non-on/off params */ 183 /*effect default values, 1st is on/off. */ 184 unsigned int def_vals[EFFECT_VALS_MAX_COUNT]; 185 }; 186 187 #define EFX_DIR_OUT 0 188 #define EFX_DIR_IN 1 189 190 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = { 191 { .name = "Surround", 192 .nid = SURROUND, 193 .mid = 0x96, 194 .reqs = {0, 1}, 195 .direct = EFX_DIR_OUT, 196 .params = 1, 197 .def_vals = {0x3F800000, 0x3F2B851F} 198 }, 199 { .name = "Crystalizer", 200 .nid = CRYSTALIZER, 201 .mid = 0x96, 202 .reqs = {7, 8}, 203 .direct = EFX_DIR_OUT, 204 .params = 1, 205 .def_vals = {0x3F800000, 0x3F266666} 206 }, 207 { .name = "Dialog Plus", 208 .nid = DIALOG_PLUS, 209 .mid = 0x96, 210 .reqs = {2, 3}, 211 .direct = EFX_DIR_OUT, 212 .params = 1, 213 .def_vals = {0x00000000, 0x3F000000} 214 }, 215 { .name = "Smart Volume", 216 .nid = SMART_VOLUME, 217 .mid = 0x96, 218 .reqs = {4, 5, 6}, 219 .direct = EFX_DIR_OUT, 220 .params = 2, 221 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000} 222 }, 223 { .name = "X-Bass", 224 .nid = X_BASS, 225 .mid = 0x96, 226 .reqs = {24, 23, 25}, 227 .direct = EFX_DIR_OUT, 228 .params = 2, 229 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000} 230 }, 231 { .name = "Equalizer", 232 .nid = EQUALIZER, 233 .mid = 0x96, 234 .reqs = {9, 10, 11, 12, 13, 14, 235 15, 16, 17, 18, 19, 20}, 236 .direct = EFX_DIR_OUT, 237 .params = 11, 238 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000, 239 0x00000000, 0x00000000, 0x00000000, 0x00000000, 240 0x00000000, 0x00000000, 0x00000000, 0x00000000} 241 }, 242 { .name = "Echo Cancellation", 243 .nid = ECHO_CANCELLATION, 244 .mid = 0x95, 245 .reqs = {0, 1, 2, 3}, 246 .direct = EFX_DIR_IN, 247 .params = 3, 248 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000} 249 }, 250 { .name = "Voice Focus", 251 .nid = VOICE_FOCUS, 252 .mid = 0x95, 253 .reqs = {6, 7, 8, 9}, 254 .direct = EFX_DIR_IN, 255 .params = 3, 256 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000} 257 }, 258 { .name = "Mic SVM", 259 .nid = MIC_SVM, 260 .mid = 0x95, 261 .reqs = {44, 45}, 262 .direct = EFX_DIR_IN, 263 .params = 1, 264 .def_vals = {0x00000000, 0x3F3D70A4} 265 }, 266 { .name = "Noise Reduction", 267 .nid = NOISE_REDUCTION, 268 .mid = 0x95, 269 .reqs = {4, 5}, 270 .direct = EFX_DIR_IN, 271 .params = 1, 272 .def_vals = {0x3F800000, 0x3F000000} 273 }, 274 { .name = "VoiceFX", 275 .nid = VOICEFX, 276 .mid = 0x95, 277 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}, 278 .direct = EFX_DIR_IN, 279 .params = 8, 280 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000, 281 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000, 282 0x00000000} 283 } 284 }; 285 286 /* Tuning controls */ 287 #ifdef ENABLE_TUNING_CONTROLS 288 289 enum { 290 #define TUNING_CTL_START_NID 0xC0 291 WEDGE_ANGLE = TUNING_CTL_START_NID, 292 SVM_LEVEL, 293 EQUALIZER_BAND_0, 294 EQUALIZER_BAND_1, 295 EQUALIZER_BAND_2, 296 EQUALIZER_BAND_3, 297 EQUALIZER_BAND_4, 298 EQUALIZER_BAND_5, 299 EQUALIZER_BAND_6, 300 EQUALIZER_BAND_7, 301 EQUALIZER_BAND_8, 302 EQUALIZER_BAND_9, 303 TUNING_CTL_END_NID 304 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID) 305 }; 306 307 struct ct_tuning_ctl { 308 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 309 hda_nid_t parent_nid; 310 hda_nid_t nid; 311 int mid; /*effect module ID*/ 312 int req; /*effect module request*/ 313 int direct; /* 0:output; 1:input*/ 314 unsigned int def_val;/*effect default values*/ 315 }; 316 317 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = { 318 { .name = "Wedge Angle", 319 .parent_nid = VOICE_FOCUS, 320 .nid = WEDGE_ANGLE, 321 .mid = 0x95, 322 .req = 8, 323 .direct = EFX_DIR_IN, 324 .def_val = 0x41F00000 325 }, 326 { .name = "SVM Level", 327 .parent_nid = MIC_SVM, 328 .nid = SVM_LEVEL, 329 .mid = 0x95, 330 .req = 45, 331 .direct = EFX_DIR_IN, 332 .def_val = 0x3F3D70A4 333 }, 334 { .name = "EQ Band0", 335 .parent_nid = EQUALIZER, 336 .nid = EQUALIZER_BAND_0, 337 .mid = 0x96, 338 .req = 11, 339 .direct = EFX_DIR_OUT, 340 .def_val = 0x00000000 341 }, 342 { .name = "EQ Band1", 343 .parent_nid = EQUALIZER, 344 .nid = EQUALIZER_BAND_1, 345 .mid = 0x96, 346 .req = 12, 347 .direct = EFX_DIR_OUT, 348 .def_val = 0x00000000 349 }, 350 { .name = "EQ Band2", 351 .parent_nid = EQUALIZER, 352 .nid = EQUALIZER_BAND_2, 353 .mid = 0x96, 354 .req = 13, 355 .direct = EFX_DIR_OUT, 356 .def_val = 0x00000000 357 }, 358 { .name = "EQ Band3", 359 .parent_nid = EQUALIZER, 360 .nid = EQUALIZER_BAND_3, 361 .mid = 0x96, 362 .req = 14, 363 .direct = EFX_DIR_OUT, 364 .def_val = 0x00000000 365 }, 366 { .name = "EQ Band4", 367 .parent_nid = EQUALIZER, 368 .nid = EQUALIZER_BAND_4, 369 .mid = 0x96, 370 .req = 15, 371 .direct = EFX_DIR_OUT, 372 .def_val = 0x00000000 373 }, 374 { .name = "EQ Band5", 375 .parent_nid = EQUALIZER, 376 .nid = EQUALIZER_BAND_5, 377 .mid = 0x96, 378 .req = 16, 379 .direct = EFX_DIR_OUT, 380 .def_val = 0x00000000 381 }, 382 { .name = "EQ Band6", 383 .parent_nid = EQUALIZER, 384 .nid = EQUALIZER_BAND_6, 385 .mid = 0x96, 386 .req = 17, 387 .direct = EFX_DIR_OUT, 388 .def_val = 0x00000000 389 }, 390 { .name = "EQ Band7", 391 .parent_nid = EQUALIZER, 392 .nid = EQUALIZER_BAND_7, 393 .mid = 0x96, 394 .req = 18, 395 .direct = EFX_DIR_OUT, 396 .def_val = 0x00000000 397 }, 398 { .name = "EQ Band8", 399 .parent_nid = EQUALIZER, 400 .nid = EQUALIZER_BAND_8, 401 .mid = 0x96, 402 .req = 19, 403 .direct = EFX_DIR_OUT, 404 .def_val = 0x00000000 405 }, 406 { .name = "EQ Band9", 407 .parent_nid = EQUALIZER, 408 .nid = EQUALIZER_BAND_9, 409 .mid = 0x96, 410 .req = 20, 411 .direct = EFX_DIR_OUT, 412 .def_val = 0x00000000 413 } 414 }; 415 #endif 416 417 /* Voice FX Presets */ 418 #define VOICEFX_MAX_PARAM_COUNT 9 419 420 struct ct_voicefx { 421 char *name; 422 hda_nid_t nid; 423 int mid; 424 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/ 425 }; 426 427 struct ct_voicefx_preset { 428 char *name; /*preset name*/ 429 unsigned int vals[VOICEFX_MAX_PARAM_COUNT]; 430 }; 431 432 static const struct ct_voicefx ca0132_voicefx = { 433 .name = "VoiceFX Capture Switch", 434 .nid = VOICEFX, 435 .mid = 0x95, 436 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18} 437 }; 438 439 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = { 440 { .name = "Neutral", 441 .vals = { 0x00000000, 0x43C80000, 0x44AF0000, 442 0x44FA0000, 0x3F800000, 0x3F800000, 443 0x3F800000, 0x00000000, 0x00000000 } 444 }, 445 { .name = "Female2Male", 446 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 447 0x44FA0000, 0x3F19999A, 0x3F866666, 448 0x3F800000, 0x00000000, 0x00000000 } 449 }, 450 { .name = "Male2Female", 451 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 452 0x450AC000, 0x4017AE14, 0x3F6B851F, 453 0x3F800000, 0x00000000, 0x00000000 } 454 }, 455 { .name = "ScrappyKid", 456 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 457 0x44FA0000, 0x40400000, 0x3F28F5C3, 458 0x3F800000, 0x00000000, 0x00000000 } 459 }, 460 { .name = "Elderly", 461 .vals = { 0x3F800000, 0x44324000, 0x44BB8000, 462 0x44E10000, 0x3FB33333, 0x3FB9999A, 463 0x3F800000, 0x3E3A2E43, 0x00000000 } 464 }, 465 { .name = "Orc", 466 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000, 467 0x45098000, 0x3F266666, 0x3FC00000, 468 0x3F800000, 0x00000000, 0x00000000 } 469 }, 470 { .name = "Elf", 471 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000, 472 0x45193000, 0x3F8E147B, 0x3F75C28F, 473 0x3F800000, 0x00000000, 0x00000000 } 474 }, 475 { .name = "Dwarf", 476 .vals = { 0x3F800000, 0x43930000, 0x44BEE000, 477 0x45007000, 0x3F451EB8, 0x3F7851EC, 478 0x3F800000, 0x00000000, 0x00000000 } 479 }, 480 { .name = "AlienBrute", 481 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF, 482 0x451F6000, 0x3F266666, 0x3FA7D945, 483 0x3F800000, 0x3CF5C28F, 0x00000000 } 484 }, 485 { .name = "Robot", 486 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 487 0x44FA0000, 0x3FB2718B, 0x3F800000, 488 0xBC07010E, 0x00000000, 0x00000000 } 489 }, 490 { .name = "Marine", 491 .vals = { 0x3F800000, 0x43C20000, 0x44906000, 492 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71, 493 0x3F0A3D71, 0x00000000, 0x00000000 } 494 }, 495 { .name = "Emo", 496 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 497 0x44FA0000, 0x3F800000, 0x3F800000, 498 0x3E4CCCCD, 0x00000000, 0x00000000 } 499 }, 500 { .name = "DeepVoice", 501 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF, 502 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA, 503 0x3F800000, 0x00000000, 0x00000000 } 504 }, 505 { .name = "Munchkin", 506 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 507 0x44FA0000, 0x3F800000, 0x3F1A043C, 508 0x3F800000, 0x00000000, 0x00000000 } 509 } 510 }; 511 512 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */ 513 514 #define EQ_PRESET_MAX_PARAM_COUNT 11 515 516 struct ct_eq { 517 char *name; 518 hda_nid_t nid; 519 int mid; 520 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/ 521 }; 522 523 struct ct_eq_preset { 524 char *name; /*preset name*/ 525 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT]; 526 }; 527 528 static const struct ct_eq ca0132_alt_eq_enum = { 529 .name = "FX: Equalizer Preset Switch", 530 .nid = EQ_PRESET_ENUM, 531 .mid = 0x96, 532 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20} 533 }; 534 535 536 static const struct ct_eq_preset ca0132_alt_eq_presets[] = { 537 { .name = "Flat", 538 .vals = { 0x00000000, 0x00000000, 0x00000000, 539 0x00000000, 0x00000000, 0x00000000, 540 0x00000000, 0x00000000, 0x00000000, 541 0x00000000, 0x00000000 } 542 }, 543 { .name = "Acoustic", 544 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD, 545 0x40000000, 0x00000000, 0x00000000, 546 0x00000000, 0x00000000, 0x40000000, 547 0x40000000, 0x40000000 } 548 }, 549 { .name = "Classical", 550 .vals = { 0x00000000, 0x00000000, 0x40C00000, 551 0x40C00000, 0x40466666, 0x00000000, 552 0x00000000, 0x00000000, 0x00000000, 553 0x40466666, 0x40466666 } 554 }, 555 { .name = "Country", 556 .vals = { 0x00000000, 0xBF99999A, 0x00000000, 557 0x3FA66666, 0x3FA66666, 0x3F8CCCCD, 558 0x00000000, 0x00000000, 0x40000000, 559 0x40466666, 0x40800000 } 560 }, 561 { .name = "Dance", 562 .vals = { 0x00000000, 0xBF99999A, 0x40000000, 563 0x40466666, 0x40866666, 0xBF99999A, 564 0xBF99999A, 0x00000000, 0x00000000, 565 0x40800000, 0x40800000 } 566 }, 567 { .name = "Jazz", 568 .vals = { 0x00000000, 0x00000000, 0x00000000, 569 0x3F8CCCCD, 0x40800000, 0x40800000, 570 0x40800000, 0x00000000, 0x3F8CCCCD, 571 0x40466666, 0x40466666 } 572 }, 573 { .name = "New Age", 574 .vals = { 0x00000000, 0x00000000, 0x40000000, 575 0x40000000, 0x00000000, 0x00000000, 576 0x00000000, 0x3F8CCCCD, 0x40000000, 577 0x40000000, 0x40000000 } 578 }, 579 { .name = "Pop", 580 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000, 581 0x40000000, 0x40000000, 0x00000000, 582 0xBF99999A, 0xBF99999A, 0x00000000, 583 0x40466666, 0x40C00000 } 584 }, 585 { .name = "Rock", 586 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A, 587 0x3F8CCCCD, 0x40000000, 0xBF99999A, 588 0xBF99999A, 0x00000000, 0x00000000, 589 0x40800000, 0x40800000 } 590 }, 591 { .name = "Vocal", 592 .vals = { 0x00000000, 0xC0000000, 0xBF99999A, 593 0xBF99999A, 0x00000000, 0x40466666, 594 0x40800000, 0x40466666, 0x00000000, 595 0x00000000, 0x3F8CCCCD } 596 } 597 }; 598 599 /* 600 * DSP reqs for handling full-range speakers/bass redirection. If a speaker is 601 * set as not being full range, and bass redirection is enabled, all 602 * frequencies below the crossover frequency are redirected to the LFE 603 * channel. If the surround configuration has no LFE channel, this can't be 604 * enabled. X-Bass must be disabled when using these. 605 */ 606 enum speaker_range_reqs { 607 SPEAKER_BASS_REDIRECT = 0x15, 608 SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16, 609 /* Between 0x16-0x1a are the X-Bass reqs. */ 610 SPEAKER_FULL_RANGE_FRONT_L_R = 0x1a, 611 SPEAKER_FULL_RANGE_CENTER_LFE = 0x1b, 612 SPEAKER_FULL_RANGE_REAR_L_R = 0x1c, 613 SPEAKER_FULL_RANGE_SURROUND_L_R = 0x1d, 614 SPEAKER_BASS_REDIRECT_SUB_GAIN = 0x1e, 615 }; 616 617 /* 618 * Definitions for the DSP req's to handle speaker tuning. These all belong to 619 * module ID 0x96, the output effects module. 620 */ 621 enum speaker_tuning_reqs { 622 /* 623 * Currently, this value is always set to 0.0f. However, on Windows, 624 * when selecting certain headphone profiles on the new Sound Blaster 625 * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is 626 * sent. This gets the speaker EQ address area, which is then used to 627 * send over (presumably) an equalizer profile for the specific 628 * headphone setup. It is sent using the same method the DSP 629 * firmware is uploaded with, which I believe is why the 'ctspeq.bin' 630 * file exists in linux firmware tree but goes unused. It would also 631 * explain why the QUERY_SPEAKER_EQ_ADDRESS req is defined but unused. 632 * Once this profile is sent over, SPEAKER_TUNING_USE_SPEAKER_EQ is 633 * set to 1.0f. 634 */ 635 SPEAKER_TUNING_USE_SPEAKER_EQ = 0x1f, 636 SPEAKER_TUNING_ENABLE_CENTER_EQ = 0x20, 637 SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL = 0x21, 638 SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL = 0x22, 639 SPEAKER_TUNING_CENTER_VOL_LEVEL = 0x23, 640 SPEAKER_TUNING_LFE_VOL_LEVEL = 0x24, 641 SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL = 0x25, 642 SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL = 0x26, 643 SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL = 0x27, 644 SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28, 645 /* 646 * Inversion is used when setting headphone virtualization to line 647 * out. Not sure why this is, but it's the only place it's ever used. 648 */ 649 SPEAKER_TUNING_FRONT_LEFT_INVERT = 0x29, 650 SPEAKER_TUNING_FRONT_RIGHT_INVERT = 0x2a, 651 SPEAKER_TUNING_CENTER_INVERT = 0x2b, 652 SPEAKER_TUNING_LFE_INVERT = 0x2c, 653 SPEAKER_TUNING_REAR_LEFT_INVERT = 0x2d, 654 SPEAKER_TUNING_REAR_RIGHT_INVERT = 0x2e, 655 SPEAKER_TUNING_SURROUND_LEFT_INVERT = 0x2f, 656 SPEAKER_TUNING_SURROUND_RIGHT_INVERT = 0x30, 657 /* Delay is used when setting surround speaker distance in Windows. */ 658 SPEAKER_TUNING_FRONT_LEFT_DELAY = 0x31, 659 SPEAKER_TUNING_FRONT_RIGHT_DELAY = 0x32, 660 SPEAKER_TUNING_CENTER_DELAY = 0x33, 661 SPEAKER_TUNING_LFE_DELAY = 0x34, 662 SPEAKER_TUNING_REAR_LEFT_DELAY = 0x35, 663 SPEAKER_TUNING_REAR_RIGHT_DELAY = 0x36, 664 SPEAKER_TUNING_SURROUND_LEFT_DELAY = 0x37, 665 SPEAKER_TUNING_SURROUND_RIGHT_DELAY = 0x38, 666 /* Of these two, only mute seems to ever be used. */ 667 SPEAKER_TUNING_MAIN_VOLUME = 0x39, 668 SPEAKER_TUNING_MUTE = 0x3a, 669 }; 670 671 /* Surround output channel count configuration structures. */ 672 #define SPEAKER_CHANNEL_CFG_COUNT 5 673 enum { 674 SPEAKER_CHANNELS_2_0, 675 SPEAKER_CHANNELS_2_1, 676 SPEAKER_CHANNELS_4_0, 677 SPEAKER_CHANNELS_4_1, 678 SPEAKER_CHANNELS_5_1, 679 }; 680 681 struct ca0132_alt_speaker_channel_cfg { 682 char *name; 683 unsigned int val; 684 }; 685 686 static const struct ca0132_alt_speaker_channel_cfg speaker_channel_cfgs[] = { 687 { .name = "2.0", 688 .val = FLOAT_ONE 689 }, 690 { .name = "2.1", 691 .val = FLOAT_TWO 692 }, 693 { .name = "4.0", 694 .val = FLOAT_FIVE 695 }, 696 { .name = "4.1", 697 .val = FLOAT_SIX 698 }, 699 { .name = "5.1", 700 .val = FLOAT_EIGHT 701 } 702 }; 703 704 /* 705 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume, 706 * and I don't know what the third req is, but it's always zero. I assume it's 707 * some sort of update or set command to tell the DSP there's new volume info. 708 */ 709 #define DSP_VOL_OUT 0 710 #define DSP_VOL_IN 1 711 712 struct ct_dsp_volume_ctl { 713 hda_nid_t vnid; 714 int mid; /* module ID*/ 715 unsigned int reqs[3]; /* scp req ID */ 716 }; 717 718 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = { 719 { .vnid = VNID_SPK, 720 .mid = 0x32, 721 .reqs = {3, 4, 2} 722 }, 723 { .vnid = VNID_MIC, 724 .mid = 0x37, 725 .reqs = {2, 3, 1} 726 } 727 }; 728 729 /* Values for ca0113_mmio_command_set for selecting output. */ 730 #define AE_CA0113_OUT_SET_COMMANDS 6 731 struct ae_ca0113_output_set { 732 unsigned int group[AE_CA0113_OUT_SET_COMMANDS]; 733 unsigned int target[AE_CA0113_OUT_SET_COMMANDS]; 734 unsigned int vals[NUM_OF_OUTPUTS][AE_CA0113_OUT_SET_COMMANDS]; 735 }; 736 737 static const struct ae_ca0113_output_set ae5_ca0113_output_presets = { 738 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 739 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 740 /* Speakers. */ 741 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }, 742 /* Headphones. */ 743 { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } }, 744 }; 745 746 static const struct ae_ca0113_output_set ae7_ca0113_output_presets = { 747 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 748 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 749 /* Speakers. */ 750 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }, 751 /* Headphones. */ 752 { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } }, 753 }; 754 755 /* ae5 ca0113 command sequences to set headphone gain levels. */ 756 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4 757 struct ae5_headphone_gain_set { 758 char *name; 759 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS]; 760 }; 761 762 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = { 763 { .name = "Low (16-31", 764 .vals = { 0xff, 0x2c, 0xf5, 0x32 } 765 }, 766 { .name = "Medium (32-149", 767 .vals = { 0x38, 0xa8, 0x3e, 0x4c } 768 }, 769 { .name = "High (150-600", 770 .vals = { 0xff, 0xff, 0xff, 0x7f } 771 } 772 }; 773 774 struct ae5_filter_set { 775 char *name; 776 unsigned int val; 777 }; 778 779 static const struct ae5_filter_set ae5_filter_presets[] = { 780 { .name = "Slow Roll Off", 781 .val = 0xa0 782 }, 783 { .name = "Minimum Phase", 784 .val = 0xc0 785 }, 786 { .name = "Fast Roll Off", 787 .val = 0x80 788 } 789 }; 790 791 /* 792 * Data structures for storing audio router remapping data. These are used to 793 * remap a currently active streams ports. 794 */ 795 struct chipio_stream_remap_data { 796 unsigned int stream_id; 797 unsigned int count; 798 799 unsigned int offset[16]; 800 unsigned int value[16]; 801 }; 802 803 static const struct chipio_stream_remap_data stream_remap_data[] = { 804 { .stream_id = 0x14, 805 .count = 0x04, 806 .offset = { 0x00, 0x04, 0x08, 0x0c }, 807 .value = { 0x0001f8c0, 0x0001f9c1, 0x0001fac6, 0x0001fbc7 }, 808 }, 809 { .stream_id = 0x0c, 810 .count = 0x0c, 811 .offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 812 0x20, 0x24, 0x28, 0x2c }, 813 .value = { 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3, 814 0x0001e2c4, 0x0001e3c5, 0x0001e8c6, 0x0001e9c7, 815 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb }, 816 }, 817 { .stream_id = 0x0c, 818 .count = 0x08, 819 .offset = { 0x08, 0x0c, 0x10, 0x14, 0x20, 0x24, 0x28, 0x2c }, 820 .value = { 0x000140c2, 0x000141c3, 0x000150c4, 0x000151c5, 821 0x000142c8, 0x000143c9, 0x000152ca, 0x000153cb }, 822 } 823 }; 824 825 enum hda_cmd_vendor_io { 826 /* for DspIO node */ 827 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000, 828 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100, 829 830 VENDOR_DSPIO_STATUS = 0xF01, 831 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702, 832 VENDOR_DSPIO_SCP_READ_DATA = 0xF02, 833 VENDOR_DSPIO_DSP_INIT = 0x703, 834 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704, 835 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04, 836 837 /* for ChipIO node */ 838 VENDOR_CHIPIO_ADDRESS_LOW = 0x000, 839 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100, 840 VENDOR_CHIPIO_STREAM_FORMAT = 0x200, 841 VENDOR_CHIPIO_DATA_LOW = 0x300, 842 VENDOR_CHIPIO_DATA_HIGH = 0x400, 843 844 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500, 845 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00, 846 847 VENDOR_CHIPIO_GET_PARAMETER = 0xF00, 848 VENDOR_CHIPIO_STATUS = 0xF01, 849 VENDOR_CHIPIO_HIC_POST_READ = 0x702, 850 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03, 851 852 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707, 853 VENDOR_CHIPIO_8051_DATA_READ = 0xF07, 854 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08, 855 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709, 856 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09, 857 858 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A, 859 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A, 860 861 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C, 862 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C, 863 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D, 864 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E, 865 VENDOR_CHIPIO_FLAG_SET = 0x70F, 866 VENDOR_CHIPIO_FLAGS_GET = 0xF0F, 867 VENDOR_CHIPIO_PARAM_SET = 0x710, 868 VENDOR_CHIPIO_PARAM_GET = 0xF10, 869 870 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711, 871 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712, 872 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12, 873 VENDOR_CHIPIO_PORT_FREE_SET = 0x713, 874 875 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17, 876 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717, 877 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18, 878 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718, 879 880 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788, 881 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88, 882 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789, 883 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89, 884 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A, 885 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A, 886 887 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D 888 }; 889 890 /* 891 * Control flag IDs 892 */ 893 enum control_flag_id { 894 /* Connection manager stream setup is bypassed/enabled */ 895 CONTROL_FLAG_C_MGR = 0, 896 /* DSP DMA is bypassed/enabled */ 897 CONTROL_FLAG_DMA = 1, 898 /* 8051 'idle' mode is disabled/enabled */ 899 CONTROL_FLAG_IDLE_ENABLE = 2, 900 /* Tracker for the SPDIF-in path is bypassed/enabled */ 901 CONTROL_FLAG_TRACKER = 3, 902 /* DigitalOut to Spdif2Out connection is disabled/enabled */ 903 CONTROL_FLAG_SPDIF2OUT = 4, 904 /* Digital Microphone is disabled/enabled */ 905 CONTROL_FLAG_DMIC = 5, 906 /* ADC_B rate is 48 kHz/96 kHz */ 907 CONTROL_FLAG_ADC_B_96KHZ = 6, 908 /* ADC_C rate is 48 kHz/96 kHz */ 909 CONTROL_FLAG_ADC_C_96KHZ = 7, 910 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */ 911 CONTROL_FLAG_DAC_96KHZ = 8, 912 /* DSP rate is 48 kHz/96 kHz */ 913 CONTROL_FLAG_DSP_96KHZ = 9, 914 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */ 915 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10, 916 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */ 917 CONTROL_FLAG_SRC_RATE_96KHZ = 11, 918 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */ 919 CONTROL_FLAG_DECODE_LOOP = 12, 920 /* De-emphasis filter on DAC-1 disabled/enabled */ 921 CONTROL_FLAG_DAC1_DEEMPHASIS = 13, 922 /* De-emphasis filter on DAC-2 disabled/enabled */ 923 CONTROL_FLAG_DAC2_DEEMPHASIS = 14, 924 /* De-emphasis filter on DAC-3 disabled/enabled */ 925 CONTROL_FLAG_DAC3_DEEMPHASIS = 15, 926 /* High-pass filter on ADC_B disabled/enabled */ 927 CONTROL_FLAG_ADC_B_HIGH_PASS = 16, 928 /* High-pass filter on ADC_C disabled/enabled */ 929 CONTROL_FLAG_ADC_C_HIGH_PASS = 17, 930 /* Common mode on Port_A disabled/enabled */ 931 CONTROL_FLAG_PORT_A_COMMON_MODE = 18, 932 /* Common mode on Port_D disabled/enabled */ 933 CONTROL_FLAG_PORT_D_COMMON_MODE = 19, 934 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */ 935 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20, 936 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */ 937 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21, 938 /* ASI rate is 48kHz/96kHz */ 939 CONTROL_FLAG_ASI_96KHZ = 22, 940 /* DAC power settings able to control attached ports no/yes */ 941 CONTROL_FLAG_DACS_CONTROL_PORTS = 23, 942 /* Clock Stop OK reporting is disabled/enabled */ 943 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24, 944 /* Number of control flags */ 945 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1) 946 }; 947 948 /* 949 * Control parameter IDs 950 */ 951 enum control_param_id { 952 /* 0: None, 1: Mic1In*/ 953 CONTROL_PARAM_VIP_SOURCE = 1, 954 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */ 955 CONTROL_PARAM_SPDIF1_SOURCE = 2, 956 /* Port A output stage gain setting to use when 16 Ohm output 957 * impedance is selected*/ 958 CONTROL_PARAM_PORTA_160OHM_GAIN = 8, 959 /* Port D output stage gain setting to use when 16 Ohm output 960 * impedance is selected*/ 961 CONTROL_PARAM_PORTD_160OHM_GAIN = 10, 962 963 /* 964 * This control param name was found in the 8051 memory, and makes 965 * sense given the fact the AE-5 uses it and has the ASI flag set. 966 */ 967 CONTROL_PARAM_ASI = 23, 968 969 /* Stream Control */ 970 971 /* Select stream with the given ID */ 972 CONTROL_PARAM_STREAM_ID = 24, 973 /* Source connection point for the selected stream */ 974 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25, 975 /* Destination connection point for the selected stream */ 976 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26, 977 /* Number of audio channels in the selected stream */ 978 CONTROL_PARAM_STREAMS_CHANNELS = 27, 979 /*Enable control for the selected stream */ 980 CONTROL_PARAM_STREAM_CONTROL = 28, 981 982 /* Connection Point Control */ 983 984 /* Select connection point with the given ID */ 985 CONTROL_PARAM_CONN_POINT_ID = 29, 986 /* Connection point sample rate */ 987 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30, 988 989 /* Node Control */ 990 991 /* Select HDA node with the given ID */ 992 CONTROL_PARAM_NODE_ID = 31 993 }; 994 995 /* 996 * Dsp Io Status codes 997 */ 998 enum hda_vendor_status_dspio { 999 /* Success */ 1000 VENDOR_STATUS_DSPIO_OK = 0x00, 1001 /* Busy, unable to accept new command, the host must retry */ 1002 VENDOR_STATUS_DSPIO_BUSY = 0x01, 1003 /* SCP command queue is full */ 1004 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02, 1005 /* SCP response queue is empty */ 1006 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03 1007 }; 1008 1009 /* 1010 * Chip Io Status codes 1011 */ 1012 enum hda_vendor_status_chipio { 1013 /* Success */ 1014 VENDOR_STATUS_CHIPIO_OK = 0x00, 1015 /* Busy, unable to accept new command, the host must retry */ 1016 VENDOR_STATUS_CHIPIO_BUSY = 0x01 1017 }; 1018 1019 /* 1020 * CA0132 sample rate 1021 */ 1022 enum ca0132_sample_rate { 1023 SR_6_000 = 0x00, 1024 SR_8_000 = 0x01, 1025 SR_9_600 = 0x02, 1026 SR_11_025 = 0x03, 1027 SR_16_000 = 0x04, 1028 SR_22_050 = 0x05, 1029 SR_24_000 = 0x06, 1030 SR_32_000 = 0x07, 1031 SR_44_100 = 0x08, 1032 SR_48_000 = 0x09, 1033 SR_88_200 = 0x0A, 1034 SR_96_000 = 0x0B, 1035 SR_144_000 = 0x0C, 1036 SR_176_400 = 0x0D, 1037 SR_192_000 = 0x0E, 1038 SR_384_000 = 0x0F, 1039 1040 SR_COUNT = 0x10, 1041 1042 SR_RATE_UNKNOWN = 0x1F 1043 }; 1044 1045 enum dsp_download_state { 1046 DSP_DOWNLOAD_FAILED = -1, 1047 DSP_DOWNLOAD_INIT = 0, 1048 DSP_DOWNLOADING = 1, 1049 DSP_DOWNLOADED = 2 1050 }; 1051 1052 /* retrieve parameters from hda format */ 1053 #define get_hdafmt_chs(fmt) (fmt & 0xf) 1054 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7) 1055 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f) 1056 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1) 1057 1058 /* 1059 * CA0132 specific 1060 */ 1061 1062 struct ca0132_spec { 1063 const struct snd_kcontrol_new *mixers[5]; 1064 unsigned int num_mixers; 1065 const struct hda_verb *base_init_verbs; 1066 const struct hda_verb *base_exit_verbs; 1067 const struct hda_verb *chip_init_verbs; 1068 const struct hda_verb *desktop_init_verbs; 1069 struct hda_verb *spec_init_verbs; 1070 struct auto_pin_cfg autocfg; 1071 1072 /* Nodes configurations */ 1073 struct hda_multi_out multiout; 1074 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS]; 1075 hda_nid_t dacs[AUTO_CFG_MAX_OUTS]; 1076 unsigned int num_outputs; 1077 hda_nid_t input_pins[AUTO_PIN_LAST]; 1078 hda_nid_t adcs[AUTO_PIN_LAST]; 1079 hda_nid_t dig_out; 1080 hda_nid_t dig_in; 1081 unsigned int num_inputs; 1082 hda_nid_t shared_mic_nid; 1083 hda_nid_t shared_out_nid; 1084 hda_nid_t unsol_tag_hp; 1085 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */ 1086 hda_nid_t unsol_tag_amic1; 1087 1088 /* chip access */ 1089 struct mutex chipio_mutex; /* chip access mutex */ 1090 u32 curr_chip_addx; 1091 1092 /* DSP download related */ 1093 enum dsp_download_state dsp_state; 1094 unsigned int dsp_stream_id; 1095 unsigned int wait_scp; 1096 unsigned int wait_scp_header; 1097 unsigned int wait_num_data; 1098 unsigned int scp_resp_header; 1099 unsigned int scp_resp_data[4]; 1100 unsigned int scp_resp_count; 1101 bool startup_check_entered; 1102 bool dsp_reload; 1103 1104 /* mixer and effects related */ 1105 unsigned char dmic_ctl; 1106 int cur_out_type; 1107 int cur_mic_type; 1108 long vnode_lvol[VNODES_COUNT]; 1109 long vnode_rvol[VNODES_COUNT]; 1110 long vnode_lswitch[VNODES_COUNT]; 1111 long vnode_rswitch[VNODES_COUNT]; 1112 long effects_switch[EFFECTS_COUNT]; 1113 long voicefx_val; 1114 long cur_mic_boost; 1115 /* ca0132_alt control related values */ 1116 unsigned char in_enum_val; 1117 unsigned char out_enum_val; 1118 unsigned char channel_cfg_val; 1119 unsigned char speaker_range_val[2]; 1120 unsigned char mic_boost_enum_val; 1121 unsigned char smart_volume_setting; 1122 unsigned char bass_redirection_val; 1123 long bass_redirect_xover_freq; 1124 long fx_ctl_val[EFFECT_LEVEL_SLIDERS]; 1125 long xbass_xover_freq; 1126 long eq_preset_val; 1127 unsigned int tlv[4]; 1128 struct hda_vmaster_mute_hook vmaster_mute; 1129 /* AE-5 Control values */ 1130 unsigned char ae5_headphone_gain_val; 1131 unsigned char ae5_filter_val; 1132 /* ZxR Control Values */ 1133 unsigned char zxr_gain_set; 1134 1135 struct hda_codec *codec; 1136 struct delayed_work unsol_hp_work; 1137 1138 #ifdef ENABLE_TUNING_CONTROLS 1139 long cur_ctl_vals[TUNING_CTLS_COUNT]; 1140 #endif 1141 /* 1142 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster 1143 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown 1144 * things. 1145 */ 1146 bool use_pci_mmio; 1147 void __iomem *mem_base; 1148 1149 /* 1150 * Whether or not to use the alt functions like alt_select_out, 1151 * alt_select_in, etc. Only used on desktop codecs for now, because of 1152 * surround sound support. 1153 */ 1154 bool use_alt_functions; 1155 1156 /* 1157 * Whether or not to use alt controls: volume effect sliders, EQ 1158 * presets, smart volume presets, and new control names with FX prefix. 1159 * Renames PlayEnhancement and CrystalVoice too. 1160 */ 1161 bool use_alt_controls; 1162 }; 1163 1164 /* 1165 * CA0132 quirks table 1166 */ 1167 enum { 1168 QUIRK_ALIENWARE, 1169 QUIRK_ALIENWARE_M17XR4, 1170 QUIRK_SBZ, 1171 QUIRK_ZXR, 1172 QUIRK_ZXR_DBPRO, 1173 QUIRK_R3DI, 1174 QUIRK_R3D, 1175 QUIRK_AE5, 1176 QUIRK_AE7, 1177 QUIRK_NONE = HDA_FIXUP_ID_NOT_SET, 1178 }; 1179 1180 #ifdef CONFIG_PCI 1181 #define ca0132_quirk(spec) ((spec)->codec->fixup_id) 1182 #define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio) 1183 #define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions) 1184 #define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls) 1185 #else 1186 #define ca0132_quirk(spec) ({ (void)(spec); QUIRK_NONE; }) 1187 #define ca0132_use_alt_functions(spec) ({ (void)(spec); false; }) 1188 #define ca0132_use_pci_mmio(spec) ({ (void)(spec); false; }) 1189 #define ca0132_use_alt_controls(spec) ({ (void)(spec); false; }) 1190 #endif 1191 1192 static const struct hda_pintbl alienware_pincfgs[] = { 1193 { 0x0b, 0x90170110 }, /* Builtin Speaker */ 1194 { 0x0c, 0x411111f0 }, /* N/A */ 1195 { 0x0d, 0x411111f0 }, /* N/A */ 1196 { 0x0e, 0x411111f0 }, /* N/A */ 1197 { 0x0f, 0x0321101f }, /* HP */ 1198 { 0x10, 0x411111f0 }, /* Headset? disabled for now */ 1199 { 0x11, 0x03a11021 }, /* Mic */ 1200 { 0x12, 0xd5a30140 }, /* Builtin Mic */ 1201 { 0x13, 0x411111f0 }, /* N/A */ 1202 { 0x18, 0x411111f0 }, /* N/A */ 1203 {} 1204 }; 1205 1206 /* Sound Blaster Z pin configs taken from Windows Driver */ 1207 static const struct hda_pintbl sbz_pincfgs[] = { 1208 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1209 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1210 { 0x0d, 0x014510f0 }, /* Digital Out */ 1211 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1212 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */ 1213 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1214 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1215 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1216 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1217 { 0x18, 0x50d000f0 }, /* N/A */ 1218 {} 1219 }; 1220 1221 /* Sound Blaster ZxR pin configs taken from Windows Driver */ 1222 static const struct hda_pintbl zxr_pincfgs[] = { 1223 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */ 1224 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/ 1225 { 0x0d, 0x014510f0 }, /* Digital Out */ 1226 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/ 1227 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */ 1228 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */ 1229 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */ 1230 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */ 1231 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1232 { 0x18, 0x50d000f0 }, /* N/A */ 1233 {} 1234 }; 1235 1236 /* Recon3D pin configs taken from Windows Driver */ 1237 static const struct hda_pintbl r3d_pincfgs[] = { 1238 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1239 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1240 { 0x0d, 0x014510f0 }, /* Digital Out */ 1241 { 0x0e, 0x01c520f0 }, /* SPDIF In */ 1242 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1243 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1244 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1245 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1246 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1247 { 0x18, 0x50d000f0 }, /* N/A */ 1248 {} 1249 }; 1250 1251 /* Sound Blaster AE-5 pin configs taken from Windows Driver */ 1252 static const struct hda_pintbl ae5_pincfgs[] = { 1253 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1254 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1255 { 0x0d, 0x014510f0 }, /* Digital Out */ 1256 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1257 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */ 1258 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1259 { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */ 1260 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1261 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1262 { 0x18, 0x50d000f0 }, /* N/A */ 1263 {} 1264 }; 1265 1266 /* Recon3D integrated pin configs taken from Windows Driver */ 1267 static const struct hda_pintbl r3di_pincfgs[] = { 1268 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1269 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1270 { 0x0d, 0x014510f0 }, /* Digital Out */ 1271 { 0x0e, 0x41c520f0 }, /* SPDIF In */ 1272 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1273 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1274 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1275 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1276 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1277 { 0x18, 0x500000f0 }, /* N/A */ 1278 {} 1279 }; 1280 1281 static const struct hda_pintbl ae7_pincfgs[] = { 1282 { 0x0b, 0x01017010 }, 1283 { 0x0c, 0x014510f0 }, 1284 { 0x0d, 0x414510f0 }, 1285 { 0x0e, 0x01c520f0 }, 1286 { 0x0f, 0x01017114 }, 1287 { 0x10, 0x01017011 }, 1288 { 0x11, 0x018170ff }, 1289 { 0x12, 0x01a170f0 }, 1290 { 0x13, 0x908700f0 }, 1291 { 0x18, 0x500000f0 }, 1292 {} 1293 }; 1294 1295 static const struct hda_quirk ca0132_quirks[] = { 1296 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4), 1297 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE), 1298 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE), 1299 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE), 1300 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ), 1301 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ), 1302 SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ), 1303 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ), 1304 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI), 1305 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI), 1306 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI), 1307 SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI), 1308 SND_PCI_QUIRK(0x3842, 0x104b, "EVGA X299 Dark", QUIRK_R3DI), 1309 SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI), 1310 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D), 1311 SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D), 1312 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5), 1313 SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5), 1314 SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7), 1315 {} 1316 }; 1317 1318 static const struct hda_model_fixup ca0132_quirk_models[] = { 1319 { .id = QUIRK_ALIENWARE, .name = "alienware" }, 1320 { .id = QUIRK_ALIENWARE_M17XR4, .name = "alienware-m17xr4" }, 1321 { .id = QUIRK_SBZ, .name = "sbz" }, 1322 { .id = QUIRK_ZXR, .name = "zxr" }, 1323 { .id = QUIRK_ZXR_DBPRO, .name = "zxr-dbpro" }, 1324 { .id = QUIRK_R3DI, .name = "r3di" }, 1325 { .id = QUIRK_R3D, .name = "r3d" }, 1326 { .id = QUIRK_AE5, .name = "ae5" }, 1327 { .id = QUIRK_AE7, .name = "ae7" }, 1328 {} 1329 }; 1330 1331 /* Output selection quirk info structures. */ 1332 #define MAX_QUIRK_MMIO_GPIO_SET_VALS 3 1333 #define MAX_QUIRK_SCP_SET_VALS 2 1334 struct ca0132_alt_out_set_info { 1335 unsigned int dac2port; /* ParamID 0x0d value. */ 1336 1337 bool has_hda_gpio; 1338 char hda_gpio_pin; 1339 char hda_gpio_set; 1340 1341 unsigned int mmio_gpio_count; 1342 char mmio_gpio_pin[MAX_QUIRK_MMIO_GPIO_SET_VALS]; 1343 char mmio_gpio_set[MAX_QUIRK_MMIO_GPIO_SET_VALS]; 1344 1345 unsigned int scp_cmds_count; 1346 unsigned int scp_cmd_mid[MAX_QUIRK_SCP_SET_VALS]; 1347 unsigned int scp_cmd_req[MAX_QUIRK_SCP_SET_VALS]; 1348 unsigned int scp_cmd_val[MAX_QUIRK_SCP_SET_VALS]; 1349 1350 bool has_chipio_write; 1351 unsigned int chipio_write_addr; 1352 unsigned int chipio_write_data; 1353 }; 1354 1355 struct ca0132_alt_out_set_quirk_data { 1356 int quirk_id; 1357 1358 bool has_headphone_gain; 1359 bool is_ae_series; 1360 1361 struct ca0132_alt_out_set_info out_set_info[NUM_OF_OUTPUTS]; 1362 }; 1363 1364 static const struct ca0132_alt_out_set_quirk_data quirk_out_set_data[] = { 1365 { .quirk_id = QUIRK_R3DI, 1366 .has_headphone_gain = false, 1367 .is_ae_series = false, 1368 .out_set_info = { 1369 /* Speakers. */ 1370 { .dac2port = 0x24, 1371 .has_hda_gpio = true, 1372 .hda_gpio_pin = 2, 1373 .hda_gpio_set = 1, 1374 .mmio_gpio_count = 0, 1375 .scp_cmds_count = 0, 1376 .has_chipio_write = false, 1377 }, 1378 /* Headphones. */ 1379 { .dac2port = 0x21, 1380 .has_hda_gpio = true, 1381 .hda_gpio_pin = 2, 1382 .hda_gpio_set = 0, 1383 .mmio_gpio_count = 0, 1384 .scp_cmds_count = 0, 1385 .has_chipio_write = false, 1386 } }, 1387 }, 1388 { .quirk_id = QUIRK_R3D, 1389 .has_headphone_gain = false, 1390 .is_ae_series = false, 1391 .out_set_info = { 1392 /* Speakers. */ 1393 { .dac2port = 0x24, 1394 .has_hda_gpio = false, 1395 .mmio_gpio_count = 1, 1396 .mmio_gpio_pin = { 1 }, 1397 .mmio_gpio_set = { 1 }, 1398 .scp_cmds_count = 0, 1399 .has_chipio_write = false, 1400 }, 1401 /* Headphones. */ 1402 { .dac2port = 0x21, 1403 .has_hda_gpio = false, 1404 .mmio_gpio_count = 1, 1405 .mmio_gpio_pin = { 1 }, 1406 .mmio_gpio_set = { 0 }, 1407 .scp_cmds_count = 0, 1408 .has_chipio_write = false, 1409 } }, 1410 }, 1411 { .quirk_id = QUIRK_SBZ, 1412 .has_headphone_gain = false, 1413 .is_ae_series = false, 1414 .out_set_info = { 1415 /* Speakers. */ 1416 { .dac2port = 0x18, 1417 .has_hda_gpio = false, 1418 .mmio_gpio_count = 3, 1419 .mmio_gpio_pin = { 7, 4, 1 }, 1420 .mmio_gpio_set = { 0, 1, 1 }, 1421 .scp_cmds_count = 0, 1422 .has_chipio_write = false, }, 1423 /* Headphones. */ 1424 { .dac2port = 0x12, 1425 .has_hda_gpio = false, 1426 .mmio_gpio_count = 3, 1427 .mmio_gpio_pin = { 7, 4, 1 }, 1428 .mmio_gpio_set = { 1, 1, 0 }, 1429 .scp_cmds_count = 0, 1430 .has_chipio_write = false, 1431 } }, 1432 }, 1433 { .quirk_id = QUIRK_ZXR, 1434 .has_headphone_gain = true, 1435 .is_ae_series = false, 1436 .out_set_info = { 1437 /* Speakers. */ 1438 { .dac2port = 0x24, 1439 .has_hda_gpio = false, 1440 .mmio_gpio_count = 3, 1441 .mmio_gpio_pin = { 2, 3, 5 }, 1442 .mmio_gpio_set = { 1, 1, 0 }, 1443 .scp_cmds_count = 0, 1444 .has_chipio_write = false, 1445 }, 1446 /* Headphones. */ 1447 { .dac2port = 0x21, 1448 .has_hda_gpio = false, 1449 .mmio_gpio_count = 3, 1450 .mmio_gpio_pin = { 2, 3, 5 }, 1451 .mmio_gpio_set = { 0, 1, 1 }, 1452 .scp_cmds_count = 0, 1453 .has_chipio_write = false, 1454 } }, 1455 }, 1456 { .quirk_id = QUIRK_AE5, 1457 .has_headphone_gain = true, 1458 .is_ae_series = true, 1459 .out_set_info = { 1460 /* Speakers. */ 1461 { .dac2port = 0xa4, 1462 .has_hda_gpio = false, 1463 .mmio_gpio_count = 0, 1464 .scp_cmds_count = 2, 1465 .scp_cmd_mid = { 0x96, 0x96 }, 1466 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1467 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1468 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO }, 1469 .has_chipio_write = true, 1470 .chipio_write_addr = 0x0018b03c, 1471 .chipio_write_data = 0x00000012 1472 }, 1473 /* Headphones. */ 1474 { .dac2port = 0xa1, 1475 .has_hda_gpio = false, 1476 .mmio_gpio_count = 0, 1477 .scp_cmds_count = 2, 1478 .scp_cmd_mid = { 0x96, 0x96 }, 1479 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1480 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1481 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE }, 1482 .has_chipio_write = true, 1483 .chipio_write_addr = 0x0018b03c, 1484 .chipio_write_data = 0x00000012 1485 } }, 1486 }, 1487 { .quirk_id = QUIRK_AE7, 1488 .has_headphone_gain = true, 1489 .is_ae_series = true, 1490 .out_set_info = { 1491 /* Speakers. */ 1492 { .dac2port = 0x58, 1493 .has_hda_gpio = false, 1494 .mmio_gpio_count = 1, 1495 .mmio_gpio_pin = { 0 }, 1496 .mmio_gpio_set = { 1 }, 1497 .scp_cmds_count = 2, 1498 .scp_cmd_mid = { 0x96, 0x96 }, 1499 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1500 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1501 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO }, 1502 .has_chipio_write = true, 1503 .chipio_write_addr = 0x0018b03c, 1504 .chipio_write_data = 0x00000000 1505 }, 1506 /* Headphones. */ 1507 { .dac2port = 0x58, 1508 .has_hda_gpio = false, 1509 .mmio_gpio_count = 1, 1510 .mmio_gpio_pin = { 0 }, 1511 .mmio_gpio_set = { 1 }, 1512 .scp_cmds_count = 2, 1513 .scp_cmd_mid = { 0x96, 0x96 }, 1514 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1515 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1516 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE }, 1517 .has_chipio_write = true, 1518 .chipio_write_addr = 0x0018b03c, 1519 .chipio_write_data = 0x00000010 1520 } }, 1521 } 1522 }; 1523 1524 /* 1525 * CA0132 codec access 1526 */ 1527 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid, 1528 unsigned int verb, unsigned int parm, unsigned int *res) 1529 { 1530 unsigned int response; 1531 response = snd_hda_codec_read(codec, nid, 0, verb, parm); 1532 *res = response; 1533 1534 return ((response == -1) ? -1 : 0); 1535 } 1536 1537 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid, 1538 unsigned short converter_format, unsigned int *res) 1539 { 1540 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT, 1541 converter_format & 0xffff, res); 1542 } 1543 1544 static int codec_set_converter_stream_channel(struct hda_codec *codec, 1545 hda_nid_t nid, unsigned char stream, 1546 unsigned char channel, unsigned int *res) 1547 { 1548 unsigned char converter_stream_channel = 0; 1549 1550 converter_stream_channel = (stream << 4) | (channel & 0x0f); 1551 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID, 1552 converter_stream_channel, res); 1553 } 1554 1555 /* Chip access helper function */ 1556 static int chipio_send(struct hda_codec *codec, 1557 unsigned int reg, 1558 unsigned int data) 1559 { 1560 unsigned int res; 1561 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1562 1563 /* send bits of data specified by reg */ 1564 do { 1565 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1566 reg, data); 1567 if (res == VENDOR_STATUS_CHIPIO_OK) 1568 return 0; 1569 msleep(20); 1570 } while (time_before(jiffies, timeout)); 1571 1572 return -EIO; 1573 } 1574 1575 /* 1576 * Write chip address through the vendor widget -- NOT protected by the Mutex! 1577 */ 1578 static int chipio_write_address(struct hda_codec *codec, 1579 unsigned int chip_addx) 1580 { 1581 struct ca0132_spec *spec = codec->spec; 1582 int res; 1583 1584 if (spec->curr_chip_addx == chip_addx) 1585 return 0; 1586 1587 /* send low 16 bits of the address */ 1588 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW, 1589 chip_addx & 0xffff); 1590 1591 if (res != -EIO) { 1592 /* send high 16 bits of the address */ 1593 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH, 1594 chip_addx >> 16); 1595 } 1596 1597 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx; 1598 1599 return res; 1600 } 1601 1602 /* 1603 * Write data through the vendor widget -- NOT protected by the Mutex! 1604 */ 1605 static int chipio_write_data(struct hda_codec *codec, unsigned int data) 1606 { 1607 struct ca0132_spec *spec = codec->spec; 1608 int res; 1609 1610 /* send low 16 bits of the data */ 1611 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff); 1612 1613 if (res != -EIO) { 1614 /* send high 16 bits of the data */ 1615 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH, 1616 data >> 16); 1617 } 1618 1619 /*If no error encountered, automatically increment the address 1620 as per chip behaviour*/ 1621 spec->curr_chip_addx = (res != -EIO) ? 1622 (spec->curr_chip_addx + 4) : ~0U; 1623 return res; 1624 } 1625 1626 /* 1627 * Write multiple data through the vendor widget -- NOT protected by the Mutex! 1628 */ 1629 static int chipio_write_data_multiple(struct hda_codec *codec, 1630 const u32 *data, 1631 unsigned int count) 1632 { 1633 int status = 0; 1634 1635 if (data == NULL) { 1636 codec_dbg(codec, "chipio_write_data null ptr\n"); 1637 return -EINVAL; 1638 } 1639 1640 while ((count-- != 0) && (status == 0)) 1641 status = chipio_write_data(codec, *data++); 1642 1643 return status; 1644 } 1645 1646 1647 /* 1648 * Read data through the vendor widget -- NOT protected by the Mutex! 1649 */ 1650 static int chipio_read_data(struct hda_codec *codec, unsigned int *data) 1651 { 1652 struct ca0132_spec *spec = codec->spec; 1653 int res; 1654 1655 /* post read */ 1656 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0); 1657 1658 if (res != -EIO) { 1659 /* read status */ 1660 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 1661 } 1662 1663 if (res != -EIO) { 1664 /* read data */ 1665 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1666 VENDOR_CHIPIO_HIC_READ_DATA, 1667 0); 1668 } 1669 1670 /*If no error encountered, automatically increment the address 1671 as per chip behaviour*/ 1672 spec->curr_chip_addx = (res != -EIO) ? 1673 (spec->curr_chip_addx + 4) : ~0U; 1674 return res; 1675 } 1676 1677 /* 1678 * Write given value to the given address through the chip I/O widget. 1679 * protected by the Mutex 1680 */ 1681 static int chipio_write(struct hda_codec *codec, 1682 unsigned int chip_addx, const unsigned int data) 1683 { 1684 struct ca0132_spec *spec = codec->spec; 1685 int err; 1686 1687 mutex_lock(&spec->chipio_mutex); 1688 1689 /* write the address, and if successful proceed to write data */ 1690 err = chipio_write_address(codec, chip_addx); 1691 if (err < 0) 1692 goto exit; 1693 1694 err = chipio_write_data(codec, data); 1695 if (err < 0) 1696 goto exit; 1697 1698 exit: 1699 mutex_unlock(&spec->chipio_mutex); 1700 return err; 1701 } 1702 1703 /* 1704 * Write given value to the given address through the chip I/O widget. 1705 * not protected by the Mutex 1706 */ 1707 static int chipio_write_no_mutex(struct hda_codec *codec, 1708 unsigned int chip_addx, const unsigned int data) 1709 { 1710 int err; 1711 1712 1713 /* write the address, and if successful proceed to write data */ 1714 err = chipio_write_address(codec, chip_addx); 1715 if (err < 0) 1716 goto exit; 1717 1718 err = chipio_write_data(codec, data); 1719 if (err < 0) 1720 goto exit; 1721 1722 exit: 1723 return err; 1724 } 1725 1726 /* 1727 * Write multiple values to the given address through the chip I/O widget. 1728 * protected by the Mutex 1729 */ 1730 static int chipio_write_multiple(struct hda_codec *codec, 1731 u32 chip_addx, 1732 const u32 *data, 1733 unsigned int count) 1734 { 1735 struct ca0132_spec *spec = codec->spec; 1736 int status; 1737 1738 mutex_lock(&spec->chipio_mutex); 1739 status = chipio_write_address(codec, chip_addx); 1740 if (status < 0) 1741 goto error; 1742 1743 status = chipio_write_data_multiple(codec, data, count); 1744 error: 1745 mutex_unlock(&spec->chipio_mutex); 1746 1747 return status; 1748 } 1749 1750 /* 1751 * Read the given address through the chip I/O widget 1752 * protected by the Mutex 1753 */ 1754 static int chipio_read(struct hda_codec *codec, 1755 unsigned int chip_addx, unsigned int *data) 1756 { 1757 struct ca0132_spec *spec = codec->spec; 1758 int err; 1759 1760 mutex_lock(&spec->chipio_mutex); 1761 1762 /* write the address, and if successful proceed to write data */ 1763 err = chipio_write_address(codec, chip_addx); 1764 if (err < 0) 1765 goto exit; 1766 1767 err = chipio_read_data(codec, data); 1768 if (err < 0) 1769 goto exit; 1770 1771 exit: 1772 mutex_unlock(&spec->chipio_mutex); 1773 return err; 1774 } 1775 1776 /* 1777 * Set chip control flags through the chip I/O widget. 1778 */ 1779 static void chipio_set_control_flag(struct hda_codec *codec, 1780 enum control_flag_id flag_id, 1781 bool flag_state) 1782 { 1783 unsigned int val; 1784 unsigned int flag_bit; 1785 1786 flag_bit = (flag_state ? 1 : 0); 1787 val = (flag_bit << 7) | (flag_id); 1788 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1789 VENDOR_CHIPIO_FLAG_SET, val); 1790 } 1791 1792 /* 1793 * Set chip parameters through the chip I/O widget. 1794 */ 1795 static void chipio_set_control_param(struct hda_codec *codec, 1796 enum control_param_id param_id, int param_val) 1797 { 1798 struct ca0132_spec *spec = codec->spec; 1799 int val; 1800 1801 if ((param_id < 32) && (param_val < 8)) { 1802 val = (param_val << 5) | (param_id); 1803 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1804 VENDOR_CHIPIO_PARAM_SET, val); 1805 } else { 1806 mutex_lock(&spec->chipio_mutex); 1807 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1808 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1809 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1810 param_id); 1811 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1812 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1813 param_val); 1814 } 1815 mutex_unlock(&spec->chipio_mutex); 1816 } 1817 } 1818 1819 /* 1820 * Set chip parameters through the chip I/O widget. NO MUTEX. 1821 */ 1822 static void chipio_set_control_param_no_mutex(struct hda_codec *codec, 1823 enum control_param_id param_id, int param_val) 1824 { 1825 int val; 1826 1827 if ((param_id < 32) && (param_val < 8)) { 1828 val = (param_val << 5) | (param_id); 1829 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1830 VENDOR_CHIPIO_PARAM_SET, val); 1831 } else { 1832 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1833 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1834 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1835 param_id); 1836 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1837 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1838 param_val); 1839 } 1840 } 1841 } 1842 /* 1843 * Connect stream to a source point, and then connect 1844 * that source point to a destination point. 1845 */ 1846 static void chipio_set_stream_source_dest(struct hda_codec *codec, 1847 int streamid, int source_point, int dest_point) 1848 { 1849 chipio_set_control_param_no_mutex(codec, 1850 CONTROL_PARAM_STREAM_ID, streamid); 1851 chipio_set_control_param_no_mutex(codec, 1852 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point); 1853 chipio_set_control_param_no_mutex(codec, 1854 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point); 1855 } 1856 1857 /* 1858 * Set number of channels in the selected stream. 1859 */ 1860 static void chipio_set_stream_channels(struct hda_codec *codec, 1861 int streamid, unsigned int channels) 1862 { 1863 chipio_set_control_param_no_mutex(codec, 1864 CONTROL_PARAM_STREAM_ID, streamid); 1865 chipio_set_control_param_no_mutex(codec, 1866 CONTROL_PARAM_STREAMS_CHANNELS, channels); 1867 } 1868 1869 /* 1870 * Enable/Disable audio stream. 1871 */ 1872 static void chipio_set_stream_control(struct hda_codec *codec, 1873 int streamid, int enable) 1874 { 1875 chipio_set_control_param_no_mutex(codec, 1876 CONTROL_PARAM_STREAM_ID, streamid); 1877 chipio_set_control_param_no_mutex(codec, 1878 CONTROL_PARAM_STREAM_CONTROL, enable); 1879 } 1880 1881 /* 1882 * Get ChipIO audio stream's status. 1883 */ 1884 static void chipio_get_stream_control(struct hda_codec *codec, 1885 int streamid, unsigned int *enable) 1886 { 1887 chipio_set_control_param_no_mutex(codec, 1888 CONTROL_PARAM_STREAM_ID, streamid); 1889 *enable = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1890 VENDOR_CHIPIO_PARAM_GET, 1891 CONTROL_PARAM_STREAM_CONTROL); 1892 } 1893 1894 /* 1895 * Set sampling rate of the connection point. NO MUTEX. 1896 */ 1897 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec, 1898 int connid, enum ca0132_sample_rate rate) 1899 { 1900 chipio_set_control_param_no_mutex(codec, 1901 CONTROL_PARAM_CONN_POINT_ID, connid); 1902 chipio_set_control_param_no_mutex(codec, 1903 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate); 1904 } 1905 1906 /* 1907 * Set sampling rate of the connection point. 1908 */ 1909 static void chipio_set_conn_rate(struct hda_codec *codec, 1910 int connid, enum ca0132_sample_rate rate) 1911 { 1912 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid); 1913 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, 1914 rate); 1915 } 1916 1917 /* 1918 * Writes to the 8051's internal address space directly instead of indirectly, 1919 * giving access to the special function registers located at addresses 1920 * 0x80-0xFF. 1921 */ 1922 static void chipio_8051_write_direct(struct hda_codec *codec, 1923 unsigned int addr, unsigned int data) 1924 { 1925 unsigned int verb; 1926 1927 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data; 1928 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr); 1929 } 1930 1931 /* 1932 * Writes to the 8051's exram, which has 16-bits of address space. 1933 * Data at addresses 0x2000-0x7fff is mirrored to 0x8000-0xdfff. 1934 * Data at 0x8000-0xdfff can also be used as program memory for the 8051 by 1935 * setting the pmem bank selection SFR. 1936 * 0xe000-0xffff is always mapped as program memory, with only 0xf000-0xffff 1937 * being writable. 1938 */ 1939 static void chipio_8051_set_address(struct hda_codec *codec, unsigned int addr) 1940 { 1941 unsigned int tmp; 1942 1943 /* Lower 8-bits. */ 1944 tmp = addr & 0xff; 1945 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1946 VENDOR_CHIPIO_8051_ADDRESS_LOW, tmp); 1947 1948 /* Upper 8-bits. */ 1949 tmp = (addr >> 8) & 0xff; 1950 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1951 VENDOR_CHIPIO_8051_ADDRESS_HIGH, tmp); 1952 } 1953 1954 static void chipio_8051_set_data(struct hda_codec *codec, unsigned int data) 1955 { 1956 /* 8-bits of data. */ 1957 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1958 VENDOR_CHIPIO_8051_DATA_WRITE, data & 0xff); 1959 } 1960 1961 static unsigned int chipio_8051_get_data(struct hda_codec *codec) 1962 { 1963 return snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1964 VENDOR_CHIPIO_8051_DATA_READ, 0); 1965 } 1966 1967 /* PLL_PMU writes share the lower address register of the 8051 exram writes. */ 1968 static void chipio_8051_set_data_pll(struct hda_codec *codec, unsigned int data) 1969 { 1970 /* 8-bits of data. */ 1971 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1972 VENDOR_CHIPIO_PLL_PMU_WRITE, data & 0xff); 1973 } 1974 1975 static void chipio_8051_write_exram(struct hda_codec *codec, 1976 unsigned int addr, unsigned int data) 1977 { 1978 struct ca0132_spec *spec = codec->spec; 1979 1980 mutex_lock(&spec->chipio_mutex); 1981 1982 chipio_8051_set_address(codec, addr); 1983 chipio_8051_set_data(codec, data); 1984 1985 mutex_unlock(&spec->chipio_mutex); 1986 } 1987 1988 static void chipio_8051_write_exram_no_mutex(struct hda_codec *codec, 1989 unsigned int addr, unsigned int data) 1990 { 1991 chipio_8051_set_address(codec, addr); 1992 chipio_8051_set_data(codec, data); 1993 } 1994 1995 /* Readback data from the 8051's exram. No mutex. */ 1996 static void chipio_8051_read_exram(struct hda_codec *codec, 1997 unsigned int addr, unsigned int *data) 1998 { 1999 chipio_8051_set_address(codec, addr); 2000 *data = chipio_8051_get_data(codec); 2001 } 2002 2003 static void chipio_8051_write_pll_pmu(struct hda_codec *codec, 2004 unsigned int addr, unsigned int data) 2005 { 2006 struct ca0132_spec *spec = codec->spec; 2007 2008 mutex_lock(&spec->chipio_mutex); 2009 2010 chipio_8051_set_address(codec, addr & 0xff); 2011 chipio_8051_set_data_pll(codec, data); 2012 2013 mutex_unlock(&spec->chipio_mutex); 2014 } 2015 2016 static void chipio_8051_write_pll_pmu_no_mutex(struct hda_codec *codec, 2017 unsigned int addr, unsigned int data) 2018 { 2019 chipio_8051_set_address(codec, addr & 0xff); 2020 chipio_8051_set_data_pll(codec, data); 2021 } 2022 2023 /* 2024 * Enable clocks. 2025 */ 2026 static void chipio_enable_clocks(struct hda_codec *codec) 2027 { 2028 struct ca0132_spec *spec = codec->spec; 2029 2030 mutex_lock(&spec->chipio_mutex); 2031 2032 chipio_8051_write_pll_pmu_no_mutex(codec, 0x00, 0xff); 2033 chipio_8051_write_pll_pmu_no_mutex(codec, 0x05, 0x0b); 2034 chipio_8051_write_pll_pmu_no_mutex(codec, 0x06, 0xff); 2035 2036 mutex_unlock(&spec->chipio_mutex); 2037 } 2038 2039 /* 2040 * CA0132 DSP IO stuffs 2041 */ 2042 static int dspio_send(struct hda_codec *codec, unsigned int reg, 2043 unsigned int data) 2044 { 2045 int res; 2046 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2047 2048 /* send bits of data specified by reg to dsp */ 2049 do { 2050 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data); 2051 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY)) 2052 return res; 2053 msleep(20); 2054 } while (time_before(jiffies, timeout)); 2055 2056 return -EIO; 2057 } 2058 2059 /* 2060 * Wait for DSP to be ready for commands 2061 */ 2062 static void dspio_write_wait(struct hda_codec *codec) 2063 { 2064 int status; 2065 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2066 2067 do { 2068 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 2069 VENDOR_DSPIO_STATUS, 0); 2070 if ((status == VENDOR_STATUS_DSPIO_OK) || 2071 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)) 2072 break; 2073 msleep(1); 2074 } while (time_before(jiffies, timeout)); 2075 } 2076 2077 /* 2078 * Write SCP data to DSP 2079 */ 2080 static int dspio_write(struct hda_codec *codec, unsigned int scp_data) 2081 { 2082 struct ca0132_spec *spec = codec->spec; 2083 int status; 2084 2085 dspio_write_wait(codec); 2086 2087 mutex_lock(&spec->chipio_mutex); 2088 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW, 2089 scp_data & 0xffff); 2090 if (status < 0) 2091 goto error; 2092 2093 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH, 2094 scp_data >> 16); 2095 if (status < 0) 2096 goto error; 2097 2098 /* OK, now check if the write itself has executed*/ 2099 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 2100 VENDOR_DSPIO_STATUS, 0); 2101 error: 2102 mutex_unlock(&spec->chipio_mutex); 2103 2104 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ? 2105 -EIO : 0; 2106 } 2107 2108 /* 2109 * Write multiple SCP data to DSP 2110 */ 2111 static int dspio_write_multiple(struct hda_codec *codec, 2112 unsigned int *buffer, unsigned int size) 2113 { 2114 int status = 0; 2115 unsigned int count; 2116 2117 if (buffer == NULL) 2118 return -EINVAL; 2119 2120 count = 0; 2121 while (count < size) { 2122 status = dspio_write(codec, *buffer++); 2123 if (status != 0) 2124 break; 2125 count++; 2126 } 2127 2128 return status; 2129 } 2130 2131 static int dspio_read(struct hda_codec *codec, unsigned int *data) 2132 { 2133 int status; 2134 2135 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0); 2136 if (status == -EIO) 2137 return status; 2138 2139 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0); 2140 if (status == -EIO || 2141 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY) 2142 return -EIO; 2143 2144 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 2145 VENDOR_DSPIO_SCP_READ_DATA, 0); 2146 2147 return 0; 2148 } 2149 2150 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer, 2151 unsigned int *buf_size, unsigned int size_count) 2152 { 2153 int status = 0; 2154 unsigned int size = *buf_size; 2155 unsigned int count; 2156 unsigned int skip_count; 2157 unsigned int dummy; 2158 2159 if (buffer == NULL) 2160 return -1; 2161 2162 count = 0; 2163 while (count < size && count < size_count) { 2164 status = dspio_read(codec, buffer++); 2165 if (status != 0) 2166 break; 2167 count++; 2168 } 2169 2170 skip_count = count; 2171 if (status == 0) { 2172 while (skip_count < size) { 2173 status = dspio_read(codec, &dummy); 2174 if (status != 0) 2175 break; 2176 skip_count++; 2177 } 2178 } 2179 *buf_size = count; 2180 2181 return status; 2182 } 2183 2184 /* 2185 * Construct the SCP header using corresponding fields 2186 */ 2187 static inline unsigned int 2188 make_scp_header(unsigned int target_id, unsigned int source_id, 2189 unsigned int get_flag, unsigned int req, 2190 unsigned int device_flag, unsigned int resp_flag, 2191 unsigned int error_flag, unsigned int data_size) 2192 { 2193 unsigned int header = 0; 2194 2195 header = (data_size & 0x1f) << 27; 2196 header |= (error_flag & 0x01) << 26; 2197 header |= (resp_flag & 0x01) << 25; 2198 header |= (device_flag & 0x01) << 24; 2199 header |= (req & 0x7f) << 17; 2200 header |= (get_flag & 0x01) << 16; 2201 header |= (source_id & 0xff) << 8; 2202 header |= target_id & 0xff; 2203 2204 return header; 2205 } 2206 2207 /* 2208 * Extract corresponding fields from SCP header 2209 */ 2210 static inline void 2211 extract_scp_header(unsigned int header, 2212 unsigned int *target_id, unsigned int *source_id, 2213 unsigned int *get_flag, unsigned int *req, 2214 unsigned int *device_flag, unsigned int *resp_flag, 2215 unsigned int *error_flag, unsigned int *data_size) 2216 { 2217 if (data_size) 2218 *data_size = (header >> 27) & 0x1f; 2219 if (error_flag) 2220 *error_flag = (header >> 26) & 0x01; 2221 if (resp_flag) 2222 *resp_flag = (header >> 25) & 0x01; 2223 if (device_flag) 2224 *device_flag = (header >> 24) & 0x01; 2225 if (req) 2226 *req = (header >> 17) & 0x7f; 2227 if (get_flag) 2228 *get_flag = (header >> 16) & 0x01; 2229 if (source_id) 2230 *source_id = (header >> 8) & 0xff; 2231 if (target_id) 2232 *target_id = header & 0xff; 2233 } 2234 2235 #define SCP_MAX_DATA_WORDS (16) 2236 2237 /* Structure to contain any SCP message */ 2238 struct scp_msg { 2239 unsigned int hdr; 2240 unsigned int data[SCP_MAX_DATA_WORDS]; 2241 }; 2242 2243 static void dspio_clear_response_queue(struct hda_codec *codec) 2244 { 2245 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2246 unsigned int dummy = 0; 2247 int status; 2248 2249 /* clear all from the response queue */ 2250 do { 2251 status = dspio_read(codec, &dummy); 2252 } while (status == 0 && time_before(jiffies, timeout)); 2253 } 2254 2255 static int dspio_get_response_data(struct hda_codec *codec) 2256 { 2257 struct ca0132_spec *spec = codec->spec; 2258 unsigned int data = 0; 2259 unsigned int count; 2260 2261 if (dspio_read(codec, &data) < 0) 2262 return -EIO; 2263 2264 if ((data & 0x00ffffff) == spec->wait_scp_header) { 2265 spec->scp_resp_header = data; 2266 spec->scp_resp_count = data >> 27; 2267 count = spec->wait_num_data; 2268 dspio_read_multiple(codec, spec->scp_resp_data, 2269 &spec->scp_resp_count, count); 2270 return 0; 2271 } 2272 2273 return -EIO; 2274 } 2275 2276 /* 2277 * Send SCP message to DSP 2278 */ 2279 static int dspio_send_scp_message(struct hda_codec *codec, 2280 unsigned char *send_buf, 2281 unsigned int send_buf_size, 2282 unsigned char *return_buf, 2283 unsigned int return_buf_size, 2284 unsigned int *bytes_returned) 2285 { 2286 struct ca0132_spec *spec = codec->spec; 2287 int status; 2288 unsigned int scp_send_size = 0; 2289 unsigned int total_size; 2290 bool waiting_for_resp = false; 2291 unsigned int header; 2292 struct scp_msg *ret_msg; 2293 unsigned int resp_src_id, resp_target_id; 2294 unsigned int data_size, src_id, target_id, get_flag, device_flag; 2295 2296 if (bytes_returned) 2297 *bytes_returned = 0; 2298 2299 /* get scp header from buffer */ 2300 header = *((unsigned int *)send_buf); 2301 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL, 2302 &device_flag, NULL, NULL, &data_size); 2303 scp_send_size = data_size + 1; 2304 total_size = (scp_send_size * 4); 2305 2306 if (send_buf_size < total_size) 2307 return -EINVAL; 2308 2309 if (get_flag || device_flag) { 2310 if (!return_buf || return_buf_size < 4 || !bytes_returned) 2311 return -EINVAL; 2312 2313 spec->wait_scp_header = *((unsigned int *)send_buf); 2314 2315 /* swap source id with target id */ 2316 resp_target_id = src_id; 2317 resp_src_id = target_id; 2318 spec->wait_scp_header &= 0xffff0000; 2319 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id); 2320 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1; 2321 spec->wait_scp = 1; 2322 waiting_for_resp = true; 2323 } 2324 2325 status = dspio_write_multiple(codec, (unsigned int *)send_buf, 2326 scp_send_size); 2327 if (status < 0) { 2328 spec->wait_scp = 0; 2329 return status; 2330 } 2331 2332 if (waiting_for_resp) { 2333 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2334 memset(return_buf, 0, return_buf_size); 2335 do { 2336 msleep(20); 2337 } while (spec->wait_scp && time_before(jiffies, timeout)); 2338 waiting_for_resp = false; 2339 if (!spec->wait_scp) { 2340 ret_msg = (struct scp_msg *)return_buf; 2341 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4); 2342 memcpy(&ret_msg->data, spec->scp_resp_data, 2343 spec->wait_num_data); 2344 *bytes_returned = (spec->scp_resp_count + 1) * 4; 2345 status = 0; 2346 } else { 2347 status = -EIO; 2348 } 2349 spec->wait_scp = 0; 2350 } 2351 2352 return status; 2353 } 2354 2355 /** 2356 * dspio_scp - Prepare and send the SCP message to DSP 2357 * @codec: the HDA codec 2358 * @mod_id: ID of the DSP module to send the command 2359 * @src_id: ID of the source 2360 * @req: ID of request to send to the DSP module 2361 * @dir: SET or GET 2362 * @data: pointer to the data to send with the request, request specific 2363 * @len: length of the data, in bytes 2364 * @reply: point to the buffer to hold data returned for a reply 2365 * @reply_len: length of the reply buffer returned from GET 2366 * 2367 * Returns zero or a negative error code. 2368 */ 2369 static int dspio_scp(struct hda_codec *codec, 2370 int mod_id, int src_id, int req, int dir, const void *data, 2371 unsigned int len, void *reply, unsigned int *reply_len) 2372 { 2373 int status = 0; 2374 struct scp_msg scp_send, scp_reply; 2375 unsigned int ret_bytes, send_size, ret_size; 2376 unsigned int send_get_flag, reply_resp_flag, reply_error_flag; 2377 unsigned int reply_data_size; 2378 2379 memset(&scp_send, 0, sizeof(scp_send)); 2380 memset(&scp_reply, 0, sizeof(scp_reply)); 2381 2382 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS)) 2383 return -EINVAL; 2384 2385 if (dir == SCP_GET && reply == NULL) { 2386 codec_dbg(codec, "dspio_scp get but has no buffer\n"); 2387 return -EINVAL; 2388 } 2389 2390 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) { 2391 codec_dbg(codec, "dspio_scp bad resp buf len parms\n"); 2392 return -EINVAL; 2393 } 2394 2395 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req, 2396 0, 0, 0, len/sizeof(unsigned int)); 2397 if (data != NULL && len > 0) { 2398 len = min((unsigned int)(sizeof(scp_send.data)), len); 2399 memcpy(scp_send.data, data, len); 2400 } 2401 2402 ret_bytes = 0; 2403 send_size = sizeof(unsigned int) + len; 2404 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send, 2405 send_size, (unsigned char *)&scp_reply, 2406 sizeof(scp_reply), &ret_bytes); 2407 2408 if (status < 0) { 2409 codec_dbg(codec, "dspio_scp: send scp msg failed\n"); 2410 return status; 2411 } 2412 2413 /* extract send and reply headers members */ 2414 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag, 2415 NULL, NULL, NULL, NULL, NULL); 2416 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL, 2417 &reply_resp_flag, &reply_error_flag, 2418 &reply_data_size); 2419 2420 if (!send_get_flag) 2421 return 0; 2422 2423 if (reply_resp_flag && !reply_error_flag) { 2424 ret_size = (ret_bytes - sizeof(scp_reply.hdr)) 2425 / sizeof(unsigned int); 2426 2427 if (*reply_len < ret_size*sizeof(unsigned int)) { 2428 codec_dbg(codec, "reply too long for buf\n"); 2429 return -EINVAL; 2430 } else if (ret_size != reply_data_size) { 2431 codec_dbg(codec, "RetLen and HdrLen .NE.\n"); 2432 return -EINVAL; 2433 } else if (!reply) { 2434 codec_dbg(codec, "NULL reply\n"); 2435 return -EINVAL; 2436 } else { 2437 *reply_len = ret_size*sizeof(unsigned int); 2438 memcpy(reply, scp_reply.data, *reply_len); 2439 } 2440 } else { 2441 codec_dbg(codec, "reply ill-formed or errflag set\n"); 2442 return -EIO; 2443 } 2444 2445 return status; 2446 } 2447 2448 /* 2449 * Set DSP parameters 2450 */ 2451 static int dspio_set_param(struct hda_codec *codec, int mod_id, 2452 int src_id, int req, const void *data, unsigned int len) 2453 { 2454 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL, 2455 NULL); 2456 } 2457 2458 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id, 2459 int req, const unsigned int data) 2460 { 2461 return dspio_set_param(codec, mod_id, 0x20, req, &data, 2462 sizeof(unsigned int)); 2463 } 2464 2465 /* 2466 * Allocate a DSP DMA channel via an SCP message 2467 */ 2468 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan) 2469 { 2470 int status = 0; 2471 unsigned int size = sizeof(*dma_chan); 2472 2473 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n"); 2474 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2475 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0, 2476 dma_chan, &size); 2477 2478 if (status < 0) { 2479 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n"); 2480 return status; 2481 } 2482 2483 if ((*dma_chan + 1) == 0) { 2484 codec_dbg(codec, "no free dma channels to allocate\n"); 2485 return -EBUSY; 2486 } 2487 2488 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan); 2489 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n"); 2490 2491 return status; 2492 } 2493 2494 /* 2495 * Free a DSP DMA via an SCP message 2496 */ 2497 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan) 2498 { 2499 int status = 0; 2500 unsigned int dummy = 0; 2501 2502 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n"); 2503 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan); 2504 2505 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2506 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan, 2507 sizeof(dma_chan), NULL, &dummy); 2508 2509 if (status < 0) { 2510 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n"); 2511 return status; 2512 } 2513 2514 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n"); 2515 2516 return status; 2517 } 2518 2519 /* 2520 * (Re)start the DSP 2521 */ 2522 static int dsp_set_run_state(struct hda_codec *codec) 2523 { 2524 unsigned int dbg_ctrl_reg; 2525 unsigned int halt_state; 2526 int err; 2527 2528 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg); 2529 if (err < 0) 2530 return err; 2531 2532 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >> 2533 DSP_DBGCNTL_STATE_LOBIT; 2534 2535 if (halt_state != 0) { 2536 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) & 2537 DSP_DBGCNTL_SS_MASK); 2538 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2539 dbg_ctrl_reg); 2540 if (err < 0) 2541 return err; 2542 2543 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) & 2544 DSP_DBGCNTL_EXEC_MASK; 2545 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2546 dbg_ctrl_reg); 2547 if (err < 0) 2548 return err; 2549 } 2550 2551 return 0; 2552 } 2553 2554 /* 2555 * Reset the DSP 2556 */ 2557 static int dsp_reset(struct hda_codec *codec) 2558 { 2559 unsigned int res; 2560 int retry = 20; 2561 2562 codec_dbg(codec, "dsp_reset\n"); 2563 do { 2564 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0); 2565 retry--; 2566 } while (res == -EIO && retry); 2567 2568 if (!retry) { 2569 codec_dbg(codec, "dsp_reset timeout\n"); 2570 return -EIO; 2571 } 2572 2573 return 0; 2574 } 2575 2576 /* 2577 * Convert chip address to DSP address 2578 */ 2579 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx, 2580 bool *code, bool *yram) 2581 { 2582 *code = *yram = false; 2583 2584 if (UC_RANGE(chip_addx, 1)) { 2585 *code = true; 2586 return UC_OFF(chip_addx); 2587 } else if (X_RANGE_ALL(chip_addx, 1)) { 2588 return X_OFF(chip_addx); 2589 } else if (Y_RANGE_ALL(chip_addx, 1)) { 2590 *yram = true; 2591 return Y_OFF(chip_addx); 2592 } 2593 2594 return INVALID_CHIP_ADDRESS; 2595 } 2596 2597 /* 2598 * Check if the DSP DMA is active 2599 */ 2600 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan) 2601 { 2602 unsigned int dma_chnlstart_reg; 2603 2604 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg); 2605 2606 return ((dma_chnlstart_reg & (1 << 2607 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0); 2608 } 2609 2610 static int dsp_dma_setup_common(struct hda_codec *codec, 2611 unsigned int chip_addx, 2612 unsigned int dma_chan, 2613 unsigned int port_map_mask, 2614 bool ovly) 2615 { 2616 int status = 0; 2617 unsigned int chnl_prop; 2618 unsigned int dsp_addx; 2619 unsigned int active; 2620 bool code, yram; 2621 2622 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n"); 2623 2624 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) { 2625 codec_dbg(codec, "dma chan num invalid\n"); 2626 return -EINVAL; 2627 } 2628 2629 if (dsp_is_dma_active(codec, dma_chan)) { 2630 codec_dbg(codec, "dma already active\n"); 2631 return -EBUSY; 2632 } 2633 2634 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2635 2636 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2637 codec_dbg(codec, "invalid chip addr\n"); 2638 return -ENXIO; 2639 } 2640 2641 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK; 2642 active = 0; 2643 2644 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n"); 2645 2646 if (ovly) { 2647 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET, 2648 &chnl_prop); 2649 2650 if (status < 0) { 2651 codec_dbg(codec, "read CHNLPROP Reg fail\n"); 2652 return status; 2653 } 2654 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n"); 2655 } 2656 2657 if (!code) 2658 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2659 else 2660 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2661 2662 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan)); 2663 2664 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop); 2665 if (status < 0) { 2666 codec_dbg(codec, "write CHNLPROP Reg fail\n"); 2667 return status; 2668 } 2669 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n"); 2670 2671 if (ovly) { 2672 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET, 2673 &active); 2674 2675 if (status < 0) { 2676 codec_dbg(codec, "read ACTIVE Reg fail\n"); 2677 return status; 2678 } 2679 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n"); 2680 } 2681 2682 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) & 2683 DSPDMAC_ACTIVE_AAR_MASK; 2684 2685 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active); 2686 if (status < 0) { 2687 codec_dbg(codec, "write ACTIVE Reg fail\n"); 2688 return status; 2689 } 2690 2691 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n"); 2692 2693 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan), 2694 port_map_mask); 2695 if (status < 0) { 2696 codec_dbg(codec, "write AUDCHSEL Reg fail\n"); 2697 return status; 2698 } 2699 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n"); 2700 2701 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan), 2702 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK); 2703 if (status < 0) { 2704 codec_dbg(codec, "write IRQCNT Reg fail\n"); 2705 return status; 2706 } 2707 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n"); 2708 2709 codec_dbg(codec, 2710 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, " 2711 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n", 2712 chip_addx, dsp_addx, dma_chan, 2713 port_map_mask, chnl_prop, active); 2714 2715 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n"); 2716 2717 return 0; 2718 } 2719 2720 /* 2721 * Setup the DSP DMA per-transfer-specific registers 2722 */ 2723 static int dsp_dma_setup(struct hda_codec *codec, 2724 unsigned int chip_addx, 2725 unsigned int count, 2726 unsigned int dma_chan) 2727 { 2728 int status = 0; 2729 bool code, yram; 2730 unsigned int dsp_addx; 2731 unsigned int addr_field; 2732 unsigned int incr_field; 2733 unsigned int base_cnt; 2734 unsigned int cur_cnt; 2735 unsigned int dma_cfg = 0; 2736 unsigned int adr_ofs = 0; 2737 unsigned int xfr_cnt = 0; 2738 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT - 2739 DSPDMAC_XFRCNT_BCNT_LOBIT + 1); 2740 2741 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n"); 2742 2743 if (count > max_dma_count) { 2744 codec_dbg(codec, "count too big\n"); 2745 return -EINVAL; 2746 } 2747 2748 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2749 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2750 codec_dbg(codec, "invalid chip addr\n"); 2751 return -ENXIO; 2752 } 2753 2754 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n"); 2755 2756 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT; 2757 incr_field = 0; 2758 2759 if (!code) { 2760 addr_field <<= 1; 2761 if (yram) 2762 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT); 2763 2764 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT); 2765 } 2766 2767 dma_cfg = addr_field + incr_field; 2768 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan), 2769 dma_cfg); 2770 if (status < 0) { 2771 codec_dbg(codec, "write DMACFG Reg fail\n"); 2772 return status; 2773 } 2774 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n"); 2775 2776 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT + 2777 (code ? 0 : 1)); 2778 2779 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan), 2780 adr_ofs); 2781 if (status < 0) { 2782 codec_dbg(codec, "write DSPADROFS Reg fail\n"); 2783 return status; 2784 } 2785 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n"); 2786 2787 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT; 2788 2789 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT; 2790 2791 xfr_cnt = base_cnt | cur_cnt; 2792 2793 status = chipio_write(codec, 2794 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt); 2795 if (status < 0) { 2796 codec_dbg(codec, "write XFRCNT Reg fail\n"); 2797 return status; 2798 } 2799 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n"); 2800 2801 codec_dbg(codec, 2802 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, " 2803 "ADROFS=0x%x, XFRCNT=0x%x\n", 2804 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt); 2805 2806 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n"); 2807 2808 return 0; 2809 } 2810 2811 /* 2812 * Start the DSP DMA 2813 */ 2814 static int dsp_dma_start(struct hda_codec *codec, 2815 unsigned int dma_chan, bool ovly) 2816 { 2817 unsigned int reg = 0; 2818 int status = 0; 2819 2820 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n"); 2821 2822 if (ovly) { 2823 status = chipio_read(codec, 2824 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2825 2826 if (status < 0) { 2827 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2828 return status; 2829 } 2830 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n"); 2831 2832 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2833 DSPDMAC_CHNLSTART_DIS_MASK); 2834 } 2835 2836 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2837 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT))); 2838 if (status < 0) { 2839 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2840 return status; 2841 } 2842 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n"); 2843 2844 return status; 2845 } 2846 2847 /* 2848 * Stop the DSP DMA 2849 */ 2850 static int dsp_dma_stop(struct hda_codec *codec, 2851 unsigned int dma_chan, bool ovly) 2852 { 2853 unsigned int reg = 0; 2854 int status = 0; 2855 2856 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n"); 2857 2858 if (ovly) { 2859 status = chipio_read(codec, 2860 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2861 2862 if (status < 0) { 2863 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2864 return status; 2865 } 2866 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n"); 2867 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2868 DSPDMAC_CHNLSTART_DIS_MASK); 2869 } 2870 2871 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2872 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT))); 2873 if (status < 0) { 2874 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2875 return status; 2876 } 2877 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n"); 2878 2879 return status; 2880 } 2881 2882 /** 2883 * dsp_allocate_router_ports - Allocate router ports 2884 * 2885 * @codec: the HDA codec 2886 * @num_chans: number of channels in the stream 2887 * @ports_per_channel: number of ports per channel 2888 * @start_device: start device 2889 * @port_map: pointer to the port list to hold the allocated ports 2890 * 2891 * Returns zero or a negative error code. 2892 */ 2893 static int dsp_allocate_router_ports(struct hda_codec *codec, 2894 unsigned int num_chans, 2895 unsigned int ports_per_channel, 2896 unsigned int start_device, 2897 unsigned int *port_map) 2898 { 2899 int status = 0; 2900 int res; 2901 u8 val; 2902 2903 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2904 if (status < 0) 2905 return status; 2906 2907 val = start_device << 6; 2908 val |= (ports_per_channel - 1) << 4; 2909 val |= num_chans - 1; 2910 2911 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2912 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET, 2913 val); 2914 2915 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2916 VENDOR_CHIPIO_PORT_ALLOC_SET, 2917 MEM_CONNID_DSP); 2918 2919 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2920 if (status < 0) 2921 return status; 2922 2923 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 2924 VENDOR_CHIPIO_PORT_ALLOC_GET, 0); 2925 2926 *port_map = res; 2927 2928 return (res < 0) ? res : 0; 2929 } 2930 2931 /* 2932 * Free router ports 2933 */ 2934 static int dsp_free_router_ports(struct hda_codec *codec) 2935 { 2936 int status = 0; 2937 2938 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2939 if (status < 0) 2940 return status; 2941 2942 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2943 VENDOR_CHIPIO_PORT_FREE_SET, 2944 MEM_CONNID_DSP); 2945 2946 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2947 2948 return status; 2949 } 2950 2951 /* 2952 * Allocate DSP ports for the download stream 2953 */ 2954 static int dsp_allocate_ports(struct hda_codec *codec, 2955 unsigned int num_chans, 2956 unsigned int rate_multi, unsigned int *port_map) 2957 { 2958 int status; 2959 2960 codec_dbg(codec, " dsp_allocate_ports() -- begin\n"); 2961 2962 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2963 codec_dbg(codec, "bad rate multiple\n"); 2964 return -EINVAL; 2965 } 2966 2967 status = dsp_allocate_router_ports(codec, num_chans, 2968 rate_multi, 0, port_map); 2969 2970 codec_dbg(codec, " dsp_allocate_ports() -- complete\n"); 2971 2972 return status; 2973 } 2974 2975 static int dsp_allocate_ports_format(struct hda_codec *codec, 2976 const unsigned short fmt, 2977 unsigned int *port_map) 2978 { 2979 unsigned int num_chans; 2980 2981 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1; 2982 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1; 2983 unsigned int rate_multi = sample_rate_mul / sample_rate_div; 2984 2985 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2986 codec_dbg(codec, "bad rate multiple\n"); 2987 return -EINVAL; 2988 } 2989 2990 num_chans = get_hdafmt_chs(fmt) + 1; 2991 2992 return dsp_allocate_ports(codec, num_chans, rate_multi, port_map); 2993 } 2994 2995 /* 2996 * free DSP ports 2997 */ 2998 static int dsp_free_ports(struct hda_codec *codec) 2999 { 3000 int status; 3001 3002 codec_dbg(codec, " dsp_free_ports() -- begin\n"); 3003 3004 status = dsp_free_router_ports(codec); 3005 if (status < 0) { 3006 codec_dbg(codec, "free router ports fail\n"); 3007 return status; 3008 } 3009 codec_dbg(codec, " dsp_free_ports() -- complete\n"); 3010 3011 return status; 3012 } 3013 3014 /* 3015 * HDA DMA engine stuffs for DSP code download 3016 */ 3017 struct dma_engine { 3018 struct hda_codec *codec; 3019 unsigned short m_converter_format; 3020 struct snd_dma_buffer *dmab; 3021 unsigned int buf_size; 3022 }; 3023 3024 3025 enum dma_state { 3026 DMA_STATE_STOP = 0, 3027 DMA_STATE_RUN = 1 3028 }; 3029 3030 static int dma_convert_to_hda_format(struct hda_codec *codec, 3031 unsigned int sample_rate, 3032 unsigned short channels, 3033 unsigned short *hda_format) 3034 { 3035 unsigned int format_val; 3036 3037 format_val = snd_hdac_calc_stream_format(sample_rate, 3038 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0); 3039 3040 if (hda_format) 3041 *hda_format = (unsigned short)format_val; 3042 3043 return 0; 3044 } 3045 3046 /* 3047 * Reset DMA for DSP download 3048 */ 3049 static int dma_reset(struct dma_engine *dma) 3050 { 3051 struct hda_codec *codec = dma->codec; 3052 struct ca0132_spec *spec = codec->spec; 3053 int status; 3054 3055 if (dma->dmab->area) 3056 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab); 3057 3058 status = snd_hda_codec_load_dsp_prepare(codec, 3059 dma->m_converter_format, 3060 dma->buf_size, 3061 dma->dmab); 3062 if (status < 0) 3063 return status; 3064 spec->dsp_stream_id = status; 3065 return 0; 3066 } 3067 3068 static int dma_set_state(struct dma_engine *dma, enum dma_state state) 3069 { 3070 bool cmd; 3071 3072 switch (state) { 3073 case DMA_STATE_STOP: 3074 cmd = false; 3075 break; 3076 case DMA_STATE_RUN: 3077 cmd = true; 3078 break; 3079 default: 3080 return 0; 3081 } 3082 3083 snd_hda_codec_load_dsp_trigger(dma->codec, cmd); 3084 return 0; 3085 } 3086 3087 static unsigned int dma_get_buffer_size(struct dma_engine *dma) 3088 { 3089 return dma->dmab->bytes; 3090 } 3091 3092 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma) 3093 { 3094 return dma->dmab->area; 3095 } 3096 3097 static int dma_xfer(struct dma_engine *dma, 3098 const unsigned int *data, 3099 unsigned int count) 3100 { 3101 memcpy(dma->dmab->area, data, count); 3102 return 0; 3103 } 3104 3105 static void dma_get_converter_format( 3106 struct dma_engine *dma, 3107 unsigned short *format) 3108 { 3109 if (format) 3110 *format = dma->m_converter_format; 3111 } 3112 3113 static unsigned int dma_get_stream_id(struct dma_engine *dma) 3114 { 3115 struct ca0132_spec *spec = dma->codec->spec; 3116 3117 return spec->dsp_stream_id; 3118 } 3119 3120 struct dsp_image_seg { 3121 u32 magic; 3122 u32 chip_addr; 3123 u32 count; 3124 u32 data[]; 3125 }; 3126 3127 static const u32 g_magic_value = 0x4c46584d; 3128 static const u32 g_chip_addr_magic_value = 0xFFFFFF01; 3129 3130 static bool is_valid(const struct dsp_image_seg *p) 3131 { 3132 return p->magic == g_magic_value; 3133 } 3134 3135 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p) 3136 { 3137 return g_chip_addr_magic_value == p->chip_addr; 3138 } 3139 3140 static bool is_last(const struct dsp_image_seg *p) 3141 { 3142 return p->count == 0; 3143 } 3144 3145 static size_t dsp_sizeof(const struct dsp_image_seg *p) 3146 { 3147 return struct_size(p, data, p->count); 3148 } 3149 3150 static const struct dsp_image_seg *get_next_seg_ptr( 3151 const struct dsp_image_seg *p) 3152 { 3153 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p)); 3154 } 3155 3156 /* 3157 * CA0132 chip DSP transfer stuffs. For DSP download. 3158 */ 3159 #define INVALID_DMA_CHANNEL (~0U) 3160 3161 /* 3162 * Program a list of address/data pairs via the ChipIO widget. 3163 * The segment data is in the format of successive pairs of words. 3164 * These are repeated as indicated by the segment's count field. 3165 */ 3166 static int dspxfr_hci_write(struct hda_codec *codec, 3167 const struct dsp_image_seg *fls) 3168 { 3169 int status; 3170 const u32 *data; 3171 unsigned int count; 3172 3173 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) { 3174 codec_dbg(codec, "hci_write invalid params\n"); 3175 return -EINVAL; 3176 } 3177 3178 count = fls->count; 3179 data = (u32 *)(fls->data); 3180 while (count >= 2) { 3181 status = chipio_write(codec, data[0], data[1]); 3182 if (status < 0) { 3183 codec_dbg(codec, "hci_write chipio failed\n"); 3184 return status; 3185 } 3186 count -= 2; 3187 data += 2; 3188 } 3189 return 0; 3190 } 3191 3192 /** 3193 * dspxfr_one_seg - Write a block of data into DSP code or data RAM using pre-allocated DMA engine. 3194 * 3195 * @codec: the HDA codec 3196 * @fls: pointer to a fast load image 3197 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3198 * no relocation 3199 * @dma_engine: pointer to DMA engine to be used for DSP download 3200 * @dma_chan: The number of DMA channels used for DSP download 3201 * @port_map_mask: port mapping 3202 * @ovly: TRUE if overlay format is required 3203 * 3204 * Returns zero or a negative error code. 3205 */ 3206 static int dspxfr_one_seg(struct hda_codec *codec, 3207 const struct dsp_image_seg *fls, 3208 unsigned int reloc, 3209 struct dma_engine *dma_engine, 3210 unsigned int dma_chan, 3211 unsigned int port_map_mask, 3212 bool ovly) 3213 { 3214 int status = 0; 3215 bool comm_dma_setup_done = false; 3216 const unsigned int *data; 3217 unsigned int chip_addx; 3218 unsigned int words_to_write; 3219 unsigned int buffer_size_words; 3220 unsigned char *buffer_addx; 3221 unsigned short hda_format; 3222 unsigned int sample_rate_div; 3223 unsigned int sample_rate_mul; 3224 unsigned int num_chans; 3225 unsigned int hda_frame_size_words; 3226 unsigned int remainder_words; 3227 const u32 *data_remainder; 3228 u32 chip_addx_remainder; 3229 unsigned int run_size_words; 3230 const struct dsp_image_seg *hci_write = NULL; 3231 unsigned long timeout; 3232 bool dma_active; 3233 3234 if (fls == NULL) 3235 return -EINVAL; 3236 if (is_hci_prog_list_seg(fls)) { 3237 hci_write = fls; 3238 fls = get_next_seg_ptr(fls); 3239 } 3240 3241 if (hci_write && (!fls || is_last(fls))) { 3242 codec_dbg(codec, "hci_write\n"); 3243 return dspxfr_hci_write(codec, hci_write); 3244 } 3245 3246 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) { 3247 codec_dbg(codec, "Invalid Params\n"); 3248 return -EINVAL; 3249 } 3250 3251 data = fls->data; 3252 chip_addx = fls->chip_addr; 3253 words_to_write = fls->count; 3254 3255 if (!words_to_write) 3256 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0; 3257 if (reloc) 3258 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2); 3259 3260 if (!UC_RANGE(chip_addx, words_to_write) && 3261 !X_RANGE_ALL(chip_addx, words_to_write) && 3262 !Y_RANGE_ALL(chip_addx, words_to_write)) { 3263 codec_dbg(codec, "Invalid chip_addx Params\n"); 3264 return -EINVAL; 3265 } 3266 3267 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) / 3268 sizeof(u32); 3269 3270 buffer_addx = dma_get_buffer_addr(dma_engine); 3271 3272 if (buffer_addx == NULL) { 3273 codec_dbg(codec, "dma_engine buffer NULL\n"); 3274 return -EINVAL; 3275 } 3276 3277 dma_get_converter_format(dma_engine, &hda_format); 3278 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1; 3279 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1; 3280 num_chans = get_hdafmt_chs(hda_format) + 1; 3281 3282 hda_frame_size_words = ((sample_rate_div == 0) ? 0 : 3283 (num_chans * sample_rate_mul / sample_rate_div)); 3284 3285 if (hda_frame_size_words == 0) { 3286 codec_dbg(codec, "frmsz zero\n"); 3287 return -EINVAL; 3288 } 3289 3290 buffer_size_words = min(buffer_size_words, 3291 (unsigned int)(UC_RANGE(chip_addx, 1) ? 3292 65536 : 32768)); 3293 buffer_size_words -= buffer_size_words % hda_frame_size_words; 3294 codec_dbg(codec, 3295 "chpadr=0x%08x frmsz=%u nchan=%u " 3296 "rate_mul=%u div=%u bufsz=%u\n", 3297 chip_addx, hda_frame_size_words, num_chans, 3298 sample_rate_mul, sample_rate_div, buffer_size_words); 3299 3300 if (buffer_size_words < hda_frame_size_words) { 3301 codec_dbg(codec, "dspxfr_one_seg:failed\n"); 3302 return -EINVAL; 3303 } 3304 3305 remainder_words = words_to_write % hda_frame_size_words; 3306 data_remainder = data; 3307 chip_addx_remainder = chip_addx; 3308 3309 data += remainder_words; 3310 chip_addx += remainder_words*sizeof(u32); 3311 words_to_write -= remainder_words; 3312 3313 while (words_to_write != 0) { 3314 run_size_words = min(buffer_size_words, words_to_write); 3315 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n", 3316 words_to_write, run_size_words, remainder_words); 3317 dma_xfer(dma_engine, data, run_size_words*sizeof(u32)); 3318 if (!comm_dma_setup_done) { 3319 status = dsp_dma_stop(codec, dma_chan, ovly); 3320 if (status < 0) 3321 return status; 3322 status = dsp_dma_setup_common(codec, chip_addx, 3323 dma_chan, port_map_mask, ovly); 3324 if (status < 0) 3325 return status; 3326 comm_dma_setup_done = true; 3327 } 3328 3329 status = dsp_dma_setup(codec, chip_addx, 3330 run_size_words, dma_chan); 3331 if (status < 0) 3332 return status; 3333 status = dsp_dma_start(codec, dma_chan, ovly); 3334 if (status < 0) 3335 return status; 3336 if (!dsp_is_dma_active(codec, dma_chan)) { 3337 codec_dbg(codec, "dspxfr:DMA did not start\n"); 3338 return -EIO; 3339 } 3340 status = dma_set_state(dma_engine, DMA_STATE_RUN); 3341 if (status < 0) 3342 return status; 3343 if (remainder_words != 0) { 3344 status = chipio_write_multiple(codec, 3345 chip_addx_remainder, 3346 data_remainder, 3347 remainder_words); 3348 if (status < 0) 3349 return status; 3350 remainder_words = 0; 3351 } 3352 if (hci_write) { 3353 status = dspxfr_hci_write(codec, hci_write); 3354 if (status < 0) 3355 return status; 3356 hci_write = NULL; 3357 } 3358 3359 timeout = jiffies + msecs_to_jiffies(2000); 3360 do { 3361 dma_active = dsp_is_dma_active(codec, dma_chan); 3362 if (!dma_active) 3363 break; 3364 msleep(20); 3365 } while (time_before(jiffies, timeout)); 3366 if (dma_active) 3367 break; 3368 3369 codec_dbg(codec, "+++++ DMA complete\n"); 3370 dma_set_state(dma_engine, DMA_STATE_STOP); 3371 status = dma_reset(dma_engine); 3372 3373 if (status < 0) 3374 return status; 3375 3376 data += run_size_words; 3377 chip_addx += run_size_words*sizeof(u32); 3378 words_to_write -= run_size_words; 3379 } 3380 3381 if (remainder_words != 0) { 3382 status = chipio_write_multiple(codec, chip_addx_remainder, 3383 data_remainder, remainder_words); 3384 } 3385 3386 return status; 3387 } 3388 3389 /** 3390 * dspxfr_image - Write the entire DSP image of a DSP code/data overlay to DSP memories 3391 * 3392 * @codec: the HDA codec 3393 * @fls_data: pointer to a fast load image 3394 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3395 * no relocation 3396 * @sample_rate: sampling rate of the stream used for DSP download 3397 * @channels: channels of the stream used for DSP download 3398 * @ovly: TRUE if overlay format is required 3399 * 3400 * Returns zero or a negative error code. 3401 */ 3402 static int dspxfr_image(struct hda_codec *codec, 3403 const struct dsp_image_seg *fls_data, 3404 unsigned int reloc, 3405 unsigned int sample_rate, 3406 unsigned short channels, 3407 bool ovly) 3408 { 3409 struct ca0132_spec *spec = codec->spec; 3410 int status; 3411 unsigned short hda_format = 0; 3412 unsigned int response; 3413 unsigned char stream_id = 0; 3414 struct dma_engine *dma_engine; 3415 unsigned int dma_chan; 3416 unsigned int port_map_mask; 3417 3418 if (fls_data == NULL) 3419 return -EINVAL; 3420 3421 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL); 3422 if (!dma_engine) 3423 return -ENOMEM; 3424 3425 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL); 3426 if (!dma_engine->dmab) { 3427 kfree(dma_engine); 3428 return -ENOMEM; 3429 } 3430 3431 dma_engine->codec = codec; 3432 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format); 3433 dma_engine->m_converter_format = hda_format; 3434 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY : 3435 DSP_DMA_WRITE_BUFLEN_INIT) * 2; 3436 3437 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0; 3438 3439 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL, 3440 hda_format, &response); 3441 3442 if (status < 0) { 3443 codec_dbg(codec, "set converter format fail\n"); 3444 goto exit; 3445 } 3446 3447 status = snd_hda_codec_load_dsp_prepare(codec, 3448 dma_engine->m_converter_format, 3449 dma_engine->buf_size, 3450 dma_engine->dmab); 3451 if (status < 0) 3452 goto exit; 3453 spec->dsp_stream_id = status; 3454 3455 if (ovly) { 3456 status = dspio_alloc_dma_chan(codec, &dma_chan); 3457 if (status < 0) { 3458 codec_dbg(codec, "alloc dmachan fail\n"); 3459 dma_chan = INVALID_DMA_CHANNEL; 3460 goto exit; 3461 } 3462 } 3463 3464 port_map_mask = 0; 3465 status = dsp_allocate_ports_format(codec, hda_format, 3466 &port_map_mask); 3467 if (status < 0) { 3468 codec_dbg(codec, "alloc ports fail\n"); 3469 goto exit; 3470 } 3471 3472 stream_id = dma_get_stream_id(dma_engine); 3473 status = codec_set_converter_stream_channel(codec, 3474 WIDGET_CHIP_CTRL, stream_id, 0, &response); 3475 if (status < 0) { 3476 codec_dbg(codec, "set stream chan fail\n"); 3477 goto exit; 3478 } 3479 3480 while ((fls_data != NULL) && !is_last(fls_data)) { 3481 if (!is_valid(fls_data)) { 3482 codec_dbg(codec, "FLS check fail\n"); 3483 status = -EINVAL; 3484 goto exit; 3485 } 3486 status = dspxfr_one_seg(codec, fls_data, reloc, 3487 dma_engine, dma_chan, 3488 port_map_mask, ovly); 3489 if (status < 0) 3490 break; 3491 3492 if (is_hci_prog_list_seg(fls_data)) 3493 fls_data = get_next_seg_ptr(fls_data); 3494 3495 if ((fls_data != NULL) && !is_last(fls_data)) 3496 fls_data = get_next_seg_ptr(fls_data); 3497 } 3498 3499 if (port_map_mask != 0) 3500 status = dsp_free_ports(codec); 3501 3502 if (status < 0) 3503 goto exit; 3504 3505 status = codec_set_converter_stream_channel(codec, 3506 WIDGET_CHIP_CTRL, 0, 0, &response); 3507 3508 exit: 3509 if (ovly && (dma_chan != INVALID_DMA_CHANNEL)) 3510 dspio_free_dma_chan(codec, dma_chan); 3511 3512 if (dma_engine->dmab->area) 3513 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab); 3514 kfree(dma_engine->dmab); 3515 kfree(dma_engine); 3516 3517 return status; 3518 } 3519 3520 /* 3521 * CA0132 DSP download stuffs. 3522 */ 3523 static void dspload_post_setup(struct hda_codec *codec) 3524 { 3525 struct ca0132_spec *spec = codec->spec; 3526 codec_dbg(codec, "---- dspload_post_setup ------\n"); 3527 if (!ca0132_use_alt_functions(spec)) { 3528 /*set DSP speaker to 2.0 configuration*/ 3529 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080); 3530 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000); 3531 3532 /*update write pointer*/ 3533 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002); 3534 } 3535 } 3536 3537 /** 3538 * dspload_image - Download DSP from a DSP Image Fast Load structure. 3539 * 3540 * @codec: the HDA codec 3541 * @fls: pointer to a fast load image 3542 * @ovly: TRUE if overlay format is required 3543 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3544 * no relocation 3545 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE 3546 * @router_chans: number of audio router channels to be allocated (0 means use 3547 * internal defaults; max is 32) 3548 * 3549 * Download DSP from a DSP Image Fast Load structure. This structure is a 3550 * linear, non-constant sized element array of structures, each of which 3551 * contain the count of the data to be loaded, the data itself, and the 3552 * corresponding starting chip address of the starting data location. 3553 * Returns zero or a negative error code. 3554 */ 3555 static int dspload_image(struct hda_codec *codec, 3556 const struct dsp_image_seg *fls, 3557 bool ovly, 3558 unsigned int reloc, 3559 bool autostart, 3560 int router_chans) 3561 { 3562 int status = 0; 3563 unsigned int sample_rate; 3564 unsigned short channels; 3565 3566 codec_dbg(codec, "---- dspload_image begin ------\n"); 3567 if (router_chans == 0) { 3568 if (!ovly) 3569 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS; 3570 else 3571 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS; 3572 } 3573 3574 sample_rate = 48000; 3575 channels = (unsigned short)router_chans; 3576 3577 while (channels > 16) { 3578 sample_rate *= 2; 3579 channels /= 2; 3580 } 3581 3582 do { 3583 codec_dbg(codec, "Ready to program DMA\n"); 3584 if (!ovly) 3585 status = dsp_reset(codec); 3586 3587 if (status < 0) 3588 break; 3589 3590 codec_dbg(codec, "dsp_reset() complete\n"); 3591 status = dspxfr_image(codec, fls, reloc, sample_rate, channels, 3592 ovly); 3593 3594 if (status < 0) 3595 break; 3596 3597 codec_dbg(codec, "dspxfr_image() complete\n"); 3598 if (autostart && !ovly) { 3599 dspload_post_setup(codec); 3600 status = dsp_set_run_state(codec); 3601 } 3602 3603 codec_dbg(codec, "LOAD FINISHED\n"); 3604 } while (0); 3605 3606 return status; 3607 } 3608 3609 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 3610 static bool dspload_is_loaded(struct hda_codec *codec) 3611 { 3612 unsigned int data = 0; 3613 int status = 0; 3614 3615 status = chipio_read(codec, 0x40004, &data); 3616 if ((status < 0) || (data != 1)) 3617 return false; 3618 3619 return true; 3620 } 3621 #else 3622 #define dspload_is_loaded(codec) false 3623 #endif 3624 3625 static bool dspload_wait_loaded(struct hda_codec *codec) 3626 { 3627 unsigned long timeout = jiffies + msecs_to_jiffies(2000); 3628 3629 do { 3630 if (dspload_is_loaded(codec)) { 3631 codec_info(codec, "ca0132 DSP downloaded and running\n"); 3632 return true; 3633 } 3634 msleep(20); 3635 } while (time_before(jiffies, timeout)); 3636 3637 codec_err(codec, "ca0132 failed to download DSP\n"); 3638 return false; 3639 } 3640 3641 /* 3642 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e 3643 * based cards, and has a second mmio region, region2, that's used for special 3644 * commands. 3645 */ 3646 3647 /* 3648 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5) 3649 * the mmio address 0x320 is used to set GPIO pins. The format for the data 3650 * The first eight bits are just the number of the pin. So far, I've only seen 3651 * this number go to 7. 3652 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value 3653 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and 3654 * then off to send that bit. 3655 */ 3656 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin, 3657 bool enable) 3658 { 3659 struct ca0132_spec *spec = codec->spec; 3660 unsigned short gpio_data; 3661 3662 gpio_data = gpio_pin & 0xF; 3663 gpio_data |= ((enable << 8) & 0x100); 3664 3665 writew(gpio_data, spec->mem_base + 0x320); 3666 } 3667 3668 /* 3669 * Special pci region2 commands that are only used by the AE-5. They follow 3670 * a set format, and require reads at certain points to seemingly 'clear' 3671 * the response data. My first tests didn't do these reads, and would cause 3672 * the card to get locked up until the memory was read. These commands 3673 * seem to work with three distinct values that I've taken to calling group, 3674 * target-id, and value. 3675 */ 3676 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group, 3677 unsigned int target, unsigned int value) 3678 { 3679 struct ca0132_spec *spec = codec->spec; 3680 unsigned int write_val; 3681 3682 writel(0x0000007e, spec->mem_base + 0x210); 3683 readl(spec->mem_base + 0x210); 3684 writel(0x0000005a, spec->mem_base + 0x210); 3685 readl(spec->mem_base + 0x210); 3686 readl(spec->mem_base + 0x210); 3687 3688 writel(0x00800005, spec->mem_base + 0x20c); 3689 writel(group, spec->mem_base + 0x804); 3690 3691 writel(0x00800005, spec->mem_base + 0x20c); 3692 write_val = (target & 0xff); 3693 write_val |= (value << 8); 3694 3695 3696 writel(write_val, spec->mem_base + 0x204); 3697 /* 3698 * Need delay here or else it goes too fast and works inconsistently. 3699 */ 3700 msleep(20); 3701 3702 readl(spec->mem_base + 0x860); 3703 readl(spec->mem_base + 0x854); 3704 readl(spec->mem_base + 0x840); 3705 3706 writel(0x00800004, spec->mem_base + 0x20c); 3707 writel(0x00000000, spec->mem_base + 0x210); 3708 readl(spec->mem_base + 0x210); 3709 readl(spec->mem_base + 0x210); 3710 } 3711 3712 /* 3713 * This second type of command is used for setting the sound filter type. 3714 */ 3715 static void ca0113_mmio_command_set_type2(struct hda_codec *codec, 3716 unsigned int group, unsigned int target, unsigned int value) 3717 { 3718 struct ca0132_spec *spec = codec->spec; 3719 unsigned int write_val; 3720 3721 writel(0x0000007e, spec->mem_base + 0x210); 3722 readl(spec->mem_base + 0x210); 3723 writel(0x0000005a, spec->mem_base + 0x210); 3724 readl(spec->mem_base + 0x210); 3725 readl(spec->mem_base + 0x210); 3726 3727 writel(0x00800003, spec->mem_base + 0x20c); 3728 writel(group, spec->mem_base + 0x804); 3729 3730 writel(0x00800005, spec->mem_base + 0x20c); 3731 write_val = (target & 0xff); 3732 write_val |= (value << 8); 3733 3734 3735 writel(write_val, spec->mem_base + 0x204); 3736 msleep(20); 3737 readl(spec->mem_base + 0x860); 3738 readl(spec->mem_base + 0x854); 3739 readl(spec->mem_base + 0x840); 3740 3741 writel(0x00800004, spec->mem_base + 0x20c); 3742 writel(0x00000000, spec->mem_base + 0x210); 3743 readl(spec->mem_base + 0x210); 3744 readl(spec->mem_base + 0x210); 3745 } 3746 3747 /* 3748 * Setup GPIO for the other variants of Core3D. 3749 */ 3750 3751 /* 3752 * Sets up the GPIO pins so that they are discoverable. If this isn't done, 3753 * the card shows as having no GPIO pins. 3754 */ 3755 static void ca0132_gpio_init(struct hda_codec *codec) 3756 { 3757 struct ca0132_spec *spec = codec->spec; 3758 3759 switch (ca0132_quirk(spec)) { 3760 case QUIRK_SBZ: 3761 case QUIRK_AE5: 3762 case QUIRK_AE7: 3763 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3764 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 3765 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23); 3766 break; 3767 case QUIRK_R3DI: 3768 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3769 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B); 3770 break; 3771 default: 3772 break; 3773 } 3774 3775 } 3776 3777 /* Sets the GPIO for audio output. */ 3778 static void ca0132_gpio_setup(struct hda_codec *codec) 3779 { 3780 struct ca0132_spec *spec = codec->spec; 3781 3782 switch (ca0132_quirk(spec)) { 3783 case QUIRK_SBZ: 3784 snd_hda_codec_write(codec, 0x01, 0, 3785 AC_VERB_SET_GPIO_DIRECTION, 0x07); 3786 snd_hda_codec_write(codec, 0x01, 0, 3787 AC_VERB_SET_GPIO_MASK, 0x07); 3788 snd_hda_codec_write(codec, 0x01, 0, 3789 AC_VERB_SET_GPIO_DATA, 0x04); 3790 snd_hda_codec_write(codec, 0x01, 0, 3791 AC_VERB_SET_GPIO_DATA, 0x06); 3792 break; 3793 case QUIRK_R3DI: 3794 snd_hda_codec_write(codec, 0x01, 0, 3795 AC_VERB_SET_GPIO_DIRECTION, 0x1E); 3796 snd_hda_codec_write(codec, 0x01, 0, 3797 AC_VERB_SET_GPIO_MASK, 0x1F); 3798 snd_hda_codec_write(codec, 0x01, 0, 3799 AC_VERB_SET_GPIO_DATA, 0x0C); 3800 break; 3801 default: 3802 break; 3803 } 3804 } 3805 3806 /* 3807 * GPIO control functions for the Recon3D integrated. 3808 */ 3809 3810 enum r3di_gpio_bit { 3811 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */ 3812 R3DI_MIC_SELECT_BIT = 1, 3813 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */ 3814 R3DI_OUT_SELECT_BIT = 2, 3815 /* 3816 * I dunno what this actually does, but it stays on until the dsp 3817 * is downloaded. 3818 */ 3819 R3DI_GPIO_DSP_DOWNLOADING = 3, 3820 /* 3821 * Same as above, no clue what it does, but it comes on after the dsp 3822 * is downloaded. 3823 */ 3824 R3DI_GPIO_DSP_DOWNLOADED = 4 3825 }; 3826 3827 enum r3di_mic_select { 3828 /* Set GPIO bit 1 to 0 for rear mic */ 3829 R3DI_REAR_MIC = 0, 3830 /* Set GPIO bit 1 to 1 for front microphone*/ 3831 R3DI_FRONT_MIC = 1 3832 }; 3833 3834 enum r3di_out_select { 3835 /* Set GPIO bit 2 to 0 for headphone */ 3836 R3DI_HEADPHONE_OUT = 0, 3837 /* Set GPIO bit 2 to 1 for speaker */ 3838 R3DI_LINE_OUT = 1 3839 }; 3840 enum r3di_dsp_status { 3841 /* Set GPIO bit 3 to 1 until DSP is downloaded */ 3842 R3DI_DSP_DOWNLOADING = 0, 3843 /* Set GPIO bit 4 to 1 once DSP is downloaded */ 3844 R3DI_DSP_DOWNLOADED = 1 3845 }; 3846 3847 3848 static void r3di_gpio_mic_set(struct hda_codec *codec, 3849 enum r3di_mic_select cur_mic) 3850 { 3851 unsigned int cur_gpio; 3852 3853 /* Get the current GPIO Data setup */ 3854 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3855 3856 switch (cur_mic) { 3857 case R3DI_REAR_MIC: 3858 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT); 3859 break; 3860 case R3DI_FRONT_MIC: 3861 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT); 3862 break; 3863 } 3864 snd_hda_codec_write(codec, codec->core.afg, 0, 3865 AC_VERB_SET_GPIO_DATA, cur_gpio); 3866 } 3867 3868 static void r3di_gpio_dsp_status_set(struct hda_codec *codec, 3869 enum r3di_dsp_status dsp_status) 3870 { 3871 unsigned int cur_gpio; 3872 3873 /* Get the current GPIO Data setup */ 3874 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3875 3876 switch (dsp_status) { 3877 case R3DI_DSP_DOWNLOADING: 3878 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING); 3879 snd_hda_codec_write(codec, codec->core.afg, 0, 3880 AC_VERB_SET_GPIO_DATA, cur_gpio); 3881 break; 3882 case R3DI_DSP_DOWNLOADED: 3883 /* Set DOWNLOADING bit to 0. */ 3884 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING); 3885 3886 snd_hda_codec_write(codec, codec->core.afg, 0, 3887 AC_VERB_SET_GPIO_DATA, cur_gpio); 3888 3889 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED); 3890 break; 3891 } 3892 3893 snd_hda_codec_write(codec, codec->core.afg, 0, 3894 AC_VERB_SET_GPIO_DATA, cur_gpio); 3895 } 3896 3897 /* 3898 * PCM callbacks 3899 */ 3900 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3901 struct hda_codec *codec, 3902 unsigned int stream_tag, 3903 unsigned int format, 3904 struct snd_pcm_substream *substream) 3905 { 3906 struct ca0132_spec *spec = codec->spec; 3907 3908 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format); 3909 3910 return 0; 3911 } 3912 3913 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3914 struct hda_codec *codec, 3915 struct snd_pcm_substream *substream) 3916 { 3917 struct ca0132_spec *spec = codec->spec; 3918 3919 if (spec->dsp_state == DSP_DOWNLOADING) 3920 return 0; 3921 3922 /*If Playback effects are on, allow stream some time to flush 3923 *effects tail*/ 3924 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 3925 msleep(50); 3926 3927 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 3928 3929 return 0; 3930 } 3931 3932 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info, 3933 struct hda_codec *codec, 3934 struct snd_pcm_substream *substream) 3935 { 3936 struct ca0132_spec *spec = codec->spec; 3937 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY; 3938 struct snd_pcm_runtime *runtime = substream->runtime; 3939 3940 if (spec->dsp_state != DSP_DOWNLOADED) 3941 return 0; 3942 3943 /* Add latency if playback enhancement and either effect is enabled. */ 3944 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) { 3945 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) || 3946 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID])) 3947 latency += DSP_PLAY_ENHANCEMENT_LATENCY; 3948 } 3949 3950 /* Applying Speaker EQ adds latency as well. */ 3951 if (spec->cur_out_type == SPEAKER_OUT) 3952 latency += DSP_SPEAKER_OUT_LATENCY; 3953 3954 return (latency * runtime->rate) / 1000; 3955 } 3956 3957 /* 3958 * Digital out 3959 */ 3960 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo, 3961 struct hda_codec *codec, 3962 struct snd_pcm_substream *substream) 3963 { 3964 struct ca0132_spec *spec = codec->spec; 3965 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3966 } 3967 3968 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3969 struct hda_codec *codec, 3970 unsigned int stream_tag, 3971 unsigned int format, 3972 struct snd_pcm_substream *substream) 3973 { 3974 struct ca0132_spec *spec = codec->spec; 3975 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3976 stream_tag, format, substream); 3977 } 3978 3979 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3980 struct hda_codec *codec, 3981 struct snd_pcm_substream *substream) 3982 { 3983 struct ca0132_spec *spec = codec->spec; 3984 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout); 3985 } 3986 3987 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo, 3988 struct hda_codec *codec, 3989 struct snd_pcm_substream *substream) 3990 { 3991 struct ca0132_spec *spec = codec->spec; 3992 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3993 } 3994 3995 /* 3996 * Analog capture 3997 */ 3998 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo, 3999 struct hda_codec *codec, 4000 unsigned int stream_tag, 4001 unsigned int format, 4002 struct snd_pcm_substream *substream) 4003 { 4004 snd_hda_codec_setup_stream(codec, hinfo->nid, 4005 stream_tag, 0, format); 4006 4007 return 0; 4008 } 4009 4010 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo, 4011 struct hda_codec *codec, 4012 struct snd_pcm_substream *substream) 4013 { 4014 struct ca0132_spec *spec = codec->spec; 4015 4016 if (spec->dsp_state == DSP_DOWNLOADING) 4017 return 0; 4018 4019 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 4020 return 0; 4021 } 4022 4023 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info, 4024 struct hda_codec *codec, 4025 struct snd_pcm_substream *substream) 4026 { 4027 struct ca0132_spec *spec = codec->spec; 4028 unsigned int latency = DSP_CAPTURE_INIT_LATENCY; 4029 struct snd_pcm_runtime *runtime = substream->runtime; 4030 4031 if (spec->dsp_state != DSP_DOWNLOADED) 4032 return 0; 4033 4034 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 4035 latency += DSP_CRYSTAL_VOICE_LATENCY; 4036 4037 return (latency * runtime->rate) / 1000; 4038 } 4039 4040 /* 4041 * Controls stuffs. 4042 */ 4043 4044 /* 4045 * Mixer controls helpers. 4046 */ 4047 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \ 4048 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4049 .name = xname, \ 4050 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 4051 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 4052 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 4053 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 4054 .info = ca0132_volume_info, \ 4055 .get = ca0132_volume_get, \ 4056 .put = ca0132_volume_put, \ 4057 .tlv = { .c = ca0132_volume_tlv }, \ 4058 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 4059 4060 /* 4061 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the 4062 * volume put, which is used for setting the DSP volume. This was done because 4063 * the ca0132 functions were taking too much time and causing lag. 4064 */ 4065 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \ 4066 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4067 .name = xname, \ 4068 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 4069 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 4070 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 4071 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 4072 .info = snd_hda_mixer_amp_volume_info, \ 4073 .get = snd_hda_mixer_amp_volume_get, \ 4074 .put = ca0132_alt_volume_put, \ 4075 .tlv = { .c = snd_hda_mixer_amp_tlv }, \ 4076 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 4077 4078 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \ 4079 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4080 .name = xname, \ 4081 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 4082 .info = snd_hda_mixer_amp_switch_info, \ 4083 .get = ca0132_switch_get, \ 4084 .put = ca0132_switch_put, \ 4085 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 4086 4087 /* stereo */ 4088 #define CA0132_CODEC_VOL(xname, nid, dir) \ 4089 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir) 4090 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \ 4091 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir) 4092 #define CA0132_CODEC_MUTE(xname, nid, dir) \ 4093 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir) 4094 4095 /* lookup tables */ 4096 /* 4097 * Lookup table with decibel values for the DSP. When volume is changed in 4098 * Windows, the DSP is also sent the dB value in floating point. In Windows, 4099 * these values have decimal points, probably because the Windows driver 4100 * actually uses floating point. We can't here, so I made a lookup table of 4101 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the 4102 * DAC's, and 9 is the maximum. 4103 */ 4104 static const unsigned int float_vol_db_lookup[] = { 4105 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000, 4106 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000, 4107 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000, 4108 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000, 4109 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000, 4110 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000, 4111 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000, 4112 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000, 4113 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000, 4114 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000, 4115 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000, 4116 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 4117 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 4118 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 4119 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 4120 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 4121 0x40C00000, 0x40E00000, 0x41000000, 0x41100000 4122 }; 4123 4124 /* 4125 * This table counts from float 0 to 1 in increments of .01, which is 4126 * useful for a few different sliders. 4127 */ 4128 static const unsigned int float_zero_to_one_lookup[] = { 4129 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 4130 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 4131 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 4132 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 4133 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 4134 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 4135 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 4136 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 4137 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 4138 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 4139 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 4140 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 4141 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 4142 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 4143 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 4144 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 4145 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 4146 }; 4147 4148 /* 4149 * This table counts from float 10 to 1000, which is the range of the x-bass 4150 * crossover slider in Windows. 4151 */ 4152 static const unsigned int float_xbass_xover_lookup[] = { 4153 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000, 4154 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000, 4155 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000, 4156 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000, 4157 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000, 4158 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000, 4159 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000, 4160 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000, 4161 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000, 4162 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000, 4163 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000, 4164 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000, 4165 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000, 4166 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000, 4167 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000, 4168 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000, 4169 0x44728000, 0x44750000, 0x44778000, 0x447A0000 4170 }; 4171 4172 /* The following are for tuning of products */ 4173 #ifdef ENABLE_TUNING_CONTROLS 4174 4175 static const unsigned int voice_focus_vals_lookup[] = { 4176 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000, 4177 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000, 4178 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000, 4179 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000, 4180 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000, 4181 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000, 4182 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000, 4183 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000, 4184 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000, 4185 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000, 4186 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000, 4187 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000, 4188 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000, 4189 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000, 4190 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000, 4191 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000, 4192 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000, 4193 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000, 4194 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000, 4195 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000, 4196 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000, 4197 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000, 4198 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000, 4199 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000, 4200 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000, 4201 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000, 4202 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000 4203 }; 4204 4205 static const unsigned int mic_svm_vals_lookup[] = { 4206 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 4207 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 4208 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 4209 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 4210 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 4211 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 4212 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 4213 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 4214 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 4215 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 4216 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 4217 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 4218 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 4219 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 4220 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 4221 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 4222 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 4223 }; 4224 4225 static const unsigned int equalizer_vals_lookup[] = { 4226 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 4227 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 4228 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 4229 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 4230 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 4231 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000, 4232 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000, 4233 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 4234 0x41C00000 4235 }; 4236 4237 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid, 4238 const unsigned int *lookup, int idx) 4239 { 4240 int i = 0; 4241 4242 for (i = 0; i < TUNING_CTLS_COUNT; i++) 4243 if (nid == ca0132_tuning_ctls[i].nid) 4244 goto found; 4245 4246 return -EINVAL; 4247 found: 4248 snd_hda_power_up(codec); 4249 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20, 4250 ca0132_tuning_ctls[i].req, 4251 &(lookup[idx]), sizeof(unsigned int)); 4252 snd_hda_power_down(codec); 4253 4254 return 1; 4255 } 4256 4257 static int tuning_ctl_get(struct snd_kcontrol *kcontrol, 4258 struct snd_ctl_elem_value *ucontrol) 4259 { 4260 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4261 struct ca0132_spec *spec = codec->spec; 4262 hda_nid_t nid = get_amp_nid(kcontrol); 4263 long *valp = ucontrol->value.integer.value; 4264 int idx = nid - TUNING_CTL_START_NID; 4265 4266 *valp = spec->cur_ctl_vals[idx]; 4267 return 0; 4268 } 4269 4270 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol, 4271 struct snd_ctl_elem_info *uinfo) 4272 { 4273 int chs = get_amp_channels(kcontrol); 4274 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4275 uinfo->count = chs == 3 ? 2 : 1; 4276 uinfo->value.integer.min = 20; 4277 uinfo->value.integer.max = 180; 4278 uinfo->value.integer.step = 1; 4279 4280 return 0; 4281 } 4282 4283 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol, 4284 struct snd_ctl_elem_value *ucontrol) 4285 { 4286 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4287 struct ca0132_spec *spec = codec->spec; 4288 hda_nid_t nid = get_amp_nid(kcontrol); 4289 long *valp = ucontrol->value.integer.value; 4290 int idx; 4291 4292 idx = nid - TUNING_CTL_START_NID; 4293 /* any change? */ 4294 if (spec->cur_ctl_vals[idx] == *valp) 4295 return 0; 4296 4297 spec->cur_ctl_vals[idx] = *valp; 4298 4299 idx = *valp - 20; 4300 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx); 4301 4302 return 1; 4303 } 4304 4305 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol, 4306 struct snd_ctl_elem_info *uinfo) 4307 { 4308 int chs = get_amp_channels(kcontrol); 4309 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4310 uinfo->count = chs == 3 ? 2 : 1; 4311 uinfo->value.integer.min = 0; 4312 uinfo->value.integer.max = 100; 4313 uinfo->value.integer.step = 1; 4314 4315 return 0; 4316 } 4317 4318 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol, 4319 struct snd_ctl_elem_value *ucontrol) 4320 { 4321 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4322 struct ca0132_spec *spec = codec->spec; 4323 hda_nid_t nid = get_amp_nid(kcontrol); 4324 long *valp = ucontrol->value.integer.value; 4325 int idx; 4326 4327 idx = nid - TUNING_CTL_START_NID; 4328 /* any change? */ 4329 if (spec->cur_ctl_vals[idx] == *valp) 4330 return 0; 4331 4332 spec->cur_ctl_vals[idx] = *valp; 4333 4334 idx = *valp; 4335 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx); 4336 4337 return 0; 4338 } 4339 4340 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol, 4341 struct snd_ctl_elem_info *uinfo) 4342 { 4343 int chs = get_amp_channels(kcontrol); 4344 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4345 uinfo->count = chs == 3 ? 2 : 1; 4346 uinfo->value.integer.min = 0; 4347 uinfo->value.integer.max = 48; 4348 uinfo->value.integer.step = 1; 4349 4350 return 0; 4351 } 4352 4353 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol, 4354 struct snd_ctl_elem_value *ucontrol) 4355 { 4356 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4357 struct ca0132_spec *spec = codec->spec; 4358 hda_nid_t nid = get_amp_nid(kcontrol); 4359 long *valp = ucontrol->value.integer.value; 4360 int idx; 4361 4362 idx = nid - TUNING_CTL_START_NID; 4363 /* any change? */ 4364 if (spec->cur_ctl_vals[idx] == *valp) 4365 return 0; 4366 4367 spec->cur_ctl_vals[idx] = *valp; 4368 4369 idx = *valp; 4370 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx); 4371 4372 return 1; 4373 } 4374 4375 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0); 4376 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0); 4377 4378 static int add_tuning_control(struct hda_codec *codec, 4379 hda_nid_t pnid, hda_nid_t nid, 4380 const char *name, int dir) 4381 { 4382 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 4383 int type = dir ? HDA_INPUT : HDA_OUTPUT; 4384 struct snd_kcontrol_new knew = 4385 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 4386 4387 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 4388 SNDRV_CTL_ELEM_ACCESS_TLV_READ; 4389 knew.tlv.c = 0; 4390 knew.tlv.p = 0; 4391 switch (pnid) { 4392 case VOICE_FOCUS: 4393 knew.info = voice_focus_ctl_info; 4394 knew.get = tuning_ctl_get; 4395 knew.put = voice_focus_ctl_put; 4396 knew.tlv.p = voice_focus_db_scale; 4397 break; 4398 case MIC_SVM: 4399 knew.info = mic_svm_ctl_info; 4400 knew.get = tuning_ctl_get; 4401 knew.put = mic_svm_ctl_put; 4402 break; 4403 case EQUALIZER: 4404 knew.info = equalizer_ctl_info; 4405 knew.get = tuning_ctl_get; 4406 knew.put = equalizer_ctl_put; 4407 knew.tlv.p = eq_db_scale; 4408 break; 4409 default: 4410 return 0; 4411 } 4412 knew.private_value = 4413 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 4414 sprintf(namestr, "%s %s Volume", name, dirstr[dir]); 4415 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 4416 } 4417 4418 static int add_tuning_ctls(struct hda_codec *codec) 4419 { 4420 int i; 4421 int err; 4422 4423 for (i = 0; i < TUNING_CTLS_COUNT; i++) { 4424 err = add_tuning_control(codec, 4425 ca0132_tuning_ctls[i].parent_nid, 4426 ca0132_tuning_ctls[i].nid, 4427 ca0132_tuning_ctls[i].name, 4428 ca0132_tuning_ctls[i].direct); 4429 if (err < 0) 4430 return err; 4431 } 4432 4433 return 0; 4434 } 4435 4436 static void ca0132_init_tuning_defaults(struct hda_codec *codec) 4437 { 4438 struct ca0132_spec *spec = codec->spec; 4439 int i; 4440 4441 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */ 4442 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10; 4443 /* SVM level defaults to 0.74. */ 4444 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74; 4445 4446 /* EQ defaults to 0dB. */ 4447 for (i = 2; i < TUNING_CTLS_COUNT; i++) 4448 spec->cur_ctl_vals[i] = 24; 4449 } 4450 #endif /*ENABLE_TUNING_CONTROLS*/ 4451 4452 /* 4453 * Select the active output. 4454 * If autodetect is enabled, output will be selected based on jack detection. 4455 * If jack inserted, headphone will be selected, else built-in speakers 4456 * If autodetect is disabled, output will be selected based on selection. 4457 */ 4458 static int ca0132_select_out(struct hda_codec *codec) 4459 { 4460 struct ca0132_spec *spec = codec->spec; 4461 unsigned int pin_ctl; 4462 int jack_present; 4463 int auto_jack; 4464 unsigned int tmp; 4465 int err; 4466 4467 codec_dbg(codec, "ca0132_select_out\n"); 4468 4469 snd_hda_power_up_pm(codec); 4470 4471 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4472 4473 if (auto_jack) 4474 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp); 4475 else 4476 jack_present = 4477 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID]; 4478 4479 if (jack_present) 4480 spec->cur_out_type = HEADPHONE_OUT; 4481 else 4482 spec->cur_out_type = SPEAKER_OUT; 4483 4484 if (spec->cur_out_type == SPEAKER_OUT) { 4485 codec_dbg(codec, "ca0132_select_out speaker\n"); 4486 /*speaker out config*/ 4487 tmp = FLOAT_ONE; 4488 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4489 if (err < 0) 4490 goto exit; 4491 /*enable speaker EQ*/ 4492 tmp = FLOAT_ONE; 4493 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4494 if (err < 0) 4495 goto exit; 4496 4497 /* Setup EAPD */ 4498 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4499 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4500 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4501 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4502 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4503 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4504 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4505 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4506 4507 /* disable headphone node */ 4508 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4509 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4510 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4511 pin_ctl & ~PIN_HP); 4512 /* enable speaker node */ 4513 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4514 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4515 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4516 pin_ctl | PIN_OUT); 4517 } else { 4518 codec_dbg(codec, "ca0132_select_out hp\n"); 4519 /*headphone out config*/ 4520 tmp = FLOAT_ZERO; 4521 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4522 if (err < 0) 4523 goto exit; 4524 /*disable speaker EQ*/ 4525 tmp = FLOAT_ZERO; 4526 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4527 if (err < 0) 4528 goto exit; 4529 4530 /* Setup EAPD */ 4531 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4532 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4533 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4534 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4535 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4536 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4537 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4538 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4539 4540 /* disable speaker*/ 4541 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4542 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4543 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4544 pin_ctl & ~PIN_HP); 4545 /* enable headphone*/ 4546 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4547 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4548 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4549 pin_ctl | PIN_HP); 4550 } 4551 4552 exit: 4553 snd_hda_power_down_pm(codec); 4554 4555 return err < 0 ? err : 0; 4556 } 4557 4558 static int ae5_headphone_gain_set(struct hda_codec *codec, long val); 4559 static int zxr_headphone_gain_set(struct hda_codec *codec, long val); 4560 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val); 4561 4562 static void ae5_mmio_select_out(struct hda_codec *codec) 4563 { 4564 struct ca0132_spec *spec = codec->spec; 4565 const struct ae_ca0113_output_set *out_cmds; 4566 unsigned int i; 4567 4568 if (ca0132_quirk(spec) == QUIRK_AE5) 4569 out_cmds = &ae5_ca0113_output_presets; 4570 else 4571 out_cmds = &ae7_ca0113_output_presets; 4572 4573 for (i = 0; i < AE_CA0113_OUT_SET_COMMANDS; i++) 4574 ca0113_mmio_command_set(codec, out_cmds->group[i], 4575 out_cmds->target[i], 4576 out_cmds->vals[spec->cur_out_type][i]); 4577 } 4578 4579 static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec) 4580 { 4581 struct ca0132_spec *spec = codec->spec; 4582 int quirk = ca0132_quirk(spec); 4583 unsigned int tmp; 4584 int err; 4585 4586 /* 2.0/4.0 setup has no LFE channel, so setting full-range does nothing. */ 4587 if (spec->channel_cfg_val == SPEAKER_CHANNELS_4_0 4588 || spec->channel_cfg_val == SPEAKER_CHANNELS_2_0) 4589 return 0; 4590 4591 /* Set front L/R full range. Zero for full-range, one for redirection. */ 4592 tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE; 4593 err = dspio_set_uint_param(codec, 0x96, 4594 SPEAKER_FULL_RANGE_FRONT_L_R, tmp); 4595 if (err < 0) 4596 return err; 4597 4598 /* When setting full-range rear, both rear and center/lfe are set. */ 4599 tmp = spec->speaker_range_val[1] ? FLOAT_ZERO : FLOAT_ONE; 4600 err = dspio_set_uint_param(codec, 0x96, 4601 SPEAKER_FULL_RANGE_CENTER_LFE, tmp); 4602 if (err < 0) 4603 return err; 4604 4605 err = dspio_set_uint_param(codec, 0x96, 4606 SPEAKER_FULL_RANGE_REAR_L_R, tmp); 4607 if (err < 0) 4608 return err; 4609 4610 /* 4611 * Only the AE series cards set this value when setting full-range, 4612 * and it's always 1.0f. 4613 */ 4614 if (quirk == QUIRK_AE5 || quirk == QUIRK_AE7) { 4615 err = dspio_set_uint_param(codec, 0x96, 4616 SPEAKER_FULL_RANGE_SURROUND_L_R, FLOAT_ONE); 4617 if (err < 0) 4618 return err; 4619 } 4620 4621 return 0; 4622 } 4623 4624 static int ca0132_alt_surround_set_bass_redirection(struct hda_codec *codec, 4625 bool val) 4626 { 4627 struct ca0132_spec *spec = codec->spec; 4628 unsigned int tmp; 4629 int err; 4630 4631 if (val && spec->channel_cfg_val != SPEAKER_CHANNELS_4_0 && 4632 spec->channel_cfg_val != SPEAKER_CHANNELS_2_0) 4633 tmp = FLOAT_ONE; 4634 else 4635 tmp = FLOAT_ZERO; 4636 4637 err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp); 4638 if (err < 0) 4639 return err; 4640 4641 /* If it is enabled, make sure to set the crossover frequency. */ 4642 if (tmp) { 4643 tmp = float_xbass_xover_lookup[spec->xbass_xover_freq]; 4644 err = dspio_set_uint_param(codec, 0x96, 4645 SPEAKER_BASS_REDIRECT_XOVER_FREQ, tmp); 4646 if (err < 0) 4647 return err; 4648 } 4649 4650 return 0; 4651 } 4652 4653 /* 4654 * These are the commands needed to setup output on each of the different card 4655 * types. 4656 */ 4657 static void ca0132_alt_select_out_get_quirk_data(struct hda_codec *codec, 4658 const struct ca0132_alt_out_set_quirk_data **quirk_data) 4659 { 4660 struct ca0132_spec *spec = codec->spec; 4661 int quirk = ca0132_quirk(spec); 4662 unsigned int i; 4663 4664 *quirk_data = NULL; 4665 for (i = 0; i < ARRAY_SIZE(quirk_out_set_data); i++) { 4666 if (quirk_out_set_data[i].quirk_id == quirk) { 4667 *quirk_data = &quirk_out_set_data[i]; 4668 return; 4669 } 4670 } 4671 } 4672 4673 static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec) 4674 { 4675 const struct ca0132_alt_out_set_quirk_data *quirk_data; 4676 const struct ca0132_alt_out_set_info *out_info; 4677 struct ca0132_spec *spec = codec->spec; 4678 unsigned int i, gpio_data; 4679 int err; 4680 4681 ca0132_alt_select_out_get_quirk_data(codec, &quirk_data); 4682 if (!quirk_data) 4683 return 0; 4684 4685 out_info = &quirk_data->out_set_info[spec->cur_out_type]; 4686 if (quirk_data->is_ae_series) 4687 ae5_mmio_select_out(codec); 4688 4689 if (out_info->has_hda_gpio) { 4690 gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0, 4691 AC_VERB_GET_GPIO_DATA, 0); 4692 4693 if (out_info->hda_gpio_set) 4694 gpio_data |= (1 << out_info->hda_gpio_pin); 4695 else 4696 gpio_data &= ~(1 << out_info->hda_gpio_pin); 4697 4698 snd_hda_codec_write(codec, codec->core.afg, 0, 4699 AC_VERB_SET_GPIO_DATA, gpio_data); 4700 } 4701 4702 if (out_info->mmio_gpio_count) { 4703 for (i = 0; i < out_info->mmio_gpio_count; i++) { 4704 ca0113_mmio_gpio_set(codec, out_info->mmio_gpio_pin[i], 4705 out_info->mmio_gpio_set[i]); 4706 } 4707 } 4708 4709 if (out_info->scp_cmds_count) { 4710 for (i = 0; i < out_info->scp_cmds_count; i++) { 4711 err = dspio_set_uint_param(codec, 4712 out_info->scp_cmd_mid[i], 4713 out_info->scp_cmd_req[i], 4714 out_info->scp_cmd_val[i]); 4715 if (err < 0) 4716 return err; 4717 } 4718 } 4719 4720 chipio_set_control_param(codec, 0x0d, out_info->dac2port); 4721 4722 if (out_info->has_chipio_write) { 4723 chipio_write(codec, out_info->chipio_write_addr, 4724 out_info->chipio_write_data); 4725 } 4726 4727 if (quirk_data->has_headphone_gain) { 4728 if (spec->cur_out_type != HEADPHONE_OUT) { 4729 if (quirk_data->is_ae_series) 4730 ae5_headphone_gain_set(codec, 2); 4731 else 4732 zxr_headphone_gain_set(codec, 0); 4733 } else { 4734 if (quirk_data->is_ae_series) 4735 ae5_headphone_gain_set(codec, 4736 spec->ae5_headphone_gain_val); 4737 else 4738 zxr_headphone_gain_set(codec, 4739 spec->zxr_gain_set); 4740 } 4741 } 4742 4743 return 0; 4744 } 4745 4746 static void ca0132_set_out_node_pincfg(struct hda_codec *codec, hda_nid_t nid, 4747 bool out_enable, bool hp_enable) 4748 { 4749 unsigned int pin_ctl; 4750 4751 pin_ctl = snd_hda_codec_read(codec, nid, 0, 4752 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4753 4754 pin_ctl = hp_enable ? pin_ctl | PIN_HP_AMP : pin_ctl & ~PIN_HP_AMP; 4755 pin_ctl = out_enable ? pin_ctl | PIN_OUT : pin_ctl & ~PIN_OUT; 4756 snd_hda_set_pin_ctl(codec, nid, pin_ctl); 4757 } 4758 4759 /* 4760 * This function behaves similarly to the ca0132_select_out funciton above, 4761 * except with a few differences. It adds the ability to select the current 4762 * output with an enumerated control "output source" if the auto detect 4763 * mute switch is set to off. If the auto detect mute switch is enabled, it 4764 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection. 4765 * It also adds the ability to auto-detect the front headphone port. 4766 */ 4767 static int ca0132_alt_select_out(struct hda_codec *codec) 4768 { 4769 struct ca0132_spec *spec = codec->spec; 4770 unsigned int tmp, outfx_set; 4771 int jack_present; 4772 int auto_jack; 4773 int err; 4774 /* Default Headphone is rear headphone */ 4775 hda_nid_t headphone_nid = spec->out_pins[1]; 4776 4777 codec_dbg(codec, "%s\n", __func__); 4778 4779 snd_hda_power_up_pm(codec); 4780 4781 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4782 4783 /* 4784 * If headphone rear or front is plugged in, set to headphone. 4785 * If neither is plugged in, set to rear line out. Only if 4786 * hp/speaker auto detect is enabled. 4787 */ 4788 if (auto_jack) { 4789 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) || 4790 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp); 4791 4792 if (jack_present) 4793 spec->cur_out_type = HEADPHONE_OUT; 4794 else 4795 spec->cur_out_type = SPEAKER_OUT; 4796 } else 4797 spec->cur_out_type = spec->out_enum_val; 4798 4799 outfx_set = spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]; 4800 4801 /* Begin DSP output switch, mute DSP volume. */ 4802 err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE); 4803 if (err < 0) 4804 goto exit; 4805 4806 if (ca0132_alt_select_out_quirk_set(codec) < 0) 4807 goto exit; 4808 4809 switch (spec->cur_out_type) { 4810 case SPEAKER_OUT: 4811 codec_dbg(codec, "%s speaker\n", __func__); 4812 4813 /* Enable EAPD */ 4814 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4815 AC_VERB_SET_EAPD_BTLENABLE, 0x01); 4816 4817 /* Disable headphone node. */ 4818 ca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0); 4819 /* Set front L-R to output. */ 4820 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0); 4821 /* Set Center/LFE to output. */ 4822 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0); 4823 /* Set rear surround to output. */ 4824 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0); 4825 4826 /* 4827 * Without PlayEnhancement being enabled, if we've got a 2.0 4828 * setup, set it to floating point eight to disable any DSP 4829 * processing effects. 4830 */ 4831 if (!outfx_set && spec->channel_cfg_val == SPEAKER_CHANNELS_2_0) 4832 tmp = FLOAT_EIGHT; 4833 else 4834 tmp = speaker_channel_cfgs[spec->channel_cfg_val].val; 4835 4836 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4837 if (err < 0) 4838 goto exit; 4839 4840 break; 4841 case HEADPHONE_OUT: 4842 codec_dbg(codec, "%s hp\n", __func__); 4843 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4844 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4845 4846 /* Disable all speaker nodes. */ 4847 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0); 4848 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0); 4849 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0); 4850 4851 /* enable headphone, either front or rear */ 4852 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp)) 4853 headphone_nid = spec->out_pins[2]; 4854 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp)) 4855 headphone_nid = spec->out_pins[1]; 4856 4857 ca0132_set_out_node_pincfg(codec, headphone_nid, 1, 1); 4858 4859 if (outfx_set) 4860 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE); 4861 else 4862 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO); 4863 4864 if (err < 0) 4865 goto exit; 4866 break; 4867 } 4868 /* 4869 * If output effects are enabled, set the X-Bass effect value again to 4870 * make sure that it's properly enabled/disabled for speaker 4871 * configurations with an LFE channel. 4872 */ 4873 if (outfx_set) 4874 ca0132_effects_set(codec, X_BASS, 4875 spec->effects_switch[X_BASS - EFFECT_START_NID]); 4876 4877 /* Set speaker EQ bypass attenuation to 0. */ 4878 err = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO); 4879 if (err < 0) 4880 goto exit; 4881 4882 /* 4883 * Although unused on all cards but the AE series, this is always set 4884 * to zero when setting the output. 4885 */ 4886 err = dspio_set_uint_param(codec, 0x96, 4887 SPEAKER_TUNING_USE_SPEAKER_EQ, FLOAT_ZERO); 4888 if (err < 0) 4889 goto exit; 4890 4891 if (spec->cur_out_type == SPEAKER_OUT) 4892 err = ca0132_alt_surround_set_bass_redirection(codec, 4893 spec->bass_redirection_val); 4894 else 4895 err = ca0132_alt_surround_set_bass_redirection(codec, 0); 4896 4897 /* Unmute DSP now that we're done with output selection. */ 4898 err = dspio_set_uint_param(codec, 0x96, 4899 SPEAKER_TUNING_MUTE, FLOAT_ZERO); 4900 if (err < 0) 4901 goto exit; 4902 4903 if (spec->cur_out_type == SPEAKER_OUT) { 4904 err = ca0132_alt_set_full_range_speaker(codec); 4905 if (err < 0) 4906 goto exit; 4907 } 4908 4909 exit: 4910 snd_hda_power_down_pm(codec); 4911 4912 return err < 0 ? err : 0; 4913 } 4914 4915 static void ca0132_unsol_hp_delayed(struct work_struct *work) 4916 { 4917 struct ca0132_spec *spec = container_of( 4918 to_delayed_work(work), struct ca0132_spec, unsol_hp_work); 4919 struct hda_jack_tbl *jack; 4920 4921 if (ca0132_use_alt_functions(spec)) 4922 ca0132_alt_select_out(spec->codec); 4923 else 4924 ca0132_select_out(spec->codec); 4925 4926 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp); 4927 if (jack) { 4928 jack->block_report = 0; 4929 snd_hda_jack_report_sync(spec->codec); 4930 } 4931 } 4932 4933 static void ca0132_set_dmic(struct hda_codec *codec, int enable); 4934 static int ca0132_mic_boost_set(struct hda_codec *codec, long val); 4935 static void resume_mic1(struct hda_codec *codec, unsigned int oldval); 4936 static int stop_mic1(struct hda_codec *codec); 4937 static int ca0132_cvoice_switch_set(struct hda_codec *codec); 4938 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val); 4939 4940 /* 4941 * Select the active VIP source 4942 */ 4943 static int ca0132_set_vipsource(struct hda_codec *codec, int val) 4944 { 4945 struct ca0132_spec *spec = codec->spec; 4946 unsigned int tmp; 4947 4948 if (spec->dsp_state != DSP_DOWNLOADED) 4949 return 0; 4950 4951 /* if CrystalVoice if off, vipsource should be 0 */ 4952 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4953 (val == 0)) { 4954 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4955 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4956 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4957 if (spec->cur_mic_type == DIGITAL_MIC) 4958 tmp = FLOAT_TWO; 4959 else 4960 tmp = FLOAT_ONE; 4961 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4962 tmp = FLOAT_ZERO; 4963 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4964 } else { 4965 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4966 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4967 if (spec->cur_mic_type == DIGITAL_MIC) 4968 tmp = FLOAT_TWO; 4969 else 4970 tmp = FLOAT_ONE; 4971 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4972 tmp = FLOAT_ONE; 4973 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4974 msleep(20); 4975 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4976 } 4977 4978 return 1; 4979 } 4980 4981 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val) 4982 { 4983 struct ca0132_spec *spec = codec->spec; 4984 unsigned int tmp; 4985 4986 if (spec->dsp_state != DSP_DOWNLOADED) 4987 return 0; 4988 4989 codec_dbg(codec, "%s\n", __func__); 4990 4991 chipio_set_stream_control(codec, 0x03, 0); 4992 chipio_set_stream_control(codec, 0x04, 0); 4993 4994 /* if CrystalVoice is off, vipsource should be 0 */ 4995 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4996 (val == 0) || spec->in_enum_val == REAR_LINE_IN) { 4997 codec_dbg(codec, "%s: off.", __func__); 4998 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4999 5000 tmp = FLOAT_ZERO; 5001 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 5002 5003 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5004 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5005 if (ca0132_quirk(spec) == QUIRK_R3DI) 5006 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5007 5008 5009 if (spec->in_enum_val == REAR_LINE_IN) 5010 tmp = FLOAT_ZERO; 5011 else { 5012 if (ca0132_quirk(spec) == QUIRK_SBZ) 5013 tmp = FLOAT_THREE; 5014 else 5015 tmp = FLOAT_ONE; 5016 } 5017 5018 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5019 5020 } else { 5021 codec_dbg(codec, "%s: on.", __func__); 5022 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 5023 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 5024 if (ca0132_quirk(spec) == QUIRK_R3DI) 5025 chipio_set_conn_rate(codec, 0x0F, SR_16_000); 5026 5027 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID]) 5028 tmp = FLOAT_TWO; 5029 else 5030 tmp = FLOAT_ONE; 5031 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5032 5033 tmp = FLOAT_ONE; 5034 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 5035 5036 msleep(20); 5037 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 5038 } 5039 5040 chipio_set_stream_control(codec, 0x03, 1); 5041 chipio_set_stream_control(codec, 0x04, 1); 5042 5043 return 1; 5044 } 5045 5046 /* 5047 * Select the active microphone. 5048 * If autodetect is enabled, mic will be selected based on jack detection. 5049 * If jack inserted, ext.mic will be selected, else built-in mic 5050 * If autodetect is disabled, mic will be selected based on selection. 5051 */ 5052 static int ca0132_select_mic(struct hda_codec *codec) 5053 { 5054 struct ca0132_spec *spec = codec->spec; 5055 int jack_present; 5056 int auto_jack; 5057 5058 codec_dbg(codec, "ca0132_select_mic\n"); 5059 5060 snd_hda_power_up_pm(codec); 5061 5062 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 5063 5064 if (auto_jack) 5065 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1); 5066 else 5067 jack_present = 5068 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID]; 5069 5070 if (jack_present) 5071 spec->cur_mic_type = LINE_MIC_IN; 5072 else 5073 spec->cur_mic_type = DIGITAL_MIC; 5074 5075 if (spec->cur_mic_type == DIGITAL_MIC) { 5076 /* enable digital Mic */ 5077 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000); 5078 ca0132_set_dmic(codec, 1); 5079 ca0132_mic_boost_set(codec, 0); 5080 /* set voice focus */ 5081 ca0132_effects_set(codec, VOICE_FOCUS, 5082 spec->effects_switch 5083 [VOICE_FOCUS - EFFECT_START_NID]); 5084 } else { 5085 /* disable digital Mic */ 5086 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000); 5087 ca0132_set_dmic(codec, 0); 5088 ca0132_mic_boost_set(codec, spec->cur_mic_boost); 5089 /* disable voice focus */ 5090 ca0132_effects_set(codec, VOICE_FOCUS, 0); 5091 } 5092 5093 snd_hda_power_down_pm(codec); 5094 5095 return 0; 5096 } 5097 5098 /* 5099 * Select the active input. 5100 * Mic detection isn't used, because it's kind of pointless on the SBZ. 5101 * The front mic has no jack-detection, so the only way to switch to it 5102 * is to do it manually in alsamixer. 5103 */ 5104 static int ca0132_alt_select_in(struct hda_codec *codec) 5105 { 5106 struct ca0132_spec *spec = codec->spec; 5107 unsigned int tmp; 5108 5109 codec_dbg(codec, "%s\n", __func__); 5110 5111 snd_hda_power_up_pm(codec); 5112 5113 chipio_set_stream_control(codec, 0x03, 0); 5114 chipio_set_stream_control(codec, 0x04, 0); 5115 5116 spec->cur_mic_type = spec->in_enum_val; 5117 5118 switch (spec->cur_mic_type) { 5119 case REAR_MIC: 5120 switch (ca0132_quirk(spec)) { 5121 case QUIRK_SBZ: 5122 case QUIRK_R3D: 5123 ca0113_mmio_gpio_set(codec, 0, false); 5124 tmp = FLOAT_THREE; 5125 break; 5126 case QUIRK_ZXR: 5127 tmp = FLOAT_THREE; 5128 break; 5129 case QUIRK_R3DI: 5130 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 5131 tmp = FLOAT_ONE; 5132 break; 5133 case QUIRK_AE5: 5134 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5135 tmp = FLOAT_THREE; 5136 break; 5137 case QUIRK_AE7: 5138 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5139 tmp = FLOAT_THREE; 5140 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, 5141 SR_96_000); 5142 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, 5143 SR_96_000); 5144 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO); 5145 break; 5146 default: 5147 tmp = FLOAT_ONE; 5148 break; 5149 } 5150 5151 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5152 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5153 if (ca0132_quirk(spec) == QUIRK_R3DI) 5154 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5155 5156 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5157 5158 chipio_set_stream_control(codec, 0x03, 1); 5159 chipio_set_stream_control(codec, 0x04, 1); 5160 switch (ca0132_quirk(spec)) { 5161 case QUIRK_SBZ: 5162 chipio_write(codec, 0x18B098, 0x0000000C); 5163 chipio_write(codec, 0x18B09C, 0x0000000C); 5164 break; 5165 case QUIRK_ZXR: 5166 chipio_write(codec, 0x18B098, 0x0000000C); 5167 chipio_write(codec, 0x18B09C, 0x000000CC); 5168 break; 5169 case QUIRK_AE5: 5170 chipio_write(codec, 0x18B098, 0x0000000C); 5171 chipio_write(codec, 0x18B09C, 0x0000004C); 5172 break; 5173 default: 5174 break; 5175 } 5176 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5177 break; 5178 case REAR_LINE_IN: 5179 ca0132_mic_boost_set(codec, 0); 5180 switch (ca0132_quirk(spec)) { 5181 case QUIRK_SBZ: 5182 case QUIRK_R3D: 5183 ca0113_mmio_gpio_set(codec, 0, false); 5184 break; 5185 case QUIRK_R3DI: 5186 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 5187 break; 5188 case QUIRK_AE5: 5189 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5190 break; 5191 case QUIRK_AE7: 5192 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f); 5193 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, 5194 SR_96_000); 5195 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, 5196 SR_96_000); 5197 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO); 5198 break; 5199 default: 5200 break; 5201 } 5202 5203 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5204 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5205 if (ca0132_quirk(spec) == QUIRK_R3DI) 5206 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5207 5208 if (ca0132_quirk(spec) == QUIRK_AE7) 5209 tmp = FLOAT_THREE; 5210 else 5211 tmp = FLOAT_ZERO; 5212 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5213 5214 switch (ca0132_quirk(spec)) { 5215 case QUIRK_SBZ: 5216 case QUIRK_AE5: 5217 chipio_write(codec, 0x18B098, 0x00000000); 5218 chipio_write(codec, 0x18B09C, 0x00000000); 5219 break; 5220 default: 5221 break; 5222 } 5223 chipio_set_stream_control(codec, 0x03, 1); 5224 chipio_set_stream_control(codec, 0x04, 1); 5225 break; 5226 case FRONT_MIC: 5227 switch (ca0132_quirk(spec)) { 5228 case QUIRK_SBZ: 5229 case QUIRK_R3D: 5230 ca0113_mmio_gpio_set(codec, 0, true); 5231 ca0113_mmio_gpio_set(codec, 5, false); 5232 tmp = FLOAT_THREE; 5233 break; 5234 case QUIRK_R3DI: 5235 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC); 5236 tmp = FLOAT_ONE; 5237 break; 5238 case QUIRK_AE5: 5239 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f); 5240 tmp = FLOAT_THREE; 5241 break; 5242 default: 5243 tmp = FLOAT_ONE; 5244 break; 5245 } 5246 5247 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5248 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5249 if (ca0132_quirk(spec) == QUIRK_R3DI) 5250 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5251 5252 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5253 5254 chipio_set_stream_control(codec, 0x03, 1); 5255 chipio_set_stream_control(codec, 0x04, 1); 5256 5257 switch (ca0132_quirk(spec)) { 5258 case QUIRK_SBZ: 5259 chipio_write(codec, 0x18B098, 0x0000000C); 5260 chipio_write(codec, 0x18B09C, 0x000000CC); 5261 break; 5262 case QUIRK_AE5: 5263 chipio_write(codec, 0x18B098, 0x0000000C); 5264 chipio_write(codec, 0x18B09C, 0x0000004C); 5265 break; 5266 default: 5267 break; 5268 } 5269 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5270 break; 5271 } 5272 ca0132_cvoice_switch_set(codec); 5273 5274 snd_hda_power_down_pm(codec); 5275 return 0; 5276 } 5277 5278 /* 5279 * Check if VNODE settings take effect immediately. 5280 */ 5281 static bool ca0132_is_vnode_effective(struct hda_codec *codec, 5282 hda_nid_t vnid, 5283 hda_nid_t *shared_nid) 5284 { 5285 struct ca0132_spec *spec = codec->spec; 5286 hda_nid_t nid; 5287 5288 switch (vnid) { 5289 case VNID_SPK: 5290 nid = spec->shared_out_nid; 5291 break; 5292 case VNID_MIC: 5293 nid = spec->shared_mic_nid; 5294 break; 5295 default: 5296 return false; 5297 } 5298 5299 if (shared_nid) 5300 *shared_nid = nid; 5301 5302 return true; 5303 } 5304 5305 /* 5306 * The following functions are control change helpers. 5307 * They return 0 if no changed. Return 1 if changed. 5308 */ 5309 static int ca0132_voicefx_set(struct hda_codec *codec, int enable) 5310 { 5311 struct ca0132_spec *spec = codec->spec; 5312 unsigned int tmp; 5313 5314 /* based on CrystalVoice state to enable VoiceFX. */ 5315 if (enable) { 5316 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ? 5317 FLOAT_ONE : FLOAT_ZERO; 5318 } else { 5319 tmp = FLOAT_ZERO; 5320 } 5321 5322 dspio_set_uint_param(codec, ca0132_voicefx.mid, 5323 ca0132_voicefx.reqs[0], tmp); 5324 5325 return 1; 5326 } 5327 5328 /* 5329 * Set the effects parameters 5330 */ 5331 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val) 5332 { 5333 struct ca0132_spec *spec = codec->spec; 5334 unsigned int on, tmp, channel_cfg; 5335 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 5336 int err = 0; 5337 int idx = nid - EFFECT_START_NID; 5338 5339 if ((idx < 0) || (idx >= num_fx)) 5340 return 0; /* no changed */ 5341 5342 /* for out effect, qualify with PE */ 5343 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) { 5344 /* if PE if off, turn off out effects. */ 5345 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 5346 val = 0; 5347 if (spec->cur_out_type == SPEAKER_OUT && nid == X_BASS) { 5348 channel_cfg = spec->channel_cfg_val; 5349 if (channel_cfg != SPEAKER_CHANNELS_2_0 && 5350 channel_cfg != SPEAKER_CHANNELS_4_0) 5351 val = 0; 5352 } 5353 } 5354 5355 /* for in effect, qualify with CrystalVoice */ 5356 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) { 5357 /* if CrystalVoice if off, turn off in effects. */ 5358 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 5359 val = 0; 5360 5361 /* Voice Focus applies to 2-ch Mic, Digital Mic */ 5362 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC)) 5363 val = 0; 5364 5365 /* If Voice Focus on SBZ, set to two channel. */ 5366 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec) 5367 && (spec->cur_mic_type != REAR_LINE_IN)) { 5368 if (spec->effects_switch[CRYSTAL_VOICE - 5369 EFFECT_START_NID]) { 5370 5371 if (spec->effects_switch[VOICE_FOCUS - 5372 EFFECT_START_NID]) { 5373 tmp = FLOAT_TWO; 5374 val = 1; 5375 } else 5376 tmp = FLOAT_ONE; 5377 5378 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5379 } 5380 } 5381 /* 5382 * For SBZ noise reduction, there's an extra command 5383 * to module ID 0x47. No clue why. 5384 */ 5385 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec) 5386 && (spec->cur_mic_type != REAR_LINE_IN)) { 5387 if (spec->effects_switch[CRYSTAL_VOICE - 5388 EFFECT_START_NID]) { 5389 if (spec->effects_switch[NOISE_REDUCTION - 5390 EFFECT_START_NID]) 5391 tmp = FLOAT_ONE; 5392 else 5393 tmp = FLOAT_ZERO; 5394 } else 5395 tmp = FLOAT_ZERO; 5396 5397 dspio_set_uint_param(codec, 0x47, 0x00, tmp); 5398 } 5399 5400 /* If rear line in disable effects. */ 5401 if (ca0132_use_alt_functions(spec) && 5402 spec->in_enum_val == REAR_LINE_IN) 5403 val = 0; 5404 } 5405 5406 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n", 5407 nid, val); 5408 5409 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE; 5410 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid, 5411 ca0132_effects[idx].reqs[0], on); 5412 5413 if (err < 0) 5414 return 0; /* no changed */ 5415 5416 return 1; 5417 } 5418 5419 /* 5420 * Turn on/off Playback Enhancements 5421 */ 5422 static int ca0132_pe_switch_set(struct hda_codec *codec) 5423 { 5424 struct ca0132_spec *spec = codec->spec; 5425 hda_nid_t nid; 5426 int i, ret = 0; 5427 5428 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n", 5429 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]); 5430 5431 if (ca0132_use_alt_functions(spec)) 5432 ca0132_alt_select_out(codec); 5433 5434 i = OUT_EFFECT_START_NID - EFFECT_START_NID; 5435 nid = OUT_EFFECT_START_NID; 5436 /* PE affects all out effects */ 5437 for (; nid < OUT_EFFECT_END_NID; nid++, i++) 5438 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 5439 5440 return ret; 5441 } 5442 5443 /* Check if Mic1 is streaming, if so, stop streaming */ 5444 static int stop_mic1(struct hda_codec *codec) 5445 { 5446 struct ca0132_spec *spec = codec->spec; 5447 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0, 5448 AC_VERB_GET_CONV, 0); 5449 if (oldval != 0) 5450 snd_hda_codec_write(codec, spec->adcs[0], 0, 5451 AC_VERB_SET_CHANNEL_STREAMID, 5452 0); 5453 return oldval; 5454 } 5455 5456 /* Resume Mic1 streaming if it was stopped. */ 5457 static void resume_mic1(struct hda_codec *codec, unsigned int oldval) 5458 { 5459 struct ca0132_spec *spec = codec->spec; 5460 /* Restore the previous stream and channel */ 5461 if (oldval != 0) 5462 snd_hda_codec_write(codec, spec->adcs[0], 0, 5463 AC_VERB_SET_CHANNEL_STREAMID, 5464 oldval); 5465 } 5466 5467 /* 5468 * Turn on/off CrystalVoice 5469 */ 5470 static int ca0132_cvoice_switch_set(struct hda_codec *codec) 5471 { 5472 struct ca0132_spec *spec = codec->spec; 5473 hda_nid_t nid; 5474 int i, ret = 0; 5475 unsigned int oldval; 5476 5477 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n", 5478 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]); 5479 5480 i = IN_EFFECT_START_NID - EFFECT_START_NID; 5481 nid = IN_EFFECT_START_NID; 5482 /* CrystalVoice affects all in effects */ 5483 for (; nid < IN_EFFECT_END_NID; nid++, i++) 5484 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 5485 5486 /* including VoiceFX */ 5487 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0)); 5488 5489 /* set correct vipsource */ 5490 oldval = stop_mic1(codec); 5491 if (ca0132_use_alt_functions(spec)) 5492 ret |= ca0132_alt_set_vipsource(codec, 1); 5493 else 5494 ret |= ca0132_set_vipsource(codec, 1); 5495 resume_mic1(codec, oldval); 5496 return ret; 5497 } 5498 5499 static int ca0132_mic_boost_set(struct hda_codec *codec, long val) 5500 { 5501 struct ca0132_spec *spec = codec->spec; 5502 int ret = 0; 5503 5504 if (val) /* on */ 5505 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5506 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3); 5507 else /* off */ 5508 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5509 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0); 5510 5511 return ret; 5512 } 5513 5514 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val) 5515 { 5516 struct ca0132_spec *spec = codec->spec; 5517 int ret = 0; 5518 5519 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5520 HDA_INPUT, 0, HDA_AMP_VOLMASK, val); 5521 return ret; 5522 } 5523 5524 static int ae5_headphone_gain_set(struct hda_codec *codec, long val) 5525 { 5526 unsigned int i; 5527 5528 for (i = 0; i < 4; i++) 5529 ca0113_mmio_command_set(codec, 0x48, 0x11 + i, 5530 ae5_headphone_gain_presets[val].vals[i]); 5531 return 0; 5532 } 5533 5534 /* 5535 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone 5536 * amplifier to handle a 600 ohm load. 5537 */ 5538 static int zxr_headphone_gain_set(struct hda_codec *codec, long val) 5539 { 5540 ca0113_mmio_gpio_set(codec, 1, val); 5541 5542 return 0; 5543 } 5544 5545 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol, 5546 struct snd_ctl_elem_value *ucontrol) 5547 { 5548 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5549 hda_nid_t nid = get_amp_nid(kcontrol); 5550 hda_nid_t shared_nid = 0; 5551 bool effective; 5552 int ret = 0; 5553 struct ca0132_spec *spec = codec->spec; 5554 int auto_jack; 5555 5556 if (nid == VNID_HP_SEL) { 5557 auto_jack = 5558 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 5559 if (!auto_jack) { 5560 if (ca0132_use_alt_functions(spec)) 5561 ca0132_alt_select_out(codec); 5562 else 5563 ca0132_select_out(codec); 5564 } 5565 return 1; 5566 } 5567 5568 if (nid == VNID_AMIC1_SEL) { 5569 auto_jack = 5570 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 5571 if (!auto_jack) 5572 ca0132_select_mic(codec); 5573 return 1; 5574 } 5575 5576 if (nid == VNID_HP_ASEL) { 5577 if (ca0132_use_alt_functions(spec)) 5578 ca0132_alt_select_out(codec); 5579 else 5580 ca0132_select_out(codec); 5581 return 1; 5582 } 5583 5584 if (nid == VNID_AMIC1_ASEL) { 5585 ca0132_select_mic(codec); 5586 return 1; 5587 } 5588 5589 /* if effective conditions, then update hw immediately. */ 5590 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 5591 if (effective) { 5592 int dir = get_amp_direction(kcontrol); 5593 int ch = get_amp_channels(kcontrol); 5594 unsigned long pval; 5595 5596 mutex_lock(&codec->control_mutex); 5597 pval = kcontrol->private_value; 5598 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 5599 0, dir); 5600 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol); 5601 kcontrol->private_value = pval; 5602 mutex_unlock(&codec->control_mutex); 5603 } 5604 5605 return ret; 5606 } 5607 /* End of control change helpers. */ 5608 5609 static void ca0132_alt_bass_redirection_xover_set(struct hda_codec *codec, 5610 long idx) 5611 { 5612 snd_hda_power_up(codec); 5613 5614 dspio_set_param(codec, 0x96, 0x20, SPEAKER_BASS_REDIRECT_XOVER_FREQ, 5615 &(float_xbass_xover_lookup[idx]), sizeof(unsigned int)); 5616 5617 snd_hda_power_down(codec); 5618 } 5619 5620 /* 5621 * Below I've added controls to mess with the effect levels, I've only enabled 5622 * them on the Sound Blaster Z, but they would probably also work on the 5623 * Chromebook. I figured they were probably tuned specifically for it, and left 5624 * out for a reason. 5625 */ 5626 5627 /* Sets DSP effect level from the sliders above the controls */ 5628 5629 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid, 5630 const unsigned int *lookup, int idx) 5631 { 5632 int i = 0; 5633 unsigned int y; 5634 /* 5635 * For X_BASS, req 2 is actually crossover freq instead of 5636 * effect level 5637 */ 5638 if (nid == X_BASS) 5639 y = 2; 5640 else 5641 y = 1; 5642 5643 snd_hda_power_up(codec); 5644 if (nid == XBASS_XOVER) { 5645 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5646 if (ca0132_effects[i].nid == X_BASS) 5647 break; 5648 5649 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5650 ca0132_effects[i].reqs[1], 5651 &(lookup[idx - 1]), sizeof(unsigned int)); 5652 } else { 5653 /* Find the actual effect structure */ 5654 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5655 if (nid == ca0132_effects[i].nid) 5656 break; 5657 5658 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5659 ca0132_effects[i].reqs[y], 5660 &(lookup[idx]), sizeof(unsigned int)); 5661 } 5662 5663 snd_hda_power_down(codec); 5664 5665 return 0; 5666 } 5667 5668 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol, 5669 struct snd_ctl_elem_value *ucontrol) 5670 { 5671 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5672 struct ca0132_spec *spec = codec->spec; 5673 long *valp = ucontrol->value.integer.value; 5674 hda_nid_t nid = get_amp_nid(kcontrol); 5675 5676 if (nid == BASS_REDIRECTION_XOVER) 5677 *valp = spec->bass_redirect_xover_freq; 5678 else 5679 *valp = spec->xbass_xover_freq; 5680 5681 return 0; 5682 } 5683 5684 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol, 5685 struct snd_ctl_elem_value *ucontrol) 5686 { 5687 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5688 struct ca0132_spec *spec = codec->spec; 5689 hda_nid_t nid = get_amp_nid(kcontrol); 5690 long *valp = ucontrol->value.integer.value; 5691 int idx = nid - OUT_EFFECT_START_NID; 5692 5693 *valp = spec->fx_ctl_val[idx]; 5694 return 0; 5695 } 5696 5697 /* 5698 * The X-bass crossover starts at 10hz, so the min is 1. The 5699 * frequency is set in multiples of 10. 5700 */ 5701 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol, 5702 struct snd_ctl_elem_info *uinfo) 5703 { 5704 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5705 uinfo->count = 1; 5706 uinfo->value.integer.min = 1; 5707 uinfo->value.integer.max = 100; 5708 uinfo->value.integer.step = 1; 5709 5710 return 0; 5711 } 5712 5713 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol, 5714 struct snd_ctl_elem_info *uinfo) 5715 { 5716 int chs = get_amp_channels(kcontrol); 5717 5718 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5719 uinfo->count = chs == 3 ? 2 : 1; 5720 uinfo->value.integer.min = 0; 5721 uinfo->value.integer.max = 100; 5722 uinfo->value.integer.step = 1; 5723 5724 return 0; 5725 } 5726 5727 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol, 5728 struct snd_ctl_elem_value *ucontrol) 5729 { 5730 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5731 struct ca0132_spec *spec = codec->spec; 5732 hda_nid_t nid = get_amp_nid(kcontrol); 5733 long *valp = ucontrol->value.integer.value; 5734 long *cur_val; 5735 int idx; 5736 5737 if (nid == BASS_REDIRECTION_XOVER) 5738 cur_val = &spec->bass_redirect_xover_freq; 5739 else 5740 cur_val = &spec->xbass_xover_freq; 5741 5742 /* any change? */ 5743 if (*cur_val == *valp) 5744 return 0; 5745 5746 *cur_val = *valp; 5747 5748 idx = *valp; 5749 if (nid == BASS_REDIRECTION_XOVER) 5750 ca0132_alt_bass_redirection_xover_set(codec, *cur_val); 5751 else 5752 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx); 5753 5754 return 0; 5755 } 5756 5757 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol, 5758 struct snd_ctl_elem_value *ucontrol) 5759 { 5760 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5761 struct ca0132_spec *spec = codec->spec; 5762 hda_nid_t nid = get_amp_nid(kcontrol); 5763 long *valp = ucontrol->value.integer.value; 5764 int idx; 5765 5766 idx = nid - EFFECT_START_NID; 5767 /* any change? */ 5768 if (spec->fx_ctl_val[idx] == *valp) 5769 return 0; 5770 5771 spec->fx_ctl_val[idx] = *valp; 5772 5773 idx = *valp; 5774 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx); 5775 5776 return 0; 5777 } 5778 5779 5780 /* 5781 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original 5782 * only has off or full 30 dB, and didn't like making a volume slider that has 5783 * traditional 0-100 in alsamixer that goes in big steps. I like enum better. 5784 */ 5785 #define MIC_BOOST_NUM_OF_STEPS 4 5786 #define MIC_BOOST_ENUM_MAX_STRLEN 10 5787 5788 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol, 5789 struct snd_ctl_elem_info *uinfo) 5790 { 5791 char *sfx = "dB"; 5792 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5793 5794 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5795 uinfo->count = 1; 5796 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS; 5797 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS) 5798 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1; 5799 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx); 5800 strcpy(uinfo->value.enumerated.name, namestr); 5801 return 0; 5802 } 5803 5804 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol, 5805 struct snd_ctl_elem_value *ucontrol) 5806 { 5807 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5808 struct ca0132_spec *spec = codec->spec; 5809 5810 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val; 5811 return 0; 5812 } 5813 5814 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol, 5815 struct snd_ctl_elem_value *ucontrol) 5816 { 5817 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5818 struct ca0132_spec *spec = codec->spec; 5819 int sel = ucontrol->value.enumerated.item[0]; 5820 unsigned int items = MIC_BOOST_NUM_OF_STEPS; 5821 5822 if (sel >= items) 5823 return 0; 5824 5825 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n", 5826 sel); 5827 5828 spec->mic_boost_enum_val = sel; 5829 5830 if (spec->in_enum_val != REAR_LINE_IN) 5831 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5832 5833 return 1; 5834 } 5835 5836 /* 5837 * Sound BlasterX AE-5 Headphone Gain Controls. 5838 */ 5839 #define AE5_HEADPHONE_GAIN_MAX 3 5840 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol, 5841 struct snd_ctl_elem_info *uinfo) 5842 { 5843 char *sfx = " Ohms)"; 5844 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5845 5846 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5847 uinfo->count = 1; 5848 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX; 5849 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX) 5850 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1; 5851 sprintf(namestr, "%s %s", 5852 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name, 5853 sfx); 5854 strcpy(uinfo->value.enumerated.name, namestr); 5855 return 0; 5856 } 5857 5858 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol, 5859 struct snd_ctl_elem_value *ucontrol) 5860 { 5861 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5862 struct ca0132_spec *spec = codec->spec; 5863 5864 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val; 5865 return 0; 5866 } 5867 5868 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol, 5869 struct snd_ctl_elem_value *ucontrol) 5870 { 5871 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5872 struct ca0132_spec *spec = codec->spec; 5873 int sel = ucontrol->value.enumerated.item[0]; 5874 unsigned int items = AE5_HEADPHONE_GAIN_MAX; 5875 5876 if (sel >= items) 5877 return 0; 5878 5879 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n", 5880 sel); 5881 5882 spec->ae5_headphone_gain_val = sel; 5883 5884 if (spec->out_enum_val == HEADPHONE_OUT) 5885 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val); 5886 5887 return 1; 5888 } 5889 5890 /* 5891 * Sound BlasterX AE-5 sound filter enumerated control. 5892 */ 5893 #define AE5_SOUND_FILTER_MAX 3 5894 5895 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol, 5896 struct snd_ctl_elem_info *uinfo) 5897 { 5898 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5899 5900 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5901 uinfo->count = 1; 5902 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX; 5903 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX) 5904 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1; 5905 sprintf(namestr, "%s", 5906 ae5_filter_presets[uinfo->value.enumerated.item].name); 5907 strcpy(uinfo->value.enumerated.name, namestr); 5908 return 0; 5909 } 5910 5911 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol, 5912 struct snd_ctl_elem_value *ucontrol) 5913 { 5914 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5915 struct ca0132_spec *spec = codec->spec; 5916 5917 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val; 5918 return 0; 5919 } 5920 5921 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol, 5922 struct snd_ctl_elem_value *ucontrol) 5923 { 5924 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5925 struct ca0132_spec *spec = codec->spec; 5926 int sel = ucontrol->value.enumerated.item[0]; 5927 unsigned int items = AE5_SOUND_FILTER_MAX; 5928 5929 if (sel >= items) 5930 return 0; 5931 5932 codec_dbg(codec, "ae5_sound_filter: %s\n", 5933 ae5_filter_presets[sel].name); 5934 5935 spec->ae5_filter_val = sel; 5936 5937 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 5938 ae5_filter_presets[sel].val); 5939 5940 return 1; 5941 } 5942 5943 /* 5944 * Input Select Control for alternative ca0132 codecs. This exists because 5945 * front microphone has no auto-detect, and we need a way to set the rear 5946 * as line-in 5947 */ 5948 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol, 5949 struct snd_ctl_elem_info *uinfo) 5950 { 5951 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5952 uinfo->count = 1; 5953 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS; 5954 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS) 5955 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1; 5956 strcpy(uinfo->value.enumerated.name, 5957 in_src_str[uinfo->value.enumerated.item]); 5958 return 0; 5959 } 5960 5961 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol, 5962 struct snd_ctl_elem_value *ucontrol) 5963 { 5964 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5965 struct ca0132_spec *spec = codec->spec; 5966 5967 ucontrol->value.enumerated.item[0] = spec->in_enum_val; 5968 return 0; 5969 } 5970 5971 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol, 5972 struct snd_ctl_elem_value *ucontrol) 5973 { 5974 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5975 struct ca0132_spec *spec = codec->spec; 5976 int sel = ucontrol->value.enumerated.item[0]; 5977 unsigned int items = IN_SRC_NUM_OF_INPUTS; 5978 5979 /* 5980 * The AE-7 has no front microphone, so limit items to 2: rear mic and 5981 * line-in. 5982 */ 5983 if (ca0132_quirk(spec) == QUIRK_AE7) 5984 items = 2; 5985 5986 if (sel >= items) 5987 return 0; 5988 5989 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n", 5990 sel, in_src_str[sel]); 5991 5992 spec->in_enum_val = sel; 5993 5994 ca0132_alt_select_in(codec); 5995 5996 return 1; 5997 } 5998 5999 /* Sound Blaster Z Output Select Control */ 6000 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol, 6001 struct snd_ctl_elem_info *uinfo) 6002 { 6003 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6004 uinfo->count = 1; 6005 uinfo->value.enumerated.items = NUM_OF_OUTPUTS; 6006 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS) 6007 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1; 6008 strcpy(uinfo->value.enumerated.name, 6009 out_type_str[uinfo->value.enumerated.item]); 6010 return 0; 6011 } 6012 6013 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol, 6014 struct snd_ctl_elem_value *ucontrol) 6015 { 6016 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6017 struct ca0132_spec *spec = codec->spec; 6018 6019 ucontrol->value.enumerated.item[0] = spec->out_enum_val; 6020 return 0; 6021 } 6022 6023 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol, 6024 struct snd_ctl_elem_value *ucontrol) 6025 { 6026 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6027 struct ca0132_spec *spec = codec->spec; 6028 int sel = ucontrol->value.enumerated.item[0]; 6029 unsigned int items = NUM_OF_OUTPUTS; 6030 unsigned int auto_jack; 6031 6032 if (sel >= items) 6033 return 0; 6034 6035 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n", 6036 sel, out_type_str[sel]); 6037 6038 spec->out_enum_val = sel; 6039 6040 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 6041 6042 if (!auto_jack) 6043 ca0132_alt_select_out(codec); 6044 6045 return 1; 6046 } 6047 6048 /* Select surround output type: 2.1, 4.0, 4.1, or 5.1. */ 6049 static int ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol *kcontrol, 6050 struct snd_ctl_elem_info *uinfo) 6051 { 6052 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT; 6053 6054 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6055 uinfo->count = 1; 6056 uinfo->value.enumerated.items = items; 6057 if (uinfo->value.enumerated.item >= items) 6058 uinfo->value.enumerated.item = items - 1; 6059 strcpy(uinfo->value.enumerated.name, 6060 speaker_channel_cfgs[uinfo->value.enumerated.item].name); 6061 return 0; 6062 } 6063 6064 static int ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol *kcontrol, 6065 struct snd_ctl_elem_value *ucontrol) 6066 { 6067 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6068 struct ca0132_spec *spec = codec->spec; 6069 6070 ucontrol->value.enumerated.item[0] = spec->channel_cfg_val; 6071 return 0; 6072 } 6073 6074 static int ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol *kcontrol, 6075 struct snd_ctl_elem_value *ucontrol) 6076 { 6077 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6078 struct ca0132_spec *spec = codec->spec; 6079 int sel = ucontrol->value.enumerated.item[0]; 6080 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT; 6081 6082 if (sel >= items) 6083 return 0; 6084 6085 codec_dbg(codec, "ca0132_alt_speaker_channels: sel=%d, channels=%s\n", 6086 sel, speaker_channel_cfgs[sel].name); 6087 6088 spec->channel_cfg_val = sel; 6089 6090 if (spec->out_enum_val == SPEAKER_OUT) 6091 ca0132_alt_select_out(codec); 6092 6093 return 1; 6094 } 6095 6096 /* 6097 * Smart Volume output setting control. Three different settings, Normal, 6098 * which takes the value from the smart volume slider. The two others, loud 6099 * and night, disregard the slider value and have uneditable values. 6100 */ 6101 #define NUM_OF_SVM_SETTINGS 3 6102 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" }; 6103 6104 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol, 6105 struct snd_ctl_elem_info *uinfo) 6106 { 6107 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6108 uinfo->count = 1; 6109 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS; 6110 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS) 6111 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1; 6112 strcpy(uinfo->value.enumerated.name, 6113 out_svm_set_enum_str[uinfo->value.enumerated.item]); 6114 return 0; 6115 } 6116 6117 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol, 6118 struct snd_ctl_elem_value *ucontrol) 6119 { 6120 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6121 struct ca0132_spec *spec = codec->spec; 6122 6123 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting; 6124 return 0; 6125 } 6126 6127 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol, 6128 struct snd_ctl_elem_value *ucontrol) 6129 { 6130 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6131 struct ca0132_spec *spec = codec->spec; 6132 int sel = ucontrol->value.enumerated.item[0]; 6133 unsigned int items = NUM_OF_SVM_SETTINGS; 6134 unsigned int idx = SMART_VOLUME - EFFECT_START_NID; 6135 unsigned int tmp; 6136 6137 if (sel >= items) 6138 return 0; 6139 6140 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n", 6141 sel, out_svm_set_enum_str[sel]); 6142 6143 spec->smart_volume_setting = sel; 6144 6145 switch (sel) { 6146 case 0: 6147 tmp = FLOAT_ZERO; 6148 break; 6149 case 1: 6150 tmp = FLOAT_ONE; 6151 break; 6152 case 2: 6153 tmp = FLOAT_TWO; 6154 break; 6155 default: 6156 tmp = FLOAT_ZERO; 6157 break; 6158 } 6159 /* Req 2 is the Smart Volume Setting req. */ 6160 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 6161 ca0132_effects[idx].reqs[2], tmp); 6162 return 1; 6163 } 6164 6165 /* Sound Blaster Z EQ preset controls */ 6166 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol, 6167 struct snd_ctl_elem_info *uinfo) 6168 { 6169 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 6170 6171 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6172 uinfo->count = 1; 6173 uinfo->value.enumerated.items = items; 6174 if (uinfo->value.enumerated.item >= items) 6175 uinfo->value.enumerated.item = items - 1; 6176 strcpy(uinfo->value.enumerated.name, 6177 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name); 6178 return 0; 6179 } 6180 6181 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol, 6182 struct snd_ctl_elem_value *ucontrol) 6183 { 6184 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6185 struct ca0132_spec *spec = codec->spec; 6186 6187 ucontrol->value.enumerated.item[0] = spec->eq_preset_val; 6188 return 0; 6189 } 6190 6191 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol, 6192 struct snd_ctl_elem_value *ucontrol) 6193 { 6194 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6195 struct ca0132_spec *spec = codec->spec; 6196 int i, err = 0; 6197 int sel = ucontrol->value.enumerated.item[0]; 6198 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 6199 6200 if (sel >= items) 6201 return 0; 6202 6203 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel, 6204 ca0132_alt_eq_presets[sel].name); 6205 /* 6206 * Idx 0 is default. 6207 * Default needs to qualify with CrystalVoice state. 6208 */ 6209 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) { 6210 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid, 6211 ca0132_alt_eq_enum.reqs[i], 6212 ca0132_alt_eq_presets[sel].vals[i]); 6213 if (err < 0) 6214 break; 6215 } 6216 6217 if (err >= 0) 6218 spec->eq_preset_val = sel; 6219 6220 return 1; 6221 } 6222 6223 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol, 6224 struct snd_ctl_elem_info *uinfo) 6225 { 6226 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets); 6227 6228 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6229 uinfo->count = 1; 6230 uinfo->value.enumerated.items = items; 6231 if (uinfo->value.enumerated.item >= items) 6232 uinfo->value.enumerated.item = items - 1; 6233 strcpy(uinfo->value.enumerated.name, 6234 ca0132_voicefx_presets[uinfo->value.enumerated.item].name); 6235 return 0; 6236 } 6237 6238 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol, 6239 struct snd_ctl_elem_value *ucontrol) 6240 { 6241 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6242 struct ca0132_spec *spec = codec->spec; 6243 6244 ucontrol->value.enumerated.item[0] = spec->voicefx_val; 6245 return 0; 6246 } 6247 6248 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol, 6249 struct snd_ctl_elem_value *ucontrol) 6250 { 6251 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6252 struct ca0132_spec *spec = codec->spec; 6253 int i, err = 0; 6254 int sel = ucontrol->value.enumerated.item[0]; 6255 6256 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets)) 6257 return 0; 6258 6259 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n", 6260 sel, ca0132_voicefx_presets[sel].name); 6261 6262 /* 6263 * Idx 0 is default. 6264 * Default needs to qualify with CrystalVoice state. 6265 */ 6266 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) { 6267 err = dspio_set_uint_param(codec, ca0132_voicefx.mid, 6268 ca0132_voicefx.reqs[i], 6269 ca0132_voicefx_presets[sel].vals[i]); 6270 if (err < 0) 6271 break; 6272 } 6273 6274 if (err >= 0) { 6275 spec->voicefx_val = sel; 6276 /* enable voice fx */ 6277 ca0132_voicefx_set(codec, (sel ? 1 : 0)); 6278 } 6279 6280 return 1; 6281 } 6282 6283 static int ca0132_switch_get(struct snd_kcontrol *kcontrol, 6284 struct snd_ctl_elem_value *ucontrol) 6285 { 6286 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6287 struct ca0132_spec *spec = codec->spec; 6288 hda_nid_t nid = get_amp_nid(kcontrol); 6289 int ch = get_amp_channels(kcontrol); 6290 long *valp = ucontrol->value.integer.value; 6291 6292 /* vnode */ 6293 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 6294 if (ch & 1) { 6295 *valp = spec->vnode_lswitch[nid - VNODE_START_NID]; 6296 valp++; 6297 } 6298 if (ch & 2) { 6299 *valp = spec->vnode_rswitch[nid - VNODE_START_NID]; 6300 valp++; 6301 } 6302 return 0; 6303 } 6304 6305 /* effects, include PE and CrystalVoice */ 6306 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) { 6307 *valp = spec->effects_switch[nid - EFFECT_START_NID]; 6308 return 0; 6309 } 6310 6311 /* mic boost */ 6312 if (nid == spec->input_pins[0]) { 6313 *valp = spec->cur_mic_boost; 6314 return 0; 6315 } 6316 6317 if (nid == ZXR_HEADPHONE_GAIN) { 6318 *valp = spec->zxr_gain_set; 6319 return 0; 6320 } 6321 6322 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) { 6323 *valp = spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT]; 6324 return 0; 6325 } 6326 6327 if (nid == BASS_REDIRECTION) { 6328 *valp = spec->bass_redirection_val; 6329 return 0; 6330 } 6331 6332 return 0; 6333 } 6334 6335 static int ca0132_switch_put(struct snd_kcontrol *kcontrol, 6336 struct snd_ctl_elem_value *ucontrol) 6337 { 6338 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6339 struct ca0132_spec *spec = codec->spec; 6340 hda_nid_t nid = get_amp_nid(kcontrol); 6341 int ch = get_amp_channels(kcontrol); 6342 long *valp = ucontrol->value.integer.value; 6343 int changed = 1; 6344 6345 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n", 6346 nid, *valp); 6347 6348 snd_hda_power_up(codec); 6349 /* vnode */ 6350 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 6351 if (ch & 1) { 6352 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp; 6353 valp++; 6354 } 6355 if (ch & 2) { 6356 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp; 6357 valp++; 6358 } 6359 changed = ca0132_vnode_switch_set(kcontrol, ucontrol); 6360 goto exit; 6361 } 6362 6363 /* PE */ 6364 if (nid == PLAY_ENHANCEMENT) { 6365 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6366 changed = ca0132_pe_switch_set(codec); 6367 goto exit; 6368 } 6369 6370 /* CrystalVoice */ 6371 if (nid == CRYSTAL_VOICE) { 6372 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6373 changed = ca0132_cvoice_switch_set(codec); 6374 goto exit; 6375 } 6376 6377 /* out and in effects */ 6378 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) || 6379 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) { 6380 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6381 changed = ca0132_effects_set(codec, nid, *valp); 6382 goto exit; 6383 } 6384 6385 /* mic boost */ 6386 if (nid == spec->input_pins[0]) { 6387 spec->cur_mic_boost = *valp; 6388 if (ca0132_use_alt_functions(spec)) { 6389 if (spec->in_enum_val != REAR_LINE_IN) 6390 changed = ca0132_mic_boost_set(codec, *valp); 6391 } else { 6392 /* Mic boost does not apply to Digital Mic */ 6393 if (spec->cur_mic_type != DIGITAL_MIC) 6394 changed = ca0132_mic_boost_set(codec, *valp); 6395 } 6396 6397 goto exit; 6398 } 6399 6400 if (nid == ZXR_HEADPHONE_GAIN) { 6401 spec->zxr_gain_set = *valp; 6402 if (spec->cur_out_type == HEADPHONE_OUT) 6403 changed = zxr_headphone_gain_set(codec, *valp); 6404 else 6405 changed = 0; 6406 6407 goto exit; 6408 } 6409 6410 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) { 6411 spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT] = *valp; 6412 if (spec->cur_out_type == SPEAKER_OUT) 6413 ca0132_alt_set_full_range_speaker(codec); 6414 6415 changed = 0; 6416 } 6417 6418 if (nid == BASS_REDIRECTION) { 6419 spec->bass_redirection_val = *valp; 6420 if (spec->cur_out_type == SPEAKER_OUT) 6421 ca0132_alt_surround_set_bass_redirection(codec, *valp); 6422 6423 changed = 0; 6424 } 6425 6426 exit: 6427 snd_hda_power_down(codec); 6428 return changed; 6429 } 6430 6431 /* 6432 * Volume related 6433 */ 6434 /* 6435 * Sets the internal DSP decibel level to match the DAC for output, and the 6436 * ADC for input. Currently only the SBZ sets dsp capture volume level, and 6437 * all alternative codecs set DSP playback volume. 6438 */ 6439 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid) 6440 { 6441 struct ca0132_spec *spec = codec->spec; 6442 unsigned int dsp_dir; 6443 unsigned int lookup_val; 6444 6445 if (nid == VNID_SPK) 6446 dsp_dir = DSP_VOL_OUT; 6447 else 6448 dsp_dir = DSP_VOL_IN; 6449 6450 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID]; 6451 6452 dspio_set_uint_param(codec, 6453 ca0132_alt_vol_ctls[dsp_dir].mid, 6454 ca0132_alt_vol_ctls[dsp_dir].reqs[0], 6455 float_vol_db_lookup[lookup_val]); 6456 6457 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID]; 6458 6459 dspio_set_uint_param(codec, 6460 ca0132_alt_vol_ctls[dsp_dir].mid, 6461 ca0132_alt_vol_ctls[dsp_dir].reqs[1], 6462 float_vol_db_lookup[lookup_val]); 6463 6464 dspio_set_uint_param(codec, 6465 ca0132_alt_vol_ctls[dsp_dir].mid, 6466 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO); 6467 } 6468 6469 static int ca0132_volume_info(struct snd_kcontrol *kcontrol, 6470 struct snd_ctl_elem_info *uinfo) 6471 { 6472 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6473 struct ca0132_spec *spec = codec->spec; 6474 hda_nid_t nid = get_amp_nid(kcontrol); 6475 int ch = get_amp_channels(kcontrol); 6476 int dir = get_amp_direction(kcontrol); 6477 unsigned long pval; 6478 int err; 6479 6480 switch (nid) { 6481 case VNID_SPK: 6482 /* follow shared_out info */ 6483 nid = spec->shared_out_nid; 6484 mutex_lock(&codec->control_mutex); 6485 pval = kcontrol->private_value; 6486 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6487 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6488 kcontrol->private_value = pval; 6489 mutex_unlock(&codec->control_mutex); 6490 break; 6491 case VNID_MIC: 6492 /* follow shared_mic info */ 6493 nid = spec->shared_mic_nid; 6494 mutex_lock(&codec->control_mutex); 6495 pval = kcontrol->private_value; 6496 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6497 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6498 kcontrol->private_value = pval; 6499 mutex_unlock(&codec->control_mutex); 6500 break; 6501 default: 6502 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6503 } 6504 return err; 6505 } 6506 6507 static int ca0132_volume_get(struct snd_kcontrol *kcontrol, 6508 struct snd_ctl_elem_value *ucontrol) 6509 { 6510 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6511 struct ca0132_spec *spec = codec->spec; 6512 hda_nid_t nid = get_amp_nid(kcontrol); 6513 int ch = get_amp_channels(kcontrol); 6514 long *valp = ucontrol->value.integer.value; 6515 6516 /* store the left and right volume */ 6517 if (ch & 1) { 6518 *valp = spec->vnode_lvol[nid - VNODE_START_NID]; 6519 valp++; 6520 } 6521 if (ch & 2) { 6522 *valp = spec->vnode_rvol[nid - VNODE_START_NID]; 6523 valp++; 6524 } 6525 return 0; 6526 } 6527 6528 static int ca0132_volume_put(struct snd_kcontrol *kcontrol, 6529 struct snd_ctl_elem_value *ucontrol) 6530 { 6531 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6532 struct ca0132_spec *spec = codec->spec; 6533 hda_nid_t nid = get_amp_nid(kcontrol); 6534 int ch = get_amp_channels(kcontrol); 6535 long *valp = ucontrol->value.integer.value; 6536 hda_nid_t shared_nid = 0; 6537 bool effective; 6538 int changed = 1; 6539 6540 /* store the left and right volume */ 6541 if (ch & 1) { 6542 spec->vnode_lvol[nid - VNODE_START_NID] = *valp; 6543 valp++; 6544 } 6545 if (ch & 2) { 6546 spec->vnode_rvol[nid - VNODE_START_NID] = *valp; 6547 valp++; 6548 } 6549 6550 /* if effective conditions, then update hw immediately. */ 6551 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 6552 if (effective) { 6553 int dir = get_amp_direction(kcontrol); 6554 unsigned long pval; 6555 6556 snd_hda_power_up(codec); 6557 mutex_lock(&codec->control_mutex); 6558 pval = kcontrol->private_value; 6559 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 6560 0, dir); 6561 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 6562 kcontrol->private_value = pval; 6563 mutex_unlock(&codec->control_mutex); 6564 snd_hda_power_down(codec); 6565 } 6566 6567 return changed; 6568 } 6569 6570 /* 6571 * This function is the same as the one above, because using an if statement 6572 * inside of the above volume control for the DSP volume would cause too much 6573 * lag. This is a lot more smooth. 6574 */ 6575 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol, 6576 struct snd_ctl_elem_value *ucontrol) 6577 { 6578 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6579 struct ca0132_spec *spec = codec->spec; 6580 hda_nid_t nid = get_amp_nid(kcontrol); 6581 int ch = get_amp_channels(kcontrol); 6582 long *valp = ucontrol->value.integer.value; 6583 hda_nid_t vnid = 0; 6584 int changed; 6585 6586 switch (nid) { 6587 case 0x02: 6588 vnid = VNID_SPK; 6589 break; 6590 case 0x07: 6591 vnid = VNID_MIC; 6592 break; 6593 } 6594 6595 /* store the left and right volume */ 6596 if (ch & 1) { 6597 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp; 6598 valp++; 6599 } 6600 if (ch & 2) { 6601 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp; 6602 valp++; 6603 } 6604 6605 snd_hda_power_up(codec); 6606 ca0132_alt_dsp_volume_put(codec, vnid); 6607 mutex_lock(&codec->control_mutex); 6608 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 6609 mutex_unlock(&codec->control_mutex); 6610 snd_hda_power_down(codec); 6611 6612 return changed; 6613 } 6614 6615 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag, 6616 unsigned int size, unsigned int __user *tlv) 6617 { 6618 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6619 struct ca0132_spec *spec = codec->spec; 6620 hda_nid_t nid = get_amp_nid(kcontrol); 6621 int ch = get_amp_channels(kcontrol); 6622 int dir = get_amp_direction(kcontrol); 6623 unsigned long pval; 6624 int err; 6625 6626 switch (nid) { 6627 case VNID_SPK: 6628 /* follow shared_out tlv */ 6629 nid = spec->shared_out_nid; 6630 mutex_lock(&codec->control_mutex); 6631 pval = kcontrol->private_value; 6632 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6633 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6634 kcontrol->private_value = pval; 6635 mutex_unlock(&codec->control_mutex); 6636 break; 6637 case VNID_MIC: 6638 /* follow shared_mic tlv */ 6639 nid = spec->shared_mic_nid; 6640 mutex_lock(&codec->control_mutex); 6641 pval = kcontrol->private_value; 6642 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6643 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6644 kcontrol->private_value = pval; 6645 mutex_unlock(&codec->control_mutex); 6646 break; 6647 default: 6648 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6649 } 6650 return err; 6651 } 6652 6653 /* Add volume slider control for effect level */ 6654 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid, 6655 const char *pfx, int dir) 6656 { 6657 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6658 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6659 struct snd_kcontrol_new knew = 6660 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 6661 6662 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]); 6663 6664 knew.tlv.c = NULL; 6665 6666 switch (nid) { 6667 case XBASS_XOVER: 6668 knew.info = ca0132_alt_xbass_xover_slider_info; 6669 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 6670 knew.put = ca0132_alt_xbass_xover_slider_put; 6671 break; 6672 default: 6673 knew.info = ca0132_alt_effect_slider_info; 6674 knew.get = ca0132_alt_slider_ctl_get; 6675 knew.put = ca0132_alt_effect_slider_put; 6676 knew.private_value = 6677 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 6678 break; 6679 } 6680 6681 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6682 } 6683 6684 /* 6685 * Added FX: prefix for the alternative codecs, because otherwise the surround 6686 * effect would conflict with the Surround sound volume control. Also seems more 6687 * clear as to what the switches do. Left alone for others. 6688 */ 6689 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid, 6690 const char *pfx, int dir) 6691 { 6692 struct ca0132_spec *spec = codec->spec; 6693 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6694 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6695 struct snd_kcontrol_new knew = 6696 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type); 6697 /* If using alt_controls, add FX: prefix. But, don't add FX: 6698 * prefix to OutFX or InFX enable controls. 6699 */ 6700 if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID)) 6701 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]); 6702 else 6703 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]); 6704 6705 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6706 } 6707 6708 static int add_voicefx(struct hda_codec *codec) 6709 { 6710 struct snd_kcontrol_new knew = 6711 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name, 6712 VOICEFX, 1, 0, HDA_INPUT); 6713 knew.info = ca0132_voicefx_info; 6714 knew.get = ca0132_voicefx_get; 6715 knew.put = ca0132_voicefx_put; 6716 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec)); 6717 } 6718 6719 /* Create the EQ Preset control */ 6720 static int add_ca0132_alt_eq_presets(struct hda_codec *codec) 6721 { 6722 struct snd_kcontrol_new knew = 6723 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name, 6724 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT); 6725 knew.info = ca0132_alt_eq_preset_info; 6726 knew.get = ca0132_alt_eq_preset_get; 6727 knew.put = ca0132_alt_eq_preset_put; 6728 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM, 6729 snd_ctl_new1(&knew, codec)); 6730 } 6731 6732 /* 6733 * Add enumerated control for the three different settings of the smart volume 6734 * output effect. Normal just uses the slider value, and loud and night are 6735 * their own things that ignore that value. 6736 */ 6737 static int ca0132_alt_add_svm_enum(struct hda_codec *codec) 6738 { 6739 struct snd_kcontrol_new knew = 6740 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting", 6741 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT); 6742 knew.info = ca0132_alt_svm_setting_info; 6743 knew.get = ca0132_alt_svm_setting_get; 6744 knew.put = ca0132_alt_svm_setting_put; 6745 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM, 6746 snd_ctl_new1(&knew, codec)); 6747 6748 } 6749 6750 /* 6751 * Create an Output Select enumerated control for codecs with surround 6752 * out capabilities. 6753 */ 6754 static int ca0132_alt_add_output_enum(struct hda_codec *codec) 6755 { 6756 struct snd_kcontrol_new knew = 6757 HDA_CODEC_MUTE_MONO("Output Select", 6758 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT); 6759 knew.info = ca0132_alt_output_select_get_info; 6760 knew.get = ca0132_alt_output_select_get; 6761 knew.put = ca0132_alt_output_select_put; 6762 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM, 6763 snd_ctl_new1(&knew, codec)); 6764 } 6765 6766 /* 6767 * Add a control for selecting channel count on speaker output. Setting this 6768 * allows the DSP to do bass redirection and channel upmixing on surround 6769 * configurations. 6770 */ 6771 static int ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec *codec) 6772 { 6773 struct snd_kcontrol_new knew = 6774 HDA_CODEC_MUTE_MONO("Surround Channel Config", 6775 SPEAKER_CHANNEL_CFG_ENUM, 1, 0, HDA_OUTPUT); 6776 knew.info = ca0132_alt_speaker_channel_cfg_get_info; 6777 knew.get = ca0132_alt_speaker_channel_cfg_get; 6778 knew.put = ca0132_alt_speaker_channel_cfg_put; 6779 return snd_hda_ctl_add(codec, SPEAKER_CHANNEL_CFG_ENUM, 6780 snd_ctl_new1(&knew, codec)); 6781 } 6782 6783 /* 6784 * Full range front stereo and rear surround switches. When these are set to 6785 * full range, the lower frequencies from these channels are no longer 6786 * redirected to the LFE channel. 6787 */ 6788 static int ca0132_alt_add_front_full_range_switch(struct hda_codec *codec) 6789 { 6790 struct snd_kcontrol_new knew = 6791 CA0132_CODEC_MUTE_MONO("Full-Range Front Speakers", 6792 SPEAKER_FULL_RANGE_FRONT, 1, HDA_OUTPUT); 6793 6794 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_FRONT, 6795 snd_ctl_new1(&knew, codec)); 6796 } 6797 6798 static int ca0132_alt_add_rear_full_range_switch(struct hda_codec *codec) 6799 { 6800 struct snd_kcontrol_new knew = 6801 CA0132_CODEC_MUTE_MONO("Full-Range Rear Speakers", 6802 SPEAKER_FULL_RANGE_REAR, 1, HDA_OUTPUT); 6803 6804 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_REAR, 6805 snd_ctl_new1(&knew, codec)); 6806 } 6807 6808 /* 6809 * Bass redirection redirects audio below the crossover frequency to the LFE 6810 * channel on speakers that are set as not being full-range. On configurations 6811 * without an LFE channel, it does nothing. Bass redirection seems to be the 6812 * replacement for X-Bass on configurations with an LFE channel. 6813 */ 6814 static int ca0132_alt_add_bass_redirection_crossover(struct hda_codec *codec) 6815 { 6816 const char *namestr = "Bass Redirection Crossover"; 6817 struct snd_kcontrol_new knew = 6818 HDA_CODEC_VOLUME_MONO(namestr, BASS_REDIRECTION_XOVER, 1, 0, 6819 HDA_OUTPUT); 6820 6821 knew.tlv.c = NULL; 6822 knew.info = ca0132_alt_xbass_xover_slider_info; 6823 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 6824 knew.put = ca0132_alt_xbass_xover_slider_put; 6825 6826 return snd_hda_ctl_add(codec, BASS_REDIRECTION_XOVER, 6827 snd_ctl_new1(&knew, codec)); 6828 } 6829 6830 static int ca0132_alt_add_bass_redirection_switch(struct hda_codec *codec) 6831 { 6832 const char *namestr = "Bass Redirection"; 6833 struct snd_kcontrol_new knew = 6834 CA0132_CODEC_MUTE_MONO(namestr, BASS_REDIRECTION, 1, 6835 HDA_OUTPUT); 6836 6837 return snd_hda_ctl_add(codec, BASS_REDIRECTION, 6838 snd_ctl_new1(&knew, codec)); 6839 } 6840 6841 /* 6842 * Create an Input Source enumerated control for the alternate ca0132 codecs 6843 * because the front microphone has no auto-detect, and Line-in has to be set 6844 * somehow. 6845 */ 6846 static int ca0132_alt_add_input_enum(struct hda_codec *codec) 6847 { 6848 struct snd_kcontrol_new knew = 6849 HDA_CODEC_MUTE_MONO("Input Source", 6850 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT); 6851 knew.info = ca0132_alt_input_source_info; 6852 knew.get = ca0132_alt_input_source_get; 6853 knew.put = ca0132_alt_input_source_put; 6854 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM, 6855 snd_ctl_new1(&knew, codec)); 6856 } 6857 6858 /* 6859 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds 6860 * more control than the original mic boost, which is either full 30dB or off. 6861 */ 6862 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec) 6863 { 6864 struct snd_kcontrol_new knew = 6865 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch", 6866 MIC_BOOST_ENUM, 1, 0, HDA_INPUT); 6867 knew.info = ca0132_alt_mic_boost_info; 6868 knew.get = ca0132_alt_mic_boost_get; 6869 knew.put = ca0132_alt_mic_boost_put; 6870 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM, 6871 snd_ctl_new1(&knew, codec)); 6872 6873 } 6874 6875 /* 6876 * Add headphone gain enumerated control for the AE-5. This switches between 6877 * three modes, low, medium, and high. When non-headphone outputs are selected, 6878 * it is automatically set to high. This is the same behavior as Windows. 6879 */ 6880 static int ae5_add_headphone_gain_enum(struct hda_codec *codec) 6881 { 6882 struct snd_kcontrol_new knew = 6883 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain", 6884 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT); 6885 knew.info = ae5_headphone_gain_info; 6886 knew.get = ae5_headphone_gain_get; 6887 knew.put = ae5_headphone_gain_put; 6888 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM, 6889 snd_ctl_new1(&knew, codec)); 6890 } 6891 6892 /* 6893 * Add sound filter enumerated control for the AE-5. This adds three different 6894 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've 6895 * read into it, it changes the DAC's interpolation filter. 6896 */ 6897 static int ae5_add_sound_filter_enum(struct hda_codec *codec) 6898 { 6899 struct snd_kcontrol_new knew = 6900 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter", 6901 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT); 6902 knew.info = ae5_sound_filter_info; 6903 knew.get = ae5_sound_filter_get; 6904 knew.put = ae5_sound_filter_put; 6905 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM, 6906 snd_ctl_new1(&knew, codec)); 6907 } 6908 6909 static int zxr_add_headphone_gain_switch(struct hda_codec *codec) 6910 { 6911 struct snd_kcontrol_new knew = 6912 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain", 6913 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT); 6914 6915 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN, 6916 snd_ctl_new1(&knew, codec)); 6917 } 6918 6919 /* 6920 * Need to create follower controls for the alternate codecs that have surround 6921 * capabilities. 6922 */ 6923 static const char * const ca0132_alt_follower_pfxs[] = { 6924 "Front", "Surround", "Center", "LFE", NULL, 6925 }; 6926 6927 /* 6928 * Also need special channel map, because the default one is incorrect. 6929 * I think this has to do with the pin for rear surround being 0x11, 6930 * and the center/lfe being 0x10. Usually the pin order is the opposite. 6931 */ 6932 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = { 6933 { .channels = 2, 6934 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } }, 6935 { .channels = 4, 6936 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6937 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6938 { .channels = 6, 6939 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6940 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE, 6941 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6942 { } 6943 }; 6944 6945 /* Add the correct chmap for streams with 6 channels. */ 6946 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec) 6947 { 6948 int err = 0; 6949 struct hda_pcm *pcm; 6950 6951 list_for_each_entry(pcm, &codec->pcm_list_head, list) { 6952 struct hda_pcm_stream *hinfo = 6953 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 6954 struct snd_pcm_chmap *chmap; 6955 const struct snd_pcm_chmap_elem *elem; 6956 6957 elem = ca0132_alt_chmaps; 6958 if (hinfo->channels_max == 6) { 6959 err = snd_pcm_add_chmap_ctls(pcm->pcm, 6960 SNDRV_PCM_STREAM_PLAYBACK, 6961 elem, hinfo->channels_max, 0, &chmap); 6962 if (err < 0) 6963 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!"); 6964 } 6965 } 6966 } 6967 6968 /* 6969 * When changing Node IDs for Mixer Controls below, make sure to update 6970 * Node IDs in ca0132_config() as well. 6971 */ 6972 static const struct snd_kcontrol_new ca0132_mixer[] = { 6973 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT), 6974 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT), 6975 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 6976 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6977 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT), 6978 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT), 6979 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6980 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6981 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch", 6982 0x12, 1, HDA_INPUT), 6983 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch", 6984 VNID_HP_SEL, 1, HDA_OUTPUT), 6985 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch", 6986 VNID_AMIC1_SEL, 1, HDA_INPUT), 6987 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6988 VNID_HP_ASEL, 1, HDA_OUTPUT), 6989 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch", 6990 VNID_AMIC1_ASEL, 1, HDA_INPUT), 6991 { } /* end */ 6992 }; 6993 6994 /* 6995 * Desktop specific control mixer. Removes auto-detect for mic, and adds 6996 * surround controls. Also sets both the Front Playback and Capture Volume 6997 * controls to alt so they set the DSP's decibel level. 6998 */ 6999 static const struct snd_kcontrol_new desktop_mixer[] = { 7000 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 7001 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 7002 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 7003 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 7004 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 7005 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 7006 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 7007 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 7008 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT), 7009 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 7010 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 7011 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 7012 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 7013 VNID_HP_ASEL, 1, HDA_OUTPUT), 7014 { } /* end */ 7015 }; 7016 7017 /* 7018 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture 7019 * because it doesn't set decibel levels for the DSP for capture. 7020 */ 7021 static const struct snd_kcontrol_new r3di_mixer[] = { 7022 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 7023 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 7024 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 7025 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 7026 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 7027 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 7028 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 7029 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 7030 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 7031 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 7032 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 7033 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 7034 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 7035 VNID_HP_ASEL, 1, HDA_OUTPUT), 7036 { } /* end */ 7037 }; 7038 7039 static int ca0132_build_controls(struct hda_codec *codec) 7040 { 7041 struct ca0132_spec *spec = codec->spec; 7042 int i, num_fx, num_sliders; 7043 int err = 0; 7044 7045 /* Add Mixer controls */ 7046 for (i = 0; i < spec->num_mixers; i++) { 7047 err = snd_hda_add_new_ctls(codec, spec->mixers[i]); 7048 if (err < 0) 7049 return err; 7050 } 7051 /* Setup vmaster with surround followers for desktop ca0132 devices */ 7052 if (ca0132_use_alt_functions(spec)) { 7053 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT, 7054 spec->tlv); 7055 snd_hda_add_vmaster(codec, "Master Playback Volume", 7056 spec->tlv, ca0132_alt_follower_pfxs, 7057 "Playback Volume", 0); 7058 err = __snd_hda_add_vmaster(codec, "Master Playback Switch", 7059 NULL, ca0132_alt_follower_pfxs, 7060 "Playback Switch", 7061 true, 0, &spec->vmaster_mute.sw_kctl); 7062 if (err < 0) 7063 return err; 7064 } 7065 7066 /* Add in and out effects controls. 7067 * VoiceFX, PE and CrystalVoice are added separately. 7068 */ 7069 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 7070 for (i = 0; i < num_fx; i++) { 7071 /* Desktop cards break if Echo Cancellation is used. */ 7072 if (ca0132_use_pci_mmio(spec)) { 7073 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID + 7074 OUT_EFFECTS_COUNT)) 7075 continue; 7076 } 7077 7078 err = add_fx_switch(codec, ca0132_effects[i].nid, 7079 ca0132_effects[i].name, 7080 ca0132_effects[i].direct); 7081 if (err < 0) 7082 return err; 7083 } 7084 /* 7085 * If codec has use_alt_controls set to true, add effect level sliders, 7086 * EQ presets, and Smart Volume presets. Also, change names to add FX 7087 * prefix, and change PlayEnhancement and CrystalVoice to match. 7088 */ 7089 if (ca0132_use_alt_controls(spec)) { 7090 err = ca0132_alt_add_svm_enum(codec); 7091 if (err < 0) 7092 return err; 7093 7094 err = add_ca0132_alt_eq_presets(codec); 7095 if (err < 0) 7096 return err; 7097 7098 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 7099 "Enable OutFX", 0); 7100 if (err < 0) 7101 return err; 7102 7103 err = add_fx_switch(codec, CRYSTAL_VOICE, 7104 "Enable InFX", 1); 7105 if (err < 0) 7106 return err; 7107 7108 num_sliders = OUT_EFFECTS_COUNT - 1; 7109 for (i = 0; i < num_sliders; i++) { 7110 err = ca0132_alt_add_effect_slider(codec, 7111 ca0132_effects[i].nid, 7112 ca0132_effects[i].name, 7113 ca0132_effects[i].direct); 7114 if (err < 0) 7115 return err; 7116 } 7117 7118 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER, 7119 "X-Bass Crossover", EFX_DIR_OUT); 7120 7121 if (err < 0) 7122 return err; 7123 } else { 7124 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 7125 "PlayEnhancement", 0); 7126 if (err < 0) 7127 return err; 7128 7129 err = add_fx_switch(codec, CRYSTAL_VOICE, 7130 "CrystalVoice", 1); 7131 if (err < 0) 7132 return err; 7133 } 7134 err = add_voicefx(codec); 7135 if (err < 0) 7136 return err; 7137 7138 /* 7139 * If the codec uses alt_functions, you need the enumerated controls 7140 * to select the new outputs and inputs, plus add the new mic boost 7141 * setting control. 7142 */ 7143 if (ca0132_use_alt_functions(spec)) { 7144 err = ca0132_alt_add_output_enum(codec); 7145 if (err < 0) 7146 return err; 7147 err = ca0132_alt_add_speaker_channel_cfg_enum(codec); 7148 if (err < 0) 7149 return err; 7150 err = ca0132_alt_add_front_full_range_switch(codec); 7151 if (err < 0) 7152 return err; 7153 err = ca0132_alt_add_rear_full_range_switch(codec); 7154 if (err < 0) 7155 return err; 7156 err = ca0132_alt_add_bass_redirection_crossover(codec); 7157 if (err < 0) 7158 return err; 7159 err = ca0132_alt_add_bass_redirection_switch(codec); 7160 if (err < 0) 7161 return err; 7162 err = ca0132_alt_add_mic_boost_enum(codec); 7163 if (err < 0) 7164 return err; 7165 /* 7166 * ZxR only has microphone input, there is no front panel 7167 * header on the card, and aux-in is handled by the DBPro board. 7168 */ 7169 if (ca0132_quirk(spec) != QUIRK_ZXR) { 7170 err = ca0132_alt_add_input_enum(codec); 7171 if (err < 0) 7172 return err; 7173 } 7174 } 7175 7176 switch (ca0132_quirk(spec)) { 7177 case QUIRK_AE5: 7178 case QUIRK_AE7: 7179 err = ae5_add_headphone_gain_enum(codec); 7180 if (err < 0) 7181 return err; 7182 err = ae5_add_sound_filter_enum(codec); 7183 if (err < 0) 7184 return err; 7185 break; 7186 case QUIRK_ZXR: 7187 err = zxr_add_headphone_gain_switch(codec); 7188 if (err < 0) 7189 return err; 7190 break; 7191 default: 7192 break; 7193 } 7194 7195 #ifdef ENABLE_TUNING_CONTROLS 7196 add_tuning_ctls(codec); 7197 #endif 7198 7199 err = snd_hda_jack_add_kctls(codec, &spec->autocfg); 7200 if (err < 0) 7201 return err; 7202 7203 if (spec->dig_out) { 7204 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 7205 spec->dig_out); 7206 if (err < 0) 7207 return err; 7208 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout); 7209 if (err < 0) 7210 return err; 7211 /* spec->multiout.share_spdif = 1; */ 7212 } 7213 7214 if (spec->dig_in) { 7215 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 7216 if (err < 0) 7217 return err; 7218 } 7219 7220 if (ca0132_use_alt_functions(spec)) 7221 ca0132_alt_add_chmap_ctls(codec); 7222 7223 return 0; 7224 } 7225 7226 static int dbpro_build_controls(struct hda_codec *codec) 7227 { 7228 struct ca0132_spec *spec = codec->spec; 7229 int err = 0; 7230 7231 if (spec->dig_out) { 7232 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 7233 spec->dig_out); 7234 if (err < 0) 7235 return err; 7236 } 7237 7238 if (spec->dig_in) { 7239 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 7240 if (err < 0) 7241 return err; 7242 } 7243 7244 return 0; 7245 } 7246 7247 /* 7248 * PCM 7249 */ 7250 static const struct hda_pcm_stream ca0132_pcm_analog_playback = { 7251 .substreams = 1, 7252 .channels_min = 2, 7253 .channels_max = 6, 7254 .ops = { 7255 .prepare = ca0132_playback_pcm_prepare, 7256 .cleanup = ca0132_playback_pcm_cleanup, 7257 .get_delay = ca0132_playback_pcm_delay, 7258 }, 7259 }; 7260 7261 static const struct hda_pcm_stream ca0132_pcm_analog_capture = { 7262 .substreams = 1, 7263 .channels_min = 2, 7264 .channels_max = 2, 7265 .ops = { 7266 .prepare = ca0132_capture_pcm_prepare, 7267 .cleanup = ca0132_capture_pcm_cleanup, 7268 .get_delay = ca0132_capture_pcm_delay, 7269 }, 7270 }; 7271 7272 static const struct hda_pcm_stream ca0132_pcm_digital_playback = { 7273 .substreams = 1, 7274 .channels_min = 2, 7275 .channels_max = 2, 7276 .ops = { 7277 .open = ca0132_dig_playback_pcm_open, 7278 .close = ca0132_dig_playback_pcm_close, 7279 .prepare = ca0132_dig_playback_pcm_prepare, 7280 .cleanup = ca0132_dig_playback_pcm_cleanup 7281 }, 7282 }; 7283 7284 static const struct hda_pcm_stream ca0132_pcm_digital_capture = { 7285 .substreams = 1, 7286 .channels_min = 2, 7287 .channels_max = 2, 7288 }; 7289 7290 static int ca0132_build_pcms(struct hda_codec *codec) 7291 { 7292 struct ca0132_spec *spec = codec->spec; 7293 struct hda_pcm *info; 7294 7295 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog"); 7296 if (!info) 7297 return -ENOMEM; 7298 if (ca0132_use_alt_functions(spec)) { 7299 info->own_chmap = true; 7300 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap 7301 = ca0132_alt_chmaps; 7302 } 7303 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback; 7304 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0]; 7305 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max = 7306 spec->multiout.max_channels; 7307 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7308 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7309 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 7310 7311 /* With the DSP enabled, desktops don't use this ADC. */ 7312 if (!ca0132_use_alt_functions(spec)) { 7313 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2"); 7314 if (!info) 7315 return -ENOMEM; 7316 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7317 ca0132_pcm_analog_capture; 7318 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7319 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1]; 7320 } 7321 7322 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear"); 7323 if (!info) 7324 return -ENOMEM; 7325 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7326 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7327 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2]; 7328 7329 if (!spec->dig_out && !spec->dig_in) 7330 return 0; 7331 7332 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 7333 if (!info) 7334 return -ENOMEM; 7335 info->pcm_type = HDA_PCM_TYPE_SPDIF; 7336 if (spec->dig_out) { 7337 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 7338 ca0132_pcm_digital_playback; 7339 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 7340 } 7341 if (spec->dig_in) { 7342 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7343 ca0132_pcm_digital_capture; 7344 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 7345 } 7346 7347 return 0; 7348 } 7349 7350 static int dbpro_build_pcms(struct hda_codec *codec) 7351 { 7352 struct ca0132_spec *spec = codec->spec; 7353 struct hda_pcm *info; 7354 7355 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog"); 7356 if (!info) 7357 return -ENOMEM; 7358 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7359 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7360 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 7361 7362 7363 if (!spec->dig_out && !spec->dig_in) 7364 return 0; 7365 7366 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 7367 if (!info) 7368 return -ENOMEM; 7369 info->pcm_type = HDA_PCM_TYPE_SPDIF; 7370 if (spec->dig_out) { 7371 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 7372 ca0132_pcm_digital_playback; 7373 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 7374 } 7375 if (spec->dig_in) { 7376 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7377 ca0132_pcm_digital_capture; 7378 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 7379 } 7380 7381 return 0; 7382 } 7383 7384 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac) 7385 { 7386 if (pin) { 7387 snd_hda_set_pin_ctl(codec, pin, PIN_HP); 7388 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 7389 snd_hda_codec_write(codec, pin, 0, 7390 AC_VERB_SET_AMP_GAIN_MUTE, 7391 AMP_OUT_UNMUTE); 7392 } 7393 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP)) 7394 snd_hda_codec_write(codec, dac, 0, 7395 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO); 7396 } 7397 7398 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc) 7399 { 7400 if (pin) { 7401 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80); 7402 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP) 7403 snd_hda_codec_write(codec, pin, 0, 7404 AC_VERB_SET_AMP_GAIN_MUTE, 7405 AMP_IN_UNMUTE(0)); 7406 } 7407 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) { 7408 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE, 7409 AMP_IN_UNMUTE(0)); 7410 7411 /* init to 0 dB and unmute. */ 7412 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 7413 HDA_AMP_VOLMASK, 0x5a); 7414 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 7415 HDA_AMP_MUTE, 0); 7416 } 7417 } 7418 7419 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir) 7420 { 7421 unsigned int caps; 7422 7423 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ? 7424 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP); 7425 snd_hda_override_amp_caps(codec, nid, dir, caps); 7426 } 7427 7428 /* 7429 * Switch between Digital built-in mic and analog mic. 7430 */ 7431 static void ca0132_set_dmic(struct hda_codec *codec, int enable) 7432 { 7433 struct ca0132_spec *spec = codec->spec; 7434 unsigned int tmp; 7435 u8 val; 7436 unsigned int oldval; 7437 7438 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable); 7439 7440 oldval = stop_mic1(codec); 7441 ca0132_set_vipsource(codec, 0); 7442 if (enable) { 7443 /* set DMic input as 2-ch */ 7444 tmp = FLOAT_TWO; 7445 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7446 7447 val = spec->dmic_ctl; 7448 val |= 0x80; 7449 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7450 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7451 7452 if (!(spec->dmic_ctl & 0x20)) 7453 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1); 7454 } else { 7455 /* set AMic input as mono */ 7456 tmp = FLOAT_ONE; 7457 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7458 7459 val = spec->dmic_ctl; 7460 /* clear bit7 and bit5 to disable dmic */ 7461 val &= 0x5f; 7462 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7463 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7464 7465 if (!(spec->dmic_ctl & 0x20)) 7466 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0); 7467 } 7468 ca0132_set_vipsource(codec, 1); 7469 resume_mic1(codec, oldval); 7470 } 7471 7472 /* 7473 * Initialization for Digital Mic. 7474 */ 7475 static void ca0132_init_dmic(struct hda_codec *codec) 7476 { 7477 struct ca0132_spec *spec = codec->spec; 7478 u8 val; 7479 7480 /* Setup Digital Mic here, but don't enable. 7481 * Enable based on jack detect. 7482 */ 7483 7484 /* MCLK uses MPIO1, set to enable. 7485 * Bit 2-0: MPIO select 7486 * Bit 3: set to disable 7487 * Bit 7-4: reserved 7488 */ 7489 val = 0x01; 7490 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7491 VENDOR_CHIPIO_DMIC_MCLK_SET, val); 7492 7493 /* Data1 uses MPIO3. Data2 not use 7494 * Bit 2-0: Data1 MPIO select 7495 * Bit 3: set disable Data1 7496 * Bit 6-4: Data2 MPIO select 7497 * Bit 7: set disable Data2 7498 */ 7499 val = 0x83; 7500 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7501 VENDOR_CHIPIO_DMIC_PIN_SET, val); 7502 7503 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first. 7504 * Bit 3-0: Channel mask 7505 * Bit 4: set for 48KHz, clear for 32KHz 7506 * Bit 5: mode 7507 * Bit 6: set to select Data2, clear for Data1 7508 * Bit 7: set to enable DMic, clear for AMic 7509 */ 7510 if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4) 7511 val = 0x33; 7512 else 7513 val = 0x23; 7514 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */ 7515 spec->dmic_ctl = val; 7516 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7517 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7518 } 7519 7520 /* 7521 * Initialization for Analog Mic 2 7522 */ 7523 static void ca0132_init_analog_mic2(struct hda_codec *codec) 7524 { 7525 struct ca0132_spec *spec = codec->spec; 7526 7527 mutex_lock(&spec->chipio_mutex); 7528 7529 chipio_8051_write_exram_no_mutex(codec, 0x1920, 0x00); 7530 chipio_8051_write_exram_no_mutex(codec, 0x192d, 0x00); 7531 7532 mutex_unlock(&spec->chipio_mutex); 7533 } 7534 7535 static void ca0132_refresh_widget_caps(struct hda_codec *codec) 7536 { 7537 struct ca0132_spec *spec = codec->spec; 7538 int i; 7539 7540 codec_dbg(codec, "ca0132_refresh_widget_caps.\n"); 7541 snd_hda_codec_update_widgets(codec); 7542 7543 for (i = 0; i < spec->multiout.num_dacs; i++) 7544 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT); 7545 7546 for (i = 0; i < spec->num_outputs; i++) 7547 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT); 7548 7549 for (i = 0; i < spec->num_inputs; i++) { 7550 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT); 7551 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT); 7552 } 7553 } 7554 7555 7556 /* If there is an active channel for some reason, find it and free it. */ 7557 static void ca0132_alt_free_active_dma_channels(struct hda_codec *codec) 7558 { 7559 unsigned int i, tmp; 7560 int status; 7561 7562 /* Read active DSPDMAC channel register. */ 7563 status = chipio_read(codec, DSPDMAC_CHNLSTART_MODULE_OFFSET, &tmp); 7564 if (status >= 0) { 7565 /* AND against 0xfff to get the active channel bits. */ 7566 tmp = tmp & 0xfff; 7567 7568 /* If there are no active channels, nothing to free. */ 7569 if (!tmp) 7570 return; 7571 } else { 7572 codec_dbg(codec, "%s: Failed to read active DSP DMA channel register.\n", 7573 __func__); 7574 return; 7575 } 7576 7577 /* 7578 * Check each DSP DMA channel for activity, and if the channel is 7579 * active, free it. 7580 */ 7581 for (i = 0; i < DSPDMAC_DMA_CFG_CHANNEL_COUNT; i++) { 7582 if (dsp_is_dma_active(codec, i)) { 7583 status = dspio_free_dma_chan(codec, i); 7584 if (status < 0) 7585 codec_dbg(codec, "%s: Failed to free active DSP DMA channel %d.\n", 7586 __func__, i); 7587 } 7588 } 7589 } 7590 7591 /* 7592 * In the case of CT_EXTENSIONS_ENABLE being set to 1, and the DSP being in 7593 * use, audio is no longer routed directly to the DAC/ADC from the HDA stream. 7594 * Instead, audio is now routed through the DSP's DMA controllers, which 7595 * the DSP is tasked with setting up itself. Through debugging, it seems the 7596 * cause of most of the no-audio on startup issues were due to improperly 7597 * configured DSP DMA channels. 7598 * 7599 * Normally, the DSP configures these the first time an HDA audio stream is 7600 * started post DSP firmware download. That is why creating a 'dummy' stream 7601 * worked in fixing the audio in some cases. This works most of the time, but 7602 * sometimes if a stream is started/stopped before the DSP can setup the DMA 7603 * configuration registers, it ends up in a broken state. Issues can also 7604 * arise if streams are started in an unusual order, i.e the audio output dma 7605 * channel being sandwiched between the mic1 and mic2 dma channels. 7606 * 7607 * The solution to this is to make sure that the DSP has no DMA channels 7608 * in use post DSP firmware download, and then to manually start each default 7609 * DSP stream that uses the DMA channels. These are 0x0c, the audio output 7610 * stream, 0x03, analog mic 1, and 0x04, analog mic 2. 7611 */ 7612 static void ca0132_alt_start_dsp_audio_streams(struct hda_codec *codec) 7613 { 7614 static const unsigned int dsp_dma_stream_ids[] = { 0x0c, 0x03, 0x04 }; 7615 struct ca0132_spec *spec = codec->spec; 7616 unsigned int i, tmp; 7617 7618 /* 7619 * Check if any of the default streams are active, and if they are, 7620 * stop them. 7621 */ 7622 mutex_lock(&spec->chipio_mutex); 7623 7624 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) { 7625 chipio_get_stream_control(codec, dsp_dma_stream_ids[i], &tmp); 7626 7627 if (tmp) { 7628 chipio_set_stream_control(codec, 7629 dsp_dma_stream_ids[i], 0); 7630 } 7631 } 7632 7633 mutex_unlock(&spec->chipio_mutex); 7634 7635 /* 7636 * If all DSP streams are inactive, there should be no active DSP DMA 7637 * channels. Check and make sure this is the case, and if it isn't, 7638 * free any active channels. 7639 */ 7640 ca0132_alt_free_active_dma_channels(codec); 7641 7642 mutex_lock(&spec->chipio_mutex); 7643 7644 /* Make sure stream 0x0c is six channels. */ 7645 chipio_set_stream_channels(codec, 0x0c, 6); 7646 7647 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) { 7648 chipio_set_stream_control(codec, 7649 dsp_dma_stream_ids[i], 1); 7650 7651 /* Give the DSP some time to setup the DMA channel. */ 7652 msleep(75); 7653 } 7654 7655 mutex_unlock(&spec->chipio_mutex); 7656 } 7657 7658 /* 7659 * The region of ChipIO memory from 0x190000-0x1903fc is a sort of 'audio 7660 * router', where each entry represents a 48khz audio channel, with a format 7661 * of an 8-bit destination, an 8-bit source, and an unknown 2-bit number 7662 * value. The 2-bit number value is seemingly 0 if inactive, 1 if active, 7663 * and 3 if it's using Sample Rate Converter ports. 7664 * An example is: 7665 * 0x0001f8c0 7666 * In this case, f8 is the destination, and c0 is the source. The number value 7667 * is 1. 7668 * This region of memory is normally managed internally by the 8051, where 7669 * the region of exram memory from 0x1477-0x1575 has each byte represent an 7670 * entry within the 0x190000 range, and when a range of entries is in use, the 7671 * ending value is overwritten with 0xff. 7672 * 0x1578 in exram is a table of 0x25 entries, corresponding to the ChipIO 7673 * streamID's, where each entry is a starting 0x190000 port offset. 7674 * 0x159d in exram is the same as 0x1578, except it contains the ending port 7675 * offset for the corresponding streamID. 7676 * 7677 * On certain cards, such as the SBZ/ZxR/AE7, these are originally setup by 7678 * the 8051, then manually overwritten to remap the ports to work with the 7679 * new DACs. 7680 * 7681 * Currently known portID's: 7682 * 0x00-0x1f: HDA audio stream input/output ports. 7683 * 0x80-0xbf: Sample rate converter input/outputs. Only valid ports seem to 7684 * have the lower-nibble set to 0x1, 0x2, and 0x9. 7685 * 0xc0-0xdf: DSP DMA input/output ports. Dynamically assigned. 7686 * 0xe0-0xff: DAC/ADC audio input/output ports. 7687 * 7688 * Currently known streamID's: 7689 * 0x03: Mic1 ADC to DSP. 7690 * 0x04: Mic2 ADC to DSP. 7691 * 0x05: HDA node 0x02 audio stream to DSP. 7692 * 0x0f: DSP Mic exit to HDA node 0x07. 7693 * 0x0c: DSP processed audio to DACs. 7694 * 0x14: DAC0, front L/R. 7695 * 7696 * It is possible to route the HDA audio streams directly to the DAC and 7697 * bypass the DSP entirely, with the only downside being that since the DSP 7698 * does volume control, the only volume control you'll get is through PCM on 7699 * the PC side, in the same way volume is handled for optical out. This may be 7700 * useful for debugging. 7701 */ 7702 static void chipio_remap_stream(struct hda_codec *codec, 7703 const struct chipio_stream_remap_data *remap_data) 7704 { 7705 unsigned int i, stream_offset; 7706 7707 /* Get the starting port for the stream to be remapped. */ 7708 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id, 7709 &stream_offset); 7710 7711 /* 7712 * Check if the stream's port value is 0xff, because the 8051 may not 7713 * have gotten around to setting up the stream yet. Wait until it's 7714 * setup to remap it's ports. 7715 */ 7716 if (stream_offset == 0xff) { 7717 for (i = 0; i < 5; i++) { 7718 msleep(25); 7719 7720 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id, 7721 &stream_offset); 7722 7723 if (stream_offset != 0xff) 7724 break; 7725 } 7726 } 7727 7728 if (stream_offset == 0xff) { 7729 codec_info(codec, "%s: Stream 0x%02x ports aren't allocated, remap failed!\n", 7730 __func__, remap_data->stream_id); 7731 return; 7732 } 7733 7734 /* Offset isn't in bytes, its in 32-bit words, so multiply it by 4. */ 7735 stream_offset *= 0x04; 7736 stream_offset += 0x190000; 7737 7738 for (i = 0; i < remap_data->count; i++) { 7739 chipio_write_no_mutex(codec, 7740 stream_offset + remap_data->offset[i], 7741 remap_data->value[i]); 7742 } 7743 7744 /* Update stream map configuration. */ 7745 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 7746 } 7747 7748 /* 7749 * Default speaker tuning values setup for alternative codecs. 7750 */ 7751 static const unsigned int sbz_default_delay_values[] = { 7752 /* Non-zero values are floating point 0.000198. */ 7753 0x394f9e38, 0x394f9e38, 0x00000000, 0x00000000, 0x00000000, 0x00000000 7754 }; 7755 7756 static const unsigned int zxr_default_delay_values[] = { 7757 /* Non-zero values are floating point 0.000220. */ 7758 0x00000000, 0x00000000, 0x3966afcd, 0x3966afcd, 0x3966afcd, 0x3966afcd 7759 }; 7760 7761 static const unsigned int ae5_default_delay_values[] = { 7762 /* Non-zero values are floating point 0.000100. */ 7763 0x00000000, 0x00000000, 0x38d1b717, 0x38d1b717, 0x38d1b717, 0x38d1b717 7764 }; 7765 7766 /* 7767 * If we never change these, probably only need them on initialization. 7768 */ 7769 static void ca0132_alt_init_speaker_tuning(struct hda_codec *codec) 7770 { 7771 struct ca0132_spec *spec = codec->spec; 7772 unsigned int i, tmp, start_req, end_req; 7773 const unsigned int *values; 7774 7775 switch (ca0132_quirk(spec)) { 7776 case QUIRK_SBZ: 7777 values = sbz_default_delay_values; 7778 break; 7779 case QUIRK_ZXR: 7780 values = zxr_default_delay_values; 7781 break; 7782 case QUIRK_AE5: 7783 case QUIRK_AE7: 7784 values = ae5_default_delay_values; 7785 break; 7786 default: 7787 values = sbz_default_delay_values; 7788 break; 7789 } 7790 7791 tmp = FLOAT_ZERO; 7792 dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_ENABLE_CENTER_EQ, tmp); 7793 7794 start_req = SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL; 7795 end_req = SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL; 7796 for (i = start_req; i < end_req + 1; i++) 7797 dspio_set_uint_param(codec, 0x96, i, tmp); 7798 7799 start_req = SPEAKER_TUNING_FRONT_LEFT_INVERT; 7800 end_req = SPEAKER_TUNING_REAR_RIGHT_INVERT; 7801 for (i = start_req; i < end_req + 1; i++) 7802 dspio_set_uint_param(codec, 0x96, i, tmp); 7803 7804 7805 for (i = 0; i < 6; i++) 7806 dspio_set_uint_param(codec, 0x96, 7807 SPEAKER_TUNING_FRONT_LEFT_DELAY + i, values[i]); 7808 } 7809 7810 /* 7811 * Initialize mic for non-chromebook ca0132 implementations. 7812 */ 7813 static void ca0132_alt_init_analog_mics(struct hda_codec *codec) 7814 { 7815 struct ca0132_spec *spec = codec->spec; 7816 unsigned int tmp; 7817 7818 /* Mic 1 Setup */ 7819 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7820 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7821 if (ca0132_quirk(spec) == QUIRK_R3DI) { 7822 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 7823 tmp = FLOAT_ONE; 7824 } else 7825 tmp = FLOAT_THREE; 7826 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7827 7828 /* Mic 2 setup (not present on desktop cards) */ 7829 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000); 7830 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000); 7831 if (ca0132_quirk(spec) == QUIRK_R3DI) 7832 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 7833 tmp = FLOAT_ZERO; 7834 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 7835 } 7836 7837 /* 7838 * Sets the source of stream 0x14 to connpointID 0x48, and the destination 7839 * connpointID to 0x91. If this isn't done, the destination is 0x71, and 7840 * you get no sound. I'm guessing this has to do with the Sound Blaster Z 7841 * having an updated DAC, which changes the destination to that DAC. 7842 */ 7843 static void sbz_connect_streams(struct hda_codec *codec) 7844 { 7845 struct ca0132_spec *spec = codec->spec; 7846 7847 mutex_lock(&spec->chipio_mutex); 7848 7849 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n"); 7850 7851 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */ 7852 chipio_write_no_mutex(codec, 0x18a020, 0x00000043); 7853 7854 /* Setup stream 0x14 with it's source and destination points */ 7855 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91); 7856 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000); 7857 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000); 7858 chipio_set_stream_channels(codec, 0x14, 2); 7859 chipio_set_stream_control(codec, 0x14, 1); 7860 7861 codec_dbg(codec, "Connect Streams exited, mutex released.\n"); 7862 7863 mutex_unlock(&spec->chipio_mutex); 7864 } 7865 7866 /* 7867 * Write data through ChipIO to setup proper stream destinations. 7868 * Not sure how it exactly works, but it seems to direct data 7869 * to different destinations. Example is f8 to c0, e0 to c0. 7870 * All I know is, if you don't set these, you get no sound. 7871 */ 7872 static void sbz_chipio_startup_data(struct hda_codec *codec) 7873 { 7874 const struct chipio_stream_remap_data *dsp_out_remap_data; 7875 struct ca0132_spec *spec = codec->spec; 7876 7877 mutex_lock(&spec->chipio_mutex); 7878 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n"); 7879 7880 /* Remap DAC0's output ports. */ 7881 chipio_remap_stream(codec, &stream_remap_data[0]); 7882 7883 /* Remap DSP audio output stream ports. */ 7884 switch (ca0132_quirk(spec)) { 7885 case QUIRK_SBZ: 7886 dsp_out_remap_data = &stream_remap_data[1]; 7887 break; 7888 7889 case QUIRK_ZXR: 7890 dsp_out_remap_data = &stream_remap_data[2]; 7891 break; 7892 7893 default: 7894 dsp_out_remap_data = NULL; 7895 break; 7896 } 7897 7898 if (dsp_out_remap_data) 7899 chipio_remap_stream(codec, dsp_out_remap_data); 7900 7901 codec_dbg(codec, "Startup Data exited, mutex released.\n"); 7902 mutex_unlock(&spec->chipio_mutex); 7903 } 7904 7905 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec) 7906 { 7907 struct ca0132_spec *spec = codec->spec; 7908 unsigned int tmp; 7909 7910 chipio_set_stream_control(codec, 0x03, 0); 7911 chipio_set_stream_control(codec, 0x04, 0); 7912 7913 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7914 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7915 7916 tmp = FLOAT_THREE; 7917 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7918 7919 chipio_set_stream_control(codec, 0x03, 1); 7920 chipio_set_stream_control(codec, 0x04, 1); 7921 7922 switch (ca0132_quirk(spec)) { 7923 case QUIRK_SBZ: 7924 chipio_write(codec, 0x18b098, 0x0000000c); 7925 chipio_write(codec, 0x18b09C, 0x0000000c); 7926 break; 7927 case QUIRK_AE5: 7928 chipio_write(codec, 0x18b098, 0x0000000c); 7929 chipio_write(codec, 0x18b09c, 0x0000004c); 7930 break; 7931 default: 7932 break; 7933 } 7934 } 7935 7936 static void ae5_post_dsp_register_set(struct hda_codec *codec) 7937 { 7938 struct ca0132_spec *spec = codec->spec; 7939 7940 chipio_8051_write_direct(codec, 0x93, 0x10); 7941 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); 7942 7943 writeb(0xff, spec->mem_base + 0x304); 7944 writeb(0xff, spec->mem_base + 0x304); 7945 writeb(0xff, spec->mem_base + 0x304); 7946 writeb(0xff, spec->mem_base + 0x304); 7947 writeb(0x00, spec->mem_base + 0x100); 7948 writeb(0xff, spec->mem_base + 0x304); 7949 writeb(0x00, spec->mem_base + 0x100); 7950 writeb(0xff, spec->mem_base + 0x304); 7951 writeb(0x00, spec->mem_base + 0x100); 7952 writeb(0xff, spec->mem_base + 0x304); 7953 writeb(0x00, spec->mem_base + 0x100); 7954 writeb(0xff, spec->mem_base + 0x304); 7955 7956 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f); 7957 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 7958 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7959 } 7960 7961 static void ae5_post_dsp_param_setup(struct hda_codec *codec) 7962 { 7963 /* 7964 * Param3 in the 8051's memory is represented by the ascii string 'mch' 7965 * which seems to be 'multichannel'. This is also mentioned in the 7966 * AE-5's registry values in Windows. 7967 */ 7968 chipio_set_control_param(codec, 3, 0); 7969 /* 7970 * I believe ASI is 'audio serial interface' and that it's used to 7971 * change colors on the external LED strip connected to the AE-5. 7972 */ 7973 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); 7974 7975 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); 7976 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 7977 7978 chipio_8051_write_exram(codec, 0xfa92, 0x22); 7979 } 7980 7981 static void ae5_post_dsp_pll_setup(struct hda_codec *codec) 7982 { 7983 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8); 7984 chipio_8051_write_pll_pmu(codec, 0x45, 0xcc); 7985 chipio_8051_write_pll_pmu(codec, 0x40, 0xcb); 7986 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7); 7987 chipio_8051_write_pll_pmu(codec, 0x51, 0x8d); 7988 } 7989 7990 static void ae5_post_dsp_stream_setup(struct hda_codec *codec) 7991 { 7992 struct ca0132_spec *spec = codec->spec; 7993 7994 mutex_lock(&spec->chipio_mutex); 7995 7996 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); 7997 7998 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); 7999 8000 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0); 8001 8002 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0); 8003 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 8004 chipio_set_stream_channels(codec, 0x18, 6); 8005 chipio_set_stream_control(codec, 0x18, 1); 8006 8007 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); 8008 8009 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7); 8010 8011 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80); 8012 8013 mutex_unlock(&spec->chipio_mutex); 8014 } 8015 8016 static void ae5_post_dsp_startup_data(struct hda_codec *codec) 8017 { 8018 struct ca0132_spec *spec = codec->spec; 8019 8020 mutex_lock(&spec->chipio_mutex); 8021 8022 chipio_write_no_mutex(codec, 0x189000, 0x0001f101); 8023 chipio_write_no_mutex(codec, 0x189004, 0x0001f101); 8024 chipio_write_no_mutex(codec, 0x189024, 0x00014004); 8025 chipio_write_no_mutex(codec, 0x189028, 0x0002000f); 8026 8027 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 8028 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 8029 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12); 8030 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00); 8031 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48); 8032 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 8033 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8034 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8035 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8036 ca0113_mmio_gpio_set(codec, 0, true); 8037 ca0113_mmio_gpio_set(codec, 1, true); 8038 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80); 8039 8040 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012); 8041 8042 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8043 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8044 8045 mutex_unlock(&spec->chipio_mutex); 8046 } 8047 8048 static void ae7_post_dsp_setup_ports(struct hda_codec *codec) 8049 { 8050 struct ca0132_spec *spec = codec->spec; 8051 8052 mutex_lock(&spec->chipio_mutex); 8053 8054 /* Seems to share the same port remapping as the SBZ. */ 8055 chipio_remap_stream(codec, &stream_remap_data[1]); 8056 8057 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 8058 ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40); 8059 ca0113_mmio_command_set(codec, 0x48, 0x17, 0x00); 8060 ca0113_mmio_command_set(codec, 0x48, 0x19, 0x00); 8061 ca0113_mmio_command_set(codec, 0x48, 0x11, 0xff); 8062 ca0113_mmio_command_set(codec, 0x48, 0x12, 0xff); 8063 ca0113_mmio_command_set(codec, 0x48, 0x13, 0xff); 8064 ca0113_mmio_command_set(codec, 0x48, 0x14, 0x7f); 8065 8066 mutex_unlock(&spec->chipio_mutex); 8067 } 8068 8069 static void ae7_post_dsp_asi_stream_setup(struct hda_codec *codec) 8070 { 8071 struct ca0132_spec *spec = codec->spec; 8072 8073 mutex_lock(&spec->chipio_mutex); 8074 8075 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); 8076 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 8077 8078 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); 8079 8080 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00); 8081 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0); 8082 8083 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 8084 chipio_set_stream_channels(codec, 0x18, 6); 8085 chipio_set_stream_control(codec, 0x18, 1); 8086 8087 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); 8088 8089 mutex_unlock(&spec->chipio_mutex); 8090 } 8091 8092 static void ae7_post_dsp_pll_setup(struct hda_codec *codec) 8093 { 8094 static const unsigned int addr[] = { 8095 0x41, 0x45, 0x40, 0x43, 0x51 8096 }; 8097 static const unsigned int data[] = { 8098 0xc8, 0xcc, 0xcb, 0xc7, 0x8d 8099 }; 8100 unsigned int i; 8101 8102 for (i = 0; i < ARRAY_SIZE(addr); i++) 8103 chipio_8051_write_pll_pmu_no_mutex(codec, addr[i], data[i]); 8104 } 8105 8106 static void ae7_post_dsp_asi_setup_ports(struct hda_codec *codec) 8107 { 8108 struct ca0132_spec *spec = codec->spec; 8109 static const unsigned int target[] = { 8110 0x0b, 0x04, 0x06, 0x0a, 0x0c, 0x11, 0x12, 0x13, 0x14 8111 }; 8112 static const unsigned int data[] = { 8113 0x12, 0x00, 0x48, 0x05, 0x5f, 0xff, 0xff, 0xff, 0x7f 8114 }; 8115 unsigned int i; 8116 8117 mutex_lock(&spec->chipio_mutex); 8118 8119 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7); 8120 8121 chipio_write_no_mutex(codec, 0x189000, 0x0001f101); 8122 chipio_write_no_mutex(codec, 0x189004, 0x0001f101); 8123 chipio_write_no_mutex(codec, 0x189024, 0x00014004); 8124 chipio_write_no_mutex(codec, 0x189028, 0x0002000f); 8125 8126 ae7_post_dsp_pll_setup(codec); 8127 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 8128 8129 for (i = 0; i < ARRAY_SIZE(target); i++) 8130 ca0113_mmio_command_set(codec, 0x48, target[i], data[i]); 8131 8132 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8133 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8134 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8135 8136 chipio_set_stream_source_dest(codec, 0x21, 0x64, 0x56); 8137 chipio_set_stream_channels(codec, 0x21, 2); 8138 chipio_set_conn_rate_no_mutex(codec, 0x56, SR_8_000); 8139 8140 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_NODE_ID, 0x09); 8141 /* 8142 * In the 8051's memory, this param is referred to as 'n2sid', which I 8143 * believe is 'node to streamID'. It seems to be a way to assign a 8144 * stream to a given HDA node. 8145 */ 8146 chipio_set_control_param_no_mutex(codec, 0x20, 0x21); 8147 8148 chipio_write_no_mutex(codec, 0x18b038, 0x00000088); 8149 8150 /* 8151 * Now, at this point on Windows, an actual stream is setup and 8152 * seemingly sends data to the HDA node 0x09, which is the digital 8153 * audio input node. This is left out here, because obviously I don't 8154 * know what data is being sent. Interestingly, the AE-5 seems to go 8155 * through the motions of getting here and never actually takes this 8156 * step, but the AE-7 does. 8157 */ 8158 8159 ca0113_mmio_gpio_set(codec, 0, 1); 8160 ca0113_mmio_gpio_set(codec, 1, 1); 8161 8162 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8163 chipio_write_no_mutex(codec, 0x18b03c, 0x00000000); 8164 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8165 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8166 8167 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00); 8168 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0); 8169 8170 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 8171 chipio_set_stream_channels(codec, 0x18, 6); 8172 8173 /* 8174 * Runs again, this has been repeated a few times, but I'm just 8175 * following what the Windows driver does. 8176 */ 8177 ae7_post_dsp_pll_setup(codec); 8178 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 8179 8180 mutex_unlock(&spec->chipio_mutex); 8181 } 8182 8183 /* 8184 * The Windows driver has commands that seem to setup ASI, which I believe to 8185 * be some sort of audio serial interface. My current speculation is that it's 8186 * related to communicating with the new DAC. 8187 */ 8188 static void ae7_post_dsp_asi_setup(struct hda_codec *codec) 8189 { 8190 chipio_8051_write_direct(codec, 0x93, 0x10); 8191 8192 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); 8193 8194 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8195 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8196 8197 chipio_set_control_param(codec, 3, 3); 8198 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); 8199 8200 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); 8201 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 8202 snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00); 8203 8204 chipio_8051_write_exram(codec, 0xfa92, 0x22); 8205 8206 ae7_post_dsp_pll_setup(codec); 8207 ae7_post_dsp_asi_stream_setup(codec); 8208 8209 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7); 8210 8211 ae7_post_dsp_asi_setup_ports(codec); 8212 } 8213 8214 /* 8215 * Setup default parameters for DSP 8216 */ 8217 static void ca0132_setup_defaults(struct hda_codec *codec) 8218 { 8219 struct ca0132_spec *spec = codec->spec; 8220 unsigned int tmp; 8221 int num_fx; 8222 int idx, i; 8223 8224 if (spec->dsp_state != DSP_DOWNLOADED) 8225 return; 8226 8227 /* out, in effects + voicefx */ 8228 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8229 for (idx = 0; idx < num_fx; idx++) { 8230 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8231 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 8232 ca0132_effects[idx].reqs[i], 8233 ca0132_effects[idx].def_vals[i]); 8234 } 8235 } 8236 8237 /*remove DSP headroom*/ 8238 tmp = FLOAT_ZERO; 8239 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8240 8241 /*set speaker EQ bypass attenuation*/ 8242 dspio_set_uint_param(codec, 0x8f, 0x01, tmp); 8243 8244 /* set AMic1 and AMic2 as mono mic */ 8245 tmp = FLOAT_ONE; 8246 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 8247 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 8248 8249 /* set AMic1 as CrystalVoice input */ 8250 tmp = FLOAT_ONE; 8251 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 8252 8253 /* set WUH source */ 8254 tmp = FLOAT_TWO; 8255 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8256 } 8257 8258 /* 8259 * Setup default parameters for Recon3D/Recon3Di DSP. 8260 */ 8261 8262 static void r3d_setup_defaults(struct hda_codec *codec) 8263 { 8264 struct ca0132_spec *spec = codec->spec; 8265 unsigned int tmp; 8266 int num_fx; 8267 int idx, i; 8268 8269 if (spec->dsp_state != DSP_DOWNLOADED) 8270 return; 8271 8272 ca0132_alt_init_analog_mics(codec); 8273 ca0132_alt_start_dsp_audio_streams(codec); 8274 8275 /*remove DSP headroom*/ 8276 tmp = FLOAT_ZERO; 8277 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8278 8279 /* set WUH source */ 8280 tmp = FLOAT_TWO; 8281 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8282 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8283 8284 /* Set speaker source? */ 8285 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8286 8287 if (ca0132_quirk(spec) == QUIRK_R3DI) 8288 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED); 8289 8290 /* Disable mute on Center/LFE. */ 8291 if (ca0132_quirk(spec) == QUIRK_R3D) { 8292 ca0113_mmio_gpio_set(codec, 2, false); 8293 ca0113_mmio_gpio_set(codec, 4, true); 8294 } 8295 8296 /* Setup effect defaults */ 8297 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8298 for (idx = 0; idx < num_fx; idx++) { 8299 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8300 dspio_set_uint_param(codec, 8301 ca0132_effects[idx].mid, 8302 ca0132_effects[idx].reqs[i], 8303 ca0132_effects[idx].def_vals[i]); 8304 } 8305 } 8306 } 8307 8308 /* 8309 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on 8310 * than the Chromebook setup. 8311 */ 8312 static void sbz_setup_defaults(struct hda_codec *codec) 8313 { 8314 struct ca0132_spec *spec = codec->spec; 8315 unsigned int tmp; 8316 int num_fx; 8317 int idx, i; 8318 8319 if (spec->dsp_state != DSP_DOWNLOADED) 8320 return; 8321 8322 ca0132_alt_init_analog_mics(codec); 8323 ca0132_alt_start_dsp_audio_streams(codec); 8324 sbz_connect_streams(codec); 8325 sbz_chipio_startup_data(codec); 8326 8327 /* 8328 * Sets internal input loopback to off, used to have a switch to 8329 * enable input loopback, but turned out to be way too buggy. 8330 */ 8331 tmp = FLOAT_ONE; 8332 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8333 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8334 8335 /*remove DSP headroom*/ 8336 tmp = FLOAT_ZERO; 8337 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8338 8339 /* set WUH source */ 8340 tmp = FLOAT_TWO; 8341 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8342 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8343 8344 /* Set speaker source? */ 8345 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8346 8347 ca0132_alt_dsp_initial_mic_setup(codec); 8348 8349 /* out, in effects + voicefx */ 8350 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8351 for (idx = 0; idx < num_fx; idx++) { 8352 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8353 dspio_set_uint_param(codec, 8354 ca0132_effects[idx].mid, 8355 ca0132_effects[idx].reqs[i], 8356 ca0132_effects[idx].def_vals[i]); 8357 } 8358 } 8359 8360 ca0132_alt_init_speaker_tuning(codec); 8361 } 8362 8363 /* 8364 * Setup default parameters for the Sound BlasterX AE-5 DSP. 8365 */ 8366 static void ae5_setup_defaults(struct hda_codec *codec) 8367 { 8368 struct ca0132_spec *spec = codec->spec; 8369 unsigned int tmp; 8370 int num_fx; 8371 int idx, i; 8372 8373 if (spec->dsp_state != DSP_DOWNLOADED) 8374 return; 8375 8376 ca0132_alt_init_analog_mics(codec); 8377 ca0132_alt_start_dsp_audio_streams(codec); 8378 8379 /* New, unknown SCP req's */ 8380 tmp = FLOAT_ZERO; 8381 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 8382 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 8383 dspio_set_uint_param(codec, 0x80, 0x0d, tmp); 8384 dspio_set_uint_param(codec, 0x80, 0x0e, tmp); 8385 8386 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8387 ca0113_mmio_gpio_set(codec, 0, false); 8388 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 8389 8390 /* Internal loopback off */ 8391 tmp = FLOAT_ONE; 8392 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8393 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8394 8395 /*remove DSP headroom*/ 8396 tmp = FLOAT_ZERO; 8397 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8398 8399 /* set WUH source */ 8400 tmp = FLOAT_TWO; 8401 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8402 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8403 8404 /* Set speaker source? */ 8405 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8406 8407 ca0132_alt_dsp_initial_mic_setup(codec); 8408 ae5_post_dsp_register_set(codec); 8409 ae5_post_dsp_param_setup(codec); 8410 ae5_post_dsp_pll_setup(codec); 8411 ae5_post_dsp_stream_setup(codec); 8412 ae5_post_dsp_startup_data(codec); 8413 8414 /* out, in effects + voicefx */ 8415 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8416 for (idx = 0; idx < num_fx; idx++) { 8417 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8418 dspio_set_uint_param(codec, 8419 ca0132_effects[idx].mid, 8420 ca0132_effects[idx].reqs[i], 8421 ca0132_effects[idx].def_vals[i]); 8422 } 8423 } 8424 8425 ca0132_alt_init_speaker_tuning(codec); 8426 } 8427 8428 /* 8429 * Setup default parameters for the Sound Blaster AE-7 DSP. 8430 */ 8431 static void ae7_setup_defaults(struct hda_codec *codec) 8432 { 8433 struct ca0132_spec *spec = codec->spec; 8434 unsigned int tmp; 8435 int num_fx; 8436 int idx, i; 8437 8438 if (spec->dsp_state != DSP_DOWNLOADED) 8439 return; 8440 8441 ca0132_alt_init_analog_mics(codec); 8442 ca0132_alt_start_dsp_audio_streams(codec); 8443 ae7_post_dsp_setup_ports(codec); 8444 8445 tmp = FLOAT_ZERO; 8446 dspio_set_uint_param(codec, 0x96, 8447 SPEAKER_TUNING_FRONT_LEFT_INVERT, tmp); 8448 dspio_set_uint_param(codec, 0x96, 8449 SPEAKER_TUNING_FRONT_RIGHT_INVERT, tmp); 8450 8451 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8452 8453 /* New, unknown SCP req's */ 8454 dspio_set_uint_param(codec, 0x80, 0x0d, tmp); 8455 dspio_set_uint_param(codec, 0x80, 0x0e, tmp); 8456 8457 ca0113_mmio_gpio_set(codec, 0, false); 8458 8459 /* Internal loopback off */ 8460 tmp = FLOAT_ONE; 8461 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8462 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8463 8464 /*remove DSP headroom*/ 8465 tmp = FLOAT_ZERO; 8466 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8467 8468 /* set WUH source */ 8469 tmp = FLOAT_TWO; 8470 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8471 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8472 8473 /* Set speaker source? */ 8474 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8475 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 8476 8477 /* 8478 * This is the second time we've called this, but this is seemingly 8479 * what Windows does. 8480 */ 8481 ca0132_alt_init_analog_mics(codec); 8482 8483 ae7_post_dsp_asi_setup(codec); 8484 8485 /* 8486 * Not sure why, but these are both set to 1. They're only set to 0 8487 * upon shutdown. 8488 */ 8489 ca0113_mmio_gpio_set(codec, 0, true); 8490 ca0113_mmio_gpio_set(codec, 1, true); 8491 8492 /* Volume control related. */ 8493 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x04); 8494 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x04); 8495 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x80); 8496 8497 /* out, in effects + voicefx */ 8498 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8499 for (idx = 0; idx < num_fx; idx++) { 8500 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8501 dspio_set_uint_param(codec, 8502 ca0132_effects[idx].mid, 8503 ca0132_effects[idx].reqs[i], 8504 ca0132_effects[idx].def_vals[i]); 8505 } 8506 } 8507 8508 ca0132_alt_init_speaker_tuning(codec); 8509 } 8510 8511 /* 8512 * Initialization of flags in chip 8513 */ 8514 static void ca0132_init_flags(struct hda_codec *codec) 8515 { 8516 struct ca0132_spec *spec = codec->spec; 8517 8518 if (ca0132_use_alt_functions(spec)) { 8519 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1); 8520 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1); 8521 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1); 8522 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1); 8523 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1); 8524 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8525 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0); 8526 chipio_set_control_flag(codec, 8527 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 8528 chipio_set_control_flag(codec, 8529 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1); 8530 } else { 8531 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8532 chipio_set_control_flag(codec, 8533 CONTROL_FLAG_PORT_A_COMMON_MODE, 0); 8534 chipio_set_control_flag(codec, 8535 CONTROL_FLAG_PORT_D_COMMON_MODE, 0); 8536 chipio_set_control_flag(codec, 8537 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0); 8538 chipio_set_control_flag(codec, 8539 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 8540 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1); 8541 } 8542 } 8543 8544 /* 8545 * Initialization of parameters in chip 8546 */ 8547 static void ca0132_init_params(struct hda_codec *codec) 8548 { 8549 struct ca0132_spec *spec = codec->spec; 8550 8551 if (ca0132_use_alt_functions(spec)) { 8552 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8553 chipio_set_conn_rate(codec, 0x0B, SR_48_000); 8554 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0); 8555 chipio_set_control_param(codec, 0, 0); 8556 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 8557 } 8558 8559 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6); 8560 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6); 8561 } 8562 8563 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k) 8564 { 8565 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k); 8566 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k); 8567 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k); 8568 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k); 8569 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k); 8570 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k); 8571 8572 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 8573 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 8574 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8575 } 8576 8577 static bool ca0132_download_dsp_images(struct hda_codec *codec) 8578 { 8579 bool dsp_loaded = false; 8580 struct ca0132_spec *spec = codec->spec; 8581 const struct dsp_image_seg *dsp_os_image; 8582 const struct firmware *fw_entry = NULL; 8583 /* 8584 * Alternate firmwares for different variants. The Recon3Di apparently 8585 * can use the default firmware, but I'll leave the option in case 8586 * it needs it again. 8587 */ 8588 switch (ca0132_quirk(spec)) { 8589 case QUIRK_SBZ: 8590 case QUIRK_R3D: 8591 case QUIRK_AE5: 8592 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE, 8593 codec->card->dev) != 0) 8594 codec_dbg(codec, "Desktop firmware not found."); 8595 else 8596 codec_dbg(codec, "Desktop firmware selected."); 8597 break; 8598 case QUIRK_R3DI: 8599 if (request_firmware(&fw_entry, R3DI_EFX_FILE, 8600 codec->card->dev) != 0) 8601 codec_dbg(codec, "Recon3Di alt firmware not detected."); 8602 else 8603 codec_dbg(codec, "Recon3Di firmware selected."); 8604 break; 8605 default: 8606 break; 8607 } 8608 /* 8609 * Use default ctefx.bin if no alt firmware is detected, or if none 8610 * exists for your particular codec. 8611 */ 8612 if (!fw_entry) { 8613 codec_dbg(codec, "Default firmware selected."); 8614 if (request_firmware(&fw_entry, EFX_FILE, 8615 codec->card->dev) != 0) 8616 return false; 8617 } 8618 8619 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data); 8620 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) { 8621 codec_err(codec, "ca0132 DSP load image failed\n"); 8622 goto exit_download; 8623 } 8624 8625 dsp_loaded = dspload_wait_loaded(codec); 8626 8627 exit_download: 8628 release_firmware(fw_entry); 8629 8630 return dsp_loaded; 8631 } 8632 8633 static void ca0132_download_dsp(struct hda_codec *codec) 8634 { 8635 struct ca0132_spec *spec = codec->spec; 8636 8637 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP 8638 return; /* NOP */ 8639 #endif 8640 8641 if (spec->dsp_state == DSP_DOWNLOAD_FAILED) 8642 return; /* don't retry failures */ 8643 8644 chipio_enable_clocks(codec); 8645 if (spec->dsp_state != DSP_DOWNLOADED) { 8646 spec->dsp_state = DSP_DOWNLOADING; 8647 8648 if (!ca0132_download_dsp_images(codec)) 8649 spec->dsp_state = DSP_DOWNLOAD_FAILED; 8650 else 8651 spec->dsp_state = DSP_DOWNLOADED; 8652 } 8653 8654 /* For codecs using alt functions, this is already done earlier */ 8655 if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec)) 8656 ca0132_set_dsp_msr(codec, true); 8657 } 8658 8659 static void ca0132_process_dsp_response(struct hda_codec *codec, 8660 struct hda_jack_callback *callback) 8661 { 8662 struct ca0132_spec *spec = codec->spec; 8663 8664 codec_dbg(codec, "ca0132_process_dsp_response\n"); 8665 snd_hda_power_up_pm(codec); 8666 if (spec->wait_scp) { 8667 if (dspio_get_response_data(codec) >= 0) 8668 spec->wait_scp = 0; 8669 } 8670 8671 dspio_clear_response_queue(codec); 8672 snd_hda_power_down_pm(codec); 8673 } 8674 8675 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 8676 { 8677 struct ca0132_spec *spec = codec->spec; 8678 struct hda_jack_tbl *tbl; 8679 8680 /* Delay enabling the HP amp, to let the mic-detection 8681 * state machine run. 8682 */ 8683 tbl = snd_hda_jack_tbl_get(codec, cb->nid); 8684 if (tbl) 8685 tbl->block_report = 1; 8686 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500)); 8687 } 8688 8689 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 8690 { 8691 struct ca0132_spec *spec = codec->spec; 8692 8693 if (ca0132_use_alt_functions(spec)) 8694 ca0132_alt_select_in(codec); 8695 else 8696 ca0132_select_mic(codec); 8697 } 8698 8699 static void ca0132_setup_unsol(struct hda_codec *codec) 8700 { 8701 struct ca0132_spec *spec = codec->spec; 8702 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback); 8703 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1, 8704 amic_callback); 8705 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP, 8706 ca0132_process_dsp_response); 8707 /* Front headphone jack detection */ 8708 if (ca0132_use_alt_functions(spec)) 8709 snd_hda_jack_detect_enable_callback(codec, 8710 spec->unsol_tag_front_hp, hp_callback); 8711 } 8712 8713 /* 8714 * Verbs tables. 8715 */ 8716 8717 /* Sends before DSP download. */ 8718 static const struct hda_verb ca0132_base_init_verbs[] = { 8719 /*enable ct extension*/ 8720 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1}, 8721 {} 8722 }; 8723 8724 /* Send at exit. */ 8725 static const struct hda_verb ca0132_base_exit_verbs[] = { 8726 /*set afg to D3*/ 8727 {0x01, AC_VERB_SET_POWER_STATE, 0x03}, 8728 /*disable ct extension*/ 8729 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0}, 8730 {} 8731 }; 8732 8733 /* Other verbs tables. Sends after DSP download. */ 8734 8735 static const struct hda_verb ca0132_init_verbs0[] = { 8736 /* chip init verbs */ 8737 {0x15, 0x70D, 0xF0}, 8738 {0x15, 0x70E, 0xFE}, 8739 {0x15, 0x707, 0x75}, 8740 {0x15, 0x707, 0xD3}, 8741 {0x15, 0x707, 0x09}, 8742 {0x15, 0x707, 0x53}, 8743 {0x15, 0x707, 0xD4}, 8744 {0x15, 0x707, 0xEF}, 8745 {0x15, 0x707, 0x75}, 8746 {0x15, 0x707, 0xD3}, 8747 {0x15, 0x707, 0x09}, 8748 {0x15, 0x707, 0x02}, 8749 {0x15, 0x707, 0x37}, 8750 {0x15, 0x707, 0x78}, 8751 {0x15, 0x53C, 0xCE}, 8752 {0x15, 0x575, 0xC9}, 8753 {0x15, 0x53D, 0xCE}, 8754 {0x15, 0x5B7, 0xC9}, 8755 {0x15, 0x70D, 0xE8}, 8756 {0x15, 0x70E, 0xFE}, 8757 {0x15, 0x707, 0x02}, 8758 {0x15, 0x707, 0x68}, 8759 {0x15, 0x707, 0x62}, 8760 {0x15, 0x53A, 0xCE}, 8761 {0x15, 0x546, 0xC9}, 8762 {0x15, 0x53B, 0xCE}, 8763 {0x15, 0x5E8, 0xC9}, 8764 {} 8765 }; 8766 8767 /* Extra init verbs for desktop cards. */ 8768 static const struct hda_verb ca0132_init_verbs1[] = { 8769 {0x15, 0x70D, 0x20}, 8770 {0x15, 0x70E, 0x19}, 8771 {0x15, 0x707, 0x00}, 8772 {0x15, 0x539, 0xCE}, 8773 {0x15, 0x546, 0xC9}, 8774 {0x15, 0x70D, 0xB7}, 8775 {0x15, 0x70E, 0x09}, 8776 {0x15, 0x707, 0x10}, 8777 {0x15, 0x70D, 0xAF}, 8778 {0x15, 0x70E, 0x09}, 8779 {0x15, 0x707, 0x01}, 8780 {0x15, 0x707, 0x05}, 8781 {0x15, 0x70D, 0x73}, 8782 {0x15, 0x70E, 0x09}, 8783 {0x15, 0x707, 0x14}, 8784 {0x15, 0x6FF, 0xC4}, 8785 {} 8786 }; 8787 8788 static void ca0132_init_chip(struct hda_codec *codec) 8789 { 8790 struct ca0132_spec *spec = codec->spec; 8791 int num_fx; 8792 int i; 8793 unsigned int on; 8794 8795 mutex_init(&spec->chipio_mutex); 8796 8797 /* 8798 * The Windows driver always does this upon startup, which seems to 8799 * clear out any previous configuration. This should help issues where 8800 * a boot into Windows prior to a boot into Linux breaks things. Also, 8801 * Windows always sends the reset twice. 8802 */ 8803 if (ca0132_use_alt_functions(spec)) { 8804 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8805 chipio_write_no_mutex(codec, 0x18b0a4, 0x000000c2); 8806 8807 snd_hda_codec_write(codec, codec->core.afg, 0, 8808 AC_VERB_SET_CODEC_RESET, 0); 8809 snd_hda_codec_write(codec, codec->core.afg, 0, 8810 AC_VERB_SET_CODEC_RESET, 0); 8811 } 8812 8813 spec->cur_out_type = SPEAKER_OUT; 8814 if (!ca0132_use_alt_functions(spec)) 8815 spec->cur_mic_type = DIGITAL_MIC; 8816 else 8817 spec->cur_mic_type = REAR_MIC; 8818 8819 spec->cur_mic_boost = 0; 8820 8821 for (i = 0; i < VNODES_COUNT; i++) { 8822 spec->vnode_lvol[i] = 0x5a; 8823 spec->vnode_rvol[i] = 0x5a; 8824 spec->vnode_lswitch[i] = 0; 8825 spec->vnode_rswitch[i] = 0; 8826 } 8827 8828 /* 8829 * Default states for effects are in ca0132_effects[]. 8830 */ 8831 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 8832 for (i = 0; i < num_fx; i++) { 8833 on = (unsigned int)ca0132_effects[i].reqs[0]; 8834 spec->effects_switch[i] = on ? 1 : 0; 8835 } 8836 /* 8837 * Sets defaults for the effect slider controls, only for alternative 8838 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz. 8839 */ 8840 if (ca0132_use_alt_controls(spec)) { 8841 /* Set speakers to default to full range. */ 8842 spec->speaker_range_val[0] = 1; 8843 spec->speaker_range_val[1] = 1; 8844 8845 spec->xbass_xover_freq = 8; 8846 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++) 8847 spec->fx_ctl_val[i] = effect_slider_defaults[i]; 8848 8849 spec->bass_redirect_xover_freq = 8; 8850 } 8851 8852 spec->voicefx_val = 0; 8853 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1; 8854 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0; 8855 8856 /* 8857 * The ZxR doesn't have a front panel header, and it's line-in is on 8858 * the daughter board. So, there is no input enum control, and we need 8859 * to make sure that spec->in_enum_val is set properly. 8860 */ 8861 if (ca0132_quirk(spec) == QUIRK_ZXR) 8862 spec->in_enum_val = REAR_MIC; 8863 8864 #ifdef ENABLE_TUNING_CONTROLS 8865 ca0132_init_tuning_defaults(codec); 8866 #endif 8867 } 8868 8869 /* 8870 * Recon3Di exit specific commands. 8871 */ 8872 /* prevents popping noise on shutdown */ 8873 static void r3di_gpio_shutdown(struct hda_codec *codec) 8874 { 8875 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00); 8876 } 8877 8878 /* 8879 * Sound Blaster Z exit specific commands. 8880 */ 8881 static void sbz_region2_exit(struct hda_codec *codec) 8882 { 8883 struct ca0132_spec *spec = codec->spec; 8884 unsigned int i; 8885 8886 for (i = 0; i < 4; i++) 8887 writeb(0x0, spec->mem_base + 0x100); 8888 for (i = 0; i < 8; i++) 8889 writeb(0xb3, spec->mem_base + 0x304); 8890 8891 ca0113_mmio_gpio_set(codec, 0, false); 8892 ca0113_mmio_gpio_set(codec, 1, false); 8893 ca0113_mmio_gpio_set(codec, 4, true); 8894 ca0113_mmio_gpio_set(codec, 5, false); 8895 ca0113_mmio_gpio_set(codec, 7, false); 8896 } 8897 8898 static void sbz_set_pin_ctl_default(struct hda_codec *codec) 8899 { 8900 static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13}; 8901 unsigned int i; 8902 8903 snd_hda_codec_write(codec, 0x11, 0, 8904 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40); 8905 8906 for (i = 0; i < ARRAY_SIZE(pins); i++) 8907 snd_hda_codec_write(codec, pins[i], 0, 8908 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00); 8909 } 8910 8911 static void ca0132_clear_unsolicited(struct hda_codec *codec) 8912 { 8913 static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13}; 8914 unsigned int i; 8915 8916 for (i = 0; i < ARRAY_SIZE(pins); i++) { 8917 snd_hda_codec_write(codec, pins[i], 0, 8918 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00); 8919 } 8920 } 8921 8922 /* On shutdown, sends commands in sets of three */ 8923 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir, 8924 int mask, int data) 8925 { 8926 if (dir >= 0) 8927 snd_hda_codec_write(codec, 0x01, 0, 8928 AC_VERB_SET_GPIO_DIRECTION, dir); 8929 if (mask >= 0) 8930 snd_hda_codec_write(codec, 0x01, 0, 8931 AC_VERB_SET_GPIO_MASK, mask); 8932 8933 if (data >= 0) 8934 snd_hda_codec_write(codec, 0x01, 0, 8935 AC_VERB_SET_GPIO_DATA, data); 8936 } 8937 8938 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec) 8939 { 8940 static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01}; 8941 unsigned int i; 8942 8943 for (i = 0; i < ARRAY_SIZE(pins); i++) 8944 snd_hda_codec_write(codec, pins[i], 0, 8945 AC_VERB_SET_POWER_STATE, 0x03); 8946 } 8947 8948 static void sbz_exit_chip(struct hda_codec *codec) 8949 { 8950 chipio_set_stream_control(codec, 0x03, 0); 8951 chipio_set_stream_control(codec, 0x04, 0); 8952 8953 /* Mess with GPIO */ 8954 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1); 8955 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05); 8956 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01); 8957 8958 chipio_set_stream_control(codec, 0x14, 0); 8959 chipio_set_stream_control(codec, 0x0C, 0); 8960 8961 chipio_set_conn_rate(codec, 0x41, SR_192_000); 8962 chipio_set_conn_rate(codec, 0x91, SR_192_000); 8963 8964 chipio_write(codec, 0x18a020, 0x00000083); 8965 8966 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03); 8967 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07); 8968 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06); 8969 8970 chipio_set_stream_control(codec, 0x0C, 0); 8971 8972 chipio_set_control_param(codec, 0x0D, 0x24); 8973 8974 ca0132_clear_unsolicited(codec); 8975 sbz_set_pin_ctl_default(codec); 8976 8977 snd_hda_codec_write(codec, 0x0B, 0, 8978 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 8979 8980 sbz_region2_exit(codec); 8981 } 8982 8983 static void r3d_exit_chip(struct hda_codec *codec) 8984 { 8985 ca0132_clear_unsolicited(codec); 8986 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 8987 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b); 8988 } 8989 8990 static void ae5_exit_chip(struct hda_codec *codec) 8991 { 8992 chipio_set_stream_control(codec, 0x03, 0); 8993 chipio_set_stream_control(codec, 0x04, 0); 8994 8995 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 8996 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8997 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8998 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 8999 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 9000 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00); 9001 ca0113_mmio_gpio_set(codec, 0, false); 9002 ca0113_mmio_gpio_set(codec, 1, false); 9003 9004 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 9005 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 9006 9007 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 9008 9009 chipio_set_stream_control(codec, 0x18, 0); 9010 chipio_set_stream_control(codec, 0x0c, 0); 9011 9012 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83); 9013 } 9014 9015 static void ae7_exit_chip(struct hda_codec *codec) 9016 { 9017 chipio_set_stream_control(codec, 0x18, 0); 9018 chipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8); 9019 chipio_set_stream_channels(codec, 0x21, 0); 9020 chipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09); 9021 chipio_set_control_param(codec, 0x20, 0x01); 9022 9023 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 9024 9025 chipio_set_stream_control(codec, 0x18, 0); 9026 chipio_set_stream_control(codec, 0x0c, 0); 9027 9028 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 9029 snd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83); 9030 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 9031 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 9032 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00); 9033 ca0113_mmio_gpio_set(codec, 0, false); 9034 ca0113_mmio_gpio_set(codec, 1, false); 9035 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9036 9037 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 9038 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 9039 } 9040 9041 static void zxr_exit_chip(struct hda_codec *codec) 9042 { 9043 chipio_set_stream_control(codec, 0x03, 0); 9044 chipio_set_stream_control(codec, 0x04, 0); 9045 chipio_set_stream_control(codec, 0x14, 0); 9046 chipio_set_stream_control(codec, 0x0C, 0); 9047 9048 chipio_set_conn_rate(codec, 0x41, SR_192_000); 9049 chipio_set_conn_rate(codec, 0x91, SR_192_000); 9050 9051 chipio_write(codec, 0x18a020, 0x00000083); 9052 9053 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 9054 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 9055 9056 ca0132_clear_unsolicited(codec); 9057 sbz_set_pin_ctl_default(codec); 9058 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00); 9059 9060 ca0113_mmio_gpio_set(codec, 5, false); 9061 ca0113_mmio_gpio_set(codec, 2, false); 9062 ca0113_mmio_gpio_set(codec, 3, false); 9063 ca0113_mmio_gpio_set(codec, 0, false); 9064 ca0113_mmio_gpio_set(codec, 4, true); 9065 ca0113_mmio_gpio_set(codec, 0, true); 9066 ca0113_mmio_gpio_set(codec, 5, true); 9067 ca0113_mmio_gpio_set(codec, 2, false); 9068 ca0113_mmio_gpio_set(codec, 3, false); 9069 } 9070 9071 static void ca0132_exit_chip(struct hda_codec *codec) 9072 { 9073 /* put any chip cleanup stuffs here. */ 9074 9075 if (dspload_is_loaded(codec)) 9076 dsp_reset(codec); 9077 } 9078 9079 /* 9080 * This fixes a problem that was hard to reproduce. Very rarely, I would 9081 * boot up, and there would be no sound, but the DSP indicated it had loaded 9082 * properly. I did a few memory dumps to see if anything was different, and 9083 * there were a few areas of memory uninitialized with a1a2a3a4. This function 9084 * checks if those areas are uninitialized, and if they are, it'll attempt to 9085 * reload the card 3 times. Usually it fixes by the second. 9086 */ 9087 static void sbz_dsp_startup_check(struct hda_codec *codec) 9088 { 9089 struct ca0132_spec *spec = codec->spec; 9090 unsigned int dsp_data_check[4]; 9091 unsigned int cur_address = 0x390; 9092 unsigned int i; 9093 unsigned int failure = 0; 9094 unsigned int reload = 3; 9095 9096 if (spec->startup_check_entered) 9097 return; 9098 9099 spec->startup_check_entered = true; 9100 9101 for (i = 0; i < 4; i++) { 9102 chipio_read(codec, cur_address, &dsp_data_check[i]); 9103 cur_address += 0x4; 9104 } 9105 for (i = 0; i < 4; i++) { 9106 if (dsp_data_check[i] == 0xa1a2a3a4) 9107 failure = 1; 9108 } 9109 9110 codec_dbg(codec, "Startup Check: %d ", failure); 9111 if (failure) 9112 codec_info(codec, "DSP not initialized properly. Attempting to fix."); 9113 /* 9114 * While the failure condition is true, and we haven't reached our 9115 * three reload limit, continue trying to reload the driver and 9116 * fix the issue. 9117 */ 9118 while (failure && (reload != 0)) { 9119 codec_info(codec, "Reloading... Tries left: %d", reload); 9120 sbz_exit_chip(codec); 9121 spec->dsp_state = DSP_DOWNLOAD_INIT; 9122 codec->patch_ops.init(codec); 9123 failure = 0; 9124 for (i = 0; i < 4; i++) { 9125 chipio_read(codec, cur_address, &dsp_data_check[i]); 9126 cur_address += 0x4; 9127 } 9128 for (i = 0; i < 4; i++) { 9129 if (dsp_data_check[i] == 0xa1a2a3a4) 9130 failure = 1; 9131 } 9132 reload--; 9133 } 9134 9135 if (!failure && reload < 3) 9136 codec_info(codec, "DSP fixed."); 9137 9138 if (!failure) 9139 return; 9140 9141 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory."); 9142 } 9143 9144 /* 9145 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add 9146 * extra precision for decibel values. If you had the dB value in floating point 9147 * you would take the value after the decimal point, multiply by 64, and divide 9148 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to 9149 * implement fixed point or floating point dB volumes. For now, I'll set them 9150 * to 0 just incase a value has lingered from a boot into Windows. 9151 */ 9152 static void ca0132_alt_vol_setup(struct hda_codec *codec) 9153 { 9154 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00); 9155 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00); 9156 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00); 9157 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00); 9158 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00); 9159 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00); 9160 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00); 9161 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00); 9162 } 9163 9164 /* 9165 * Extra commands that don't really fit anywhere else. 9166 */ 9167 static void sbz_pre_dsp_setup(struct hda_codec *codec) 9168 { 9169 struct ca0132_spec *spec = codec->spec; 9170 9171 writel(0x00820680, spec->mem_base + 0x01C); 9172 writel(0x00820680, spec->mem_base + 0x01C); 9173 9174 chipio_write(codec, 0x18b0a4, 0x000000c2); 9175 9176 snd_hda_codec_write(codec, 0x11, 0, 9177 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 9178 } 9179 9180 static void r3d_pre_dsp_setup(struct hda_codec *codec) 9181 { 9182 chipio_write(codec, 0x18b0a4, 0x000000c2); 9183 9184 chipio_8051_write_exram(codec, 0x1c1e, 0x5b); 9185 9186 snd_hda_codec_write(codec, 0x11, 0, 9187 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 9188 } 9189 9190 static void r3di_pre_dsp_setup(struct hda_codec *codec) 9191 { 9192 chipio_write(codec, 0x18b0a4, 0x000000c2); 9193 9194 chipio_8051_write_exram(codec, 0x1c1e, 0x5b); 9195 chipio_8051_write_exram(codec, 0x1920, 0x00); 9196 chipio_8051_write_exram(codec, 0x1921, 0x40); 9197 9198 snd_hda_codec_write(codec, 0x11, 0, 9199 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04); 9200 } 9201 9202 /* 9203 * The ZxR seems to use alternative DAC's for the surround channels, which 9204 * require PLL PMU setup for the clock rate, I'm guessing. Without setting 9205 * this up, we get no audio out of the surround jacks. 9206 */ 9207 static void zxr_pre_dsp_setup(struct hda_codec *codec) 9208 { 9209 static const unsigned int addr[] = { 0x43, 0x40, 0x41, 0x42, 0x45 }; 9210 static const unsigned int data[] = { 0x08, 0x0c, 0x0b, 0x07, 0x0d }; 9211 unsigned int i; 9212 9213 chipio_write(codec, 0x189000, 0x0001f100); 9214 msleep(50); 9215 chipio_write(codec, 0x18900c, 0x0001f100); 9216 msleep(50); 9217 9218 /* 9219 * This writes a RET instruction at the entry point of the function at 9220 * 0xfa92 in exram. This function seems to have something to do with 9221 * ASI. Might be some way to prevent the card from reconfiguring the 9222 * ASI stuff itself. 9223 */ 9224 chipio_8051_write_exram(codec, 0xfa92, 0x22); 9225 9226 chipio_8051_write_pll_pmu(codec, 0x51, 0x98); 9227 9228 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x82); 9229 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 3); 9230 9231 chipio_write(codec, 0x18902c, 0x00000000); 9232 msleep(50); 9233 chipio_write(codec, 0x18902c, 0x00000003); 9234 msleep(50); 9235 9236 for (i = 0; i < ARRAY_SIZE(addr); i++) 9237 chipio_8051_write_pll_pmu(codec, addr[i], data[i]); 9238 } 9239 9240 /* 9241 * These are sent before the DSP is downloaded. Not sure 9242 * what they do, or if they're necessary. Could possibly 9243 * be removed. Figure they're better to leave in. 9244 */ 9245 static const unsigned int ca0113_mmio_init_address_sbz[] = { 9246 0x400, 0x408, 0x40c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 9247 0xc0c, 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04 9248 }; 9249 9250 static const unsigned int ca0113_mmio_init_data_sbz[] = { 9251 0x00000030, 0x00000000, 0x00000003, 0x00000003, 0x00000003, 9252 0x00000003, 0x000000c1, 0x000000f1, 0x00000001, 0x000000c7, 9253 0x000000c1, 0x00000080 9254 }; 9255 9256 static const unsigned int ca0113_mmio_init_data_zxr[] = { 9257 0x00000030, 0x00000000, 0x00000000, 0x00000003, 0x00000003, 9258 0x00000003, 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 9259 0x000000c1, 0x00000080 9260 }; 9261 9262 static const unsigned int ca0113_mmio_init_address_ae5[] = { 9263 0x400, 0x42c, 0x46c, 0x4ac, 0x4ec, 0x43c, 0x47c, 0x4bc, 0x4fc, 0x408, 9264 0x100, 0x410, 0x40c, 0x100, 0x100, 0x830, 0x86c, 0x800, 0x86c, 0x800, 9265 0x804, 0x20c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 0xc0c, 9266 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04, 0x01c 9267 }; 9268 9269 static const unsigned int ca0113_mmio_init_data_ae5[] = { 9270 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 9271 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 9272 0x00000600, 0x00000014, 0x00000001, 0x0000060f, 0x0000070f, 9273 0x00000aff, 0x00000000, 0x0000006b, 0x00000001, 0x0000006b, 9274 0x00000057, 0x00800000, 0x00880680, 0x00000080, 0x00000030, 9275 0x00000000, 0x00000000, 0x00000003, 0x00000003, 0x00000003, 9276 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1, 9277 0x00000080, 0x00880680 9278 }; 9279 9280 static void ca0132_mmio_init_sbz(struct hda_codec *codec) 9281 { 9282 struct ca0132_spec *spec = codec->spec; 9283 unsigned int tmp[2], i, count, cur_addr; 9284 const unsigned int *addr, *data; 9285 9286 addr = ca0113_mmio_init_address_sbz; 9287 for (i = 0; i < 3; i++) 9288 writel(0x00000000, spec->mem_base + addr[i]); 9289 9290 cur_addr = i; 9291 switch (ca0132_quirk(spec)) { 9292 case QUIRK_ZXR: 9293 tmp[0] = 0x00880480; 9294 tmp[1] = 0x00000080; 9295 break; 9296 case QUIRK_SBZ: 9297 tmp[0] = 0x00820680; 9298 tmp[1] = 0x00000083; 9299 break; 9300 case QUIRK_R3D: 9301 tmp[0] = 0x00880680; 9302 tmp[1] = 0x00000083; 9303 break; 9304 default: 9305 tmp[0] = 0x00000000; 9306 tmp[1] = 0x00000000; 9307 break; 9308 } 9309 9310 for (i = 0; i < 2; i++) 9311 writel(tmp[i], spec->mem_base + addr[cur_addr + i]); 9312 9313 cur_addr += i; 9314 9315 switch (ca0132_quirk(spec)) { 9316 case QUIRK_ZXR: 9317 count = ARRAY_SIZE(ca0113_mmio_init_data_zxr); 9318 data = ca0113_mmio_init_data_zxr; 9319 break; 9320 default: 9321 count = ARRAY_SIZE(ca0113_mmio_init_data_sbz); 9322 data = ca0113_mmio_init_data_sbz; 9323 break; 9324 } 9325 9326 for (i = 0; i < count; i++) 9327 writel(data[i], spec->mem_base + addr[cur_addr + i]); 9328 } 9329 9330 static void ca0132_mmio_init_ae5(struct hda_codec *codec) 9331 { 9332 struct ca0132_spec *spec = codec->spec; 9333 const unsigned int *addr, *data; 9334 unsigned int i, count; 9335 9336 addr = ca0113_mmio_init_address_ae5; 9337 data = ca0113_mmio_init_data_ae5; 9338 count = ARRAY_SIZE(ca0113_mmio_init_data_ae5); 9339 9340 if (ca0132_quirk(spec) == QUIRK_AE7) { 9341 writel(0x00000680, spec->mem_base + 0x1c); 9342 writel(0x00880680, spec->mem_base + 0x1c); 9343 } 9344 9345 for (i = 0; i < count; i++) { 9346 /* 9347 * AE-7 shares all writes with the AE-5, except that it writes 9348 * a different value to 0x20c. 9349 */ 9350 if (i == 21 && ca0132_quirk(spec) == QUIRK_AE7) { 9351 writel(0x00800001, spec->mem_base + addr[i]); 9352 continue; 9353 } 9354 9355 writel(data[i], spec->mem_base + addr[i]); 9356 } 9357 9358 if (ca0132_quirk(spec) == QUIRK_AE5) 9359 writel(0x00880680, spec->mem_base + 0x1c); 9360 } 9361 9362 static void ca0132_mmio_init(struct hda_codec *codec) 9363 { 9364 struct ca0132_spec *spec = codec->spec; 9365 9366 switch (ca0132_quirk(spec)) { 9367 case QUIRK_R3D: 9368 case QUIRK_SBZ: 9369 case QUIRK_ZXR: 9370 ca0132_mmio_init_sbz(codec); 9371 break; 9372 case QUIRK_AE5: 9373 ca0132_mmio_init_ae5(codec); 9374 break; 9375 default: 9376 break; 9377 } 9378 } 9379 9380 static const unsigned int ca0132_ae5_register_set_addresses[] = { 9381 0x304, 0x304, 0x304, 0x304, 0x100, 0x304, 0x100, 0x304, 0x100, 0x304, 9382 0x100, 0x304, 0x86c, 0x800, 0x86c, 0x800, 0x804 9383 }; 9384 9385 static const unsigned char ca0132_ae5_register_set_data[] = { 9386 0x0f, 0x0e, 0x1f, 0x0c, 0x3f, 0x08, 0x7f, 0x00, 0xff, 0x00, 0x6b, 9387 0x01, 0x6b, 0x57 9388 }; 9389 9390 /* 9391 * This function writes to some SFR's, does some region2 writes, and then 9392 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does 9393 * what it does. 9394 */ 9395 static void ae5_register_set(struct hda_codec *codec) 9396 { 9397 struct ca0132_spec *spec = codec->spec; 9398 unsigned int count = ARRAY_SIZE(ca0132_ae5_register_set_addresses); 9399 const unsigned int *addr = ca0132_ae5_register_set_addresses; 9400 const unsigned char *data = ca0132_ae5_register_set_data; 9401 unsigned int i, cur_addr; 9402 unsigned char tmp[3]; 9403 9404 if (ca0132_quirk(spec) == QUIRK_AE7) 9405 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8); 9406 9407 chipio_8051_write_direct(codec, 0x93, 0x10); 9408 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); 9409 9410 if (ca0132_quirk(spec) == QUIRK_AE7) { 9411 tmp[0] = 0x03; 9412 tmp[1] = 0x03; 9413 tmp[2] = 0x07; 9414 } else { 9415 tmp[0] = 0x0f; 9416 tmp[1] = 0x0f; 9417 tmp[2] = 0x0f; 9418 } 9419 9420 for (i = cur_addr = 0; i < 3; i++, cur_addr++) 9421 writeb(tmp[i], spec->mem_base + addr[cur_addr]); 9422 9423 /* 9424 * First writes are in single bytes, final are in 4 bytes. So, we use 9425 * writeb, then writel. 9426 */ 9427 for (i = 0; cur_addr < 12; i++, cur_addr++) 9428 writeb(data[i], spec->mem_base + addr[cur_addr]); 9429 9430 for (; cur_addr < count; i++, cur_addr++) 9431 writel(data[i], spec->mem_base + addr[cur_addr]); 9432 9433 writel(0x00800001, spec->mem_base + 0x20c); 9434 9435 if (ca0132_quirk(spec) == QUIRK_AE7) { 9436 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 9437 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 9438 } else { 9439 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 9440 } 9441 9442 chipio_8051_write_direct(codec, 0x90, 0x00); 9443 chipio_8051_write_direct(codec, 0x90, 0x10); 9444 9445 if (ca0132_quirk(spec) == QUIRK_AE5) 9446 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 9447 } 9448 9449 /* 9450 * Extra init functions for alternative ca0132 codecs. Done 9451 * here so they don't clutter up the main ca0132_init function 9452 * anymore than they have to. 9453 */ 9454 static void ca0132_alt_init(struct hda_codec *codec) 9455 { 9456 struct ca0132_spec *spec = codec->spec; 9457 9458 ca0132_alt_vol_setup(codec); 9459 9460 switch (ca0132_quirk(spec)) { 9461 case QUIRK_SBZ: 9462 codec_dbg(codec, "SBZ alt_init"); 9463 ca0132_gpio_init(codec); 9464 sbz_pre_dsp_setup(codec); 9465 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9466 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9467 break; 9468 case QUIRK_R3DI: 9469 codec_dbg(codec, "R3DI alt_init"); 9470 ca0132_gpio_init(codec); 9471 ca0132_gpio_setup(codec); 9472 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING); 9473 r3di_pre_dsp_setup(codec); 9474 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9475 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4); 9476 break; 9477 case QUIRK_R3D: 9478 r3d_pre_dsp_setup(codec); 9479 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9480 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9481 break; 9482 case QUIRK_AE5: 9483 ca0132_gpio_init(codec); 9484 chipio_8051_write_pll_pmu(codec, 0x49, 0x88); 9485 chipio_write(codec, 0x18b030, 0x00000020); 9486 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9487 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9488 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9489 break; 9490 case QUIRK_AE7: 9491 ca0132_gpio_init(codec); 9492 chipio_8051_write_pll_pmu(codec, 0x49, 0x88); 9493 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9494 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9495 chipio_write(codec, 0x18b008, 0x000000f8); 9496 chipio_write(codec, 0x18b008, 0x000000f0); 9497 chipio_write(codec, 0x18b030, 0x00000020); 9498 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9499 break; 9500 case QUIRK_ZXR: 9501 chipio_8051_write_pll_pmu(codec, 0x49, 0x88); 9502 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9503 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9504 zxr_pre_dsp_setup(codec); 9505 break; 9506 default: 9507 break; 9508 } 9509 } 9510 9511 static int ca0132_init(struct hda_codec *codec) 9512 { 9513 struct ca0132_spec *spec = codec->spec; 9514 struct auto_pin_cfg *cfg = &spec->autocfg; 9515 int i; 9516 bool dsp_loaded; 9517 9518 /* 9519 * If the DSP is already downloaded, and init has been entered again, 9520 * there's only two reasons for it. One, the codec has awaken from a 9521 * suspended state, and in that case dspload_is_loaded will return 9522 * false, and the init will be ran again. The other reason it gets 9523 * re entered is on startup for some reason it triggers a suspend and 9524 * resume state. In this case, it will check if the DSP is downloaded, 9525 * and not run the init function again. For codecs using alt_functions, 9526 * it will check if the DSP is loaded properly. 9527 */ 9528 if (spec->dsp_state == DSP_DOWNLOADED) { 9529 dsp_loaded = dspload_is_loaded(codec); 9530 if (!dsp_loaded) { 9531 spec->dsp_reload = true; 9532 spec->dsp_state = DSP_DOWNLOAD_INIT; 9533 } else { 9534 if (ca0132_quirk(spec) == QUIRK_SBZ) 9535 sbz_dsp_startup_check(codec); 9536 return 0; 9537 } 9538 } 9539 9540 if (spec->dsp_state != DSP_DOWNLOAD_FAILED) 9541 spec->dsp_state = DSP_DOWNLOAD_INIT; 9542 spec->curr_chip_addx = INVALID_CHIP_ADDRESS; 9543 9544 if (ca0132_use_pci_mmio(spec)) 9545 ca0132_mmio_init(codec); 9546 9547 snd_hda_power_up_pm(codec); 9548 9549 if (ca0132_quirk(spec) == QUIRK_AE5 || ca0132_quirk(spec) == QUIRK_AE7) 9550 ae5_register_set(codec); 9551 9552 ca0132_init_params(codec); 9553 ca0132_init_flags(codec); 9554 9555 snd_hda_sequence_write(codec, spec->base_init_verbs); 9556 9557 if (ca0132_use_alt_functions(spec)) 9558 ca0132_alt_init(codec); 9559 9560 ca0132_download_dsp(codec); 9561 9562 ca0132_refresh_widget_caps(codec); 9563 9564 switch (ca0132_quirk(spec)) { 9565 case QUIRK_R3DI: 9566 case QUIRK_R3D: 9567 r3d_setup_defaults(codec); 9568 break; 9569 case QUIRK_SBZ: 9570 case QUIRK_ZXR: 9571 sbz_setup_defaults(codec); 9572 break; 9573 case QUIRK_AE5: 9574 ae5_setup_defaults(codec); 9575 break; 9576 case QUIRK_AE7: 9577 ae7_setup_defaults(codec); 9578 break; 9579 default: 9580 ca0132_setup_defaults(codec); 9581 ca0132_init_analog_mic2(codec); 9582 ca0132_init_dmic(codec); 9583 break; 9584 } 9585 9586 for (i = 0; i < spec->num_outputs; i++) 9587 init_output(codec, spec->out_pins[i], spec->dacs[0]); 9588 9589 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 9590 9591 for (i = 0; i < spec->num_inputs; i++) 9592 init_input(codec, spec->input_pins[i], spec->adcs[i]); 9593 9594 init_input(codec, cfg->dig_in_pin, spec->dig_in); 9595 9596 if (!ca0132_use_alt_functions(spec)) { 9597 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9598 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9599 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D); 9600 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9601 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20); 9602 } 9603 9604 if (ca0132_quirk(spec) == QUIRK_SBZ) 9605 ca0132_gpio_setup(codec); 9606 9607 snd_hda_sequence_write(codec, spec->spec_init_verbs); 9608 if (ca0132_use_alt_functions(spec)) { 9609 ca0132_alt_select_out(codec); 9610 ca0132_alt_select_in(codec); 9611 } else { 9612 ca0132_select_out(codec); 9613 ca0132_select_mic(codec); 9614 } 9615 9616 snd_hda_jack_report_sync(codec); 9617 9618 /* 9619 * Re set the PlayEnhancement switch on a resume event, because the 9620 * controls will not be reloaded. 9621 */ 9622 if (spec->dsp_reload) { 9623 spec->dsp_reload = false; 9624 ca0132_pe_switch_set(codec); 9625 } 9626 9627 snd_hda_power_down_pm(codec); 9628 9629 return 0; 9630 } 9631 9632 static int dbpro_init(struct hda_codec *codec) 9633 { 9634 struct ca0132_spec *spec = codec->spec; 9635 struct auto_pin_cfg *cfg = &spec->autocfg; 9636 unsigned int i; 9637 9638 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 9639 init_input(codec, cfg->dig_in_pin, spec->dig_in); 9640 9641 for (i = 0; i < spec->num_inputs; i++) 9642 init_input(codec, spec->input_pins[i], spec->adcs[i]); 9643 9644 return 0; 9645 } 9646 9647 static void ca0132_free(struct hda_codec *codec) 9648 { 9649 struct ca0132_spec *spec = codec->spec; 9650 9651 cancel_delayed_work_sync(&spec->unsol_hp_work); 9652 snd_hda_power_up(codec); 9653 switch (ca0132_quirk(spec)) { 9654 case QUIRK_SBZ: 9655 sbz_exit_chip(codec); 9656 break; 9657 case QUIRK_ZXR: 9658 zxr_exit_chip(codec); 9659 break; 9660 case QUIRK_R3D: 9661 r3d_exit_chip(codec); 9662 break; 9663 case QUIRK_AE5: 9664 ae5_exit_chip(codec); 9665 break; 9666 case QUIRK_AE7: 9667 ae7_exit_chip(codec); 9668 break; 9669 case QUIRK_R3DI: 9670 r3di_gpio_shutdown(codec); 9671 break; 9672 default: 9673 break; 9674 } 9675 9676 snd_hda_sequence_write(codec, spec->base_exit_verbs); 9677 ca0132_exit_chip(codec); 9678 9679 snd_hda_power_down(codec); 9680 #ifdef CONFIG_PCI 9681 if (spec->mem_base) 9682 pci_iounmap(codec->bus->pci, spec->mem_base); 9683 #endif 9684 kfree(spec->spec_init_verbs); 9685 kfree(codec->spec); 9686 } 9687 9688 static void dbpro_free(struct hda_codec *codec) 9689 { 9690 struct ca0132_spec *spec = codec->spec; 9691 9692 zxr_dbpro_power_state_shutdown(codec); 9693 9694 kfree(spec->spec_init_verbs); 9695 kfree(codec->spec); 9696 } 9697 9698 #ifdef CONFIG_PM 9699 static int ca0132_suspend(struct hda_codec *codec) 9700 { 9701 struct ca0132_spec *spec = codec->spec; 9702 9703 cancel_delayed_work_sync(&spec->unsol_hp_work); 9704 return 0; 9705 } 9706 #endif 9707 9708 static const struct hda_codec_ops ca0132_patch_ops = { 9709 .build_controls = ca0132_build_controls, 9710 .build_pcms = ca0132_build_pcms, 9711 .init = ca0132_init, 9712 .free = ca0132_free, 9713 .unsol_event = snd_hda_jack_unsol_event, 9714 #ifdef CONFIG_PM 9715 .suspend = ca0132_suspend, 9716 #endif 9717 }; 9718 9719 static const struct hda_codec_ops dbpro_patch_ops = { 9720 .build_controls = dbpro_build_controls, 9721 .build_pcms = dbpro_build_pcms, 9722 .init = dbpro_init, 9723 .free = dbpro_free, 9724 }; 9725 9726 static void ca0132_config(struct hda_codec *codec) 9727 { 9728 struct ca0132_spec *spec = codec->spec; 9729 9730 spec->dacs[0] = 0x2; 9731 spec->dacs[1] = 0x3; 9732 spec->dacs[2] = 0x4; 9733 9734 spec->multiout.dac_nids = spec->dacs; 9735 spec->multiout.num_dacs = 3; 9736 9737 if (!ca0132_use_alt_functions(spec)) 9738 spec->multiout.max_channels = 2; 9739 else 9740 spec->multiout.max_channels = 6; 9741 9742 switch (ca0132_quirk(spec)) { 9743 case QUIRK_ALIENWARE: 9744 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__); 9745 snd_hda_apply_pincfgs(codec, alienware_pincfgs); 9746 break; 9747 case QUIRK_SBZ: 9748 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__); 9749 snd_hda_apply_pincfgs(codec, sbz_pincfgs); 9750 break; 9751 case QUIRK_ZXR: 9752 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__); 9753 snd_hda_apply_pincfgs(codec, zxr_pincfgs); 9754 break; 9755 case QUIRK_R3D: 9756 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__); 9757 snd_hda_apply_pincfgs(codec, r3d_pincfgs); 9758 break; 9759 case QUIRK_R3DI: 9760 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__); 9761 snd_hda_apply_pincfgs(codec, r3di_pincfgs); 9762 break; 9763 case QUIRK_AE5: 9764 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__); 9765 snd_hda_apply_pincfgs(codec, ae5_pincfgs); 9766 break; 9767 case QUIRK_AE7: 9768 codec_dbg(codec, "%s: QUIRK_AE7 applied.\n", __func__); 9769 snd_hda_apply_pincfgs(codec, ae7_pincfgs); 9770 break; 9771 default: 9772 break; 9773 } 9774 9775 switch (ca0132_quirk(spec)) { 9776 case QUIRK_ALIENWARE: 9777 spec->num_outputs = 2; 9778 spec->out_pins[0] = 0x0b; /* speaker out */ 9779 spec->out_pins[1] = 0x0f; 9780 spec->shared_out_nid = 0x2; 9781 spec->unsol_tag_hp = 0x0f; 9782 9783 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 9784 spec->adcs[1] = 0x8; /* analog mic2 */ 9785 spec->adcs[2] = 0xa; /* what u hear */ 9786 9787 spec->num_inputs = 3; 9788 spec->input_pins[0] = 0x12; 9789 spec->input_pins[1] = 0x11; 9790 spec->input_pins[2] = 0x13; 9791 spec->shared_mic_nid = 0x7; 9792 spec->unsol_tag_amic1 = 0x11; 9793 break; 9794 case QUIRK_SBZ: 9795 case QUIRK_R3D: 9796 spec->num_outputs = 2; 9797 spec->out_pins[0] = 0x0B; /* Line out */ 9798 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9799 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9800 spec->out_pins[3] = 0x11; /* Rear surround */ 9801 spec->shared_out_nid = 0x2; 9802 spec->unsol_tag_hp = spec->out_pins[1]; 9803 spec->unsol_tag_front_hp = spec->out_pins[2]; 9804 9805 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9806 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 9807 spec->adcs[2] = 0xa; /* what u hear */ 9808 9809 spec->num_inputs = 2; 9810 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9811 spec->input_pins[1] = 0x13; /* What U Hear */ 9812 spec->shared_mic_nid = 0x7; 9813 spec->unsol_tag_amic1 = spec->input_pins[0]; 9814 9815 /* SPDIF I/O */ 9816 spec->dig_out = 0x05; 9817 spec->multiout.dig_out_nid = spec->dig_out; 9818 spec->dig_in = 0x09; 9819 break; 9820 case QUIRK_ZXR: 9821 spec->num_outputs = 2; 9822 spec->out_pins[0] = 0x0B; /* Line out */ 9823 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9824 spec->out_pins[2] = 0x10; /* Center/LFE */ 9825 spec->out_pins[3] = 0x11; /* Rear surround */ 9826 spec->shared_out_nid = 0x2; 9827 spec->unsol_tag_hp = spec->out_pins[1]; 9828 spec->unsol_tag_front_hp = spec->out_pins[2]; 9829 9830 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9831 spec->adcs[1] = 0x8; /* Not connected, no front mic */ 9832 spec->adcs[2] = 0xa; /* what u hear */ 9833 9834 spec->num_inputs = 2; 9835 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9836 spec->input_pins[1] = 0x13; /* What U Hear */ 9837 spec->shared_mic_nid = 0x7; 9838 spec->unsol_tag_amic1 = spec->input_pins[0]; 9839 break; 9840 case QUIRK_ZXR_DBPRO: 9841 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */ 9842 9843 spec->num_inputs = 1; 9844 spec->input_pins[0] = 0x11; /* RCA Line-in */ 9845 9846 spec->dig_out = 0x05; 9847 spec->multiout.dig_out_nid = spec->dig_out; 9848 9849 spec->dig_in = 0x09; 9850 break; 9851 case QUIRK_AE5: 9852 case QUIRK_AE7: 9853 spec->num_outputs = 2; 9854 spec->out_pins[0] = 0x0B; /* Line out */ 9855 spec->out_pins[1] = 0x11; /* Rear headphone out */ 9856 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9857 spec->out_pins[3] = 0x0F; /* Rear surround */ 9858 spec->shared_out_nid = 0x2; 9859 spec->unsol_tag_hp = spec->out_pins[1]; 9860 spec->unsol_tag_front_hp = spec->out_pins[2]; 9861 9862 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9863 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 9864 spec->adcs[2] = 0xa; /* what u hear */ 9865 9866 spec->num_inputs = 2; 9867 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9868 spec->input_pins[1] = 0x13; /* What U Hear */ 9869 spec->shared_mic_nid = 0x7; 9870 spec->unsol_tag_amic1 = spec->input_pins[0]; 9871 9872 /* SPDIF I/O */ 9873 spec->dig_out = 0x05; 9874 spec->multiout.dig_out_nid = spec->dig_out; 9875 break; 9876 case QUIRK_R3DI: 9877 spec->num_outputs = 2; 9878 spec->out_pins[0] = 0x0B; /* Line out */ 9879 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9880 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9881 spec->out_pins[3] = 0x11; /* Rear surround */ 9882 spec->shared_out_nid = 0x2; 9883 spec->unsol_tag_hp = spec->out_pins[1]; 9884 spec->unsol_tag_front_hp = spec->out_pins[2]; 9885 9886 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */ 9887 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */ 9888 spec->adcs[2] = 0x0a; /* what u hear */ 9889 9890 spec->num_inputs = 2; 9891 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9892 spec->input_pins[1] = 0x13; /* What U Hear */ 9893 spec->shared_mic_nid = 0x7; 9894 spec->unsol_tag_amic1 = spec->input_pins[0]; 9895 9896 /* SPDIF I/O */ 9897 spec->dig_out = 0x05; 9898 spec->multiout.dig_out_nid = spec->dig_out; 9899 break; 9900 default: 9901 spec->num_outputs = 2; 9902 spec->out_pins[0] = 0x0b; /* speaker out */ 9903 spec->out_pins[1] = 0x10; /* headphone out */ 9904 spec->shared_out_nid = 0x2; 9905 spec->unsol_tag_hp = spec->out_pins[1]; 9906 9907 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 9908 spec->adcs[1] = 0x8; /* analog mic2 */ 9909 spec->adcs[2] = 0xa; /* what u hear */ 9910 9911 spec->num_inputs = 3; 9912 spec->input_pins[0] = 0x12; 9913 spec->input_pins[1] = 0x11; 9914 spec->input_pins[2] = 0x13; 9915 spec->shared_mic_nid = 0x7; 9916 spec->unsol_tag_amic1 = spec->input_pins[0]; 9917 9918 /* SPDIF I/O */ 9919 spec->dig_out = 0x05; 9920 spec->multiout.dig_out_nid = spec->dig_out; 9921 spec->dig_in = 0x09; 9922 break; 9923 } 9924 } 9925 9926 static int ca0132_prepare_verbs(struct hda_codec *codec) 9927 { 9928 /* Verbs + terminator (an empty element) */ 9929 #define NUM_SPEC_VERBS 2 9930 struct ca0132_spec *spec = codec->spec; 9931 9932 spec->chip_init_verbs = ca0132_init_verbs0; 9933 /* 9934 * Since desktop cards use pci_mmio, this can be used to determine 9935 * whether or not to use these verbs instead of a separate bool. 9936 */ 9937 if (ca0132_use_pci_mmio(spec)) 9938 spec->desktop_init_verbs = ca0132_init_verbs1; 9939 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS, 9940 sizeof(struct hda_verb), 9941 GFP_KERNEL); 9942 if (!spec->spec_init_verbs) 9943 return -ENOMEM; 9944 9945 /* config EAPD */ 9946 spec->spec_init_verbs[0].nid = 0x0b; 9947 spec->spec_init_verbs[0].param = 0x78D; 9948 spec->spec_init_verbs[0].verb = 0x00; 9949 9950 /* Previously commented configuration */ 9951 /* 9952 spec->spec_init_verbs[2].nid = 0x0b; 9953 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE; 9954 spec->spec_init_verbs[2].verb = 0x02; 9955 9956 spec->spec_init_verbs[3].nid = 0x10; 9957 spec->spec_init_verbs[3].param = 0x78D; 9958 spec->spec_init_verbs[3].verb = 0x02; 9959 9960 spec->spec_init_verbs[4].nid = 0x10; 9961 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE; 9962 spec->spec_init_verbs[4].verb = 0x02; 9963 */ 9964 9965 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */ 9966 return 0; 9967 } 9968 9969 /* 9970 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular 9971 * Sound Blaster Z cards. However, they have different HDA codec subsystem 9972 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro 9973 * daughter boards ID. 9974 */ 9975 static void sbz_detect_quirk(struct hda_codec *codec) 9976 { 9977 switch (codec->core.subsystem_id) { 9978 case 0x11020033: 9979 codec->fixup_id = QUIRK_ZXR; 9980 break; 9981 case 0x1102003f: 9982 codec->fixup_id = QUIRK_ZXR_DBPRO; 9983 break; 9984 default: 9985 codec->fixup_id = QUIRK_SBZ; 9986 break; 9987 } 9988 } 9989 9990 static int patch_ca0132(struct hda_codec *codec) 9991 { 9992 struct ca0132_spec *spec; 9993 int err; 9994 9995 codec_dbg(codec, "patch_ca0132\n"); 9996 9997 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 9998 if (!spec) 9999 return -ENOMEM; 10000 codec->spec = spec; 10001 spec->codec = codec; 10002 10003 /* Detect codec quirk */ 10004 snd_hda_pick_fixup(codec, ca0132_quirk_models, ca0132_quirks, NULL); 10005 if (ca0132_quirk(spec) == QUIRK_SBZ) 10006 sbz_detect_quirk(codec); 10007 10008 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO) 10009 codec->patch_ops = dbpro_patch_ops; 10010 else 10011 codec->patch_ops = ca0132_patch_ops; 10012 10013 codec->pcm_format_first = 1; 10014 codec->no_sticky_stream = 1; 10015 10016 10017 spec->dsp_state = DSP_DOWNLOAD_INIT; 10018 spec->num_mixers = 1; 10019 10020 /* Set which mixers each quirk uses. */ 10021 switch (ca0132_quirk(spec)) { 10022 case QUIRK_SBZ: 10023 spec->mixers[0] = desktop_mixer; 10024 snd_hda_codec_set_name(codec, "Sound Blaster Z"); 10025 break; 10026 case QUIRK_ZXR: 10027 spec->mixers[0] = desktop_mixer; 10028 snd_hda_codec_set_name(codec, "Sound Blaster ZxR"); 10029 break; 10030 case QUIRK_ZXR_DBPRO: 10031 break; 10032 case QUIRK_R3D: 10033 spec->mixers[0] = desktop_mixer; 10034 snd_hda_codec_set_name(codec, "Recon3D"); 10035 break; 10036 case QUIRK_R3DI: 10037 spec->mixers[0] = r3di_mixer; 10038 snd_hda_codec_set_name(codec, "Recon3Di"); 10039 break; 10040 case QUIRK_AE5: 10041 spec->mixers[0] = desktop_mixer; 10042 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5"); 10043 break; 10044 case QUIRK_AE7: 10045 spec->mixers[0] = desktop_mixer; 10046 snd_hda_codec_set_name(codec, "Sound Blaster AE-7"); 10047 break; 10048 default: 10049 spec->mixers[0] = ca0132_mixer; 10050 break; 10051 } 10052 10053 /* Setup whether or not to use alt functions/controls/pci_mmio */ 10054 switch (ca0132_quirk(spec)) { 10055 case QUIRK_SBZ: 10056 case QUIRK_R3D: 10057 case QUIRK_AE5: 10058 case QUIRK_AE7: 10059 case QUIRK_ZXR: 10060 spec->use_alt_controls = true; 10061 spec->use_alt_functions = true; 10062 spec->use_pci_mmio = true; 10063 break; 10064 case QUIRK_R3DI: 10065 spec->use_alt_controls = true; 10066 spec->use_alt_functions = true; 10067 spec->use_pci_mmio = false; 10068 break; 10069 default: 10070 spec->use_alt_controls = false; 10071 spec->use_alt_functions = false; 10072 spec->use_pci_mmio = false; 10073 break; 10074 } 10075 10076 #ifdef CONFIG_PCI 10077 if (spec->use_pci_mmio) { 10078 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20); 10079 if (spec->mem_base == NULL) { 10080 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE."); 10081 codec->fixup_id = QUIRK_NONE; 10082 } 10083 } 10084 #endif 10085 10086 spec->base_init_verbs = ca0132_base_init_verbs; 10087 spec->base_exit_verbs = ca0132_base_exit_verbs; 10088 10089 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed); 10090 10091 ca0132_init_chip(codec); 10092 10093 ca0132_config(codec); 10094 10095 err = ca0132_prepare_verbs(codec); 10096 if (err < 0) 10097 goto error; 10098 10099 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL); 10100 if (err < 0) 10101 goto error; 10102 10103 ca0132_setup_unsol(codec); 10104 10105 return 0; 10106 10107 error: 10108 ca0132_free(codec); 10109 return err; 10110 } 10111 10112 /* 10113 * patch entries 10114 */ 10115 static const struct hda_device_id snd_hda_id_ca0132[] = { 10116 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132), 10117 {} /* terminator */ 10118 }; 10119 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132); 10120 10121 MODULE_LICENSE("GPL"); 10122 MODULE_DESCRIPTION("Creative Sound Core3D codec"); 10123 10124 static struct hda_codec_driver ca0132_driver = { 10125 .id = snd_hda_id_ca0132, 10126 }; 10127 10128 module_hda_codec_driver(ca0132_driver); 10129