1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clocksource.h> 9 #include <linux/completion.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/moduleparam.h> 18 #include <linux/mutex.h> 19 #include <linux/of_device.h> 20 #include <linux/slab.h> 21 #include <linux/time.h> 22 #include <linux/string.h> 23 #include <linux/pm_runtime.h> 24 25 #include <sound/core.h> 26 #include <sound/initval.h> 27 28 #include <sound/hda_codec.h> 29 #include "hda_controller.h" 30 31 /* Defines for Nvidia Tegra HDA support */ 32 #define HDA_BAR0 0x8000 33 34 #define HDA_CFG_CMD 0x1004 35 #define HDA_CFG_BAR0 0x1010 36 37 #define HDA_ENABLE_IO_SPACE (1 << 0) 38 #define HDA_ENABLE_MEM_SPACE (1 << 1) 39 #define HDA_ENABLE_BUS_MASTER (1 << 2) 40 #define HDA_ENABLE_SERR (1 << 8) 41 #define HDA_DISABLE_INTR (1 << 10) 42 #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF 43 #define HDA_BAR0_FINAL_PROGRAM (1 << 14) 44 45 /* IPFS */ 46 #define HDA_IPFS_CONFIG 0x180 47 #define HDA_IPFS_EN_FPCI 0x1 48 49 #define HDA_IPFS_FPCI_BAR0 0x80 50 #define HDA_FPCI_BAR0_START 0x40 51 52 #define HDA_IPFS_INTR_MASK 0x188 53 #define HDA_IPFS_EN_INTR (1 << 16) 54 55 /* max number of SDs */ 56 #define NUM_CAPTURE_SD 1 57 #define NUM_PLAYBACK_SD 1 58 59 struct hda_tegra { 60 struct azx chip; 61 struct device *dev; 62 struct clk *hda_clk; 63 struct clk *hda2codec_2x_clk; 64 struct clk *hda2hdmi_clk; 65 void __iomem *regs; 66 struct work_struct probe_work; 67 }; 68 69 #ifdef CONFIG_PM 70 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 71 module_param(power_save, bint, 0644); 72 MODULE_PARM_DESC(power_save, 73 "Automatic power-saving timeout (in seconds, 0 = disable)."); 74 #else 75 #define power_save 0 76 #endif 77 78 static const struct hda_controller_ops hda_tegra_ops; /* nothing special */ 79 80 static void hda_tegra_init(struct hda_tegra *hda) 81 { 82 u32 v; 83 84 /* Enable PCI access */ 85 v = readl(hda->regs + HDA_IPFS_CONFIG); 86 v |= HDA_IPFS_EN_FPCI; 87 writel(v, hda->regs + HDA_IPFS_CONFIG); 88 89 /* Enable MEM/IO space and bus master */ 90 v = readl(hda->regs + HDA_CFG_CMD); 91 v &= ~HDA_DISABLE_INTR; 92 v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE | 93 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR; 94 writel(v, hda->regs + HDA_CFG_CMD); 95 96 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0); 97 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0); 98 writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0); 99 100 v = readl(hda->regs + HDA_IPFS_INTR_MASK); 101 v |= HDA_IPFS_EN_INTR; 102 writel(v, hda->regs + HDA_IPFS_INTR_MASK); 103 } 104 105 static int hda_tegra_enable_clocks(struct hda_tegra *data) 106 { 107 int rc; 108 109 rc = clk_prepare_enable(data->hda_clk); 110 if (rc) 111 return rc; 112 rc = clk_prepare_enable(data->hda2codec_2x_clk); 113 if (rc) 114 goto disable_hda; 115 rc = clk_prepare_enable(data->hda2hdmi_clk); 116 if (rc) 117 goto disable_codec_2x; 118 119 return 0; 120 121 disable_codec_2x: 122 clk_disable_unprepare(data->hda2codec_2x_clk); 123 disable_hda: 124 clk_disable_unprepare(data->hda_clk); 125 return rc; 126 } 127 128 static void hda_tegra_disable_clocks(struct hda_tegra *data) 129 { 130 clk_disable_unprepare(data->hda2hdmi_clk); 131 clk_disable_unprepare(data->hda2codec_2x_clk); 132 clk_disable_unprepare(data->hda_clk); 133 } 134 135 /* 136 * power management 137 */ 138 static int __maybe_unused hda_tegra_suspend(struct device *dev) 139 { 140 struct snd_card *card = dev_get_drvdata(dev); 141 int rc; 142 143 rc = pm_runtime_force_suspend(dev); 144 if (rc < 0) 145 return rc; 146 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 147 148 return 0; 149 } 150 151 static int __maybe_unused hda_tegra_resume(struct device *dev) 152 { 153 struct snd_card *card = dev_get_drvdata(dev); 154 int rc; 155 156 rc = pm_runtime_force_resume(dev); 157 if (rc < 0) 158 return rc; 159 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 160 161 return 0; 162 } 163 164 static int __maybe_unused hda_tegra_runtime_suspend(struct device *dev) 165 { 166 struct snd_card *card = dev_get_drvdata(dev); 167 struct azx *chip = card->private_data; 168 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 169 struct hdac_bus *bus = azx_bus(chip); 170 171 if (chip && chip->running) { 172 azx_stop_chip(chip); 173 synchronize_irq(bus->irq); 174 azx_enter_link_reset(chip); 175 } 176 hda_tegra_disable_clocks(hda); 177 178 return 0; 179 } 180 181 static int __maybe_unused hda_tegra_runtime_resume(struct device *dev) 182 { 183 struct snd_card *card = dev_get_drvdata(dev); 184 struct azx *chip = card->private_data; 185 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 186 int rc; 187 188 rc = hda_tegra_enable_clocks(hda); 189 if (rc != 0) 190 return rc; 191 if (chip && chip->running) { 192 hda_tegra_init(hda); 193 azx_init_chip(chip, 1); 194 } 195 196 return 0; 197 } 198 199 static const struct dev_pm_ops hda_tegra_pm = { 200 SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume) 201 SET_RUNTIME_PM_OPS(hda_tegra_runtime_suspend, 202 hda_tegra_runtime_resume, 203 NULL) 204 }; 205 206 static int hda_tegra_dev_disconnect(struct snd_device *device) 207 { 208 struct azx *chip = device->device_data; 209 210 chip->bus.shutdown = 1; 211 return 0; 212 } 213 214 /* 215 * destructor 216 */ 217 static int hda_tegra_dev_free(struct snd_device *device) 218 { 219 struct azx *chip = device->device_data; 220 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 221 222 cancel_work_sync(&hda->probe_work); 223 if (azx_bus(chip)->chip_init) { 224 azx_stop_all_streams(chip); 225 azx_stop_chip(chip); 226 } 227 228 azx_free_stream_pages(chip); 229 azx_free_streams(chip); 230 snd_hdac_bus_exit(azx_bus(chip)); 231 232 return 0; 233 } 234 235 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev) 236 { 237 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 238 struct hdac_bus *bus = azx_bus(chip); 239 struct device *dev = hda->dev; 240 struct resource *res; 241 242 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 243 hda->regs = devm_ioremap_resource(dev, res); 244 if (IS_ERR(hda->regs)) 245 return PTR_ERR(hda->regs); 246 247 bus->remap_addr = hda->regs + HDA_BAR0; 248 bus->addr = res->start + HDA_BAR0; 249 250 hda_tegra_init(hda); 251 252 return 0; 253 } 254 255 static int hda_tegra_init_clk(struct hda_tegra *hda) 256 { 257 struct device *dev = hda->dev; 258 259 hda->hda_clk = devm_clk_get(dev, "hda"); 260 if (IS_ERR(hda->hda_clk)) { 261 dev_err(dev, "failed to get hda clock\n"); 262 return PTR_ERR(hda->hda_clk); 263 } 264 hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x"); 265 if (IS_ERR(hda->hda2codec_2x_clk)) { 266 dev_err(dev, "failed to get hda2codec_2x clock\n"); 267 return PTR_ERR(hda->hda2codec_2x_clk); 268 } 269 hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi"); 270 if (IS_ERR(hda->hda2hdmi_clk)) { 271 dev_err(dev, "failed to get hda2hdmi clock\n"); 272 return PTR_ERR(hda->hda2hdmi_clk); 273 } 274 275 return 0; 276 } 277 278 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev) 279 { 280 struct hdac_bus *bus = azx_bus(chip); 281 struct snd_card *card = chip->card; 282 int err; 283 unsigned short gcap; 284 int irq_id = platform_get_irq(pdev, 0); 285 const char *sname, *drv_name = "tegra-hda"; 286 struct device_node *np = pdev->dev.of_node; 287 288 err = hda_tegra_init_chip(chip, pdev); 289 if (err) 290 return err; 291 292 err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt, 293 IRQF_SHARED, KBUILD_MODNAME, chip); 294 if (err) { 295 dev_err(chip->card->dev, 296 "unable to request IRQ %d, disabling device\n", 297 irq_id); 298 return err; 299 } 300 bus->irq = irq_id; 301 302 synchronize_irq(bus->irq); 303 304 gcap = azx_readw(chip, GCAP); 305 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 306 307 /* read number of streams from GCAP register instead of using 308 * hardcoded value 309 */ 310 chip->capture_streams = (gcap >> 8) & 0x0f; 311 chip->playback_streams = (gcap >> 12) & 0x0f; 312 if (!chip->playback_streams && !chip->capture_streams) { 313 /* gcap didn't give any info, switching to old method */ 314 chip->playback_streams = NUM_PLAYBACK_SD; 315 chip->capture_streams = NUM_CAPTURE_SD; 316 } 317 chip->capture_index_offset = 0; 318 chip->playback_index_offset = chip->capture_streams; 319 chip->num_streams = chip->playback_streams + chip->capture_streams; 320 321 /* initialize streams */ 322 err = azx_init_streams(chip); 323 if (err < 0) { 324 dev_err(card->dev, "failed to initialize streams: %d\n", err); 325 return err; 326 } 327 328 err = azx_alloc_stream_pages(chip); 329 if (err < 0) { 330 dev_err(card->dev, "failed to allocate stream pages: %d\n", 331 err); 332 return err; 333 } 334 335 /* initialize chip */ 336 azx_init_chip(chip, 1); 337 338 /* codec detection */ 339 if (!bus->codec_mask) { 340 dev_err(card->dev, "no codecs found!\n"); 341 return -ENODEV; 342 } 343 344 /* driver name */ 345 strncpy(card->driver, drv_name, sizeof(card->driver)); 346 /* shortname for card */ 347 sname = of_get_property(np, "nvidia,model", NULL); 348 if (!sname) 349 sname = drv_name; 350 if (strlen(sname) > sizeof(card->shortname)) 351 dev_info(card->dev, "truncating shortname for card\n"); 352 strncpy(card->shortname, sname, sizeof(card->shortname)); 353 354 /* longname for card */ 355 snprintf(card->longname, sizeof(card->longname), 356 "%s at 0x%lx irq %i", 357 card->shortname, bus->addr, bus->irq); 358 359 return 0; 360 } 361 362 /* 363 * constructor 364 */ 365 366 static void hda_tegra_probe_work(struct work_struct *work); 367 368 static int hda_tegra_create(struct snd_card *card, 369 unsigned int driver_caps, 370 struct hda_tegra *hda) 371 { 372 static struct snd_device_ops ops = { 373 .dev_disconnect = hda_tegra_dev_disconnect, 374 .dev_free = hda_tegra_dev_free, 375 }; 376 struct azx *chip; 377 int err; 378 379 chip = &hda->chip; 380 381 mutex_init(&chip->open_mutex); 382 chip->card = card; 383 chip->ops = &hda_tegra_ops; 384 chip->driver_caps = driver_caps; 385 chip->driver_type = driver_caps & 0xff; 386 chip->dev_index = 0; 387 INIT_LIST_HEAD(&chip->pcm_list); 388 389 chip->codec_probe_mask = -1; 390 391 chip->single_cmd = false; 392 chip->snoop = true; 393 394 INIT_WORK(&hda->probe_work, hda_tegra_probe_work); 395 396 err = azx_bus_init(chip, NULL); 397 if (err < 0) 398 return err; 399 400 chip->bus.needs_damn_long_delay = 1; 401 402 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 403 if (err < 0) { 404 dev_err(card->dev, "Error creating device\n"); 405 return err; 406 } 407 408 return 0; 409 } 410 411 static const struct of_device_id hda_tegra_match[] = { 412 { .compatible = "nvidia,tegra30-hda" }, 413 {}, 414 }; 415 MODULE_DEVICE_TABLE(of, hda_tegra_match); 416 417 static int hda_tegra_probe(struct platform_device *pdev) 418 { 419 const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR | 420 AZX_DCAPS_PM_RUNTIME; 421 struct snd_card *card; 422 struct azx *chip; 423 struct hda_tegra *hda; 424 int err; 425 426 hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL); 427 if (!hda) 428 return -ENOMEM; 429 hda->dev = &pdev->dev; 430 chip = &hda->chip; 431 432 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, 433 THIS_MODULE, 0, &card); 434 if (err < 0) { 435 dev_err(&pdev->dev, "Error creating card!\n"); 436 return err; 437 } 438 439 err = hda_tegra_init_clk(hda); 440 if (err < 0) 441 goto out_free; 442 443 err = hda_tegra_create(card, driver_flags, hda); 444 if (err < 0) 445 goto out_free; 446 card->private_data = chip; 447 448 dev_set_drvdata(&pdev->dev, card); 449 450 pm_runtime_enable(hda->dev); 451 if (!azx_has_pm_runtime(chip)) 452 pm_runtime_forbid(hda->dev); 453 454 schedule_work(&hda->probe_work); 455 456 return 0; 457 458 out_free: 459 snd_card_free(card); 460 return err; 461 } 462 463 static void hda_tegra_probe_work(struct work_struct *work) 464 { 465 struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work); 466 struct azx *chip = &hda->chip; 467 struct platform_device *pdev = to_platform_device(hda->dev); 468 int err; 469 470 pm_runtime_get_sync(hda->dev); 471 err = hda_tegra_first_init(chip, pdev); 472 if (err < 0) 473 goto out_free; 474 475 /* create codec instances */ 476 err = azx_probe_codecs(chip, 8); 477 if (err < 0) 478 goto out_free; 479 480 err = azx_codec_configure(chip); 481 if (err < 0) 482 goto out_free; 483 484 err = snd_card_register(chip->card); 485 if (err < 0) 486 goto out_free; 487 488 chip->running = 1; 489 snd_hda_set_power_save(&chip->bus, power_save * 1000); 490 491 out_free: 492 pm_runtime_put(hda->dev); 493 return; /* no error return from async probe */ 494 } 495 496 static int hda_tegra_remove(struct platform_device *pdev) 497 { 498 int ret; 499 500 ret = snd_card_free(dev_get_drvdata(&pdev->dev)); 501 pm_runtime_disable(&pdev->dev); 502 503 return ret; 504 } 505 506 static void hda_tegra_shutdown(struct platform_device *pdev) 507 { 508 struct snd_card *card = dev_get_drvdata(&pdev->dev); 509 struct azx *chip; 510 511 if (!card) 512 return; 513 chip = card->private_data; 514 if (chip && chip->running) 515 azx_stop_chip(chip); 516 } 517 518 static struct platform_driver tegra_platform_hda = { 519 .driver = { 520 .name = "tegra-hda", 521 .pm = &hda_tegra_pm, 522 .of_match_table = hda_tegra_match, 523 }, 524 .probe = hda_tegra_probe, 525 .remove = hda_tegra_remove, 526 .shutdown = hda_tegra_shutdown, 527 }; 528 module_platform_driver(tegra_platform_hda); 529 530 MODULE_DESCRIPTION("Tegra HDA bus driver"); 531 MODULE_LICENSE("GPL v2"); 532