1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clocksource.h> 9 #include <linux/completion.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/moduleparam.h> 18 #include <linux/mutex.h> 19 #include <linux/of_device.h> 20 #include <linux/slab.h> 21 #include <linux/time.h> 22 #include <linux/string.h> 23 #include <linux/pm_runtime.h> 24 25 #include <sound/core.h> 26 #include <sound/initval.h> 27 28 #include <sound/hda_codec.h> 29 #include "hda_controller.h" 30 31 /* Defines for Nvidia Tegra HDA support */ 32 #define HDA_BAR0 0x8000 33 34 #define HDA_CFG_CMD 0x1004 35 #define HDA_CFG_BAR0 0x1010 36 37 #define HDA_ENABLE_IO_SPACE (1 << 0) 38 #define HDA_ENABLE_MEM_SPACE (1 << 1) 39 #define HDA_ENABLE_BUS_MASTER (1 << 2) 40 #define HDA_ENABLE_SERR (1 << 8) 41 #define HDA_DISABLE_INTR (1 << 10) 42 #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF 43 #define HDA_BAR0_FINAL_PROGRAM (1 << 14) 44 45 /* IPFS */ 46 #define HDA_IPFS_CONFIG 0x180 47 #define HDA_IPFS_EN_FPCI 0x1 48 49 #define HDA_IPFS_FPCI_BAR0 0x80 50 #define HDA_FPCI_BAR0_START 0x40 51 52 #define HDA_IPFS_INTR_MASK 0x188 53 #define HDA_IPFS_EN_INTR (1 << 16) 54 55 /* FPCI */ 56 #define FPCI_DBG_CFG_2 0x10F4 57 #define FPCI_GCAP_NSDO_SHIFT 18 58 #define FPCI_GCAP_NSDO_MASK (0x3 << FPCI_GCAP_NSDO_SHIFT) 59 60 /* max number of SDs */ 61 #define NUM_CAPTURE_SD 1 62 #define NUM_PLAYBACK_SD 1 63 64 /* 65 * Tegra194 does not reflect correct number of SDO lines. Below macro 66 * is used to update the GCAP register to workaround the issue. 67 */ 68 #define TEGRA194_NUM_SDO_LINES 4 69 70 struct hda_tegra { 71 struct azx chip; 72 struct device *dev; 73 struct clk *hda_clk; 74 struct clk *hda2codec_2x_clk; 75 struct clk *hda2hdmi_clk; 76 void __iomem *regs; 77 struct work_struct probe_work; 78 }; 79 80 #ifdef CONFIG_PM 81 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 82 module_param(power_save, bint, 0644); 83 MODULE_PARM_DESC(power_save, 84 "Automatic power-saving timeout (in seconds, 0 = disable)."); 85 #else 86 #define power_save 0 87 #endif 88 89 static const struct hda_controller_ops hda_tegra_ops; /* nothing special */ 90 91 static void hda_tegra_init(struct hda_tegra *hda) 92 { 93 u32 v; 94 95 /* Enable PCI access */ 96 v = readl(hda->regs + HDA_IPFS_CONFIG); 97 v |= HDA_IPFS_EN_FPCI; 98 writel(v, hda->regs + HDA_IPFS_CONFIG); 99 100 /* Enable MEM/IO space and bus master */ 101 v = readl(hda->regs + HDA_CFG_CMD); 102 v &= ~HDA_DISABLE_INTR; 103 v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE | 104 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR; 105 writel(v, hda->regs + HDA_CFG_CMD); 106 107 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0); 108 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0); 109 writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0); 110 111 v = readl(hda->regs + HDA_IPFS_INTR_MASK); 112 v |= HDA_IPFS_EN_INTR; 113 writel(v, hda->regs + HDA_IPFS_INTR_MASK); 114 } 115 116 static int hda_tegra_enable_clocks(struct hda_tegra *data) 117 { 118 int rc; 119 120 rc = clk_prepare_enable(data->hda_clk); 121 if (rc) 122 return rc; 123 rc = clk_prepare_enable(data->hda2codec_2x_clk); 124 if (rc) 125 goto disable_hda; 126 rc = clk_prepare_enable(data->hda2hdmi_clk); 127 if (rc) 128 goto disable_codec_2x; 129 130 return 0; 131 132 disable_codec_2x: 133 clk_disable_unprepare(data->hda2codec_2x_clk); 134 disable_hda: 135 clk_disable_unprepare(data->hda_clk); 136 return rc; 137 } 138 139 static void hda_tegra_disable_clocks(struct hda_tegra *data) 140 { 141 clk_disable_unprepare(data->hda2hdmi_clk); 142 clk_disable_unprepare(data->hda2codec_2x_clk); 143 clk_disable_unprepare(data->hda_clk); 144 } 145 146 /* 147 * power management 148 */ 149 static int __maybe_unused hda_tegra_suspend(struct device *dev) 150 { 151 struct snd_card *card = dev_get_drvdata(dev); 152 int rc; 153 154 rc = pm_runtime_force_suspend(dev); 155 if (rc < 0) 156 return rc; 157 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 158 159 return 0; 160 } 161 162 static int __maybe_unused hda_tegra_resume(struct device *dev) 163 { 164 struct snd_card *card = dev_get_drvdata(dev); 165 int rc; 166 167 rc = pm_runtime_force_resume(dev); 168 if (rc < 0) 169 return rc; 170 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 171 172 return 0; 173 } 174 175 static int __maybe_unused hda_tegra_runtime_suspend(struct device *dev) 176 { 177 struct snd_card *card = dev_get_drvdata(dev); 178 struct azx *chip = card->private_data; 179 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 180 181 if (chip && chip->running) { 182 azx_stop_chip(chip); 183 azx_enter_link_reset(chip); 184 } 185 hda_tegra_disable_clocks(hda); 186 187 return 0; 188 } 189 190 static int __maybe_unused hda_tegra_runtime_resume(struct device *dev) 191 { 192 struct snd_card *card = dev_get_drvdata(dev); 193 struct azx *chip = card->private_data; 194 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 195 int rc; 196 197 rc = hda_tegra_enable_clocks(hda); 198 if (rc != 0) 199 return rc; 200 if (chip && chip->running) { 201 hda_tegra_init(hda); 202 azx_init_chip(chip, 1); 203 } 204 205 return 0; 206 } 207 208 static const struct dev_pm_ops hda_tegra_pm = { 209 SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume) 210 SET_RUNTIME_PM_OPS(hda_tegra_runtime_suspend, 211 hda_tegra_runtime_resume, 212 NULL) 213 }; 214 215 static int hda_tegra_dev_disconnect(struct snd_device *device) 216 { 217 struct azx *chip = device->device_data; 218 219 chip->bus.shutdown = 1; 220 return 0; 221 } 222 223 /* 224 * destructor 225 */ 226 static int hda_tegra_dev_free(struct snd_device *device) 227 { 228 struct azx *chip = device->device_data; 229 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 230 231 cancel_work_sync(&hda->probe_work); 232 if (azx_bus(chip)->chip_init) { 233 azx_stop_all_streams(chip); 234 azx_stop_chip(chip); 235 } 236 237 azx_free_stream_pages(chip); 238 azx_free_streams(chip); 239 snd_hdac_bus_exit(azx_bus(chip)); 240 241 return 0; 242 } 243 244 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev) 245 { 246 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 247 struct hdac_bus *bus = azx_bus(chip); 248 struct device *dev = hda->dev; 249 struct resource *res; 250 251 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 252 hda->regs = devm_ioremap_resource(dev, res); 253 if (IS_ERR(hda->regs)) 254 return PTR_ERR(hda->regs); 255 256 bus->remap_addr = hda->regs + HDA_BAR0; 257 bus->addr = res->start + HDA_BAR0; 258 259 hda_tegra_init(hda); 260 261 return 0; 262 } 263 264 static int hda_tegra_init_clk(struct hda_tegra *hda) 265 { 266 struct device *dev = hda->dev; 267 268 hda->hda_clk = devm_clk_get(dev, "hda"); 269 if (IS_ERR(hda->hda_clk)) { 270 dev_err(dev, "failed to get hda clock\n"); 271 return PTR_ERR(hda->hda_clk); 272 } 273 hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x"); 274 if (IS_ERR(hda->hda2codec_2x_clk)) { 275 dev_err(dev, "failed to get hda2codec_2x clock\n"); 276 return PTR_ERR(hda->hda2codec_2x_clk); 277 } 278 hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi"); 279 if (IS_ERR(hda->hda2hdmi_clk)) { 280 dev_err(dev, "failed to get hda2hdmi clock\n"); 281 return PTR_ERR(hda->hda2hdmi_clk); 282 } 283 284 return 0; 285 } 286 287 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev) 288 { 289 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 290 struct hdac_bus *bus = azx_bus(chip); 291 struct snd_card *card = chip->card; 292 int err; 293 unsigned short gcap; 294 int irq_id = platform_get_irq(pdev, 0); 295 const char *sname, *drv_name = "tegra-hda"; 296 struct device_node *np = pdev->dev.of_node; 297 298 err = hda_tegra_init_chip(chip, pdev); 299 if (err) 300 return err; 301 302 err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt, 303 IRQF_SHARED, KBUILD_MODNAME, chip); 304 if (err) { 305 dev_err(chip->card->dev, 306 "unable to request IRQ %d, disabling device\n", 307 irq_id); 308 return err; 309 } 310 bus->irq = irq_id; 311 bus->dma_stop_delay = 100; 312 card->sync_irq = bus->irq; 313 314 /* 315 * Tegra194 has 4 SDO lines and the STRIPE can be used to 316 * indicate how many of the SDO lines the stream should be 317 * striped. But GCAP register does not reflect the true 318 * capability of HW. Below workaround helps to fix this. 319 * 320 * GCAP_NSDO is bits 19:18 in T_AZA_DBG_CFG_2, 321 * 0 for 1 SDO, 1 for 2 SDO, 2 for 4 SDO lines. 322 */ 323 if (of_device_is_compatible(np, "nvidia,tegra194-hda")) { 324 u32 val; 325 326 dev_info(card->dev, "Override SDO lines to %u\n", 327 TEGRA194_NUM_SDO_LINES); 328 329 val = readl(hda->regs + FPCI_DBG_CFG_2) & ~FPCI_GCAP_NSDO_MASK; 330 val |= (TEGRA194_NUM_SDO_LINES >> 1) << FPCI_GCAP_NSDO_SHIFT; 331 writel(val, hda->regs + FPCI_DBG_CFG_2); 332 } 333 334 gcap = azx_readw(chip, GCAP); 335 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 336 337 chip->align_buffer_size = 1; 338 339 /* read number of streams from GCAP register instead of using 340 * hardcoded value 341 */ 342 chip->capture_streams = (gcap >> 8) & 0x0f; 343 chip->playback_streams = (gcap >> 12) & 0x0f; 344 if (!chip->playback_streams && !chip->capture_streams) { 345 /* gcap didn't give any info, switching to old method */ 346 chip->playback_streams = NUM_PLAYBACK_SD; 347 chip->capture_streams = NUM_CAPTURE_SD; 348 } 349 chip->capture_index_offset = 0; 350 chip->playback_index_offset = chip->capture_streams; 351 chip->num_streams = chip->playback_streams + chip->capture_streams; 352 353 /* initialize streams */ 354 err = azx_init_streams(chip); 355 if (err < 0) { 356 dev_err(card->dev, "failed to initialize streams: %d\n", err); 357 return err; 358 } 359 360 err = azx_alloc_stream_pages(chip); 361 if (err < 0) { 362 dev_err(card->dev, "failed to allocate stream pages: %d\n", 363 err); 364 return err; 365 } 366 367 /* initialize chip */ 368 azx_init_chip(chip, 1); 369 370 /* 371 * Playback (for 44.1K/48K, 2-channel, 16-bps) fails with 372 * 4 SDO lines due to legacy design limitation. Following 373 * is, from HD Audio Specification (Revision 1.0a), used to 374 * control striping of the stream across multiple SDO lines 375 * for sample rates <= 48K. 376 * 377 * { ((num_channels * bits_per_sample) / number of SDOs) >= 8 } 378 * 379 * Due to legacy design issue it is recommended that above 380 * ratio must be greater than 8. Since number of SDO lines is 381 * in powers of 2, next available ratio is 16 which can be 382 * used as a limiting factor here. 383 */ 384 if (of_device_is_compatible(np, "nvidia,tegra194-hda")) 385 chip->bus.core.sdo_limit = 16; 386 387 /* codec detection */ 388 if (!bus->codec_mask) { 389 dev_err(card->dev, "no codecs found!\n"); 390 return -ENODEV; 391 } 392 393 /* driver name */ 394 strncpy(card->driver, drv_name, sizeof(card->driver)); 395 /* shortname for card */ 396 sname = of_get_property(np, "nvidia,model", NULL); 397 if (!sname) 398 sname = drv_name; 399 if (strlen(sname) > sizeof(card->shortname)) 400 dev_info(card->dev, "truncating shortname for card\n"); 401 strncpy(card->shortname, sname, sizeof(card->shortname)); 402 403 /* longname for card */ 404 snprintf(card->longname, sizeof(card->longname), 405 "%s at 0x%lx irq %i", 406 card->shortname, bus->addr, bus->irq); 407 408 return 0; 409 } 410 411 /* 412 * constructor 413 */ 414 415 static void hda_tegra_probe_work(struct work_struct *work); 416 417 static int hda_tegra_create(struct snd_card *card, 418 unsigned int driver_caps, 419 struct hda_tegra *hda) 420 { 421 static const struct snd_device_ops ops = { 422 .dev_disconnect = hda_tegra_dev_disconnect, 423 .dev_free = hda_tegra_dev_free, 424 }; 425 struct azx *chip; 426 int err; 427 428 chip = &hda->chip; 429 430 mutex_init(&chip->open_mutex); 431 chip->card = card; 432 chip->ops = &hda_tegra_ops; 433 chip->driver_caps = driver_caps; 434 chip->driver_type = driver_caps & 0xff; 435 chip->dev_index = 0; 436 INIT_LIST_HEAD(&chip->pcm_list); 437 438 chip->codec_probe_mask = -1; 439 440 chip->single_cmd = false; 441 chip->snoop = true; 442 443 INIT_WORK(&hda->probe_work, hda_tegra_probe_work); 444 445 err = azx_bus_init(chip, NULL); 446 if (err < 0) 447 return err; 448 449 chip->bus.core.sync_write = 0; 450 chip->bus.core.needs_damn_long_delay = 1; 451 chip->bus.core.aligned_mmio = 1; 452 453 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 454 if (err < 0) { 455 dev_err(card->dev, "Error creating device\n"); 456 return err; 457 } 458 459 return 0; 460 } 461 462 static const struct of_device_id hda_tegra_match[] = { 463 { .compatible = "nvidia,tegra30-hda" }, 464 { .compatible = "nvidia,tegra194-hda" }, 465 {}, 466 }; 467 MODULE_DEVICE_TABLE(of, hda_tegra_match); 468 469 static int hda_tegra_probe(struct platform_device *pdev) 470 { 471 const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR | 472 AZX_DCAPS_PM_RUNTIME; 473 struct snd_card *card; 474 struct azx *chip; 475 struct hda_tegra *hda; 476 int err; 477 478 hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL); 479 if (!hda) 480 return -ENOMEM; 481 hda->dev = &pdev->dev; 482 chip = &hda->chip; 483 484 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, 485 THIS_MODULE, 0, &card); 486 if (err < 0) { 487 dev_err(&pdev->dev, "Error creating card!\n"); 488 return err; 489 } 490 491 err = hda_tegra_init_clk(hda); 492 if (err < 0) 493 goto out_free; 494 495 err = hda_tegra_create(card, driver_flags, hda); 496 if (err < 0) 497 goto out_free; 498 card->private_data = chip; 499 500 dev_set_drvdata(&pdev->dev, card); 501 502 pm_runtime_enable(hda->dev); 503 if (!azx_has_pm_runtime(chip)) 504 pm_runtime_forbid(hda->dev); 505 506 schedule_work(&hda->probe_work); 507 508 return 0; 509 510 out_free: 511 snd_card_free(card); 512 return err; 513 } 514 515 static void hda_tegra_probe_work(struct work_struct *work) 516 { 517 struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work); 518 struct azx *chip = &hda->chip; 519 struct platform_device *pdev = to_platform_device(hda->dev); 520 int err; 521 522 pm_runtime_get_sync(hda->dev); 523 err = hda_tegra_first_init(chip, pdev); 524 if (err < 0) 525 goto out_free; 526 527 /* create codec instances */ 528 err = azx_probe_codecs(chip, 8); 529 if (err < 0) 530 goto out_free; 531 532 err = azx_codec_configure(chip); 533 if (err < 0) 534 goto out_free; 535 536 err = snd_card_register(chip->card); 537 if (err < 0) 538 goto out_free; 539 540 chip->running = 1; 541 snd_hda_set_power_save(&chip->bus, power_save * 1000); 542 543 out_free: 544 pm_runtime_put(hda->dev); 545 return; /* no error return from async probe */ 546 } 547 548 static int hda_tegra_remove(struct platform_device *pdev) 549 { 550 int ret; 551 552 ret = snd_card_free(dev_get_drvdata(&pdev->dev)); 553 pm_runtime_disable(&pdev->dev); 554 555 return ret; 556 } 557 558 static void hda_tegra_shutdown(struct platform_device *pdev) 559 { 560 struct snd_card *card = dev_get_drvdata(&pdev->dev); 561 struct azx *chip; 562 563 if (!card) 564 return; 565 chip = card->private_data; 566 if (chip && chip->running) 567 azx_stop_chip(chip); 568 } 569 570 static struct platform_driver tegra_platform_hda = { 571 .driver = { 572 .name = "tegra-hda", 573 .pm = &hda_tegra_pm, 574 .of_match_table = hda_tegra_match, 575 }, 576 .probe = hda_tegra_probe, 577 .remove = hda_tegra_remove, 578 .shutdown = hda_tegra_shutdown, 579 }; 580 module_platform_driver(tegra_platform_hda); 581 582 MODULE_DESCRIPTION("Tegra HDA bus driver"); 583 MODULE_LICENSE("GPL v2"); 584