1 /* 2 * 3 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 * 17 */ 18 19 #include <linux/clk.h> 20 #include <linux/clocksource.h> 21 #include <linux/completion.h> 22 #include <linux/delay.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/init.h> 25 #include <linux/interrupt.h> 26 #include <linux/io.h> 27 #include <linux/kernel.h> 28 #include <linux/module.h> 29 #include <linux/moduleparam.h> 30 #include <linux/mutex.h> 31 #include <linux/of_device.h> 32 #include <linux/slab.h> 33 #include <linux/time.h> 34 35 #include <sound/core.h> 36 #include <sound/initval.h> 37 38 #include "hda_codec.h" 39 #include "hda_controller.h" 40 41 /* Defines for Nvidia Tegra HDA support */ 42 #define HDA_BAR0 0x8000 43 44 #define HDA_CFG_CMD 0x1004 45 #define HDA_CFG_BAR0 0x1010 46 47 #define HDA_ENABLE_IO_SPACE (1 << 0) 48 #define HDA_ENABLE_MEM_SPACE (1 << 1) 49 #define HDA_ENABLE_BUS_MASTER (1 << 2) 50 #define HDA_ENABLE_SERR (1 << 8) 51 #define HDA_DISABLE_INTR (1 << 10) 52 #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF 53 #define HDA_BAR0_FINAL_PROGRAM (1 << 14) 54 55 /* IPFS */ 56 #define HDA_IPFS_CONFIG 0x180 57 #define HDA_IPFS_EN_FPCI 0x1 58 59 #define HDA_IPFS_FPCI_BAR0 0x80 60 #define HDA_FPCI_BAR0_START 0x40 61 62 #define HDA_IPFS_INTR_MASK 0x188 63 #define HDA_IPFS_EN_INTR (1 << 16) 64 65 /* max number of SDs */ 66 #define NUM_CAPTURE_SD 1 67 #define NUM_PLAYBACK_SD 1 68 69 struct hda_tegra { 70 struct azx chip; 71 struct device *dev; 72 struct clk *hda_clk; 73 struct clk *hda2codec_2x_clk; 74 struct clk *hda2hdmi_clk; 75 void __iomem *regs; 76 }; 77 78 #ifdef CONFIG_PM 79 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 80 module_param(power_save, bint, 0644); 81 MODULE_PARM_DESC(power_save, 82 "Automatic power-saving timeout (in seconds, 0 = disable)."); 83 #else 84 #define power_save 0 85 #endif 86 87 /* 88 * DMA page allocation ops. 89 */ 90 static int dma_alloc_pages(struct azx *chip, int type, size_t size, 91 struct snd_dma_buffer *buf) 92 { 93 return snd_dma_alloc_pages(type, chip->card->dev, size, buf); 94 } 95 96 static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf) 97 { 98 snd_dma_free_pages(buf); 99 } 100 101 static int substream_alloc_pages(struct azx *chip, 102 struct snd_pcm_substream *substream, 103 size_t size) 104 { 105 struct azx_dev *azx_dev = get_azx_dev(substream); 106 107 azx_dev->bufsize = 0; 108 azx_dev->period_bytes = 0; 109 azx_dev->format_val = 0; 110 return snd_pcm_lib_malloc_pages(substream, size); 111 } 112 113 static int substream_free_pages(struct azx *chip, 114 struct snd_pcm_substream *substream) 115 { 116 return snd_pcm_lib_free_pages(substream); 117 } 118 119 /* 120 * Register access ops. Tegra HDA register access is DWORD only. 121 */ 122 static void hda_tegra_writel(u32 value, u32 *addr) 123 { 124 writel(value, addr); 125 } 126 127 static u32 hda_tegra_readl(u32 *addr) 128 { 129 return readl(addr); 130 } 131 132 static void hda_tegra_writew(u16 value, u16 *addr) 133 { 134 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 135 void *dword_addr = (void *)((unsigned long)(addr) & ~0x3); 136 u32 v; 137 138 v = readl(dword_addr); 139 v &= ~(0xffff << shift); 140 v |= value << shift; 141 writel(v, dword_addr); 142 } 143 144 static u16 hda_tegra_readw(u16 *addr) 145 { 146 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 147 void *dword_addr = (void *)((unsigned long)(addr) & ~0x3); 148 u32 v; 149 150 v = readl(dword_addr); 151 return (v >> shift) & 0xffff; 152 } 153 154 static void hda_tegra_writeb(u8 value, u8 *addr) 155 { 156 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 157 void *dword_addr = (void *)((unsigned long)(addr) & ~0x3); 158 u32 v; 159 160 v = readl(dword_addr); 161 v &= ~(0xff << shift); 162 v |= value << shift; 163 writel(v, dword_addr); 164 } 165 166 static u8 hda_tegra_readb(u8 *addr) 167 { 168 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 169 void *dword_addr = (void *)((unsigned long)(addr) & ~0x3); 170 u32 v; 171 172 v = readl(dword_addr); 173 return (v >> shift) & 0xff; 174 } 175 176 static const struct hda_controller_ops hda_tegra_ops = { 177 .reg_writel = hda_tegra_writel, 178 .reg_readl = hda_tegra_readl, 179 .reg_writew = hda_tegra_writew, 180 .reg_readw = hda_tegra_readw, 181 .reg_writeb = hda_tegra_writeb, 182 .reg_readb = hda_tegra_readb, 183 .dma_alloc_pages = dma_alloc_pages, 184 .dma_free_pages = dma_free_pages, 185 .substream_alloc_pages = substream_alloc_pages, 186 .substream_free_pages = substream_free_pages, 187 }; 188 189 static void hda_tegra_init(struct hda_tegra *hda) 190 { 191 u32 v; 192 193 /* Enable PCI access */ 194 v = readl(hda->regs + HDA_IPFS_CONFIG); 195 v |= HDA_IPFS_EN_FPCI; 196 writel(v, hda->regs + HDA_IPFS_CONFIG); 197 198 /* Enable MEM/IO space and bus master */ 199 v = readl(hda->regs + HDA_CFG_CMD); 200 v &= ~HDA_DISABLE_INTR; 201 v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE | 202 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR; 203 writel(v, hda->regs + HDA_CFG_CMD); 204 205 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0); 206 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0); 207 writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0); 208 209 v = readl(hda->regs + HDA_IPFS_INTR_MASK); 210 v |= HDA_IPFS_EN_INTR; 211 writel(v, hda->regs + HDA_IPFS_INTR_MASK); 212 } 213 214 static int hda_tegra_enable_clocks(struct hda_tegra *data) 215 { 216 int rc; 217 218 rc = clk_prepare_enable(data->hda_clk); 219 if (rc) 220 return rc; 221 rc = clk_prepare_enable(data->hda2codec_2x_clk); 222 if (rc) 223 goto disable_hda; 224 rc = clk_prepare_enable(data->hda2hdmi_clk); 225 if (rc) 226 goto disable_codec_2x; 227 228 return 0; 229 230 disable_codec_2x: 231 clk_disable_unprepare(data->hda2codec_2x_clk); 232 disable_hda: 233 clk_disable_unprepare(data->hda_clk); 234 return rc; 235 } 236 237 #ifdef CONFIG_PM_SLEEP 238 static void hda_tegra_disable_clocks(struct hda_tegra *data) 239 { 240 clk_disable_unprepare(data->hda2hdmi_clk); 241 clk_disable_unprepare(data->hda2codec_2x_clk); 242 clk_disable_unprepare(data->hda_clk); 243 } 244 245 /* 246 * power management 247 */ 248 static int hda_tegra_suspend(struct device *dev) 249 { 250 struct snd_card *card = dev_get_drvdata(dev); 251 struct azx *chip = card->private_data; 252 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 253 254 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 255 256 azx_stop_chip(chip); 257 azx_enter_link_reset(chip); 258 hda_tegra_disable_clocks(hda); 259 260 return 0; 261 } 262 263 static int hda_tegra_resume(struct device *dev) 264 { 265 struct snd_card *card = dev_get_drvdata(dev); 266 struct azx *chip = card->private_data; 267 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 268 269 hda_tegra_enable_clocks(hda); 270 271 hda_tegra_init(hda); 272 273 azx_init_chip(chip, 1); 274 275 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 276 277 return 0; 278 } 279 #endif /* CONFIG_PM_SLEEP */ 280 281 static const struct dev_pm_ops hda_tegra_pm = { 282 SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume) 283 }; 284 285 /* 286 * destructor 287 */ 288 static int hda_tegra_dev_free(struct snd_device *device) 289 { 290 int i; 291 struct azx *chip = device->device_data; 292 293 if (chip->initialized) { 294 for (i = 0; i < chip->num_streams; i++) 295 azx_stream_stop(chip, &chip->azx_dev[i]); 296 azx_stop_chip(chip); 297 } 298 299 azx_free_stream_pages(chip); 300 301 return 0; 302 } 303 304 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev) 305 { 306 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 307 struct device *dev = hda->dev; 308 struct resource *res; 309 int err; 310 311 hda->hda_clk = devm_clk_get(dev, "hda"); 312 if (IS_ERR(hda->hda_clk)) 313 return PTR_ERR(hda->hda_clk); 314 hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x"); 315 if (IS_ERR(hda->hda2codec_2x_clk)) 316 return PTR_ERR(hda->hda2codec_2x_clk); 317 hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi"); 318 if (IS_ERR(hda->hda2hdmi_clk)) 319 return PTR_ERR(hda->hda2hdmi_clk); 320 321 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 322 hda->regs = devm_ioremap_resource(dev, res); 323 if (IS_ERR(hda->regs)) 324 return PTR_ERR(hda->regs); 325 326 chip->remap_addr = hda->regs + HDA_BAR0; 327 chip->addr = res->start + HDA_BAR0; 328 329 err = hda_tegra_enable_clocks(hda); 330 if (err) 331 return err; 332 333 hda_tegra_init(hda); 334 335 return 0; 336 } 337 338 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev) 339 { 340 struct snd_card *card = chip->card; 341 int err; 342 unsigned short gcap; 343 int irq_id = platform_get_irq(pdev, 0); 344 345 err = hda_tegra_init_chip(chip, pdev); 346 if (err) 347 return err; 348 349 err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt, 350 IRQF_SHARED, KBUILD_MODNAME, chip); 351 if (err) { 352 dev_err(chip->card->dev, 353 "unable to request IRQ %d, disabling device\n", 354 irq_id); 355 return err; 356 } 357 chip->irq = irq_id; 358 359 synchronize_irq(chip->irq); 360 361 gcap = azx_readw(chip, GCAP); 362 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 363 364 /* read number of streams from GCAP register instead of using 365 * hardcoded value 366 */ 367 chip->capture_streams = (gcap >> 8) & 0x0f; 368 chip->playback_streams = (gcap >> 12) & 0x0f; 369 if (!chip->playback_streams && !chip->capture_streams) { 370 /* gcap didn't give any info, switching to old method */ 371 chip->playback_streams = NUM_PLAYBACK_SD; 372 chip->capture_streams = NUM_CAPTURE_SD; 373 } 374 chip->capture_index_offset = 0; 375 chip->playback_index_offset = chip->capture_streams; 376 chip->num_streams = chip->playback_streams + chip->capture_streams; 377 chip->azx_dev = devm_kcalloc(card->dev, chip->num_streams, 378 sizeof(*chip->azx_dev), GFP_KERNEL); 379 if (!chip->azx_dev) 380 return -ENOMEM; 381 382 err = azx_alloc_stream_pages(chip); 383 if (err < 0) 384 return err; 385 386 /* initialize streams */ 387 azx_init_stream(chip); 388 389 /* initialize chip */ 390 azx_init_chip(chip, 1); 391 392 /* codec detection */ 393 if (!chip->codec_mask) { 394 dev_err(card->dev, "no codecs found!\n"); 395 return -ENODEV; 396 } 397 398 strcpy(card->driver, "tegra-hda"); 399 strcpy(card->shortname, "tegra-hda"); 400 snprintf(card->longname, sizeof(card->longname), 401 "%s at 0x%lx irq %i", 402 card->shortname, chip->addr, chip->irq); 403 404 return 0; 405 } 406 407 /* 408 * constructor 409 */ 410 static int hda_tegra_create(struct snd_card *card, 411 unsigned int driver_caps, 412 const struct hda_controller_ops *hda_ops, 413 struct hda_tegra *hda) 414 { 415 static struct snd_device_ops ops = { 416 .dev_free = hda_tegra_dev_free, 417 }; 418 struct azx *chip; 419 int err; 420 421 chip = &hda->chip; 422 423 spin_lock_init(&chip->reg_lock); 424 mutex_init(&chip->open_mutex); 425 chip->card = card; 426 chip->ops = hda_ops; 427 chip->irq = -1; 428 chip->driver_caps = driver_caps; 429 chip->driver_type = driver_caps & 0xff; 430 chip->dev_index = 0; 431 INIT_LIST_HEAD(&chip->pcm_list); 432 433 chip->codec_probe_mask = -1; 434 435 chip->single_cmd = false; 436 chip->snoop = true; 437 438 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 439 if (err < 0) { 440 dev_err(card->dev, "Error creating device\n"); 441 return err; 442 } 443 444 return 0; 445 } 446 447 static const struct of_device_id hda_tegra_match[] = { 448 { .compatible = "nvidia,tegra30-hda" }, 449 {}, 450 }; 451 MODULE_DEVICE_TABLE(of, hda_tegra_match); 452 453 static int hda_tegra_probe(struct platform_device *pdev) 454 { 455 struct snd_card *card; 456 struct azx *chip; 457 struct hda_tegra *hda; 458 int err; 459 const unsigned int driver_flags = AZX_DCAPS_RIRB_DELAY; 460 461 hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL); 462 if (!hda) 463 return -ENOMEM; 464 hda->dev = &pdev->dev; 465 chip = &hda->chip; 466 467 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, 468 THIS_MODULE, 0, &card); 469 if (err < 0) { 470 dev_err(&pdev->dev, "Error creating card!\n"); 471 return err; 472 } 473 474 err = hda_tegra_create(card, driver_flags, &hda_tegra_ops, hda); 475 if (err < 0) 476 goto out_free; 477 card->private_data = chip; 478 479 dev_set_drvdata(&pdev->dev, card); 480 481 err = hda_tegra_first_init(chip, pdev); 482 if (err < 0) 483 goto out_free; 484 485 /* create codec instances */ 486 err = azx_bus_create(chip, NULL); 487 if (err < 0) 488 goto out_free; 489 490 err = azx_probe_codecs(chip, 0); 491 if (err < 0) 492 goto out_free; 493 494 err = azx_codec_configure(chip); 495 if (err < 0) 496 goto out_free; 497 498 err = snd_card_register(chip->card); 499 if (err < 0) 500 goto out_free; 501 502 chip->running = 1; 503 snd_hda_set_power_save(chip->bus, power_save * 1000); 504 505 return 0; 506 507 out_free: 508 snd_card_free(card); 509 return err; 510 } 511 512 static int hda_tegra_remove(struct platform_device *pdev) 513 { 514 return snd_card_free(dev_get_drvdata(&pdev->dev)); 515 } 516 517 static void hda_tegra_shutdown(struct platform_device *pdev) 518 { 519 struct snd_card *card = dev_get_drvdata(&pdev->dev); 520 struct azx *chip; 521 522 if (!card) 523 return; 524 chip = card->private_data; 525 if (chip && chip->running) 526 azx_stop_chip(chip); 527 } 528 529 static struct platform_driver tegra_platform_hda = { 530 .driver = { 531 .name = "tegra-hda", 532 .pm = &hda_tegra_pm, 533 .of_match_table = hda_tegra_match, 534 }, 535 .probe = hda_tegra_probe, 536 .remove = hda_tegra_remove, 537 .shutdown = hda_tegra_shutdown, 538 }; 539 module_platform_driver(tegra_platform_hda); 540 541 MODULE_DESCRIPTION("Tegra HDA bus driver"); 542 MODULE_LICENSE("GPL v2"); 543