1 /* 2 * 3 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 * 17 */ 18 19 #include <linux/clk.h> 20 #include <linux/clocksource.h> 21 #include <linux/completion.h> 22 #include <linux/delay.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/init.h> 25 #include <linux/interrupt.h> 26 #include <linux/io.h> 27 #include <linux/kernel.h> 28 #include <linux/module.h> 29 #include <linux/moduleparam.h> 30 #include <linux/mutex.h> 31 #include <linux/of_device.h> 32 #include <linux/slab.h> 33 #include <linux/time.h> 34 #include <linux/string.h> 35 #include <linux/pm_runtime.h> 36 37 #include <sound/core.h> 38 #include <sound/initval.h> 39 40 #include <sound/hda_codec.h> 41 #include "hda_controller.h" 42 43 /* Defines for Nvidia Tegra HDA support */ 44 #define HDA_BAR0 0x8000 45 46 #define HDA_CFG_CMD 0x1004 47 #define HDA_CFG_BAR0 0x1010 48 49 #define HDA_ENABLE_IO_SPACE (1 << 0) 50 #define HDA_ENABLE_MEM_SPACE (1 << 1) 51 #define HDA_ENABLE_BUS_MASTER (1 << 2) 52 #define HDA_ENABLE_SERR (1 << 8) 53 #define HDA_DISABLE_INTR (1 << 10) 54 #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF 55 #define HDA_BAR0_FINAL_PROGRAM (1 << 14) 56 57 /* IPFS */ 58 #define HDA_IPFS_CONFIG 0x180 59 #define HDA_IPFS_EN_FPCI 0x1 60 61 #define HDA_IPFS_FPCI_BAR0 0x80 62 #define HDA_FPCI_BAR0_START 0x40 63 64 #define HDA_IPFS_INTR_MASK 0x188 65 #define HDA_IPFS_EN_INTR (1 << 16) 66 67 /* max number of SDs */ 68 #define NUM_CAPTURE_SD 1 69 #define NUM_PLAYBACK_SD 1 70 71 struct hda_tegra { 72 struct azx chip; 73 struct device *dev; 74 struct clk *hda_clk; 75 struct clk *hda2codec_2x_clk; 76 struct clk *hda2hdmi_clk; 77 void __iomem *regs; 78 struct work_struct probe_work; 79 }; 80 81 #ifdef CONFIG_PM 82 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 83 module_param(power_save, bint, 0644); 84 MODULE_PARM_DESC(power_save, 85 "Automatic power-saving timeout (in seconds, 0 = disable)."); 86 #else 87 #define power_save 0 88 #endif 89 90 /* 91 * DMA page allocation ops. 92 */ 93 static int dma_alloc_pages(struct hdac_bus *bus, int type, size_t size, 94 struct snd_dma_buffer *buf) 95 { 96 return snd_dma_alloc_pages(type, bus->dev, size, buf); 97 } 98 99 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf) 100 { 101 snd_dma_free_pages(buf); 102 } 103 104 /* 105 * Register access ops. Tegra HDA register access is DWORD only. 106 */ 107 static void hda_tegra_writel(u32 value, u32 __iomem *addr) 108 { 109 writel(value, addr); 110 } 111 112 static u32 hda_tegra_readl(u32 __iomem *addr) 113 { 114 return readl(addr); 115 } 116 117 static void hda_tegra_writew(u16 value, u16 __iomem *addr) 118 { 119 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 120 void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3); 121 u32 v; 122 123 v = readl(dword_addr); 124 v &= ~(0xffff << shift); 125 v |= value << shift; 126 writel(v, dword_addr); 127 } 128 129 static u16 hda_tegra_readw(u16 __iomem *addr) 130 { 131 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 132 void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3); 133 u32 v; 134 135 v = readl(dword_addr); 136 return (v >> shift) & 0xffff; 137 } 138 139 static void hda_tegra_writeb(u8 value, u8 __iomem *addr) 140 { 141 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 142 void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3); 143 u32 v; 144 145 v = readl(dword_addr); 146 v &= ~(0xff << shift); 147 v |= value << shift; 148 writel(v, dword_addr); 149 } 150 151 static u8 hda_tegra_readb(u8 __iomem *addr) 152 { 153 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 154 void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3); 155 u32 v; 156 157 v = readl(dword_addr); 158 return (v >> shift) & 0xff; 159 } 160 161 static const struct hdac_io_ops hda_tegra_io_ops = { 162 .reg_writel = hda_tegra_writel, 163 .reg_readl = hda_tegra_readl, 164 .reg_writew = hda_tegra_writew, 165 .reg_readw = hda_tegra_readw, 166 .reg_writeb = hda_tegra_writeb, 167 .reg_readb = hda_tegra_readb, 168 .dma_alloc_pages = dma_alloc_pages, 169 .dma_free_pages = dma_free_pages, 170 }; 171 172 static const struct hda_controller_ops hda_tegra_ops; /* nothing special */ 173 174 static void hda_tegra_init(struct hda_tegra *hda) 175 { 176 u32 v; 177 178 /* Enable PCI access */ 179 v = readl(hda->regs + HDA_IPFS_CONFIG); 180 v |= HDA_IPFS_EN_FPCI; 181 writel(v, hda->regs + HDA_IPFS_CONFIG); 182 183 /* Enable MEM/IO space and bus master */ 184 v = readl(hda->regs + HDA_CFG_CMD); 185 v &= ~HDA_DISABLE_INTR; 186 v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE | 187 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR; 188 writel(v, hda->regs + HDA_CFG_CMD); 189 190 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0); 191 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0); 192 writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0); 193 194 v = readl(hda->regs + HDA_IPFS_INTR_MASK); 195 v |= HDA_IPFS_EN_INTR; 196 writel(v, hda->regs + HDA_IPFS_INTR_MASK); 197 } 198 199 static int hda_tegra_enable_clocks(struct hda_tegra *data) 200 { 201 int rc; 202 203 rc = clk_prepare_enable(data->hda_clk); 204 if (rc) 205 return rc; 206 rc = clk_prepare_enable(data->hda2codec_2x_clk); 207 if (rc) 208 goto disable_hda; 209 rc = clk_prepare_enable(data->hda2hdmi_clk); 210 if (rc) 211 goto disable_codec_2x; 212 213 return 0; 214 215 disable_codec_2x: 216 clk_disable_unprepare(data->hda2codec_2x_clk); 217 disable_hda: 218 clk_disable_unprepare(data->hda_clk); 219 return rc; 220 } 221 222 static void hda_tegra_disable_clocks(struct hda_tegra *data) 223 { 224 clk_disable_unprepare(data->hda2hdmi_clk); 225 clk_disable_unprepare(data->hda2codec_2x_clk); 226 clk_disable_unprepare(data->hda_clk); 227 } 228 229 /* 230 * power management 231 */ 232 static int __maybe_unused hda_tegra_suspend(struct device *dev) 233 { 234 struct snd_card *card = dev_get_drvdata(dev); 235 int rc; 236 237 rc = pm_runtime_force_suspend(dev); 238 if (rc < 0) 239 return rc; 240 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 241 242 return 0; 243 } 244 245 static int __maybe_unused hda_tegra_resume(struct device *dev) 246 { 247 struct snd_card *card = dev_get_drvdata(dev); 248 int rc; 249 250 rc = pm_runtime_force_resume(dev); 251 if (rc < 0) 252 return rc; 253 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 254 255 return 0; 256 } 257 258 static int __maybe_unused hda_tegra_runtime_suspend(struct device *dev) 259 { 260 struct snd_card *card = dev_get_drvdata(dev); 261 struct azx *chip = card->private_data; 262 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 263 struct hdac_bus *bus = azx_bus(chip); 264 265 if (chip && chip->running) { 266 azx_stop_chip(chip); 267 synchronize_irq(bus->irq); 268 azx_enter_link_reset(chip); 269 } 270 hda_tegra_disable_clocks(hda); 271 272 return 0; 273 } 274 275 static int __maybe_unused hda_tegra_runtime_resume(struct device *dev) 276 { 277 struct snd_card *card = dev_get_drvdata(dev); 278 struct azx *chip = card->private_data; 279 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 280 int rc; 281 282 rc = hda_tegra_enable_clocks(hda); 283 if (rc != 0) 284 return rc; 285 if (chip && chip->running) { 286 hda_tegra_init(hda); 287 azx_init_chip(chip, 1); 288 } 289 290 return 0; 291 } 292 293 static const struct dev_pm_ops hda_tegra_pm = { 294 SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume) 295 SET_RUNTIME_PM_OPS(hda_tegra_runtime_suspend, 296 hda_tegra_runtime_resume, 297 NULL) 298 }; 299 300 static int hda_tegra_dev_disconnect(struct snd_device *device) 301 { 302 struct azx *chip = device->device_data; 303 304 chip->bus.shutdown = 1; 305 return 0; 306 } 307 308 /* 309 * destructor 310 */ 311 static int hda_tegra_dev_free(struct snd_device *device) 312 { 313 struct azx *chip = device->device_data; 314 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 315 316 cancel_work_sync(&hda->probe_work); 317 if (azx_bus(chip)->chip_init) { 318 azx_stop_all_streams(chip); 319 azx_stop_chip(chip); 320 } 321 322 azx_free_stream_pages(chip); 323 azx_free_streams(chip); 324 snd_hdac_bus_exit(azx_bus(chip)); 325 326 return 0; 327 } 328 329 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev) 330 { 331 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 332 struct hdac_bus *bus = azx_bus(chip); 333 struct device *dev = hda->dev; 334 struct resource *res; 335 336 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 337 hda->regs = devm_ioremap_resource(dev, res); 338 if (IS_ERR(hda->regs)) 339 return PTR_ERR(hda->regs); 340 341 bus->remap_addr = hda->regs + HDA_BAR0; 342 bus->addr = res->start + HDA_BAR0; 343 344 hda_tegra_init(hda); 345 346 return 0; 347 } 348 349 static int hda_tegra_init_clk(struct hda_tegra *hda) 350 { 351 struct device *dev = hda->dev; 352 353 hda->hda_clk = devm_clk_get(dev, "hda"); 354 if (IS_ERR(hda->hda_clk)) { 355 dev_err(dev, "failed to get hda clock\n"); 356 return PTR_ERR(hda->hda_clk); 357 } 358 hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x"); 359 if (IS_ERR(hda->hda2codec_2x_clk)) { 360 dev_err(dev, "failed to get hda2codec_2x clock\n"); 361 return PTR_ERR(hda->hda2codec_2x_clk); 362 } 363 hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi"); 364 if (IS_ERR(hda->hda2hdmi_clk)) { 365 dev_err(dev, "failed to get hda2hdmi clock\n"); 366 return PTR_ERR(hda->hda2hdmi_clk); 367 } 368 369 return 0; 370 } 371 372 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev) 373 { 374 struct hdac_bus *bus = azx_bus(chip); 375 struct snd_card *card = chip->card; 376 int err; 377 unsigned short gcap; 378 int irq_id = platform_get_irq(pdev, 0); 379 const char *sname, *drv_name = "tegra-hda"; 380 struct device_node *np = pdev->dev.of_node; 381 382 err = hda_tegra_init_chip(chip, pdev); 383 if (err) 384 return err; 385 386 err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt, 387 IRQF_SHARED, KBUILD_MODNAME, chip); 388 if (err) { 389 dev_err(chip->card->dev, 390 "unable to request IRQ %d, disabling device\n", 391 irq_id); 392 return err; 393 } 394 bus->irq = irq_id; 395 396 synchronize_irq(bus->irq); 397 398 gcap = azx_readw(chip, GCAP); 399 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 400 401 /* read number of streams from GCAP register instead of using 402 * hardcoded value 403 */ 404 chip->capture_streams = (gcap >> 8) & 0x0f; 405 chip->playback_streams = (gcap >> 12) & 0x0f; 406 if (!chip->playback_streams && !chip->capture_streams) { 407 /* gcap didn't give any info, switching to old method */ 408 chip->playback_streams = NUM_PLAYBACK_SD; 409 chip->capture_streams = NUM_CAPTURE_SD; 410 } 411 chip->capture_index_offset = 0; 412 chip->playback_index_offset = chip->capture_streams; 413 chip->num_streams = chip->playback_streams + chip->capture_streams; 414 415 /* initialize streams */ 416 err = azx_init_streams(chip); 417 if (err < 0) { 418 dev_err(card->dev, "failed to initialize streams: %d\n", err); 419 return err; 420 } 421 422 err = azx_alloc_stream_pages(chip); 423 if (err < 0) { 424 dev_err(card->dev, "failed to allocate stream pages: %d\n", 425 err); 426 return err; 427 } 428 429 /* initialize chip */ 430 azx_init_chip(chip, 1); 431 432 /* codec detection */ 433 if (!bus->codec_mask) { 434 dev_err(card->dev, "no codecs found!\n"); 435 return -ENODEV; 436 } 437 438 /* driver name */ 439 strncpy(card->driver, drv_name, sizeof(card->driver)); 440 /* shortname for card */ 441 sname = of_get_property(np, "nvidia,model", NULL); 442 if (!sname) 443 sname = drv_name; 444 if (strlen(sname) > sizeof(card->shortname)) 445 dev_info(card->dev, "truncating shortname for card\n"); 446 strncpy(card->shortname, sname, sizeof(card->shortname)); 447 448 /* longname for card */ 449 snprintf(card->longname, sizeof(card->longname), 450 "%s at 0x%lx irq %i", 451 card->shortname, bus->addr, bus->irq); 452 453 return 0; 454 } 455 456 /* 457 * constructor 458 */ 459 460 static void hda_tegra_probe_work(struct work_struct *work); 461 462 static int hda_tegra_create(struct snd_card *card, 463 unsigned int driver_caps, 464 struct hda_tegra *hda) 465 { 466 static struct snd_device_ops ops = { 467 .dev_disconnect = hda_tegra_dev_disconnect, 468 .dev_free = hda_tegra_dev_free, 469 }; 470 struct azx *chip; 471 int err; 472 473 chip = &hda->chip; 474 475 mutex_init(&chip->open_mutex); 476 chip->card = card; 477 chip->ops = &hda_tegra_ops; 478 chip->driver_caps = driver_caps; 479 chip->driver_type = driver_caps & 0xff; 480 chip->dev_index = 0; 481 INIT_LIST_HEAD(&chip->pcm_list); 482 483 chip->codec_probe_mask = -1; 484 485 chip->single_cmd = false; 486 chip->snoop = true; 487 488 INIT_WORK(&hda->probe_work, hda_tegra_probe_work); 489 490 err = azx_bus_init(chip, NULL, &hda_tegra_io_ops); 491 if (err < 0) 492 return err; 493 494 chip->bus.needs_damn_long_delay = 1; 495 496 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 497 if (err < 0) { 498 dev_err(card->dev, "Error creating device\n"); 499 return err; 500 } 501 502 return 0; 503 } 504 505 static const struct of_device_id hda_tegra_match[] = { 506 { .compatible = "nvidia,tegra30-hda" }, 507 {}, 508 }; 509 MODULE_DEVICE_TABLE(of, hda_tegra_match); 510 511 static int hda_tegra_probe(struct platform_device *pdev) 512 { 513 const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR | 514 AZX_DCAPS_PM_RUNTIME; 515 struct snd_card *card; 516 struct azx *chip; 517 struct hda_tegra *hda; 518 int err; 519 520 hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL); 521 if (!hda) 522 return -ENOMEM; 523 hda->dev = &pdev->dev; 524 chip = &hda->chip; 525 526 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, 527 THIS_MODULE, 0, &card); 528 if (err < 0) { 529 dev_err(&pdev->dev, "Error creating card!\n"); 530 return err; 531 } 532 533 err = hda_tegra_init_clk(hda); 534 if (err < 0) 535 goto out_free; 536 537 err = hda_tegra_create(card, driver_flags, hda); 538 if (err < 0) 539 goto out_free; 540 card->private_data = chip; 541 542 dev_set_drvdata(&pdev->dev, card); 543 544 pm_runtime_enable(hda->dev); 545 if (!azx_has_pm_runtime(chip)) 546 pm_runtime_forbid(hda->dev); 547 548 schedule_work(&hda->probe_work); 549 550 return 0; 551 552 out_free: 553 snd_card_free(card); 554 return err; 555 } 556 557 static void hda_tegra_probe_work(struct work_struct *work) 558 { 559 struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work); 560 struct azx *chip = &hda->chip; 561 struct platform_device *pdev = to_platform_device(hda->dev); 562 int err; 563 564 pm_runtime_get_sync(hda->dev); 565 err = hda_tegra_first_init(chip, pdev); 566 if (err < 0) 567 goto out_free; 568 569 /* create codec instances */ 570 err = azx_probe_codecs(chip, 8); 571 if (err < 0) 572 goto out_free; 573 574 err = azx_codec_configure(chip); 575 if (err < 0) 576 goto out_free; 577 578 err = snd_card_register(chip->card); 579 if (err < 0) 580 goto out_free; 581 582 chip->running = 1; 583 snd_hda_set_power_save(&chip->bus, power_save * 1000); 584 585 out_free: 586 pm_runtime_put(hda->dev); 587 return; /* no error return from async probe */ 588 } 589 590 static int hda_tegra_remove(struct platform_device *pdev) 591 { 592 int ret; 593 594 ret = snd_card_free(dev_get_drvdata(&pdev->dev)); 595 pm_runtime_disable(&pdev->dev); 596 597 return ret; 598 } 599 600 static void hda_tegra_shutdown(struct platform_device *pdev) 601 { 602 struct snd_card *card = dev_get_drvdata(&pdev->dev); 603 struct azx *chip; 604 605 if (!card) 606 return; 607 chip = card->private_data; 608 if (chip && chip->running) 609 azx_stop_chip(chip); 610 } 611 612 static struct platform_driver tegra_platform_hda = { 613 .driver = { 614 .name = "tegra-hda", 615 .pm = &hda_tegra_pm, 616 .of_match_table = hda_tegra_match, 617 }, 618 .probe = hda_tegra_probe, 619 .remove = hda_tegra_remove, 620 .shutdown = hda_tegra_shutdown, 621 }; 622 module_platform_driver(tegra_platform_hda); 623 624 MODULE_DESCRIPTION("Tegra HDA bus driver"); 625 MODULE_LICENSE("GPL v2"); 626