1 /* 2 * 3 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 * 17 */ 18 19 #include <linux/clk.h> 20 #include <linux/clocksource.h> 21 #include <linux/completion.h> 22 #include <linux/delay.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/init.h> 25 #include <linux/interrupt.h> 26 #include <linux/io.h> 27 #include <linux/kernel.h> 28 #include <linux/module.h> 29 #include <linux/moduleparam.h> 30 #include <linux/mutex.h> 31 #include <linux/of_device.h> 32 #include <linux/slab.h> 33 #include <linux/time.h> 34 #include <linux/string.h> 35 36 #include <sound/core.h> 37 #include <sound/initval.h> 38 39 #include <sound/hda_codec.h> 40 #include "hda_controller.h" 41 42 /* Defines for Nvidia Tegra HDA support */ 43 #define HDA_BAR0 0x8000 44 45 #define HDA_CFG_CMD 0x1004 46 #define HDA_CFG_BAR0 0x1010 47 48 #define HDA_ENABLE_IO_SPACE (1 << 0) 49 #define HDA_ENABLE_MEM_SPACE (1 << 1) 50 #define HDA_ENABLE_BUS_MASTER (1 << 2) 51 #define HDA_ENABLE_SERR (1 << 8) 52 #define HDA_DISABLE_INTR (1 << 10) 53 #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF 54 #define HDA_BAR0_FINAL_PROGRAM (1 << 14) 55 56 /* IPFS */ 57 #define HDA_IPFS_CONFIG 0x180 58 #define HDA_IPFS_EN_FPCI 0x1 59 60 #define HDA_IPFS_FPCI_BAR0 0x80 61 #define HDA_FPCI_BAR0_START 0x40 62 63 #define HDA_IPFS_INTR_MASK 0x188 64 #define HDA_IPFS_EN_INTR (1 << 16) 65 66 /* max number of SDs */ 67 #define NUM_CAPTURE_SD 1 68 #define NUM_PLAYBACK_SD 1 69 70 struct hda_tegra { 71 struct azx chip; 72 struct device *dev; 73 struct clk *hda_clk; 74 struct clk *hda2codec_2x_clk; 75 struct clk *hda2hdmi_clk; 76 void __iomem *regs; 77 struct work_struct probe_work; 78 }; 79 80 #ifdef CONFIG_PM 81 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 82 module_param(power_save, bint, 0644); 83 MODULE_PARM_DESC(power_save, 84 "Automatic power-saving timeout (in seconds, 0 = disable)."); 85 #else 86 #define power_save 0 87 #endif 88 89 /* 90 * DMA page allocation ops. 91 */ 92 static int dma_alloc_pages(struct hdac_bus *bus, int type, size_t size, 93 struct snd_dma_buffer *buf) 94 { 95 return snd_dma_alloc_pages(type, bus->dev, size, buf); 96 } 97 98 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf) 99 { 100 snd_dma_free_pages(buf); 101 } 102 103 /* 104 * Register access ops. Tegra HDA register access is DWORD only. 105 */ 106 static void hda_tegra_writel(u32 value, u32 __iomem *addr) 107 { 108 writel(value, addr); 109 } 110 111 static u32 hda_tegra_readl(u32 __iomem *addr) 112 { 113 return readl(addr); 114 } 115 116 static void hda_tegra_writew(u16 value, u16 __iomem *addr) 117 { 118 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 119 void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3); 120 u32 v; 121 122 v = readl(dword_addr); 123 v &= ~(0xffff << shift); 124 v |= value << shift; 125 writel(v, dword_addr); 126 } 127 128 static u16 hda_tegra_readw(u16 __iomem *addr) 129 { 130 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 131 void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3); 132 u32 v; 133 134 v = readl(dword_addr); 135 return (v >> shift) & 0xffff; 136 } 137 138 static void hda_tegra_writeb(u8 value, u8 __iomem *addr) 139 { 140 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 141 void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3); 142 u32 v; 143 144 v = readl(dword_addr); 145 v &= ~(0xff << shift); 146 v |= value << shift; 147 writel(v, dword_addr); 148 } 149 150 static u8 hda_tegra_readb(u8 __iomem *addr) 151 { 152 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 153 void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3); 154 u32 v; 155 156 v = readl(dword_addr); 157 return (v >> shift) & 0xff; 158 } 159 160 static const struct hdac_io_ops hda_tegra_io_ops = { 161 .reg_writel = hda_tegra_writel, 162 .reg_readl = hda_tegra_readl, 163 .reg_writew = hda_tegra_writew, 164 .reg_readw = hda_tegra_readw, 165 .reg_writeb = hda_tegra_writeb, 166 .reg_readb = hda_tegra_readb, 167 .dma_alloc_pages = dma_alloc_pages, 168 .dma_free_pages = dma_free_pages, 169 }; 170 171 static const struct hda_controller_ops hda_tegra_ops; /* nothing special */ 172 173 static void hda_tegra_init(struct hda_tegra *hda) 174 { 175 u32 v; 176 177 /* Enable PCI access */ 178 v = readl(hda->regs + HDA_IPFS_CONFIG); 179 v |= HDA_IPFS_EN_FPCI; 180 writel(v, hda->regs + HDA_IPFS_CONFIG); 181 182 /* Enable MEM/IO space and bus master */ 183 v = readl(hda->regs + HDA_CFG_CMD); 184 v &= ~HDA_DISABLE_INTR; 185 v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE | 186 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR; 187 writel(v, hda->regs + HDA_CFG_CMD); 188 189 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0); 190 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0); 191 writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0); 192 193 v = readl(hda->regs + HDA_IPFS_INTR_MASK); 194 v |= HDA_IPFS_EN_INTR; 195 writel(v, hda->regs + HDA_IPFS_INTR_MASK); 196 } 197 198 static int hda_tegra_enable_clocks(struct hda_tegra *data) 199 { 200 int rc; 201 202 rc = clk_prepare_enable(data->hda_clk); 203 if (rc) 204 return rc; 205 rc = clk_prepare_enable(data->hda2codec_2x_clk); 206 if (rc) 207 goto disable_hda; 208 rc = clk_prepare_enable(data->hda2hdmi_clk); 209 if (rc) 210 goto disable_codec_2x; 211 212 return 0; 213 214 disable_codec_2x: 215 clk_disable_unprepare(data->hda2codec_2x_clk); 216 disable_hda: 217 clk_disable_unprepare(data->hda_clk); 218 return rc; 219 } 220 221 #ifdef CONFIG_PM_SLEEP 222 static void hda_tegra_disable_clocks(struct hda_tegra *data) 223 { 224 clk_disable_unprepare(data->hda2hdmi_clk); 225 clk_disable_unprepare(data->hda2codec_2x_clk); 226 clk_disable_unprepare(data->hda_clk); 227 } 228 229 /* 230 * power management 231 */ 232 static int hda_tegra_suspend(struct device *dev) 233 { 234 struct snd_card *card = dev_get_drvdata(dev); 235 struct azx *chip = card->private_data; 236 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 237 238 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 239 240 azx_stop_chip(chip); 241 azx_enter_link_reset(chip); 242 hda_tegra_disable_clocks(hda); 243 244 return 0; 245 } 246 247 static int hda_tegra_resume(struct device *dev) 248 { 249 struct snd_card *card = dev_get_drvdata(dev); 250 struct azx *chip = card->private_data; 251 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 252 253 hda_tegra_enable_clocks(hda); 254 255 hda_tegra_init(hda); 256 257 azx_init_chip(chip, 1); 258 259 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 260 261 return 0; 262 } 263 #endif /* CONFIG_PM_SLEEP */ 264 265 static const struct dev_pm_ops hda_tegra_pm = { 266 SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume) 267 }; 268 269 static int hda_tegra_dev_disconnect(struct snd_device *device) 270 { 271 struct azx *chip = device->device_data; 272 273 chip->bus.shutdown = 1; 274 return 0; 275 } 276 277 /* 278 * destructor 279 */ 280 static int hda_tegra_dev_free(struct snd_device *device) 281 { 282 struct azx *chip = device->device_data; 283 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 284 285 cancel_work_sync(&hda->probe_work); 286 if (azx_bus(chip)->chip_init) { 287 azx_stop_all_streams(chip); 288 azx_stop_chip(chip); 289 } 290 291 azx_free_stream_pages(chip); 292 azx_free_streams(chip); 293 snd_hdac_bus_exit(azx_bus(chip)); 294 295 return 0; 296 } 297 298 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev) 299 { 300 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 301 struct hdac_bus *bus = azx_bus(chip); 302 struct device *dev = hda->dev; 303 struct resource *res; 304 int err; 305 306 hda->hda_clk = devm_clk_get(dev, "hda"); 307 if (IS_ERR(hda->hda_clk)) { 308 dev_err(dev, "failed to get hda clock\n"); 309 return PTR_ERR(hda->hda_clk); 310 } 311 hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x"); 312 if (IS_ERR(hda->hda2codec_2x_clk)) { 313 dev_err(dev, "failed to get hda2codec_2x clock\n"); 314 return PTR_ERR(hda->hda2codec_2x_clk); 315 } 316 hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi"); 317 if (IS_ERR(hda->hda2hdmi_clk)) { 318 dev_err(dev, "failed to get hda2hdmi clock\n"); 319 return PTR_ERR(hda->hda2hdmi_clk); 320 } 321 322 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 323 hda->regs = devm_ioremap_resource(dev, res); 324 if (IS_ERR(hda->regs)) 325 return PTR_ERR(hda->regs); 326 327 bus->remap_addr = hda->regs + HDA_BAR0; 328 bus->addr = res->start + HDA_BAR0; 329 330 err = hda_tegra_enable_clocks(hda); 331 if (err) { 332 dev_err(dev, "failed to get enable clocks\n"); 333 return err; 334 } 335 336 hda_tegra_init(hda); 337 338 return 0; 339 } 340 341 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev) 342 { 343 struct hdac_bus *bus = azx_bus(chip); 344 struct snd_card *card = chip->card; 345 int err; 346 unsigned short gcap; 347 int irq_id = platform_get_irq(pdev, 0); 348 const char *sname; 349 struct device_node *root; 350 351 err = hda_tegra_init_chip(chip, pdev); 352 if (err) 353 return err; 354 355 err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt, 356 IRQF_SHARED, KBUILD_MODNAME, chip); 357 if (err) { 358 dev_err(chip->card->dev, 359 "unable to request IRQ %d, disabling device\n", 360 irq_id); 361 return err; 362 } 363 bus->irq = irq_id; 364 365 synchronize_irq(bus->irq); 366 367 gcap = azx_readw(chip, GCAP); 368 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 369 370 /* read number of streams from GCAP register instead of using 371 * hardcoded value 372 */ 373 chip->capture_streams = (gcap >> 8) & 0x0f; 374 chip->playback_streams = (gcap >> 12) & 0x0f; 375 if (!chip->playback_streams && !chip->capture_streams) { 376 /* gcap didn't give any info, switching to old method */ 377 chip->playback_streams = NUM_PLAYBACK_SD; 378 chip->capture_streams = NUM_CAPTURE_SD; 379 } 380 chip->capture_index_offset = 0; 381 chip->playback_index_offset = chip->capture_streams; 382 chip->num_streams = chip->playback_streams + chip->capture_streams; 383 384 /* initialize streams */ 385 err = azx_init_streams(chip); 386 if (err < 0) { 387 dev_err(card->dev, "failed to initialize streams: %d\n", err); 388 return err; 389 } 390 391 err = azx_alloc_stream_pages(chip); 392 if (err < 0) { 393 dev_err(card->dev, "failed to allocate stream pages: %d\n", 394 err); 395 return err; 396 } 397 398 /* initialize chip */ 399 azx_init_chip(chip, 1); 400 401 /* codec detection */ 402 if (!bus->codec_mask) { 403 dev_err(card->dev, "no codecs found!\n"); 404 return -ENODEV; 405 } 406 407 /* driver name */ 408 strcpy(card->driver, "tegra-hda"); 409 410 root = of_find_node_by_path("/"); 411 sname = of_get_property(root, "compatible", NULL); 412 of_node_put(root); 413 if (!sname) { 414 dev_err(card->dev, 415 "failed to get compatible property from root node\n"); 416 return -ENODEV; 417 } 418 /* shortname for card */ 419 if (strlen(sname) > sizeof(card->shortname)) 420 dev_info(card->dev, "truncating shortname for card\n"); 421 strncpy(card->shortname, sname, sizeof(card->shortname)); 422 423 /* longname for card */ 424 snprintf(card->longname, sizeof(card->longname), 425 "%s at 0x%lx irq %i", 426 card->shortname, bus->addr, bus->irq); 427 428 return 0; 429 } 430 431 /* 432 * constructor 433 */ 434 435 static void hda_tegra_probe_work(struct work_struct *work); 436 437 static int hda_tegra_create(struct snd_card *card, 438 unsigned int driver_caps, 439 struct hda_tegra *hda) 440 { 441 static struct snd_device_ops ops = { 442 .dev_disconnect = hda_tegra_dev_disconnect, 443 .dev_free = hda_tegra_dev_free, 444 }; 445 struct azx *chip; 446 int err; 447 448 chip = &hda->chip; 449 450 mutex_init(&chip->open_mutex); 451 chip->card = card; 452 chip->ops = &hda_tegra_ops; 453 chip->driver_caps = driver_caps; 454 chip->driver_type = driver_caps & 0xff; 455 chip->dev_index = 0; 456 INIT_LIST_HEAD(&chip->pcm_list); 457 458 chip->codec_probe_mask = -1; 459 460 chip->single_cmd = false; 461 chip->snoop = true; 462 463 INIT_WORK(&hda->probe_work, hda_tegra_probe_work); 464 465 err = azx_bus_init(chip, NULL, &hda_tegra_io_ops); 466 if (err < 0) 467 return err; 468 469 chip->bus.needs_damn_long_delay = 1; 470 471 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 472 if (err < 0) { 473 dev_err(card->dev, "Error creating device\n"); 474 return err; 475 } 476 477 return 0; 478 } 479 480 static const struct of_device_id hda_tegra_match[] = { 481 { .compatible = "nvidia,tegra30-hda" }, 482 {}, 483 }; 484 MODULE_DEVICE_TABLE(of, hda_tegra_match); 485 486 static int hda_tegra_probe(struct platform_device *pdev) 487 { 488 const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR; 489 struct snd_card *card; 490 struct azx *chip; 491 struct hda_tegra *hda; 492 int err; 493 494 hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL); 495 if (!hda) 496 return -ENOMEM; 497 hda->dev = &pdev->dev; 498 chip = &hda->chip; 499 500 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, 501 THIS_MODULE, 0, &card); 502 if (err < 0) { 503 dev_err(&pdev->dev, "Error creating card!\n"); 504 return err; 505 } 506 507 err = hda_tegra_create(card, driver_flags, hda); 508 if (err < 0) 509 goto out_free; 510 card->private_data = chip; 511 512 dev_set_drvdata(&pdev->dev, card); 513 schedule_work(&hda->probe_work); 514 515 return 0; 516 517 out_free: 518 snd_card_free(card); 519 return err; 520 } 521 522 static void hda_tegra_probe_work(struct work_struct *work) 523 { 524 struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work); 525 struct azx *chip = &hda->chip; 526 struct platform_device *pdev = to_platform_device(hda->dev); 527 int err; 528 529 err = hda_tegra_first_init(chip, pdev); 530 if (err < 0) 531 goto out_free; 532 533 /* create codec instances */ 534 err = azx_probe_codecs(chip, 8); 535 if (err < 0) 536 goto out_free; 537 538 err = azx_codec_configure(chip); 539 if (err < 0) 540 goto out_free; 541 542 err = snd_card_register(chip->card); 543 if (err < 0) 544 goto out_free; 545 546 chip->running = 1; 547 snd_hda_set_power_save(&chip->bus, power_save * 1000); 548 549 out_free: 550 return; /* no error return from async probe */ 551 } 552 553 static int hda_tegra_remove(struct platform_device *pdev) 554 { 555 return snd_card_free(dev_get_drvdata(&pdev->dev)); 556 } 557 558 static void hda_tegra_shutdown(struct platform_device *pdev) 559 { 560 struct snd_card *card = dev_get_drvdata(&pdev->dev); 561 struct azx *chip; 562 563 if (!card) 564 return; 565 chip = card->private_data; 566 if (chip && chip->running) 567 azx_stop_chip(chip); 568 } 569 570 static struct platform_driver tegra_platform_hda = { 571 .driver = { 572 .name = "tegra-hda", 573 .pm = &hda_tegra_pm, 574 .of_match_table = hda_tegra_match, 575 }, 576 .probe = hda_tegra_probe, 577 .remove = hda_tegra_remove, 578 .shutdown = hda_tegra_shutdown, 579 }; 580 module_platform_driver(tegra_platform_hda); 581 582 MODULE_DESCRIPTION("Tegra HDA bus driver"); 583 MODULE_LICENSE("GPL v2"); 584