1 /* 2 * 3 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 * 17 */ 18 19 #include <linux/clk.h> 20 #include <linux/clocksource.h> 21 #include <linux/completion.h> 22 #include <linux/delay.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/init.h> 25 #include <linux/interrupt.h> 26 #include <linux/io.h> 27 #include <linux/kernel.h> 28 #include <linux/module.h> 29 #include <linux/moduleparam.h> 30 #include <linux/mutex.h> 31 #include <linux/of_device.h> 32 #include <linux/slab.h> 33 #include <linux/time.h> 34 35 #include <sound/core.h> 36 #include <sound/initval.h> 37 38 #include "hda_codec.h" 39 #include "hda_controller.h" 40 #include "hda_priv.h" 41 42 /* Defines for Nvidia Tegra HDA support */ 43 #define HDA_BAR0 0x8000 44 45 #define HDA_CFG_CMD 0x1004 46 #define HDA_CFG_BAR0 0x1010 47 48 #define HDA_ENABLE_IO_SPACE (1 << 0) 49 #define HDA_ENABLE_MEM_SPACE (1 << 1) 50 #define HDA_ENABLE_BUS_MASTER (1 << 2) 51 #define HDA_ENABLE_SERR (1 << 8) 52 #define HDA_DISABLE_INTR (1 << 10) 53 #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF 54 #define HDA_BAR0_FINAL_PROGRAM (1 << 14) 55 56 /* IPFS */ 57 #define HDA_IPFS_CONFIG 0x180 58 #define HDA_IPFS_EN_FPCI 0x1 59 60 #define HDA_IPFS_FPCI_BAR0 0x80 61 #define HDA_FPCI_BAR0_START 0x40 62 63 #define HDA_IPFS_INTR_MASK 0x188 64 #define HDA_IPFS_EN_INTR (1 << 16) 65 66 /* max number of SDs */ 67 #define NUM_CAPTURE_SD 1 68 #define NUM_PLAYBACK_SD 1 69 70 struct hda_tegra { 71 struct azx chip; 72 struct device *dev; 73 struct clk *hda_clk; 74 struct clk *hda2codec_2x_clk; 75 struct clk *hda2hdmi_clk; 76 void __iomem *regs; 77 }; 78 79 #ifdef CONFIG_PM 80 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 81 module_param(power_save, bint, 0644); 82 MODULE_PARM_DESC(power_save, 83 "Automatic power-saving timeout (in seconds, 0 = disable)."); 84 #else 85 static int power_save = 0; 86 #endif 87 88 /* 89 * DMA page allocation ops. 90 */ 91 static int dma_alloc_pages(struct azx *chip, int type, size_t size, 92 struct snd_dma_buffer *buf) 93 { 94 return snd_dma_alloc_pages(type, chip->card->dev, size, buf); 95 } 96 97 static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf) 98 { 99 snd_dma_free_pages(buf); 100 } 101 102 static int substream_alloc_pages(struct azx *chip, 103 struct snd_pcm_substream *substream, 104 size_t size) 105 { 106 struct azx_dev *azx_dev = get_azx_dev(substream); 107 108 azx_dev->bufsize = 0; 109 azx_dev->period_bytes = 0; 110 azx_dev->format_val = 0; 111 return snd_pcm_lib_malloc_pages(substream, size); 112 } 113 114 static int substream_free_pages(struct azx *chip, 115 struct snd_pcm_substream *substream) 116 { 117 return snd_pcm_lib_free_pages(substream); 118 } 119 120 /* 121 * Register access ops. Tegra HDA register access is DWORD only. 122 */ 123 static void hda_tegra_writel(u32 value, u32 *addr) 124 { 125 writel(value, addr); 126 } 127 128 static u32 hda_tegra_readl(u32 *addr) 129 { 130 return readl(addr); 131 } 132 133 static void hda_tegra_writew(u16 value, u16 *addr) 134 { 135 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 136 void *dword_addr = (void *)((unsigned long)(addr) & ~0x3); 137 u32 v; 138 139 v = readl(dword_addr); 140 v &= ~(0xffff << shift); 141 v |= value << shift; 142 writel(v, dword_addr); 143 } 144 145 static u16 hda_tegra_readw(u16 *addr) 146 { 147 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 148 void *dword_addr = (void *)((unsigned long)(addr) & ~0x3); 149 u32 v; 150 151 v = readl(dword_addr); 152 return (v >> shift) & 0xffff; 153 } 154 155 static void hda_tegra_writeb(u8 value, u8 *addr) 156 { 157 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 158 void *dword_addr = (void *)((unsigned long)(addr) & ~0x3); 159 u32 v; 160 161 v = readl(dword_addr); 162 v &= ~(0xff << shift); 163 v |= value << shift; 164 writel(v, dword_addr); 165 } 166 167 static u8 hda_tegra_readb(u8 *addr) 168 { 169 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 170 void *dword_addr = (void *)((unsigned long)(addr) & ~0x3); 171 u32 v; 172 173 v = readl(dword_addr); 174 return (v >> shift) & 0xff; 175 } 176 177 static const struct hda_controller_ops hda_tegra_ops = { 178 .reg_writel = hda_tegra_writel, 179 .reg_readl = hda_tegra_readl, 180 .reg_writew = hda_tegra_writew, 181 .reg_readw = hda_tegra_readw, 182 .reg_writeb = hda_tegra_writeb, 183 .reg_readb = hda_tegra_readb, 184 .dma_alloc_pages = dma_alloc_pages, 185 .dma_free_pages = dma_free_pages, 186 .substream_alloc_pages = substream_alloc_pages, 187 .substream_free_pages = substream_free_pages, 188 }; 189 190 static void hda_tegra_init(struct hda_tegra *hda) 191 { 192 u32 v; 193 194 /* Enable PCI access */ 195 v = readl(hda->regs + HDA_IPFS_CONFIG); 196 v |= HDA_IPFS_EN_FPCI; 197 writel(v, hda->regs + HDA_IPFS_CONFIG); 198 199 /* Enable MEM/IO space and bus master */ 200 v = readl(hda->regs + HDA_CFG_CMD); 201 v &= ~HDA_DISABLE_INTR; 202 v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE | 203 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR; 204 writel(v, hda->regs + HDA_CFG_CMD); 205 206 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0); 207 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0); 208 writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0); 209 210 v = readl(hda->regs + HDA_IPFS_INTR_MASK); 211 v |= HDA_IPFS_EN_INTR; 212 writel(v, hda->regs + HDA_IPFS_INTR_MASK); 213 } 214 215 static int hda_tegra_enable_clocks(struct hda_tegra *data) 216 { 217 int rc; 218 219 rc = clk_prepare_enable(data->hda_clk); 220 if (rc) 221 return rc; 222 rc = clk_prepare_enable(data->hda2codec_2x_clk); 223 if (rc) 224 goto disable_hda; 225 rc = clk_prepare_enable(data->hda2hdmi_clk); 226 if (rc) 227 goto disable_codec_2x; 228 229 return 0; 230 231 disable_codec_2x: 232 clk_disable_unprepare(data->hda2codec_2x_clk); 233 disable_hda: 234 clk_disable_unprepare(data->hda_clk); 235 return rc; 236 } 237 238 #ifdef CONFIG_PM_SLEEP 239 static void hda_tegra_disable_clocks(struct hda_tegra *data) 240 { 241 clk_disable_unprepare(data->hda2hdmi_clk); 242 clk_disable_unprepare(data->hda2codec_2x_clk); 243 clk_disable_unprepare(data->hda_clk); 244 } 245 246 /* 247 * power management 248 */ 249 static int hda_tegra_suspend(struct device *dev) 250 { 251 struct snd_card *card = dev_get_drvdata(dev); 252 struct azx *chip = card->private_data; 253 struct azx_pcm *p; 254 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 255 256 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 257 list_for_each_entry(p, &chip->pcm_list, list) 258 snd_pcm_suspend_all(p->pcm); 259 if (chip->initialized) 260 snd_hda_suspend(chip->bus); 261 262 azx_stop_chip(chip); 263 azx_enter_link_reset(chip); 264 hda_tegra_disable_clocks(hda); 265 266 return 0; 267 } 268 269 static int hda_tegra_resume(struct device *dev) 270 { 271 struct snd_card *card = dev_get_drvdata(dev); 272 struct azx *chip = card->private_data; 273 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 274 275 hda_tegra_enable_clocks(hda); 276 277 hda_tegra_init(hda); 278 279 azx_init_chip(chip, 1); 280 281 snd_hda_resume(chip->bus); 282 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 283 284 return 0; 285 } 286 #endif /* CONFIG_PM_SLEEP */ 287 288 static const struct dev_pm_ops hda_tegra_pm = { 289 SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume) 290 }; 291 292 /* 293 * destructor 294 */ 295 static int hda_tegra_dev_free(struct snd_device *device) 296 { 297 int i; 298 struct azx *chip = device->device_data; 299 300 azx_notifier_unregister(chip); 301 302 if (chip->initialized) { 303 for (i = 0; i < chip->num_streams; i++) 304 azx_stream_stop(chip, &chip->azx_dev[i]); 305 azx_stop_chip(chip); 306 } 307 308 azx_free_stream_pages(chip); 309 310 return 0; 311 } 312 313 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev) 314 { 315 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 316 struct device *dev = hda->dev; 317 struct resource *res; 318 int err; 319 320 hda->hda_clk = devm_clk_get(dev, "hda"); 321 if (IS_ERR(hda->hda_clk)) 322 return PTR_ERR(hda->hda_clk); 323 hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x"); 324 if (IS_ERR(hda->hda2codec_2x_clk)) 325 return PTR_ERR(hda->hda2codec_2x_clk); 326 hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi"); 327 if (IS_ERR(hda->hda2hdmi_clk)) 328 return PTR_ERR(hda->hda2hdmi_clk); 329 330 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 331 hda->regs = devm_ioremap_resource(dev, res); 332 if (IS_ERR(chip->remap_addr)) 333 return PTR_ERR(chip->remap_addr); 334 335 chip->remap_addr = hda->regs + HDA_BAR0; 336 chip->addr = res->start + HDA_BAR0; 337 338 err = hda_tegra_enable_clocks(hda); 339 if (err) 340 return err; 341 342 hda_tegra_init(hda); 343 344 return 0; 345 } 346 347 /* 348 * The codecs were powered up in snd_hda_codec_new(). 349 * Now all initialization done, so turn them down if possible 350 */ 351 static void power_down_all_codecs(struct azx *chip) 352 { 353 struct hda_codec *codec; 354 list_for_each_entry(codec, &chip->bus->codec_list, list) 355 snd_hda_power_down(codec); 356 } 357 358 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev) 359 { 360 struct snd_card *card = chip->card; 361 int err; 362 unsigned short gcap; 363 int irq_id = platform_get_irq(pdev, 0); 364 365 err = hda_tegra_init_chip(chip, pdev); 366 if (err) 367 return err; 368 369 err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt, 370 IRQF_SHARED, KBUILD_MODNAME, chip); 371 if (err) { 372 dev_err(chip->card->dev, 373 "unable to request IRQ %d, disabling device\n", 374 irq_id); 375 return err; 376 } 377 chip->irq = irq_id; 378 379 synchronize_irq(chip->irq); 380 381 gcap = azx_readw(chip, GCAP); 382 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 383 384 /* read number of streams from GCAP register instead of using 385 * hardcoded value 386 */ 387 chip->capture_streams = (gcap >> 8) & 0x0f; 388 chip->playback_streams = (gcap >> 12) & 0x0f; 389 if (!chip->playback_streams && !chip->capture_streams) { 390 /* gcap didn't give any info, switching to old method */ 391 chip->playback_streams = NUM_PLAYBACK_SD; 392 chip->capture_streams = NUM_CAPTURE_SD; 393 } 394 chip->capture_index_offset = 0; 395 chip->playback_index_offset = chip->capture_streams; 396 chip->num_streams = chip->playback_streams + chip->capture_streams; 397 chip->azx_dev = devm_kcalloc(card->dev, chip->num_streams, 398 sizeof(*chip->azx_dev), GFP_KERNEL); 399 if (!chip->azx_dev) 400 return -ENOMEM; 401 402 err = azx_alloc_stream_pages(chip); 403 if (err < 0) 404 return err; 405 406 /* initialize streams */ 407 azx_init_stream(chip); 408 409 /* initialize chip */ 410 azx_init_chip(chip, 1); 411 412 /* codec detection */ 413 if (!chip->codec_mask) { 414 dev_err(card->dev, "no codecs found!\n"); 415 return -ENODEV; 416 } 417 418 strcpy(card->driver, "tegra-hda"); 419 strcpy(card->shortname, "tegra-hda"); 420 snprintf(card->longname, sizeof(card->longname), 421 "%s at 0x%lx irq %i", 422 card->shortname, chip->addr, chip->irq); 423 424 return 0; 425 } 426 427 /* 428 * constructor 429 */ 430 static int hda_tegra_create(struct snd_card *card, 431 unsigned int driver_caps, 432 const struct hda_controller_ops *hda_ops, 433 struct hda_tegra *hda) 434 { 435 static struct snd_device_ops ops = { 436 .dev_free = hda_tegra_dev_free, 437 }; 438 struct azx *chip; 439 int err; 440 441 chip = &hda->chip; 442 443 spin_lock_init(&chip->reg_lock); 444 mutex_init(&chip->open_mutex); 445 chip->card = card; 446 chip->ops = hda_ops; 447 chip->irq = -1; 448 chip->driver_caps = driver_caps; 449 chip->driver_type = driver_caps & 0xff; 450 chip->dev_index = 0; 451 INIT_LIST_HEAD(&chip->pcm_list); 452 453 chip->codec_probe_mask = -1; 454 455 chip->single_cmd = false; 456 chip->snoop = true; 457 458 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 459 if (err < 0) { 460 dev_err(card->dev, "Error creating device\n"); 461 return err; 462 } 463 464 return 0; 465 } 466 467 static const struct of_device_id hda_tegra_match[] = { 468 { .compatible = "nvidia,tegra30-hda" }, 469 {}, 470 }; 471 MODULE_DEVICE_TABLE(of, hda_tegra_match); 472 473 static int hda_tegra_probe(struct platform_device *pdev) 474 { 475 struct snd_card *card; 476 struct azx *chip; 477 struct hda_tegra *hda; 478 int err; 479 const unsigned int driver_flags = AZX_DCAPS_RIRB_DELAY; 480 481 hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL); 482 if (!hda) 483 return -ENOMEM; 484 hda->dev = &pdev->dev; 485 chip = &hda->chip; 486 487 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, 488 THIS_MODULE, 0, &card); 489 if (err < 0) { 490 dev_err(&pdev->dev, "Error creating card!\n"); 491 return err; 492 } 493 494 err = hda_tegra_create(card, driver_flags, &hda_tegra_ops, hda); 495 if (err < 0) 496 goto out_free; 497 card->private_data = chip; 498 499 dev_set_drvdata(&pdev->dev, card); 500 501 err = hda_tegra_first_init(chip, pdev); 502 if (err < 0) 503 goto out_free; 504 505 /* create codec instances */ 506 err = azx_codec_create(chip, NULL, 0, &power_save); 507 if (err < 0) 508 goto out_free; 509 510 err = azx_codec_configure(chip); 511 if (err < 0) 512 goto out_free; 513 514 /* create PCM streams */ 515 err = snd_hda_build_pcms(chip->bus); 516 if (err < 0) 517 goto out_free; 518 519 /* create mixer controls */ 520 err = azx_mixer_create(chip); 521 if (err < 0) 522 goto out_free; 523 524 err = snd_card_register(chip->card); 525 if (err < 0) 526 goto out_free; 527 528 chip->running = 1; 529 power_down_all_codecs(chip); 530 azx_notifier_register(chip); 531 532 return 0; 533 534 out_free: 535 snd_card_free(card); 536 return err; 537 } 538 539 static int hda_tegra_remove(struct platform_device *pdev) 540 { 541 return snd_card_free(dev_get_drvdata(&pdev->dev)); 542 } 543 544 static struct platform_driver tegra_platform_hda = { 545 .driver = { 546 .name = "tegra-hda", 547 .pm = &hda_tegra_pm, 548 .of_match_table = hda_tegra_match, 549 }, 550 .probe = hda_tegra_probe, 551 .remove = hda_tegra_remove, 552 }; 553 module_platform_driver(tegra_platform_hda); 554 555 MODULE_DESCRIPTION("Tegra HDA bus driver"); 556 MODULE_LICENSE("GPL v2"); 557