1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clocksource.h> 9 #include <linux/completion.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/moduleparam.h> 18 #include <linux/mutex.h> 19 #include <linux/of_device.h> 20 #include <linux/slab.h> 21 #include <linux/time.h> 22 #include <linux/string.h> 23 #include <linux/pm_runtime.h> 24 25 #include <sound/core.h> 26 #include <sound/initval.h> 27 28 #include <sound/hda_codec.h> 29 #include "hda_controller.h" 30 31 /* Defines for Nvidia Tegra HDA support */ 32 #define HDA_BAR0 0x8000 33 34 #define HDA_CFG_CMD 0x1004 35 #define HDA_CFG_BAR0 0x1010 36 37 #define HDA_ENABLE_IO_SPACE (1 << 0) 38 #define HDA_ENABLE_MEM_SPACE (1 << 1) 39 #define HDA_ENABLE_BUS_MASTER (1 << 2) 40 #define HDA_ENABLE_SERR (1 << 8) 41 #define HDA_DISABLE_INTR (1 << 10) 42 #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF 43 #define HDA_BAR0_FINAL_PROGRAM (1 << 14) 44 45 /* IPFS */ 46 #define HDA_IPFS_CONFIG 0x180 47 #define HDA_IPFS_EN_FPCI 0x1 48 49 #define HDA_IPFS_FPCI_BAR0 0x80 50 #define HDA_FPCI_BAR0_START 0x40 51 52 #define HDA_IPFS_INTR_MASK 0x188 53 #define HDA_IPFS_EN_INTR (1 << 16) 54 55 /* FPCI */ 56 #define FPCI_DBG_CFG_2 0x10F4 57 #define FPCI_GCAP_NSDO_SHIFT 18 58 #define FPCI_GCAP_NSDO_MASK (0x3 << FPCI_GCAP_NSDO_SHIFT) 59 60 /* max number of SDs */ 61 #define NUM_CAPTURE_SD 1 62 #define NUM_PLAYBACK_SD 1 63 64 /* 65 * Tegra194 does not reflect correct number of SDO lines. Below macro 66 * is used to update the GCAP register to workaround the issue. 67 */ 68 #define TEGRA194_NUM_SDO_LINES 4 69 70 struct hda_tegra { 71 struct azx chip; 72 struct device *dev; 73 struct clk *hda_clk; 74 struct clk *hda2codec_2x_clk; 75 struct clk *hda2hdmi_clk; 76 void __iomem *regs; 77 struct work_struct probe_work; 78 }; 79 80 #ifdef CONFIG_PM 81 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 82 module_param(power_save, bint, 0644); 83 MODULE_PARM_DESC(power_save, 84 "Automatic power-saving timeout (in seconds, 0 = disable)."); 85 #else 86 #define power_save 0 87 #endif 88 89 static const struct hda_controller_ops hda_tegra_ops; /* nothing special */ 90 91 static void hda_tegra_init(struct hda_tegra *hda) 92 { 93 u32 v; 94 95 /* Enable PCI access */ 96 v = readl(hda->regs + HDA_IPFS_CONFIG); 97 v |= HDA_IPFS_EN_FPCI; 98 writel(v, hda->regs + HDA_IPFS_CONFIG); 99 100 /* Enable MEM/IO space and bus master */ 101 v = readl(hda->regs + HDA_CFG_CMD); 102 v &= ~HDA_DISABLE_INTR; 103 v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE | 104 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR; 105 writel(v, hda->regs + HDA_CFG_CMD); 106 107 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0); 108 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0); 109 writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0); 110 111 v = readl(hda->regs + HDA_IPFS_INTR_MASK); 112 v |= HDA_IPFS_EN_INTR; 113 writel(v, hda->regs + HDA_IPFS_INTR_MASK); 114 } 115 116 static int hda_tegra_enable_clocks(struct hda_tegra *data) 117 { 118 int rc; 119 120 rc = clk_prepare_enable(data->hda_clk); 121 if (rc) 122 return rc; 123 rc = clk_prepare_enable(data->hda2codec_2x_clk); 124 if (rc) 125 goto disable_hda; 126 rc = clk_prepare_enable(data->hda2hdmi_clk); 127 if (rc) 128 goto disable_codec_2x; 129 130 return 0; 131 132 disable_codec_2x: 133 clk_disable_unprepare(data->hda2codec_2x_clk); 134 disable_hda: 135 clk_disable_unprepare(data->hda_clk); 136 return rc; 137 } 138 139 static void hda_tegra_disable_clocks(struct hda_tegra *data) 140 { 141 clk_disable_unprepare(data->hda2hdmi_clk); 142 clk_disable_unprepare(data->hda2codec_2x_clk); 143 clk_disable_unprepare(data->hda_clk); 144 } 145 146 /* 147 * power management 148 */ 149 static int __maybe_unused hda_tegra_suspend(struct device *dev) 150 { 151 struct snd_card *card = dev_get_drvdata(dev); 152 int rc; 153 154 rc = pm_runtime_force_suspend(dev); 155 if (rc < 0) 156 return rc; 157 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 158 159 return 0; 160 } 161 162 static int __maybe_unused hda_tegra_resume(struct device *dev) 163 { 164 struct snd_card *card = dev_get_drvdata(dev); 165 int rc; 166 167 rc = pm_runtime_force_resume(dev); 168 if (rc < 0) 169 return rc; 170 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 171 172 return 0; 173 } 174 175 static int __maybe_unused hda_tegra_runtime_suspend(struct device *dev) 176 { 177 struct snd_card *card = dev_get_drvdata(dev); 178 struct azx *chip = card->private_data; 179 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 180 181 if (chip && chip->running) { 182 /* enable controller wake up event */ 183 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 184 STATESTS_INT_MASK); 185 186 azx_stop_chip(chip); 187 azx_enter_link_reset(chip); 188 } 189 hda_tegra_disable_clocks(hda); 190 191 return 0; 192 } 193 194 static int __maybe_unused hda_tegra_runtime_resume(struct device *dev) 195 { 196 struct snd_card *card = dev_get_drvdata(dev); 197 struct azx *chip = card->private_data; 198 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 199 int rc; 200 201 rc = hda_tegra_enable_clocks(hda); 202 if (rc != 0) 203 return rc; 204 if (chip && chip->running) { 205 hda_tegra_init(hda); 206 azx_init_chip(chip, 1); 207 /* disable controller wake up event*/ 208 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 209 ~STATESTS_INT_MASK); 210 } 211 212 return 0; 213 } 214 215 static const struct dev_pm_ops hda_tegra_pm = { 216 SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume) 217 SET_RUNTIME_PM_OPS(hda_tegra_runtime_suspend, 218 hda_tegra_runtime_resume, 219 NULL) 220 }; 221 222 static int hda_tegra_dev_disconnect(struct snd_device *device) 223 { 224 struct azx *chip = device->device_data; 225 226 chip->bus.shutdown = 1; 227 return 0; 228 } 229 230 /* 231 * destructor 232 */ 233 static int hda_tegra_dev_free(struct snd_device *device) 234 { 235 struct azx *chip = device->device_data; 236 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 237 238 cancel_work_sync(&hda->probe_work); 239 if (azx_bus(chip)->chip_init) { 240 azx_stop_all_streams(chip); 241 azx_stop_chip(chip); 242 } 243 244 azx_free_stream_pages(chip); 245 azx_free_streams(chip); 246 snd_hdac_bus_exit(azx_bus(chip)); 247 248 return 0; 249 } 250 251 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev) 252 { 253 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 254 struct hdac_bus *bus = azx_bus(chip); 255 struct device *dev = hda->dev; 256 struct resource *res; 257 258 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 259 hda->regs = devm_ioremap_resource(dev, res); 260 if (IS_ERR(hda->regs)) 261 return PTR_ERR(hda->regs); 262 263 bus->remap_addr = hda->regs + HDA_BAR0; 264 bus->addr = res->start + HDA_BAR0; 265 266 hda_tegra_init(hda); 267 268 return 0; 269 } 270 271 static int hda_tegra_init_clk(struct hda_tegra *hda) 272 { 273 struct device *dev = hda->dev; 274 275 hda->hda_clk = devm_clk_get(dev, "hda"); 276 if (IS_ERR(hda->hda_clk)) { 277 dev_err(dev, "failed to get hda clock\n"); 278 return PTR_ERR(hda->hda_clk); 279 } 280 hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x"); 281 if (IS_ERR(hda->hda2codec_2x_clk)) { 282 dev_err(dev, "failed to get hda2codec_2x clock\n"); 283 return PTR_ERR(hda->hda2codec_2x_clk); 284 } 285 hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi"); 286 if (IS_ERR(hda->hda2hdmi_clk)) { 287 dev_err(dev, "failed to get hda2hdmi clock\n"); 288 return PTR_ERR(hda->hda2hdmi_clk); 289 } 290 291 return 0; 292 } 293 294 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev) 295 { 296 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 297 struct hdac_bus *bus = azx_bus(chip); 298 struct snd_card *card = chip->card; 299 int err; 300 unsigned short gcap; 301 int irq_id = platform_get_irq(pdev, 0); 302 const char *sname, *drv_name = "tegra-hda"; 303 struct device_node *np = pdev->dev.of_node; 304 305 err = hda_tegra_init_chip(chip, pdev); 306 if (err) 307 return err; 308 309 err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt, 310 IRQF_SHARED, KBUILD_MODNAME, chip); 311 if (err) { 312 dev_err(chip->card->dev, 313 "unable to request IRQ %d, disabling device\n", 314 irq_id); 315 return err; 316 } 317 bus->irq = irq_id; 318 bus->dma_stop_delay = 100; 319 card->sync_irq = bus->irq; 320 321 /* 322 * Tegra194 has 4 SDO lines and the STRIPE can be used to 323 * indicate how many of the SDO lines the stream should be 324 * striped. But GCAP register does not reflect the true 325 * capability of HW. Below workaround helps to fix this. 326 * 327 * GCAP_NSDO is bits 19:18 in T_AZA_DBG_CFG_2, 328 * 0 for 1 SDO, 1 for 2 SDO, 2 for 4 SDO lines. 329 */ 330 if (of_device_is_compatible(np, "nvidia,tegra194-hda")) { 331 u32 val; 332 333 dev_info(card->dev, "Override SDO lines to %u\n", 334 TEGRA194_NUM_SDO_LINES); 335 336 val = readl(hda->regs + FPCI_DBG_CFG_2) & ~FPCI_GCAP_NSDO_MASK; 337 val |= (TEGRA194_NUM_SDO_LINES >> 1) << FPCI_GCAP_NSDO_SHIFT; 338 writel(val, hda->regs + FPCI_DBG_CFG_2); 339 } 340 341 gcap = azx_readw(chip, GCAP); 342 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 343 344 chip->align_buffer_size = 1; 345 346 /* read number of streams from GCAP register instead of using 347 * hardcoded value 348 */ 349 chip->capture_streams = (gcap >> 8) & 0x0f; 350 chip->playback_streams = (gcap >> 12) & 0x0f; 351 if (!chip->playback_streams && !chip->capture_streams) { 352 /* gcap didn't give any info, switching to old method */ 353 chip->playback_streams = NUM_PLAYBACK_SD; 354 chip->capture_streams = NUM_CAPTURE_SD; 355 } 356 chip->capture_index_offset = 0; 357 chip->playback_index_offset = chip->capture_streams; 358 chip->num_streams = chip->playback_streams + chip->capture_streams; 359 360 /* initialize streams */ 361 err = azx_init_streams(chip); 362 if (err < 0) { 363 dev_err(card->dev, "failed to initialize streams: %d\n", err); 364 return err; 365 } 366 367 err = azx_alloc_stream_pages(chip); 368 if (err < 0) { 369 dev_err(card->dev, "failed to allocate stream pages: %d\n", 370 err); 371 return err; 372 } 373 374 /* initialize chip */ 375 azx_init_chip(chip, 1); 376 377 /* 378 * Playback (for 44.1K/48K, 2-channel, 16-bps) fails with 379 * 4 SDO lines due to legacy design limitation. Following 380 * is, from HD Audio Specification (Revision 1.0a), used to 381 * control striping of the stream across multiple SDO lines 382 * for sample rates <= 48K. 383 * 384 * { ((num_channels * bits_per_sample) / number of SDOs) >= 8 } 385 * 386 * Due to legacy design issue it is recommended that above 387 * ratio must be greater than 8. Since number of SDO lines is 388 * in powers of 2, next available ratio is 16 which can be 389 * used as a limiting factor here. 390 */ 391 if (of_device_is_compatible(np, "nvidia,tegra30-hda")) 392 chip->bus.core.sdo_limit = 16; 393 394 /* codec detection */ 395 if (!bus->codec_mask) { 396 dev_err(card->dev, "no codecs found!\n"); 397 return -ENODEV; 398 } 399 400 /* driver name */ 401 strncpy(card->driver, drv_name, sizeof(card->driver)); 402 /* shortname for card */ 403 sname = of_get_property(np, "nvidia,model", NULL); 404 if (!sname) 405 sname = drv_name; 406 if (strlen(sname) > sizeof(card->shortname)) 407 dev_info(card->dev, "truncating shortname for card\n"); 408 strncpy(card->shortname, sname, sizeof(card->shortname)); 409 410 /* longname for card */ 411 snprintf(card->longname, sizeof(card->longname), 412 "%s at 0x%lx irq %i", 413 card->shortname, bus->addr, bus->irq); 414 415 return 0; 416 } 417 418 /* 419 * constructor 420 */ 421 422 static void hda_tegra_probe_work(struct work_struct *work); 423 424 static int hda_tegra_create(struct snd_card *card, 425 unsigned int driver_caps, 426 struct hda_tegra *hda) 427 { 428 static const struct snd_device_ops ops = { 429 .dev_disconnect = hda_tegra_dev_disconnect, 430 .dev_free = hda_tegra_dev_free, 431 }; 432 struct azx *chip; 433 int err; 434 435 chip = &hda->chip; 436 437 mutex_init(&chip->open_mutex); 438 chip->card = card; 439 chip->ops = &hda_tegra_ops; 440 chip->driver_caps = driver_caps; 441 chip->driver_type = driver_caps & 0xff; 442 chip->dev_index = 0; 443 INIT_LIST_HEAD(&chip->pcm_list); 444 445 chip->codec_probe_mask = -1; 446 447 chip->single_cmd = false; 448 chip->snoop = true; 449 450 INIT_WORK(&hda->probe_work, hda_tegra_probe_work); 451 452 err = azx_bus_init(chip, NULL); 453 if (err < 0) 454 return err; 455 456 chip->bus.core.sync_write = 0; 457 chip->bus.core.needs_damn_long_delay = 1; 458 chip->bus.core.aligned_mmio = 1; 459 460 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 461 if (err < 0) { 462 dev_err(card->dev, "Error creating device\n"); 463 return err; 464 } 465 466 return 0; 467 } 468 469 static const struct of_device_id hda_tegra_match[] = { 470 { .compatible = "nvidia,tegra30-hda" }, 471 { .compatible = "nvidia,tegra194-hda" }, 472 {}, 473 }; 474 MODULE_DEVICE_TABLE(of, hda_tegra_match); 475 476 static int hda_tegra_probe(struct platform_device *pdev) 477 { 478 const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR | 479 AZX_DCAPS_PM_RUNTIME; 480 struct snd_card *card; 481 struct azx *chip; 482 struct hda_tegra *hda; 483 int err; 484 485 hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL); 486 if (!hda) 487 return -ENOMEM; 488 hda->dev = &pdev->dev; 489 chip = &hda->chip; 490 491 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, 492 THIS_MODULE, 0, &card); 493 if (err < 0) { 494 dev_err(&pdev->dev, "Error creating card!\n"); 495 return err; 496 } 497 498 err = hda_tegra_init_clk(hda); 499 if (err < 0) 500 goto out_free; 501 502 err = hda_tegra_create(card, driver_flags, hda); 503 if (err < 0) 504 goto out_free; 505 card->private_data = chip; 506 507 dev_set_drvdata(&pdev->dev, card); 508 509 pm_runtime_enable(hda->dev); 510 if (!azx_has_pm_runtime(chip)) 511 pm_runtime_forbid(hda->dev); 512 513 schedule_work(&hda->probe_work); 514 515 return 0; 516 517 out_free: 518 snd_card_free(card); 519 return err; 520 } 521 522 static void hda_tegra_probe_work(struct work_struct *work) 523 { 524 struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work); 525 struct azx *chip = &hda->chip; 526 struct platform_device *pdev = to_platform_device(hda->dev); 527 int err; 528 529 pm_runtime_get_sync(hda->dev); 530 err = hda_tegra_first_init(chip, pdev); 531 if (err < 0) 532 goto out_free; 533 534 /* create codec instances */ 535 err = azx_probe_codecs(chip, 8); 536 if (err < 0) 537 goto out_free; 538 539 err = azx_codec_configure(chip); 540 if (err < 0) 541 goto out_free; 542 543 err = snd_card_register(chip->card); 544 if (err < 0) 545 goto out_free; 546 547 chip->running = 1; 548 snd_hda_set_power_save(&chip->bus, power_save * 1000); 549 550 out_free: 551 pm_runtime_put(hda->dev); 552 return; /* no error return from async probe */ 553 } 554 555 static int hda_tegra_remove(struct platform_device *pdev) 556 { 557 int ret; 558 559 ret = snd_card_free(dev_get_drvdata(&pdev->dev)); 560 pm_runtime_disable(&pdev->dev); 561 562 return ret; 563 } 564 565 static void hda_tegra_shutdown(struct platform_device *pdev) 566 { 567 struct snd_card *card = dev_get_drvdata(&pdev->dev); 568 struct azx *chip; 569 570 if (!card) 571 return; 572 chip = card->private_data; 573 if (chip && chip->running) 574 azx_stop_chip(chip); 575 } 576 577 static struct platform_driver tegra_platform_hda = { 578 .driver = { 579 .name = "tegra-hda", 580 .pm = &hda_tegra_pm, 581 .of_match_table = hda_tegra_match, 582 }, 583 .probe = hda_tegra_probe, 584 .remove = hda_tegra_remove, 585 .shutdown = hda_tegra_shutdown, 586 }; 587 module_platform_driver(tegra_platform_hda); 588 589 MODULE_DESCRIPTION("Tegra HDA bus driver"); 590 MODULE_LICENSE("GPL v2"); 591