1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clocksource.h> 9 #include <linux/completion.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/moduleparam.h> 18 #include <linux/mutex.h> 19 #include <linux/of_device.h> 20 #include <linux/slab.h> 21 #include <linux/time.h> 22 #include <linux/string.h> 23 #include <linux/pm_runtime.h> 24 25 #include <sound/core.h> 26 #include <sound/initval.h> 27 28 #include <sound/hda_codec.h> 29 #include "hda_controller.h" 30 31 /* Defines for Nvidia Tegra HDA support */ 32 #define HDA_BAR0 0x8000 33 34 #define HDA_CFG_CMD 0x1004 35 #define HDA_CFG_BAR0 0x1010 36 37 #define HDA_ENABLE_IO_SPACE (1 << 0) 38 #define HDA_ENABLE_MEM_SPACE (1 << 1) 39 #define HDA_ENABLE_BUS_MASTER (1 << 2) 40 #define HDA_ENABLE_SERR (1 << 8) 41 #define HDA_DISABLE_INTR (1 << 10) 42 #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF 43 #define HDA_BAR0_FINAL_PROGRAM (1 << 14) 44 45 /* IPFS */ 46 #define HDA_IPFS_CONFIG 0x180 47 #define HDA_IPFS_EN_FPCI 0x1 48 49 #define HDA_IPFS_FPCI_BAR0 0x80 50 #define HDA_FPCI_BAR0_START 0x40 51 52 #define HDA_IPFS_INTR_MASK 0x188 53 #define HDA_IPFS_EN_INTR (1 << 16) 54 55 /* max number of SDs */ 56 #define NUM_CAPTURE_SD 1 57 #define NUM_PLAYBACK_SD 1 58 59 struct hda_tegra { 60 struct azx chip; 61 struct device *dev; 62 struct clk *hda_clk; 63 struct clk *hda2codec_2x_clk; 64 struct clk *hda2hdmi_clk; 65 void __iomem *regs; 66 struct work_struct probe_work; 67 }; 68 69 #ifdef CONFIG_PM 70 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 71 module_param(power_save, bint, 0644); 72 MODULE_PARM_DESC(power_save, 73 "Automatic power-saving timeout (in seconds, 0 = disable)."); 74 #else 75 #define power_save 0 76 #endif 77 78 /* 79 * DMA page allocation ops. 80 */ 81 static int dma_alloc_pages(struct hdac_bus *bus, int type, size_t size, 82 struct snd_dma_buffer *buf) 83 { 84 return snd_dma_alloc_pages(type, bus->dev, size, buf); 85 } 86 87 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf) 88 { 89 snd_dma_free_pages(buf); 90 } 91 92 /* 93 * Register access ops. Tegra HDA register access is DWORD only. 94 */ 95 static void hda_tegra_writel(u32 value, u32 __iomem *addr) 96 { 97 writel(value, addr); 98 } 99 100 static u32 hda_tegra_readl(u32 __iomem *addr) 101 { 102 return readl(addr); 103 } 104 105 static void hda_tegra_writew(u16 value, u16 __iomem *addr) 106 { 107 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 108 void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3); 109 u32 v; 110 111 v = readl(dword_addr); 112 v &= ~(0xffff << shift); 113 v |= value << shift; 114 writel(v, dword_addr); 115 } 116 117 static u16 hda_tegra_readw(u16 __iomem *addr) 118 { 119 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 120 void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3); 121 u32 v; 122 123 v = readl(dword_addr); 124 return (v >> shift) & 0xffff; 125 } 126 127 static void hda_tegra_writeb(u8 value, u8 __iomem *addr) 128 { 129 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 130 void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3); 131 u32 v; 132 133 v = readl(dword_addr); 134 v &= ~(0xff << shift); 135 v |= value << shift; 136 writel(v, dword_addr); 137 } 138 139 static u8 hda_tegra_readb(u8 __iomem *addr) 140 { 141 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 142 void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3); 143 u32 v; 144 145 v = readl(dword_addr); 146 return (v >> shift) & 0xff; 147 } 148 149 static const struct hdac_io_ops hda_tegra_io_ops = { 150 .reg_writel = hda_tegra_writel, 151 .reg_readl = hda_tegra_readl, 152 .reg_writew = hda_tegra_writew, 153 .reg_readw = hda_tegra_readw, 154 .reg_writeb = hda_tegra_writeb, 155 .reg_readb = hda_tegra_readb, 156 .dma_alloc_pages = dma_alloc_pages, 157 .dma_free_pages = dma_free_pages, 158 }; 159 160 static const struct hda_controller_ops hda_tegra_ops; /* nothing special */ 161 162 static void hda_tegra_init(struct hda_tegra *hda) 163 { 164 u32 v; 165 166 /* Enable PCI access */ 167 v = readl(hda->regs + HDA_IPFS_CONFIG); 168 v |= HDA_IPFS_EN_FPCI; 169 writel(v, hda->regs + HDA_IPFS_CONFIG); 170 171 /* Enable MEM/IO space and bus master */ 172 v = readl(hda->regs + HDA_CFG_CMD); 173 v &= ~HDA_DISABLE_INTR; 174 v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE | 175 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR; 176 writel(v, hda->regs + HDA_CFG_CMD); 177 178 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0); 179 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0); 180 writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0); 181 182 v = readl(hda->regs + HDA_IPFS_INTR_MASK); 183 v |= HDA_IPFS_EN_INTR; 184 writel(v, hda->regs + HDA_IPFS_INTR_MASK); 185 } 186 187 static int hda_tegra_enable_clocks(struct hda_tegra *data) 188 { 189 int rc; 190 191 rc = clk_prepare_enable(data->hda_clk); 192 if (rc) 193 return rc; 194 rc = clk_prepare_enable(data->hda2codec_2x_clk); 195 if (rc) 196 goto disable_hda; 197 rc = clk_prepare_enable(data->hda2hdmi_clk); 198 if (rc) 199 goto disable_codec_2x; 200 201 return 0; 202 203 disable_codec_2x: 204 clk_disable_unprepare(data->hda2codec_2x_clk); 205 disable_hda: 206 clk_disable_unprepare(data->hda_clk); 207 return rc; 208 } 209 210 static void hda_tegra_disable_clocks(struct hda_tegra *data) 211 { 212 clk_disable_unprepare(data->hda2hdmi_clk); 213 clk_disable_unprepare(data->hda2codec_2x_clk); 214 clk_disable_unprepare(data->hda_clk); 215 } 216 217 /* 218 * power management 219 */ 220 static int __maybe_unused hda_tegra_suspend(struct device *dev) 221 { 222 struct snd_card *card = dev_get_drvdata(dev); 223 int rc; 224 225 rc = pm_runtime_force_suspend(dev); 226 if (rc < 0) 227 return rc; 228 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 229 230 return 0; 231 } 232 233 static int __maybe_unused hda_tegra_resume(struct device *dev) 234 { 235 struct snd_card *card = dev_get_drvdata(dev); 236 int rc; 237 238 rc = pm_runtime_force_resume(dev); 239 if (rc < 0) 240 return rc; 241 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 242 243 return 0; 244 } 245 246 static int __maybe_unused hda_tegra_runtime_suspend(struct device *dev) 247 { 248 struct snd_card *card = dev_get_drvdata(dev); 249 struct azx *chip = card->private_data; 250 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 251 struct hdac_bus *bus = azx_bus(chip); 252 253 if (chip && chip->running) { 254 azx_stop_chip(chip); 255 synchronize_irq(bus->irq); 256 azx_enter_link_reset(chip); 257 } 258 hda_tegra_disable_clocks(hda); 259 260 return 0; 261 } 262 263 static int __maybe_unused hda_tegra_runtime_resume(struct device *dev) 264 { 265 struct snd_card *card = dev_get_drvdata(dev); 266 struct azx *chip = card->private_data; 267 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 268 int rc; 269 270 rc = hda_tegra_enable_clocks(hda); 271 if (rc != 0) 272 return rc; 273 if (chip && chip->running) { 274 hda_tegra_init(hda); 275 azx_init_chip(chip, 1); 276 } 277 278 return 0; 279 } 280 281 static const struct dev_pm_ops hda_tegra_pm = { 282 SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume) 283 SET_RUNTIME_PM_OPS(hda_tegra_runtime_suspend, 284 hda_tegra_runtime_resume, 285 NULL) 286 }; 287 288 static int hda_tegra_dev_disconnect(struct snd_device *device) 289 { 290 struct azx *chip = device->device_data; 291 292 chip->bus.shutdown = 1; 293 return 0; 294 } 295 296 /* 297 * destructor 298 */ 299 static int hda_tegra_dev_free(struct snd_device *device) 300 { 301 struct azx *chip = device->device_data; 302 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 303 304 cancel_work_sync(&hda->probe_work); 305 if (azx_bus(chip)->chip_init) { 306 azx_stop_all_streams(chip); 307 azx_stop_chip(chip); 308 } 309 310 azx_free_stream_pages(chip); 311 azx_free_streams(chip); 312 snd_hdac_bus_exit(azx_bus(chip)); 313 314 return 0; 315 } 316 317 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev) 318 { 319 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 320 struct hdac_bus *bus = azx_bus(chip); 321 struct device *dev = hda->dev; 322 struct resource *res; 323 324 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 325 hda->regs = devm_ioremap_resource(dev, res); 326 if (IS_ERR(hda->regs)) 327 return PTR_ERR(hda->regs); 328 329 bus->remap_addr = hda->regs + HDA_BAR0; 330 bus->addr = res->start + HDA_BAR0; 331 332 hda_tegra_init(hda); 333 334 return 0; 335 } 336 337 static int hda_tegra_init_clk(struct hda_tegra *hda) 338 { 339 struct device *dev = hda->dev; 340 341 hda->hda_clk = devm_clk_get(dev, "hda"); 342 if (IS_ERR(hda->hda_clk)) { 343 dev_err(dev, "failed to get hda clock\n"); 344 return PTR_ERR(hda->hda_clk); 345 } 346 hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x"); 347 if (IS_ERR(hda->hda2codec_2x_clk)) { 348 dev_err(dev, "failed to get hda2codec_2x clock\n"); 349 return PTR_ERR(hda->hda2codec_2x_clk); 350 } 351 hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi"); 352 if (IS_ERR(hda->hda2hdmi_clk)) { 353 dev_err(dev, "failed to get hda2hdmi clock\n"); 354 return PTR_ERR(hda->hda2hdmi_clk); 355 } 356 357 return 0; 358 } 359 360 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev) 361 { 362 struct hdac_bus *bus = azx_bus(chip); 363 struct snd_card *card = chip->card; 364 int err; 365 unsigned short gcap; 366 int irq_id = platform_get_irq(pdev, 0); 367 const char *sname, *drv_name = "tegra-hda"; 368 struct device_node *np = pdev->dev.of_node; 369 370 err = hda_tegra_init_chip(chip, pdev); 371 if (err) 372 return err; 373 374 err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt, 375 IRQF_SHARED, KBUILD_MODNAME, chip); 376 if (err) { 377 dev_err(chip->card->dev, 378 "unable to request IRQ %d, disabling device\n", 379 irq_id); 380 return err; 381 } 382 bus->irq = irq_id; 383 384 synchronize_irq(bus->irq); 385 386 gcap = azx_readw(chip, GCAP); 387 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 388 389 /* read number of streams from GCAP register instead of using 390 * hardcoded value 391 */ 392 chip->capture_streams = (gcap >> 8) & 0x0f; 393 chip->playback_streams = (gcap >> 12) & 0x0f; 394 if (!chip->playback_streams && !chip->capture_streams) { 395 /* gcap didn't give any info, switching to old method */ 396 chip->playback_streams = NUM_PLAYBACK_SD; 397 chip->capture_streams = NUM_CAPTURE_SD; 398 } 399 chip->capture_index_offset = 0; 400 chip->playback_index_offset = chip->capture_streams; 401 chip->num_streams = chip->playback_streams + chip->capture_streams; 402 403 /* initialize streams */ 404 err = azx_init_streams(chip); 405 if (err < 0) { 406 dev_err(card->dev, "failed to initialize streams: %d\n", err); 407 return err; 408 } 409 410 err = azx_alloc_stream_pages(chip); 411 if (err < 0) { 412 dev_err(card->dev, "failed to allocate stream pages: %d\n", 413 err); 414 return err; 415 } 416 417 /* initialize chip */ 418 azx_init_chip(chip, 1); 419 420 /* codec detection */ 421 if (!bus->codec_mask) { 422 dev_err(card->dev, "no codecs found!\n"); 423 return -ENODEV; 424 } 425 426 /* driver name */ 427 strncpy(card->driver, drv_name, sizeof(card->driver)); 428 /* shortname for card */ 429 sname = of_get_property(np, "nvidia,model", NULL); 430 if (!sname) 431 sname = drv_name; 432 if (strlen(sname) > sizeof(card->shortname)) 433 dev_info(card->dev, "truncating shortname for card\n"); 434 strncpy(card->shortname, sname, sizeof(card->shortname)); 435 436 /* longname for card */ 437 snprintf(card->longname, sizeof(card->longname), 438 "%s at 0x%lx irq %i", 439 card->shortname, bus->addr, bus->irq); 440 441 return 0; 442 } 443 444 /* 445 * constructor 446 */ 447 448 static void hda_tegra_probe_work(struct work_struct *work); 449 450 static int hda_tegra_create(struct snd_card *card, 451 unsigned int driver_caps, 452 struct hda_tegra *hda) 453 { 454 static struct snd_device_ops ops = { 455 .dev_disconnect = hda_tegra_dev_disconnect, 456 .dev_free = hda_tegra_dev_free, 457 }; 458 struct azx *chip; 459 int err; 460 461 chip = &hda->chip; 462 463 mutex_init(&chip->open_mutex); 464 chip->card = card; 465 chip->ops = &hda_tegra_ops; 466 chip->driver_caps = driver_caps; 467 chip->driver_type = driver_caps & 0xff; 468 chip->dev_index = 0; 469 INIT_LIST_HEAD(&chip->pcm_list); 470 471 chip->codec_probe_mask = -1; 472 473 chip->single_cmd = false; 474 chip->snoop = true; 475 476 INIT_WORK(&hda->probe_work, hda_tegra_probe_work); 477 478 err = azx_bus_init(chip, NULL, &hda_tegra_io_ops); 479 if (err < 0) 480 return err; 481 482 chip->bus.needs_damn_long_delay = 1; 483 484 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 485 if (err < 0) { 486 dev_err(card->dev, "Error creating device\n"); 487 return err; 488 } 489 490 return 0; 491 } 492 493 static const struct of_device_id hda_tegra_match[] = { 494 { .compatible = "nvidia,tegra30-hda" }, 495 {}, 496 }; 497 MODULE_DEVICE_TABLE(of, hda_tegra_match); 498 499 static int hda_tegra_probe(struct platform_device *pdev) 500 { 501 const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR | 502 AZX_DCAPS_PM_RUNTIME; 503 struct snd_card *card; 504 struct azx *chip; 505 struct hda_tegra *hda; 506 int err; 507 508 hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL); 509 if (!hda) 510 return -ENOMEM; 511 hda->dev = &pdev->dev; 512 chip = &hda->chip; 513 514 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, 515 THIS_MODULE, 0, &card); 516 if (err < 0) { 517 dev_err(&pdev->dev, "Error creating card!\n"); 518 return err; 519 } 520 521 err = hda_tegra_init_clk(hda); 522 if (err < 0) 523 goto out_free; 524 525 err = hda_tegra_create(card, driver_flags, hda); 526 if (err < 0) 527 goto out_free; 528 card->private_data = chip; 529 530 dev_set_drvdata(&pdev->dev, card); 531 532 pm_runtime_enable(hda->dev); 533 if (!azx_has_pm_runtime(chip)) 534 pm_runtime_forbid(hda->dev); 535 536 schedule_work(&hda->probe_work); 537 538 return 0; 539 540 out_free: 541 snd_card_free(card); 542 return err; 543 } 544 545 static void hda_tegra_probe_work(struct work_struct *work) 546 { 547 struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work); 548 struct azx *chip = &hda->chip; 549 struct platform_device *pdev = to_platform_device(hda->dev); 550 int err; 551 552 pm_runtime_get_sync(hda->dev); 553 err = hda_tegra_first_init(chip, pdev); 554 if (err < 0) 555 goto out_free; 556 557 /* create codec instances */ 558 err = azx_probe_codecs(chip, 8); 559 if (err < 0) 560 goto out_free; 561 562 err = azx_codec_configure(chip); 563 if (err < 0) 564 goto out_free; 565 566 err = snd_card_register(chip->card); 567 if (err < 0) 568 goto out_free; 569 570 chip->running = 1; 571 snd_hda_set_power_save(&chip->bus, power_save * 1000); 572 573 out_free: 574 pm_runtime_put(hda->dev); 575 return; /* no error return from async probe */ 576 } 577 578 static int hda_tegra_remove(struct platform_device *pdev) 579 { 580 int ret; 581 582 ret = snd_card_free(dev_get_drvdata(&pdev->dev)); 583 pm_runtime_disable(&pdev->dev); 584 585 return ret; 586 } 587 588 static void hda_tegra_shutdown(struct platform_device *pdev) 589 { 590 struct snd_card *card = dev_get_drvdata(&pdev->dev); 591 struct azx *chip; 592 593 if (!card) 594 return; 595 chip = card->private_data; 596 if (chip && chip->running) 597 azx_stop_chip(chip); 598 } 599 600 static struct platform_driver tegra_platform_hda = { 601 .driver = { 602 .name = "tegra-hda", 603 .pm = &hda_tegra_pm, 604 .of_match_table = hda_tegra_match, 605 }, 606 .probe = hda_tegra_probe, 607 .remove = hda_tegra_remove, 608 .shutdown = hda_tegra_shutdown, 609 }; 610 module_platform_driver(tegra_platform_hda); 611 612 MODULE_DESCRIPTION("Tegra HDA bus driver"); 613 MODULE_LICENSE("GPL v2"); 614