1 /* 2 * 3 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 * 17 */ 18 19 #include <linux/clk.h> 20 #include <linux/clocksource.h> 21 #include <linux/completion.h> 22 #include <linux/delay.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/init.h> 25 #include <linux/interrupt.h> 26 #include <linux/io.h> 27 #include <linux/kernel.h> 28 #include <linux/module.h> 29 #include <linux/moduleparam.h> 30 #include <linux/mutex.h> 31 #include <linux/of_device.h> 32 #include <linux/slab.h> 33 #include <linux/time.h> 34 #include <linux/string.h> 35 36 #include <sound/core.h> 37 #include <sound/initval.h> 38 39 #include <sound/hda_codec.h> 40 #include "hda_controller.h" 41 42 /* Defines for Nvidia Tegra HDA support */ 43 #define HDA_BAR0 0x8000 44 45 #define HDA_CFG_CMD 0x1004 46 #define HDA_CFG_BAR0 0x1010 47 48 #define HDA_ENABLE_IO_SPACE (1 << 0) 49 #define HDA_ENABLE_MEM_SPACE (1 << 1) 50 #define HDA_ENABLE_BUS_MASTER (1 << 2) 51 #define HDA_ENABLE_SERR (1 << 8) 52 #define HDA_DISABLE_INTR (1 << 10) 53 #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF 54 #define HDA_BAR0_FINAL_PROGRAM (1 << 14) 55 56 /* IPFS */ 57 #define HDA_IPFS_CONFIG 0x180 58 #define HDA_IPFS_EN_FPCI 0x1 59 60 #define HDA_IPFS_FPCI_BAR0 0x80 61 #define HDA_FPCI_BAR0_START 0x40 62 63 #define HDA_IPFS_INTR_MASK 0x188 64 #define HDA_IPFS_EN_INTR (1 << 16) 65 66 /* max number of SDs */ 67 #define NUM_CAPTURE_SD 1 68 #define NUM_PLAYBACK_SD 1 69 70 struct hda_tegra { 71 struct azx chip; 72 struct device *dev; 73 struct clk *hda_clk; 74 struct clk *hda2codec_2x_clk; 75 struct clk *hda2hdmi_clk; 76 void __iomem *regs; 77 struct work_struct probe_work; 78 }; 79 80 #ifdef CONFIG_PM 81 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 82 module_param(power_save, bint, 0644); 83 MODULE_PARM_DESC(power_save, 84 "Automatic power-saving timeout (in seconds, 0 = disable)."); 85 #else 86 #define power_save 0 87 #endif 88 89 /* 90 * DMA page allocation ops. 91 */ 92 static int dma_alloc_pages(struct hdac_bus *bus, int type, size_t size, 93 struct snd_dma_buffer *buf) 94 { 95 return snd_dma_alloc_pages(type, bus->dev, size, buf); 96 } 97 98 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf) 99 { 100 snd_dma_free_pages(buf); 101 } 102 103 /* 104 * Register access ops. Tegra HDA register access is DWORD only. 105 */ 106 static void hda_tegra_writel(u32 value, u32 __iomem *addr) 107 { 108 writel(value, addr); 109 } 110 111 static u32 hda_tegra_readl(u32 __iomem *addr) 112 { 113 return readl(addr); 114 } 115 116 static void hda_tegra_writew(u16 value, u16 __iomem *addr) 117 { 118 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 119 void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3); 120 u32 v; 121 122 v = readl(dword_addr); 123 v &= ~(0xffff << shift); 124 v |= value << shift; 125 writel(v, dword_addr); 126 } 127 128 static u16 hda_tegra_readw(u16 __iomem *addr) 129 { 130 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 131 void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3); 132 u32 v; 133 134 v = readl(dword_addr); 135 return (v >> shift) & 0xffff; 136 } 137 138 static void hda_tegra_writeb(u8 value, u8 __iomem *addr) 139 { 140 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 141 void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3); 142 u32 v; 143 144 v = readl(dword_addr); 145 v &= ~(0xff << shift); 146 v |= value << shift; 147 writel(v, dword_addr); 148 } 149 150 static u8 hda_tegra_readb(u8 __iomem *addr) 151 { 152 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 153 void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3); 154 u32 v; 155 156 v = readl(dword_addr); 157 return (v >> shift) & 0xff; 158 } 159 160 static const struct hdac_io_ops hda_tegra_io_ops = { 161 .reg_writel = hda_tegra_writel, 162 .reg_readl = hda_tegra_readl, 163 .reg_writew = hda_tegra_writew, 164 .reg_readw = hda_tegra_readw, 165 .reg_writeb = hda_tegra_writeb, 166 .reg_readb = hda_tegra_readb, 167 .dma_alloc_pages = dma_alloc_pages, 168 .dma_free_pages = dma_free_pages, 169 }; 170 171 static const struct hda_controller_ops hda_tegra_ops; /* nothing special */ 172 173 static void hda_tegra_init(struct hda_tegra *hda) 174 { 175 u32 v; 176 177 /* Enable PCI access */ 178 v = readl(hda->regs + HDA_IPFS_CONFIG); 179 v |= HDA_IPFS_EN_FPCI; 180 writel(v, hda->regs + HDA_IPFS_CONFIG); 181 182 /* Enable MEM/IO space and bus master */ 183 v = readl(hda->regs + HDA_CFG_CMD); 184 v &= ~HDA_DISABLE_INTR; 185 v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE | 186 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR; 187 writel(v, hda->regs + HDA_CFG_CMD); 188 189 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0); 190 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0); 191 writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0); 192 193 v = readl(hda->regs + HDA_IPFS_INTR_MASK); 194 v |= HDA_IPFS_EN_INTR; 195 writel(v, hda->regs + HDA_IPFS_INTR_MASK); 196 } 197 198 static int hda_tegra_enable_clocks(struct hda_tegra *data) 199 { 200 int rc; 201 202 rc = clk_prepare_enable(data->hda_clk); 203 if (rc) 204 return rc; 205 rc = clk_prepare_enable(data->hda2codec_2x_clk); 206 if (rc) 207 goto disable_hda; 208 rc = clk_prepare_enable(data->hda2hdmi_clk); 209 if (rc) 210 goto disable_codec_2x; 211 212 return 0; 213 214 disable_codec_2x: 215 clk_disable_unprepare(data->hda2codec_2x_clk); 216 disable_hda: 217 clk_disable_unprepare(data->hda_clk); 218 return rc; 219 } 220 221 #ifdef CONFIG_PM_SLEEP 222 static void hda_tegra_disable_clocks(struct hda_tegra *data) 223 { 224 clk_disable_unprepare(data->hda2hdmi_clk); 225 clk_disable_unprepare(data->hda2codec_2x_clk); 226 clk_disable_unprepare(data->hda_clk); 227 } 228 229 /* 230 * power management 231 */ 232 static int hda_tegra_suspend(struct device *dev) 233 { 234 struct snd_card *card = dev_get_drvdata(dev); 235 struct azx *chip = card->private_data; 236 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 237 struct hdac_bus *bus = azx_bus(chip); 238 239 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 240 241 azx_stop_chip(chip); 242 synchronize_irq(bus->irq); 243 azx_enter_link_reset(chip); 244 hda_tegra_disable_clocks(hda); 245 246 return 0; 247 } 248 249 static int hda_tegra_resume(struct device *dev) 250 { 251 struct snd_card *card = dev_get_drvdata(dev); 252 struct azx *chip = card->private_data; 253 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 254 255 hda_tegra_enable_clocks(hda); 256 257 hda_tegra_init(hda); 258 259 azx_init_chip(chip, 1); 260 261 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 262 263 return 0; 264 } 265 #endif /* CONFIG_PM_SLEEP */ 266 267 static const struct dev_pm_ops hda_tegra_pm = { 268 SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume) 269 }; 270 271 static int hda_tegra_dev_disconnect(struct snd_device *device) 272 { 273 struct azx *chip = device->device_data; 274 275 chip->bus.shutdown = 1; 276 return 0; 277 } 278 279 /* 280 * destructor 281 */ 282 static int hda_tegra_dev_free(struct snd_device *device) 283 { 284 struct azx *chip = device->device_data; 285 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 286 287 cancel_work_sync(&hda->probe_work); 288 if (azx_bus(chip)->chip_init) { 289 azx_stop_all_streams(chip); 290 azx_stop_chip(chip); 291 } 292 293 azx_free_stream_pages(chip); 294 azx_free_streams(chip); 295 snd_hdac_bus_exit(azx_bus(chip)); 296 297 return 0; 298 } 299 300 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev) 301 { 302 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 303 struct hdac_bus *bus = azx_bus(chip); 304 struct device *dev = hda->dev; 305 struct resource *res; 306 int err; 307 308 hda->hda_clk = devm_clk_get(dev, "hda"); 309 if (IS_ERR(hda->hda_clk)) { 310 dev_err(dev, "failed to get hda clock\n"); 311 return PTR_ERR(hda->hda_clk); 312 } 313 hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x"); 314 if (IS_ERR(hda->hda2codec_2x_clk)) { 315 dev_err(dev, "failed to get hda2codec_2x clock\n"); 316 return PTR_ERR(hda->hda2codec_2x_clk); 317 } 318 hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi"); 319 if (IS_ERR(hda->hda2hdmi_clk)) { 320 dev_err(dev, "failed to get hda2hdmi clock\n"); 321 return PTR_ERR(hda->hda2hdmi_clk); 322 } 323 324 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 325 hda->regs = devm_ioremap_resource(dev, res); 326 if (IS_ERR(hda->regs)) 327 return PTR_ERR(hda->regs); 328 329 bus->remap_addr = hda->regs + HDA_BAR0; 330 bus->addr = res->start + HDA_BAR0; 331 332 err = hda_tegra_enable_clocks(hda); 333 if (err) { 334 dev_err(dev, "failed to get enable clocks\n"); 335 return err; 336 } 337 338 hda_tegra_init(hda); 339 340 return 0; 341 } 342 343 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev) 344 { 345 struct hdac_bus *bus = azx_bus(chip); 346 struct snd_card *card = chip->card; 347 int err; 348 unsigned short gcap; 349 int irq_id = platform_get_irq(pdev, 0); 350 const char *sname; 351 struct device_node *root; 352 353 err = hda_tegra_init_chip(chip, pdev); 354 if (err) 355 return err; 356 357 err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt, 358 IRQF_SHARED, KBUILD_MODNAME, chip); 359 if (err) { 360 dev_err(chip->card->dev, 361 "unable to request IRQ %d, disabling device\n", 362 irq_id); 363 return err; 364 } 365 bus->irq = irq_id; 366 367 synchronize_irq(bus->irq); 368 369 gcap = azx_readw(chip, GCAP); 370 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 371 372 /* read number of streams from GCAP register instead of using 373 * hardcoded value 374 */ 375 chip->capture_streams = (gcap >> 8) & 0x0f; 376 chip->playback_streams = (gcap >> 12) & 0x0f; 377 if (!chip->playback_streams && !chip->capture_streams) { 378 /* gcap didn't give any info, switching to old method */ 379 chip->playback_streams = NUM_PLAYBACK_SD; 380 chip->capture_streams = NUM_CAPTURE_SD; 381 } 382 chip->capture_index_offset = 0; 383 chip->playback_index_offset = chip->capture_streams; 384 chip->num_streams = chip->playback_streams + chip->capture_streams; 385 386 /* initialize streams */ 387 err = azx_init_streams(chip); 388 if (err < 0) { 389 dev_err(card->dev, "failed to initialize streams: %d\n", err); 390 return err; 391 } 392 393 err = azx_alloc_stream_pages(chip); 394 if (err < 0) { 395 dev_err(card->dev, "failed to allocate stream pages: %d\n", 396 err); 397 return err; 398 } 399 400 /* initialize chip */ 401 azx_init_chip(chip, 1); 402 403 /* codec detection */ 404 if (!bus->codec_mask) { 405 dev_err(card->dev, "no codecs found!\n"); 406 return -ENODEV; 407 } 408 409 /* driver name */ 410 strcpy(card->driver, "tegra-hda"); 411 412 root = of_find_node_by_path("/"); 413 sname = of_get_property(root, "compatible", NULL); 414 of_node_put(root); 415 if (!sname) { 416 dev_err(card->dev, 417 "failed to get compatible property from root node\n"); 418 return -ENODEV; 419 } 420 /* shortname for card */ 421 if (strlen(sname) > sizeof(card->shortname)) 422 dev_info(card->dev, "truncating shortname for card\n"); 423 strncpy(card->shortname, sname, sizeof(card->shortname)); 424 425 /* longname for card */ 426 snprintf(card->longname, sizeof(card->longname), 427 "%s at 0x%lx irq %i", 428 card->shortname, bus->addr, bus->irq); 429 430 return 0; 431 } 432 433 /* 434 * constructor 435 */ 436 437 static void hda_tegra_probe_work(struct work_struct *work); 438 439 static int hda_tegra_create(struct snd_card *card, 440 unsigned int driver_caps, 441 struct hda_tegra *hda) 442 { 443 static struct snd_device_ops ops = { 444 .dev_disconnect = hda_tegra_dev_disconnect, 445 .dev_free = hda_tegra_dev_free, 446 }; 447 struct azx *chip; 448 int err; 449 450 chip = &hda->chip; 451 452 mutex_init(&chip->open_mutex); 453 chip->card = card; 454 chip->ops = &hda_tegra_ops; 455 chip->driver_caps = driver_caps; 456 chip->driver_type = driver_caps & 0xff; 457 chip->dev_index = 0; 458 INIT_LIST_HEAD(&chip->pcm_list); 459 460 chip->codec_probe_mask = -1; 461 462 chip->single_cmd = false; 463 chip->snoop = true; 464 465 INIT_WORK(&hda->probe_work, hda_tegra_probe_work); 466 467 err = azx_bus_init(chip, NULL, &hda_tegra_io_ops); 468 if (err < 0) 469 return err; 470 471 chip->bus.needs_damn_long_delay = 1; 472 473 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 474 if (err < 0) { 475 dev_err(card->dev, "Error creating device\n"); 476 return err; 477 } 478 479 return 0; 480 } 481 482 static const struct of_device_id hda_tegra_match[] = { 483 { .compatible = "nvidia,tegra30-hda" }, 484 {}, 485 }; 486 MODULE_DEVICE_TABLE(of, hda_tegra_match); 487 488 static int hda_tegra_probe(struct platform_device *pdev) 489 { 490 const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR; 491 struct snd_card *card; 492 struct azx *chip; 493 struct hda_tegra *hda; 494 int err; 495 496 hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL); 497 if (!hda) 498 return -ENOMEM; 499 hda->dev = &pdev->dev; 500 chip = &hda->chip; 501 502 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, 503 THIS_MODULE, 0, &card); 504 if (err < 0) { 505 dev_err(&pdev->dev, "Error creating card!\n"); 506 return err; 507 } 508 509 err = hda_tegra_create(card, driver_flags, hda); 510 if (err < 0) 511 goto out_free; 512 card->private_data = chip; 513 514 dev_set_drvdata(&pdev->dev, card); 515 schedule_work(&hda->probe_work); 516 517 return 0; 518 519 out_free: 520 snd_card_free(card); 521 return err; 522 } 523 524 static void hda_tegra_probe_work(struct work_struct *work) 525 { 526 struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work); 527 struct azx *chip = &hda->chip; 528 struct platform_device *pdev = to_platform_device(hda->dev); 529 int err; 530 531 err = hda_tegra_first_init(chip, pdev); 532 if (err < 0) 533 goto out_free; 534 535 /* create codec instances */ 536 err = azx_probe_codecs(chip, 8); 537 if (err < 0) 538 goto out_free; 539 540 err = azx_codec_configure(chip); 541 if (err < 0) 542 goto out_free; 543 544 err = snd_card_register(chip->card); 545 if (err < 0) 546 goto out_free; 547 548 chip->running = 1; 549 snd_hda_set_power_save(&chip->bus, power_save * 1000); 550 551 out_free: 552 return; /* no error return from async probe */ 553 } 554 555 static int hda_tegra_remove(struct platform_device *pdev) 556 { 557 return snd_card_free(dev_get_drvdata(&pdev->dev)); 558 } 559 560 static void hda_tegra_shutdown(struct platform_device *pdev) 561 { 562 struct snd_card *card = dev_get_drvdata(&pdev->dev); 563 struct azx *chip; 564 565 if (!card) 566 return; 567 chip = card->private_data; 568 if (chip && chip->running) 569 azx_stop_chip(chip); 570 } 571 572 static struct platform_driver tegra_platform_hda = { 573 .driver = { 574 .name = "tegra-hda", 575 .pm = &hda_tegra_pm, 576 .of_match_table = hda_tegra_match, 577 }, 578 .probe = hda_tegra_probe, 579 .remove = hda_tegra_remove, 580 .shutdown = hda_tegra_shutdown, 581 }; 582 module_platform_driver(tegra_platform_hda); 583 584 MODULE_DESCRIPTION("Tegra HDA bus driver"); 585 MODULE_LICENSE("GPL v2"); 586