1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clocksource.h> 9 #include <linux/completion.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/moduleparam.h> 18 #include <linux/mutex.h> 19 #include <linux/of_device.h> 20 #include <linux/slab.h> 21 #include <linux/time.h> 22 #include <linux/string.h> 23 #include <linux/pm_runtime.h> 24 25 #include <sound/core.h> 26 #include <sound/initval.h> 27 28 #include <sound/hda_codec.h> 29 #include "hda_controller.h" 30 31 /* Defines for Nvidia Tegra HDA support */ 32 #define HDA_BAR0 0x8000 33 34 #define HDA_CFG_CMD 0x1004 35 #define HDA_CFG_BAR0 0x1010 36 37 #define HDA_ENABLE_IO_SPACE (1 << 0) 38 #define HDA_ENABLE_MEM_SPACE (1 << 1) 39 #define HDA_ENABLE_BUS_MASTER (1 << 2) 40 #define HDA_ENABLE_SERR (1 << 8) 41 #define HDA_DISABLE_INTR (1 << 10) 42 #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF 43 #define HDA_BAR0_FINAL_PROGRAM (1 << 14) 44 45 /* IPFS */ 46 #define HDA_IPFS_CONFIG 0x180 47 #define HDA_IPFS_EN_FPCI 0x1 48 49 #define HDA_IPFS_FPCI_BAR0 0x80 50 #define HDA_FPCI_BAR0_START 0x40 51 52 #define HDA_IPFS_INTR_MASK 0x188 53 #define HDA_IPFS_EN_INTR (1 << 16) 54 55 /* FPCI */ 56 #define FPCI_DBG_CFG_2 0x10F4 57 #define FPCI_GCAP_NSDO_SHIFT 18 58 #define FPCI_GCAP_NSDO_MASK (0x3 << FPCI_GCAP_NSDO_SHIFT) 59 60 /* max number of SDs */ 61 #define NUM_CAPTURE_SD 1 62 #define NUM_PLAYBACK_SD 1 63 64 /* 65 * Tegra194 does not reflect correct number of SDO lines. Below macro 66 * is used to update the GCAP register to workaround the issue. 67 */ 68 #define TEGRA194_NUM_SDO_LINES 4 69 70 struct hda_tegra { 71 struct azx chip; 72 struct device *dev; 73 struct clk *hda_clk; 74 struct clk *hda2codec_2x_clk; 75 struct clk *hda2hdmi_clk; 76 void __iomem *regs; 77 struct work_struct probe_work; 78 }; 79 80 #ifdef CONFIG_PM 81 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 82 module_param(power_save, bint, 0644); 83 MODULE_PARM_DESC(power_save, 84 "Automatic power-saving timeout (in seconds, 0 = disable)."); 85 #else 86 #define power_save 0 87 #endif 88 89 static const struct hda_controller_ops hda_tegra_ops; /* nothing special */ 90 91 static void hda_tegra_init(struct hda_tegra *hda) 92 { 93 u32 v; 94 95 /* Enable PCI access */ 96 v = readl(hda->regs + HDA_IPFS_CONFIG); 97 v |= HDA_IPFS_EN_FPCI; 98 writel(v, hda->regs + HDA_IPFS_CONFIG); 99 100 /* Enable MEM/IO space and bus master */ 101 v = readl(hda->regs + HDA_CFG_CMD); 102 v &= ~HDA_DISABLE_INTR; 103 v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE | 104 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR; 105 writel(v, hda->regs + HDA_CFG_CMD); 106 107 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0); 108 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0); 109 writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0); 110 111 v = readl(hda->regs + HDA_IPFS_INTR_MASK); 112 v |= HDA_IPFS_EN_INTR; 113 writel(v, hda->regs + HDA_IPFS_INTR_MASK); 114 } 115 116 static int hda_tegra_enable_clocks(struct hda_tegra *data) 117 { 118 int rc; 119 120 rc = clk_prepare_enable(data->hda_clk); 121 if (rc) 122 return rc; 123 rc = clk_prepare_enable(data->hda2codec_2x_clk); 124 if (rc) 125 goto disable_hda; 126 rc = clk_prepare_enable(data->hda2hdmi_clk); 127 if (rc) 128 goto disable_codec_2x; 129 130 return 0; 131 132 disable_codec_2x: 133 clk_disable_unprepare(data->hda2codec_2x_clk); 134 disable_hda: 135 clk_disable_unprepare(data->hda_clk); 136 return rc; 137 } 138 139 static void hda_tegra_disable_clocks(struct hda_tegra *data) 140 { 141 clk_disable_unprepare(data->hda2hdmi_clk); 142 clk_disable_unprepare(data->hda2codec_2x_clk); 143 clk_disable_unprepare(data->hda_clk); 144 } 145 146 /* 147 * power management 148 */ 149 static int __maybe_unused hda_tegra_suspend(struct device *dev) 150 { 151 struct snd_card *card = dev_get_drvdata(dev); 152 int rc; 153 154 rc = pm_runtime_force_suspend(dev); 155 if (rc < 0) 156 return rc; 157 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 158 159 return 0; 160 } 161 162 static int __maybe_unused hda_tegra_resume(struct device *dev) 163 { 164 struct snd_card *card = dev_get_drvdata(dev); 165 int rc; 166 167 rc = pm_runtime_force_resume(dev); 168 if (rc < 0) 169 return rc; 170 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 171 172 return 0; 173 } 174 175 static int __maybe_unused hda_tegra_runtime_suspend(struct device *dev) 176 { 177 struct snd_card *card = dev_get_drvdata(dev); 178 struct azx *chip = card->private_data; 179 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 180 181 if (chip && chip->running) { 182 azx_stop_chip(chip); 183 azx_enter_link_reset(chip); 184 } 185 hda_tegra_disable_clocks(hda); 186 187 return 0; 188 } 189 190 static int __maybe_unused hda_tegra_runtime_resume(struct device *dev) 191 { 192 struct snd_card *card = dev_get_drvdata(dev); 193 struct azx *chip = card->private_data; 194 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 195 int rc; 196 197 rc = hda_tegra_enable_clocks(hda); 198 if (rc != 0) 199 return rc; 200 if (chip && chip->running) { 201 hda_tegra_init(hda); 202 azx_init_chip(chip, 1); 203 } 204 205 return 0; 206 } 207 208 static const struct dev_pm_ops hda_tegra_pm = { 209 SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume) 210 SET_RUNTIME_PM_OPS(hda_tegra_runtime_suspend, 211 hda_tegra_runtime_resume, 212 NULL) 213 }; 214 215 static int hda_tegra_dev_disconnect(struct snd_device *device) 216 { 217 struct azx *chip = device->device_data; 218 219 chip->bus.shutdown = 1; 220 return 0; 221 } 222 223 /* 224 * destructor 225 */ 226 static int hda_tegra_dev_free(struct snd_device *device) 227 { 228 struct azx *chip = device->device_data; 229 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 230 231 cancel_work_sync(&hda->probe_work); 232 if (azx_bus(chip)->chip_init) { 233 azx_stop_all_streams(chip); 234 azx_stop_chip(chip); 235 } 236 237 azx_free_stream_pages(chip); 238 azx_free_streams(chip); 239 snd_hdac_bus_exit(azx_bus(chip)); 240 241 return 0; 242 } 243 244 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev) 245 { 246 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 247 struct hdac_bus *bus = azx_bus(chip); 248 struct device *dev = hda->dev; 249 struct resource *res; 250 251 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 252 hda->regs = devm_ioremap_resource(dev, res); 253 if (IS_ERR(hda->regs)) 254 return PTR_ERR(hda->regs); 255 256 bus->remap_addr = hda->regs + HDA_BAR0; 257 bus->addr = res->start + HDA_BAR0; 258 259 hda_tegra_init(hda); 260 261 return 0; 262 } 263 264 static int hda_tegra_init_clk(struct hda_tegra *hda) 265 { 266 struct device *dev = hda->dev; 267 268 hda->hda_clk = devm_clk_get(dev, "hda"); 269 if (IS_ERR(hda->hda_clk)) { 270 dev_err(dev, "failed to get hda clock\n"); 271 return PTR_ERR(hda->hda_clk); 272 } 273 hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x"); 274 if (IS_ERR(hda->hda2codec_2x_clk)) { 275 dev_err(dev, "failed to get hda2codec_2x clock\n"); 276 return PTR_ERR(hda->hda2codec_2x_clk); 277 } 278 hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi"); 279 if (IS_ERR(hda->hda2hdmi_clk)) { 280 dev_err(dev, "failed to get hda2hdmi clock\n"); 281 return PTR_ERR(hda->hda2hdmi_clk); 282 } 283 284 return 0; 285 } 286 287 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev) 288 { 289 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 290 struct hdac_bus *bus = azx_bus(chip); 291 struct snd_card *card = chip->card; 292 int err; 293 unsigned short gcap; 294 int irq_id = platform_get_irq(pdev, 0); 295 const char *sname, *drv_name = "tegra-hda"; 296 struct device_node *np = pdev->dev.of_node; 297 298 err = hda_tegra_init_chip(chip, pdev); 299 if (err) 300 return err; 301 302 err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt, 303 IRQF_SHARED, KBUILD_MODNAME, chip); 304 if (err) { 305 dev_err(chip->card->dev, 306 "unable to request IRQ %d, disabling device\n", 307 irq_id); 308 return err; 309 } 310 bus->irq = irq_id; 311 card->sync_irq = bus->irq; 312 313 /* 314 * Tegra194 has 4 SDO lines and the STRIPE can be used to 315 * indicate how many of the SDO lines the stream should be 316 * striped. But GCAP register does not reflect the true 317 * capability of HW. Below workaround helps to fix this. 318 * 319 * GCAP_NSDO is bits 19:18 in T_AZA_DBG_CFG_2, 320 * 0 for 1 SDO, 1 for 2 SDO, 2 for 4 SDO lines. 321 */ 322 if (of_device_is_compatible(np, "nvidia,tegra194-hda")) { 323 u32 val; 324 325 dev_info(card->dev, "Override SDO lines to %u\n", 326 TEGRA194_NUM_SDO_LINES); 327 328 val = readl(hda->regs + FPCI_DBG_CFG_2) & ~FPCI_GCAP_NSDO_MASK; 329 val |= (TEGRA194_NUM_SDO_LINES >> 1) << FPCI_GCAP_NSDO_SHIFT; 330 writel(val, hda->regs + FPCI_DBG_CFG_2); 331 } 332 333 gcap = azx_readw(chip, GCAP); 334 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 335 336 /* read number of streams from GCAP register instead of using 337 * hardcoded value 338 */ 339 chip->capture_streams = (gcap >> 8) & 0x0f; 340 chip->playback_streams = (gcap >> 12) & 0x0f; 341 if (!chip->playback_streams && !chip->capture_streams) { 342 /* gcap didn't give any info, switching to old method */ 343 chip->playback_streams = NUM_PLAYBACK_SD; 344 chip->capture_streams = NUM_CAPTURE_SD; 345 } 346 chip->capture_index_offset = 0; 347 chip->playback_index_offset = chip->capture_streams; 348 chip->num_streams = chip->playback_streams + chip->capture_streams; 349 350 /* initialize streams */ 351 err = azx_init_streams(chip); 352 if (err < 0) { 353 dev_err(card->dev, "failed to initialize streams: %d\n", err); 354 return err; 355 } 356 357 err = azx_alloc_stream_pages(chip); 358 if (err < 0) { 359 dev_err(card->dev, "failed to allocate stream pages: %d\n", 360 err); 361 return err; 362 } 363 364 /* initialize chip */ 365 azx_init_chip(chip, 1); 366 367 /* 368 * Playback (for 44.1K/48K, 2-channel, 16-bps) fails with 369 * 4 SDO lines due to legacy design limitation. Following 370 * is, from HD Audio Specification (Revision 1.0a), used to 371 * control striping of the stream across multiple SDO lines 372 * for sample rates <= 48K. 373 * 374 * { ((num_channels * bits_per_sample) / number of SDOs) >= 8 } 375 * 376 * Due to legacy design issue it is recommended that above 377 * ratio must be greater than 8. Since number of SDO lines is 378 * in powers of 2, next available ratio is 16 which can be 379 * used as a limiting factor here. 380 */ 381 if (of_device_is_compatible(np, "nvidia,tegra194-hda")) 382 chip->bus.core.sdo_limit = 16; 383 384 /* codec detection */ 385 if (!bus->codec_mask) { 386 dev_err(card->dev, "no codecs found!\n"); 387 return -ENODEV; 388 } 389 390 /* driver name */ 391 strncpy(card->driver, drv_name, sizeof(card->driver)); 392 /* shortname for card */ 393 sname = of_get_property(np, "nvidia,model", NULL); 394 if (!sname) 395 sname = drv_name; 396 if (strlen(sname) > sizeof(card->shortname)) 397 dev_info(card->dev, "truncating shortname for card\n"); 398 strncpy(card->shortname, sname, sizeof(card->shortname)); 399 400 /* longname for card */ 401 snprintf(card->longname, sizeof(card->longname), 402 "%s at 0x%lx irq %i", 403 card->shortname, bus->addr, bus->irq); 404 405 return 0; 406 } 407 408 /* 409 * constructor 410 */ 411 412 static void hda_tegra_probe_work(struct work_struct *work); 413 414 static int hda_tegra_create(struct snd_card *card, 415 unsigned int driver_caps, 416 struct hda_tegra *hda) 417 { 418 static const struct snd_device_ops ops = { 419 .dev_disconnect = hda_tegra_dev_disconnect, 420 .dev_free = hda_tegra_dev_free, 421 }; 422 struct azx *chip; 423 int err; 424 425 chip = &hda->chip; 426 427 mutex_init(&chip->open_mutex); 428 chip->card = card; 429 chip->ops = &hda_tegra_ops; 430 chip->driver_caps = driver_caps; 431 chip->driver_type = driver_caps & 0xff; 432 chip->dev_index = 0; 433 INIT_LIST_HEAD(&chip->pcm_list); 434 435 chip->codec_probe_mask = -1; 436 437 chip->single_cmd = false; 438 chip->snoop = true; 439 440 INIT_WORK(&hda->probe_work, hda_tegra_probe_work); 441 442 err = azx_bus_init(chip, NULL); 443 if (err < 0) 444 return err; 445 446 chip->bus.core.needs_damn_long_delay = 1; 447 chip->bus.core.aligned_mmio = 1; 448 449 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 450 if (err < 0) { 451 dev_err(card->dev, "Error creating device\n"); 452 return err; 453 } 454 455 return 0; 456 } 457 458 static const struct of_device_id hda_tegra_match[] = { 459 { .compatible = "nvidia,tegra30-hda" }, 460 { .compatible = "nvidia,tegra194-hda" }, 461 {}, 462 }; 463 MODULE_DEVICE_TABLE(of, hda_tegra_match); 464 465 static int hda_tegra_probe(struct platform_device *pdev) 466 { 467 const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR | 468 AZX_DCAPS_PM_RUNTIME; 469 struct snd_card *card; 470 struct azx *chip; 471 struct hda_tegra *hda; 472 int err; 473 474 hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL); 475 if (!hda) 476 return -ENOMEM; 477 hda->dev = &pdev->dev; 478 chip = &hda->chip; 479 480 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, 481 THIS_MODULE, 0, &card); 482 if (err < 0) { 483 dev_err(&pdev->dev, "Error creating card!\n"); 484 return err; 485 } 486 487 err = hda_tegra_init_clk(hda); 488 if (err < 0) 489 goto out_free; 490 491 err = hda_tegra_create(card, driver_flags, hda); 492 if (err < 0) 493 goto out_free; 494 card->private_data = chip; 495 496 dev_set_drvdata(&pdev->dev, card); 497 498 pm_runtime_enable(hda->dev); 499 if (!azx_has_pm_runtime(chip)) 500 pm_runtime_forbid(hda->dev); 501 502 schedule_work(&hda->probe_work); 503 504 return 0; 505 506 out_free: 507 snd_card_free(card); 508 return err; 509 } 510 511 static void hda_tegra_probe_work(struct work_struct *work) 512 { 513 struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work); 514 struct azx *chip = &hda->chip; 515 struct platform_device *pdev = to_platform_device(hda->dev); 516 int err; 517 518 pm_runtime_get_sync(hda->dev); 519 err = hda_tegra_first_init(chip, pdev); 520 if (err < 0) 521 goto out_free; 522 523 /* create codec instances */ 524 err = azx_probe_codecs(chip, 8); 525 if (err < 0) 526 goto out_free; 527 528 err = azx_codec_configure(chip); 529 if (err < 0) 530 goto out_free; 531 532 err = snd_card_register(chip->card); 533 if (err < 0) 534 goto out_free; 535 536 chip->running = 1; 537 snd_hda_set_power_save(&chip->bus, power_save * 1000); 538 539 out_free: 540 pm_runtime_put(hda->dev); 541 return; /* no error return from async probe */ 542 } 543 544 static int hda_tegra_remove(struct platform_device *pdev) 545 { 546 int ret; 547 548 ret = snd_card_free(dev_get_drvdata(&pdev->dev)); 549 pm_runtime_disable(&pdev->dev); 550 551 return ret; 552 } 553 554 static void hda_tegra_shutdown(struct platform_device *pdev) 555 { 556 struct snd_card *card = dev_get_drvdata(&pdev->dev); 557 struct azx *chip; 558 559 if (!card) 560 return; 561 chip = card->private_data; 562 if (chip && chip->running) 563 azx_stop_chip(chip); 564 } 565 566 static struct platform_driver tegra_platform_hda = { 567 .driver = { 568 .name = "tegra-hda", 569 .pm = &hda_tegra_pm, 570 .of_match_table = hda_tegra_match, 571 }, 572 .probe = hda_tegra_probe, 573 .remove = hda_tegra_remove, 574 .shutdown = hda_tegra_shutdown, 575 }; 576 module_platform_driver(tegra_platform_hda); 577 578 MODULE_DESCRIPTION("Tegra HDA bus driver"); 579 MODULE_LICENSE("GPL v2"); 580