1 /* 2 * 3 * hda_intel.c - Implementation of primary alsa driver code base 4 * for Intel HD Audio. 5 * 6 * Copyright(c) 2004 Intel Corporation. All rights reserved. 7 * 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the Free 13 * Software Foundation; either version 2 of the License, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 * 21 * You should have received a copy of the GNU General Public License along with 22 * this program; if not, write to the Free Software Foundation, Inc., 59 23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 24 * 25 * CONTACTS: 26 * 27 * Matt Jared matt.jared@intel.com 28 * Andy Kopp andy.kopp@intel.com 29 * Dan Kogan dan.d.kogan@intel.com 30 * 31 * CHANGES: 32 * 33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 34 * 35 */ 36 37 #include <linux/delay.h> 38 #include <linux/interrupt.h> 39 #include <linux/kernel.h> 40 #include <linux/module.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/moduleparam.h> 43 #include <linux/init.h> 44 #include <linux/slab.h> 45 #include <linux/pci.h> 46 #include <linux/mutex.h> 47 #include <linux/io.h> 48 #include <linux/pm_runtime.h> 49 #include <linux/clocksource.h> 50 #include <linux/time.h> 51 #include <linux/completion.h> 52 53 #ifdef CONFIG_X86 54 /* for snoop control */ 55 #include <asm/pgtable.h> 56 #include <asm/cacheflush.h> 57 #endif 58 #include <sound/core.h> 59 #include <sound/initval.h> 60 #include <sound/hdaudio.h> 61 #include <sound/hda_i915.h> 62 #include <linux/vgaarb.h> 63 #include <linux/vga_switcheroo.h> 64 #include <linux/firmware.h> 65 #include "hda_codec.h" 66 #include "hda_controller.h" 67 #include "hda_intel.h" 68 69 #define CREATE_TRACE_POINTS 70 #include "hda_intel_trace.h" 71 72 /* position fix mode */ 73 enum { 74 POS_FIX_AUTO, 75 POS_FIX_LPIB, 76 POS_FIX_POSBUF, 77 POS_FIX_VIACOMBO, 78 POS_FIX_COMBO, 79 }; 80 81 /* Defines for ATI HD Audio support in SB450 south bridge */ 82 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 83 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 84 85 /* Defines for Nvidia HDA support */ 86 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 87 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 88 #define NVIDIA_HDA_ISTRM_COH 0x4d 89 #define NVIDIA_HDA_OSTRM_COH 0x4c 90 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 91 92 /* Defines for Intel SCH HDA snoop control */ 93 #define INTEL_HDA_CGCTL 0x48 94 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) 95 #define INTEL_SCH_HDA_DEVC 0x78 96 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 97 98 /* Define IN stream 0 FIFO size offset in VIA controller */ 99 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 100 /* Define VIA HD Audio Device ID*/ 101 #define VIA_HDAC_DEVICE_ID 0x3288 102 103 /* max number of SDs */ 104 /* ICH, ATI and VIA have 4 playback and 4 capture */ 105 #define ICH6_NUM_CAPTURE 4 106 #define ICH6_NUM_PLAYBACK 4 107 108 /* ULI has 6 playback and 5 capture */ 109 #define ULI_NUM_CAPTURE 5 110 #define ULI_NUM_PLAYBACK 6 111 112 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 113 #define ATIHDMI_NUM_CAPTURE 0 114 #define ATIHDMI_NUM_PLAYBACK 8 115 116 /* TERA has 4 playback and 3 capture */ 117 #define TERA_NUM_CAPTURE 3 118 #define TERA_NUM_PLAYBACK 4 119 120 121 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 122 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 123 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 124 static char *model[SNDRV_CARDS]; 125 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 126 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 127 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 128 static int probe_only[SNDRV_CARDS]; 129 static int jackpoll_ms[SNDRV_CARDS]; 130 static bool single_cmd; 131 static int enable_msi = -1; 132 #ifdef CONFIG_SND_HDA_PATCH_LOADER 133 static char *patch[SNDRV_CARDS]; 134 #endif 135 #ifdef CONFIG_SND_HDA_INPUT_BEEP 136 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 137 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 138 #endif 139 140 module_param_array(index, int, NULL, 0444); 141 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 142 module_param_array(id, charp, NULL, 0444); 143 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 144 module_param_array(enable, bool, NULL, 0444); 145 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 146 module_param_array(model, charp, NULL, 0444); 147 MODULE_PARM_DESC(model, "Use the given board model."); 148 module_param_array(position_fix, int, NULL, 0444); 149 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 150 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO)."); 151 module_param_array(bdl_pos_adj, int, NULL, 0644); 152 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 153 module_param_array(probe_mask, int, NULL, 0444); 154 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 155 module_param_array(probe_only, int, NULL, 0444); 156 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 157 module_param_array(jackpoll_ms, int, NULL, 0444); 158 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 159 module_param(single_cmd, bool, 0444); 160 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 161 "(for debugging only)."); 162 module_param(enable_msi, bint, 0444); 163 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 164 #ifdef CONFIG_SND_HDA_PATCH_LOADER 165 module_param_array(patch, charp, NULL, 0444); 166 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 167 #endif 168 #ifdef CONFIG_SND_HDA_INPUT_BEEP 169 module_param_array(beep_mode, bool, NULL, 0444); 170 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 171 "(0=off, 1=on) (default=1)."); 172 #endif 173 174 #ifdef CONFIG_PM 175 static int param_set_xint(const char *val, const struct kernel_param *kp); 176 static const struct kernel_param_ops param_ops_xint = { 177 .set = param_set_xint, 178 .get = param_get_int, 179 }; 180 #define param_check_xint param_check_int 181 182 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 183 module_param(power_save, xint, 0644); 184 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 185 "(in second, 0 = disable)."); 186 187 /* reset the HD-audio controller in power save mode. 188 * this may give more power-saving, but will take longer time to 189 * wake up. 190 */ 191 static bool power_save_controller = 1; 192 module_param(power_save_controller, bool, 0644); 193 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 194 #else 195 #define power_save 0 196 #endif /* CONFIG_PM */ 197 198 static int align_buffer_size = -1; 199 module_param(align_buffer_size, bint, 0644); 200 MODULE_PARM_DESC(align_buffer_size, 201 "Force buffer and period sizes to be multiple of 128 bytes."); 202 203 #ifdef CONFIG_X86 204 static int hda_snoop = -1; 205 module_param_named(snoop, hda_snoop, bint, 0444); 206 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 207 #else 208 #define hda_snoop true 209 #endif 210 211 212 MODULE_LICENSE("GPL"); 213 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 214 "{Intel, ICH6M}," 215 "{Intel, ICH7}," 216 "{Intel, ESB2}," 217 "{Intel, ICH8}," 218 "{Intel, ICH9}," 219 "{Intel, ICH10}," 220 "{Intel, PCH}," 221 "{Intel, CPT}," 222 "{Intel, PPT}," 223 "{Intel, LPT}," 224 "{Intel, LPT_LP}," 225 "{Intel, WPT_LP}," 226 "{Intel, SPT}," 227 "{Intel, SPT_LP}," 228 "{Intel, HPT}," 229 "{Intel, PBG}," 230 "{Intel, SCH}," 231 "{ATI, SB450}," 232 "{ATI, SB600}," 233 "{ATI, RS600}," 234 "{ATI, RS690}," 235 "{ATI, RS780}," 236 "{ATI, R600}," 237 "{ATI, RV630}," 238 "{ATI, RV610}," 239 "{ATI, RV670}," 240 "{ATI, RV635}," 241 "{ATI, RV620}," 242 "{ATI, RV770}," 243 "{VIA, VT8251}," 244 "{VIA, VT8237A}," 245 "{SiS, SIS966}," 246 "{ULI, M5461}}"); 247 MODULE_DESCRIPTION("Intel HDA driver"); 248 249 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 250 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 251 #define SUPPORT_VGA_SWITCHEROO 252 #endif 253 #endif 254 255 256 /* 257 */ 258 259 /* driver types */ 260 enum { 261 AZX_DRIVER_ICH, 262 AZX_DRIVER_PCH, 263 AZX_DRIVER_SCH, 264 AZX_DRIVER_HDMI, 265 AZX_DRIVER_ATI, 266 AZX_DRIVER_ATIHDMI, 267 AZX_DRIVER_ATIHDMI_NS, 268 AZX_DRIVER_VIA, 269 AZX_DRIVER_SIS, 270 AZX_DRIVER_ULI, 271 AZX_DRIVER_NVIDIA, 272 AZX_DRIVER_TERA, 273 AZX_DRIVER_CTX, 274 AZX_DRIVER_CTHDA, 275 AZX_DRIVER_CMEDIA, 276 AZX_DRIVER_GENERIC, 277 AZX_NUM_DRIVERS, /* keep this as last entry */ 278 }; 279 280 #define azx_get_snoop_type(chip) \ 281 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 282 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 283 284 /* quirks for old Intel chipsets */ 285 #define AZX_DCAPS_INTEL_ICH \ 286 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 287 288 /* quirks for Intel PCH */ 289 #define AZX_DCAPS_INTEL_PCH_BASE \ 290 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 291 AZX_DCAPS_SNOOP_TYPE(SCH)) 292 293 /* PCH up to IVB; no runtime PM */ 294 #define AZX_DCAPS_INTEL_PCH_NOPM \ 295 (AZX_DCAPS_INTEL_PCH_BASE) 296 297 /* PCH for HSW/BDW; with runtime PM */ 298 #define AZX_DCAPS_INTEL_PCH \ 299 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) 300 301 /* HSW HDMI */ 302 #define AZX_DCAPS_INTEL_HASWELL \ 303 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 304 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\ 305 AZX_DCAPS_SNOOP_TYPE(SCH)) 306 307 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 308 #define AZX_DCAPS_INTEL_BROADWELL \ 309 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 310 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\ 311 AZX_DCAPS_SNOOP_TYPE(SCH)) 312 313 #define AZX_DCAPS_INTEL_BAYTRAIL \ 314 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL) 315 316 #define AZX_DCAPS_INTEL_BRASWELL \ 317 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL) 318 319 #define AZX_DCAPS_INTEL_SKYLAKE \ 320 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\ 321 AZX_DCAPS_I915_POWERWELL) 322 323 #define AZX_DCAPS_INTEL_BROXTON \ 324 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\ 325 AZX_DCAPS_I915_POWERWELL) 326 327 /* quirks for ATI SB / AMD Hudson */ 328 #define AZX_DCAPS_PRESET_ATI_SB \ 329 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\ 330 AZX_DCAPS_SNOOP_TYPE(ATI)) 331 332 /* quirks for ATI/AMD HDMI */ 333 #define AZX_DCAPS_PRESET_ATI_HDMI \ 334 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\ 335 AZX_DCAPS_NO_MSI64) 336 337 /* quirks for ATI HDMI with snoop off */ 338 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 339 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 340 341 /* quirks for Nvidia */ 342 #define AZX_DCAPS_PRESET_NVIDIA \ 343 (AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \ 344 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 345 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 346 347 #define AZX_DCAPS_PRESET_CTHDA \ 348 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 349 AZX_DCAPS_NO_64BIT |\ 350 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 351 352 /* 353 * vga_switcheroo support 354 */ 355 #ifdef SUPPORT_VGA_SWITCHEROO 356 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 357 #else 358 #define use_vga_switcheroo(chip) 0 359 #endif 360 361 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \ 362 ((pci)->device == 0x0c0c) || \ 363 ((pci)->device == 0x0d0c) || \ 364 ((pci)->device == 0x160c)) 365 366 #define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170) 367 #define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70) 368 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98) 369 #define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci)) 370 371 static char *driver_short_names[] = { 372 [AZX_DRIVER_ICH] = "HDA Intel", 373 [AZX_DRIVER_PCH] = "HDA Intel PCH", 374 [AZX_DRIVER_SCH] = "HDA Intel MID", 375 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 376 [AZX_DRIVER_ATI] = "HDA ATI SB", 377 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 378 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 379 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 380 [AZX_DRIVER_SIS] = "HDA SIS966", 381 [AZX_DRIVER_ULI] = "HDA ULI M5461", 382 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 383 [AZX_DRIVER_TERA] = "HDA Teradici", 384 [AZX_DRIVER_CTX] = "HDA Creative", 385 [AZX_DRIVER_CTHDA] = "HDA Creative", 386 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 387 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 388 }; 389 390 #ifdef CONFIG_X86 391 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on) 392 { 393 int pages; 394 395 if (azx_snoop(chip)) 396 return; 397 if (!dmab || !dmab->area || !dmab->bytes) 398 return; 399 400 #ifdef CONFIG_SND_DMA_SGBUF 401 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) { 402 struct snd_sg_buf *sgbuf = dmab->private_data; 403 if (chip->driver_type == AZX_DRIVER_CMEDIA) 404 return; /* deal with only CORB/RIRB buffers */ 405 if (on) 406 set_pages_array_wc(sgbuf->page_table, sgbuf->pages); 407 else 408 set_pages_array_wb(sgbuf->page_table, sgbuf->pages); 409 return; 410 } 411 #endif 412 413 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT; 414 if (on) 415 set_memory_wc((unsigned long)dmab->area, pages); 416 else 417 set_memory_wb((unsigned long)dmab->area, pages); 418 } 419 420 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 421 bool on) 422 { 423 __mark_pages_wc(chip, buf, on); 424 } 425 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 426 struct snd_pcm_substream *substream, bool on) 427 { 428 if (azx_dev->wc_marked != on) { 429 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on); 430 azx_dev->wc_marked = on; 431 } 432 } 433 #else 434 /* NOP for other archs */ 435 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 436 bool on) 437 { 438 } 439 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 440 struct snd_pcm_substream *substream, bool on) 441 { 442 } 443 #endif 444 445 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 446 447 /* 448 * initialize the PCI registers 449 */ 450 /* update bits in a PCI register byte */ 451 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 452 unsigned char mask, unsigned char val) 453 { 454 unsigned char data; 455 456 pci_read_config_byte(pci, reg, &data); 457 data &= ~mask; 458 data |= (val & mask); 459 pci_write_config_byte(pci, reg, data); 460 } 461 462 static void azx_init_pci(struct azx *chip) 463 { 464 int snoop_type = azx_get_snoop_type(chip); 465 466 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 467 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 468 * Ensuring these bits are 0 clears playback static on some HD Audio 469 * codecs. 470 * The PCI register TCSEL is defined in the Intel manuals. 471 */ 472 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 473 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 474 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 475 } 476 477 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 478 * we need to enable snoop. 479 */ 480 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 481 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 482 azx_snoop(chip)); 483 update_pci_byte(chip->pci, 484 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 485 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 486 } 487 488 /* For NVIDIA HDA, enable snoop */ 489 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 490 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 491 azx_snoop(chip)); 492 update_pci_byte(chip->pci, 493 NVIDIA_HDA_TRANSREG_ADDR, 494 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 495 update_pci_byte(chip->pci, 496 NVIDIA_HDA_ISTRM_COH, 497 0x01, NVIDIA_HDA_ENABLE_COHBIT); 498 update_pci_byte(chip->pci, 499 NVIDIA_HDA_OSTRM_COH, 500 0x01, NVIDIA_HDA_ENABLE_COHBIT); 501 } 502 503 /* Enable SCH/PCH snoop if needed */ 504 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 505 unsigned short snoop; 506 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 507 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 508 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 509 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 510 if (!azx_snoop(chip)) 511 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 512 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 513 pci_read_config_word(chip->pci, 514 INTEL_SCH_HDA_DEVC, &snoop); 515 } 516 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 517 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 518 "Disabled" : "Enabled"); 519 } 520 } 521 522 /* 523 * In BXT-P A0, HD-Audio DMA requests is later than expected, 524 * and makes an audio stream sensitive to system latencies when 525 * 24/32 bits are playing. 526 * Adjusting threshold of DMA fifo to force the DMA request 527 * sooner to improve latency tolerance at the expense of power. 528 */ 529 static void bxt_reduce_dma_latency(struct azx *chip) 530 { 531 u32 val; 532 533 val = azx_readl(chip, SKL_EM4L); 534 val &= (0x3 << 20); 535 azx_writel(chip, SKL_EM4L, val); 536 } 537 538 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 539 { 540 struct hdac_bus *bus = azx_bus(chip); 541 struct pci_dev *pci = chip->pci; 542 u32 val; 543 544 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 545 snd_hdac_set_codec_wakeup(bus, true); 546 if (IS_SKL_PLUS(pci)) { 547 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 548 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; 549 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 550 } 551 azx_init_chip(chip, full_reset); 552 if (IS_SKL_PLUS(pci)) { 553 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 554 val = val | INTEL_HDA_CGCTL_MISCBDCGE; 555 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 556 } 557 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 558 snd_hdac_set_codec_wakeup(bus, false); 559 560 /* reduce dma latency to avoid noise */ 561 if (IS_BXT(pci)) 562 bxt_reduce_dma_latency(chip); 563 } 564 565 /* calculate runtime delay from LPIB */ 566 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 567 unsigned int pos) 568 { 569 struct snd_pcm_substream *substream = azx_dev->core.substream; 570 int stream = substream->stream; 571 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 572 int delay; 573 574 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 575 delay = pos - lpib_pos; 576 else 577 delay = lpib_pos - pos; 578 if (delay < 0) { 579 if (delay >= azx_dev->core.delay_negative_threshold) 580 delay = 0; 581 else 582 delay += azx_dev->core.bufsize; 583 } 584 585 if (delay >= azx_dev->core.period_bytes) { 586 dev_info(chip->card->dev, 587 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 588 delay, azx_dev->core.period_bytes); 589 delay = 0; 590 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 591 chip->get_delay[stream] = NULL; 592 } 593 594 return bytes_to_frames(substream->runtime, delay); 595 } 596 597 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 598 599 /* called from IRQ */ 600 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 601 { 602 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 603 int ok; 604 605 ok = azx_position_ok(chip, azx_dev); 606 if (ok == 1) { 607 azx_dev->irq_pending = 0; 608 return ok; 609 } else if (ok == 0) { 610 /* bogus IRQ, process it later */ 611 azx_dev->irq_pending = 1; 612 schedule_work(&hda->irq_pending_work); 613 } 614 return 0; 615 } 616 617 /* Enable/disable i915 display power for the link */ 618 static int azx_intel_link_power(struct azx *chip, bool enable) 619 { 620 struct hdac_bus *bus = azx_bus(chip); 621 622 return snd_hdac_display_power(bus, enable); 623 } 624 625 /* 626 * Check whether the current DMA position is acceptable for updating 627 * periods. Returns non-zero if it's OK. 628 * 629 * Many HD-audio controllers appear pretty inaccurate about 630 * the update-IRQ timing. The IRQ is issued before actually the 631 * data is processed. So, we need to process it afterwords in a 632 * workqueue. 633 */ 634 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 635 { 636 struct snd_pcm_substream *substream = azx_dev->core.substream; 637 int stream = substream->stream; 638 u32 wallclk; 639 unsigned int pos; 640 641 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 642 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 643 return -1; /* bogus (too early) interrupt */ 644 645 if (chip->get_position[stream]) 646 pos = chip->get_position[stream](chip, azx_dev); 647 else { /* use the position buffer as default */ 648 pos = azx_get_pos_posbuf(chip, azx_dev); 649 if (!pos || pos == (u32)-1) { 650 dev_info(chip->card->dev, 651 "Invalid position buffer, using LPIB read method instead.\n"); 652 chip->get_position[stream] = azx_get_pos_lpib; 653 if (chip->get_position[0] == azx_get_pos_lpib && 654 chip->get_position[1] == azx_get_pos_lpib) 655 azx_bus(chip)->use_posbuf = false; 656 pos = azx_get_pos_lpib(chip, azx_dev); 657 chip->get_delay[stream] = NULL; 658 } else { 659 chip->get_position[stream] = azx_get_pos_posbuf; 660 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 661 chip->get_delay[stream] = azx_get_delay_from_lpib; 662 } 663 } 664 665 if (pos >= azx_dev->core.bufsize) 666 pos = 0; 667 668 if (WARN_ONCE(!azx_dev->core.period_bytes, 669 "hda-intel: zero azx_dev->period_bytes")) 670 return -1; /* this shouldn't happen! */ 671 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 672 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 673 /* NG - it's below the first next period boundary */ 674 return chip->bdl_pos_adj ? 0 : -1; 675 azx_dev->core.start_wallclk += wallclk; 676 return 1; /* OK, it's fine */ 677 } 678 679 /* 680 * The work for pending PCM period updates. 681 */ 682 static void azx_irq_pending_work(struct work_struct *work) 683 { 684 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 685 struct azx *chip = &hda->chip; 686 struct hdac_bus *bus = azx_bus(chip); 687 struct hdac_stream *s; 688 int pending, ok; 689 690 if (!hda->irq_pending_warned) { 691 dev_info(chip->card->dev, 692 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 693 chip->card->number); 694 hda->irq_pending_warned = 1; 695 } 696 697 for (;;) { 698 pending = 0; 699 spin_lock_irq(&bus->reg_lock); 700 list_for_each_entry(s, &bus->stream_list, list) { 701 struct azx_dev *azx_dev = stream_to_azx_dev(s); 702 if (!azx_dev->irq_pending || 703 !s->substream || 704 !s->running) 705 continue; 706 ok = azx_position_ok(chip, azx_dev); 707 if (ok > 0) { 708 azx_dev->irq_pending = 0; 709 spin_unlock(&bus->reg_lock); 710 snd_pcm_period_elapsed(s->substream); 711 spin_lock(&bus->reg_lock); 712 } else if (ok < 0) { 713 pending = 0; /* too early */ 714 } else 715 pending++; 716 } 717 spin_unlock_irq(&bus->reg_lock); 718 if (!pending) 719 return; 720 msleep(1); 721 } 722 } 723 724 /* clear irq_pending flags and assure no on-going workq */ 725 static void azx_clear_irq_pending(struct azx *chip) 726 { 727 struct hdac_bus *bus = azx_bus(chip); 728 struct hdac_stream *s; 729 730 spin_lock_irq(&bus->reg_lock); 731 list_for_each_entry(s, &bus->stream_list, list) { 732 struct azx_dev *azx_dev = stream_to_azx_dev(s); 733 azx_dev->irq_pending = 0; 734 } 735 spin_unlock_irq(&bus->reg_lock); 736 } 737 738 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 739 { 740 struct hdac_bus *bus = azx_bus(chip); 741 742 if (request_irq(chip->pci->irq, azx_interrupt, 743 chip->msi ? 0 : IRQF_SHARED, 744 chip->card->irq_descr, chip)) { 745 dev_err(chip->card->dev, 746 "unable to grab IRQ %d, disabling device\n", 747 chip->pci->irq); 748 if (do_disconnect) 749 snd_card_disconnect(chip->card); 750 return -1; 751 } 752 bus->irq = chip->pci->irq; 753 pci_intx(chip->pci, !chip->msi); 754 return 0; 755 } 756 757 /* get the current DMA position with correction on VIA chips */ 758 static unsigned int azx_via_get_position(struct azx *chip, 759 struct azx_dev *azx_dev) 760 { 761 unsigned int link_pos, mini_pos, bound_pos; 762 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 763 unsigned int fifo_size; 764 765 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 766 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 767 /* Playback, no problem using link position */ 768 return link_pos; 769 } 770 771 /* Capture */ 772 /* For new chipset, 773 * use mod to get the DMA position just like old chipset 774 */ 775 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 776 mod_dma_pos %= azx_dev->core.period_bytes; 777 778 /* azx_dev->fifo_size can't get FIFO size of in stream. 779 * Get from base address + offset. 780 */ 781 fifo_size = readw(azx_bus(chip)->remap_addr + 782 VIA_IN_STREAM0_FIFO_SIZE_OFFSET); 783 784 if (azx_dev->insufficient) { 785 /* Link position never gather than FIFO size */ 786 if (link_pos <= fifo_size) 787 return 0; 788 789 azx_dev->insufficient = 0; 790 } 791 792 if (link_pos <= fifo_size) 793 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 794 else 795 mini_pos = link_pos - fifo_size; 796 797 /* Find nearest previous boudary */ 798 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 799 mod_link_pos = link_pos % azx_dev->core.period_bytes; 800 if (mod_link_pos >= fifo_size) 801 bound_pos = link_pos - mod_link_pos; 802 else if (mod_dma_pos >= mod_mini_pos) 803 bound_pos = mini_pos - mod_mini_pos; 804 else { 805 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 806 if (bound_pos >= azx_dev->core.bufsize) 807 bound_pos = 0; 808 } 809 810 /* Calculate real DMA position we want */ 811 return bound_pos + mod_dma_pos; 812 } 813 814 #ifdef CONFIG_PM 815 static DEFINE_MUTEX(card_list_lock); 816 static LIST_HEAD(card_list); 817 818 static void azx_add_card_list(struct azx *chip) 819 { 820 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 821 mutex_lock(&card_list_lock); 822 list_add(&hda->list, &card_list); 823 mutex_unlock(&card_list_lock); 824 } 825 826 static void azx_del_card_list(struct azx *chip) 827 { 828 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 829 mutex_lock(&card_list_lock); 830 list_del_init(&hda->list); 831 mutex_unlock(&card_list_lock); 832 } 833 834 /* trigger power-save check at writing parameter */ 835 static int param_set_xint(const char *val, const struct kernel_param *kp) 836 { 837 struct hda_intel *hda; 838 struct azx *chip; 839 int prev = power_save; 840 int ret = param_set_int(val, kp); 841 842 if (ret || prev == power_save) 843 return ret; 844 845 mutex_lock(&card_list_lock); 846 list_for_each_entry(hda, &card_list, list) { 847 chip = &hda->chip; 848 if (!hda->probe_continued || chip->disabled) 849 continue; 850 snd_hda_set_power_save(&chip->bus, power_save * 1000); 851 } 852 mutex_unlock(&card_list_lock); 853 return 0; 854 } 855 #else 856 #define azx_add_card_list(chip) /* NOP */ 857 #define azx_del_card_list(chip) /* NOP */ 858 #endif /* CONFIG_PM */ 859 860 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO) 861 /* 862 * power management 863 */ 864 static int azx_suspend(struct device *dev) 865 { 866 struct snd_card *card = dev_get_drvdata(dev); 867 struct azx *chip; 868 struct hda_intel *hda; 869 struct hdac_bus *bus; 870 871 if (!card) 872 return 0; 873 874 chip = card->private_data; 875 hda = container_of(chip, struct hda_intel, chip); 876 if (chip->disabled || hda->init_failed || !chip->running) 877 return 0; 878 879 bus = azx_bus(chip); 880 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 881 azx_clear_irq_pending(chip); 882 azx_stop_chip(chip); 883 azx_enter_link_reset(chip); 884 if (bus->irq >= 0) { 885 free_irq(bus->irq, chip); 886 bus->irq = -1; 887 } 888 889 if (chip->msi) 890 pci_disable_msi(chip->pci); 891 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL 892 && hda->need_i915_power) 893 snd_hdac_display_power(bus, false); 894 895 trace_azx_suspend(chip); 896 return 0; 897 } 898 899 static int azx_resume(struct device *dev) 900 { 901 struct pci_dev *pci = to_pci_dev(dev); 902 struct snd_card *card = dev_get_drvdata(dev); 903 struct azx *chip; 904 struct hda_intel *hda; 905 906 if (!card) 907 return 0; 908 909 chip = card->private_data; 910 hda = container_of(chip, struct hda_intel, chip); 911 if (chip->disabled || hda->init_failed || !chip->running) 912 return 0; 913 914 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL 915 && hda->need_i915_power) { 916 snd_hdac_display_power(azx_bus(chip), true); 917 snd_hdac_i915_set_bclk(azx_bus(chip)); 918 } 919 if (chip->msi) 920 if (pci_enable_msi(pci) < 0) 921 chip->msi = 0; 922 if (azx_acquire_irq(chip, 1) < 0) 923 return -EIO; 924 azx_init_pci(chip); 925 926 hda_intel_init_chip(chip, true); 927 928 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 929 930 trace_azx_resume(chip); 931 return 0; 932 } 933 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */ 934 935 #ifdef CONFIG_PM_SLEEP 936 /* put codec down to D3 at hibernation for Intel SKL+; 937 * otherwise BIOS may still access the codec and screw up the driver 938 */ 939 static int azx_freeze_noirq(struct device *dev) 940 { 941 struct pci_dev *pci = to_pci_dev(dev); 942 943 if (IS_SKL_PLUS(pci)) 944 pci_set_power_state(pci, PCI_D3hot); 945 946 return 0; 947 } 948 949 static int azx_thaw_noirq(struct device *dev) 950 { 951 struct pci_dev *pci = to_pci_dev(dev); 952 953 if (IS_SKL_PLUS(pci)) 954 pci_set_power_state(pci, PCI_D0); 955 956 return 0; 957 } 958 #endif /* CONFIG_PM_SLEEP */ 959 960 #ifdef CONFIG_PM 961 static int azx_runtime_suspend(struct device *dev) 962 { 963 struct snd_card *card = dev_get_drvdata(dev); 964 struct azx *chip; 965 struct hda_intel *hda; 966 967 if (!card) 968 return 0; 969 970 chip = card->private_data; 971 hda = container_of(chip, struct hda_intel, chip); 972 if (chip->disabled || hda->init_failed) 973 return 0; 974 975 if (!azx_has_pm_runtime(chip)) 976 return 0; 977 978 /* enable controller wake up event */ 979 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 980 STATESTS_INT_MASK); 981 982 azx_stop_chip(chip); 983 azx_enter_link_reset(chip); 984 azx_clear_irq_pending(chip); 985 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL 986 && hda->need_i915_power) 987 snd_hdac_display_power(azx_bus(chip), false); 988 989 trace_azx_runtime_suspend(chip); 990 return 0; 991 } 992 993 static int azx_runtime_resume(struct device *dev) 994 { 995 struct snd_card *card = dev_get_drvdata(dev); 996 struct azx *chip; 997 struct hda_intel *hda; 998 struct hdac_bus *bus; 999 struct hda_codec *codec; 1000 int status; 1001 1002 if (!card) 1003 return 0; 1004 1005 chip = card->private_data; 1006 hda = container_of(chip, struct hda_intel, chip); 1007 if (chip->disabled || hda->init_failed) 1008 return 0; 1009 1010 if (!azx_has_pm_runtime(chip)) 1011 return 0; 1012 1013 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1014 bus = azx_bus(chip); 1015 if (hda->need_i915_power) { 1016 snd_hdac_display_power(bus, true); 1017 snd_hdac_i915_set_bclk(bus); 1018 } else { 1019 /* toggle codec wakeup bit for STATESTS read */ 1020 snd_hdac_set_codec_wakeup(bus, true); 1021 snd_hdac_set_codec_wakeup(bus, false); 1022 } 1023 } 1024 1025 /* Read STATESTS before controller reset */ 1026 status = azx_readw(chip, STATESTS); 1027 1028 azx_init_pci(chip); 1029 hda_intel_init_chip(chip, true); 1030 1031 if (status) { 1032 list_for_each_codec(codec, &chip->bus) 1033 if (status & (1 << codec->addr)) 1034 schedule_delayed_work(&codec->jackpoll_work, 1035 codec->jackpoll_interval); 1036 } 1037 1038 /* disable controller Wake Up event*/ 1039 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 1040 ~STATESTS_INT_MASK); 1041 1042 trace_azx_runtime_resume(chip); 1043 return 0; 1044 } 1045 1046 static int azx_runtime_idle(struct device *dev) 1047 { 1048 struct snd_card *card = dev_get_drvdata(dev); 1049 struct azx *chip; 1050 struct hda_intel *hda; 1051 1052 if (!card) 1053 return 0; 1054 1055 chip = card->private_data; 1056 hda = container_of(chip, struct hda_intel, chip); 1057 if (chip->disabled || hda->init_failed) 1058 return 0; 1059 1060 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1061 azx_bus(chip)->codec_powered || !chip->running) 1062 return -EBUSY; 1063 1064 return 0; 1065 } 1066 1067 static const struct dev_pm_ops azx_pm = { 1068 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1069 #ifdef CONFIG_PM_SLEEP 1070 .freeze_noirq = azx_freeze_noirq, 1071 .thaw_noirq = azx_thaw_noirq, 1072 #endif 1073 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1074 }; 1075 1076 #define AZX_PM_OPS &azx_pm 1077 #else 1078 #define AZX_PM_OPS NULL 1079 #endif /* CONFIG_PM */ 1080 1081 1082 static int azx_probe_continue(struct azx *chip); 1083 1084 #ifdef SUPPORT_VGA_SWITCHEROO 1085 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1086 1087 static void azx_vs_set_state(struct pci_dev *pci, 1088 enum vga_switcheroo_state state) 1089 { 1090 struct snd_card *card = pci_get_drvdata(pci); 1091 struct azx *chip = card->private_data; 1092 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1093 bool disabled; 1094 1095 wait_for_completion(&hda->probe_wait); 1096 if (hda->init_failed) 1097 return; 1098 1099 disabled = (state == VGA_SWITCHEROO_OFF); 1100 if (chip->disabled == disabled) 1101 return; 1102 1103 if (!hda->probe_continued) { 1104 chip->disabled = disabled; 1105 if (!disabled) { 1106 dev_info(chip->card->dev, 1107 "Start delayed initialization\n"); 1108 if (azx_probe_continue(chip) < 0) { 1109 dev_err(chip->card->dev, "initialization error\n"); 1110 hda->init_failed = true; 1111 } 1112 } 1113 } else { 1114 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1115 disabled ? "Disabling" : "Enabling"); 1116 if (disabled) { 1117 pm_runtime_put_sync_suspend(card->dev); 1118 azx_suspend(card->dev); 1119 /* when we get suspended by vga_switcheroo we end up in D3cold, 1120 * however we have no ACPI handle, so pci/acpi can't put us there, 1121 * put ourselves there */ 1122 pci->current_state = PCI_D3cold; 1123 chip->disabled = true; 1124 if (snd_hda_lock_devices(&chip->bus)) 1125 dev_warn(chip->card->dev, 1126 "Cannot lock devices!\n"); 1127 } else { 1128 snd_hda_unlock_devices(&chip->bus); 1129 pm_runtime_get_noresume(card->dev); 1130 chip->disabled = false; 1131 azx_resume(card->dev); 1132 } 1133 } 1134 } 1135 1136 static bool azx_vs_can_switch(struct pci_dev *pci) 1137 { 1138 struct snd_card *card = pci_get_drvdata(pci); 1139 struct azx *chip = card->private_data; 1140 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1141 1142 wait_for_completion(&hda->probe_wait); 1143 if (hda->init_failed) 1144 return false; 1145 if (chip->disabled || !hda->probe_continued) 1146 return true; 1147 if (snd_hda_lock_devices(&chip->bus)) 1148 return false; 1149 snd_hda_unlock_devices(&chip->bus); 1150 return true; 1151 } 1152 1153 static void init_vga_switcheroo(struct azx *chip) 1154 { 1155 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1156 struct pci_dev *p = get_bound_vga(chip->pci); 1157 if (p) { 1158 dev_info(chip->card->dev, 1159 "Handle vga_switcheroo audio client\n"); 1160 hda->use_vga_switcheroo = 1; 1161 pci_dev_put(p); 1162 } 1163 } 1164 1165 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1166 .set_gpu_state = azx_vs_set_state, 1167 .can_switch = azx_vs_can_switch, 1168 }; 1169 1170 static int register_vga_switcheroo(struct azx *chip) 1171 { 1172 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1173 int err; 1174 1175 if (!hda->use_vga_switcheroo) 1176 return 0; 1177 /* FIXME: currently only handling DIS controller 1178 * is there any machine with two switchable HDMI audio controllers? 1179 */ 1180 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, 1181 VGA_SWITCHEROO_DIS); 1182 if (err < 0) 1183 return err; 1184 hda->vga_switcheroo_registered = 1; 1185 1186 /* register as an optimus hdmi audio power domain */ 1187 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev, 1188 &hda->hdmi_pm_domain); 1189 return 0; 1190 } 1191 #else 1192 #define init_vga_switcheroo(chip) /* NOP */ 1193 #define register_vga_switcheroo(chip) 0 1194 #define check_hdmi_disabled(pci) false 1195 #endif /* SUPPORT_VGA_SWITCHER */ 1196 1197 /* 1198 * destructor 1199 */ 1200 static int azx_free(struct azx *chip) 1201 { 1202 struct pci_dev *pci = chip->pci; 1203 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1204 struct hdac_bus *bus = azx_bus(chip); 1205 1206 if (azx_has_pm_runtime(chip) && chip->running) 1207 pm_runtime_get_noresume(&pci->dev); 1208 1209 azx_del_card_list(chip); 1210 1211 hda->init_failed = 1; /* to be sure */ 1212 complete_all(&hda->probe_wait); 1213 1214 if (use_vga_switcheroo(hda)) { 1215 if (chip->disabled && hda->probe_continued) 1216 snd_hda_unlock_devices(&chip->bus); 1217 if (hda->vga_switcheroo_registered) 1218 vga_switcheroo_unregister_client(chip->pci); 1219 } 1220 1221 if (bus->chip_init) { 1222 azx_clear_irq_pending(chip); 1223 azx_stop_all_streams(chip); 1224 azx_stop_chip(chip); 1225 } 1226 1227 if (bus->irq >= 0) 1228 free_irq(bus->irq, (void*)chip); 1229 if (chip->msi) 1230 pci_disable_msi(chip->pci); 1231 iounmap(bus->remap_addr); 1232 1233 azx_free_stream_pages(chip); 1234 azx_free_streams(chip); 1235 snd_hdac_bus_exit(bus); 1236 1237 if (chip->region_requested) 1238 pci_release_regions(chip->pci); 1239 1240 pci_disable_device(chip->pci); 1241 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1242 release_firmware(chip->fw); 1243 #endif 1244 1245 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1246 if (hda->need_i915_power) 1247 snd_hdac_display_power(bus, false); 1248 snd_hdac_i915_exit(bus); 1249 } 1250 kfree(hda); 1251 1252 return 0; 1253 } 1254 1255 static int azx_dev_disconnect(struct snd_device *device) 1256 { 1257 struct azx *chip = device->device_data; 1258 1259 chip->bus.shutdown = 1; 1260 return 0; 1261 } 1262 1263 static int azx_dev_free(struct snd_device *device) 1264 { 1265 return azx_free(device->device_data); 1266 } 1267 1268 #ifdef SUPPORT_VGA_SWITCHEROO 1269 /* 1270 * Check of disabled HDMI controller by vga_switcheroo 1271 */ 1272 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1273 { 1274 struct pci_dev *p; 1275 1276 /* check only discrete GPU */ 1277 switch (pci->vendor) { 1278 case PCI_VENDOR_ID_ATI: 1279 case PCI_VENDOR_ID_AMD: 1280 case PCI_VENDOR_ID_NVIDIA: 1281 if (pci->devfn == 1) { 1282 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1283 pci->bus->number, 0); 1284 if (p) { 1285 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA) 1286 return p; 1287 pci_dev_put(p); 1288 } 1289 } 1290 break; 1291 } 1292 return NULL; 1293 } 1294 1295 static bool check_hdmi_disabled(struct pci_dev *pci) 1296 { 1297 bool vga_inactive = false; 1298 struct pci_dev *p = get_bound_vga(pci); 1299 1300 if (p) { 1301 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1302 vga_inactive = true; 1303 pci_dev_put(p); 1304 } 1305 return vga_inactive; 1306 } 1307 #endif /* SUPPORT_VGA_SWITCHEROO */ 1308 1309 /* 1310 * white/black-listing for position_fix 1311 */ 1312 static struct snd_pci_quirk position_fix_list[] = { 1313 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1314 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1315 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1316 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1317 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1318 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1319 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1320 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1321 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1322 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1323 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1324 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1325 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1326 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1327 {} 1328 }; 1329 1330 static int check_position_fix(struct azx *chip, int fix) 1331 { 1332 const struct snd_pci_quirk *q; 1333 1334 switch (fix) { 1335 case POS_FIX_AUTO: 1336 case POS_FIX_LPIB: 1337 case POS_FIX_POSBUF: 1338 case POS_FIX_VIACOMBO: 1339 case POS_FIX_COMBO: 1340 return fix; 1341 } 1342 1343 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1344 if (q) { 1345 dev_info(chip->card->dev, 1346 "position_fix set to %d for device %04x:%04x\n", 1347 q->value, q->subvendor, q->subdevice); 1348 return q->value; 1349 } 1350 1351 /* Check VIA/ATI HD Audio Controller exist */ 1352 if (chip->driver_type == AZX_DRIVER_VIA) { 1353 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1354 return POS_FIX_VIACOMBO; 1355 } 1356 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1357 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1358 return POS_FIX_LPIB; 1359 } 1360 return POS_FIX_AUTO; 1361 } 1362 1363 static void assign_position_fix(struct azx *chip, int fix) 1364 { 1365 static azx_get_pos_callback_t callbacks[] = { 1366 [POS_FIX_AUTO] = NULL, 1367 [POS_FIX_LPIB] = azx_get_pos_lpib, 1368 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1369 [POS_FIX_VIACOMBO] = azx_via_get_position, 1370 [POS_FIX_COMBO] = azx_get_pos_lpib, 1371 }; 1372 1373 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1374 1375 /* combo mode uses LPIB only for playback */ 1376 if (fix == POS_FIX_COMBO) 1377 chip->get_position[1] = NULL; 1378 1379 if (fix == POS_FIX_POSBUF && 1380 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1381 chip->get_delay[0] = chip->get_delay[1] = 1382 azx_get_delay_from_lpib; 1383 } 1384 1385 } 1386 1387 /* 1388 * black-lists for probe_mask 1389 */ 1390 static struct snd_pci_quirk probe_mask_list[] = { 1391 /* Thinkpad often breaks the controller communication when accessing 1392 * to the non-working (or non-existing) modem codec slot. 1393 */ 1394 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1395 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1396 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1397 /* broken BIOS */ 1398 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1399 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1400 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1401 /* forced codec slots */ 1402 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1403 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1404 /* WinFast VP200 H (Teradici) user reported broken communication */ 1405 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1406 {} 1407 }; 1408 1409 #define AZX_FORCE_CODEC_MASK 0x100 1410 1411 static void check_probe_mask(struct azx *chip, int dev) 1412 { 1413 const struct snd_pci_quirk *q; 1414 1415 chip->codec_probe_mask = probe_mask[dev]; 1416 if (chip->codec_probe_mask == -1) { 1417 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1418 if (q) { 1419 dev_info(chip->card->dev, 1420 "probe_mask set to 0x%x for device %04x:%04x\n", 1421 q->value, q->subvendor, q->subdevice); 1422 chip->codec_probe_mask = q->value; 1423 } 1424 } 1425 1426 /* check forced option */ 1427 if (chip->codec_probe_mask != -1 && 1428 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1429 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1430 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1431 (int)azx_bus(chip)->codec_mask); 1432 } 1433 } 1434 1435 /* 1436 * white/black-list for enable_msi 1437 */ 1438 static struct snd_pci_quirk msi_black_list[] = { 1439 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1440 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1441 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1442 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1443 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1444 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1445 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1446 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1447 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1448 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1449 {} 1450 }; 1451 1452 static void check_msi(struct azx *chip) 1453 { 1454 const struct snd_pci_quirk *q; 1455 1456 if (enable_msi >= 0) { 1457 chip->msi = !!enable_msi; 1458 return; 1459 } 1460 chip->msi = 1; /* enable MSI as default */ 1461 q = snd_pci_quirk_lookup(chip->pci, msi_black_list); 1462 if (q) { 1463 dev_info(chip->card->dev, 1464 "msi for device %04x:%04x set to %d\n", 1465 q->subvendor, q->subdevice, q->value); 1466 chip->msi = q->value; 1467 return; 1468 } 1469 1470 /* NVidia chipsets seem to cause troubles with MSI */ 1471 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1472 dev_info(chip->card->dev, "Disabling MSI\n"); 1473 chip->msi = 0; 1474 } 1475 } 1476 1477 /* check the snoop mode availability */ 1478 static void azx_check_snoop_available(struct azx *chip) 1479 { 1480 int snoop = hda_snoop; 1481 1482 if (snoop >= 0) { 1483 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1484 snoop ? "snoop" : "non-snoop"); 1485 chip->snoop = snoop; 1486 return; 1487 } 1488 1489 snoop = true; 1490 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1491 chip->driver_type == AZX_DRIVER_VIA) { 1492 /* force to non-snoop mode for a new VIA controller 1493 * when BIOS is set 1494 */ 1495 u8 val; 1496 pci_read_config_byte(chip->pci, 0x42, &val); 1497 if (!(val & 0x80) && chip->pci->revision == 0x30) 1498 snoop = false; 1499 } 1500 1501 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1502 snoop = false; 1503 1504 chip->snoop = snoop; 1505 if (!snoop) 1506 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1507 } 1508 1509 static void azx_probe_work(struct work_struct *work) 1510 { 1511 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work); 1512 azx_probe_continue(&hda->chip); 1513 } 1514 1515 static int default_bdl_pos_adj(struct azx *chip) 1516 { 1517 /* some exceptions: Atoms seem problematic with value 1 */ 1518 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { 1519 switch (chip->pci->device) { 1520 case 0x0f04: /* Baytrail */ 1521 case 0x2284: /* Braswell */ 1522 return 32; 1523 } 1524 } 1525 1526 switch (chip->driver_type) { 1527 case AZX_DRIVER_ICH: 1528 case AZX_DRIVER_PCH: 1529 return 1; 1530 default: 1531 return 32; 1532 } 1533 } 1534 1535 /* 1536 * constructor 1537 */ 1538 static const struct hdac_io_ops pci_hda_io_ops; 1539 static const struct hda_controller_ops pci_hda_ops; 1540 1541 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1542 int dev, unsigned int driver_caps, 1543 struct azx **rchip) 1544 { 1545 static struct snd_device_ops ops = { 1546 .dev_disconnect = azx_dev_disconnect, 1547 .dev_free = azx_dev_free, 1548 }; 1549 struct hda_intel *hda; 1550 struct azx *chip; 1551 int err; 1552 1553 *rchip = NULL; 1554 1555 err = pci_enable_device(pci); 1556 if (err < 0) 1557 return err; 1558 1559 hda = kzalloc(sizeof(*hda), GFP_KERNEL); 1560 if (!hda) { 1561 pci_disable_device(pci); 1562 return -ENOMEM; 1563 } 1564 1565 chip = &hda->chip; 1566 mutex_init(&chip->open_mutex); 1567 chip->card = card; 1568 chip->pci = pci; 1569 chip->ops = &pci_hda_ops; 1570 chip->driver_caps = driver_caps; 1571 chip->driver_type = driver_caps & 0xff; 1572 check_msi(chip); 1573 chip->dev_index = dev; 1574 chip->jackpoll_ms = jackpoll_ms; 1575 INIT_LIST_HEAD(&chip->pcm_list); 1576 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1577 INIT_LIST_HEAD(&hda->list); 1578 init_vga_switcheroo(chip); 1579 init_completion(&hda->probe_wait); 1580 1581 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1582 1583 check_probe_mask(chip, dev); 1584 1585 chip->single_cmd = single_cmd; 1586 azx_check_snoop_available(chip); 1587 1588 if (bdl_pos_adj[dev] < 0) 1589 chip->bdl_pos_adj = default_bdl_pos_adj(chip); 1590 else 1591 chip->bdl_pos_adj = bdl_pos_adj[dev]; 1592 1593 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops); 1594 if (err < 0) { 1595 kfree(hda); 1596 pci_disable_device(pci); 1597 return err; 1598 } 1599 1600 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 1601 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); 1602 chip->bus.needs_damn_long_delay = 1; 1603 } 1604 1605 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1606 if (err < 0) { 1607 dev_err(card->dev, "Error creating device [card]!\n"); 1608 azx_free(chip); 1609 return err; 1610 } 1611 1612 /* continue probing in work context as may trigger request module */ 1613 INIT_WORK(&hda->probe_work, azx_probe_work); 1614 1615 *rchip = chip; 1616 1617 return 0; 1618 } 1619 1620 static int azx_first_init(struct azx *chip) 1621 { 1622 int dev = chip->dev_index; 1623 struct pci_dev *pci = chip->pci; 1624 struct snd_card *card = chip->card; 1625 struct hdac_bus *bus = azx_bus(chip); 1626 int err; 1627 unsigned short gcap; 1628 unsigned int dma_bits = 64; 1629 1630 #if BITS_PER_LONG != 64 1631 /* Fix up base address on ULI M5461 */ 1632 if (chip->driver_type == AZX_DRIVER_ULI) { 1633 u16 tmp3; 1634 pci_read_config_word(pci, 0x40, &tmp3); 1635 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1636 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1637 } 1638 #endif 1639 1640 err = pci_request_regions(pci, "ICH HD audio"); 1641 if (err < 0) 1642 return err; 1643 chip->region_requested = 1; 1644 1645 bus->addr = pci_resource_start(pci, 0); 1646 bus->remap_addr = pci_ioremap_bar(pci, 0); 1647 if (bus->remap_addr == NULL) { 1648 dev_err(card->dev, "ioremap error\n"); 1649 return -ENXIO; 1650 } 1651 1652 if (chip->msi) { 1653 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1654 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1655 pci->no_64bit_msi = true; 1656 } 1657 if (pci_enable_msi(pci) < 0) 1658 chip->msi = 0; 1659 } 1660 1661 if (azx_acquire_irq(chip, 0) < 0) 1662 return -EBUSY; 1663 1664 pci_set_master(pci); 1665 synchronize_irq(bus->irq); 1666 1667 gcap = azx_readw(chip, GCAP); 1668 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1669 1670 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1671 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1672 dma_bits = 40; 1673 1674 /* disable SB600 64bit support for safety */ 1675 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1676 struct pci_dev *p_smbus; 1677 dma_bits = 40; 1678 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1679 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1680 NULL); 1681 if (p_smbus) { 1682 if (p_smbus->revision < 0x30) 1683 gcap &= ~AZX_GCAP_64OK; 1684 pci_dev_put(p_smbus); 1685 } 1686 } 1687 1688 /* disable 64bit DMA address on some devices */ 1689 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1690 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1691 gcap &= ~AZX_GCAP_64OK; 1692 } 1693 1694 /* disable buffer size rounding to 128-byte multiples if supported */ 1695 if (align_buffer_size >= 0) 1696 chip->align_buffer_size = !!align_buffer_size; 1697 else { 1698 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1699 chip->align_buffer_size = 0; 1700 else 1701 chip->align_buffer_size = 1; 1702 } 1703 1704 /* allow 64bit DMA address if supported by H/W */ 1705 if (!(gcap & AZX_GCAP_64OK)) 1706 dma_bits = 32; 1707 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) { 1708 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits)); 1709 } else { 1710 dma_set_mask(&pci->dev, DMA_BIT_MASK(32)); 1711 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32)); 1712 } 1713 1714 /* read number of streams from GCAP register instead of using 1715 * hardcoded value 1716 */ 1717 chip->capture_streams = (gcap >> 8) & 0x0f; 1718 chip->playback_streams = (gcap >> 12) & 0x0f; 1719 if (!chip->playback_streams && !chip->capture_streams) { 1720 /* gcap didn't give any info, switching to old method */ 1721 1722 switch (chip->driver_type) { 1723 case AZX_DRIVER_ULI: 1724 chip->playback_streams = ULI_NUM_PLAYBACK; 1725 chip->capture_streams = ULI_NUM_CAPTURE; 1726 break; 1727 case AZX_DRIVER_ATIHDMI: 1728 case AZX_DRIVER_ATIHDMI_NS: 1729 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1730 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1731 break; 1732 case AZX_DRIVER_GENERIC: 1733 default: 1734 chip->playback_streams = ICH6_NUM_PLAYBACK; 1735 chip->capture_streams = ICH6_NUM_CAPTURE; 1736 break; 1737 } 1738 } 1739 chip->capture_index_offset = 0; 1740 chip->playback_index_offset = chip->capture_streams; 1741 chip->num_streams = chip->playback_streams + chip->capture_streams; 1742 1743 /* initialize streams */ 1744 err = azx_init_streams(chip); 1745 if (err < 0) 1746 return err; 1747 1748 err = azx_alloc_stream_pages(chip); 1749 if (err < 0) 1750 return err; 1751 1752 /* initialize chip */ 1753 azx_init_pci(chip); 1754 1755 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 1756 snd_hdac_i915_set_bclk(bus); 1757 1758 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 1759 1760 /* codec detection */ 1761 if (!azx_bus(chip)->codec_mask) { 1762 dev_err(card->dev, "no codecs found!\n"); 1763 return -ENODEV; 1764 } 1765 1766 strcpy(card->driver, "HDA-Intel"); 1767 strlcpy(card->shortname, driver_short_names[chip->driver_type], 1768 sizeof(card->shortname)); 1769 snprintf(card->longname, sizeof(card->longname), 1770 "%s at 0x%lx irq %i", 1771 card->shortname, bus->addr, bus->irq); 1772 1773 return 0; 1774 } 1775 1776 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1777 /* callback from request_firmware_nowait() */ 1778 static void azx_firmware_cb(const struct firmware *fw, void *context) 1779 { 1780 struct snd_card *card = context; 1781 struct azx *chip = card->private_data; 1782 struct pci_dev *pci = chip->pci; 1783 1784 if (!fw) { 1785 dev_err(card->dev, "Cannot load firmware, aborting\n"); 1786 goto error; 1787 } 1788 1789 chip->fw = fw; 1790 if (!chip->disabled) { 1791 /* continue probing */ 1792 if (azx_probe_continue(chip)) 1793 goto error; 1794 } 1795 return; /* OK */ 1796 1797 error: 1798 snd_card_free(card); 1799 pci_set_drvdata(pci, NULL); 1800 } 1801 #endif 1802 1803 /* 1804 * HDA controller ops. 1805 */ 1806 1807 /* PCI register access. */ 1808 static void pci_azx_writel(u32 value, u32 __iomem *addr) 1809 { 1810 writel(value, addr); 1811 } 1812 1813 static u32 pci_azx_readl(u32 __iomem *addr) 1814 { 1815 return readl(addr); 1816 } 1817 1818 static void pci_azx_writew(u16 value, u16 __iomem *addr) 1819 { 1820 writew(value, addr); 1821 } 1822 1823 static u16 pci_azx_readw(u16 __iomem *addr) 1824 { 1825 return readw(addr); 1826 } 1827 1828 static void pci_azx_writeb(u8 value, u8 __iomem *addr) 1829 { 1830 writeb(value, addr); 1831 } 1832 1833 static u8 pci_azx_readb(u8 __iomem *addr) 1834 { 1835 return readb(addr); 1836 } 1837 1838 static int disable_msi_reset_irq(struct azx *chip) 1839 { 1840 struct hdac_bus *bus = azx_bus(chip); 1841 int err; 1842 1843 free_irq(bus->irq, chip); 1844 bus->irq = -1; 1845 pci_disable_msi(chip->pci); 1846 chip->msi = 0; 1847 err = azx_acquire_irq(chip, 1); 1848 if (err < 0) 1849 return err; 1850 1851 return 0; 1852 } 1853 1854 /* DMA page allocation helpers. */ 1855 static int dma_alloc_pages(struct hdac_bus *bus, 1856 int type, 1857 size_t size, 1858 struct snd_dma_buffer *buf) 1859 { 1860 struct azx *chip = bus_to_azx(bus); 1861 int err; 1862 1863 err = snd_dma_alloc_pages(type, 1864 bus->dev, 1865 size, buf); 1866 if (err < 0) 1867 return err; 1868 mark_pages_wc(chip, buf, true); 1869 return 0; 1870 } 1871 1872 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf) 1873 { 1874 struct azx *chip = bus_to_azx(bus); 1875 1876 mark_pages_wc(chip, buf, false); 1877 snd_dma_free_pages(buf); 1878 } 1879 1880 static int substream_alloc_pages(struct azx *chip, 1881 struct snd_pcm_substream *substream, 1882 size_t size) 1883 { 1884 struct azx_dev *azx_dev = get_azx_dev(substream); 1885 int ret; 1886 1887 mark_runtime_wc(chip, azx_dev, substream, false); 1888 ret = snd_pcm_lib_malloc_pages(substream, size); 1889 if (ret < 0) 1890 return ret; 1891 mark_runtime_wc(chip, azx_dev, substream, true); 1892 return 0; 1893 } 1894 1895 static int substream_free_pages(struct azx *chip, 1896 struct snd_pcm_substream *substream) 1897 { 1898 struct azx_dev *azx_dev = get_azx_dev(substream); 1899 mark_runtime_wc(chip, azx_dev, substream, false); 1900 return snd_pcm_lib_free_pages(substream); 1901 } 1902 1903 static void pcm_mmap_prepare(struct snd_pcm_substream *substream, 1904 struct vm_area_struct *area) 1905 { 1906 #ifdef CONFIG_X86 1907 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1908 struct azx *chip = apcm->chip; 1909 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA) 1910 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); 1911 #endif 1912 } 1913 1914 static const struct hdac_io_ops pci_hda_io_ops = { 1915 .reg_writel = pci_azx_writel, 1916 .reg_readl = pci_azx_readl, 1917 .reg_writew = pci_azx_writew, 1918 .reg_readw = pci_azx_readw, 1919 .reg_writeb = pci_azx_writeb, 1920 .reg_readb = pci_azx_readb, 1921 .dma_alloc_pages = dma_alloc_pages, 1922 .dma_free_pages = dma_free_pages, 1923 }; 1924 1925 static const struct hda_controller_ops pci_hda_ops = { 1926 .disable_msi_reset_irq = disable_msi_reset_irq, 1927 .substream_alloc_pages = substream_alloc_pages, 1928 .substream_free_pages = substream_free_pages, 1929 .pcm_mmap_prepare = pcm_mmap_prepare, 1930 .position_check = azx_position_check, 1931 .link_power = azx_intel_link_power, 1932 }; 1933 1934 static int azx_probe(struct pci_dev *pci, 1935 const struct pci_device_id *pci_id) 1936 { 1937 static int dev; 1938 struct snd_card *card; 1939 struct hda_intel *hda; 1940 struct azx *chip; 1941 bool schedule_probe; 1942 int err; 1943 1944 if (dev >= SNDRV_CARDS) 1945 return -ENODEV; 1946 if (!enable[dev]) { 1947 dev++; 1948 return -ENOENT; 1949 } 1950 1951 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 1952 0, &card); 1953 if (err < 0) { 1954 dev_err(&pci->dev, "Error creating card!\n"); 1955 return err; 1956 } 1957 1958 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 1959 if (err < 0) 1960 goto out_free; 1961 card->private_data = chip; 1962 hda = container_of(chip, struct hda_intel, chip); 1963 1964 pci_set_drvdata(pci, card); 1965 1966 err = register_vga_switcheroo(chip); 1967 if (err < 0) { 1968 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 1969 goto out_free; 1970 } 1971 1972 if (check_hdmi_disabled(pci)) { 1973 dev_info(card->dev, "VGA controller is disabled\n"); 1974 dev_info(card->dev, "Delaying initialization\n"); 1975 chip->disabled = true; 1976 } 1977 1978 schedule_probe = !chip->disabled; 1979 1980 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1981 if (patch[dev] && *patch[dev]) { 1982 dev_info(card->dev, "Applying patch firmware '%s'\n", 1983 patch[dev]); 1984 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 1985 &pci->dev, GFP_KERNEL, card, 1986 azx_firmware_cb); 1987 if (err < 0) 1988 goto out_free; 1989 schedule_probe = false; /* continued in azx_firmware_cb() */ 1990 } 1991 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 1992 1993 #ifndef CONFIG_SND_HDA_I915 1994 if (CONTROLLER_IN_GPU(pci)) 1995 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); 1996 #endif 1997 1998 if (schedule_probe) 1999 schedule_work(&hda->probe_work); 2000 2001 dev++; 2002 if (chip->disabled) 2003 complete_all(&hda->probe_wait); 2004 return 0; 2005 2006 out_free: 2007 snd_card_free(card); 2008 return err; 2009 } 2010 2011 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 2012 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 2013 [AZX_DRIVER_NVIDIA] = 8, 2014 [AZX_DRIVER_TERA] = 1, 2015 }; 2016 2017 static int azx_probe_continue(struct azx *chip) 2018 { 2019 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2020 struct hdac_bus *bus = azx_bus(chip); 2021 struct pci_dev *pci = chip->pci; 2022 int dev = chip->dev_index; 2023 int err; 2024 2025 hda->probe_continued = 1; 2026 2027 /* Request display power well for the HDA controller or codec. For 2028 * Haswell/Broadwell, both the display HDA controller and codec need 2029 * this power. For other platforms, like Baytrail/Braswell, only the 2030 * display codec needs the power and it can be released after probe. 2031 */ 2032 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 2033 /* HSW/BDW controllers need this power */ 2034 if (CONTROLLER_IN_GPU(pci)) 2035 hda->need_i915_power = 1; 2036 2037 err = snd_hdac_i915_init(bus); 2038 if (err < 0) { 2039 /* if the controller is bound only with HDMI/DP 2040 * (for HSW and BDW), we need to abort the probe; 2041 * for other chips, still continue probing as other 2042 * codecs can be on the same link. 2043 */ 2044 if (CONTROLLER_IN_GPU(pci)) { 2045 dev_err(chip->card->dev, 2046 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); 2047 goto out_free; 2048 } else 2049 goto skip_i915; 2050 } 2051 2052 err = snd_hdac_display_power(bus, true); 2053 if (err < 0) { 2054 dev_err(chip->card->dev, 2055 "Cannot turn on display power on i915\n"); 2056 goto i915_power_fail; 2057 } 2058 } 2059 2060 skip_i915: 2061 err = azx_first_init(chip); 2062 if (err < 0) 2063 goto out_free; 2064 2065 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2066 chip->beep_mode = beep_mode[dev]; 2067 #endif 2068 2069 /* create codec instances */ 2070 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2071 if (err < 0) 2072 goto out_free; 2073 2074 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2075 if (chip->fw) { 2076 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2077 chip->fw->data); 2078 if (err < 0) 2079 goto out_free; 2080 #ifndef CONFIG_PM 2081 release_firmware(chip->fw); /* no longer needed */ 2082 chip->fw = NULL; 2083 #endif 2084 } 2085 #endif 2086 if ((probe_only[dev] & 1) == 0) { 2087 err = azx_codec_configure(chip); 2088 if (err < 0) 2089 goto out_free; 2090 } 2091 2092 err = snd_card_register(chip->card); 2093 if (err < 0) 2094 goto out_free; 2095 2096 chip->running = 1; 2097 azx_add_card_list(chip); 2098 snd_hda_set_power_save(&chip->bus, power_save * 1000); 2099 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo) 2100 pm_runtime_put_autosuspend(&pci->dev); 2101 2102 out_free: 2103 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL 2104 && !hda->need_i915_power) 2105 snd_hdac_display_power(bus, false); 2106 2107 i915_power_fail: 2108 if (err < 0) 2109 hda->init_failed = 1; 2110 complete_all(&hda->probe_wait); 2111 return err; 2112 } 2113 2114 static void azx_remove(struct pci_dev *pci) 2115 { 2116 struct snd_card *card = pci_get_drvdata(pci); 2117 struct azx *chip; 2118 struct hda_intel *hda; 2119 2120 if (card) { 2121 /* cancel the pending probing work */ 2122 chip = card->private_data; 2123 hda = container_of(chip, struct hda_intel, chip); 2124 cancel_work_sync(&hda->probe_work); 2125 2126 snd_card_free(card); 2127 } 2128 } 2129 2130 static void azx_shutdown(struct pci_dev *pci) 2131 { 2132 struct snd_card *card = pci_get_drvdata(pci); 2133 struct azx *chip; 2134 2135 if (!card) 2136 return; 2137 chip = card->private_data; 2138 if (chip && chip->running) 2139 azx_stop_chip(chip); 2140 } 2141 2142 /* PCI IDs */ 2143 static const struct pci_device_id azx_ids[] = { 2144 /* CPT */ 2145 { PCI_DEVICE(0x8086, 0x1c20), 2146 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2147 /* PBG */ 2148 { PCI_DEVICE(0x8086, 0x1d20), 2149 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2150 /* Panther Point */ 2151 { PCI_DEVICE(0x8086, 0x1e20), 2152 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2153 /* Lynx Point */ 2154 { PCI_DEVICE(0x8086, 0x8c20), 2155 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2156 /* 9 Series */ 2157 { PCI_DEVICE(0x8086, 0x8ca0), 2158 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2159 /* Wellsburg */ 2160 { PCI_DEVICE(0x8086, 0x8d20), 2161 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2162 { PCI_DEVICE(0x8086, 0x8d21), 2163 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2164 /* Lewisburg */ 2165 { PCI_DEVICE(0x8086, 0xa1f0), 2166 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2167 { PCI_DEVICE(0x8086, 0xa270), 2168 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2169 /* Lynx Point-LP */ 2170 { PCI_DEVICE(0x8086, 0x9c20), 2171 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2172 /* Lynx Point-LP */ 2173 { PCI_DEVICE(0x8086, 0x9c21), 2174 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2175 /* Wildcat Point-LP */ 2176 { PCI_DEVICE(0x8086, 0x9ca0), 2177 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2178 /* Sunrise Point */ 2179 { PCI_DEVICE(0x8086, 0xa170), 2180 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2181 /* Sunrise Point-LP */ 2182 { PCI_DEVICE(0x8086, 0x9d70), 2183 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2184 /* Broxton-P(Apollolake) */ 2185 { PCI_DEVICE(0x8086, 0x5a98), 2186 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON }, 2187 /* Broxton-T */ 2188 { PCI_DEVICE(0x8086, 0x1a98), 2189 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON }, 2190 /* Haswell */ 2191 { PCI_DEVICE(0x8086, 0x0a0c), 2192 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2193 { PCI_DEVICE(0x8086, 0x0c0c), 2194 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2195 { PCI_DEVICE(0x8086, 0x0d0c), 2196 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2197 /* Broadwell */ 2198 { PCI_DEVICE(0x8086, 0x160c), 2199 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 2200 /* 5 Series/3400 */ 2201 { PCI_DEVICE(0x8086, 0x3b56), 2202 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2203 /* Poulsbo */ 2204 { PCI_DEVICE(0x8086, 0x811b), 2205 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2206 /* Oaktrail */ 2207 { PCI_DEVICE(0x8086, 0x080a), 2208 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2209 /* BayTrail */ 2210 { PCI_DEVICE(0x8086, 0x0f04), 2211 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL }, 2212 /* Braswell */ 2213 { PCI_DEVICE(0x8086, 0x2284), 2214 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL }, 2215 /* ICH6 */ 2216 { PCI_DEVICE(0x8086, 0x2668), 2217 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2218 /* ICH7 */ 2219 { PCI_DEVICE(0x8086, 0x27d8), 2220 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2221 /* ESB2 */ 2222 { PCI_DEVICE(0x8086, 0x269a), 2223 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2224 /* ICH8 */ 2225 { PCI_DEVICE(0x8086, 0x284b), 2226 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2227 /* ICH9 */ 2228 { PCI_DEVICE(0x8086, 0x293e), 2229 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2230 /* ICH9 */ 2231 { PCI_DEVICE(0x8086, 0x293f), 2232 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2233 /* ICH10 */ 2234 { PCI_DEVICE(0x8086, 0x3a3e), 2235 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2236 /* ICH10 */ 2237 { PCI_DEVICE(0x8086, 0x3a6e), 2238 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2239 /* Generic Intel */ 2240 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2241 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2242 .class_mask = 0xffffff, 2243 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2244 /* ATI SB 450/600/700/800/900 */ 2245 { PCI_DEVICE(0x1002, 0x437b), 2246 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2247 { PCI_DEVICE(0x1002, 0x4383), 2248 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2249 /* AMD Hudson */ 2250 { PCI_DEVICE(0x1022, 0x780d), 2251 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2252 /* ATI HDMI */ 2253 { PCI_DEVICE(0x1002, 0x1308), 2254 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2255 { PCI_DEVICE(0x1002, 0x157a), 2256 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2257 { PCI_DEVICE(0x1002, 0x793b), 2258 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2259 { PCI_DEVICE(0x1002, 0x7919), 2260 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2261 { PCI_DEVICE(0x1002, 0x960f), 2262 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2263 { PCI_DEVICE(0x1002, 0x970f), 2264 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2265 { PCI_DEVICE(0x1002, 0x9840), 2266 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2267 { PCI_DEVICE(0x1002, 0xaa00), 2268 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2269 { PCI_DEVICE(0x1002, 0xaa08), 2270 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2271 { PCI_DEVICE(0x1002, 0xaa10), 2272 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2273 { PCI_DEVICE(0x1002, 0xaa18), 2274 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2275 { PCI_DEVICE(0x1002, 0xaa20), 2276 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2277 { PCI_DEVICE(0x1002, 0xaa28), 2278 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2279 { PCI_DEVICE(0x1002, 0xaa30), 2280 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2281 { PCI_DEVICE(0x1002, 0xaa38), 2282 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2283 { PCI_DEVICE(0x1002, 0xaa40), 2284 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2285 { PCI_DEVICE(0x1002, 0xaa48), 2286 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2287 { PCI_DEVICE(0x1002, 0xaa50), 2288 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2289 { PCI_DEVICE(0x1002, 0xaa58), 2290 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2291 { PCI_DEVICE(0x1002, 0xaa60), 2292 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2293 { PCI_DEVICE(0x1002, 0xaa68), 2294 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2295 { PCI_DEVICE(0x1002, 0xaa80), 2296 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2297 { PCI_DEVICE(0x1002, 0xaa88), 2298 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2299 { PCI_DEVICE(0x1002, 0xaa90), 2300 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2301 { PCI_DEVICE(0x1002, 0xaa98), 2302 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2303 { PCI_DEVICE(0x1002, 0x9902), 2304 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2305 { PCI_DEVICE(0x1002, 0xaaa0), 2306 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2307 { PCI_DEVICE(0x1002, 0xaaa8), 2308 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2309 { PCI_DEVICE(0x1002, 0xaab0), 2310 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2311 { PCI_DEVICE(0x1002, 0xaac0), 2312 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2313 { PCI_DEVICE(0x1002, 0xaac8), 2314 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2315 { PCI_DEVICE(0x1002, 0xaad8), 2316 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2317 { PCI_DEVICE(0x1002, 0xaae8), 2318 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2319 { PCI_DEVICE(0x1002, 0xaae0), 2320 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2321 { PCI_DEVICE(0x1002, 0xaaf0), 2322 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2323 /* VIA VT8251/VT8237A */ 2324 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2325 /* VIA GFX VT7122/VX900 */ 2326 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2327 /* VIA GFX VT6122/VX11 */ 2328 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2329 /* SIS966 */ 2330 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2331 /* ULI M5461 */ 2332 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2333 /* NVIDIA MCP */ 2334 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2335 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2336 .class_mask = 0xffffff, 2337 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2338 /* Teradici */ 2339 { PCI_DEVICE(0x6549, 0x1200), 2340 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2341 { PCI_DEVICE(0x6549, 0x2200), 2342 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2343 /* Creative X-Fi (CA0110-IBG) */ 2344 /* CTHDA chips */ 2345 { PCI_DEVICE(0x1102, 0x0010), 2346 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2347 { PCI_DEVICE(0x1102, 0x0012), 2348 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2349 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2350 /* the following entry conflicts with snd-ctxfi driver, 2351 * as ctxfi driver mutates from HD-audio to native mode with 2352 * a special command sequence. 2353 */ 2354 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2355 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2356 .class_mask = 0xffffff, 2357 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2358 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2359 #else 2360 /* this entry seems still valid -- i.e. without emu20kx chip */ 2361 { PCI_DEVICE(0x1102, 0x0009), 2362 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2363 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2364 #endif 2365 /* CM8888 */ 2366 { PCI_DEVICE(0x13f6, 0x5011), 2367 .driver_data = AZX_DRIVER_CMEDIA | 2368 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2369 /* Vortex86MX */ 2370 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2371 /* VMware HDAudio */ 2372 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2373 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2374 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2375 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2376 .class_mask = 0xffffff, 2377 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2378 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2379 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2380 .class_mask = 0xffffff, 2381 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2382 { 0, } 2383 }; 2384 MODULE_DEVICE_TABLE(pci, azx_ids); 2385 2386 /* pci_driver definition */ 2387 static struct pci_driver azx_driver = { 2388 .name = KBUILD_MODNAME, 2389 .id_table = azx_ids, 2390 .probe = azx_probe, 2391 .remove = azx_remove, 2392 .shutdown = azx_shutdown, 2393 .driver = { 2394 .pm = AZX_PM_OPS, 2395 }, 2396 }; 2397 2398 module_pci_driver(azx_driver); 2399