1 /* 2 * 3 * hda_intel.c - Implementation of primary alsa driver code base 4 * for Intel HD Audio. 5 * 6 * Copyright(c) 2004 Intel Corporation. All rights reserved. 7 * 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the Free 13 * Software Foundation; either version 2 of the License, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 * 21 * You should have received a copy of the GNU General Public License along with 22 * this program; if not, write to the Free Software Foundation, Inc., 59 23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 24 * 25 * CONTACTS: 26 * 27 * Matt Jared matt.jared@intel.com 28 * Andy Kopp andy.kopp@intel.com 29 * Dan Kogan dan.d.kogan@intel.com 30 * 31 * CHANGES: 32 * 33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 34 * 35 */ 36 37 #include <linux/delay.h> 38 #include <linux/interrupt.h> 39 #include <linux/kernel.h> 40 #include <linux/module.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/moduleparam.h> 43 #include <linux/init.h> 44 #include <linux/slab.h> 45 #include <linux/pci.h> 46 #include <linux/mutex.h> 47 #include <linux/reboot.h> 48 #include <linux/io.h> 49 #include <linux/pm_runtime.h> 50 #include <linux/clocksource.h> 51 #include <linux/time.h> 52 #include <linux/completion.h> 53 54 #ifdef CONFIG_X86 55 /* for snoop control */ 56 #include <asm/pgtable.h> 57 #include <asm/cacheflush.h> 58 #endif 59 #include <sound/core.h> 60 #include <sound/initval.h> 61 #include <linux/vgaarb.h> 62 #include <linux/vga_switcheroo.h> 63 #include <linux/firmware.h> 64 #include "hda_codec.h" 65 #include "hda_i915.h" 66 67 68 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 69 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 70 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 71 static char *model[SNDRV_CARDS]; 72 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 73 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 74 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 75 static int probe_only[SNDRV_CARDS]; 76 static int jackpoll_ms[SNDRV_CARDS]; 77 static bool single_cmd; 78 static int enable_msi = -1; 79 #ifdef CONFIG_SND_HDA_PATCH_LOADER 80 static char *patch[SNDRV_CARDS]; 81 #endif 82 #ifdef CONFIG_SND_HDA_INPUT_BEEP 83 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 84 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 85 #endif 86 87 module_param_array(index, int, NULL, 0444); 88 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 89 module_param_array(id, charp, NULL, 0444); 90 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 91 module_param_array(enable, bool, NULL, 0444); 92 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 93 module_param_array(model, charp, NULL, 0444); 94 MODULE_PARM_DESC(model, "Use the given board model."); 95 module_param_array(position_fix, int, NULL, 0444); 96 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 97 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO)."); 98 module_param_array(bdl_pos_adj, int, NULL, 0644); 99 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 100 module_param_array(probe_mask, int, NULL, 0444); 101 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 102 module_param_array(probe_only, int, NULL, 0444); 103 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 104 module_param_array(jackpoll_ms, int, NULL, 0444); 105 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 106 module_param(single_cmd, bool, 0444); 107 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 108 "(for debugging only)."); 109 module_param(enable_msi, bint, 0444); 110 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 111 #ifdef CONFIG_SND_HDA_PATCH_LOADER 112 module_param_array(patch, charp, NULL, 0444); 113 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 114 #endif 115 #ifdef CONFIG_SND_HDA_INPUT_BEEP 116 module_param_array(beep_mode, bool, NULL, 0444); 117 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 118 "(0=off, 1=on) (default=1)."); 119 #endif 120 121 #ifdef CONFIG_PM 122 static int param_set_xint(const char *val, const struct kernel_param *kp); 123 static struct kernel_param_ops param_ops_xint = { 124 .set = param_set_xint, 125 .get = param_get_int, 126 }; 127 #define param_check_xint param_check_int 128 129 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 130 module_param(power_save, xint, 0644); 131 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 132 "(in second, 0 = disable)."); 133 134 /* reset the HD-audio controller in power save mode. 135 * this may give more power-saving, but will take longer time to 136 * wake up. 137 */ 138 static bool power_save_controller = 1; 139 module_param(power_save_controller, bool, 0644); 140 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 141 #endif /* CONFIG_PM */ 142 143 static int align_buffer_size = -1; 144 module_param(align_buffer_size, bint, 0644); 145 MODULE_PARM_DESC(align_buffer_size, 146 "Force buffer and period sizes to be multiple of 128 bytes."); 147 148 #ifdef CONFIG_X86 149 static bool hda_snoop = true; 150 module_param_named(snoop, hda_snoop, bool, 0444); 151 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 152 #define azx_snoop(chip) (chip)->snoop 153 #else 154 #define hda_snoop true 155 #define azx_snoop(chip) true 156 #endif 157 158 159 MODULE_LICENSE("GPL"); 160 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 161 "{Intel, ICH6M}," 162 "{Intel, ICH7}," 163 "{Intel, ESB2}," 164 "{Intel, ICH8}," 165 "{Intel, ICH9}," 166 "{Intel, ICH10}," 167 "{Intel, PCH}," 168 "{Intel, CPT}," 169 "{Intel, PPT}," 170 "{Intel, LPT}," 171 "{Intel, LPT_LP}," 172 "{Intel, HPT}," 173 "{Intel, PBG}," 174 "{Intel, SCH}," 175 "{ATI, SB450}," 176 "{ATI, SB600}," 177 "{ATI, RS600}," 178 "{ATI, RS690}," 179 "{ATI, RS780}," 180 "{ATI, R600}," 181 "{ATI, RV630}," 182 "{ATI, RV610}," 183 "{ATI, RV670}," 184 "{ATI, RV635}," 185 "{ATI, RV620}," 186 "{ATI, RV770}," 187 "{VIA, VT8251}," 188 "{VIA, VT8237A}," 189 "{SiS, SIS966}," 190 "{ULI, M5461}}"); 191 MODULE_DESCRIPTION("Intel HDA driver"); 192 193 #ifdef CONFIG_SND_VERBOSE_PRINTK 194 #define SFX /* nop */ 195 #else 196 #define SFX "hda-intel " 197 #endif 198 199 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 200 #ifdef CONFIG_SND_HDA_CODEC_HDMI 201 #define SUPPORT_VGA_SWITCHEROO 202 #endif 203 #endif 204 205 206 /* 207 * registers 208 */ 209 #define ICH6_REG_GCAP 0x00 210 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */ 211 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */ 212 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */ 213 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */ 214 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */ 215 #define ICH6_REG_VMIN 0x02 216 #define ICH6_REG_VMAJ 0x03 217 #define ICH6_REG_OUTPAY 0x04 218 #define ICH6_REG_INPAY 0x06 219 #define ICH6_REG_GCTL 0x08 220 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */ 221 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */ 222 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */ 223 #define ICH6_REG_WAKEEN 0x0c 224 #define ICH6_REG_STATESTS 0x0e 225 #define ICH6_REG_GSTS 0x10 226 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */ 227 #define ICH6_REG_INTCTL 0x20 228 #define ICH6_REG_INTSTS 0x24 229 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */ 230 #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */ 231 #define ICH6_REG_SSYNC 0x38 232 #define ICH6_REG_CORBLBASE 0x40 233 #define ICH6_REG_CORBUBASE 0x44 234 #define ICH6_REG_CORBWP 0x48 235 #define ICH6_REG_CORBRP 0x4a 236 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */ 237 #define ICH6_REG_CORBCTL 0x4c 238 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */ 239 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */ 240 #define ICH6_REG_CORBSTS 0x4d 241 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */ 242 #define ICH6_REG_CORBSIZE 0x4e 243 244 #define ICH6_REG_RIRBLBASE 0x50 245 #define ICH6_REG_RIRBUBASE 0x54 246 #define ICH6_REG_RIRBWP 0x58 247 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */ 248 #define ICH6_REG_RINTCNT 0x5a 249 #define ICH6_REG_RIRBCTL 0x5c 250 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */ 251 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */ 252 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */ 253 #define ICH6_REG_RIRBSTS 0x5d 254 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */ 255 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */ 256 #define ICH6_REG_RIRBSIZE 0x5e 257 258 #define ICH6_REG_IC 0x60 259 #define ICH6_REG_IR 0x64 260 #define ICH6_REG_IRS 0x68 261 #define ICH6_IRS_VALID (1<<1) 262 #define ICH6_IRS_BUSY (1<<0) 263 264 #define ICH6_REG_DPLBASE 0x70 265 #define ICH6_REG_DPUBASE 0x74 266 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */ 267 268 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ 269 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; 270 271 /* stream register offsets from stream base */ 272 #define ICH6_REG_SD_CTL 0x00 273 #define ICH6_REG_SD_STS 0x03 274 #define ICH6_REG_SD_LPIB 0x04 275 #define ICH6_REG_SD_CBL 0x08 276 #define ICH6_REG_SD_LVI 0x0c 277 #define ICH6_REG_SD_FIFOW 0x0e 278 #define ICH6_REG_SD_FIFOSIZE 0x10 279 #define ICH6_REG_SD_FORMAT 0x12 280 #define ICH6_REG_SD_BDLPL 0x18 281 #define ICH6_REG_SD_BDLPU 0x1c 282 283 /* PCI space */ 284 #define ICH6_PCIREG_TCSEL 0x44 285 286 /* 287 * other constants 288 */ 289 290 /* max number of SDs */ 291 /* ICH, ATI and VIA have 4 playback and 4 capture */ 292 #define ICH6_NUM_CAPTURE 4 293 #define ICH6_NUM_PLAYBACK 4 294 295 /* ULI has 6 playback and 5 capture */ 296 #define ULI_NUM_CAPTURE 5 297 #define ULI_NUM_PLAYBACK 6 298 299 /* ATI HDMI has 1 playback and 0 capture */ 300 #define ATIHDMI_NUM_CAPTURE 0 301 #define ATIHDMI_NUM_PLAYBACK 1 302 303 /* TERA has 4 playback and 3 capture */ 304 #define TERA_NUM_CAPTURE 3 305 #define TERA_NUM_PLAYBACK 4 306 307 /* this number is statically defined for simplicity */ 308 #define MAX_AZX_DEV 16 309 310 /* max number of fragments - we may use more if allocating more pages for BDL */ 311 #define BDL_SIZE 4096 312 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16) 313 #define AZX_MAX_FRAG 32 314 /* max buffer size - no h/w limit, you can increase as you like */ 315 #define AZX_MAX_BUF_SIZE (1024*1024*1024) 316 317 /* RIRB int mask: overrun[2], response[0] */ 318 #define RIRB_INT_RESPONSE 0x01 319 #define RIRB_INT_OVERRUN 0x04 320 #define RIRB_INT_MASK 0x05 321 322 /* STATESTS int mask: S3,SD2,SD1,SD0 */ 323 #define AZX_MAX_CODECS 8 324 #define AZX_DEFAULT_CODECS 4 325 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1) 326 327 /* SD_CTL bits */ 328 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ 329 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ 330 #define SD_CTL_STRIPE (3 << 16) /* stripe control */ 331 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */ 332 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */ 333 #define SD_CTL_STREAM_TAG_MASK (0xf << 20) 334 #define SD_CTL_STREAM_TAG_SHIFT 20 335 336 /* SD_CTL and SD_STS */ 337 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ 338 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ 339 #define SD_INT_COMPLETE 0x04 /* completion interrupt */ 340 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\ 341 SD_INT_COMPLETE) 342 343 /* SD_STS */ 344 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */ 345 346 /* INTCTL and INTSTS */ 347 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */ 348 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ 349 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ 350 351 /* below are so far hardcoded - should read registers in future */ 352 #define ICH6_MAX_CORB_ENTRIES 256 353 #define ICH6_MAX_RIRB_ENTRIES 256 354 355 /* position fix mode */ 356 enum { 357 POS_FIX_AUTO, 358 POS_FIX_LPIB, 359 POS_FIX_POSBUF, 360 POS_FIX_VIACOMBO, 361 POS_FIX_COMBO, 362 }; 363 364 /* Defines for ATI HD Audio support in SB450 south bridge */ 365 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 366 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 367 368 /* Defines for Nvidia HDA support */ 369 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 370 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 371 #define NVIDIA_HDA_ISTRM_COH 0x4d 372 #define NVIDIA_HDA_OSTRM_COH 0x4c 373 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 374 375 /* Defines for Intel SCH HDA snoop control */ 376 #define INTEL_SCH_HDA_DEVC 0x78 377 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 378 379 /* Define IN stream 0 FIFO size offset in VIA controller */ 380 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 381 /* Define VIA HD Audio Device ID*/ 382 #define VIA_HDAC_DEVICE_ID 0x3288 383 384 /* HD Audio class code */ 385 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403 386 387 /* 388 */ 389 390 struct azx_dev { 391 struct snd_dma_buffer bdl; /* BDL buffer */ 392 u32 *posbuf; /* position buffer pointer */ 393 394 unsigned int bufsize; /* size of the play buffer in bytes */ 395 unsigned int period_bytes; /* size of the period in bytes */ 396 unsigned int frags; /* number for period in the play buffer */ 397 unsigned int fifo_size; /* FIFO size */ 398 unsigned long start_wallclk; /* start + minimum wallclk */ 399 unsigned long period_wallclk; /* wallclk for period */ 400 401 void __iomem *sd_addr; /* stream descriptor pointer */ 402 403 u32 sd_int_sta_mask; /* stream int status mask */ 404 405 /* pcm support */ 406 struct snd_pcm_substream *substream; /* assigned substream, 407 * set in PCM open 408 */ 409 unsigned int format_val; /* format value to be set in the 410 * controller and the codec 411 */ 412 unsigned char stream_tag; /* assigned stream */ 413 unsigned char index; /* stream index */ 414 int assigned_key; /* last device# key assigned to */ 415 416 unsigned int opened :1; 417 unsigned int running :1; 418 unsigned int irq_pending :1; 419 unsigned int prepared:1; 420 unsigned int locked:1; 421 /* 422 * For VIA: 423 * A flag to ensure DMA position is 0 424 * when link position is not greater than FIFO size 425 */ 426 unsigned int insufficient :1; 427 unsigned int wc_marked:1; 428 unsigned int no_period_wakeup:1; 429 430 struct timecounter azx_tc; 431 struct cyclecounter azx_cc; 432 433 #ifdef CONFIG_SND_HDA_DSP_LOADER 434 struct mutex dsp_mutex; 435 #endif 436 }; 437 438 /* DSP lock helpers */ 439 #ifdef CONFIG_SND_HDA_DSP_LOADER 440 #define dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex) 441 #define dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex) 442 #define dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex) 443 #define dsp_is_locked(dev) ((dev)->locked) 444 #else 445 #define dsp_lock_init(dev) do {} while (0) 446 #define dsp_lock(dev) do {} while (0) 447 #define dsp_unlock(dev) do {} while (0) 448 #define dsp_is_locked(dev) 0 449 #endif 450 451 /* CORB/RIRB */ 452 struct azx_rb { 453 u32 *buf; /* CORB/RIRB buffer 454 * Each CORB entry is 4byte, RIRB is 8byte 455 */ 456 dma_addr_t addr; /* physical address of CORB/RIRB buffer */ 457 /* for RIRB */ 458 unsigned short rp, wp; /* read/write pointers */ 459 int cmds[AZX_MAX_CODECS]; /* number of pending requests */ 460 u32 res[AZX_MAX_CODECS]; /* last read value */ 461 }; 462 463 struct azx_pcm { 464 struct azx *chip; 465 struct snd_pcm *pcm; 466 struct hda_codec *codec; 467 struct hda_pcm_stream *hinfo[2]; 468 struct list_head list; 469 }; 470 471 struct azx { 472 struct snd_card *card; 473 struct pci_dev *pci; 474 int dev_index; 475 476 /* chip type specific */ 477 int driver_type; 478 unsigned int driver_caps; 479 int playback_streams; 480 int playback_index_offset; 481 int capture_streams; 482 int capture_index_offset; 483 int num_streams; 484 485 /* pci resources */ 486 unsigned long addr; 487 void __iomem *remap_addr; 488 int irq; 489 490 /* locks */ 491 spinlock_t reg_lock; 492 struct mutex open_mutex; 493 struct completion probe_wait; 494 495 /* streams (x num_streams) */ 496 struct azx_dev *azx_dev; 497 498 /* PCM */ 499 struct list_head pcm_list; /* azx_pcm list */ 500 501 /* HD codec */ 502 unsigned short codec_mask; 503 int codec_probe_mask; /* copied from probe_mask option */ 504 struct hda_bus *bus; 505 unsigned int beep_mode; 506 507 /* CORB/RIRB */ 508 struct azx_rb corb; 509 struct azx_rb rirb; 510 511 /* CORB/RIRB and position buffers */ 512 struct snd_dma_buffer rb; 513 struct snd_dma_buffer posbuf; 514 515 #ifdef CONFIG_SND_HDA_PATCH_LOADER 516 const struct firmware *fw; 517 #endif 518 519 /* flags */ 520 int position_fix[2]; /* for both playback/capture streams */ 521 int poll_count; 522 unsigned int running :1; 523 unsigned int initialized :1; 524 unsigned int single_cmd :1; 525 unsigned int polling_mode :1; 526 unsigned int msi :1; 527 unsigned int irq_pending_warned :1; 528 unsigned int probing :1; /* codec probing phase */ 529 unsigned int snoop:1; 530 unsigned int align_buffer_size:1; 531 unsigned int region_requested:1; 532 533 /* VGA-switcheroo setup */ 534 unsigned int use_vga_switcheroo:1; 535 unsigned int vga_switcheroo_registered:1; 536 unsigned int init_failed:1; /* delayed init failed */ 537 unsigned int disabled:1; /* disabled by VGA-switcher */ 538 539 /* for debugging */ 540 unsigned int last_cmd[AZX_MAX_CODECS]; 541 542 /* for pending irqs */ 543 struct work_struct irq_pending_work; 544 545 #ifdef CONFIG_SND_HDA_I915 546 struct work_struct probe_work; 547 #endif 548 549 /* reboot notifier (for mysterious hangup problem at power-down) */ 550 struct notifier_block reboot_notifier; 551 552 /* card list (for power_save trigger) */ 553 struct list_head list; 554 555 #ifdef CONFIG_SND_HDA_DSP_LOADER 556 struct azx_dev saved_azx_dev; 557 #endif 558 559 /* secondary power domain for hdmi audio under vga device */ 560 struct dev_pm_domain hdmi_pm_domain; 561 }; 562 563 #define CREATE_TRACE_POINTS 564 #include "hda_intel_trace.h" 565 566 /* driver types */ 567 enum { 568 AZX_DRIVER_ICH, 569 AZX_DRIVER_PCH, 570 AZX_DRIVER_SCH, 571 AZX_DRIVER_ATI, 572 AZX_DRIVER_ATIHDMI, 573 AZX_DRIVER_ATIHDMI_NS, 574 AZX_DRIVER_VIA, 575 AZX_DRIVER_SIS, 576 AZX_DRIVER_ULI, 577 AZX_DRIVER_NVIDIA, 578 AZX_DRIVER_TERA, 579 AZX_DRIVER_CTX, 580 AZX_DRIVER_CTHDA, 581 AZX_DRIVER_GENERIC, 582 AZX_NUM_DRIVERS, /* keep this as last entry */ 583 }; 584 585 /* driver quirks (capabilities) */ 586 /* bits 0-7 are used for indicating driver type */ 587 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */ 588 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */ 589 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */ 590 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */ 591 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */ 592 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */ 593 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */ 594 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */ 595 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */ 596 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */ 597 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */ 598 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */ 599 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */ 600 #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */ 601 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */ 602 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */ 603 #define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */ 604 #define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */ 605 #define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 power well support */ 606 607 /* quirks for Intel PCH */ 608 #define AZX_DCAPS_INTEL_PCH_NOPM \ 609 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \ 610 AZX_DCAPS_COUNT_LPIB_DELAY) 611 612 #define AZX_DCAPS_INTEL_PCH \ 613 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME) 614 615 /* quirks for ATI SB / AMD Hudson */ 616 #define AZX_DCAPS_PRESET_ATI_SB \ 617 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \ 618 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB) 619 620 /* quirks for ATI/AMD HDMI */ 621 #define AZX_DCAPS_PRESET_ATI_HDMI \ 622 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB) 623 624 /* quirks for Nvidia */ 625 #define AZX_DCAPS_PRESET_NVIDIA \ 626 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\ 627 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT) 628 629 #define AZX_DCAPS_PRESET_CTHDA \ 630 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY) 631 632 /* 633 * VGA-switcher support 634 */ 635 #ifdef SUPPORT_VGA_SWITCHEROO 636 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 637 #else 638 #define use_vga_switcheroo(chip) 0 639 #endif 640 641 static char *driver_short_names[] = { 642 [AZX_DRIVER_ICH] = "HDA Intel", 643 [AZX_DRIVER_PCH] = "HDA Intel PCH", 644 [AZX_DRIVER_SCH] = "HDA Intel MID", 645 [AZX_DRIVER_ATI] = "HDA ATI SB", 646 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 647 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 648 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 649 [AZX_DRIVER_SIS] = "HDA SIS966", 650 [AZX_DRIVER_ULI] = "HDA ULI M5461", 651 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 652 [AZX_DRIVER_TERA] = "HDA Teradici", 653 [AZX_DRIVER_CTX] = "HDA Creative", 654 [AZX_DRIVER_CTHDA] = "HDA Creative", 655 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 656 }; 657 658 /* 659 * macros for easy use 660 */ 661 #define azx_writel(chip,reg,value) \ 662 writel(value, (chip)->remap_addr + ICH6_REG_##reg) 663 #define azx_readl(chip,reg) \ 664 readl((chip)->remap_addr + ICH6_REG_##reg) 665 #define azx_writew(chip,reg,value) \ 666 writew(value, (chip)->remap_addr + ICH6_REG_##reg) 667 #define azx_readw(chip,reg) \ 668 readw((chip)->remap_addr + ICH6_REG_##reg) 669 #define azx_writeb(chip,reg,value) \ 670 writeb(value, (chip)->remap_addr + ICH6_REG_##reg) 671 #define azx_readb(chip,reg) \ 672 readb((chip)->remap_addr + ICH6_REG_##reg) 673 674 #define azx_sd_writel(dev,reg,value) \ 675 writel(value, (dev)->sd_addr + ICH6_REG_##reg) 676 #define azx_sd_readl(dev,reg) \ 677 readl((dev)->sd_addr + ICH6_REG_##reg) 678 #define azx_sd_writew(dev,reg,value) \ 679 writew(value, (dev)->sd_addr + ICH6_REG_##reg) 680 #define azx_sd_readw(dev,reg) \ 681 readw((dev)->sd_addr + ICH6_REG_##reg) 682 #define azx_sd_writeb(dev,reg,value) \ 683 writeb(value, (dev)->sd_addr + ICH6_REG_##reg) 684 #define azx_sd_readb(dev,reg) \ 685 readb((dev)->sd_addr + ICH6_REG_##reg) 686 687 /* for pcm support */ 688 #define get_azx_dev(substream) (substream->runtime->private_data) 689 690 #ifdef CONFIG_X86 691 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on) 692 { 693 int pages; 694 695 if (azx_snoop(chip)) 696 return; 697 if (!dmab || !dmab->area || !dmab->bytes) 698 return; 699 700 #ifdef CONFIG_SND_DMA_SGBUF 701 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) { 702 struct snd_sg_buf *sgbuf = dmab->private_data; 703 if (on) 704 set_pages_array_wc(sgbuf->page_table, sgbuf->pages); 705 else 706 set_pages_array_wb(sgbuf->page_table, sgbuf->pages); 707 return; 708 } 709 #endif 710 711 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT; 712 if (on) 713 set_memory_wc((unsigned long)dmab->area, pages); 714 else 715 set_memory_wb((unsigned long)dmab->area, pages); 716 } 717 718 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 719 bool on) 720 { 721 __mark_pages_wc(chip, buf, on); 722 } 723 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 724 struct snd_pcm_substream *substream, bool on) 725 { 726 if (azx_dev->wc_marked != on) { 727 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on); 728 azx_dev->wc_marked = on; 729 } 730 } 731 #else 732 /* NOP for other archs */ 733 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 734 bool on) 735 { 736 } 737 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 738 struct snd_pcm_substream *substream, bool on) 739 { 740 } 741 #endif 742 743 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 744 static int azx_send_cmd(struct hda_bus *bus, unsigned int val); 745 /* 746 * Interface for HD codec 747 */ 748 749 /* 750 * CORB / RIRB interface 751 */ 752 static int azx_alloc_cmd_io(struct azx *chip) 753 { 754 int err; 755 756 /* single page (at least 4096 bytes) must suffice for both ringbuffes */ 757 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, 758 snd_dma_pci_data(chip->pci), 759 PAGE_SIZE, &chip->rb); 760 if (err < 0) { 761 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci)); 762 return err; 763 } 764 mark_pages_wc(chip, &chip->rb, true); 765 return 0; 766 } 767 768 static void azx_init_cmd_io(struct azx *chip) 769 { 770 spin_lock_irq(&chip->reg_lock); 771 /* CORB set up */ 772 chip->corb.addr = chip->rb.addr; 773 chip->corb.buf = (u32 *)chip->rb.area; 774 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr); 775 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr)); 776 777 /* set the corb size to 256 entries (ULI requires explicitly) */ 778 azx_writeb(chip, CORBSIZE, 0x02); 779 /* set the corb write pointer to 0 */ 780 azx_writew(chip, CORBWP, 0); 781 /* reset the corb hw read pointer */ 782 azx_writew(chip, CORBRP, ICH6_CORBRP_RST); 783 /* enable corb dma */ 784 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN); 785 786 /* RIRB set up */ 787 chip->rirb.addr = chip->rb.addr + 2048; 788 chip->rirb.buf = (u32 *)(chip->rb.area + 2048); 789 chip->rirb.wp = chip->rirb.rp = 0; 790 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds)); 791 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr); 792 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr)); 793 794 /* set the rirb size to 256 entries (ULI requires explicitly) */ 795 azx_writeb(chip, RIRBSIZE, 0x02); 796 /* reset the rirb hw write pointer */ 797 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST); 798 /* set N=1, get RIRB response interrupt for new entry */ 799 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) 800 azx_writew(chip, RINTCNT, 0xc0); 801 else 802 azx_writew(chip, RINTCNT, 1); 803 /* enable rirb dma and response irq */ 804 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN); 805 spin_unlock_irq(&chip->reg_lock); 806 } 807 808 static void azx_free_cmd_io(struct azx *chip) 809 { 810 spin_lock_irq(&chip->reg_lock); 811 /* disable ringbuffer DMAs */ 812 azx_writeb(chip, RIRBCTL, 0); 813 azx_writeb(chip, CORBCTL, 0); 814 spin_unlock_irq(&chip->reg_lock); 815 } 816 817 static unsigned int azx_command_addr(u32 cmd) 818 { 819 unsigned int addr = cmd >> 28; 820 821 if (addr >= AZX_MAX_CODECS) { 822 snd_BUG(); 823 addr = 0; 824 } 825 826 return addr; 827 } 828 829 static unsigned int azx_response_addr(u32 res) 830 { 831 unsigned int addr = res & 0xf; 832 833 if (addr >= AZX_MAX_CODECS) { 834 snd_BUG(); 835 addr = 0; 836 } 837 838 return addr; 839 } 840 841 /* send a command */ 842 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val) 843 { 844 struct azx *chip = bus->private_data; 845 unsigned int addr = azx_command_addr(val); 846 unsigned int wp, rp; 847 848 spin_lock_irq(&chip->reg_lock); 849 850 /* add command to corb */ 851 wp = azx_readw(chip, CORBWP); 852 if (wp == 0xffff) { 853 /* something wrong, controller likely turned to D3 */ 854 spin_unlock_irq(&chip->reg_lock); 855 return -EIO; 856 } 857 wp++; 858 wp %= ICH6_MAX_CORB_ENTRIES; 859 860 rp = azx_readw(chip, CORBRP); 861 if (wp == rp) { 862 /* oops, it's full */ 863 spin_unlock_irq(&chip->reg_lock); 864 return -EAGAIN; 865 } 866 867 chip->rirb.cmds[addr]++; 868 chip->corb.buf[wp] = cpu_to_le32(val); 869 azx_writel(chip, CORBWP, wp); 870 871 spin_unlock_irq(&chip->reg_lock); 872 873 return 0; 874 } 875 876 #define ICH6_RIRB_EX_UNSOL_EV (1<<4) 877 878 /* retrieve RIRB entry - called from interrupt handler */ 879 static void azx_update_rirb(struct azx *chip) 880 { 881 unsigned int rp, wp; 882 unsigned int addr; 883 u32 res, res_ex; 884 885 wp = azx_readw(chip, RIRBWP); 886 if (wp == 0xffff) { 887 /* something wrong, controller likely turned to D3 */ 888 return; 889 } 890 891 if (wp == chip->rirb.wp) 892 return; 893 chip->rirb.wp = wp; 894 895 while (chip->rirb.rp != wp) { 896 chip->rirb.rp++; 897 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES; 898 899 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */ 900 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]); 901 res = le32_to_cpu(chip->rirb.buf[rp]); 902 addr = azx_response_addr(res_ex); 903 if (res_ex & ICH6_RIRB_EX_UNSOL_EV) 904 snd_hda_queue_unsol_event(chip->bus, res, res_ex); 905 else if (chip->rirb.cmds[addr]) { 906 chip->rirb.res[addr] = res; 907 smp_wmb(); 908 chip->rirb.cmds[addr]--; 909 } else 910 snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, " 911 "last cmd=%#08x\n", 912 pci_name(chip->pci), 913 res, res_ex, 914 chip->last_cmd[addr]); 915 } 916 } 917 918 /* receive a response */ 919 static unsigned int azx_rirb_get_response(struct hda_bus *bus, 920 unsigned int addr) 921 { 922 struct azx *chip = bus->private_data; 923 unsigned long timeout; 924 unsigned long loopcounter; 925 int do_poll = 0; 926 927 again: 928 timeout = jiffies + msecs_to_jiffies(1000); 929 930 for (loopcounter = 0;; loopcounter++) { 931 if (chip->polling_mode || do_poll) { 932 spin_lock_irq(&chip->reg_lock); 933 azx_update_rirb(chip); 934 spin_unlock_irq(&chip->reg_lock); 935 } 936 if (!chip->rirb.cmds[addr]) { 937 smp_rmb(); 938 bus->rirb_error = 0; 939 940 if (!do_poll) 941 chip->poll_count = 0; 942 return chip->rirb.res[addr]; /* the last value */ 943 } 944 if (time_after(jiffies, timeout)) 945 break; 946 if (bus->needs_damn_long_delay || loopcounter > 3000) 947 msleep(2); /* temporary workaround */ 948 else { 949 udelay(10); 950 cond_resched(); 951 } 952 } 953 954 if (!bus->no_response_fallback) 955 return -1; 956 957 if (!chip->polling_mode && chip->poll_count < 2) { 958 snd_printdd(SFX "%s: azx_get_response timeout, " 959 "polling the codec once: last cmd=0x%08x\n", 960 pci_name(chip->pci), chip->last_cmd[addr]); 961 do_poll = 1; 962 chip->poll_count++; 963 goto again; 964 } 965 966 967 if (!chip->polling_mode) { 968 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, " 969 "switching to polling mode: last cmd=0x%08x\n", 970 pci_name(chip->pci), chip->last_cmd[addr]); 971 chip->polling_mode = 1; 972 goto again; 973 } 974 975 if (chip->msi) { 976 snd_printk(KERN_WARNING SFX "%s: No response from codec, " 977 "disabling MSI: last cmd=0x%08x\n", 978 pci_name(chip->pci), chip->last_cmd[addr]); 979 free_irq(chip->irq, chip); 980 chip->irq = -1; 981 pci_disable_msi(chip->pci); 982 chip->msi = 0; 983 if (azx_acquire_irq(chip, 1) < 0) { 984 bus->rirb_error = 1; 985 return -1; 986 } 987 goto again; 988 } 989 990 if (chip->probing) { 991 /* If this critical timeout happens during the codec probing 992 * phase, this is likely an access to a non-existing codec 993 * slot. Better to return an error and reset the system. 994 */ 995 return -1; 996 } 997 998 /* a fatal communication error; need either to reset or to fallback 999 * to the single_cmd mode 1000 */ 1001 bus->rirb_error = 1; 1002 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) { 1003 bus->response_reset = 1; 1004 return -1; /* give a chance to retry */ 1005 } 1006 1007 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, " 1008 "switching to single_cmd mode: last cmd=0x%08x\n", 1009 chip->last_cmd[addr]); 1010 chip->single_cmd = 1; 1011 bus->response_reset = 0; 1012 /* release CORB/RIRB */ 1013 azx_free_cmd_io(chip); 1014 /* disable unsolicited responses */ 1015 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL); 1016 return -1; 1017 } 1018 1019 /* 1020 * Use the single immediate command instead of CORB/RIRB for simplicity 1021 * 1022 * Note: according to Intel, this is not preferred use. The command was 1023 * intended for the BIOS only, and may get confused with unsolicited 1024 * responses. So, we shouldn't use it for normal operation from the 1025 * driver. 1026 * I left the codes, however, for debugging/testing purposes. 1027 */ 1028 1029 /* receive a response */ 1030 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr) 1031 { 1032 int timeout = 50; 1033 1034 while (timeout--) { 1035 /* check IRV busy bit */ 1036 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) { 1037 /* reuse rirb.res as the response return value */ 1038 chip->rirb.res[addr] = azx_readl(chip, IR); 1039 return 0; 1040 } 1041 udelay(1); 1042 } 1043 if (printk_ratelimit()) 1044 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n", 1045 pci_name(chip->pci), azx_readw(chip, IRS)); 1046 chip->rirb.res[addr] = -1; 1047 return -EIO; 1048 } 1049 1050 /* send a command */ 1051 static int azx_single_send_cmd(struct hda_bus *bus, u32 val) 1052 { 1053 struct azx *chip = bus->private_data; 1054 unsigned int addr = azx_command_addr(val); 1055 int timeout = 50; 1056 1057 bus->rirb_error = 0; 1058 while (timeout--) { 1059 /* check ICB busy bit */ 1060 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) { 1061 /* Clear IRV valid bit */ 1062 azx_writew(chip, IRS, azx_readw(chip, IRS) | 1063 ICH6_IRS_VALID); 1064 azx_writel(chip, IC, val); 1065 azx_writew(chip, IRS, azx_readw(chip, IRS) | 1066 ICH6_IRS_BUSY); 1067 return azx_single_wait_for_response(chip, addr); 1068 } 1069 udelay(1); 1070 } 1071 if (printk_ratelimit()) 1072 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n", 1073 pci_name(chip->pci), azx_readw(chip, IRS), val); 1074 return -EIO; 1075 } 1076 1077 /* receive a response */ 1078 static unsigned int azx_single_get_response(struct hda_bus *bus, 1079 unsigned int addr) 1080 { 1081 struct azx *chip = bus->private_data; 1082 return chip->rirb.res[addr]; 1083 } 1084 1085 /* 1086 * The below are the main callbacks from hda_codec. 1087 * 1088 * They are just the skeleton to call sub-callbacks according to the 1089 * current setting of chip->single_cmd. 1090 */ 1091 1092 /* send a command */ 1093 static int azx_send_cmd(struct hda_bus *bus, unsigned int val) 1094 { 1095 struct azx *chip = bus->private_data; 1096 1097 if (chip->disabled) 1098 return 0; 1099 chip->last_cmd[azx_command_addr(val)] = val; 1100 if (chip->single_cmd) 1101 return azx_single_send_cmd(bus, val); 1102 else 1103 return azx_corb_send_cmd(bus, val); 1104 } 1105 1106 /* get a response */ 1107 static unsigned int azx_get_response(struct hda_bus *bus, 1108 unsigned int addr) 1109 { 1110 struct azx *chip = bus->private_data; 1111 if (chip->disabled) 1112 return 0; 1113 if (chip->single_cmd) 1114 return azx_single_get_response(bus, addr); 1115 else 1116 return azx_rirb_get_response(bus, addr); 1117 } 1118 1119 #ifdef CONFIG_PM 1120 static void azx_power_notify(struct hda_bus *bus, bool power_up); 1121 #endif 1122 1123 #ifdef CONFIG_SND_HDA_DSP_LOADER 1124 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format, 1125 unsigned int byte_size, 1126 struct snd_dma_buffer *bufp); 1127 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start); 1128 static void azx_load_dsp_cleanup(struct hda_bus *bus, 1129 struct snd_dma_buffer *dmab); 1130 #endif 1131 1132 /* enter link reset */ 1133 static void azx_enter_link_reset(struct azx *chip) 1134 { 1135 unsigned long timeout; 1136 1137 /* reset controller */ 1138 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); 1139 1140 timeout = jiffies + msecs_to_jiffies(100); 1141 while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) && 1142 time_before(jiffies, timeout)) 1143 usleep_range(500, 1000); 1144 } 1145 1146 /* exit link reset */ 1147 static void azx_exit_link_reset(struct azx *chip) 1148 { 1149 unsigned long timeout; 1150 1151 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET); 1152 1153 timeout = jiffies + msecs_to_jiffies(100); 1154 while (!azx_readb(chip, GCTL) && 1155 time_before(jiffies, timeout)) 1156 usleep_range(500, 1000); 1157 } 1158 1159 /* reset codec link */ 1160 static int azx_reset(struct azx *chip, int full_reset) 1161 { 1162 if (!full_reset) 1163 goto __skip; 1164 1165 /* clear STATESTS */ 1166 azx_writew(chip, STATESTS, STATESTS_INT_MASK); 1167 1168 /* reset controller */ 1169 azx_enter_link_reset(chip); 1170 1171 /* delay for >= 100us for codec PLL to settle per spec 1172 * Rev 0.9 section 5.5.1 1173 */ 1174 usleep_range(500, 1000); 1175 1176 /* Bring controller out of reset */ 1177 azx_exit_link_reset(chip); 1178 1179 /* Brent Chartrand said to wait >= 540us for codecs to initialize */ 1180 usleep_range(1000, 1200); 1181 1182 __skip: 1183 /* check to see if controller is ready */ 1184 if (!azx_readb(chip, GCTL)) { 1185 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci)); 1186 return -EBUSY; 1187 } 1188 1189 /* Accept unsolicited responses */ 1190 if (!chip->single_cmd) 1191 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | 1192 ICH6_GCTL_UNSOL); 1193 1194 /* detect codecs */ 1195 if (!chip->codec_mask) { 1196 chip->codec_mask = azx_readw(chip, STATESTS); 1197 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask); 1198 } 1199 1200 return 0; 1201 } 1202 1203 1204 /* 1205 * Lowlevel interface 1206 */ 1207 1208 /* enable interrupts */ 1209 static void azx_int_enable(struct azx *chip) 1210 { 1211 /* enable controller CIE and GIE */ 1212 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) | 1213 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN); 1214 } 1215 1216 /* disable interrupts */ 1217 static void azx_int_disable(struct azx *chip) 1218 { 1219 int i; 1220 1221 /* disable interrupts in stream descriptor */ 1222 for (i = 0; i < chip->num_streams; i++) { 1223 struct azx_dev *azx_dev = &chip->azx_dev[i]; 1224 azx_sd_writeb(azx_dev, SD_CTL, 1225 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK); 1226 } 1227 1228 /* disable SIE for all streams */ 1229 azx_writeb(chip, INTCTL, 0); 1230 1231 /* disable controller CIE and GIE */ 1232 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) & 1233 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN)); 1234 } 1235 1236 /* clear interrupts */ 1237 static void azx_int_clear(struct azx *chip) 1238 { 1239 int i; 1240 1241 /* clear stream status */ 1242 for (i = 0; i < chip->num_streams; i++) { 1243 struct azx_dev *azx_dev = &chip->azx_dev[i]; 1244 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); 1245 } 1246 1247 /* clear STATESTS */ 1248 azx_writew(chip, STATESTS, STATESTS_INT_MASK); 1249 1250 /* clear rirb status */ 1251 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); 1252 1253 /* clear int status */ 1254 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM); 1255 } 1256 1257 /* start a stream */ 1258 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev) 1259 { 1260 /* 1261 * Before stream start, initialize parameter 1262 */ 1263 azx_dev->insufficient = 1; 1264 1265 /* enable SIE */ 1266 azx_writel(chip, INTCTL, 1267 azx_readl(chip, INTCTL) | (1 << azx_dev->index)); 1268 /* set DMA start and interrupt mask */ 1269 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | 1270 SD_CTL_DMA_START | SD_INT_MASK); 1271 } 1272 1273 /* stop DMA */ 1274 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev) 1275 { 1276 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & 1277 ~(SD_CTL_DMA_START | SD_INT_MASK)); 1278 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ 1279 } 1280 1281 /* stop a stream */ 1282 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev) 1283 { 1284 azx_stream_clear(chip, azx_dev); 1285 /* disable SIE */ 1286 azx_writel(chip, INTCTL, 1287 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index)); 1288 } 1289 1290 1291 /* 1292 * reset and start the controller registers 1293 */ 1294 static void azx_init_chip(struct azx *chip, int full_reset) 1295 { 1296 if (chip->initialized) 1297 return; 1298 1299 /* reset controller */ 1300 azx_reset(chip, full_reset); 1301 1302 /* initialize interrupts */ 1303 azx_int_clear(chip); 1304 azx_int_enable(chip); 1305 1306 /* initialize the codec command I/O */ 1307 if (!chip->single_cmd) 1308 azx_init_cmd_io(chip); 1309 1310 /* program the position buffer */ 1311 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr); 1312 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr)); 1313 1314 chip->initialized = 1; 1315 } 1316 1317 /* 1318 * initialize the PCI registers 1319 */ 1320 /* update bits in a PCI register byte */ 1321 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 1322 unsigned char mask, unsigned char val) 1323 { 1324 unsigned char data; 1325 1326 pci_read_config_byte(pci, reg, &data); 1327 data &= ~mask; 1328 data |= (val & mask); 1329 pci_write_config_byte(pci, reg, data); 1330 } 1331 1332 static void azx_init_pci(struct azx *chip) 1333 { 1334 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 1335 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 1336 * Ensuring these bits are 0 clears playback static on some HD Audio 1337 * codecs. 1338 * The PCI register TCSEL is defined in the Intel manuals. 1339 */ 1340 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 1341 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci)); 1342 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0); 1343 } 1344 1345 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 1346 * we need to enable snoop. 1347 */ 1348 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) { 1349 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip)); 1350 update_pci_byte(chip->pci, 1351 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 1352 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 1353 } 1354 1355 /* For NVIDIA HDA, enable snoop */ 1356 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) { 1357 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip)); 1358 update_pci_byte(chip->pci, 1359 NVIDIA_HDA_TRANSREG_ADDR, 1360 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 1361 update_pci_byte(chip->pci, 1362 NVIDIA_HDA_ISTRM_COH, 1363 0x01, NVIDIA_HDA_ENABLE_COHBIT); 1364 update_pci_byte(chip->pci, 1365 NVIDIA_HDA_OSTRM_COH, 1366 0x01, NVIDIA_HDA_ENABLE_COHBIT); 1367 } 1368 1369 /* Enable SCH/PCH snoop if needed */ 1370 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) { 1371 unsigned short snoop; 1372 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 1373 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 1374 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 1375 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 1376 if (!azx_snoop(chip)) 1377 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 1378 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 1379 pci_read_config_word(chip->pci, 1380 INTEL_SCH_HDA_DEVC, &snoop); 1381 } 1382 snd_printdd(SFX "%s: SCH snoop: %s\n", 1383 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) 1384 ? "Disabled" : "Enabled"); 1385 } 1386 } 1387 1388 1389 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 1390 1391 /* 1392 * interrupt handler 1393 */ 1394 static irqreturn_t azx_interrupt(int irq, void *dev_id) 1395 { 1396 struct azx *chip = dev_id; 1397 struct azx_dev *azx_dev; 1398 u32 status; 1399 u8 sd_status; 1400 int i, ok; 1401 1402 #ifdef CONFIG_PM_RUNTIME 1403 if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME) 1404 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE) 1405 return IRQ_NONE; 1406 #endif 1407 1408 spin_lock(&chip->reg_lock); 1409 1410 if (chip->disabled) { 1411 spin_unlock(&chip->reg_lock); 1412 return IRQ_NONE; 1413 } 1414 1415 status = azx_readl(chip, INTSTS); 1416 if (status == 0 || status == 0xffffffff) { 1417 spin_unlock(&chip->reg_lock); 1418 return IRQ_NONE; 1419 } 1420 1421 for (i = 0; i < chip->num_streams; i++) { 1422 azx_dev = &chip->azx_dev[i]; 1423 if (status & azx_dev->sd_int_sta_mask) { 1424 sd_status = azx_sd_readb(azx_dev, SD_STS); 1425 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); 1426 if (!azx_dev->substream || !azx_dev->running || 1427 !(sd_status & SD_INT_COMPLETE)) 1428 continue; 1429 /* check whether this IRQ is really acceptable */ 1430 ok = azx_position_ok(chip, azx_dev); 1431 if (ok == 1) { 1432 azx_dev->irq_pending = 0; 1433 spin_unlock(&chip->reg_lock); 1434 snd_pcm_period_elapsed(azx_dev->substream); 1435 spin_lock(&chip->reg_lock); 1436 } else if (ok == 0 && chip->bus && chip->bus->workq) { 1437 /* bogus IRQ, process it later */ 1438 azx_dev->irq_pending = 1; 1439 queue_work(chip->bus->workq, 1440 &chip->irq_pending_work); 1441 } 1442 } 1443 } 1444 1445 /* clear rirb int */ 1446 status = azx_readb(chip, RIRBSTS); 1447 if (status & RIRB_INT_MASK) { 1448 if (status & RIRB_INT_RESPONSE) { 1449 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY) 1450 udelay(80); 1451 azx_update_rirb(chip); 1452 } 1453 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); 1454 } 1455 1456 #if 0 1457 /* clear state status int */ 1458 if (azx_readw(chip, STATESTS) & 0x04) 1459 azx_writew(chip, STATESTS, 0x04); 1460 #endif 1461 spin_unlock(&chip->reg_lock); 1462 1463 return IRQ_HANDLED; 1464 } 1465 1466 1467 /* 1468 * set up a BDL entry 1469 */ 1470 static int setup_bdle(struct azx *chip, 1471 struct snd_dma_buffer *dmab, 1472 struct azx_dev *azx_dev, u32 **bdlp, 1473 int ofs, int size, int with_ioc) 1474 { 1475 u32 *bdl = *bdlp; 1476 1477 while (size > 0) { 1478 dma_addr_t addr; 1479 int chunk; 1480 1481 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES) 1482 return -EINVAL; 1483 1484 addr = snd_sgbuf_get_addr(dmab, ofs); 1485 /* program the address field of the BDL entry */ 1486 bdl[0] = cpu_to_le32((u32)addr); 1487 bdl[1] = cpu_to_le32(upper_32_bits(addr)); 1488 /* program the size field of the BDL entry */ 1489 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size); 1490 /* one BDLE cannot cross 4K boundary on CTHDA chips */ 1491 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) { 1492 u32 remain = 0x1000 - (ofs & 0xfff); 1493 if (chunk > remain) 1494 chunk = remain; 1495 } 1496 bdl[2] = cpu_to_le32(chunk); 1497 /* program the IOC to enable interrupt 1498 * only when the whole fragment is processed 1499 */ 1500 size -= chunk; 1501 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01); 1502 bdl += 4; 1503 azx_dev->frags++; 1504 ofs += chunk; 1505 } 1506 *bdlp = bdl; 1507 return ofs; 1508 } 1509 1510 /* 1511 * set up BDL entries 1512 */ 1513 static int azx_setup_periods(struct azx *chip, 1514 struct snd_pcm_substream *substream, 1515 struct azx_dev *azx_dev) 1516 { 1517 u32 *bdl; 1518 int i, ofs, periods, period_bytes; 1519 int pos_adj; 1520 1521 /* reset BDL address */ 1522 azx_sd_writel(azx_dev, SD_BDLPL, 0); 1523 azx_sd_writel(azx_dev, SD_BDLPU, 0); 1524 1525 period_bytes = azx_dev->period_bytes; 1526 periods = azx_dev->bufsize / period_bytes; 1527 1528 /* program the initial BDL entries */ 1529 bdl = (u32 *)azx_dev->bdl.area; 1530 ofs = 0; 1531 azx_dev->frags = 0; 1532 pos_adj = bdl_pos_adj[chip->dev_index]; 1533 if (!azx_dev->no_period_wakeup && pos_adj > 0) { 1534 struct snd_pcm_runtime *runtime = substream->runtime; 1535 int pos_align = pos_adj; 1536 pos_adj = (pos_adj * runtime->rate + 47999) / 48000; 1537 if (!pos_adj) 1538 pos_adj = pos_align; 1539 else 1540 pos_adj = ((pos_adj + pos_align - 1) / pos_align) * 1541 pos_align; 1542 pos_adj = frames_to_bytes(runtime, pos_adj); 1543 if (pos_adj >= period_bytes) { 1544 snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n", 1545 pci_name(chip->pci), bdl_pos_adj[chip->dev_index]); 1546 pos_adj = 0; 1547 } else { 1548 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), 1549 azx_dev, 1550 &bdl, ofs, pos_adj, true); 1551 if (ofs < 0) 1552 goto error; 1553 } 1554 } else 1555 pos_adj = 0; 1556 for (i = 0; i < periods; i++) { 1557 if (i == periods - 1 && pos_adj) 1558 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), 1559 azx_dev, &bdl, ofs, 1560 period_bytes - pos_adj, 0); 1561 else 1562 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), 1563 azx_dev, &bdl, ofs, 1564 period_bytes, 1565 !azx_dev->no_period_wakeup); 1566 if (ofs < 0) 1567 goto error; 1568 } 1569 return 0; 1570 1571 error: 1572 snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n", 1573 pci_name(chip->pci), azx_dev->bufsize, period_bytes); 1574 return -EINVAL; 1575 } 1576 1577 /* reset stream */ 1578 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev) 1579 { 1580 unsigned char val; 1581 int timeout; 1582 1583 azx_stream_clear(chip, azx_dev); 1584 1585 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | 1586 SD_CTL_STREAM_RESET); 1587 udelay(3); 1588 timeout = 300; 1589 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && 1590 --timeout) 1591 ; 1592 val &= ~SD_CTL_STREAM_RESET; 1593 azx_sd_writeb(azx_dev, SD_CTL, val); 1594 udelay(3); 1595 1596 timeout = 300; 1597 /* waiting for hardware to report that the stream is out of reset */ 1598 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && 1599 --timeout) 1600 ; 1601 1602 /* reset first position - may not be synced with hw at this time */ 1603 *azx_dev->posbuf = 0; 1604 } 1605 1606 /* 1607 * set up the SD for streaming 1608 */ 1609 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev) 1610 { 1611 unsigned int val; 1612 /* make sure the run bit is zero for SD */ 1613 azx_stream_clear(chip, azx_dev); 1614 /* program the stream_tag */ 1615 val = azx_sd_readl(azx_dev, SD_CTL); 1616 val = (val & ~SD_CTL_STREAM_TAG_MASK) | 1617 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT); 1618 if (!azx_snoop(chip)) 1619 val |= SD_CTL_TRAFFIC_PRIO; 1620 azx_sd_writel(azx_dev, SD_CTL, val); 1621 1622 /* program the length of samples in cyclic buffer */ 1623 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize); 1624 1625 /* program the stream format */ 1626 /* this value needs to be the same as the one programmed */ 1627 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val); 1628 1629 /* program the stream LVI (last valid index) of the BDL */ 1630 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1); 1631 1632 /* program the BDL address */ 1633 /* lower BDL address */ 1634 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); 1635 /* upper BDL address */ 1636 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr)); 1637 1638 /* enable the position buffer */ 1639 if (chip->position_fix[0] != POS_FIX_LPIB || 1640 chip->position_fix[1] != POS_FIX_LPIB) { 1641 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE)) 1642 azx_writel(chip, DPLBASE, 1643 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE); 1644 } 1645 1646 /* set the interrupt enable bits in the descriptor control register */ 1647 azx_sd_writel(azx_dev, SD_CTL, 1648 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK); 1649 1650 return 0; 1651 } 1652 1653 /* 1654 * Probe the given codec address 1655 */ 1656 static int probe_codec(struct azx *chip, int addr) 1657 { 1658 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | 1659 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; 1660 unsigned int res; 1661 1662 mutex_lock(&chip->bus->cmd_mutex); 1663 chip->probing = 1; 1664 azx_send_cmd(chip->bus, cmd); 1665 res = azx_get_response(chip->bus, addr); 1666 chip->probing = 0; 1667 mutex_unlock(&chip->bus->cmd_mutex); 1668 if (res == -1) 1669 return -EIO; 1670 snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr); 1671 return 0; 1672 } 1673 1674 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, 1675 struct hda_pcm *cpcm); 1676 static void azx_stop_chip(struct azx *chip); 1677 1678 static void azx_bus_reset(struct hda_bus *bus) 1679 { 1680 struct azx *chip = bus->private_data; 1681 1682 bus->in_reset = 1; 1683 azx_stop_chip(chip); 1684 azx_init_chip(chip, 1); 1685 #ifdef CONFIG_PM 1686 if (chip->initialized) { 1687 struct azx_pcm *p; 1688 list_for_each_entry(p, &chip->pcm_list, list) 1689 snd_pcm_suspend_all(p->pcm); 1690 snd_hda_suspend(chip->bus); 1691 snd_hda_resume(chip->bus); 1692 } 1693 #endif 1694 bus->in_reset = 0; 1695 } 1696 1697 static int get_jackpoll_interval(struct azx *chip) 1698 { 1699 int i = jackpoll_ms[chip->dev_index]; 1700 unsigned int j; 1701 if (i == 0) 1702 return 0; 1703 if (i < 50 || i > 60000) 1704 j = 0; 1705 else 1706 j = msecs_to_jiffies(i); 1707 if (j == 0) 1708 snd_printk(KERN_WARNING SFX 1709 "jackpoll_ms value out of range: %d\n", i); 1710 return j; 1711 } 1712 1713 /* 1714 * Codec initialization 1715 */ 1716 1717 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 1718 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 1719 [AZX_DRIVER_NVIDIA] = 8, 1720 [AZX_DRIVER_TERA] = 1, 1721 }; 1722 1723 static int azx_codec_create(struct azx *chip, const char *model) 1724 { 1725 struct hda_bus_template bus_temp; 1726 int c, codecs, err; 1727 int max_slots; 1728 1729 memset(&bus_temp, 0, sizeof(bus_temp)); 1730 bus_temp.private_data = chip; 1731 bus_temp.modelname = model; 1732 bus_temp.pci = chip->pci; 1733 bus_temp.ops.command = azx_send_cmd; 1734 bus_temp.ops.get_response = azx_get_response; 1735 bus_temp.ops.attach_pcm = azx_attach_pcm_stream; 1736 bus_temp.ops.bus_reset = azx_bus_reset; 1737 #ifdef CONFIG_PM 1738 bus_temp.power_save = &power_save; 1739 bus_temp.ops.pm_notify = azx_power_notify; 1740 #endif 1741 #ifdef CONFIG_SND_HDA_DSP_LOADER 1742 bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare; 1743 bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger; 1744 bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup; 1745 #endif 1746 1747 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus); 1748 if (err < 0) 1749 return err; 1750 1751 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) { 1752 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci)); 1753 chip->bus->needs_damn_long_delay = 1; 1754 } 1755 1756 codecs = 0; 1757 max_slots = azx_max_codecs[chip->driver_type]; 1758 if (!max_slots) 1759 max_slots = AZX_DEFAULT_CODECS; 1760 1761 /* First try to probe all given codec slots */ 1762 for (c = 0; c < max_slots; c++) { 1763 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { 1764 if (probe_codec(chip, c) < 0) { 1765 /* Some BIOSen give you wrong codec addresses 1766 * that don't exist 1767 */ 1768 snd_printk(KERN_WARNING SFX 1769 "%s: Codec #%d probe error; " 1770 "disabling it...\n", pci_name(chip->pci), c); 1771 chip->codec_mask &= ~(1 << c); 1772 /* More badly, accessing to a non-existing 1773 * codec often screws up the controller chip, 1774 * and disturbs the further communications. 1775 * Thus if an error occurs during probing, 1776 * better to reset the controller chip to 1777 * get back to the sanity state. 1778 */ 1779 azx_stop_chip(chip); 1780 azx_init_chip(chip, 1); 1781 } 1782 } 1783 } 1784 1785 /* AMD chipsets often cause the communication stalls upon certain 1786 * sequence like the pin-detection. It seems that forcing the synced 1787 * access works around the stall. Grrr... 1788 */ 1789 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) { 1790 snd_printd(SFX "%s: Enable sync_write for stable communication\n", 1791 pci_name(chip->pci)); 1792 chip->bus->sync_write = 1; 1793 chip->bus->allow_bus_reset = 1; 1794 } 1795 1796 /* Then create codec instances */ 1797 for (c = 0; c < max_slots; c++) { 1798 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { 1799 struct hda_codec *codec; 1800 err = snd_hda_codec_new(chip->bus, c, &codec); 1801 if (err < 0) 1802 continue; 1803 codec->jackpoll_interval = get_jackpoll_interval(chip); 1804 codec->beep_mode = chip->beep_mode; 1805 codecs++; 1806 } 1807 } 1808 if (!codecs) { 1809 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci)); 1810 return -ENXIO; 1811 } 1812 return 0; 1813 } 1814 1815 /* configure each codec instance */ 1816 static int azx_codec_configure(struct azx *chip) 1817 { 1818 struct hda_codec *codec; 1819 list_for_each_entry(codec, &chip->bus->codec_list, list) { 1820 snd_hda_codec_configure(codec); 1821 } 1822 return 0; 1823 } 1824 1825 1826 /* 1827 * PCM support 1828 */ 1829 1830 /* assign a stream for the PCM */ 1831 static inline struct azx_dev * 1832 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream) 1833 { 1834 int dev, i, nums; 1835 struct azx_dev *res = NULL; 1836 /* make a non-zero unique key for the substream */ 1837 int key = (substream->pcm->device << 16) | (substream->number << 2) | 1838 (substream->stream + 1); 1839 1840 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1841 dev = chip->playback_index_offset; 1842 nums = chip->playback_streams; 1843 } else { 1844 dev = chip->capture_index_offset; 1845 nums = chip->capture_streams; 1846 } 1847 for (i = 0; i < nums; i++, dev++) { 1848 struct azx_dev *azx_dev = &chip->azx_dev[dev]; 1849 dsp_lock(azx_dev); 1850 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) { 1851 res = azx_dev; 1852 if (res->assigned_key == key) { 1853 res->opened = 1; 1854 res->assigned_key = key; 1855 dsp_unlock(azx_dev); 1856 return azx_dev; 1857 } 1858 } 1859 dsp_unlock(azx_dev); 1860 } 1861 if (res) { 1862 dsp_lock(res); 1863 res->opened = 1; 1864 res->assigned_key = key; 1865 dsp_unlock(res); 1866 } 1867 return res; 1868 } 1869 1870 /* release the assigned stream */ 1871 static inline void azx_release_device(struct azx_dev *azx_dev) 1872 { 1873 azx_dev->opened = 0; 1874 } 1875 1876 static cycle_t azx_cc_read(const struct cyclecounter *cc) 1877 { 1878 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc); 1879 struct snd_pcm_substream *substream = azx_dev->substream; 1880 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1881 struct azx *chip = apcm->chip; 1882 1883 return azx_readl(chip, WALLCLK); 1884 } 1885 1886 static void azx_timecounter_init(struct snd_pcm_substream *substream, 1887 bool force, cycle_t last) 1888 { 1889 struct azx_dev *azx_dev = get_azx_dev(substream); 1890 struct timecounter *tc = &azx_dev->azx_tc; 1891 struct cyclecounter *cc = &azx_dev->azx_cc; 1892 u64 nsec; 1893 1894 cc->read = azx_cc_read; 1895 cc->mask = CLOCKSOURCE_MASK(32); 1896 1897 /* 1898 * Converting from 24 MHz to ns means applying a 125/3 factor. 1899 * To avoid any saturation issues in intermediate operations, 1900 * the 125 factor is applied first. The division is applied 1901 * last after reading the timecounter value. 1902 * Applying the 1/3 factor as part of the multiplication 1903 * requires at least 20 bits for a decent precision, however 1904 * overflows occur after about 4 hours or less, not a option. 1905 */ 1906 1907 cc->mult = 125; /* saturation after 195 years */ 1908 cc->shift = 0; 1909 1910 nsec = 0; /* audio time is elapsed time since trigger */ 1911 timecounter_init(tc, cc, nsec); 1912 if (force) 1913 /* 1914 * force timecounter to use predefined value, 1915 * used for synchronized starts 1916 */ 1917 tc->cycle_last = last; 1918 } 1919 1920 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream, 1921 u64 nsec) 1922 { 1923 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1924 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 1925 u64 codec_frames, codec_nsecs; 1926 1927 if (!hinfo->ops.get_delay) 1928 return nsec; 1929 1930 codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream); 1931 codec_nsecs = div_u64(codec_frames * 1000000000LL, 1932 substream->runtime->rate); 1933 1934 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 1935 return nsec + codec_nsecs; 1936 1937 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0; 1938 } 1939 1940 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream, 1941 struct timespec *ts) 1942 { 1943 struct azx_dev *azx_dev = get_azx_dev(substream); 1944 u64 nsec; 1945 1946 nsec = timecounter_read(&azx_dev->azx_tc); 1947 nsec = div_u64(nsec, 3); /* can be optimized */ 1948 nsec = azx_adjust_codec_delay(substream, nsec); 1949 1950 *ts = ns_to_timespec(nsec); 1951 1952 return 0; 1953 } 1954 1955 static struct snd_pcm_hardware azx_pcm_hw = { 1956 .info = (SNDRV_PCM_INFO_MMAP | 1957 SNDRV_PCM_INFO_INTERLEAVED | 1958 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1959 SNDRV_PCM_INFO_MMAP_VALID | 1960 /* No full-resume yet implemented */ 1961 /* SNDRV_PCM_INFO_RESUME |*/ 1962 SNDRV_PCM_INFO_PAUSE | 1963 SNDRV_PCM_INFO_SYNC_START | 1964 SNDRV_PCM_INFO_HAS_WALL_CLOCK | 1965 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), 1966 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1967 .rates = SNDRV_PCM_RATE_48000, 1968 .rate_min = 48000, 1969 .rate_max = 48000, 1970 .channels_min = 2, 1971 .channels_max = 2, 1972 .buffer_bytes_max = AZX_MAX_BUF_SIZE, 1973 .period_bytes_min = 128, 1974 .period_bytes_max = AZX_MAX_BUF_SIZE / 2, 1975 .periods_min = 2, 1976 .periods_max = AZX_MAX_FRAG, 1977 .fifo_size = 0, 1978 }; 1979 1980 static int azx_pcm_open(struct snd_pcm_substream *substream) 1981 { 1982 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1983 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 1984 struct azx *chip = apcm->chip; 1985 struct azx_dev *azx_dev; 1986 struct snd_pcm_runtime *runtime = substream->runtime; 1987 unsigned long flags; 1988 int err; 1989 int buff_step; 1990 1991 mutex_lock(&chip->open_mutex); 1992 azx_dev = azx_assign_device(chip, substream); 1993 if (azx_dev == NULL) { 1994 mutex_unlock(&chip->open_mutex); 1995 return -EBUSY; 1996 } 1997 runtime->hw = azx_pcm_hw; 1998 runtime->hw.channels_min = hinfo->channels_min; 1999 runtime->hw.channels_max = hinfo->channels_max; 2000 runtime->hw.formats = hinfo->formats; 2001 runtime->hw.rates = hinfo->rates; 2002 snd_pcm_limit_hw_rates(runtime); 2003 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); 2004 2005 /* avoid wrap-around with wall-clock */ 2006 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME, 2007 20, 2008 178000000); 2009 2010 if (chip->align_buffer_size) 2011 /* constrain buffer sizes to be multiple of 128 2012 bytes. This is more efficient in terms of memory 2013 access but isn't required by the HDA spec and 2014 prevents users from specifying exact period/buffer 2015 sizes. For example for 44.1kHz, a period size set 2016 to 20ms will be rounded to 19.59ms. */ 2017 buff_step = 128; 2018 else 2019 /* Don't enforce steps on buffer sizes, still need to 2020 be multiple of 4 bytes (HDA spec). Tested on Intel 2021 HDA controllers, may not work on all devices where 2022 option needs to be disabled */ 2023 buff_step = 4; 2024 2025 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 2026 buff_step); 2027 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 2028 buff_step); 2029 snd_hda_power_up_d3wait(apcm->codec); 2030 err = hinfo->ops.open(hinfo, apcm->codec, substream); 2031 if (err < 0) { 2032 azx_release_device(azx_dev); 2033 snd_hda_power_down(apcm->codec); 2034 mutex_unlock(&chip->open_mutex); 2035 return err; 2036 } 2037 snd_pcm_limit_hw_rates(runtime); 2038 /* sanity check */ 2039 if (snd_BUG_ON(!runtime->hw.channels_min) || 2040 snd_BUG_ON(!runtime->hw.channels_max) || 2041 snd_BUG_ON(!runtime->hw.formats) || 2042 snd_BUG_ON(!runtime->hw.rates)) { 2043 azx_release_device(azx_dev); 2044 hinfo->ops.close(hinfo, apcm->codec, substream); 2045 snd_hda_power_down(apcm->codec); 2046 mutex_unlock(&chip->open_mutex); 2047 return -EINVAL; 2048 } 2049 2050 /* disable WALLCLOCK timestamps for capture streams 2051 until we figure out how to handle digital inputs */ 2052 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 2053 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; 2054 2055 spin_lock_irqsave(&chip->reg_lock, flags); 2056 azx_dev->substream = substream; 2057 azx_dev->running = 0; 2058 spin_unlock_irqrestore(&chip->reg_lock, flags); 2059 2060 runtime->private_data = azx_dev; 2061 snd_pcm_set_sync(substream); 2062 mutex_unlock(&chip->open_mutex); 2063 return 0; 2064 } 2065 2066 static int azx_pcm_close(struct snd_pcm_substream *substream) 2067 { 2068 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2069 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 2070 struct azx *chip = apcm->chip; 2071 struct azx_dev *azx_dev = get_azx_dev(substream); 2072 unsigned long flags; 2073 2074 mutex_lock(&chip->open_mutex); 2075 spin_lock_irqsave(&chip->reg_lock, flags); 2076 azx_dev->substream = NULL; 2077 azx_dev->running = 0; 2078 spin_unlock_irqrestore(&chip->reg_lock, flags); 2079 azx_release_device(azx_dev); 2080 hinfo->ops.close(hinfo, apcm->codec, substream); 2081 snd_hda_power_down(apcm->codec); 2082 mutex_unlock(&chip->open_mutex); 2083 return 0; 2084 } 2085 2086 static int azx_pcm_hw_params(struct snd_pcm_substream *substream, 2087 struct snd_pcm_hw_params *hw_params) 2088 { 2089 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2090 struct azx *chip = apcm->chip; 2091 struct azx_dev *azx_dev = get_azx_dev(substream); 2092 int ret; 2093 2094 dsp_lock(azx_dev); 2095 if (dsp_is_locked(azx_dev)) { 2096 ret = -EBUSY; 2097 goto unlock; 2098 } 2099 2100 mark_runtime_wc(chip, azx_dev, substream, false); 2101 azx_dev->bufsize = 0; 2102 azx_dev->period_bytes = 0; 2103 azx_dev->format_val = 0; 2104 ret = snd_pcm_lib_malloc_pages(substream, 2105 params_buffer_bytes(hw_params)); 2106 if (ret < 0) 2107 goto unlock; 2108 mark_runtime_wc(chip, azx_dev, substream, true); 2109 unlock: 2110 dsp_unlock(azx_dev); 2111 return ret; 2112 } 2113 2114 static int azx_pcm_hw_free(struct snd_pcm_substream *substream) 2115 { 2116 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2117 struct azx_dev *azx_dev = get_azx_dev(substream); 2118 struct azx *chip = apcm->chip; 2119 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 2120 2121 /* reset BDL address */ 2122 dsp_lock(azx_dev); 2123 if (!dsp_is_locked(azx_dev)) { 2124 azx_sd_writel(azx_dev, SD_BDLPL, 0); 2125 azx_sd_writel(azx_dev, SD_BDLPU, 0); 2126 azx_sd_writel(azx_dev, SD_CTL, 0); 2127 azx_dev->bufsize = 0; 2128 azx_dev->period_bytes = 0; 2129 azx_dev->format_val = 0; 2130 } 2131 2132 snd_hda_codec_cleanup(apcm->codec, hinfo, substream); 2133 2134 mark_runtime_wc(chip, azx_dev, substream, false); 2135 azx_dev->prepared = 0; 2136 dsp_unlock(azx_dev); 2137 return snd_pcm_lib_free_pages(substream); 2138 } 2139 2140 static int azx_pcm_prepare(struct snd_pcm_substream *substream) 2141 { 2142 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2143 struct azx *chip = apcm->chip; 2144 struct azx_dev *azx_dev = get_azx_dev(substream); 2145 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 2146 struct snd_pcm_runtime *runtime = substream->runtime; 2147 unsigned int bufsize, period_bytes, format_val, stream_tag; 2148 int err; 2149 struct hda_spdif_out *spdif = 2150 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid); 2151 unsigned short ctls = spdif ? spdif->ctls : 0; 2152 2153 dsp_lock(azx_dev); 2154 if (dsp_is_locked(azx_dev)) { 2155 err = -EBUSY; 2156 goto unlock; 2157 } 2158 2159 azx_stream_reset(chip, azx_dev); 2160 format_val = snd_hda_calc_stream_format(runtime->rate, 2161 runtime->channels, 2162 runtime->format, 2163 hinfo->maxbps, 2164 ctls); 2165 if (!format_val) { 2166 snd_printk(KERN_ERR SFX 2167 "%s: invalid format_val, rate=%d, ch=%d, format=%d\n", 2168 pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format); 2169 err = -EINVAL; 2170 goto unlock; 2171 } 2172 2173 bufsize = snd_pcm_lib_buffer_bytes(substream); 2174 period_bytes = snd_pcm_lib_period_bytes(substream); 2175 2176 snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n", 2177 pci_name(chip->pci), bufsize, format_val); 2178 2179 if (bufsize != azx_dev->bufsize || 2180 period_bytes != azx_dev->period_bytes || 2181 format_val != azx_dev->format_val || 2182 runtime->no_period_wakeup != azx_dev->no_period_wakeup) { 2183 azx_dev->bufsize = bufsize; 2184 azx_dev->period_bytes = period_bytes; 2185 azx_dev->format_val = format_val; 2186 azx_dev->no_period_wakeup = runtime->no_period_wakeup; 2187 err = azx_setup_periods(chip, substream, azx_dev); 2188 if (err < 0) 2189 goto unlock; 2190 } 2191 2192 /* wallclk has 24Mhz clock source */ 2193 azx_dev->period_wallclk = (((runtime->period_size * 24000) / 2194 runtime->rate) * 1000); 2195 azx_setup_controller(chip, azx_dev); 2196 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 2197 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1; 2198 else 2199 azx_dev->fifo_size = 0; 2200 2201 stream_tag = azx_dev->stream_tag; 2202 /* CA-IBG chips need the playback stream starting from 1 */ 2203 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) && 2204 stream_tag > chip->capture_streams) 2205 stream_tag -= chip->capture_streams; 2206 err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag, 2207 azx_dev->format_val, substream); 2208 2209 unlock: 2210 if (!err) 2211 azx_dev->prepared = 1; 2212 dsp_unlock(azx_dev); 2213 return err; 2214 } 2215 2216 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 2217 { 2218 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2219 struct azx *chip = apcm->chip; 2220 struct azx_dev *azx_dev; 2221 struct snd_pcm_substream *s; 2222 int rstart = 0, start, nsync = 0, sbits = 0; 2223 int nwait, timeout; 2224 2225 azx_dev = get_azx_dev(substream); 2226 trace_azx_pcm_trigger(chip, azx_dev, cmd); 2227 2228 if (dsp_is_locked(azx_dev) || !azx_dev->prepared) 2229 return -EPIPE; 2230 2231 switch (cmd) { 2232 case SNDRV_PCM_TRIGGER_START: 2233 rstart = 1; 2234 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 2235 case SNDRV_PCM_TRIGGER_RESUME: 2236 start = 1; 2237 break; 2238 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 2239 case SNDRV_PCM_TRIGGER_SUSPEND: 2240 case SNDRV_PCM_TRIGGER_STOP: 2241 start = 0; 2242 break; 2243 default: 2244 return -EINVAL; 2245 } 2246 2247 snd_pcm_group_for_each_entry(s, substream) { 2248 if (s->pcm->card != substream->pcm->card) 2249 continue; 2250 azx_dev = get_azx_dev(s); 2251 sbits |= 1 << azx_dev->index; 2252 nsync++; 2253 snd_pcm_trigger_done(s, substream); 2254 } 2255 2256 spin_lock(&chip->reg_lock); 2257 2258 /* first, set SYNC bits of corresponding streams */ 2259 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC) 2260 azx_writel(chip, OLD_SSYNC, 2261 azx_readl(chip, OLD_SSYNC) | sbits); 2262 else 2263 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits); 2264 2265 snd_pcm_group_for_each_entry(s, substream) { 2266 if (s->pcm->card != substream->pcm->card) 2267 continue; 2268 azx_dev = get_azx_dev(s); 2269 if (start) { 2270 azx_dev->start_wallclk = azx_readl(chip, WALLCLK); 2271 if (!rstart) 2272 azx_dev->start_wallclk -= 2273 azx_dev->period_wallclk; 2274 azx_stream_start(chip, azx_dev); 2275 } else { 2276 azx_stream_stop(chip, azx_dev); 2277 } 2278 azx_dev->running = start; 2279 } 2280 spin_unlock(&chip->reg_lock); 2281 if (start) { 2282 /* wait until all FIFOs get ready */ 2283 for (timeout = 5000; timeout; timeout--) { 2284 nwait = 0; 2285 snd_pcm_group_for_each_entry(s, substream) { 2286 if (s->pcm->card != substream->pcm->card) 2287 continue; 2288 azx_dev = get_azx_dev(s); 2289 if (!(azx_sd_readb(azx_dev, SD_STS) & 2290 SD_STS_FIFO_READY)) 2291 nwait++; 2292 } 2293 if (!nwait) 2294 break; 2295 cpu_relax(); 2296 } 2297 } else { 2298 /* wait until all RUN bits are cleared */ 2299 for (timeout = 5000; timeout; timeout--) { 2300 nwait = 0; 2301 snd_pcm_group_for_each_entry(s, substream) { 2302 if (s->pcm->card != substream->pcm->card) 2303 continue; 2304 azx_dev = get_azx_dev(s); 2305 if (azx_sd_readb(azx_dev, SD_CTL) & 2306 SD_CTL_DMA_START) 2307 nwait++; 2308 } 2309 if (!nwait) 2310 break; 2311 cpu_relax(); 2312 } 2313 } 2314 spin_lock(&chip->reg_lock); 2315 /* reset SYNC bits */ 2316 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC) 2317 azx_writel(chip, OLD_SSYNC, 2318 azx_readl(chip, OLD_SSYNC) & ~sbits); 2319 else 2320 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits); 2321 if (start) { 2322 azx_timecounter_init(substream, 0, 0); 2323 if (nsync > 1) { 2324 cycle_t cycle_last; 2325 2326 /* same start cycle for master and group */ 2327 azx_dev = get_azx_dev(substream); 2328 cycle_last = azx_dev->azx_tc.cycle_last; 2329 2330 snd_pcm_group_for_each_entry(s, substream) { 2331 if (s->pcm->card != substream->pcm->card) 2332 continue; 2333 azx_timecounter_init(s, 1, cycle_last); 2334 } 2335 } 2336 } 2337 spin_unlock(&chip->reg_lock); 2338 return 0; 2339 } 2340 2341 /* get the current DMA position with correction on VIA chips */ 2342 static unsigned int azx_via_get_position(struct azx *chip, 2343 struct azx_dev *azx_dev) 2344 { 2345 unsigned int link_pos, mini_pos, bound_pos; 2346 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 2347 unsigned int fifo_size; 2348 2349 link_pos = azx_sd_readl(azx_dev, SD_LPIB); 2350 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 2351 /* Playback, no problem using link position */ 2352 return link_pos; 2353 } 2354 2355 /* Capture */ 2356 /* For new chipset, 2357 * use mod to get the DMA position just like old chipset 2358 */ 2359 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf); 2360 mod_dma_pos %= azx_dev->period_bytes; 2361 2362 /* azx_dev->fifo_size can't get FIFO size of in stream. 2363 * Get from base address + offset. 2364 */ 2365 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET); 2366 2367 if (azx_dev->insufficient) { 2368 /* Link position never gather than FIFO size */ 2369 if (link_pos <= fifo_size) 2370 return 0; 2371 2372 azx_dev->insufficient = 0; 2373 } 2374 2375 if (link_pos <= fifo_size) 2376 mini_pos = azx_dev->bufsize + link_pos - fifo_size; 2377 else 2378 mini_pos = link_pos - fifo_size; 2379 2380 /* Find nearest previous boudary */ 2381 mod_mini_pos = mini_pos % azx_dev->period_bytes; 2382 mod_link_pos = link_pos % azx_dev->period_bytes; 2383 if (mod_link_pos >= fifo_size) 2384 bound_pos = link_pos - mod_link_pos; 2385 else if (mod_dma_pos >= mod_mini_pos) 2386 bound_pos = mini_pos - mod_mini_pos; 2387 else { 2388 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes; 2389 if (bound_pos >= azx_dev->bufsize) 2390 bound_pos = 0; 2391 } 2392 2393 /* Calculate real DMA position we want */ 2394 return bound_pos + mod_dma_pos; 2395 } 2396 2397 static unsigned int azx_get_position(struct azx *chip, 2398 struct azx_dev *azx_dev, 2399 bool with_check) 2400 { 2401 struct snd_pcm_substream *substream = azx_dev->substream; 2402 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2403 unsigned int pos; 2404 int stream = substream->stream; 2405 struct hda_pcm_stream *hinfo = apcm->hinfo[stream]; 2406 int delay = 0; 2407 2408 switch (chip->position_fix[stream]) { 2409 case POS_FIX_LPIB: 2410 /* read LPIB */ 2411 pos = azx_sd_readl(azx_dev, SD_LPIB); 2412 break; 2413 case POS_FIX_VIACOMBO: 2414 pos = azx_via_get_position(chip, azx_dev); 2415 break; 2416 default: 2417 /* use the position buffer */ 2418 pos = le32_to_cpu(*azx_dev->posbuf); 2419 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) { 2420 if (!pos || pos == (u32)-1) { 2421 printk(KERN_WARNING 2422 "hda-intel: Invalid position buffer, " 2423 "using LPIB read method instead.\n"); 2424 chip->position_fix[stream] = POS_FIX_LPIB; 2425 pos = azx_sd_readl(azx_dev, SD_LPIB); 2426 } else 2427 chip->position_fix[stream] = POS_FIX_POSBUF; 2428 } 2429 break; 2430 } 2431 2432 if (pos >= azx_dev->bufsize) 2433 pos = 0; 2434 2435 /* calculate runtime delay from LPIB */ 2436 if (substream->runtime && 2437 chip->position_fix[stream] == POS_FIX_POSBUF && 2438 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 2439 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB); 2440 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 2441 delay = pos - lpib_pos; 2442 else 2443 delay = lpib_pos - pos; 2444 if (delay < 0) 2445 delay += azx_dev->bufsize; 2446 if (delay >= azx_dev->period_bytes) { 2447 snd_printk(KERN_WARNING SFX 2448 "%s: Unstable LPIB (%d >= %d); " 2449 "disabling LPIB delay counting\n", 2450 pci_name(chip->pci), delay, azx_dev->period_bytes); 2451 delay = 0; 2452 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 2453 } 2454 delay = bytes_to_frames(substream->runtime, delay); 2455 } 2456 2457 if (substream->runtime) { 2458 if (hinfo->ops.get_delay) 2459 delay += hinfo->ops.get_delay(hinfo, apcm->codec, 2460 substream); 2461 substream->runtime->delay = delay; 2462 } 2463 2464 trace_azx_get_position(chip, azx_dev, pos, delay); 2465 return pos; 2466 } 2467 2468 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) 2469 { 2470 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2471 struct azx *chip = apcm->chip; 2472 struct azx_dev *azx_dev = get_azx_dev(substream); 2473 return bytes_to_frames(substream->runtime, 2474 azx_get_position(chip, azx_dev, false)); 2475 } 2476 2477 /* 2478 * Check whether the current DMA position is acceptable for updating 2479 * periods. Returns non-zero if it's OK. 2480 * 2481 * Many HD-audio controllers appear pretty inaccurate about 2482 * the update-IRQ timing. The IRQ is issued before actually the 2483 * data is processed. So, we need to process it afterwords in a 2484 * workqueue. 2485 */ 2486 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 2487 { 2488 u32 wallclk; 2489 unsigned int pos; 2490 2491 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk; 2492 if (wallclk < (azx_dev->period_wallclk * 2) / 3) 2493 return -1; /* bogus (too early) interrupt */ 2494 2495 pos = azx_get_position(chip, azx_dev, true); 2496 2497 if (WARN_ONCE(!azx_dev->period_bytes, 2498 "hda-intel: zero azx_dev->period_bytes")) 2499 return -1; /* this shouldn't happen! */ 2500 if (wallclk < (azx_dev->period_wallclk * 5) / 4 && 2501 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2) 2502 /* NG - it's below the first next period boundary */ 2503 return bdl_pos_adj[chip->dev_index] ? 0 : -1; 2504 azx_dev->start_wallclk += wallclk; 2505 return 1; /* OK, it's fine */ 2506 } 2507 2508 /* 2509 * The work for pending PCM period updates. 2510 */ 2511 static void azx_irq_pending_work(struct work_struct *work) 2512 { 2513 struct azx *chip = container_of(work, struct azx, irq_pending_work); 2514 int i, pending, ok; 2515 2516 if (!chip->irq_pending_warned) { 2517 printk(KERN_WARNING 2518 "hda-intel: IRQ timing workaround is activated " 2519 "for card #%d. Suggest a bigger bdl_pos_adj.\n", 2520 chip->card->number); 2521 chip->irq_pending_warned = 1; 2522 } 2523 2524 for (;;) { 2525 pending = 0; 2526 spin_lock_irq(&chip->reg_lock); 2527 for (i = 0; i < chip->num_streams; i++) { 2528 struct azx_dev *azx_dev = &chip->azx_dev[i]; 2529 if (!azx_dev->irq_pending || 2530 !azx_dev->substream || 2531 !azx_dev->running) 2532 continue; 2533 ok = azx_position_ok(chip, azx_dev); 2534 if (ok > 0) { 2535 azx_dev->irq_pending = 0; 2536 spin_unlock(&chip->reg_lock); 2537 snd_pcm_period_elapsed(azx_dev->substream); 2538 spin_lock(&chip->reg_lock); 2539 } else if (ok < 0) { 2540 pending = 0; /* too early */ 2541 } else 2542 pending++; 2543 } 2544 spin_unlock_irq(&chip->reg_lock); 2545 if (!pending) 2546 return; 2547 msleep(1); 2548 } 2549 } 2550 2551 /* clear irq_pending flags and assure no on-going workq */ 2552 static void azx_clear_irq_pending(struct azx *chip) 2553 { 2554 int i; 2555 2556 spin_lock_irq(&chip->reg_lock); 2557 for (i = 0; i < chip->num_streams; i++) 2558 chip->azx_dev[i].irq_pending = 0; 2559 spin_unlock_irq(&chip->reg_lock); 2560 } 2561 2562 #ifdef CONFIG_X86 2563 static int azx_pcm_mmap(struct snd_pcm_substream *substream, 2564 struct vm_area_struct *area) 2565 { 2566 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2567 struct azx *chip = apcm->chip; 2568 if (!azx_snoop(chip)) 2569 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); 2570 return snd_pcm_lib_default_mmap(substream, area); 2571 } 2572 #else 2573 #define azx_pcm_mmap NULL 2574 #endif 2575 2576 static struct snd_pcm_ops azx_pcm_ops = { 2577 .open = azx_pcm_open, 2578 .close = azx_pcm_close, 2579 .ioctl = snd_pcm_lib_ioctl, 2580 .hw_params = azx_pcm_hw_params, 2581 .hw_free = azx_pcm_hw_free, 2582 .prepare = azx_pcm_prepare, 2583 .trigger = azx_pcm_trigger, 2584 .pointer = azx_pcm_pointer, 2585 .wall_clock = azx_get_wallclock_tstamp, 2586 .mmap = azx_pcm_mmap, 2587 .page = snd_pcm_sgbuf_ops_page, 2588 }; 2589 2590 static void azx_pcm_free(struct snd_pcm *pcm) 2591 { 2592 struct azx_pcm *apcm = pcm->private_data; 2593 if (apcm) { 2594 list_del(&apcm->list); 2595 kfree(apcm); 2596 } 2597 } 2598 2599 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024) 2600 2601 static int 2602 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, 2603 struct hda_pcm *cpcm) 2604 { 2605 struct azx *chip = bus->private_data; 2606 struct snd_pcm *pcm; 2607 struct azx_pcm *apcm; 2608 int pcm_dev = cpcm->device; 2609 unsigned int size; 2610 int s, err; 2611 2612 list_for_each_entry(apcm, &chip->pcm_list, list) { 2613 if (apcm->pcm->device == pcm_dev) { 2614 snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n", 2615 pci_name(chip->pci), pcm_dev); 2616 return -EBUSY; 2617 } 2618 } 2619 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, 2620 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams, 2621 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams, 2622 &pcm); 2623 if (err < 0) 2624 return err; 2625 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name)); 2626 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL); 2627 if (apcm == NULL) 2628 return -ENOMEM; 2629 apcm->chip = chip; 2630 apcm->pcm = pcm; 2631 apcm->codec = codec; 2632 pcm->private_data = apcm; 2633 pcm->private_free = azx_pcm_free; 2634 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM) 2635 pcm->dev_class = SNDRV_PCM_CLASS_MODEM; 2636 list_add_tail(&apcm->list, &chip->pcm_list); 2637 cpcm->pcm = pcm; 2638 for (s = 0; s < 2; s++) { 2639 apcm->hinfo[s] = &cpcm->stream[s]; 2640 if (cpcm->stream[s].substreams) 2641 snd_pcm_set_ops(pcm, s, &azx_pcm_ops); 2642 } 2643 /* buffer pre-allocation */ 2644 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024; 2645 if (size > MAX_PREALLOC_SIZE) 2646 size = MAX_PREALLOC_SIZE; 2647 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG, 2648 snd_dma_pci_data(chip->pci), 2649 size, MAX_PREALLOC_SIZE); 2650 return 0; 2651 } 2652 2653 /* 2654 * mixer creation - all stuff is implemented in hda module 2655 */ 2656 static int azx_mixer_create(struct azx *chip) 2657 { 2658 return snd_hda_build_controls(chip->bus); 2659 } 2660 2661 2662 /* 2663 * initialize SD streams 2664 */ 2665 static int azx_init_stream(struct azx *chip) 2666 { 2667 int i; 2668 2669 /* initialize each stream (aka device) 2670 * assign the starting bdl address to each stream (device) 2671 * and initialize 2672 */ 2673 for (i = 0; i < chip->num_streams; i++) { 2674 struct azx_dev *azx_dev = &chip->azx_dev[i]; 2675 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8); 2676 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ 2677 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80); 2678 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ 2679 azx_dev->sd_int_sta_mask = 1 << i; 2680 /* stream tag: must be non-zero and unique */ 2681 azx_dev->index = i; 2682 azx_dev->stream_tag = i + 1; 2683 } 2684 2685 return 0; 2686 } 2687 2688 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 2689 { 2690 if (request_irq(chip->pci->irq, azx_interrupt, 2691 chip->msi ? 0 : IRQF_SHARED, 2692 KBUILD_MODNAME, chip)) { 2693 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, " 2694 "disabling device\n", chip->pci->irq); 2695 if (do_disconnect) 2696 snd_card_disconnect(chip->card); 2697 return -1; 2698 } 2699 chip->irq = chip->pci->irq; 2700 pci_intx(chip->pci, !chip->msi); 2701 return 0; 2702 } 2703 2704 2705 static void azx_stop_chip(struct azx *chip) 2706 { 2707 if (!chip->initialized) 2708 return; 2709 2710 /* disable interrupts */ 2711 azx_int_disable(chip); 2712 azx_int_clear(chip); 2713 2714 /* disable CORB/RIRB */ 2715 azx_free_cmd_io(chip); 2716 2717 /* disable position buffer */ 2718 azx_writel(chip, DPLBASE, 0); 2719 azx_writel(chip, DPUBASE, 0); 2720 2721 chip->initialized = 0; 2722 } 2723 2724 #ifdef CONFIG_SND_HDA_DSP_LOADER 2725 /* 2726 * DSP loading code (e.g. for CA0132) 2727 */ 2728 2729 /* use the first stream for loading DSP */ 2730 static struct azx_dev * 2731 azx_get_dsp_loader_dev(struct azx *chip) 2732 { 2733 return &chip->azx_dev[chip->playback_index_offset]; 2734 } 2735 2736 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format, 2737 unsigned int byte_size, 2738 struct snd_dma_buffer *bufp) 2739 { 2740 u32 *bdl; 2741 struct azx *chip = bus->private_data; 2742 struct azx_dev *azx_dev; 2743 int err; 2744 2745 azx_dev = azx_get_dsp_loader_dev(chip); 2746 2747 dsp_lock(azx_dev); 2748 spin_lock_irq(&chip->reg_lock); 2749 if (azx_dev->running || azx_dev->locked) { 2750 spin_unlock_irq(&chip->reg_lock); 2751 err = -EBUSY; 2752 goto unlock; 2753 } 2754 azx_dev->prepared = 0; 2755 chip->saved_azx_dev = *azx_dev; 2756 azx_dev->locked = 1; 2757 spin_unlock_irq(&chip->reg_lock); 2758 2759 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, 2760 snd_dma_pci_data(chip->pci), 2761 byte_size, bufp); 2762 if (err < 0) 2763 goto err_alloc; 2764 2765 mark_pages_wc(chip, bufp, true); 2766 azx_dev->bufsize = byte_size; 2767 azx_dev->period_bytes = byte_size; 2768 azx_dev->format_val = format; 2769 2770 azx_stream_reset(chip, azx_dev); 2771 2772 /* reset BDL address */ 2773 azx_sd_writel(azx_dev, SD_BDLPL, 0); 2774 azx_sd_writel(azx_dev, SD_BDLPU, 0); 2775 2776 azx_dev->frags = 0; 2777 bdl = (u32 *)azx_dev->bdl.area; 2778 err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0); 2779 if (err < 0) 2780 goto error; 2781 2782 azx_setup_controller(chip, azx_dev); 2783 dsp_unlock(azx_dev); 2784 return azx_dev->stream_tag; 2785 2786 error: 2787 mark_pages_wc(chip, bufp, false); 2788 snd_dma_free_pages(bufp); 2789 err_alloc: 2790 spin_lock_irq(&chip->reg_lock); 2791 if (azx_dev->opened) 2792 *azx_dev = chip->saved_azx_dev; 2793 azx_dev->locked = 0; 2794 spin_unlock_irq(&chip->reg_lock); 2795 unlock: 2796 dsp_unlock(azx_dev); 2797 return err; 2798 } 2799 2800 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start) 2801 { 2802 struct azx *chip = bus->private_data; 2803 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); 2804 2805 if (start) 2806 azx_stream_start(chip, azx_dev); 2807 else 2808 azx_stream_stop(chip, azx_dev); 2809 azx_dev->running = start; 2810 } 2811 2812 static void azx_load_dsp_cleanup(struct hda_bus *bus, 2813 struct snd_dma_buffer *dmab) 2814 { 2815 struct azx *chip = bus->private_data; 2816 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); 2817 2818 if (!dmab->area || !azx_dev->locked) 2819 return; 2820 2821 dsp_lock(azx_dev); 2822 /* reset BDL address */ 2823 azx_sd_writel(azx_dev, SD_BDLPL, 0); 2824 azx_sd_writel(azx_dev, SD_BDLPU, 0); 2825 azx_sd_writel(azx_dev, SD_CTL, 0); 2826 azx_dev->bufsize = 0; 2827 azx_dev->period_bytes = 0; 2828 azx_dev->format_val = 0; 2829 2830 mark_pages_wc(chip, dmab, false); 2831 snd_dma_free_pages(dmab); 2832 dmab->area = NULL; 2833 2834 spin_lock_irq(&chip->reg_lock); 2835 if (azx_dev->opened) 2836 *azx_dev = chip->saved_azx_dev; 2837 azx_dev->locked = 0; 2838 spin_unlock_irq(&chip->reg_lock); 2839 dsp_unlock(azx_dev); 2840 } 2841 #endif /* CONFIG_SND_HDA_DSP_LOADER */ 2842 2843 #ifdef CONFIG_PM 2844 /* power-up/down the controller */ 2845 static void azx_power_notify(struct hda_bus *bus, bool power_up) 2846 { 2847 struct azx *chip = bus->private_data; 2848 2849 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) 2850 return; 2851 2852 if (power_up) 2853 pm_runtime_get_sync(&chip->pci->dev); 2854 else 2855 pm_runtime_put_sync(&chip->pci->dev); 2856 } 2857 2858 static DEFINE_MUTEX(card_list_lock); 2859 static LIST_HEAD(card_list); 2860 2861 static void azx_add_card_list(struct azx *chip) 2862 { 2863 mutex_lock(&card_list_lock); 2864 list_add(&chip->list, &card_list); 2865 mutex_unlock(&card_list_lock); 2866 } 2867 2868 static void azx_del_card_list(struct azx *chip) 2869 { 2870 mutex_lock(&card_list_lock); 2871 list_del_init(&chip->list); 2872 mutex_unlock(&card_list_lock); 2873 } 2874 2875 /* trigger power-save check at writing parameter */ 2876 static int param_set_xint(const char *val, const struct kernel_param *kp) 2877 { 2878 struct azx *chip; 2879 struct hda_codec *c; 2880 int prev = power_save; 2881 int ret = param_set_int(val, kp); 2882 2883 if (ret || prev == power_save) 2884 return ret; 2885 2886 mutex_lock(&card_list_lock); 2887 list_for_each_entry(chip, &card_list, list) { 2888 if (!chip->bus || chip->disabled) 2889 continue; 2890 list_for_each_entry(c, &chip->bus->codec_list, list) 2891 snd_hda_power_sync(c); 2892 } 2893 mutex_unlock(&card_list_lock); 2894 return 0; 2895 } 2896 #else 2897 #define azx_add_card_list(chip) /* NOP */ 2898 #define azx_del_card_list(chip) /* NOP */ 2899 #endif /* CONFIG_PM */ 2900 2901 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO) 2902 /* 2903 * power management 2904 */ 2905 static int azx_suspend(struct device *dev) 2906 { 2907 struct pci_dev *pci = to_pci_dev(dev); 2908 struct snd_card *card = dev_get_drvdata(dev); 2909 struct azx *chip = card->private_data; 2910 struct azx_pcm *p; 2911 2912 if (chip->disabled) 2913 return 0; 2914 2915 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2916 azx_clear_irq_pending(chip); 2917 list_for_each_entry(p, &chip->pcm_list, list) 2918 snd_pcm_suspend_all(p->pcm); 2919 if (chip->initialized) 2920 snd_hda_suspend(chip->bus); 2921 azx_stop_chip(chip); 2922 azx_enter_link_reset(chip); 2923 if (chip->irq >= 0) { 2924 free_irq(chip->irq, chip); 2925 chip->irq = -1; 2926 } 2927 if (chip->msi) 2928 pci_disable_msi(chip->pci); 2929 pci_disable_device(pci); 2930 pci_save_state(pci); 2931 pci_set_power_state(pci, PCI_D3hot); 2932 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 2933 hda_display_power(false); 2934 return 0; 2935 } 2936 2937 static int azx_resume(struct device *dev) 2938 { 2939 struct pci_dev *pci = to_pci_dev(dev); 2940 struct snd_card *card = dev_get_drvdata(dev); 2941 struct azx *chip = card->private_data; 2942 2943 if (chip->disabled) 2944 return 0; 2945 2946 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 2947 hda_display_power(true); 2948 pci_set_power_state(pci, PCI_D0); 2949 pci_restore_state(pci); 2950 if (pci_enable_device(pci) < 0) { 2951 printk(KERN_ERR "hda-intel: pci_enable_device failed, " 2952 "disabling device\n"); 2953 snd_card_disconnect(card); 2954 return -EIO; 2955 } 2956 pci_set_master(pci); 2957 if (chip->msi) 2958 if (pci_enable_msi(pci) < 0) 2959 chip->msi = 0; 2960 if (azx_acquire_irq(chip, 1) < 0) 2961 return -EIO; 2962 azx_init_pci(chip); 2963 2964 azx_init_chip(chip, 1); 2965 2966 snd_hda_resume(chip->bus); 2967 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2968 return 0; 2969 } 2970 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */ 2971 2972 #ifdef CONFIG_PM_RUNTIME 2973 static int azx_runtime_suspend(struct device *dev) 2974 { 2975 struct snd_card *card = dev_get_drvdata(dev); 2976 struct azx *chip = card->private_data; 2977 2978 if (chip->disabled) 2979 return 0; 2980 2981 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) 2982 return 0; 2983 2984 /* enable controller wake up event */ 2985 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 2986 STATESTS_INT_MASK); 2987 2988 azx_stop_chip(chip); 2989 azx_enter_link_reset(chip); 2990 azx_clear_irq_pending(chip); 2991 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 2992 hda_display_power(false); 2993 return 0; 2994 } 2995 2996 static int azx_runtime_resume(struct device *dev) 2997 { 2998 struct snd_card *card = dev_get_drvdata(dev); 2999 struct azx *chip = card->private_data; 3000 struct hda_bus *bus; 3001 struct hda_codec *codec; 3002 int status; 3003 3004 if (chip->disabled) 3005 return 0; 3006 3007 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) 3008 return 0; 3009 3010 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 3011 hda_display_power(true); 3012 3013 /* Read STATESTS before controller reset */ 3014 status = azx_readw(chip, STATESTS); 3015 3016 azx_init_pci(chip); 3017 azx_init_chip(chip, 1); 3018 3019 bus = chip->bus; 3020 if (status && bus) { 3021 list_for_each_entry(codec, &bus->codec_list, list) 3022 if (status & (1 << codec->addr)) 3023 queue_delayed_work(codec->bus->workq, 3024 &codec->jackpoll_work, codec->jackpoll_interval); 3025 } 3026 3027 /* disable controller Wake Up event*/ 3028 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 3029 ~STATESTS_INT_MASK); 3030 3031 return 0; 3032 } 3033 3034 static int azx_runtime_idle(struct device *dev) 3035 { 3036 struct snd_card *card = dev_get_drvdata(dev); 3037 struct azx *chip = card->private_data; 3038 3039 if (chip->disabled) 3040 return 0; 3041 3042 if (!power_save_controller || 3043 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) 3044 return -EBUSY; 3045 3046 return 0; 3047 } 3048 3049 #endif /* CONFIG_PM_RUNTIME */ 3050 3051 #ifdef CONFIG_PM 3052 static const struct dev_pm_ops azx_pm = { 3053 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 3054 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 3055 }; 3056 3057 #define AZX_PM_OPS &azx_pm 3058 #else 3059 #define AZX_PM_OPS NULL 3060 #endif /* CONFIG_PM */ 3061 3062 3063 /* 3064 * reboot notifier for hang-up problem at power-down 3065 */ 3066 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf) 3067 { 3068 struct azx *chip = container_of(nb, struct azx, reboot_notifier); 3069 snd_hda_bus_reboot_notify(chip->bus); 3070 azx_stop_chip(chip); 3071 return NOTIFY_OK; 3072 } 3073 3074 static void azx_notifier_register(struct azx *chip) 3075 { 3076 chip->reboot_notifier.notifier_call = azx_halt; 3077 register_reboot_notifier(&chip->reboot_notifier); 3078 } 3079 3080 static void azx_notifier_unregister(struct azx *chip) 3081 { 3082 if (chip->reboot_notifier.notifier_call) 3083 unregister_reboot_notifier(&chip->reboot_notifier); 3084 } 3085 3086 static int azx_probe_continue(struct azx *chip); 3087 3088 #ifdef SUPPORT_VGA_SWITCHEROO 3089 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 3090 3091 static void azx_vs_set_state(struct pci_dev *pci, 3092 enum vga_switcheroo_state state) 3093 { 3094 struct snd_card *card = pci_get_drvdata(pci); 3095 struct azx *chip = card->private_data; 3096 bool disabled; 3097 3098 wait_for_completion(&chip->probe_wait); 3099 if (chip->init_failed) 3100 return; 3101 3102 disabled = (state == VGA_SWITCHEROO_OFF); 3103 if (chip->disabled == disabled) 3104 return; 3105 3106 if (!chip->bus) { 3107 chip->disabled = disabled; 3108 if (!disabled) { 3109 snd_printk(KERN_INFO SFX 3110 "%s: Start delayed initialization\n", 3111 pci_name(chip->pci)); 3112 if (azx_probe_continue(chip) < 0) { 3113 snd_printk(KERN_ERR SFX 3114 "%s: initialization error\n", 3115 pci_name(chip->pci)); 3116 chip->init_failed = true; 3117 } 3118 } 3119 } else { 3120 snd_printk(KERN_INFO SFX 3121 "%s: %s via VGA-switcheroo\n", pci_name(chip->pci), 3122 disabled ? "Disabling" : "Enabling"); 3123 if (disabled) { 3124 pm_runtime_put_sync_suspend(&pci->dev); 3125 azx_suspend(&pci->dev); 3126 /* when we get suspended by vga switcheroo we end up in D3cold, 3127 * however we have no ACPI handle, so pci/acpi can't put us there, 3128 * put ourselves there */ 3129 pci->current_state = PCI_D3cold; 3130 chip->disabled = true; 3131 if (snd_hda_lock_devices(chip->bus)) 3132 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n", 3133 pci_name(chip->pci)); 3134 } else { 3135 snd_hda_unlock_devices(chip->bus); 3136 pm_runtime_get_noresume(&pci->dev); 3137 chip->disabled = false; 3138 azx_resume(&pci->dev); 3139 } 3140 } 3141 } 3142 3143 static bool azx_vs_can_switch(struct pci_dev *pci) 3144 { 3145 struct snd_card *card = pci_get_drvdata(pci); 3146 struct azx *chip = card->private_data; 3147 3148 wait_for_completion(&chip->probe_wait); 3149 if (chip->init_failed) 3150 return false; 3151 if (chip->disabled || !chip->bus) 3152 return true; 3153 if (snd_hda_lock_devices(chip->bus)) 3154 return false; 3155 snd_hda_unlock_devices(chip->bus); 3156 return true; 3157 } 3158 3159 static void init_vga_switcheroo(struct azx *chip) 3160 { 3161 struct pci_dev *p = get_bound_vga(chip->pci); 3162 if (p) { 3163 snd_printk(KERN_INFO SFX 3164 "%s: Handle VGA-switcheroo audio client\n", 3165 pci_name(chip->pci)); 3166 chip->use_vga_switcheroo = 1; 3167 pci_dev_put(p); 3168 } 3169 } 3170 3171 static const struct vga_switcheroo_client_ops azx_vs_ops = { 3172 .set_gpu_state = azx_vs_set_state, 3173 .can_switch = azx_vs_can_switch, 3174 }; 3175 3176 static int register_vga_switcheroo(struct azx *chip) 3177 { 3178 int err; 3179 3180 if (!chip->use_vga_switcheroo) 3181 return 0; 3182 /* FIXME: currently only handling DIS controller 3183 * is there any machine with two switchable HDMI audio controllers? 3184 */ 3185 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, 3186 VGA_SWITCHEROO_DIS, 3187 chip->bus != NULL); 3188 if (err < 0) 3189 return err; 3190 chip->vga_switcheroo_registered = 1; 3191 3192 /* register as an optimus hdmi audio power domain */ 3193 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(&chip->pci->dev, &chip->hdmi_pm_domain); 3194 return 0; 3195 } 3196 #else 3197 #define init_vga_switcheroo(chip) /* NOP */ 3198 #define register_vga_switcheroo(chip) 0 3199 #define check_hdmi_disabled(pci) false 3200 #endif /* SUPPORT_VGA_SWITCHER */ 3201 3202 /* 3203 * destructor 3204 */ 3205 static int azx_free(struct azx *chip) 3206 { 3207 struct pci_dev *pci = chip->pci; 3208 int i; 3209 3210 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) 3211 && chip->running) 3212 pm_runtime_get_noresume(&pci->dev); 3213 3214 azx_del_card_list(chip); 3215 3216 azx_notifier_unregister(chip); 3217 3218 chip->init_failed = 1; /* to be sure */ 3219 complete_all(&chip->probe_wait); 3220 3221 if (use_vga_switcheroo(chip)) { 3222 if (chip->disabled && chip->bus) 3223 snd_hda_unlock_devices(chip->bus); 3224 if (chip->vga_switcheroo_registered) 3225 vga_switcheroo_unregister_client(chip->pci); 3226 } 3227 3228 if (chip->initialized) { 3229 azx_clear_irq_pending(chip); 3230 for (i = 0; i < chip->num_streams; i++) 3231 azx_stream_stop(chip, &chip->azx_dev[i]); 3232 azx_stop_chip(chip); 3233 } 3234 3235 if (chip->irq >= 0) 3236 free_irq(chip->irq, (void*)chip); 3237 if (chip->msi) 3238 pci_disable_msi(chip->pci); 3239 if (chip->remap_addr) 3240 iounmap(chip->remap_addr); 3241 3242 if (chip->azx_dev) { 3243 for (i = 0; i < chip->num_streams; i++) 3244 if (chip->azx_dev[i].bdl.area) { 3245 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false); 3246 snd_dma_free_pages(&chip->azx_dev[i].bdl); 3247 } 3248 } 3249 if (chip->rb.area) { 3250 mark_pages_wc(chip, &chip->rb, false); 3251 snd_dma_free_pages(&chip->rb); 3252 } 3253 if (chip->posbuf.area) { 3254 mark_pages_wc(chip, &chip->posbuf, false); 3255 snd_dma_free_pages(&chip->posbuf); 3256 } 3257 if (chip->region_requested) 3258 pci_release_regions(chip->pci); 3259 pci_disable_device(chip->pci); 3260 kfree(chip->azx_dev); 3261 #ifdef CONFIG_SND_HDA_PATCH_LOADER 3262 if (chip->fw) 3263 release_firmware(chip->fw); 3264 #endif 3265 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 3266 hda_display_power(false); 3267 hda_i915_exit(); 3268 } 3269 kfree(chip); 3270 3271 return 0; 3272 } 3273 3274 static int azx_dev_free(struct snd_device *device) 3275 { 3276 return azx_free(device->device_data); 3277 } 3278 3279 #ifdef SUPPORT_VGA_SWITCHEROO 3280 /* 3281 * Check of disabled HDMI controller by vga-switcheroo 3282 */ 3283 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 3284 { 3285 struct pci_dev *p; 3286 3287 /* check only discrete GPU */ 3288 switch (pci->vendor) { 3289 case PCI_VENDOR_ID_ATI: 3290 case PCI_VENDOR_ID_AMD: 3291 case PCI_VENDOR_ID_NVIDIA: 3292 if (pci->devfn == 1) { 3293 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 3294 pci->bus->number, 0); 3295 if (p) { 3296 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA) 3297 return p; 3298 pci_dev_put(p); 3299 } 3300 } 3301 break; 3302 } 3303 return NULL; 3304 } 3305 3306 static bool check_hdmi_disabled(struct pci_dev *pci) 3307 { 3308 bool vga_inactive = false; 3309 struct pci_dev *p = get_bound_vga(pci); 3310 3311 if (p) { 3312 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 3313 vga_inactive = true; 3314 pci_dev_put(p); 3315 } 3316 return vga_inactive; 3317 } 3318 #endif /* SUPPORT_VGA_SWITCHEROO */ 3319 3320 /* 3321 * white/black-listing for position_fix 3322 */ 3323 static struct snd_pci_quirk position_fix_list[] = { 3324 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 3325 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 3326 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 3327 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 3328 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 3329 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 3330 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 3331 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 3332 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 3333 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 3334 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 3335 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 3336 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 3337 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 3338 {} 3339 }; 3340 3341 static int check_position_fix(struct azx *chip, int fix) 3342 { 3343 const struct snd_pci_quirk *q; 3344 3345 switch (fix) { 3346 case POS_FIX_AUTO: 3347 case POS_FIX_LPIB: 3348 case POS_FIX_POSBUF: 3349 case POS_FIX_VIACOMBO: 3350 case POS_FIX_COMBO: 3351 return fix; 3352 } 3353 3354 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 3355 if (q) { 3356 printk(KERN_INFO 3357 "hda_intel: position_fix set to %d " 3358 "for device %04x:%04x\n", 3359 q->value, q->subvendor, q->subdevice); 3360 return q->value; 3361 } 3362 3363 /* Check VIA/ATI HD Audio Controller exist */ 3364 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) { 3365 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci)); 3366 return POS_FIX_VIACOMBO; 3367 } 3368 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 3369 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci)); 3370 return POS_FIX_LPIB; 3371 } 3372 return POS_FIX_AUTO; 3373 } 3374 3375 /* 3376 * black-lists for probe_mask 3377 */ 3378 static struct snd_pci_quirk probe_mask_list[] = { 3379 /* Thinkpad often breaks the controller communication when accessing 3380 * to the non-working (or non-existing) modem codec slot. 3381 */ 3382 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 3383 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 3384 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 3385 /* broken BIOS */ 3386 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 3387 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 3388 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 3389 /* forced codec slots */ 3390 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 3391 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 3392 /* WinFast VP200 H (Teradici) user reported broken communication */ 3393 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 3394 {} 3395 }; 3396 3397 #define AZX_FORCE_CODEC_MASK 0x100 3398 3399 static void check_probe_mask(struct azx *chip, int dev) 3400 { 3401 const struct snd_pci_quirk *q; 3402 3403 chip->codec_probe_mask = probe_mask[dev]; 3404 if (chip->codec_probe_mask == -1) { 3405 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 3406 if (q) { 3407 printk(KERN_INFO 3408 "hda_intel: probe_mask set to 0x%x " 3409 "for device %04x:%04x\n", 3410 q->value, q->subvendor, q->subdevice); 3411 chip->codec_probe_mask = q->value; 3412 } 3413 } 3414 3415 /* check forced option */ 3416 if (chip->codec_probe_mask != -1 && 3417 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 3418 chip->codec_mask = chip->codec_probe_mask & 0xff; 3419 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n", 3420 chip->codec_mask); 3421 } 3422 } 3423 3424 /* 3425 * white/black-list for enable_msi 3426 */ 3427 static struct snd_pci_quirk msi_black_list[] = { 3428 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 3429 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 3430 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 3431 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 3432 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 3433 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 3434 {} 3435 }; 3436 3437 static void check_msi(struct azx *chip) 3438 { 3439 const struct snd_pci_quirk *q; 3440 3441 if (enable_msi >= 0) { 3442 chip->msi = !!enable_msi; 3443 return; 3444 } 3445 chip->msi = 1; /* enable MSI as default */ 3446 q = snd_pci_quirk_lookup(chip->pci, msi_black_list); 3447 if (q) { 3448 printk(KERN_INFO 3449 "hda_intel: msi for device %04x:%04x set to %d\n", 3450 q->subvendor, q->subdevice, q->value); 3451 chip->msi = q->value; 3452 return; 3453 } 3454 3455 /* NVidia chipsets seem to cause troubles with MSI */ 3456 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 3457 printk(KERN_INFO "hda_intel: Disabling MSI\n"); 3458 chip->msi = 0; 3459 } 3460 } 3461 3462 /* check the snoop mode availability */ 3463 static void azx_check_snoop_available(struct azx *chip) 3464 { 3465 bool snoop = chip->snoop; 3466 3467 switch (chip->driver_type) { 3468 case AZX_DRIVER_VIA: 3469 /* force to non-snoop mode for a new VIA controller 3470 * when BIOS is set 3471 */ 3472 if (snoop) { 3473 u8 val; 3474 pci_read_config_byte(chip->pci, 0x42, &val); 3475 if (!(val & 0x80) && chip->pci->revision == 0x30) 3476 snoop = false; 3477 } 3478 break; 3479 case AZX_DRIVER_ATIHDMI_NS: 3480 /* new ATI HDMI requires non-snoop */ 3481 snoop = false; 3482 break; 3483 case AZX_DRIVER_CTHDA: 3484 snoop = false; 3485 break; 3486 } 3487 3488 if (snoop != chip->snoop) { 3489 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n", 3490 pci_name(chip->pci), snoop ? "snoop" : "non-snoop"); 3491 chip->snoop = snoop; 3492 } 3493 } 3494 3495 #ifdef CONFIG_SND_HDA_I915 3496 static void azx_probe_work(struct work_struct *work) 3497 { 3498 azx_probe_continue(container_of(work, struct azx, probe_work)); 3499 } 3500 #endif 3501 3502 /* 3503 * constructor 3504 */ 3505 static int azx_create(struct snd_card *card, struct pci_dev *pci, 3506 int dev, unsigned int driver_caps, 3507 struct azx **rchip) 3508 { 3509 static struct snd_device_ops ops = { 3510 .dev_free = azx_dev_free, 3511 }; 3512 struct azx *chip; 3513 int err; 3514 3515 *rchip = NULL; 3516 3517 err = pci_enable_device(pci); 3518 if (err < 0) 3519 return err; 3520 3521 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 3522 if (!chip) { 3523 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci)); 3524 pci_disable_device(pci); 3525 return -ENOMEM; 3526 } 3527 3528 spin_lock_init(&chip->reg_lock); 3529 mutex_init(&chip->open_mutex); 3530 chip->card = card; 3531 chip->pci = pci; 3532 chip->irq = -1; 3533 chip->driver_caps = driver_caps; 3534 chip->driver_type = driver_caps & 0xff; 3535 check_msi(chip); 3536 chip->dev_index = dev; 3537 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work); 3538 INIT_LIST_HEAD(&chip->pcm_list); 3539 INIT_LIST_HEAD(&chip->list); 3540 init_vga_switcheroo(chip); 3541 init_completion(&chip->probe_wait); 3542 3543 chip->position_fix[0] = chip->position_fix[1] = 3544 check_position_fix(chip, position_fix[dev]); 3545 /* combo mode uses LPIB for playback */ 3546 if (chip->position_fix[0] == POS_FIX_COMBO) { 3547 chip->position_fix[0] = POS_FIX_LPIB; 3548 chip->position_fix[1] = POS_FIX_AUTO; 3549 } 3550 3551 check_probe_mask(chip, dev); 3552 3553 chip->single_cmd = single_cmd; 3554 chip->snoop = hda_snoop; 3555 azx_check_snoop_available(chip); 3556 3557 if (bdl_pos_adj[dev] < 0) { 3558 switch (chip->driver_type) { 3559 case AZX_DRIVER_ICH: 3560 case AZX_DRIVER_PCH: 3561 bdl_pos_adj[dev] = 1; 3562 break; 3563 default: 3564 bdl_pos_adj[dev] = 32; 3565 break; 3566 } 3567 } 3568 3569 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 3570 if (err < 0) { 3571 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n", 3572 pci_name(chip->pci)); 3573 azx_free(chip); 3574 return err; 3575 } 3576 3577 #ifdef CONFIG_SND_HDA_I915 3578 /* continue probing in work context as may trigger request module */ 3579 INIT_WORK(&chip->probe_work, azx_probe_work); 3580 #endif 3581 3582 *rchip = chip; 3583 3584 return 0; 3585 } 3586 3587 static int azx_first_init(struct azx *chip) 3588 { 3589 int dev = chip->dev_index; 3590 struct pci_dev *pci = chip->pci; 3591 struct snd_card *card = chip->card; 3592 int i, err; 3593 unsigned short gcap; 3594 3595 #if BITS_PER_LONG != 64 3596 /* Fix up base address on ULI M5461 */ 3597 if (chip->driver_type == AZX_DRIVER_ULI) { 3598 u16 tmp3; 3599 pci_read_config_word(pci, 0x40, &tmp3); 3600 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 3601 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 3602 } 3603 #endif 3604 3605 err = pci_request_regions(pci, "ICH HD audio"); 3606 if (err < 0) 3607 return err; 3608 chip->region_requested = 1; 3609 3610 chip->addr = pci_resource_start(pci, 0); 3611 chip->remap_addr = pci_ioremap_bar(pci, 0); 3612 if (chip->remap_addr == NULL) { 3613 snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci)); 3614 return -ENXIO; 3615 } 3616 3617 if (chip->msi) 3618 if (pci_enable_msi(pci) < 0) 3619 chip->msi = 0; 3620 3621 if (azx_acquire_irq(chip, 0) < 0) 3622 return -EBUSY; 3623 3624 pci_set_master(pci); 3625 synchronize_irq(chip->irq); 3626 3627 gcap = azx_readw(chip, GCAP); 3628 snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap); 3629 3630 /* disable SB600 64bit support for safety */ 3631 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 3632 struct pci_dev *p_smbus; 3633 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 3634 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 3635 NULL); 3636 if (p_smbus) { 3637 if (p_smbus->revision < 0x30) 3638 gcap &= ~ICH6_GCAP_64OK; 3639 pci_dev_put(p_smbus); 3640 } 3641 } 3642 3643 /* disable 64bit DMA address on some devices */ 3644 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 3645 snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci)); 3646 gcap &= ~ICH6_GCAP_64OK; 3647 } 3648 3649 /* disable buffer size rounding to 128-byte multiples if supported */ 3650 if (align_buffer_size >= 0) 3651 chip->align_buffer_size = !!align_buffer_size; 3652 else { 3653 if (chip->driver_caps & AZX_DCAPS_BUFSIZE) 3654 chip->align_buffer_size = 0; 3655 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE) 3656 chip->align_buffer_size = 1; 3657 else 3658 chip->align_buffer_size = 1; 3659 } 3660 3661 /* allow 64bit DMA address if supported by H/W */ 3662 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64))) 3663 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64)); 3664 else { 3665 pci_set_dma_mask(pci, DMA_BIT_MASK(32)); 3666 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32)); 3667 } 3668 3669 /* read number of streams from GCAP register instead of using 3670 * hardcoded value 3671 */ 3672 chip->capture_streams = (gcap >> 8) & 0x0f; 3673 chip->playback_streams = (gcap >> 12) & 0x0f; 3674 if (!chip->playback_streams && !chip->capture_streams) { 3675 /* gcap didn't give any info, switching to old method */ 3676 3677 switch (chip->driver_type) { 3678 case AZX_DRIVER_ULI: 3679 chip->playback_streams = ULI_NUM_PLAYBACK; 3680 chip->capture_streams = ULI_NUM_CAPTURE; 3681 break; 3682 case AZX_DRIVER_ATIHDMI: 3683 case AZX_DRIVER_ATIHDMI_NS: 3684 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 3685 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 3686 break; 3687 case AZX_DRIVER_GENERIC: 3688 default: 3689 chip->playback_streams = ICH6_NUM_PLAYBACK; 3690 chip->capture_streams = ICH6_NUM_CAPTURE; 3691 break; 3692 } 3693 } 3694 chip->capture_index_offset = 0; 3695 chip->playback_index_offset = chip->capture_streams; 3696 chip->num_streams = chip->playback_streams + chip->capture_streams; 3697 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), 3698 GFP_KERNEL); 3699 if (!chip->azx_dev) { 3700 snd_printk(KERN_ERR SFX "%s: cannot malloc azx_dev\n", pci_name(chip->pci)); 3701 return -ENOMEM; 3702 } 3703 3704 for (i = 0; i < chip->num_streams; i++) { 3705 dsp_lock_init(&chip->azx_dev[i]); 3706 /* allocate memory for the BDL for each stream */ 3707 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, 3708 snd_dma_pci_data(chip->pci), 3709 BDL_SIZE, &chip->azx_dev[i].bdl); 3710 if (err < 0) { 3711 snd_printk(KERN_ERR SFX "%s: cannot allocate BDL\n", pci_name(chip->pci)); 3712 return -ENOMEM; 3713 } 3714 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true); 3715 } 3716 /* allocate memory for the position buffer */ 3717 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, 3718 snd_dma_pci_data(chip->pci), 3719 chip->num_streams * 8, &chip->posbuf); 3720 if (err < 0) { 3721 snd_printk(KERN_ERR SFX "%s: cannot allocate posbuf\n", pci_name(chip->pci)); 3722 return -ENOMEM; 3723 } 3724 mark_pages_wc(chip, &chip->posbuf, true); 3725 /* allocate CORB/RIRB */ 3726 err = azx_alloc_cmd_io(chip); 3727 if (err < 0) 3728 return err; 3729 3730 /* initialize streams */ 3731 azx_init_stream(chip); 3732 3733 /* initialize chip */ 3734 azx_init_pci(chip); 3735 azx_init_chip(chip, (probe_only[dev] & 2) == 0); 3736 3737 /* codec detection */ 3738 if (!chip->codec_mask) { 3739 snd_printk(KERN_ERR SFX "%s: no codecs found!\n", pci_name(chip->pci)); 3740 return -ENODEV; 3741 } 3742 3743 strcpy(card->driver, "HDA-Intel"); 3744 strlcpy(card->shortname, driver_short_names[chip->driver_type], 3745 sizeof(card->shortname)); 3746 snprintf(card->longname, sizeof(card->longname), 3747 "%s at 0x%lx irq %i", 3748 card->shortname, chip->addr, chip->irq); 3749 3750 return 0; 3751 } 3752 3753 static void power_down_all_codecs(struct azx *chip) 3754 { 3755 #ifdef CONFIG_PM 3756 /* The codecs were powered up in snd_hda_codec_new(). 3757 * Now all initialization done, so turn them down if possible 3758 */ 3759 struct hda_codec *codec; 3760 list_for_each_entry(codec, &chip->bus->codec_list, list) { 3761 snd_hda_power_down(codec); 3762 } 3763 #endif 3764 } 3765 3766 #ifdef CONFIG_SND_HDA_PATCH_LOADER 3767 /* callback from request_firmware_nowait() */ 3768 static void azx_firmware_cb(const struct firmware *fw, void *context) 3769 { 3770 struct snd_card *card = context; 3771 struct azx *chip = card->private_data; 3772 struct pci_dev *pci = chip->pci; 3773 3774 if (!fw) { 3775 snd_printk(KERN_ERR SFX "%s: Cannot load firmware, aborting\n", 3776 pci_name(chip->pci)); 3777 goto error; 3778 } 3779 3780 chip->fw = fw; 3781 if (!chip->disabled) { 3782 /* continue probing */ 3783 if (azx_probe_continue(chip)) 3784 goto error; 3785 } 3786 return; /* OK */ 3787 3788 error: 3789 snd_card_free(card); 3790 pci_set_drvdata(pci, NULL); 3791 } 3792 #endif 3793 3794 static int azx_probe(struct pci_dev *pci, 3795 const struct pci_device_id *pci_id) 3796 { 3797 static int dev; 3798 struct snd_card *card; 3799 struct azx *chip; 3800 bool probe_now; 3801 int err; 3802 3803 if (dev >= SNDRV_CARDS) 3804 return -ENODEV; 3805 if (!enable[dev]) { 3806 dev++; 3807 return -ENOENT; 3808 } 3809 3810 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card); 3811 if (err < 0) { 3812 snd_printk(KERN_ERR "hda-intel: Error creating card!\n"); 3813 return err; 3814 } 3815 3816 snd_card_set_dev(card, &pci->dev); 3817 3818 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 3819 if (err < 0) 3820 goto out_free; 3821 card->private_data = chip; 3822 3823 pci_set_drvdata(pci, card); 3824 3825 err = register_vga_switcheroo(chip); 3826 if (err < 0) { 3827 snd_printk(KERN_ERR SFX 3828 "%s: Error registering VGA-switcheroo client\n", pci_name(pci)); 3829 goto out_free; 3830 } 3831 3832 if (check_hdmi_disabled(pci)) { 3833 snd_printk(KERN_INFO SFX "%s: VGA controller is disabled\n", 3834 pci_name(pci)); 3835 snd_printk(KERN_INFO SFX "%s: Delaying initialization\n", pci_name(pci)); 3836 chip->disabled = true; 3837 } 3838 3839 probe_now = !chip->disabled; 3840 3841 #ifdef CONFIG_SND_HDA_PATCH_LOADER 3842 if (patch[dev] && *patch[dev]) { 3843 snd_printk(KERN_ERR SFX "%s: Applying patch firmware '%s'\n", 3844 pci_name(pci), patch[dev]); 3845 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 3846 &pci->dev, GFP_KERNEL, card, 3847 azx_firmware_cb); 3848 if (err < 0) 3849 goto out_free; 3850 probe_now = false; /* continued in azx_firmware_cb() */ 3851 } 3852 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 3853 3854 /* continue probing in work context, avoid request_module deadlock */ 3855 if (probe_now && (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)) { 3856 #ifdef CONFIG_SND_HDA_I915 3857 probe_now = false; 3858 schedule_work(&chip->probe_work); 3859 #else 3860 snd_printk(KERN_ERR SFX "Haswell must build in CONFIG_SND_HDA_I915\n"); 3861 #endif 3862 } 3863 3864 if (probe_now) { 3865 err = azx_probe_continue(chip); 3866 if (err < 0) 3867 goto out_free; 3868 } 3869 3870 dev++; 3871 complete_all(&chip->probe_wait); 3872 return 0; 3873 3874 out_free: 3875 snd_card_free(card); 3876 return err; 3877 } 3878 3879 static int azx_probe_continue(struct azx *chip) 3880 { 3881 struct pci_dev *pci = chip->pci; 3882 int dev = chip->dev_index; 3883 int err; 3884 3885 /* Request power well for Haswell HDA controller and codec */ 3886 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 3887 #ifdef CONFIG_SND_HDA_I915 3888 err = hda_i915_init(); 3889 if (err < 0) { 3890 snd_printk(KERN_ERR SFX "Error request power-well from i915\n"); 3891 goto out_free; 3892 } 3893 #endif 3894 hda_display_power(true); 3895 } 3896 3897 err = azx_first_init(chip); 3898 if (err < 0) 3899 goto out_free; 3900 3901 #ifdef CONFIG_SND_HDA_INPUT_BEEP 3902 chip->beep_mode = beep_mode[dev]; 3903 #endif 3904 3905 /* create codec instances */ 3906 err = azx_codec_create(chip, model[dev]); 3907 if (err < 0) 3908 goto out_free; 3909 #ifdef CONFIG_SND_HDA_PATCH_LOADER 3910 if (chip->fw) { 3911 err = snd_hda_load_patch(chip->bus, chip->fw->size, 3912 chip->fw->data); 3913 if (err < 0) 3914 goto out_free; 3915 #ifndef CONFIG_PM 3916 release_firmware(chip->fw); /* no longer needed */ 3917 chip->fw = NULL; 3918 #endif 3919 } 3920 #endif 3921 if ((probe_only[dev] & 1) == 0) { 3922 err = azx_codec_configure(chip); 3923 if (err < 0) 3924 goto out_free; 3925 } 3926 3927 /* create PCM streams */ 3928 err = snd_hda_build_pcms(chip->bus); 3929 if (err < 0) 3930 goto out_free; 3931 3932 /* create mixer controls */ 3933 err = azx_mixer_create(chip); 3934 if (err < 0) 3935 goto out_free; 3936 3937 err = snd_card_register(chip->card); 3938 if (err < 0) 3939 goto out_free; 3940 3941 chip->running = 1; 3942 power_down_all_codecs(chip); 3943 azx_notifier_register(chip); 3944 azx_add_card_list(chip); 3945 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo) 3946 pm_runtime_put_noidle(&pci->dev); 3947 3948 return 0; 3949 3950 out_free: 3951 chip->init_failed = 1; 3952 return err; 3953 } 3954 3955 static void azx_remove(struct pci_dev *pci) 3956 { 3957 struct snd_card *card = pci_get_drvdata(pci); 3958 3959 if (card) 3960 snd_card_free(card); 3961 } 3962 3963 /* PCI IDs */ 3964 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = { 3965 /* CPT */ 3966 { PCI_DEVICE(0x8086, 0x1c20), 3967 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 3968 /* PBG */ 3969 { PCI_DEVICE(0x8086, 0x1d20), 3970 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 3971 /* Panther Point */ 3972 { PCI_DEVICE(0x8086, 0x1e20), 3973 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 3974 /* Lynx Point */ 3975 { PCI_DEVICE(0x8086, 0x8c20), 3976 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 3977 /* Wellsburg */ 3978 { PCI_DEVICE(0x8086, 0x8d20), 3979 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 3980 { PCI_DEVICE(0x8086, 0x8d21), 3981 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 3982 /* Lynx Point-LP */ 3983 { PCI_DEVICE(0x8086, 0x9c20), 3984 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 3985 /* Lynx Point-LP */ 3986 { PCI_DEVICE(0x8086, 0x9c21), 3987 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 3988 /* Haswell */ 3989 { PCI_DEVICE(0x8086, 0x0a0c), 3990 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH | 3991 AZX_DCAPS_I915_POWERWELL }, 3992 { PCI_DEVICE(0x8086, 0x0c0c), 3993 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH | 3994 AZX_DCAPS_I915_POWERWELL }, 3995 { PCI_DEVICE(0x8086, 0x0d0c), 3996 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH | 3997 AZX_DCAPS_I915_POWERWELL }, 3998 /* 5 Series/3400 */ 3999 { PCI_DEVICE(0x8086, 0x3b56), 4000 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 4001 /* Poulsbo */ 4002 { PCI_DEVICE(0x8086, 0x811b), 4003 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 4004 /* Oaktrail */ 4005 { PCI_DEVICE(0x8086, 0x080a), 4006 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 4007 /* BayTrail */ 4008 { PCI_DEVICE(0x8086, 0x0f04), 4009 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 4010 /* ICH */ 4011 { PCI_DEVICE(0x8086, 0x2668), 4012 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 4013 AZX_DCAPS_BUFSIZE }, /* ICH6 */ 4014 { PCI_DEVICE(0x8086, 0x27d8), 4015 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 4016 AZX_DCAPS_BUFSIZE }, /* ICH7 */ 4017 { PCI_DEVICE(0x8086, 0x269a), 4018 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 4019 AZX_DCAPS_BUFSIZE }, /* ESB2 */ 4020 { PCI_DEVICE(0x8086, 0x284b), 4021 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 4022 AZX_DCAPS_BUFSIZE }, /* ICH8 */ 4023 { PCI_DEVICE(0x8086, 0x293e), 4024 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 4025 AZX_DCAPS_BUFSIZE }, /* ICH9 */ 4026 { PCI_DEVICE(0x8086, 0x293f), 4027 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 4028 AZX_DCAPS_BUFSIZE }, /* ICH9 */ 4029 { PCI_DEVICE(0x8086, 0x3a3e), 4030 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 4031 AZX_DCAPS_BUFSIZE }, /* ICH10 */ 4032 { PCI_DEVICE(0x8086, 0x3a6e), 4033 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 4034 AZX_DCAPS_BUFSIZE }, /* ICH10 */ 4035 /* Generic Intel */ 4036 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 4037 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 4038 .class_mask = 0xffffff, 4039 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE }, 4040 /* ATI SB 450/600/700/800/900 */ 4041 { PCI_DEVICE(0x1002, 0x437b), 4042 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 4043 { PCI_DEVICE(0x1002, 0x4383), 4044 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 4045 /* AMD Hudson */ 4046 { PCI_DEVICE(0x1022, 0x780d), 4047 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 4048 /* ATI HDMI */ 4049 { PCI_DEVICE(0x1002, 0x793b), 4050 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4051 { PCI_DEVICE(0x1002, 0x7919), 4052 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4053 { PCI_DEVICE(0x1002, 0x960f), 4054 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4055 { PCI_DEVICE(0x1002, 0x970f), 4056 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4057 { PCI_DEVICE(0x1002, 0xaa00), 4058 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4059 { PCI_DEVICE(0x1002, 0xaa08), 4060 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4061 { PCI_DEVICE(0x1002, 0xaa10), 4062 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4063 { PCI_DEVICE(0x1002, 0xaa18), 4064 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4065 { PCI_DEVICE(0x1002, 0xaa20), 4066 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4067 { PCI_DEVICE(0x1002, 0xaa28), 4068 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4069 { PCI_DEVICE(0x1002, 0xaa30), 4070 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4071 { PCI_DEVICE(0x1002, 0xaa38), 4072 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4073 { PCI_DEVICE(0x1002, 0xaa40), 4074 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4075 { PCI_DEVICE(0x1002, 0xaa48), 4076 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4077 { PCI_DEVICE(0x1002, 0x9902), 4078 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, 4079 { PCI_DEVICE(0x1002, 0xaaa0), 4080 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, 4081 { PCI_DEVICE(0x1002, 0xaaa8), 4082 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, 4083 { PCI_DEVICE(0x1002, 0xaab0), 4084 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, 4085 /* VIA VT8251/VT8237A */ 4086 { PCI_DEVICE(0x1106, 0x3288), 4087 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA }, 4088 /* VIA GFX VT7122/VX900 */ 4089 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 4090 /* VIA GFX VT6122/VX11 */ 4091 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 4092 /* SIS966 */ 4093 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 4094 /* ULI M5461 */ 4095 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 4096 /* NVIDIA MCP */ 4097 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 4098 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 4099 .class_mask = 0xffffff, 4100 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 4101 /* Teradici */ 4102 { PCI_DEVICE(0x6549, 0x1200), 4103 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 4104 { PCI_DEVICE(0x6549, 0x2200), 4105 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 4106 /* Creative X-Fi (CA0110-IBG) */ 4107 /* CTHDA chips */ 4108 { PCI_DEVICE(0x1102, 0x0010), 4109 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 4110 { PCI_DEVICE(0x1102, 0x0012), 4111 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 4112 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE) 4113 /* the following entry conflicts with snd-ctxfi driver, 4114 * as ctxfi driver mutates from HD-audio to native mode with 4115 * a special command sequence. 4116 */ 4117 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 4118 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 4119 .class_mask = 0xffffff, 4120 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 4121 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, 4122 #else 4123 /* this entry seems still valid -- i.e. without emu20kx chip */ 4124 { PCI_DEVICE(0x1102, 0x0009), 4125 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 4126 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, 4127 #endif 4128 /* Vortex86MX */ 4129 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 4130 /* VMware HDAudio */ 4131 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 4132 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 4133 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 4134 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 4135 .class_mask = 0xffffff, 4136 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 4137 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 4138 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 4139 .class_mask = 0xffffff, 4140 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 4141 { 0, } 4142 }; 4143 MODULE_DEVICE_TABLE(pci, azx_ids); 4144 4145 /* pci_driver definition */ 4146 static struct pci_driver azx_driver = { 4147 .name = KBUILD_MODNAME, 4148 .id_table = azx_ids, 4149 .probe = azx_probe, 4150 .remove = azx_remove, 4151 .driver = { 4152 .pm = AZX_PM_OPS, 4153 }, 4154 }; 4155 4156 module_pci_driver(azx_driver); 4157