1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * hda_intel.c - Implementation of primary alsa driver code base 5 * for Intel HD Audio. 6 * 7 * Copyright(c) 2004 Intel Corporation. All rights reserved. 8 * 9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 10 * PeiSen Hou <pshou@realtek.com.tw> 11 * 12 * CONTACTS: 13 * 14 * Matt Jared matt.jared@intel.com 15 * Andy Kopp andy.kopp@intel.com 16 * Dan Kogan dan.d.kogan@intel.com 17 * 18 * CHANGES: 19 * 20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/moduleparam.h> 29 #include <linux/init.h> 30 #include <linux/slab.h> 31 #include <linux/pci.h> 32 #include <linux/mutex.h> 33 #include <linux/io.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/clocksource.h> 36 #include <linux/time.h> 37 #include <linux/completion.h> 38 #include <linux/acpi.h> 39 #include <linux/pgtable.h> 40 41 #ifdef CONFIG_X86 42 /* for snoop control */ 43 #include <asm/set_memory.h> 44 #include <asm/cpufeature.h> 45 #endif 46 #include <sound/core.h> 47 #include <sound/initval.h> 48 #include <sound/hdaudio.h> 49 #include <sound/hda_i915.h> 50 #include <sound/intel-dsp-config.h> 51 #include <linux/vgaarb.h> 52 #include <linux/vga_switcheroo.h> 53 #include <linux/firmware.h> 54 #include <sound/hda_codec.h> 55 #include "hda_controller.h" 56 #include "hda_intel.h" 57 58 #define CREATE_TRACE_POINTS 59 #include "hda_intel_trace.h" 60 61 /* position fix mode */ 62 enum { 63 POS_FIX_AUTO, 64 POS_FIX_LPIB, 65 POS_FIX_POSBUF, 66 POS_FIX_VIACOMBO, 67 POS_FIX_COMBO, 68 POS_FIX_SKL, 69 POS_FIX_FIFO, 70 }; 71 72 /* Defines for ATI HD Audio support in SB450 south bridge */ 73 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 74 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 75 76 /* Defines for Nvidia HDA support */ 77 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 78 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 79 #define NVIDIA_HDA_ISTRM_COH 0x4d 80 #define NVIDIA_HDA_OSTRM_COH 0x4c 81 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 82 83 /* Defines for Intel SCH HDA snoop control */ 84 #define INTEL_HDA_CGCTL 0x48 85 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) 86 #define INTEL_SCH_HDA_DEVC 0x78 87 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 88 89 /* max number of SDs */ 90 /* ICH, ATI and VIA have 4 playback and 4 capture */ 91 #define ICH6_NUM_CAPTURE 4 92 #define ICH6_NUM_PLAYBACK 4 93 94 /* ULI has 6 playback and 5 capture */ 95 #define ULI_NUM_CAPTURE 5 96 #define ULI_NUM_PLAYBACK 6 97 98 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 99 #define ATIHDMI_NUM_CAPTURE 0 100 #define ATIHDMI_NUM_PLAYBACK 8 101 102 103 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 104 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 105 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 106 static char *model[SNDRV_CARDS]; 107 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 108 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 109 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 110 static int probe_only[SNDRV_CARDS]; 111 static int jackpoll_ms[SNDRV_CARDS]; 112 static int single_cmd = -1; 113 static int enable_msi = -1; 114 #ifdef CONFIG_SND_HDA_PATCH_LOADER 115 static char *patch[SNDRV_CARDS]; 116 #endif 117 #ifdef CONFIG_SND_HDA_INPUT_BEEP 118 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 119 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 120 #endif 121 static bool dmic_detect = 1; 122 123 module_param_array(index, int, NULL, 0444); 124 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 125 module_param_array(id, charp, NULL, 0444); 126 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 127 module_param_array(enable, bool, NULL, 0444); 128 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 129 module_param_array(model, charp, NULL, 0444); 130 MODULE_PARM_DESC(model, "Use the given board model."); 131 module_param_array(position_fix, int, NULL, 0444); 132 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 133 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO)."); 134 module_param_array(bdl_pos_adj, int, NULL, 0644); 135 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 136 module_param_array(probe_mask, int, NULL, 0444); 137 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 138 module_param_array(probe_only, int, NULL, 0444); 139 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 140 module_param_array(jackpoll_ms, int, NULL, 0444); 141 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 142 module_param(single_cmd, bint, 0444); 143 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 144 "(for debugging only)."); 145 module_param(enable_msi, bint, 0444); 146 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 147 #ifdef CONFIG_SND_HDA_PATCH_LOADER 148 module_param_array(patch, charp, NULL, 0444); 149 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 150 #endif 151 #ifdef CONFIG_SND_HDA_INPUT_BEEP 152 module_param_array(beep_mode, bool, NULL, 0444); 153 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 154 "(0=off, 1=on) (default=1)."); 155 #endif 156 module_param(dmic_detect, bool, 0444); 157 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) " 158 "(0=off, 1=on) (default=1); " 159 "deprecated, use snd-intel-dspcfg.dsp_driver option instead"); 160 161 #ifdef CONFIG_PM 162 static int param_set_xint(const char *val, const struct kernel_param *kp); 163 static const struct kernel_param_ops param_ops_xint = { 164 .set = param_set_xint, 165 .get = param_get_int, 166 }; 167 #define param_check_xint param_check_int 168 169 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 170 module_param(power_save, xint, 0644); 171 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 172 "(in second, 0 = disable)."); 173 174 static bool pm_blacklist = true; 175 module_param(pm_blacklist, bool, 0644); 176 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist"); 177 178 /* reset the HD-audio controller in power save mode. 179 * this may give more power-saving, but will take longer time to 180 * wake up. 181 */ 182 static bool power_save_controller = 1; 183 module_param(power_save_controller, bool, 0644); 184 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 185 #else 186 #define power_save 0 187 #endif /* CONFIG_PM */ 188 189 static int align_buffer_size = -1; 190 module_param(align_buffer_size, bint, 0644); 191 MODULE_PARM_DESC(align_buffer_size, 192 "Force buffer and period sizes to be multiple of 128 bytes."); 193 194 #ifdef CONFIG_X86 195 static int hda_snoop = -1; 196 module_param_named(snoop, hda_snoop, bint, 0444); 197 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 198 #else 199 #define hda_snoop true 200 #endif 201 202 203 MODULE_LICENSE("GPL"); 204 MODULE_DESCRIPTION("Intel HDA driver"); 205 206 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 207 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 208 #define SUPPORT_VGA_SWITCHEROO 209 #endif 210 #endif 211 212 213 /* 214 */ 215 216 /* driver types */ 217 enum { 218 AZX_DRIVER_ICH, 219 AZX_DRIVER_PCH, 220 AZX_DRIVER_SCH, 221 AZX_DRIVER_SKL, 222 AZX_DRIVER_HDMI, 223 AZX_DRIVER_ATI, 224 AZX_DRIVER_ATIHDMI, 225 AZX_DRIVER_ATIHDMI_NS, 226 AZX_DRIVER_VIA, 227 AZX_DRIVER_SIS, 228 AZX_DRIVER_ULI, 229 AZX_DRIVER_NVIDIA, 230 AZX_DRIVER_TERA, 231 AZX_DRIVER_CTX, 232 AZX_DRIVER_CTHDA, 233 AZX_DRIVER_CMEDIA, 234 AZX_DRIVER_ZHAOXIN, 235 AZX_DRIVER_GENERIC, 236 AZX_NUM_DRIVERS, /* keep this as last entry */ 237 }; 238 239 #define azx_get_snoop_type(chip) \ 240 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 241 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 242 243 /* quirks for old Intel chipsets */ 244 #define AZX_DCAPS_INTEL_ICH \ 245 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 246 247 /* quirks for Intel PCH */ 248 #define AZX_DCAPS_INTEL_PCH_BASE \ 249 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 250 AZX_DCAPS_SNOOP_TYPE(SCH)) 251 252 /* PCH up to IVB; no runtime PM; bind with i915 gfx */ 253 #define AZX_DCAPS_INTEL_PCH_NOPM \ 254 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 255 256 /* PCH for HSW/BDW; with runtime PM */ 257 /* no i915 binding for this as HSW/BDW has another controller for HDMI */ 258 #define AZX_DCAPS_INTEL_PCH \ 259 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) 260 261 /* HSW HDMI */ 262 #define AZX_DCAPS_INTEL_HASWELL \ 263 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 264 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 265 AZX_DCAPS_SNOOP_TYPE(SCH)) 266 267 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 268 #define AZX_DCAPS_INTEL_BROADWELL \ 269 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 270 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 271 AZX_DCAPS_SNOOP_TYPE(SCH)) 272 273 #define AZX_DCAPS_INTEL_BAYTRAIL \ 274 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 275 276 #define AZX_DCAPS_INTEL_BRASWELL \ 277 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 278 AZX_DCAPS_I915_COMPONENT) 279 280 #define AZX_DCAPS_INTEL_SKYLAKE \ 281 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 282 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT) 283 284 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE 285 286 /* quirks for ATI SB / AMD Hudson */ 287 #define AZX_DCAPS_PRESET_ATI_SB \ 288 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\ 289 AZX_DCAPS_SNOOP_TYPE(ATI)) 290 291 /* quirks for ATI/AMD HDMI */ 292 #define AZX_DCAPS_PRESET_ATI_HDMI \ 293 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\ 294 AZX_DCAPS_NO_MSI64) 295 296 /* quirks for ATI HDMI with snoop off */ 297 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 298 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 299 300 /* quirks for AMD SB */ 301 #define AZX_DCAPS_PRESET_AMD_SB \ 302 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\ 303 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\ 304 AZX_DCAPS_RETRY_PROBE) 305 306 /* quirks for Nvidia */ 307 #define AZX_DCAPS_PRESET_NVIDIA \ 308 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 309 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 310 311 #define AZX_DCAPS_PRESET_CTHDA \ 312 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 313 AZX_DCAPS_NO_64BIT |\ 314 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 315 316 /* 317 * vga_switcheroo support 318 */ 319 #ifdef SUPPORT_VGA_SWITCHEROO 320 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 321 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power) 322 #else 323 #define use_vga_switcheroo(chip) 0 324 #define needs_eld_notify_link(chip) false 325 #endif 326 327 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \ 328 ((pci)->device == 0x0c0c) || \ 329 ((pci)->device == 0x0d0c) || \ 330 ((pci)->device == 0x160c) || \ 331 ((pci)->device == 0x490d) || \ 332 ((pci)->device == 0x4f90) || \ 333 ((pci)->device == 0x4f91) || \ 334 ((pci)->device == 0x4f92)) 335 336 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98) 337 338 static const char * const driver_short_names[] = { 339 [AZX_DRIVER_ICH] = "HDA Intel", 340 [AZX_DRIVER_PCH] = "HDA Intel PCH", 341 [AZX_DRIVER_SCH] = "HDA Intel MID", 342 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */ 343 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 344 [AZX_DRIVER_ATI] = "HDA ATI SB", 345 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 346 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 347 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 348 [AZX_DRIVER_SIS] = "HDA SIS966", 349 [AZX_DRIVER_ULI] = "HDA ULI M5461", 350 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 351 [AZX_DRIVER_TERA] = "HDA Teradici", 352 [AZX_DRIVER_CTX] = "HDA Creative", 353 [AZX_DRIVER_CTHDA] = "HDA Creative", 354 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 355 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin", 356 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 357 }; 358 359 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 360 static void set_default_power_save(struct azx *chip); 361 362 /* 363 * initialize the PCI registers 364 */ 365 /* update bits in a PCI register byte */ 366 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 367 unsigned char mask, unsigned char val) 368 { 369 unsigned char data; 370 371 pci_read_config_byte(pci, reg, &data); 372 data &= ~mask; 373 data |= (val & mask); 374 pci_write_config_byte(pci, reg, data); 375 } 376 377 static void azx_init_pci(struct azx *chip) 378 { 379 int snoop_type = azx_get_snoop_type(chip); 380 381 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 382 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 383 * Ensuring these bits are 0 clears playback static on some HD Audio 384 * codecs. 385 * The PCI register TCSEL is defined in the Intel manuals. 386 */ 387 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 388 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 389 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 390 } 391 392 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 393 * we need to enable snoop. 394 */ 395 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 396 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 397 azx_snoop(chip)); 398 update_pci_byte(chip->pci, 399 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 400 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 401 } 402 403 /* For NVIDIA HDA, enable snoop */ 404 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 405 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 406 azx_snoop(chip)); 407 update_pci_byte(chip->pci, 408 NVIDIA_HDA_TRANSREG_ADDR, 409 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 410 update_pci_byte(chip->pci, 411 NVIDIA_HDA_ISTRM_COH, 412 0x01, NVIDIA_HDA_ENABLE_COHBIT); 413 update_pci_byte(chip->pci, 414 NVIDIA_HDA_OSTRM_COH, 415 0x01, NVIDIA_HDA_ENABLE_COHBIT); 416 } 417 418 /* Enable SCH/PCH snoop if needed */ 419 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 420 unsigned short snoop; 421 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 422 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 423 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 424 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 425 if (!azx_snoop(chip)) 426 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 427 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 428 pci_read_config_word(chip->pci, 429 INTEL_SCH_HDA_DEVC, &snoop); 430 } 431 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 432 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 433 "Disabled" : "Enabled"); 434 } 435 } 436 437 /* 438 * In BXT-P A0, HD-Audio DMA requests is later than expected, 439 * and makes an audio stream sensitive to system latencies when 440 * 24/32 bits are playing. 441 * Adjusting threshold of DMA fifo to force the DMA request 442 * sooner to improve latency tolerance at the expense of power. 443 */ 444 static void bxt_reduce_dma_latency(struct azx *chip) 445 { 446 u32 val; 447 448 val = azx_readl(chip, VS_EM4L); 449 val &= (0x3 << 20); 450 azx_writel(chip, VS_EM4L, val); 451 } 452 453 /* 454 * ML_LCAP bits: 455 * bit 0: 6 MHz Supported 456 * bit 1: 12 MHz Supported 457 * bit 2: 24 MHz Supported 458 * bit 3: 48 MHz Supported 459 * bit 4: 96 MHz Supported 460 * bit 5: 192 MHz Supported 461 */ 462 static int intel_get_lctl_scf(struct azx *chip) 463 { 464 struct hdac_bus *bus = azx_bus(chip); 465 static const int preferred_bits[] = { 2, 3, 1, 4, 5 }; 466 u32 val, t; 467 int i; 468 469 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); 470 471 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) { 472 t = preferred_bits[i]; 473 if (val & (1 << t)) 474 return t; 475 } 476 477 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz"); 478 return 0; 479 } 480 481 static int intel_ml_lctl_set_power(struct azx *chip, int state) 482 { 483 struct hdac_bus *bus = azx_bus(chip); 484 u32 val; 485 int timeout; 486 487 /* 488 * the codecs are sharing the first link setting by default 489 * If other links are enabled for stream, they need similar fix 490 */ 491 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 492 val &= ~AZX_ML_LCTL_SPA; 493 val |= state << AZX_ML_LCTL_SPA_SHIFT; 494 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 495 /* wait for CPA */ 496 timeout = 50; 497 while (timeout) { 498 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) & 499 AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT)) 500 return 0; 501 timeout--; 502 udelay(10); 503 } 504 505 return -1; 506 } 507 508 static void intel_init_lctl(struct azx *chip) 509 { 510 struct hdac_bus *bus = azx_bus(chip); 511 u32 val; 512 int ret; 513 514 /* 0. check lctl register value is correct or not */ 515 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 516 /* if SCF is already set, let's use it */ 517 if ((val & AZX_ML_LCTL_SCF) != 0) 518 return; 519 520 /* 521 * Before operating on SPA, CPA must match SPA. 522 * Any deviation may result in undefined behavior. 523 */ 524 if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) != 525 ((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT)) 526 return; 527 528 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */ 529 ret = intel_ml_lctl_set_power(chip, 0); 530 udelay(100); 531 if (ret) 532 goto set_spa; 533 534 /* 2. update SCF to select a properly audio clock*/ 535 val &= ~AZX_ML_LCTL_SCF; 536 val |= intel_get_lctl_scf(chip); 537 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 538 539 set_spa: 540 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */ 541 intel_ml_lctl_set_power(chip, 1); 542 udelay(100); 543 } 544 545 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 546 { 547 struct hdac_bus *bus = azx_bus(chip); 548 struct pci_dev *pci = chip->pci; 549 u32 val; 550 551 snd_hdac_set_codec_wakeup(bus, true); 552 if (chip->driver_type == AZX_DRIVER_SKL) { 553 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 554 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; 555 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 556 } 557 azx_init_chip(chip, full_reset); 558 if (chip->driver_type == AZX_DRIVER_SKL) { 559 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 560 val = val | INTEL_HDA_CGCTL_MISCBDCGE; 561 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 562 } 563 564 snd_hdac_set_codec_wakeup(bus, false); 565 566 /* reduce dma latency to avoid noise */ 567 if (IS_BXT(pci)) 568 bxt_reduce_dma_latency(chip); 569 570 if (bus->mlcap != NULL) 571 intel_init_lctl(chip); 572 } 573 574 /* calculate runtime delay from LPIB */ 575 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 576 unsigned int pos) 577 { 578 struct snd_pcm_substream *substream = azx_dev->core.substream; 579 int stream = substream->stream; 580 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 581 int delay; 582 583 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 584 delay = pos - lpib_pos; 585 else 586 delay = lpib_pos - pos; 587 if (delay < 0) { 588 if (delay >= azx_dev->core.delay_negative_threshold) 589 delay = 0; 590 else 591 delay += azx_dev->core.bufsize; 592 } 593 594 if (delay >= azx_dev->core.period_bytes) { 595 dev_info(chip->card->dev, 596 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 597 delay, azx_dev->core.period_bytes); 598 delay = 0; 599 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 600 chip->get_delay[stream] = NULL; 601 } 602 603 return bytes_to_frames(substream->runtime, delay); 604 } 605 606 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 607 608 /* called from IRQ */ 609 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 610 { 611 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 612 int ok; 613 614 ok = azx_position_ok(chip, azx_dev); 615 if (ok == 1) { 616 azx_dev->irq_pending = 0; 617 return ok; 618 } else if (ok == 0) { 619 /* bogus IRQ, process it later */ 620 azx_dev->irq_pending = 1; 621 schedule_work(&hda->irq_pending_work); 622 } 623 return 0; 624 } 625 626 #define display_power(chip, enable) \ 627 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable) 628 629 /* 630 * Check whether the current DMA position is acceptable for updating 631 * periods. Returns non-zero if it's OK. 632 * 633 * Many HD-audio controllers appear pretty inaccurate about 634 * the update-IRQ timing. The IRQ is issued before actually the 635 * data is processed. So, we need to process it afterwords in a 636 * workqueue. 637 * 638 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update 639 */ 640 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 641 { 642 struct snd_pcm_substream *substream = azx_dev->core.substream; 643 struct snd_pcm_runtime *runtime = substream->runtime; 644 int stream = substream->stream; 645 u32 wallclk; 646 unsigned int pos; 647 snd_pcm_uframes_t hwptr, target; 648 649 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 650 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 651 return -1; /* bogus (too early) interrupt */ 652 653 if (chip->get_position[stream]) 654 pos = chip->get_position[stream](chip, azx_dev); 655 else { /* use the position buffer as default */ 656 pos = azx_get_pos_posbuf(chip, azx_dev); 657 if (!pos || pos == (u32)-1) { 658 dev_info(chip->card->dev, 659 "Invalid position buffer, using LPIB read method instead.\n"); 660 chip->get_position[stream] = azx_get_pos_lpib; 661 if (chip->get_position[0] == azx_get_pos_lpib && 662 chip->get_position[1] == azx_get_pos_lpib) 663 azx_bus(chip)->use_posbuf = false; 664 pos = azx_get_pos_lpib(chip, azx_dev); 665 chip->get_delay[stream] = NULL; 666 } else { 667 chip->get_position[stream] = azx_get_pos_posbuf; 668 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 669 chip->get_delay[stream] = azx_get_delay_from_lpib; 670 } 671 } 672 673 if (pos >= azx_dev->core.bufsize) 674 pos = 0; 675 676 if (WARN_ONCE(!azx_dev->core.period_bytes, 677 "hda-intel: zero azx_dev->period_bytes")) 678 return -1; /* this shouldn't happen! */ 679 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 680 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 681 /* NG - it's below the first next period boundary */ 682 return chip->bdl_pos_adj ? 0 : -1; 683 azx_dev->core.start_wallclk += wallclk; 684 685 if (azx_dev->core.no_period_wakeup) 686 return 1; /* OK, no need to check period boundary */ 687 688 if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt) 689 return 1; /* OK, already in hwptr updating process */ 690 691 /* check whether the period gets really elapsed */ 692 pos = bytes_to_frames(runtime, pos); 693 hwptr = runtime->hw_ptr_base + pos; 694 if (hwptr < runtime->status->hw_ptr) 695 hwptr += runtime->buffer_size; 696 target = runtime->hw_ptr_interrupt + runtime->period_size; 697 if (hwptr < target) { 698 /* too early wakeup, process it later */ 699 return chip->bdl_pos_adj ? 0 : -1; 700 } 701 702 return 1; /* OK, it's fine */ 703 } 704 705 /* 706 * The work for pending PCM period updates. 707 */ 708 static void azx_irq_pending_work(struct work_struct *work) 709 { 710 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 711 struct azx *chip = &hda->chip; 712 struct hdac_bus *bus = azx_bus(chip); 713 struct hdac_stream *s; 714 int pending, ok; 715 716 if (!hda->irq_pending_warned) { 717 dev_info(chip->card->dev, 718 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 719 chip->card->number); 720 hda->irq_pending_warned = 1; 721 } 722 723 for (;;) { 724 pending = 0; 725 spin_lock_irq(&bus->reg_lock); 726 list_for_each_entry(s, &bus->stream_list, list) { 727 struct azx_dev *azx_dev = stream_to_azx_dev(s); 728 if (!azx_dev->irq_pending || 729 !s->substream || 730 !s->running) 731 continue; 732 ok = azx_position_ok(chip, azx_dev); 733 if (ok > 0) { 734 azx_dev->irq_pending = 0; 735 spin_unlock(&bus->reg_lock); 736 snd_pcm_period_elapsed(s->substream); 737 spin_lock(&bus->reg_lock); 738 } else if (ok < 0) { 739 pending = 0; /* too early */ 740 } else 741 pending++; 742 } 743 spin_unlock_irq(&bus->reg_lock); 744 if (!pending) 745 return; 746 msleep(1); 747 } 748 } 749 750 /* clear irq_pending flags and assure no on-going workq */ 751 static void azx_clear_irq_pending(struct azx *chip) 752 { 753 struct hdac_bus *bus = azx_bus(chip); 754 struct hdac_stream *s; 755 756 spin_lock_irq(&bus->reg_lock); 757 list_for_each_entry(s, &bus->stream_list, list) { 758 struct azx_dev *azx_dev = stream_to_azx_dev(s); 759 azx_dev->irq_pending = 0; 760 } 761 spin_unlock_irq(&bus->reg_lock); 762 } 763 764 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 765 { 766 struct hdac_bus *bus = azx_bus(chip); 767 768 if (request_irq(chip->pci->irq, azx_interrupt, 769 chip->msi ? 0 : IRQF_SHARED, 770 chip->card->irq_descr, chip)) { 771 dev_err(chip->card->dev, 772 "unable to grab IRQ %d, disabling device\n", 773 chip->pci->irq); 774 if (do_disconnect) 775 snd_card_disconnect(chip->card); 776 return -1; 777 } 778 bus->irq = chip->pci->irq; 779 chip->card->sync_irq = bus->irq; 780 pci_intx(chip->pci, !chip->msi); 781 return 0; 782 } 783 784 /* get the current DMA position with correction on VIA chips */ 785 static unsigned int azx_via_get_position(struct azx *chip, 786 struct azx_dev *azx_dev) 787 { 788 unsigned int link_pos, mini_pos, bound_pos; 789 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 790 unsigned int fifo_size; 791 792 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 793 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 794 /* Playback, no problem using link position */ 795 return link_pos; 796 } 797 798 /* Capture */ 799 /* For new chipset, 800 * use mod to get the DMA position just like old chipset 801 */ 802 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 803 mod_dma_pos %= azx_dev->core.period_bytes; 804 805 fifo_size = azx_stream(azx_dev)->fifo_size - 1; 806 807 if (azx_dev->insufficient) { 808 /* Link position never gather than FIFO size */ 809 if (link_pos <= fifo_size) 810 return 0; 811 812 azx_dev->insufficient = 0; 813 } 814 815 if (link_pos <= fifo_size) 816 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 817 else 818 mini_pos = link_pos - fifo_size; 819 820 /* Find nearest previous boudary */ 821 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 822 mod_link_pos = link_pos % azx_dev->core.period_bytes; 823 if (mod_link_pos >= fifo_size) 824 bound_pos = link_pos - mod_link_pos; 825 else if (mod_dma_pos >= mod_mini_pos) 826 bound_pos = mini_pos - mod_mini_pos; 827 else { 828 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 829 if (bound_pos >= azx_dev->core.bufsize) 830 bound_pos = 0; 831 } 832 833 /* Calculate real DMA position we want */ 834 return bound_pos + mod_dma_pos; 835 } 836 837 #define AMD_FIFO_SIZE 32 838 839 /* get the current DMA position with FIFO size correction */ 840 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev) 841 { 842 struct snd_pcm_substream *substream = azx_dev->core.substream; 843 struct snd_pcm_runtime *runtime = substream->runtime; 844 unsigned int pos, delay; 845 846 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 847 if (!runtime) 848 return pos; 849 850 runtime->delay = AMD_FIFO_SIZE; 851 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE); 852 if (azx_dev->insufficient) { 853 if (pos < delay) { 854 delay = pos; 855 runtime->delay = bytes_to_frames(runtime, pos); 856 } else { 857 azx_dev->insufficient = 0; 858 } 859 } 860 861 /* correct the DMA position for capture stream */ 862 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 863 if (pos < delay) 864 pos += azx_dev->core.bufsize; 865 pos -= delay; 866 } 867 868 return pos; 869 } 870 871 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev, 872 unsigned int pos) 873 { 874 struct snd_pcm_substream *substream = azx_dev->core.substream; 875 876 /* just read back the calculated value in the above */ 877 return substream->runtime->delay; 878 } 879 880 static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset) 881 { 882 azx_stop_chip(chip); 883 if (!skip_link_reset) 884 azx_enter_link_reset(chip); 885 azx_clear_irq_pending(chip); 886 display_power(chip, false); 887 } 888 889 #ifdef CONFIG_PM 890 static DEFINE_MUTEX(card_list_lock); 891 static LIST_HEAD(card_list); 892 893 static void azx_shutdown_chip(struct azx *chip) 894 { 895 __azx_shutdown_chip(chip, false); 896 } 897 898 static void azx_add_card_list(struct azx *chip) 899 { 900 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 901 mutex_lock(&card_list_lock); 902 list_add(&hda->list, &card_list); 903 mutex_unlock(&card_list_lock); 904 } 905 906 static void azx_del_card_list(struct azx *chip) 907 { 908 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 909 mutex_lock(&card_list_lock); 910 list_del_init(&hda->list); 911 mutex_unlock(&card_list_lock); 912 } 913 914 /* trigger power-save check at writing parameter */ 915 static int param_set_xint(const char *val, const struct kernel_param *kp) 916 { 917 struct hda_intel *hda; 918 struct azx *chip; 919 int prev = power_save; 920 int ret = param_set_int(val, kp); 921 922 if (ret || prev == power_save) 923 return ret; 924 925 mutex_lock(&card_list_lock); 926 list_for_each_entry(hda, &card_list, list) { 927 chip = &hda->chip; 928 if (!hda->probe_continued || chip->disabled) 929 continue; 930 snd_hda_set_power_save(&chip->bus, power_save * 1000); 931 } 932 mutex_unlock(&card_list_lock); 933 return 0; 934 } 935 936 /* 937 * power management 938 */ 939 static bool azx_is_pm_ready(struct snd_card *card) 940 { 941 struct azx *chip; 942 struct hda_intel *hda; 943 944 if (!card) 945 return false; 946 chip = card->private_data; 947 hda = container_of(chip, struct hda_intel, chip); 948 if (chip->disabled || hda->init_failed || !chip->running) 949 return false; 950 return true; 951 } 952 953 static void __azx_runtime_resume(struct azx *chip) 954 { 955 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 956 struct hdac_bus *bus = azx_bus(chip); 957 struct hda_codec *codec; 958 int status; 959 960 display_power(chip, true); 961 if (hda->need_i915_power) 962 snd_hdac_i915_set_bclk(bus); 963 964 /* Read STATESTS before controller reset */ 965 status = azx_readw(chip, STATESTS); 966 967 azx_init_pci(chip); 968 hda_intel_init_chip(chip, true); 969 970 /* Avoid codec resume if runtime resume is for system suspend */ 971 if (!chip->pm_prepared) { 972 list_for_each_codec(codec, &chip->bus) { 973 if (codec->relaxed_resume) 974 continue; 975 976 if (codec->forced_resume || (status & (1 << codec->addr))) 977 pm_request_resume(hda_codec_dev(codec)); 978 } 979 } 980 981 /* power down again for link-controlled chips */ 982 if (!hda->need_i915_power) 983 display_power(chip, false); 984 } 985 986 #ifdef CONFIG_PM_SLEEP 987 static int azx_prepare(struct device *dev) 988 { 989 struct snd_card *card = dev_get_drvdata(dev); 990 struct azx *chip; 991 992 if (!azx_is_pm_ready(card)) 993 return 0; 994 995 chip = card->private_data; 996 chip->pm_prepared = 1; 997 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 998 999 flush_work(&azx_bus(chip)->unsol_work); 1000 1001 /* HDA controller always requires different WAKEEN for runtime suspend 1002 * and system suspend, so don't use direct-complete here. 1003 */ 1004 return 0; 1005 } 1006 1007 static void azx_complete(struct device *dev) 1008 { 1009 struct snd_card *card = dev_get_drvdata(dev); 1010 struct azx *chip; 1011 1012 if (!azx_is_pm_ready(card)) 1013 return; 1014 1015 chip = card->private_data; 1016 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1017 chip->pm_prepared = 0; 1018 } 1019 1020 static int azx_suspend(struct device *dev) 1021 { 1022 struct snd_card *card = dev_get_drvdata(dev); 1023 struct azx *chip; 1024 struct hdac_bus *bus; 1025 1026 if (!azx_is_pm_ready(card)) 1027 return 0; 1028 1029 chip = card->private_data; 1030 bus = azx_bus(chip); 1031 azx_shutdown_chip(chip); 1032 if (bus->irq >= 0) { 1033 free_irq(bus->irq, chip); 1034 bus->irq = -1; 1035 chip->card->sync_irq = -1; 1036 } 1037 1038 if (chip->msi) 1039 pci_disable_msi(chip->pci); 1040 1041 trace_azx_suspend(chip); 1042 return 0; 1043 } 1044 1045 static int azx_resume(struct device *dev) 1046 { 1047 struct snd_card *card = dev_get_drvdata(dev); 1048 struct azx *chip; 1049 1050 if (!azx_is_pm_ready(card)) 1051 return 0; 1052 1053 chip = card->private_data; 1054 if (chip->msi) 1055 if (pci_enable_msi(chip->pci) < 0) 1056 chip->msi = 0; 1057 if (azx_acquire_irq(chip, 1) < 0) 1058 return -EIO; 1059 1060 __azx_runtime_resume(chip); 1061 1062 trace_azx_resume(chip); 1063 return 0; 1064 } 1065 1066 /* put codec down to D3 at hibernation for Intel SKL+; 1067 * otherwise BIOS may still access the codec and screw up the driver 1068 */ 1069 static int azx_freeze_noirq(struct device *dev) 1070 { 1071 struct snd_card *card = dev_get_drvdata(dev); 1072 struct azx *chip = card->private_data; 1073 struct pci_dev *pci = to_pci_dev(dev); 1074 1075 if (!azx_is_pm_ready(card)) 1076 return 0; 1077 if (chip->driver_type == AZX_DRIVER_SKL) 1078 pci_set_power_state(pci, PCI_D3hot); 1079 1080 return 0; 1081 } 1082 1083 static int azx_thaw_noirq(struct device *dev) 1084 { 1085 struct snd_card *card = dev_get_drvdata(dev); 1086 struct azx *chip = card->private_data; 1087 struct pci_dev *pci = to_pci_dev(dev); 1088 1089 if (!azx_is_pm_ready(card)) 1090 return 0; 1091 if (chip->driver_type == AZX_DRIVER_SKL) 1092 pci_set_power_state(pci, PCI_D0); 1093 1094 return 0; 1095 } 1096 #endif /* CONFIG_PM_SLEEP */ 1097 1098 static int azx_runtime_suspend(struct device *dev) 1099 { 1100 struct snd_card *card = dev_get_drvdata(dev); 1101 struct azx *chip; 1102 1103 if (!azx_is_pm_ready(card)) 1104 return 0; 1105 chip = card->private_data; 1106 1107 /* enable controller wake up event */ 1108 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK); 1109 1110 azx_shutdown_chip(chip); 1111 trace_azx_runtime_suspend(chip); 1112 return 0; 1113 } 1114 1115 static int azx_runtime_resume(struct device *dev) 1116 { 1117 struct snd_card *card = dev_get_drvdata(dev); 1118 struct azx *chip; 1119 1120 if (!azx_is_pm_ready(card)) 1121 return 0; 1122 chip = card->private_data; 1123 __azx_runtime_resume(chip); 1124 1125 /* disable controller Wake Up event*/ 1126 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK); 1127 1128 trace_azx_runtime_resume(chip); 1129 return 0; 1130 } 1131 1132 static int azx_runtime_idle(struct device *dev) 1133 { 1134 struct snd_card *card = dev_get_drvdata(dev); 1135 struct azx *chip; 1136 struct hda_intel *hda; 1137 1138 if (!card) 1139 return 0; 1140 1141 chip = card->private_data; 1142 hda = container_of(chip, struct hda_intel, chip); 1143 if (chip->disabled || hda->init_failed) 1144 return 0; 1145 1146 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1147 azx_bus(chip)->codec_powered || !chip->running) 1148 return -EBUSY; 1149 1150 /* ELD notification gets broken when HD-audio bus is off */ 1151 if (needs_eld_notify_link(chip)) 1152 return -EBUSY; 1153 1154 return 0; 1155 } 1156 1157 static const struct dev_pm_ops azx_pm = { 1158 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1159 #ifdef CONFIG_PM_SLEEP 1160 .prepare = azx_prepare, 1161 .complete = azx_complete, 1162 .freeze_noirq = azx_freeze_noirq, 1163 .thaw_noirq = azx_thaw_noirq, 1164 #endif 1165 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1166 }; 1167 1168 #define AZX_PM_OPS &azx_pm 1169 #else 1170 #define azx_add_card_list(chip) /* NOP */ 1171 #define azx_del_card_list(chip) /* NOP */ 1172 #define AZX_PM_OPS NULL 1173 #endif /* CONFIG_PM */ 1174 1175 1176 static int azx_probe_continue(struct azx *chip); 1177 1178 #ifdef SUPPORT_VGA_SWITCHEROO 1179 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1180 1181 static void azx_vs_set_state(struct pci_dev *pci, 1182 enum vga_switcheroo_state state) 1183 { 1184 struct snd_card *card = pci_get_drvdata(pci); 1185 struct azx *chip = card->private_data; 1186 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1187 struct hda_codec *codec; 1188 bool disabled; 1189 1190 wait_for_completion(&hda->probe_wait); 1191 if (hda->init_failed) 1192 return; 1193 1194 disabled = (state == VGA_SWITCHEROO_OFF); 1195 if (chip->disabled == disabled) 1196 return; 1197 1198 if (!hda->probe_continued) { 1199 chip->disabled = disabled; 1200 if (!disabled) { 1201 dev_info(chip->card->dev, 1202 "Start delayed initialization\n"); 1203 if (azx_probe_continue(chip) < 0) 1204 dev_err(chip->card->dev, "initialization error\n"); 1205 } 1206 } else { 1207 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1208 disabled ? "Disabling" : "Enabling"); 1209 if (disabled) { 1210 list_for_each_codec(codec, &chip->bus) { 1211 pm_runtime_suspend(hda_codec_dev(codec)); 1212 pm_runtime_disable(hda_codec_dev(codec)); 1213 } 1214 pm_runtime_suspend(card->dev); 1215 pm_runtime_disable(card->dev); 1216 /* when we get suspended by vga_switcheroo we end up in D3cold, 1217 * however we have no ACPI handle, so pci/acpi can't put us there, 1218 * put ourselves there */ 1219 pci->current_state = PCI_D3cold; 1220 chip->disabled = true; 1221 if (snd_hda_lock_devices(&chip->bus)) 1222 dev_warn(chip->card->dev, 1223 "Cannot lock devices!\n"); 1224 } else { 1225 snd_hda_unlock_devices(&chip->bus); 1226 chip->disabled = false; 1227 pm_runtime_enable(card->dev); 1228 list_for_each_codec(codec, &chip->bus) { 1229 pm_runtime_enable(hda_codec_dev(codec)); 1230 pm_runtime_resume(hda_codec_dev(codec)); 1231 } 1232 } 1233 } 1234 } 1235 1236 static bool azx_vs_can_switch(struct pci_dev *pci) 1237 { 1238 struct snd_card *card = pci_get_drvdata(pci); 1239 struct azx *chip = card->private_data; 1240 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1241 1242 wait_for_completion(&hda->probe_wait); 1243 if (hda->init_failed) 1244 return false; 1245 if (chip->disabled || !hda->probe_continued) 1246 return true; 1247 if (snd_hda_lock_devices(&chip->bus)) 1248 return false; 1249 snd_hda_unlock_devices(&chip->bus); 1250 return true; 1251 } 1252 1253 /* 1254 * The discrete GPU cannot power down unless the HDA controller runtime 1255 * suspends, so activate runtime PM on codecs even if power_save == 0. 1256 */ 1257 static void setup_vga_switcheroo_runtime_pm(struct azx *chip) 1258 { 1259 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1260 struct hda_codec *codec; 1261 1262 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) { 1263 list_for_each_codec(codec, &chip->bus) 1264 codec->auto_runtime_pm = 1; 1265 /* reset the power save setup */ 1266 if (chip->running) 1267 set_default_power_save(chip); 1268 } 1269 } 1270 1271 static void azx_vs_gpu_bound(struct pci_dev *pci, 1272 enum vga_switcheroo_client_id client_id) 1273 { 1274 struct snd_card *card = pci_get_drvdata(pci); 1275 struct azx *chip = card->private_data; 1276 1277 if (client_id == VGA_SWITCHEROO_DIS) 1278 chip->bus.keep_power = 0; 1279 setup_vga_switcheroo_runtime_pm(chip); 1280 } 1281 1282 static void init_vga_switcheroo(struct azx *chip) 1283 { 1284 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1285 struct pci_dev *p = get_bound_vga(chip->pci); 1286 struct pci_dev *parent; 1287 if (p) { 1288 dev_info(chip->card->dev, 1289 "Handle vga_switcheroo audio client\n"); 1290 hda->use_vga_switcheroo = 1; 1291 1292 /* cleared in either gpu_bound op or codec probe, or when its 1293 * upstream port has _PR3 (i.e. dGPU). 1294 */ 1295 parent = pci_upstream_bridge(p); 1296 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1; 1297 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; 1298 pci_dev_put(p); 1299 } 1300 } 1301 1302 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1303 .set_gpu_state = azx_vs_set_state, 1304 .can_switch = azx_vs_can_switch, 1305 .gpu_bound = azx_vs_gpu_bound, 1306 }; 1307 1308 static int register_vga_switcheroo(struct azx *chip) 1309 { 1310 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1311 struct pci_dev *p; 1312 int err; 1313 1314 if (!hda->use_vga_switcheroo) 1315 return 0; 1316 1317 p = get_bound_vga(chip->pci); 1318 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p); 1319 pci_dev_put(p); 1320 1321 if (err < 0) 1322 return err; 1323 hda->vga_switcheroo_registered = 1; 1324 1325 return 0; 1326 } 1327 #else 1328 #define init_vga_switcheroo(chip) /* NOP */ 1329 #define register_vga_switcheroo(chip) 0 1330 #define check_hdmi_disabled(pci) false 1331 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */ 1332 #endif /* SUPPORT_VGA_SWITCHER */ 1333 1334 /* 1335 * destructor 1336 */ 1337 static void azx_free(struct azx *chip) 1338 { 1339 struct pci_dev *pci = chip->pci; 1340 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1341 struct hdac_bus *bus = azx_bus(chip); 1342 1343 if (hda->freed) 1344 return; 1345 1346 if (azx_has_pm_runtime(chip) && chip->running) { 1347 pm_runtime_get_noresume(&pci->dev); 1348 pm_runtime_forbid(&pci->dev); 1349 pm_runtime_dont_use_autosuspend(&pci->dev); 1350 } 1351 1352 chip->running = 0; 1353 1354 azx_del_card_list(chip); 1355 1356 hda->init_failed = 1; /* to be sure */ 1357 complete_all(&hda->probe_wait); 1358 1359 if (use_vga_switcheroo(hda)) { 1360 if (chip->disabled && hda->probe_continued) 1361 snd_hda_unlock_devices(&chip->bus); 1362 if (hda->vga_switcheroo_registered) 1363 vga_switcheroo_unregister_client(chip->pci); 1364 } 1365 1366 if (bus->chip_init) { 1367 azx_clear_irq_pending(chip); 1368 azx_stop_all_streams(chip); 1369 azx_stop_chip(chip); 1370 } 1371 1372 if (bus->irq >= 0) 1373 free_irq(bus->irq, (void*)chip); 1374 1375 azx_free_stream_pages(chip); 1376 azx_free_streams(chip); 1377 snd_hdac_bus_exit(bus); 1378 1379 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1380 release_firmware(chip->fw); 1381 #endif 1382 display_power(chip, false); 1383 1384 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) 1385 snd_hdac_i915_exit(bus); 1386 1387 hda->freed = 1; 1388 } 1389 1390 static int azx_dev_disconnect(struct snd_device *device) 1391 { 1392 struct azx *chip = device->device_data; 1393 struct hdac_bus *bus = azx_bus(chip); 1394 1395 chip->bus.shutdown = 1; 1396 cancel_work_sync(&bus->unsol_work); 1397 1398 return 0; 1399 } 1400 1401 static int azx_dev_free(struct snd_device *device) 1402 { 1403 azx_free(device->device_data); 1404 return 0; 1405 } 1406 1407 #ifdef SUPPORT_VGA_SWITCHEROO 1408 #ifdef CONFIG_ACPI 1409 /* ATPX is in the integrated GPU's namespace */ 1410 static bool atpx_present(void) 1411 { 1412 struct pci_dev *pdev = NULL; 1413 acpi_handle dhandle, atpx_handle; 1414 acpi_status status; 1415 1416 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 1417 dhandle = ACPI_HANDLE(&pdev->dev); 1418 if (dhandle) { 1419 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1420 if (ACPI_SUCCESS(status)) { 1421 pci_dev_put(pdev); 1422 return true; 1423 } 1424 } 1425 } 1426 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 1427 dhandle = ACPI_HANDLE(&pdev->dev); 1428 if (dhandle) { 1429 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1430 if (ACPI_SUCCESS(status)) { 1431 pci_dev_put(pdev); 1432 return true; 1433 } 1434 } 1435 } 1436 return false; 1437 } 1438 #else 1439 static bool atpx_present(void) 1440 { 1441 return false; 1442 } 1443 #endif 1444 1445 /* 1446 * Check of disabled HDMI controller by vga_switcheroo 1447 */ 1448 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1449 { 1450 struct pci_dev *p; 1451 1452 /* check only discrete GPU */ 1453 switch (pci->vendor) { 1454 case PCI_VENDOR_ID_ATI: 1455 case PCI_VENDOR_ID_AMD: 1456 if (pci->devfn == 1) { 1457 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1458 pci->bus->number, 0); 1459 if (p) { 1460 /* ATPX is in the integrated GPU's ACPI namespace 1461 * rather than the dGPU's namespace. However, 1462 * the dGPU is the one who is involved in 1463 * vgaswitcheroo. 1464 */ 1465 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) && 1466 atpx_present()) 1467 return p; 1468 pci_dev_put(p); 1469 } 1470 } 1471 break; 1472 case PCI_VENDOR_ID_NVIDIA: 1473 if (pci->devfn == 1) { 1474 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1475 pci->bus->number, 0); 1476 if (p) { 1477 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) 1478 return p; 1479 pci_dev_put(p); 1480 } 1481 } 1482 break; 1483 } 1484 return NULL; 1485 } 1486 1487 static bool check_hdmi_disabled(struct pci_dev *pci) 1488 { 1489 bool vga_inactive = false; 1490 struct pci_dev *p = get_bound_vga(pci); 1491 1492 if (p) { 1493 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1494 vga_inactive = true; 1495 pci_dev_put(p); 1496 } 1497 return vga_inactive; 1498 } 1499 #endif /* SUPPORT_VGA_SWITCHEROO */ 1500 1501 /* 1502 * allow/deny-listing for position_fix 1503 */ 1504 static const struct snd_pci_quirk position_fix_list[] = { 1505 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1506 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1507 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1508 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1509 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1510 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1511 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1512 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1513 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1514 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1515 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1516 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1517 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1518 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1519 {} 1520 }; 1521 1522 static int check_position_fix(struct azx *chip, int fix) 1523 { 1524 const struct snd_pci_quirk *q; 1525 1526 switch (fix) { 1527 case POS_FIX_AUTO: 1528 case POS_FIX_LPIB: 1529 case POS_FIX_POSBUF: 1530 case POS_FIX_VIACOMBO: 1531 case POS_FIX_COMBO: 1532 case POS_FIX_SKL: 1533 case POS_FIX_FIFO: 1534 return fix; 1535 } 1536 1537 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1538 if (q) { 1539 dev_info(chip->card->dev, 1540 "position_fix set to %d for device %04x:%04x\n", 1541 q->value, q->subvendor, q->subdevice); 1542 return q->value; 1543 } 1544 1545 /* Check VIA/ATI HD Audio Controller exist */ 1546 if (chip->driver_type == AZX_DRIVER_VIA) { 1547 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1548 return POS_FIX_VIACOMBO; 1549 } 1550 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) { 1551 dev_dbg(chip->card->dev, "Using FIFO position fix\n"); 1552 return POS_FIX_FIFO; 1553 } 1554 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1555 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1556 return POS_FIX_LPIB; 1557 } 1558 if (chip->driver_type == AZX_DRIVER_SKL) { 1559 dev_dbg(chip->card->dev, "Using SKL position fix\n"); 1560 return POS_FIX_SKL; 1561 } 1562 return POS_FIX_AUTO; 1563 } 1564 1565 static void assign_position_fix(struct azx *chip, int fix) 1566 { 1567 static const azx_get_pos_callback_t callbacks[] = { 1568 [POS_FIX_AUTO] = NULL, 1569 [POS_FIX_LPIB] = azx_get_pos_lpib, 1570 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1571 [POS_FIX_VIACOMBO] = azx_via_get_position, 1572 [POS_FIX_COMBO] = azx_get_pos_lpib, 1573 [POS_FIX_SKL] = azx_get_pos_posbuf, 1574 [POS_FIX_FIFO] = azx_get_pos_fifo, 1575 }; 1576 1577 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1578 1579 /* combo mode uses LPIB only for playback */ 1580 if (fix == POS_FIX_COMBO) 1581 chip->get_position[1] = NULL; 1582 1583 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) && 1584 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1585 chip->get_delay[0] = chip->get_delay[1] = 1586 azx_get_delay_from_lpib; 1587 } 1588 1589 if (fix == POS_FIX_FIFO) 1590 chip->get_delay[0] = chip->get_delay[1] = 1591 azx_get_delay_from_fifo; 1592 } 1593 1594 /* 1595 * deny-lists for probe_mask 1596 */ 1597 static const struct snd_pci_quirk probe_mask_list[] = { 1598 /* Thinkpad often breaks the controller communication when accessing 1599 * to the non-working (or non-existing) modem codec slot. 1600 */ 1601 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1602 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1603 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1604 /* broken BIOS */ 1605 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1606 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1607 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1608 /* forced codec slots */ 1609 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1610 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1611 SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105), 1612 /* WinFast VP200 H (Teradici) user reported broken communication */ 1613 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1614 {} 1615 }; 1616 1617 #define AZX_FORCE_CODEC_MASK 0x100 1618 1619 static void check_probe_mask(struct azx *chip, int dev) 1620 { 1621 const struct snd_pci_quirk *q; 1622 1623 chip->codec_probe_mask = probe_mask[dev]; 1624 if (chip->codec_probe_mask == -1) { 1625 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1626 if (q) { 1627 dev_info(chip->card->dev, 1628 "probe_mask set to 0x%x for device %04x:%04x\n", 1629 q->value, q->subvendor, q->subdevice); 1630 chip->codec_probe_mask = q->value; 1631 } 1632 } 1633 1634 /* check forced option */ 1635 if (chip->codec_probe_mask != -1 && 1636 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1637 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1638 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1639 (int)azx_bus(chip)->codec_mask); 1640 } 1641 } 1642 1643 /* 1644 * allow/deny-list for enable_msi 1645 */ 1646 static const struct snd_pci_quirk msi_deny_list[] = { 1647 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1648 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1649 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1650 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1651 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1652 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1653 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1654 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1655 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1656 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1657 {} 1658 }; 1659 1660 static void check_msi(struct azx *chip) 1661 { 1662 const struct snd_pci_quirk *q; 1663 1664 if (enable_msi >= 0) { 1665 chip->msi = !!enable_msi; 1666 return; 1667 } 1668 chip->msi = 1; /* enable MSI as default */ 1669 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list); 1670 if (q) { 1671 dev_info(chip->card->dev, 1672 "msi for device %04x:%04x set to %d\n", 1673 q->subvendor, q->subdevice, q->value); 1674 chip->msi = q->value; 1675 return; 1676 } 1677 1678 /* NVidia chipsets seem to cause troubles with MSI */ 1679 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1680 dev_info(chip->card->dev, "Disabling MSI\n"); 1681 chip->msi = 0; 1682 } 1683 } 1684 1685 /* check the snoop mode availability */ 1686 static void azx_check_snoop_available(struct azx *chip) 1687 { 1688 int snoop = hda_snoop; 1689 1690 if (snoop >= 0) { 1691 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1692 snoop ? "snoop" : "non-snoop"); 1693 chip->snoop = snoop; 1694 chip->uc_buffer = !snoop; 1695 return; 1696 } 1697 1698 snoop = true; 1699 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1700 chip->driver_type == AZX_DRIVER_VIA) { 1701 /* force to non-snoop mode for a new VIA controller 1702 * when BIOS is set 1703 */ 1704 u8 val; 1705 pci_read_config_byte(chip->pci, 0x42, &val); 1706 if (!(val & 0x80) && (chip->pci->revision == 0x30 || 1707 chip->pci->revision == 0x20)) 1708 snoop = false; 1709 } 1710 1711 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1712 snoop = false; 1713 1714 chip->snoop = snoop; 1715 if (!snoop) { 1716 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1717 /* C-Media requires non-cached pages only for CORB/RIRB */ 1718 if (chip->driver_type != AZX_DRIVER_CMEDIA) 1719 chip->uc_buffer = true; 1720 } 1721 } 1722 1723 static void azx_probe_work(struct work_struct *work) 1724 { 1725 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work); 1726 azx_probe_continue(&hda->chip); 1727 } 1728 1729 static int default_bdl_pos_adj(struct azx *chip) 1730 { 1731 /* some exceptions: Atoms seem problematic with value 1 */ 1732 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { 1733 switch (chip->pci->device) { 1734 case 0x0f04: /* Baytrail */ 1735 case 0x2284: /* Braswell */ 1736 return 32; 1737 } 1738 } 1739 1740 switch (chip->driver_type) { 1741 case AZX_DRIVER_ICH: 1742 case AZX_DRIVER_PCH: 1743 return 1; 1744 default: 1745 return 32; 1746 } 1747 } 1748 1749 /* 1750 * constructor 1751 */ 1752 static const struct hda_controller_ops pci_hda_ops; 1753 1754 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1755 int dev, unsigned int driver_caps, 1756 struct azx **rchip) 1757 { 1758 static const struct snd_device_ops ops = { 1759 .dev_disconnect = azx_dev_disconnect, 1760 .dev_free = azx_dev_free, 1761 }; 1762 struct hda_intel *hda; 1763 struct azx *chip; 1764 int err; 1765 1766 *rchip = NULL; 1767 1768 err = pcim_enable_device(pci); 1769 if (err < 0) 1770 return err; 1771 1772 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL); 1773 if (!hda) 1774 return -ENOMEM; 1775 1776 chip = &hda->chip; 1777 mutex_init(&chip->open_mutex); 1778 chip->card = card; 1779 chip->pci = pci; 1780 chip->ops = &pci_hda_ops; 1781 chip->driver_caps = driver_caps; 1782 chip->driver_type = driver_caps & 0xff; 1783 check_msi(chip); 1784 chip->dev_index = dev; 1785 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000) 1786 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]); 1787 INIT_LIST_HEAD(&chip->pcm_list); 1788 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1789 INIT_LIST_HEAD(&hda->list); 1790 init_vga_switcheroo(chip); 1791 init_completion(&hda->probe_wait); 1792 1793 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1794 1795 if (single_cmd < 0) /* allow fallback to single_cmd at errors */ 1796 chip->fallback_to_single_cmd = 1; 1797 else /* explicitly set to single_cmd or not */ 1798 chip->single_cmd = single_cmd; 1799 1800 azx_check_snoop_available(chip); 1801 1802 if (bdl_pos_adj[dev] < 0) 1803 chip->bdl_pos_adj = default_bdl_pos_adj(chip); 1804 else 1805 chip->bdl_pos_adj = bdl_pos_adj[dev]; 1806 1807 err = azx_bus_init(chip, model[dev]); 1808 if (err < 0) 1809 return err; 1810 1811 /* use the non-cached pages in non-snoop mode */ 1812 if (!azx_snoop(chip)) 1813 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC_SG; 1814 1815 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 1816 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); 1817 chip->bus.core.needs_damn_long_delay = 1; 1818 } 1819 1820 check_probe_mask(chip, dev); 1821 1822 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1823 if (err < 0) { 1824 dev_err(card->dev, "Error creating device [card]!\n"); 1825 azx_free(chip); 1826 return err; 1827 } 1828 1829 /* continue probing in work context as may trigger request module */ 1830 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work); 1831 1832 *rchip = chip; 1833 1834 return 0; 1835 } 1836 1837 static int azx_first_init(struct azx *chip) 1838 { 1839 int dev = chip->dev_index; 1840 struct pci_dev *pci = chip->pci; 1841 struct snd_card *card = chip->card; 1842 struct hdac_bus *bus = azx_bus(chip); 1843 int err; 1844 unsigned short gcap; 1845 unsigned int dma_bits = 64; 1846 1847 #if BITS_PER_LONG != 64 1848 /* Fix up base address on ULI M5461 */ 1849 if (chip->driver_type == AZX_DRIVER_ULI) { 1850 u16 tmp3; 1851 pci_read_config_word(pci, 0x40, &tmp3); 1852 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1853 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1854 } 1855 #endif 1856 1857 err = pcim_iomap_regions(pci, 1 << 0, "ICH HD audio"); 1858 if (err < 0) 1859 return err; 1860 1861 bus->addr = pci_resource_start(pci, 0); 1862 bus->remap_addr = pcim_iomap_table(pci)[0]; 1863 1864 if (chip->driver_type == AZX_DRIVER_SKL) 1865 snd_hdac_bus_parse_capabilities(bus); 1866 1867 /* 1868 * Some Intel CPUs has always running timer (ART) feature and 1869 * controller may have Global time sync reporting capability, so 1870 * check both of these before declaring synchronized time reporting 1871 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 1872 */ 1873 chip->gts_present = false; 1874 1875 #ifdef CONFIG_X86 1876 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART)) 1877 chip->gts_present = true; 1878 #endif 1879 1880 if (chip->msi) { 1881 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1882 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1883 pci->no_64bit_msi = true; 1884 } 1885 if (pci_enable_msi(pci) < 0) 1886 chip->msi = 0; 1887 } 1888 1889 pci_set_master(pci); 1890 1891 gcap = azx_readw(chip, GCAP); 1892 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1893 1894 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1895 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1896 dma_bits = 40; 1897 1898 /* disable SB600 64bit support for safety */ 1899 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1900 struct pci_dev *p_smbus; 1901 dma_bits = 40; 1902 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1903 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1904 NULL); 1905 if (p_smbus) { 1906 if (p_smbus->revision < 0x30) 1907 gcap &= ~AZX_GCAP_64OK; 1908 pci_dev_put(p_smbus); 1909 } 1910 } 1911 1912 /* NVidia hardware normally only supports up to 40 bits of DMA */ 1913 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) 1914 dma_bits = 40; 1915 1916 /* disable 64bit DMA address on some devices */ 1917 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1918 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1919 gcap &= ~AZX_GCAP_64OK; 1920 } 1921 1922 /* disable buffer size rounding to 128-byte multiples if supported */ 1923 if (align_buffer_size >= 0) 1924 chip->align_buffer_size = !!align_buffer_size; 1925 else { 1926 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1927 chip->align_buffer_size = 0; 1928 else 1929 chip->align_buffer_size = 1; 1930 } 1931 1932 /* allow 64bit DMA address if supported by H/W */ 1933 if (!(gcap & AZX_GCAP_64OK)) 1934 dma_bits = 32; 1935 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits))) 1936 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); 1937 dma_set_max_seg_size(&pci->dev, UINT_MAX); 1938 1939 /* read number of streams from GCAP register instead of using 1940 * hardcoded value 1941 */ 1942 chip->capture_streams = (gcap >> 8) & 0x0f; 1943 chip->playback_streams = (gcap >> 12) & 0x0f; 1944 if (!chip->playback_streams && !chip->capture_streams) { 1945 /* gcap didn't give any info, switching to old method */ 1946 1947 switch (chip->driver_type) { 1948 case AZX_DRIVER_ULI: 1949 chip->playback_streams = ULI_NUM_PLAYBACK; 1950 chip->capture_streams = ULI_NUM_CAPTURE; 1951 break; 1952 case AZX_DRIVER_ATIHDMI: 1953 case AZX_DRIVER_ATIHDMI_NS: 1954 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1955 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1956 break; 1957 case AZX_DRIVER_GENERIC: 1958 default: 1959 chip->playback_streams = ICH6_NUM_PLAYBACK; 1960 chip->capture_streams = ICH6_NUM_CAPTURE; 1961 break; 1962 } 1963 } 1964 chip->capture_index_offset = 0; 1965 chip->playback_index_offset = chip->capture_streams; 1966 chip->num_streams = chip->playback_streams + chip->capture_streams; 1967 1968 /* sanity check for the SDxCTL.STRM field overflow */ 1969 if (chip->num_streams > 15 && 1970 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) { 1971 dev_warn(chip->card->dev, "number of I/O streams is %d, " 1972 "forcing separate stream tags", chip->num_streams); 1973 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG; 1974 } 1975 1976 /* initialize streams */ 1977 err = azx_init_streams(chip); 1978 if (err < 0) 1979 return err; 1980 1981 err = azx_alloc_stream_pages(chip); 1982 if (err < 0) 1983 return err; 1984 1985 /* initialize chip */ 1986 azx_init_pci(chip); 1987 1988 snd_hdac_i915_set_bclk(bus); 1989 1990 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 1991 1992 /* codec detection */ 1993 if (!azx_bus(chip)->codec_mask) { 1994 dev_err(card->dev, "no codecs found!\n"); 1995 /* keep running the rest for the runtime PM */ 1996 } 1997 1998 if (azx_acquire_irq(chip, 0) < 0) 1999 return -EBUSY; 2000 2001 strcpy(card->driver, "HDA-Intel"); 2002 strscpy(card->shortname, driver_short_names[chip->driver_type], 2003 sizeof(card->shortname)); 2004 snprintf(card->longname, sizeof(card->longname), 2005 "%s at 0x%lx irq %i", 2006 card->shortname, bus->addr, bus->irq); 2007 2008 return 0; 2009 } 2010 2011 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2012 /* callback from request_firmware_nowait() */ 2013 static void azx_firmware_cb(const struct firmware *fw, void *context) 2014 { 2015 struct snd_card *card = context; 2016 struct azx *chip = card->private_data; 2017 2018 if (fw) 2019 chip->fw = fw; 2020 else 2021 dev_err(card->dev, "Cannot load firmware, continue without patching\n"); 2022 if (!chip->disabled) { 2023 /* continue probing */ 2024 azx_probe_continue(chip); 2025 } 2026 } 2027 #endif 2028 2029 static int disable_msi_reset_irq(struct azx *chip) 2030 { 2031 struct hdac_bus *bus = azx_bus(chip); 2032 int err; 2033 2034 free_irq(bus->irq, chip); 2035 bus->irq = -1; 2036 chip->card->sync_irq = -1; 2037 pci_disable_msi(chip->pci); 2038 chip->msi = 0; 2039 err = azx_acquire_irq(chip, 1); 2040 if (err < 0) 2041 return err; 2042 2043 return 0; 2044 } 2045 2046 /* Denylist for skipping the whole probe: 2047 * some HD-audio PCI entries are exposed without any codecs, and such devices 2048 * should be ignored from the beginning. 2049 */ 2050 static const struct pci_device_id driver_denylist[] = { 2051 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */ 2052 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */ 2053 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */ 2054 {} 2055 }; 2056 2057 static const struct hda_controller_ops pci_hda_ops = { 2058 .disable_msi_reset_irq = disable_msi_reset_irq, 2059 .position_check = azx_position_check, 2060 }; 2061 2062 static DECLARE_BITMAP(probed_devs, SNDRV_CARDS); 2063 2064 static int azx_probe(struct pci_dev *pci, 2065 const struct pci_device_id *pci_id) 2066 { 2067 struct snd_card *card; 2068 struct hda_intel *hda; 2069 struct azx *chip; 2070 bool schedule_probe; 2071 int dev; 2072 int err; 2073 2074 if (pci_match_id(driver_denylist, pci)) { 2075 dev_info(&pci->dev, "Skipping the device on the denylist\n"); 2076 return -ENODEV; 2077 } 2078 2079 dev = find_first_zero_bit(probed_devs, SNDRV_CARDS); 2080 if (dev >= SNDRV_CARDS) 2081 return -ENODEV; 2082 if (!enable[dev]) { 2083 set_bit(dev, probed_devs); 2084 return -ENOENT; 2085 } 2086 2087 /* 2088 * stop probe if another Intel's DSP driver should be activated 2089 */ 2090 if (dmic_detect) { 2091 err = snd_intel_dsp_driver_probe(pci); 2092 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) { 2093 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n"); 2094 return -ENODEV; 2095 } 2096 } else { 2097 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n"); 2098 } 2099 2100 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2101 0, &card); 2102 if (err < 0) { 2103 dev_err(&pci->dev, "Error creating card!\n"); 2104 return err; 2105 } 2106 2107 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2108 if (err < 0) 2109 goto out_free; 2110 card->private_data = chip; 2111 hda = container_of(chip, struct hda_intel, chip); 2112 2113 pci_set_drvdata(pci, card); 2114 2115 err = register_vga_switcheroo(chip); 2116 if (err < 0) { 2117 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 2118 goto out_free; 2119 } 2120 2121 if (check_hdmi_disabled(pci)) { 2122 dev_info(card->dev, "VGA controller is disabled\n"); 2123 dev_info(card->dev, "Delaying initialization\n"); 2124 chip->disabled = true; 2125 } 2126 2127 schedule_probe = !chip->disabled; 2128 2129 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2130 if (patch[dev] && *patch[dev]) { 2131 dev_info(card->dev, "Applying patch firmware '%s'\n", 2132 patch[dev]); 2133 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 2134 &pci->dev, GFP_KERNEL, card, 2135 azx_firmware_cb); 2136 if (err < 0) 2137 goto out_free; 2138 schedule_probe = false; /* continued in azx_firmware_cb() */ 2139 } 2140 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 2141 2142 #ifndef CONFIG_SND_HDA_I915 2143 if (CONTROLLER_IN_GPU(pci)) 2144 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); 2145 #endif 2146 2147 if (schedule_probe) 2148 schedule_delayed_work(&hda->probe_work, 0); 2149 2150 set_bit(dev, probed_devs); 2151 if (chip->disabled) 2152 complete_all(&hda->probe_wait); 2153 return 0; 2154 2155 out_free: 2156 snd_card_free(card); 2157 return err; 2158 } 2159 2160 #ifdef CONFIG_PM 2161 /* On some boards setting power_save to a non 0 value leads to clicking / 2162 * popping sounds when ever we enter/leave powersaving mode. Ideally we would 2163 * figure out how to avoid these sounds, but that is not always feasible. 2164 * So we keep a list of devices where we disable powersaving as its known 2165 * to causes problems on these devices. 2166 */ 2167 static const struct snd_pci_quirk power_save_denylist[] = { 2168 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2169 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0), 2170 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2171 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0), 2172 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2173 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0), 2174 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2175 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0), 2176 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2177 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0), 2178 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2179 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ 2180 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0), 2181 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2182 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0), 2183 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */ 2184 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0), 2185 /* https://bugs.launchpad.net/bugs/1821663 */ 2186 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0), 2187 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */ 2188 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), 2189 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ 2190 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), 2191 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ 2192 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), 2193 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ 2194 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0), 2195 /* https://bugs.launchpad.net/bugs/1821663 */ 2196 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0), 2197 {} 2198 }; 2199 #endif /* CONFIG_PM */ 2200 2201 static void set_default_power_save(struct azx *chip) 2202 { 2203 int val = power_save; 2204 2205 #ifdef CONFIG_PM 2206 if (pm_blacklist) { 2207 const struct snd_pci_quirk *q; 2208 2209 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist); 2210 if (q && val) { 2211 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n", 2212 q->subvendor, q->subdevice); 2213 val = 0; 2214 } 2215 } 2216 #endif /* CONFIG_PM */ 2217 snd_hda_set_power_save(&chip->bus, val * 1000); 2218 } 2219 2220 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 2221 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 2222 [AZX_DRIVER_NVIDIA] = 8, 2223 [AZX_DRIVER_TERA] = 1, 2224 }; 2225 2226 static int azx_probe_continue(struct azx *chip) 2227 { 2228 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2229 struct hdac_bus *bus = azx_bus(chip); 2230 struct pci_dev *pci = chip->pci; 2231 int dev = chip->dev_index; 2232 int err; 2233 2234 if (chip->disabled || hda->init_failed) 2235 return -EIO; 2236 if (hda->probe_retry) 2237 goto probe_retry; 2238 2239 to_hda_bus(bus)->bus_probing = 1; 2240 hda->probe_continued = 1; 2241 2242 /* bind with i915 if needed */ 2243 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) { 2244 err = snd_hdac_i915_init(bus); 2245 if (err < 0) { 2246 /* if the controller is bound only with HDMI/DP 2247 * (for HSW and BDW), we need to abort the probe; 2248 * for other chips, still continue probing as other 2249 * codecs can be on the same link. 2250 */ 2251 if (CONTROLLER_IN_GPU(pci)) { 2252 dev_err(chip->card->dev, 2253 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); 2254 goto out_free; 2255 } else { 2256 /* don't bother any longer */ 2257 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT; 2258 } 2259 } 2260 2261 /* HSW/BDW controllers need this power */ 2262 if (CONTROLLER_IN_GPU(pci)) 2263 hda->need_i915_power = true; 2264 } 2265 2266 /* Request display power well for the HDA controller or codec. For 2267 * Haswell/Broadwell, both the display HDA controller and codec need 2268 * this power. For other platforms, like Baytrail/Braswell, only the 2269 * display codec needs the power and it can be released after probe. 2270 */ 2271 display_power(chip, true); 2272 2273 err = azx_first_init(chip); 2274 if (err < 0) 2275 goto out_free; 2276 2277 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2278 chip->beep_mode = beep_mode[dev]; 2279 #endif 2280 2281 /* create codec instances */ 2282 if (bus->codec_mask) { 2283 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2284 if (err < 0) 2285 goto out_free; 2286 } 2287 2288 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2289 if (chip->fw) { 2290 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2291 chip->fw->data); 2292 if (err < 0) 2293 goto out_free; 2294 #ifndef CONFIG_PM 2295 release_firmware(chip->fw); /* no longer needed */ 2296 chip->fw = NULL; 2297 #endif 2298 } 2299 #endif 2300 2301 probe_retry: 2302 if (bus->codec_mask && !(probe_only[dev] & 1)) { 2303 err = azx_codec_configure(chip); 2304 if (err) { 2305 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) && 2306 ++hda->probe_retry < 60) { 2307 schedule_delayed_work(&hda->probe_work, 2308 msecs_to_jiffies(1000)); 2309 return 0; /* keep things up */ 2310 } 2311 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n"); 2312 goto out_free; 2313 } 2314 } 2315 2316 err = snd_card_register(chip->card); 2317 if (err < 0) 2318 goto out_free; 2319 2320 setup_vga_switcheroo_runtime_pm(chip); 2321 2322 chip->running = 1; 2323 azx_add_card_list(chip); 2324 2325 set_default_power_save(chip); 2326 2327 if (azx_has_pm_runtime(chip)) { 2328 pm_runtime_use_autosuspend(&pci->dev); 2329 pm_runtime_allow(&pci->dev); 2330 pm_runtime_put_autosuspend(&pci->dev); 2331 } 2332 2333 out_free: 2334 if (err < 0) { 2335 pci_set_drvdata(pci, NULL); 2336 snd_card_free(chip->card); 2337 return err; 2338 } 2339 2340 if (!hda->need_i915_power) 2341 display_power(chip, false); 2342 complete_all(&hda->probe_wait); 2343 to_hda_bus(bus)->bus_probing = 0; 2344 hda->probe_retry = 0; 2345 return 0; 2346 } 2347 2348 static void azx_remove(struct pci_dev *pci) 2349 { 2350 struct snd_card *card = pci_get_drvdata(pci); 2351 struct azx *chip; 2352 struct hda_intel *hda; 2353 2354 if (card) { 2355 /* cancel the pending probing work */ 2356 chip = card->private_data; 2357 hda = container_of(chip, struct hda_intel, chip); 2358 /* FIXME: below is an ugly workaround. 2359 * Both device_release_driver() and driver_probe_device() 2360 * take *both* the device's and its parent's lock before 2361 * calling the remove() and probe() callbacks. The codec 2362 * probe takes the locks of both the codec itself and its 2363 * parent, i.e. the PCI controller dev. Meanwhile, when 2364 * the PCI controller is unbound, it takes its lock, too 2365 * ==> ouch, a deadlock! 2366 * As a workaround, we unlock temporarily here the controller 2367 * device during cancel_work_sync() call. 2368 */ 2369 device_unlock(&pci->dev); 2370 cancel_delayed_work_sync(&hda->probe_work); 2371 device_lock(&pci->dev); 2372 2373 clear_bit(chip->dev_index, probed_devs); 2374 pci_set_drvdata(pci, NULL); 2375 snd_card_free(card); 2376 } 2377 } 2378 2379 static void azx_shutdown(struct pci_dev *pci) 2380 { 2381 struct snd_card *card = pci_get_drvdata(pci); 2382 struct azx *chip; 2383 2384 if (!card) 2385 return; 2386 chip = card->private_data; 2387 if (chip && chip->running) 2388 __azx_shutdown_chip(chip, true); 2389 } 2390 2391 /* PCI IDs */ 2392 static const struct pci_device_id azx_ids[] = { 2393 /* CPT */ 2394 { PCI_DEVICE(0x8086, 0x1c20), 2395 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2396 /* PBG */ 2397 { PCI_DEVICE(0x8086, 0x1d20), 2398 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2399 /* Panther Point */ 2400 { PCI_DEVICE(0x8086, 0x1e20), 2401 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2402 /* Lynx Point */ 2403 { PCI_DEVICE(0x8086, 0x8c20), 2404 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2405 /* 9 Series */ 2406 { PCI_DEVICE(0x8086, 0x8ca0), 2407 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2408 /* Wellsburg */ 2409 { PCI_DEVICE(0x8086, 0x8d20), 2410 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2411 { PCI_DEVICE(0x8086, 0x8d21), 2412 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2413 /* Lewisburg */ 2414 { PCI_DEVICE(0x8086, 0xa1f0), 2415 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2416 { PCI_DEVICE(0x8086, 0xa270), 2417 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2418 /* Lynx Point-LP */ 2419 { PCI_DEVICE(0x8086, 0x9c20), 2420 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2421 /* Lynx Point-LP */ 2422 { PCI_DEVICE(0x8086, 0x9c21), 2423 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2424 /* Wildcat Point-LP */ 2425 { PCI_DEVICE(0x8086, 0x9ca0), 2426 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2427 /* Sunrise Point */ 2428 { PCI_DEVICE(0x8086, 0xa170), 2429 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2430 /* Sunrise Point-LP */ 2431 { PCI_DEVICE(0x8086, 0x9d70), 2432 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2433 /* Kabylake */ 2434 { PCI_DEVICE(0x8086, 0xa171), 2435 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2436 /* Kabylake-LP */ 2437 { PCI_DEVICE(0x8086, 0x9d71), 2438 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2439 /* Kabylake-H */ 2440 { PCI_DEVICE(0x8086, 0xa2f0), 2441 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2442 /* Coffelake */ 2443 { PCI_DEVICE(0x8086, 0xa348), 2444 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2445 /* Cannonlake */ 2446 { PCI_DEVICE(0x8086, 0x9dc8), 2447 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2448 /* CometLake-LP */ 2449 { PCI_DEVICE(0x8086, 0x02C8), 2450 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2451 /* CometLake-H */ 2452 { PCI_DEVICE(0x8086, 0x06C8), 2453 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2454 { PCI_DEVICE(0x8086, 0xf1c8), 2455 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2456 /* CometLake-S */ 2457 { PCI_DEVICE(0x8086, 0xa3f0), 2458 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2459 /* CometLake-R */ 2460 { PCI_DEVICE(0x8086, 0xf0c8), 2461 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2462 /* Icelake */ 2463 { PCI_DEVICE(0x8086, 0x34c8), 2464 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2465 /* Icelake-H */ 2466 { PCI_DEVICE(0x8086, 0x3dc8), 2467 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2468 /* Jasperlake */ 2469 { PCI_DEVICE(0x8086, 0x38c8), 2470 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2471 { PCI_DEVICE(0x8086, 0x4dc8), 2472 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2473 /* Tigerlake */ 2474 { PCI_DEVICE(0x8086, 0xa0c8), 2475 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2476 /* Tigerlake-H */ 2477 { PCI_DEVICE(0x8086, 0x43c8), 2478 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2479 /* DG1 */ 2480 { PCI_DEVICE(0x8086, 0x490d), 2481 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2482 /* DG2 */ 2483 { PCI_DEVICE(0x8086, 0x4f90), 2484 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2485 { PCI_DEVICE(0x8086, 0x4f91), 2486 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2487 { PCI_DEVICE(0x8086, 0x4f92), 2488 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2489 /* Alderlake-S */ 2490 { PCI_DEVICE(0x8086, 0x7ad0), 2491 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2492 /* Alderlake-P */ 2493 { PCI_DEVICE(0x8086, 0x51c8), 2494 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2495 { PCI_DEVICE(0x8086, 0x51c9), 2496 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2497 { PCI_DEVICE(0x8086, 0x51cd), 2498 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2499 /* Alderlake-M */ 2500 { PCI_DEVICE(0x8086, 0x51cc), 2501 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2502 /* Alderlake-N */ 2503 { PCI_DEVICE(0x8086, 0x54c8), 2504 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2505 /* Elkhart Lake */ 2506 { PCI_DEVICE(0x8086, 0x4b55), 2507 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2508 { PCI_DEVICE(0x8086, 0x4b58), 2509 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2510 /* Raptor Lake */ 2511 { PCI_DEVICE(0x8086, 0x7a50), 2512 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2513 { PCI_DEVICE(0x8086, 0x51ca), 2514 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2515 { PCI_DEVICE(0x8086, 0x51cb), 2516 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2517 { PCI_DEVICE(0x8086, 0x51ce), 2518 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2519 { PCI_DEVICE(0x8086, 0x51cf), 2520 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2521 /* Meteorlake-P */ 2522 { PCI_DEVICE(0x8086, 0x7e28), 2523 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2524 /* Broxton-P(Apollolake) */ 2525 { PCI_DEVICE(0x8086, 0x5a98), 2526 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2527 /* Broxton-T */ 2528 { PCI_DEVICE(0x8086, 0x1a98), 2529 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2530 /* Gemini-Lake */ 2531 { PCI_DEVICE(0x8086, 0x3198), 2532 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2533 /* Haswell */ 2534 { PCI_DEVICE(0x8086, 0x0a0c), 2535 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2536 { PCI_DEVICE(0x8086, 0x0c0c), 2537 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2538 { PCI_DEVICE(0x8086, 0x0d0c), 2539 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2540 /* Broadwell */ 2541 { PCI_DEVICE(0x8086, 0x160c), 2542 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 2543 /* 5 Series/3400 */ 2544 { PCI_DEVICE(0x8086, 0x3b56), 2545 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2546 { PCI_DEVICE(0x8086, 0x3b57), 2547 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2548 /* Poulsbo */ 2549 { PCI_DEVICE(0x8086, 0x811b), 2550 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE | 2551 AZX_DCAPS_POSFIX_LPIB }, 2552 /* Oaktrail */ 2553 { PCI_DEVICE(0x8086, 0x080a), 2554 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2555 /* BayTrail */ 2556 { PCI_DEVICE(0x8086, 0x0f04), 2557 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL }, 2558 /* Braswell */ 2559 { PCI_DEVICE(0x8086, 0x2284), 2560 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL }, 2561 /* ICH6 */ 2562 { PCI_DEVICE(0x8086, 0x2668), 2563 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2564 /* ICH7 */ 2565 { PCI_DEVICE(0x8086, 0x27d8), 2566 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2567 /* ESB2 */ 2568 { PCI_DEVICE(0x8086, 0x269a), 2569 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2570 /* ICH8 */ 2571 { PCI_DEVICE(0x8086, 0x284b), 2572 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2573 /* ICH9 */ 2574 { PCI_DEVICE(0x8086, 0x293e), 2575 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2576 /* ICH9 */ 2577 { PCI_DEVICE(0x8086, 0x293f), 2578 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2579 /* ICH10 */ 2580 { PCI_DEVICE(0x8086, 0x3a3e), 2581 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2582 /* ICH10 */ 2583 { PCI_DEVICE(0x8086, 0x3a6e), 2584 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2585 /* Generic Intel */ 2586 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2587 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2588 .class_mask = 0xffffff, 2589 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2590 /* ATI SB 450/600/700/800/900 */ 2591 { PCI_DEVICE(0x1002, 0x437b), 2592 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2593 { PCI_DEVICE(0x1002, 0x4383), 2594 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2595 /* AMD Hudson */ 2596 { PCI_DEVICE(0x1022, 0x780d), 2597 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2598 /* AMD, X370 & co */ 2599 { PCI_DEVICE(0x1022, 0x1457), 2600 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2601 /* AMD, X570 & co */ 2602 { PCI_DEVICE(0x1022, 0x1487), 2603 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2604 /* AMD Stoney */ 2605 { PCI_DEVICE(0x1022, 0x157a), 2606 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | 2607 AZX_DCAPS_PM_RUNTIME }, 2608 /* AMD Raven */ 2609 { PCI_DEVICE(0x1022, 0x15e3), 2610 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2611 /* ATI HDMI */ 2612 { PCI_DEVICE(0x1002, 0x0002), 2613 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2614 AZX_DCAPS_PM_RUNTIME }, 2615 { PCI_DEVICE(0x1002, 0x1308), 2616 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2617 { PCI_DEVICE(0x1002, 0x157a), 2618 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2619 { PCI_DEVICE(0x1002, 0x15b3), 2620 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2621 { PCI_DEVICE(0x1002, 0x793b), 2622 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2623 { PCI_DEVICE(0x1002, 0x7919), 2624 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2625 { PCI_DEVICE(0x1002, 0x960f), 2626 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2627 { PCI_DEVICE(0x1002, 0x970f), 2628 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2629 { PCI_DEVICE(0x1002, 0x9840), 2630 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2631 { PCI_DEVICE(0x1002, 0xaa00), 2632 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2633 { PCI_DEVICE(0x1002, 0xaa08), 2634 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2635 { PCI_DEVICE(0x1002, 0xaa10), 2636 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2637 { PCI_DEVICE(0x1002, 0xaa18), 2638 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2639 { PCI_DEVICE(0x1002, 0xaa20), 2640 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2641 { PCI_DEVICE(0x1002, 0xaa28), 2642 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2643 { PCI_DEVICE(0x1002, 0xaa30), 2644 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2645 { PCI_DEVICE(0x1002, 0xaa38), 2646 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2647 { PCI_DEVICE(0x1002, 0xaa40), 2648 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2649 { PCI_DEVICE(0x1002, 0xaa48), 2650 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2651 { PCI_DEVICE(0x1002, 0xaa50), 2652 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2653 { PCI_DEVICE(0x1002, 0xaa58), 2654 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2655 { PCI_DEVICE(0x1002, 0xaa60), 2656 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2657 { PCI_DEVICE(0x1002, 0xaa68), 2658 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2659 { PCI_DEVICE(0x1002, 0xaa80), 2660 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2661 { PCI_DEVICE(0x1002, 0xaa88), 2662 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2663 { PCI_DEVICE(0x1002, 0xaa90), 2664 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2665 { PCI_DEVICE(0x1002, 0xaa98), 2666 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2667 { PCI_DEVICE(0x1002, 0x9902), 2668 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2669 { PCI_DEVICE(0x1002, 0xaaa0), 2670 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2671 { PCI_DEVICE(0x1002, 0xaaa8), 2672 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2673 { PCI_DEVICE(0x1002, 0xaab0), 2674 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2675 { PCI_DEVICE(0x1002, 0xaac0), 2676 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2677 AZX_DCAPS_PM_RUNTIME }, 2678 { PCI_DEVICE(0x1002, 0xaac8), 2679 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2680 AZX_DCAPS_PM_RUNTIME }, 2681 { PCI_DEVICE(0x1002, 0xaad8), 2682 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2683 AZX_DCAPS_PM_RUNTIME }, 2684 { PCI_DEVICE(0x1002, 0xaae0), 2685 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2686 AZX_DCAPS_PM_RUNTIME }, 2687 { PCI_DEVICE(0x1002, 0xaae8), 2688 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2689 AZX_DCAPS_PM_RUNTIME }, 2690 { PCI_DEVICE(0x1002, 0xaaf0), 2691 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2692 AZX_DCAPS_PM_RUNTIME }, 2693 { PCI_DEVICE(0x1002, 0xaaf8), 2694 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2695 AZX_DCAPS_PM_RUNTIME }, 2696 { PCI_DEVICE(0x1002, 0xab00), 2697 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2698 AZX_DCAPS_PM_RUNTIME }, 2699 { PCI_DEVICE(0x1002, 0xab08), 2700 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2701 AZX_DCAPS_PM_RUNTIME }, 2702 { PCI_DEVICE(0x1002, 0xab10), 2703 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2704 AZX_DCAPS_PM_RUNTIME }, 2705 { PCI_DEVICE(0x1002, 0xab18), 2706 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2707 AZX_DCAPS_PM_RUNTIME }, 2708 { PCI_DEVICE(0x1002, 0xab20), 2709 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2710 AZX_DCAPS_PM_RUNTIME }, 2711 { PCI_DEVICE(0x1002, 0xab28), 2712 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2713 AZX_DCAPS_PM_RUNTIME }, 2714 { PCI_DEVICE(0x1002, 0xab38), 2715 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2716 AZX_DCAPS_PM_RUNTIME }, 2717 /* VIA VT8251/VT8237A */ 2718 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2719 /* VIA GFX VT7122/VX900 */ 2720 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2721 /* VIA GFX VT6122/VX11 */ 2722 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2723 /* SIS966 */ 2724 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2725 /* ULI M5461 */ 2726 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2727 /* NVIDIA MCP */ 2728 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2729 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2730 .class_mask = 0xffffff, 2731 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2732 /* Teradici */ 2733 { PCI_DEVICE(0x6549, 0x1200), 2734 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2735 { PCI_DEVICE(0x6549, 0x2200), 2736 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2737 /* Creative X-Fi (CA0110-IBG) */ 2738 /* CTHDA chips */ 2739 { PCI_DEVICE(0x1102, 0x0010), 2740 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2741 { PCI_DEVICE(0x1102, 0x0012), 2742 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2743 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2744 /* the following entry conflicts with snd-ctxfi driver, 2745 * as ctxfi driver mutates from HD-audio to native mode with 2746 * a special command sequence. 2747 */ 2748 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2749 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2750 .class_mask = 0xffffff, 2751 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2752 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2753 #else 2754 /* this entry seems still valid -- i.e. without emu20kx chip */ 2755 { PCI_DEVICE(0x1102, 0x0009), 2756 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2757 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2758 #endif 2759 /* CM8888 */ 2760 { PCI_DEVICE(0x13f6, 0x5011), 2761 .driver_data = AZX_DRIVER_CMEDIA | 2762 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2763 /* Vortex86MX */ 2764 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2765 /* VMware HDAudio */ 2766 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2767 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2768 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2769 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2770 .class_mask = 0xffffff, 2771 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2772 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2773 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2774 .class_mask = 0xffffff, 2775 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2776 /* Zhaoxin */ 2777 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN }, 2778 { 0, } 2779 }; 2780 MODULE_DEVICE_TABLE(pci, azx_ids); 2781 2782 /* pci_driver definition */ 2783 static struct pci_driver azx_driver = { 2784 .name = KBUILD_MODNAME, 2785 .id_table = azx_ids, 2786 .probe = azx_probe, 2787 .remove = azx_remove, 2788 .shutdown = azx_shutdown, 2789 .driver = { 2790 .pm = AZX_PM_OPS, 2791 }, 2792 }; 2793 2794 module_pci_driver(azx_driver); 2795