1 /* 2 * 3 * hda_intel.c - Implementation of primary alsa driver code base 4 * for Intel HD Audio. 5 * 6 * Copyright(c) 2004 Intel Corporation. All rights reserved. 7 * 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the Free 13 * Software Foundation; either version 2 of the License, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 * 21 * You should have received a copy of the GNU General Public License along with 22 * this program; if not, write to the Free Software Foundation, Inc., 59 23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 24 * 25 * CONTACTS: 26 * 27 * Matt Jared matt.jared@intel.com 28 * Andy Kopp andy.kopp@intel.com 29 * Dan Kogan dan.d.kogan@intel.com 30 * 31 * CHANGES: 32 * 33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 34 * 35 */ 36 37 #include <linux/delay.h> 38 #include <linux/interrupt.h> 39 #include <linux/kernel.h> 40 #include <linux/module.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/moduleparam.h> 43 #include <linux/init.h> 44 #include <linux/slab.h> 45 #include <linux/pci.h> 46 #include <linux/mutex.h> 47 #include <linux/reboot.h> 48 #include <linux/io.h> 49 #include <linux/pm_runtime.h> 50 #include <linux/clocksource.h> 51 #include <linux/time.h> 52 #include <linux/completion.h> 53 54 #ifdef CONFIG_X86 55 /* for snoop control */ 56 #include <asm/pgtable.h> 57 #include <asm/cacheflush.h> 58 #endif 59 #include <sound/core.h> 60 #include <sound/initval.h> 61 #include <linux/vgaarb.h> 62 #include <linux/vga_switcheroo.h> 63 #include <linux/firmware.h> 64 #include "hda_codec.h" 65 66 67 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 68 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 69 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 70 static char *model[SNDRV_CARDS]; 71 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 72 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 73 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 74 static int probe_only[SNDRV_CARDS]; 75 static int jackpoll_ms[SNDRV_CARDS]; 76 static bool single_cmd; 77 static int enable_msi = -1; 78 #ifdef CONFIG_SND_HDA_PATCH_LOADER 79 static char *patch[SNDRV_CARDS]; 80 #endif 81 #ifdef CONFIG_SND_HDA_INPUT_BEEP 82 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 83 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 84 #endif 85 86 module_param_array(index, int, NULL, 0444); 87 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 88 module_param_array(id, charp, NULL, 0444); 89 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 90 module_param_array(enable, bool, NULL, 0444); 91 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 92 module_param_array(model, charp, NULL, 0444); 93 MODULE_PARM_DESC(model, "Use the given board model."); 94 module_param_array(position_fix, int, NULL, 0444); 95 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 96 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO)."); 97 module_param_array(bdl_pos_adj, int, NULL, 0644); 98 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 99 module_param_array(probe_mask, int, NULL, 0444); 100 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 101 module_param_array(probe_only, int, NULL, 0444); 102 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 103 module_param_array(jackpoll_ms, int, NULL, 0444); 104 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 105 module_param(single_cmd, bool, 0444); 106 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 107 "(for debugging only)."); 108 module_param(enable_msi, bint, 0444); 109 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 110 #ifdef CONFIG_SND_HDA_PATCH_LOADER 111 module_param_array(patch, charp, NULL, 0444); 112 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 113 #endif 114 #ifdef CONFIG_SND_HDA_INPUT_BEEP 115 module_param_array(beep_mode, bool, NULL, 0444); 116 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 117 "(0=off, 1=on) (default=1)."); 118 #endif 119 120 #ifdef CONFIG_PM 121 static int param_set_xint(const char *val, const struct kernel_param *kp); 122 static struct kernel_param_ops param_ops_xint = { 123 .set = param_set_xint, 124 .get = param_get_int, 125 }; 126 #define param_check_xint param_check_int 127 128 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 129 module_param(power_save, xint, 0644); 130 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 131 "(in second, 0 = disable)."); 132 133 /* reset the HD-audio controller in power save mode. 134 * this may give more power-saving, but will take longer time to 135 * wake up. 136 */ 137 static bool power_save_controller = 1; 138 module_param(power_save_controller, bool, 0644); 139 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 140 #endif /* CONFIG_PM */ 141 142 static int align_buffer_size = -1; 143 module_param(align_buffer_size, bint, 0644); 144 MODULE_PARM_DESC(align_buffer_size, 145 "Force buffer and period sizes to be multiple of 128 bytes."); 146 147 #ifdef CONFIG_X86 148 static bool hda_snoop = true; 149 module_param_named(snoop, hda_snoop, bool, 0444); 150 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 151 #define azx_snoop(chip) (chip)->snoop 152 #else 153 #define hda_snoop true 154 #define azx_snoop(chip) true 155 #endif 156 157 158 MODULE_LICENSE("GPL"); 159 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 160 "{Intel, ICH6M}," 161 "{Intel, ICH7}," 162 "{Intel, ESB2}," 163 "{Intel, ICH8}," 164 "{Intel, ICH9}," 165 "{Intel, ICH10}," 166 "{Intel, PCH}," 167 "{Intel, CPT}," 168 "{Intel, PPT}," 169 "{Intel, LPT}," 170 "{Intel, LPT_LP}," 171 "{Intel, HPT}," 172 "{Intel, PBG}," 173 "{Intel, SCH}," 174 "{ATI, SB450}," 175 "{ATI, SB600}," 176 "{ATI, RS600}," 177 "{ATI, RS690}," 178 "{ATI, RS780}," 179 "{ATI, R600}," 180 "{ATI, RV630}," 181 "{ATI, RV610}," 182 "{ATI, RV670}," 183 "{ATI, RV635}," 184 "{ATI, RV620}," 185 "{ATI, RV770}," 186 "{VIA, VT8251}," 187 "{VIA, VT8237A}," 188 "{SiS, SIS966}," 189 "{ULI, M5461}}"); 190 MODULE_DESCRIPTION("Intel HDA driver"); 191 192 #ifdef CONFIG_SND_VERBOSE_PRINTK 193 #define SFX /* nop */ 194 #else 195 #define SFX "hda-intel " 196 #endif 197 198 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 199 #ifdef CONFIG_SND_HDA_CODEC_HDMI 200 #define SUPPORT_VGA_SWITCHEROO 201 #endif 202 #endif 203 204 205 /* 206 * registers 207 */ 208 #define ICH6_REG_GCAP 0x00 209 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */ 210 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */ 211 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */ 212 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */ 213 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */ 214 #define ICH6_REG_VMIN 0x02 215 #define ICH6_REG_VMAJ 0x03 216 #define ICH6_REG_OUTPAY 0x04 217 #define ICH6_REG_INPAY 0x06 218 #define ICH6_REG_GCTL 0x08 219 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */ 220 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */ 221 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */ 222 #define ICH6_REG_WAKEEN 0x0c 223 #define ICH6_REG_STATESTS 0x0e 224 #define ICH6_REG_GSTS 0x10 225 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */ 226 #define ICH6_REG_INTCTL 0x20 227 #define ICH6_REG_INTSTS 0x24 228 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */ 229 #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */ 230 #define ICH6_REG_SSYNC 0x38 231 #define ICH6_REG_CORBLBASE 0x40 232 #define ICH6_REG_CORBUBASE 0x44 233 #define ICH6_REG_CORBWP 0x48 234 #define ICH6_REG_CORBRP 0x4a 235 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */ 236 #define ICH6_REG_CORBCTL 0x4c 237 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */ 238 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */ 239 #define ICH6_REG_CORBSTS 0x4d 240 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */ 241 #define ICH6_REG_CORBSIZE 0x4e 242 243 #define ICH6_REG_RIRBLBASE 0x50 244 #define ICH6_REG_RIRBUBASE 0x54 245 #define ICH6_REG_RIRBWP 0x58 246 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */ 247 #define ICH6_REG_RINTCNT 0x5a 248 #define ICH6_REG_RIRBCTL 0x5c 249 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */ 250 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */ 251 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */ 252 #define ICH6_REG_RIRBSTS 0x5d 253 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */ 254 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */ 255 #define ICH6_REG_RIRBSIZE 0x5e 256 257 #define ICH6_REG_IC 0x60 258 #define ICH6_REG_IR 0x64 259 #define ICH6_REG_IRS 0x68 260 #define ICH6_IRS_VALID (1<<1) 261 #define ICH6_IRS_BUSY (1<<0) 262 263 #define ICH6_REG_DPLBASE 0x70 264 #define ICH6_REG_DPUBASE 0x74 265 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */ 266 267 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ 268 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; 269 270 /* stream register offsets from stream base */ 271 #define ICH6_REG_SD_CTL 0x00 272 #define ICH6_REG_SD_STS 0x03 273 #define ICH6_REG_SD_LPIB 0x04 274 #define ICH6_REG_SD_CBL 0x08 275 #define ICH6_REG_SD_LVI 0x0c 276 #define ICH6_REG_SD_FIFOW 0x0e 277 #define ICH6_REG_SD_FIFOSIZE 0x10 278 #define ICH6_REG_SD_FORMAT 0x12 279 #define ICH6_REG_SD_BDLPL 0x18 280 #define ICH6_REG_SD_BDLPU 0x1c 281 282 /* PCI space */ 283 #define ICH6_PCIREG_TCSEL 0x44 284 285 /* 286 * other constants 287 */ 288 289 /* max number of SDs */ 290 /* ICH, ATI and VIA have 4 playback and 4 capture */ 291 #define ICH6_NUM_CAPTURE 4 292 #define ICH6_NUM_PLAYBACK 4 293 294 /* ULI has 6 playback and 5 capture */ 295 #define ULI_NUM_CAPTURE 5 296 #define ULI_NUM_PLAYBACK 6 297 298 /* ATI HDMI has 1 playback and 0 capture */ 299 #define ATIHDMI_NUM_CAPTURE 0 300 #define ATIHDMI_NUM_PLAYBACK 1 301 302 /* TERA has 4 playback and 3 capture */ 303 #define TERA_NUM_CAPTURE 3 304 #define TERA_NUM_PLAYBACK 4 305 306 /* this number is statically defined for simplicity */ 307 #define MAX_AZX_DEV 16 308 309 /* max number of fragments - we may use more if allocating more pages for BDL */ 310 #define BDL_SIZE 4096 311 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16) 312 #define AZX_MAX_FRAG 32 313 /* max buffer size - no h/w limit, you can increase as you like */ 314 #define AZX_MAX_BUF_SIZE (1024*1024*1024) 315 316 /* RIRB int mask: overrun[2], response[0] */ 317 #define RIRB_INT_RESPONSE 0x01 318 #define RIRB_INT_OVERRUN 0x04 319 #define RIRB_INT_MASK 0x05 320 321 /* STATESTS int mask: S3,SD2,SD1,SD0 */ 322 #define AZX_MAX_CODECS 8 323 #define AZX_DEFAULT_CODECS 4 324 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1) 325 326 /* SD_CTL bits */ 327 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ 328 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ 329 #define SD_CTL_STRIPE (3 << 16) /* stripe control */ 330 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */ 331 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */ 332 #define SD_CTL_STREAM_TAG_MASK (0xf << 20) 333 #define SD_CTL_STREAM_TAG_SHIFT 20 334 335 /* SD_CTL and SD_STS */ 336 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ 337 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ 338 #define SD_INT_COMPLETE 0x04 /* completion interrupt */ 339 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\ 340 SD_INT_COMPLETE) 341 342 /* SD_STS */ 343 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */ 344 345 /* INTCTL and INTSTS */ 346 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */ 347 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ 348 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ 349 350 /* below are so far hardcoded - should read registers in future */ 351 #define ICH6_MAX_CORB_ENTRIES 256 352 #define ICH6_MAX_RIRB_ENTRIES 256 353 354 /* position fix mode */ 355 enum { 356 POS_FIX_AUTO, 357 POS_FIX_LPIB, 358 POS_FIX_POSBUF, 359 POS_FIX_VIACOMBO, 360 POS_FIX_COMBO, 361 }; 362 363 /* Defines for ATI HD Audio support in SB450 south bridge */ 364 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 365 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 366 367 /* Defines for Nvidia HDA support */ 368 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 369 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 370 #define NVIDIA_HDA_ISTRM_COH 0x4d 371 #define NVIDIA_HDA_OSTRM_COH 0x4c 372 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 373 374 /* Defines for Intel SCH HDA snoop control */ 375 #define INTEL_SCH_HDA_DEVC 0x78 376 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 377 378 /* Define IN stream 0 FIFO size offset in VIA controller */ 379 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 380 /* Define VIA HD Audio Device ID*/ 381 #define VIA_HDAC_DEVICE_ID 0x3288 382 383 /* HD Audio class code */ 384 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403 385 386 /* 387 */ 388 389 struct azx_dev { 390 struct snd_dma_buffer bdl; /* BDL buffer */ 391 u32 *posbuf; /* position buffer pointer */ 392 393 unsigned int bufsize; /* size of the play buffer in bytes */ 394 unsigned int period_bytes; /* size of the period in bytes */ 395 unsigned int frags; /* number for period in the play buffer */ 396 unsigned int fifo_size; /* FIFO size */ 397 unsigned long start_wallclk; /* start + minimum wallclk */ 398 unsigned long period_wallclk; /* wallclk for period */ 399 400 void __iomem *sd_addr; /* stream descriptor pointer */ 401 402 u32 sd_int_sta_mask; /* stream int status mask */ 403 404 /* pcm support */ 405 struct snd_pcm_substream *substream; /* assigned substream, 406 * set in PCM open 407 */ 408 unsigned int format_val; /* format value to be set in the 409 * controller and the codec 410 */ 411 unsigned char stream_tag; /* assigned stream */ 412 unsigned char index; /* stream index */ 413 int assigned_key; /* last device# key assigned to */ 414 415 unsigned int opened :1; 416 unsigned int running :1; 417 unsigned int irq_pending :1; 418 unsigned int prepared:1; 419 unsigned int locked:1; 420 /* 421 * For VIA: 422 * A flag to ensure DMA position is 0 423 * when link position is not greater than FIFO size 424 */ 425 unsigned int insufficient :1; 426 unsigned int wc_marked:1; 427 unsigned int no_period_wakeup:1; 428 429 struct timecounter azx_tc; 430 struct cyclecounter azx_cc; 431 432 #ifdef CONFIG_SND_HDA_DSP_LOADER 433 struct mutex dsp_mutex; 434 #endif 435 }; 436 437 /* DSP lock helpers */ 438 #ifdef CONFIG_SND_HDA_DSP_LOADER 439 #define dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex) 440 #define dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex) 441 #define dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex) 442 #define dsp_is_locked(dev) ((dev)->locked) 443 #else 444 #define dsp_lock_init(dev) do {} while (0) 445 #define dsp_lock(dev) do {} while (0) 446 #define dsp_unlock(dev) do {} while (0) 447 #define dsp_is_locked(dev) 0 448 #endif 449 450 /* CORB/RIRB */ 451 struct azx_rb { 452 u32 *buf; /* CORB/RIRB buffer 453 * Each CORB entry is 4byte, RIRB is 8byte 454 */ 455 dma_addr_t addr; /* physical address of CORB/RIRB buffer */ 456 /* for RIRB */ 457 unsigned short rp, wp; /* read/write pointers */ 458 int cmds[AZX_MAX_CODECS]; /* number of pending requests */ 459 u32 res[AZX_MAX_CODECS]; /* last read value */ 460 }; 461 462 struct azx_pcm { 463 struct azx *chip; 464 struct snd_pcm *pcm; 465 struct hda_codec *codec; 466 struct hda_pcm_stream *hinfo[2]; 467 struct list_head list; 468 }; 469 470 struct azx { 471 struct snd_card *card; 472 struct pci_dev *pci; 473 int dev_index; 474 475 /* chip type specific */ 476 int driver_type; 477 unsigned int driver_caps; 478 int playback_streams; 479 int playback_index_offset; 480 int capture_streams; 481 int capture_index_offset; 482 int num_streams; 483 484 /* pci resources */ 485 unsigned long addr; 486 void __iomem *remap_addr; 487 int irq; 488 489 /* locks */ 490 spinlock_t reg_lock; 491 struct mutex open_mutex; 492 struct completion probe_wait; 493 494 /* streams (x num_streams) */ 495 struct azx_dev *azx_dev; 496 497 /* PCM */ 498 struct list_head pcm_list; /* azx_pcm list */ 499 500 /* HD codec */ 501 unsigned short codec_mask; 502 int codec_probe_mask; /* copied from probe_mask option */ 503 struct hda_bus *bus; 504 unsigned int beep_mode; 505 506 /* CORB/RIRB */ 507 struct azx_rb corb; 508 struct azx_rb rirb; 509 510 /* CORB/RIRB and position buffers */ 511 struct snd_dma_buffer rb; 512 struct snd_dma_buffer posbuf; 513 514 #ifdef CONFIG_SND_HDA_PATCH_LOADER 515 const struct firmware *fw; 516 #endif 517 518 /* flags */ 519 int position_fix[2]; /* for both playback/capture streams */ 520 int poll_count; 521 unsigned int running :1; 522 unsigned int initialized :1; 523 unsigned int single_cmd :1; 524 unsigned int polling_mode :1; 525 unsigned int msi :1; 526 unsigned int irq_pending_warned :1; 527 unsigned int probing :1; /* codec probing phase */ 528 unsigned int snoop:1; 529 unsigned int align_buffer_size:1; 530 unsigned int region_requested:1; 531 532 /* VGA-switcheroo setup */ 533 unsigned int use_vga_switcheroo:1; 534 unsigned int vga_switcheroo_registered:1; 535 unsigned int init_failed:1; /* delayed init failed */ 536 unsigned int disabled:1; /* disabled by VGA-switcher */ 537 538 /* for debugging */ 539 unsigned int last_cmd[AZX_MAX_CODECS]; 540 541 /* for pending irqs */ 542 struct work_struct irq_pending_work; 543 544 /* reboot notifier (for mysterious hangup problem at power-down) */ 545 struct notifier_block reboot_notifier; 546 547 /* card list (for power_save trigger) */ 548 struct list_head list; 549 550 #ifdef CONFIG_SND_HDA_DSP_LOADER 551 struct azx_dev saved_azx_dev; 552 #endif 553 }; 554 555 #define CREATE_TRACE_POINTS 556 #include "hda_intel_trace.h" 557 558 /* driver types */ 559 enum { 560 AZX_DRIVER_ICH, 561 AZX_DRIVER_PCH, 562 AZX_DRIVER_SCH, 563 AZX_DRIVER_ATI, 564 AZX_DRIVER_ATIHDMI, 565 AZX_DRIVER_ATIHDMI_NS, 566 AZX_DRIVER_VIA, 567 AZX_DRIVER_SIS, 568 AZX_DRIVER_ULI, 569 AZX_DRIVER_NVIDIA, 570 AZX_DRIVER_TERA, 571 AZX_DRIVER_CTX, 572 AZX_DRIVER_CTHDA, 573 AZX_DRIVER_GENERIC, 574 AZX_NUM_DRIVERS, /* keep this as last entry */ 575 }; 576 577 /* driver quirks (capabilities) */ 578 /* bits 0-7 are used for indicating driver type */ 579 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */ 580 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */ 581 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */ 582 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */ 583 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */ 584 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */ 585 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */ 586 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */ 587 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */ 588 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */ 589 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */ 590 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */ 591 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */ 592 #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */ 593 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */ 594 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */ 595 #define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */ 596 #define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */ 597 598 /* quirks for Intel PCH */ 599 #define AZX_DCAPS_INTEL_PCH_NOPM \ 600 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \ 601 AZX_DCAPS_COUNT_LPIB_DELAY) 602 603 #define AZX_DCAPS_INTEL_PCH \ 604 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME) 605 606 /* quirks for ATI SB / AMD Hudson */ 607 #define AZX_DCAPS_PRESET_ATI_SB \ 608 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \ 609 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB) 610 611 /* quirks for ATI/AMD HDMI */ 612 #define AZX_DCAPS_PRESET_ATI_HDMI \ 613 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB) 614 615 /* quirks for Nvidia */ 616 #define AZX_DCAPS_PRESET_NVIDIA \ 617 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\ 618 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT) 619 620 #define AZX_DCAPS_PRESET_CTHDA \ 621 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY) 622 623 /* 624 * VGA-switcher support 625 */ 626 #ifdef SUPPORT_VGA_SWITCHEROO 627 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 628 #else 629 #define use_vga_switcheroo(chip) 0 630 #endif 631 632 static char *driver_short_names[] = { 633 [AZX_DRIVER_ICH] = "HDA Intel", 634 [AZX_DRIVER_PCH] = "HDA Intel PCH", 635 [AZX_DRIVER_SCH] = "HDA Intel MID", 636 [AZX_DRIVER_ATI] = "HDA ATI SB", 637 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 638 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 639 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 640 [AZX_DRIVER_SIS] = "HDA SIS966", 641 [AZX_DRIVER_ULI] = "HDA ULI M5461", 642 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 643 [AZX_DRIVER_TERA] = "HDA Teradici", 644 [AZX_DRIVER_CTX] = "HDA Creative", 645 [AZX_DRIVER_CTHDA] = "HDA Creative", 646 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 647 }; 648 649 /* 650 * macros for easy use 651 */ 652 #define azx_writel(chip,reg,value) \ 653 writel(value, (chip)->remap_addr + ICH6_REG_##reg) 654 #define azx_readl(chip,reg) \ 655 readl((chip)->remap_addr + ICH6_REG_##reg) 656 #define azx_writew(chip,reg,value) \ 657 writew(value, (chip)->remap_addr + ICH6_REG_##reg) 658 #define azx_readw(chip,reg) \ 659 readw((chip)->remap_addr + ICH6_REG_##reg) 660 #define azx_writeb(chip,reg,value) \ 661 writeb(value, (chip)->remap_addr + ICH6_REG_##reg) 662 #define azx_readb(chip,reg) \ 663 readb((chip)->remap_addr + ICH6_REG_##reg) 664 665 #define azx_sd_writel(dev,reg,value) \ 666 writel(value, (dev)->sd_addr + ICH6_REG_##reg) 667 #define azx_sd_readl(dev,reg) \ 668 readl((dev)->sd_addr + ICH6_REG_##reg) 669 #define azx_sd_writew(dev,reg,value) \ 670 writew(value, (dev)->sd_addr + ICH6_REG_##reg) 671 #define azx_sd_readw(dev,reg) \ 672 readw((dev)->sd_addr + ICH6_REG_##reg) 673 #define azx_sd_writeb(dev,reg,value) \ 674 writeb(value, (dev)->sd_addr + ICH6_REG_##reg) 675 #define azx_sd_readb(dev,reg) \ 676 readb((dev)->sd_addr + ICH6_REG_##reg) 677 678 /* for pcm support */ 679 #define get_azx_dev(substream) (substream->runtime->private_data) 680 681 #ifdef CONFIG_X86 682 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on) 683 { 684 int pages; 685 686 if (azx_snoop(chip)) 687 return; 688 if (!dmab || !dmab->area || !dmab->bytes) 689 return; 690 691 #ifdef CONFIG_SND_DMA_SGBUF 692 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) { 693 struct snd_sg_buf *sgbuf = dmab->private_data; 694 if (on) 695 set_pages_array_wc(sgbuf->page_table, sgbuf->pages); 696 else 697 set_pages_array_wb(sgbuf->page_table, sgbuf->pages); 698 return; 699 } 700 #endif 701 702 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT; 703 if (on) 704 set_memory_wc((unsigned long)dmab->area, pages); 705 else 706 set_memory_wb((unsigned long)dmab->area, pages); 707 } 708 709 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 710 bool on) 711 { 712 __mark_pages_wc(chip, buf, on); 713 } 714 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 715 struct snd_pcm_substream *substream, bool on) 716 { 717 if (azx_dev->wc_marked != on) { 718 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on); 719 azx_dev->wc_marked = on; 720 } 721 } 722 #else 723 /* NOP for other archs */ 724 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 725 bool on) 726 { 727 } 728 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 729 struct snd_pcm_substream *substream, bool on) 730 { 731 } 732 #endif 733 734 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 735 static int azx_send_cmd(struct hda_bus *bus, unsigned int val); 736 /* 737 * Interface for HD codec 738 */ 739 740 /* 741 * CORB / RIRB interface 742 */ 743 static int azx_alloc_cmd_io(struct azx *chip) 744 { 745 int err; 746 747 /* single page (at least 4096 bytes) must suffice for both ringbuffes */ 748 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, 749 snd_dma_pci_data(chip->pci), 750 PAGE_SIZE, &chip->rb); 751 if (err < 0) { 752 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci)); 753 return err; 754 } 755 mark_pages_wc(chip, &chip->rb, true); 756 return 0; 757 } 758 759 static void azx_init_cmd_io(struct azx *chip) 760 { 761 spin_lock_irq(&chip->reg_lock); 762 /* CORB set up */ 763 chip->corb.addr = chip->rb.addr; 764 chip->corb.buf = (u32 *)chip->rb.area; 765 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr); 766 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr)); 767 768 /* set the corb size to 256 entries (ULI requires explicitly) */ 769 azx_writeb(chip, CORBSIZE, 0x02); 770 /* set the corb write pointer to 0 */ 771 azx_writew(chip, CORBWP, 0); 772 /* reset the corb hw read pointer */ 773 azx_writew(chip, CORBRP, ICH6_CORBRP_RST); 774 /* enable corb dma */ 775 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN); 776 777 /* RIRB set up */ 778 chip->rirb.addr = chip->rb.addr + 2048; 779 chip->rirb.buf = (u32 *)(chip->rb.area + 2048); 780 chip->rirb.wp = chip->rirb.rp = 0; 781 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds)); 782 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr); 783 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr)); 784 785 /* set the rirb size to 256 entries (ULI requires explicitly) */ 786 azx_writeb(chip, RIRBSIZE, 0x02); 787 /* reset the rirb hw write pointer */ 788 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST); 789 /* set N=1, get RIRB response interrupt for new entry */ 790 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) 791 azx_writew(chip, RINTCNT, 0xc0); 792 else 793 azx_writew(chip, RINTCNT, 1); 794 /* enable rirb dma and response irq */ 795 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN); 796 spin_unlock_irq(&chip->reg_lock); 797 } 798 799 static void azx_free_cmd_io(struct azx *chip) 800 { 801 spin_lock_irq(&chip->reg_lock); 802 /* disable ringbuffer DMAs */ 803 azx_writeb(chip, RIRBCTL, 0); 804 azx_writeb(chip, CORBCTL, 0); 805 spin_unlock_irq(&chip->reg_lock); 806 } 807 808 static unsigned int azx_command_addr(u32 cmd) 809 { 810 unsigned int addr = cmd >> 28; 811 812 if (addr >= AZX_MAX_CODECS) { 813 snd_BUG(); 814 addr = 0; 815 } 816 817 return addr; 818 } 819 820 static unsigned int azx_response_addr(u32 res) 821 { 822 unsigned int addr = res & 0xf; 823 824 if (addr >= AZX_MAX_CODECS) { 825 snd_BUG(); 826 addr = 0; 827 } 828 829 return addr; 830 } 831 832 /* send a command */ 833 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val) 834 { 835 struct azx *chip = bus->private_data; 836 unsigned int addr = azx_command_addr(val); 837 unsigned int wp, rp; 838 839 spin_lock_irq(&chip->reg_lock); 840 841 /* add command to corb */ 842 wp = azx_readw(chip, CORBWP); 843 if (wp == 0xffff) { 844 /* something wrong, controller likely turned to D3 */ 845 spin_unlock_irq(&chip->reg_lock); 846 return -EIO; 847 } 848 wp++; 849 wp %= ICH6_MAX_CORB_ENTRIES; 850 851 rp = azx_readw(chip, CORBRP); 852 if (wp == rp) { 853 /* oops, it's full */ 854 spin_unlock_irq(&chip->reg_lock); 855 return -EAGAIN; 856 } 857 858 chip->rirb.cmds[addr]++; 859 chip->corb.buf[wp] = cpu_to_le32(val); 860 azx_writel(chip, CORBWP, wp); 861 862 spin_unlock_irq(&chip->reg_lock); 863 864 return 0; 865 } 866 867 #define ICH6_RIRB_EX_UNSOL_EV (1<<4) 868 869 /* retrieve RIRB entry - called from interrupt handler */ 870 static void azx_update_rirb(struct azx *chip) 871 { 872 unsigned int rp, wp; 873 unsigned int addr; 874 u32 res, res_ex; 875 876 wp = azx_readw(chip, RIRBWP); 877 if (wp == 0xffff) { 878 /* something wrong, controller likely turned to D3 */ 879 return; 880 } 881 882 if (wp == chip->rirb.wp) 883 return; 884 chip->rirb.wp = wp; 885 886 while (chip->rirb.rp != wp) { 887 chip->rirb.rp++; 888 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES; 889 890 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */ 891 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]); 892 res = le32_to_cpu(chip->rirb.buf[rp]); 893 addr = azx_response_addr(res_ex); 894 if (res_ex & ICH6_RIRB_EX_UNSOL_EV) 895 snd_hda_queue_unsol_event(chip->bus, res, res_ex); 896 else if (chip->rirb.cmds[addr]) { 897 chip->rirb.res[addr] = res; 898 smp_wmb(); 899 chip->rirb.cmds[addr]--; 900 } else 901 snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, " 902 "last cmd=%#08x\n", 903 pci_name(chip->pci), 904 res, res_ex, 905 chip->last_cmd[addr]); 906 } 907 } 908 909 /* receive a response */ 910 static unsigned int azx_rirb_get_response(struct hda_bus *bus, 911 unsigned int addr) 912 { 913 struct azx *chip = bus->private_data; 914 unsigned long timeout; 915 unsigned long loopcounter; 916 int do_poll = 0; 917 918 again: 919 timeout = jiffies + msecs_to_jiffies(1000); 920 921 for (loopcounter = 0;; loopcounter++) { 922 if (chip->polling_mode || do_poll) { 923 spin_lock_irq(&chip->reg_lock); 924 azx_update_rirb(chip); 925 spin_unlock_irq(&chip->reg_lock); 926 } 927 if (!chip->rirb.cmds[addr]) { 928 smp_rmb(); 929 bus->rirb_error = 0; 930 931 if (!do_poll) 932 chip->poll_count = 0; 933 return chip->rirb.res[addr]; /* the last value */ 934 } 935 if (time_after(jiffies, timeout)) 936 break; 937 if (bus->needs_damn_long_delay || loopcounter > 3000) 938 msleep(2); /* temporary workaround */ 939 else { 940 udelay(10); 941 cond_resched(); 942 } 943 } 944 945 if (!chip->polling_mode && chip->poll_count < 2) { 946 snd_printdd(SFX "%s: azx_get_response timeout, " 947 "polling the codec once: last cmd=0x%08x\n", 948 pci_name(chip->pci), chip->last_cmd[addr]); 949 do_poll = 1; 950 chip->poll_count++; 951 goto again; 952 } 953 954 955 if (!chip->polling_mode) { 956 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, " 957 "switching to polling mode: last cmd=0x%08x\n", 958 pci_name(chip->pci), chip->last_cmd[addr]); 959 chip->polling_mode = 1; 960 goto again; 961 } 962 963 if (chip->msi) { 964 snd_printk(KERN_WARNING SFX "%s: No response from codec, " 965 "disabling MSI: last cmd=0x%08x\n", 966 pci_name(chip->pci), chip->last_cmd[addr]); 967 free_irq(chip->irq, chip); 968 chip->irq = -1; 969 pci_disable_msi(chip->pci); 970 chip->msi = 0; 971 if (azx_acquire_irq(chip, 1) < 0) { 972 bus->rirb_error = 1; 973 return -1; 974 } 975 goto again; 976 } 977 978 if (chip->probing) { 979 /* If this critical timeout happens during the codec probing 980 * phase, this is likely an access to a non-existing codec 981 * slot. Better to return an error and reset the system. 982 */ 983 return -1; 984 } 985 986 /* a fatal communication error; need either to reset or to fallback 987 * to the single_cmd mode 988 */ 989 bus->rirb_error = 1; 990 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) { 991 bus->response_reset = 1; 992 return -1; /* give a chance to retry */ 993 } 994 995 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, " 996 "switching to single_cmd mode: last cmd=0x%08x\n", 997 chip->last_cmd[addr]); 998 chip->single_cmd = 1; 999 bus->response_reset = 0; 1000 /* release CORB/RIRB */ 1001 azx_free_cmd_io(chip); 1002 /* disable unsolicited responses */ 1003 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL); 1004 return -1; 1005 } 1006 1007 /* 1008 * Use the single immediate command instead of CORB/RIRB for simplicity 1009 * 1010 * Note: according to Intel, this is not preferred use. The command was 1011 * intended for the BIOS only, and may get confused with unsolicited 1012 * responses. So, we shouldn't use it for normal operation from the 1013 * driver. 1014 * I left the codes, however, for debugging/testing purposes. 1015 */ 1016 1017 /* receive a response */ 1018 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr) 1019 { 1020 int timeout = 50; 1021 1022 while (timeout--) { 1023 /* check IRV busy bit */ 1024 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) { 1025 /* reuse rirb.res as the response return value */ 1026 chip->rirb.res[addr] = azx_readl(chip, IR); 1027 return 0; 1028 } 1029 udelay(1); 1030 } 1031 if (printk_ratelimit()) 1032 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n", 1033 pci_name(chip->pci), azx_readw(chip, IRS)); 1034 chip->rirb.res[addr] = -1; 1035 return -EIO; 1036 } 1037 1038 /* send a command */ 1039 static int azx_single_send_cmd(struct hda_bus *bus, u32 val) 1040 { 1041 struct azx *chip = bus->private_data; 1042 unsigned int addr = azx_command_addr(val); 1043 int timeout = 50; 1044 1045 bus->rirb_error = 0; 1046 while (timeout--) { 1047 /* check ICB busy bit */ 1048 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) { 1049 /* Clear IRV valid bit */ 1050 azx_writew(chip, IRS, azx_readw(chip, IRS) | 1051 ICH6_IRS_VALID); 1052 azx_writel(chip, IC, val); 1053 azx_writew(chip, IRS, azx_readw(chip, IRS) | 1054 ICH6_IRS_BUSY); 1055 return azx_single_wait_for_response(chip, addr); 1056 } 1057 udelay(1); 1058 } 1059 if (printk_ratelimit()) 1060 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n", 1061 pci_name(chip->pci), azx_readw(chip, IRS), val); 1062 return -EIO; 1063 } 1064 1065 /* receive a response */ 1066 static unsigned int azx_single_get_response(struct hda_bus *bus, 1067 unsigned int addr) 1068 { 1069 struct azx *chip = bus->private_data; 1070 return chip->rirb.res[addr]; 1071 } 1072 1073 /* 1074 * The below are the main callbacks from hda_codec. 1075 * 1076 * They are just the skeleton to call sub-callbacks according to the 1077 * current setting of chip->single_cmd. 1078 */ 1079 1080 /* send a command */ 1081 static int azx_send_cmd(struct hda_bus *bus, unsigned int val) 1082 { 1083 struct azx *chip = bus->private_data; 1084 1085 if (chip->disabled) 1086 return 0; 1087 chip->last_cmd[azx_command_addr(val)] = val; 1088 if (chip->single_cmd) 1089 return azx_single_send_cmd(bus, val); 1090 else 1091 return azx_corb_send_cmd(bus, val); 1092 } 1093 1094 /* get a response */ 1095 static unsigned int azx_get_response(struct hda_bus *bus, 1096 unsigned int addr) 1097 { 1098 struct azx *chip = bus->private_data; 1099 if (chip->disabled) 1100 return 0; 1101 if (chip->single_cmd) 1102 return azx_single_get_response(bus, addr); 1103 else 1104 return azx_rirb_get_response(bus, addr); 1105 } 1106 1107 #ifdef CONFIG_PM 1108 static void azx_power_notify(struct hda_bus *bus, bool power_up); 1109 #endif 1110 1111 #ifdef CONFIG_SND_HDA_DSP_LOADER 1112 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format, 1113 unsigned int byte_size, 1114 struct snd_dma_buffer *bufp); 1115 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start); 1116 static void azx_load_dsp_cleanup(struct hda_bus *bus, 1117 struct snd_dma_buffer *dmab); 1118 #endif 1119 1120 /* reset codec link */ 1121 static int azx_reset(struct azx *chip, int full_reset) 1122 { 1123 unsigned long timeout; 1124 1125 if (!full_reset) 1126 goto __skip; 1127 1128 /* clear STATESTS */ 1129 azx_writeb(chip, STATESTS, STATESTS_INT_MASK); 1130 1131 /* reset controller */ 1132 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); 1133 1134 timeout = jiffies + msecs_to_jiffies(100); 1135 while (azx_readb(chip, GCTL) && 1136 time_before(jiffies, timeout)) 1137 usleep_range(500, 1000); 1138 1139 /* delay for >= 100us for codec PLL to settle per spec 1140 * Rev 0.9 section 5.5.1 1141 */ 1142 usleep_range(500, 1000); 1143 1144 /* Bring controller out of reset */ 1145 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET); 1146 1147 timeout = jiffies + msecs_to_jiffies(100); 1148 while (!azx_readb(chip, GCTL) && 1149 time_before(jiffies, timeout)) 1150 usleep_range(500, 1000); 1151 1152 /* Brent Chartrand said to wait >= 540us for codecs to initialize */ 1153 usleep_range(1000, 1200); 1154 1155 __skip: 1156 /* check to see if controller is ready */ 1157 if (!azx_readb(chip, GCTL)) { 1158 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci)); 1159 return -EBUSY; 1160 } 1161 1162 /* Accept unsolicited responses */ 1163 if (!chip->single_cmd) 1164 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | 1165 ICH6_GCTL_UNSOL); 1166 1167 /* detect codecs */ 1168 if (!chip->codec_mask) { 1169 chip->codec_mask = azx_readw(chip, STATESTS); 1170 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask); 1171 } 1172 1173 return 0; 1174 } 1175 1176 1177 /* 1178 * Lowlevel interface 1179 */ 1180 1181 /* enable interrupts */ 1182 static void azx_int_enable(struct azx *chip) 1183 { 1184 /* enable controller CIE and GIE */ 1185 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) | 1186 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN); 1187 } 1188 1189 /* disable interrupts */ 1190 static void azx_int_disable(struct azx *chip) 1191 { 1192 int i; 1193 1194 /* disable interrupts in stream descriptor */ 1195 for (i = 0; i < chip->num_streams; i++) { 1196 struct azx_dev *azx_dev = &chip->azx_dev[i]; 1197 azx_sd_writeb(azx_dev, SD_CTL, 1198 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK); 1199 } 1200 1201 /* disable SIE for all streams */ 1202 azx_writeb(chip, INTCTL, 0); 1203 1204 /* disable controller CIE and GIE */ 1205 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) & 1206 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN)); 1207 } 1208 1209 /* clear interrupts */ 1210 static void azx_int_clear(struct azx *chip) 1211 { 1212 int i; 1213 1214 /* clear stream status */ 1215 for (i = 0; i < chip->num_streams; i++) { 1216 struct azx_dev *azx_dev = &chip->azx_dev[i]; 1217 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); 1218 } 1219 1220 /* clear STATESTS */ 1221 azx_writeb(chip, STATESTS, STATESTS_INT_MASK); 1222 1223 /* clear rirb status */ 1224 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); 1225 1226 /* clear int status */ 1227 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM); 1228 } 1229 1230 /* start a stream */ 1231 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev) 1232 { 1233 /* 1234 * Before stream start, initialize parameter 1235 */ 1236 azx_dev->insufficient = 1; 1237 1238 /* enable SIE */ 1239 azx_writel(chip, INTCTL, 1240 azx_readl(chip, INTCTL) | (1 << azx_dev->index)); 1241 /* set DMA start and interrupt mask */ 1242 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | 1243 SD_CTL_DMA_START | SD_INT_MASK); 1244 } 1245 1246 /* stop DMA */ 1247 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev) 1248 { 1249 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & 1250 ~(SD_CTL_DMA_START | SD_INT_MASK)); 1251 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ 1252 } 1253 1254 /* stop a stream */ 1255 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev) 1256 { 1257 azx_stream_clear(chip, azx_dev); 1258 /* disable SIE */ 1259 azx_writel(chip, INTCTL, 1260 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index)); 1261 } 1262 1263 1264 /* 1265 * reset and start the controller registers 1266 */ 1267 static void azx_init_chip(struct azx *chip, int full_reset) 1268 { 1269 if (chip->initialized) 1270 return; 1271 1272 /* reset controller */ 1273 azx_reset(chip, full_reset); 1274 1275 /* initialize interrupts */ 1276 azx_int_clear(chip); 1277 azx_int_enable(chip); 1278 1279 /* initialize the codec command I/O */ 1280 if (!chip->single_cmd) 1281 azx_init_cmd_io(chip); 1282 1283 /* program the position buffer */ 1284 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr); 1285 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr)); 1286 1287 chip->initialized = 1; 1288 } 1289 1290 /* 1291 * initialize the PCI registers 1292 */ 1293 /* update bits in a PCI register byte */ 1294 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 1295 unsigned char mask, unsigned char val) 1296 { 1297 unsigned char data; 1298 1299 pci_read_config_byte(pci, reg, &data); 1300 data &= ~mask; 1301 data |= (val & mask); 1302 pci_write_config_byte(pci, reg, data); 1303 } 1304 1305 static void azx_init_pci(struct azx *chip) 1306 { 1307 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 1308 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 1309 * Ensuring these bits are 0 clears playback static on some HD Audio 1310 * codecs. 1311 * The PCI register TCSEL is defined in the Intel manuals. 1312 */ 1313 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 1314 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci)); 1315 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0); 1316 } 1317 1318 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 1319 * we need to enable snoop. 1320 */ 1321 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) { 1322 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip)); 1323 update_pci_byte(chip->pci, 1324 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 1325 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 1326 } 1327 1328 /* For NVIDIA HDA, enable snoop */ 1329 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) { 1330 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip)); 1331 update_pci_byte(chip->pci, 1332 NVIDIA_HDA_TRANSREG_ADDR, 1333 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 1334 update_pci_byte(chip->pci, 1335 NVIDIA_HDA_ISTRM_COH, 1336 0x01, NVIDIA_HDA_ENABLE_COHBIT); 1337 update_pci_byte(chip->pci, 1338 NVIDIA_HDA_OSTRM_COH, 1339 0x01, NVIDIA_HDA_ENABLE_COHBIT); 1340 } 1341 1342 /* Enable SCH/PCH snoop if needed */ 1343 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) { 1344 unsigned short snoop; 1345 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 1346 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 1347 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 1348 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 1349 if (!azx_snoop(chip)) 1350 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 1351 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 1352 pci_read_config_word(chip->pci, 1353 INTEL_SCH_HDA_DEVC, &snoop); 1354 } 1355 snd_printdd(SFX "%s: SCH snoop: %s\n", 1356 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) 1357 ? "Disabled" : "Enabled"); 1358 } 1359 } 1360 1361 1362 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 1363 1364 /* 1365 * interrupt handler 1366 */ 1367 static irqreturn_t azx_interrupt(int irq, void *dev_id) 1368 { 1369 struct azx *chip = dev_id; 1370 struct azx_dev *azx_dev; 1371 u32 status; 1372 u8 sd_status; 1373 int i, ok; 1374 1375 #ifdef CONFIG_PM_RUNTIME 1376 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE) 1377 return IRQ_NONE; 1378 #endif 1379 1380 spin_lock(&chip->reg_lock); 1381 1382 if (chip->disabled) { 1383 spin_unlock(&chip->reg_lock); 1384 return IRQ_NONE; 1385 } 1386 1387 status = azx_readl(chip, INTSTS); 1388 if (status == 0) { 1389 spin_unlock(&chip->reg_lock); 1390 return IRQ_NONE; 1391 } 1392 1393 for (i = 0; i < chip->num_streams; i++) { 1394 azx_dev = &chip->azx_dev[i]; 1395 if (status & azx_dev->sd_int_sta_mask) { 1396 sd_status = azx_sd_readb(azx_dev, SD_STS); 1397 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); 1398 if (!azx_dev->substream || !azx_dev->running || 1399 !(sd_status & SD_INT_COMPLETE)) 1400 continue; 1401 /* check whether this IRQ is really acceptable */ 1402 ok = azx_position_ok(chip, azx_dev); 1403 if (ok == 1) { 1404 azx_dev->irq_pending = 0; 1405 spin_unlock(&chip->reg_lock); 1406 snd_pcm_period_elapsed(azx_dev->substream); 1407 spin_lock(&chip->reg_lock); 1408 } else if (ok == 0 && chip->bus && chip->bus->workq) { 1409 /* bogus IRQ, process it later */ 1410 azx_dev->irq_pending = 1; 1411 queue_work(chip->bus->workq, 1412 &chip->irq_pending_work); 1413 } 1414 } 1415 } 1416 1417 /* clear rirb int */ 1418 status = azx_readb(chip, RIRBSTS); 1419 if (status & RIRB_INT_MASK) { 1420 if (status & RIRB_INT_RESPONSE) { 1421 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY) 1422 udelay(80); 1423 azx_update_rirb(chip); 1424 } 1425 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); 1426 } 1427 1428 #if 0 1429 /* clear state status int */ 1430 if (azx_readb(chip, STATESTS) & 0x04) 1431 azx_writeb(chip, STATESTS, 0x04); 1432 #endif 1433 spin_unlock(&chip->reg_lock); 1434 1435 return IRQ_HANDLED; 1436 } 1437 1438 1439 /* 1440 * set up a BDL entry 1441 */ 1442 static int setup_bdle(struct azx *chip, 1443 struct snd_dma_buffer *dmab, 1444 struct azx_dev *azx_dev, u32 **bdlp, 1445 int ofs, int size, int with_ioc) 1446 { 1447 u32 *bdl = *bdlp; 1448 1449 while (size > 0) { 1450 dma_addr_t addr; 1451 int chunk; 1452 1453 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES) 1454 return -EINVAL; 1455 1456 addr = snd_sgbuf_get_addr(dmab, ofs); 1457 /* program the address field of the BDL entry */ 1458 bdl[0] = cpu_to_le32((u32)addr); 1459 bdl[1] = cpu_to_le32(upper_32_bits(addr)); 1460 /* program the size field of the BDL entry */ 1461 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size); 1462 /* one BDLE cannot cross 4K boundary on CTHDA chips */ 1463 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) { 1464 u32 remain = 0x1000 - (ofs & 0xfff); 1465 if (chunk > remain) 1466 chunk = remain; 1467 } 1468 bdl[2] = cpu_to_le32(chunk); 1469 /* program the IOC to enable interrupt 1470 * only when the whole fragment is processed 1471 */ 1472 size -= chunk; 1473 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01); 1474 bdl += 4; 1475 azx_dev->frags++; 1476 ofs += chunk; 1477 } 1478 *bdlp = bdl; 1479 return ofs; 1480 } 1481 1482 /* 1483 * set up BDL entries 1484 */ 1485 static int azx_setup_periods(struct azx *chip, 1486 struct snd_pcm_substream *substream, 1487 struct azx_dev *azx_dev) 1488 { 1489 u32 *bdl; 1490 int i, ofs, periods, period_bytes; 1491 int pos_adj; 1492 1493 /* reset BDL address */ 1494 azx_sd_writel(azx_dev, SD_BDLPL, 0); 1495 azx_sd_writel(azx_dev, SD_BDLPU, 0); 1496 1497 period_bytes = azx_dev->period_bytes; 1498 periods = azx_dev->bufsize / period_bytes; 1499 1500 /* program the initial BDL entries */ 1501 bdl = (u32 *)azx_dev->bdl.area; 1502 ofs = 0; 1503 azx_dev->frags = 0; 1504 pos_adj = bdl_pos_adj[chip->dev_index]; 1505 if (!azx_dev->no_period_wakeup && pos_adj > 0) { 1506 struct snd_pcm_runtime *runtime = substream->runtime; 1507 int pos_align = pos_adj; 1508 pos_adj = (pos_adj * runtime->rate + 47999) / 48000; 1509 if (!pos_adj) 1510 pos_adj = pos_align; 1511 else 1512 pos_adj = ((pos_adj + pos_align - 1) / pos_align) * 1513 pos_align; 1514 pos_adj = frames_to_bytes(runtime, pos_adj); 1515 if (pos_adj >= period_bytes) { 1516 snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n", 1517 pci_name(chip->pci), bdl_pos_adj[chip->dev_index]); 1518 pos_adj = 0; 1519 } else { 1520 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), 1521 azx_dev, 1522 &bdl, ofs, pos_adj, true); 1523 if (ofs < 0) 1524 goto error; 1525 } 1526 } else 1527 pos_adj = 0; 1528 for (i = 0; i < periods; i++) { 1529 if (i == periods - 1 && pos_adj) 1530 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), 1531 azx_dev, &bdl, ofs, 1532 period_bytes - pos_adj, 0); 1533 else 1534 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), 1535 azx_dev, &bdl, ofs, 1536 period_bytes, 1537 !azx_dev->no_period_wakeup); 1538 if (ofs < 0) 1539 goto error; 1540 } 1541 return 0; 1542 1543 error: 1544 snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n", 1545 pci_name(chip->pci), azx_dev->bufsize, period_bytes); 1546 return -EINVAL; 1547 } 1548 1549 /* reset stream */ 1550 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev) 1551 { 1552 unsigned char val; 1553 int timeout; 1554 1555 azx_stream_clear(chip, azx_dev); 1556 1557 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | 1558 SD_CTL_STREAM_RESET); 1559 udelay(3); 1560 timeout = 300; 1561 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && 1562 --timeout) 1563 ; 1564 val &= ~SD_CTL_STREAM_RESET; 1565 azx_sd_writeb(azx_dev, SD_CTL, val); 1566 udelay(3); 1567 1568 timeout = 300; 1569 /* waiting for hardware to report that the stream is out of reset */ 1570 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && 1571 --timeout) 1572 ; 1573 1574 /* reset first position - may not be synced with hw at this time */ 1575 *azx_dev->posbuf = 0; 1576 } 1577 1578 /* 1579 * set up the SD for streaming 1580 */ 1581 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev) 1582 { 1583 unsigned int val; 1584 /* make sure the run bit is zero for SD */ 1585 azx_stream_clear(chip, azx_dev); 1586 /* program the stream_tag */ 1587 val = azx_sd_readl(azx_dev, SD_CTL); 1588 val = (val & ~SD_CTL_STREAM_TAG_MASK) | 1589 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT); 1590 if (!azx_snoop(chip)) 1591 val |= SD_CTL_TRAFFIC_PRIO; 1592 azx_sd_writel(azx_dev, SD_CTL, val); 1593 1594 /* program the length of samples in cyclic buffer */ 1595 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize); 1596 1597 /* program the stream format */ 1598 /* this value needs to be the same as the one programmed */ 1599 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val); 1600 1601 /* program the stream LVI (last valid index) of the BDL */ 1602 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1); 1603 1604 /* program the BDL address */ 1605 /* lower BDL address */ 1606 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); 1607 /* upper BDL address */ 1608 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr)); 1609 1610 /* enable the position buffer */ 1611 if (chip->position_fix[0] != POS_FIX_LPIB || 1612 chip->position_fix[1] != POS_FIX_LPIB) { 1613 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE)) 1614 azx_writel(chip, DPLBASE, 1615 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE); 1616 } 1617 1618 /* set the interrupt enable bits in the descriptor control register */ 1619 azx_sd_writel(azx_dev, SD_CTL, 1620 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK); 1621 1622 return 0; 1623 } 1624 1625 /* 1626 * Probe the given codec address 1627 */ 1628 static int probe_codec(struct azx *chip, int addr) 1629 { 1630 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | 1631 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; 1632 unsigned int res; 1633 1634 mutex_lock(&chip->bus->cmd_mutex); 1635 chip->probing = 1; 1636 azx_send_cmd(chip->bus, cmd); 1637 res = azx_get_response(chip->bus, addr); 1638 chip->probing = 0; 1639 mutex_unlock(&chip->bus->cmd_mutex); 1640 if (res == -1) 1641 return -EIO; 1642 snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr); 1643 return 0; 1644 } 1645 1646 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, 1647 struct hda_pcm *cpcm); 1648 static void azx_stop_chip(struct azx *chip); 1649 1650 static void azx_bus_reset(struct hda_bus *bus) 1651 { 1652 struct azx *chip = bus->private_data; 1653 1654 bus->in_reset = 1; 1655 azx_stop_chip(chip); 1656 azx_init_chip(chip, 1); 1657 #ifdef CONFIG_PM 1658 if (chip->initialized) { 1659 struct azx_pcm *p; 1660 list_for_each_entry(p, &chip->pcm_list, list) 1661 snd_pcm_suspend_all(p->pcm); 1662 snd_hda_suspend(chip->bus); 1663 snd_hda_resume(chip->bus); 1664 } 1665 #endif 1666 bus->in_reset = 0; 1667 } 1668 1669 static int get_jackpoll_interval(struct azx *chip) 1670 { 1671 int i = jackpoll_ms[chip->dev_index]; 1672 unsigned int j; 1673 if (i == 0) 1674 return 0; 1675 if (i < 50 || i > 60000) 1676 j = 0; 1677 else 1678 j = msecs_to_jiffies(i); 1679 if (j == 0) 1680 snd_printk(KERN_WARNING SFX 1681 "jackpoll_ms value out of range: %d\n", i); 1682 return j; 1683 } 1684 1685 /* 1686 * Codec initialization 1687 */ 1688 1689 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 1690 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 1691 [AZX_DRIVER_NVIDIA] = 8, 1692 [AZX_DRIVER_TERA] = 1, 1693 }; 1694 1695 static int azx_codec_create(struct azx *chip, const char *model) 1696 { 1697 struct hda_bus_template bus_temp; 1698 int c, codecs, err; 1699 int max_slots; 1700 1701 memset(&bus_temp, 0, sizeof(bus_temp)); 1702 bus_temp.private_data = chip; 1703 bus_temp.modelname = model; 1704 bus_temp.pci = chip->pci; 1705 bus_temp.ops.command = azx_send_cmd; 1706 bus_temp.ops.get_response = azx_get_response; 1707 bus_temp.ops.attach_pcm = azx_attach_pcm_stream; 1708 bus_temp.ops.bus_reset = azx_bus_reset; 1709 #ifdef CONFIG_PM 1710 bus_temp.power_save = &power_save; 1711 bus_temp.ops.pm_notify = azx_power_notify; 1712 #endif 1713 #ifdef CONFIG_SND_HDA_DSP_LOADER 1714 bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare; 1715 bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger; 1716 bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup; 1717 #endif 1718 1719 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus); 1720 if (err < 0) 1721 return err; 1722 1723 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) { 1724 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci)); 1725 chip->bus->needs_damn_long_delay = 1; 1726 } 1727 1728 codecs = 0; 1729 max_slots = azx_max_codecs[chip->driver_type]; 1730 if (!max_slots) 1731 max_slots = AZX_DEFAULT_CODECS; 1732 1733 /* First try to probe all given codec slots */ 1734 for (c = 0; c < max_slots; c++) { 1735 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { 1736 if (probe_codec(chip, c) < 0) { 1737 /* Some BIOSen give you wrong codec addresses 1738 * that don't exist 1739 */ 1740 snd_printk(KERN_WARNING SFX 1741 "%s: Codec #%d probe error; " 1742 "disabling it...\n", pci_name(chip->pci), c); 1743 chip->codec_mask &= ~(1 << c); 1744 /* More badly, accessing to a non-existing 1745 * codec often screws up the controller chip, 1746 * and disturbs the further communications. 1747 * Thus if an error occurs during probing, 1748 * better to reset the controller chip to 1749 * get back to the sanity state. 1750 */ 1751 azx_stop_chip(chip); 1752 azx_init_chip(chip, 1); 1753 } 1754 } 1755 } 1756 1757 /* AMD chipsets often cause the communication stalls upon certain 1758 * sequence like the pin-detection. It seems that forcing the synced 1759 * access works around the stall. Grrr... 1760 */ 1761 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) { 1762 snd_printd(SFX "%s: Enable sync_write for stable communication\n", 1763 pci_name(chip->pci)); 1764 chip->bus->sync_write = 1; 1765 chip->bus->allow_bus_reset = 1; 1766 } 1767 1768 /* Then create codec instances */ 1769 for (c = 0; c < max_slots; c++) { 1770 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { 1771 struct hda_codec *codec; 1772 err = snd_hda_codec_new(chip->bus, c, &codec); 1773 if (err < 0) 1774 continue; 1775 codec->jackpoll_interval = get_jackpoll_interval(chip); 1776 codec->beep_mode = chip->beep_mode; 1777 codecs++; 1778 } 1779 } 1780 if (!codecs) { 1781 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci)); 1782 return -ENXIO; 1783 } 1784 return 0; 1785 } 1786 1787 /* configure each codec instance */ 1788 static int azx_codec_configure(struct azx *chip) 1789 { 1790 struct hda_codec *codec; 1791 list_for_each_entry(codec, &chip->bus->codec_list, list) { 1792 snd_hda_codec_configure(codec); 1793 } 1794 return 0; 1795 } 1796 1797 1798 /* 1799 * PCM support 1800 */ 1801 1802 /* assign a stream for the PCM */ 1803 static inline struct azx_dev * 1804 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream) 1805 { 1806 int dev, i, nums; 1807 struct azx_dev *res = NULL; 1808 /* make a non-zero unique key for the substream */ 1809 int key = (substream->pcm->device << 16) | (substream->number << 2) | 1810 (substream->stream + 1); 1811 1812 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1813 dev = chip->playback_index_offset; 1814 nums = chip->playback_streams; 1815 } else { 1816 dev = chip->capture_index_offset; 1817 nums = chip->capture_streams; 1818 } 1819 for (i = 0; i < nums; i++, dev++) { 1820 struct azx_dev *azx_dev = &chip->azx_dev[dev]; 1821 dsp_lock(azx_dev); 1822 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) { 1823 res = azx_dev; 1824 if (res->assigned_key == key) { 1825 res->opened = 1; 1826 res->assigned_key = key; 1827 dsp_unlock(azx_dev); 1828 return azx_dev; 1829 } 1830 } 1831 dsp_unlock(azx_dev); 1832 } 1833 if (res) { 1834 dsp_lock(res); 1835 res->opened = 1; 1836 res->assigned_key = key; 1837 dsp_unlock(res); 1838 } 1839 return res; 1840 } 1841 1842 /* release the assigned stream */ 1843 static inline void azx_release_device(struct azx_dev *azx_dev) 1844 { 1845 azx_dev->opened = 0; 1846 } 1847 1848 static cycle_t azx_cc_read(const struct cyclecounter *cc) 1849 { 1850 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc); 1851 struct snd_pcm_substream *substream = azx_dev->substream; 1852 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1853 struct azx *chip = apcm->chip; 1854 1855 return azx_readl(chip, WALLCLK); 1856 } 1857 1858 static void azx_timecounter_init(struct snd_pcm_substream *substream, 1859 bool force, cycle_t last) 1860 { 1861 struct azx_dev *azx_dev = get_azx_dev(substream); 1862 struct timecounter *tc = &azx_dev->azx_tc; 1863 struct cyclecounter *cc = &azx_dev->azx_cc; 1864 u64 nsec; 1865 1866 cc->read = azx_cc_read; 1867 cc->mask = CLOCKSOURCE_MASK(32); 1868 1869 /* 1870 * Converting from 24 MHz to ns means applying a 125/3 factor. 1871 * To avoid any saturation issues in intermediate operations, 1872 * the 125 factor is applied first. The division is applied 1873 * last after reading the timecounter value. 1874 * Applying the 1/3 factor as part of the multiplication 1875 * requires at least 20 bits for a decent precision, however 1876 * overflows occur after about 4 hours or less, not a option. 1877 */ 1878 1879 cc->mult = 125; /* saturation after 195 years */ 1880 cc->shift = 0; 1881 1882 nsec = 0; /* audio time is elapsed time since trigger */ 1883 timecounter_init(tc, cc, nsec); 1884 if (force) 1885 /* 1886 * force timecounter to use predefined value, 1887 * used for synchronized starts 1888 */ 1889 tc->cycle_last = last; 1890 } 1891 1892 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream, 1893 u64 nsec) 1894 { 1895 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1896 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 1897 u64 codec_frames, codec_nsecs; 1898 1899 if (!hinfo->ops.get_delay) 1900 return nsec; 1901 1902 codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream); 1903 codec_nsecs = div_u64(codec_frames * 1000000000LL, 1904 substream->runtime->rate); 1905 1906 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 1907 return nsec + codec_nsecs; 1908 1909 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0; 1910 } 1911 1912 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream, 1913 struct timespec *ts) 1914 { 1915 struct azx_dev *azx_dev = get_azx_dev(substream); 1916 u64 nsec; 1917 1918 nsec = timecounter_read(&azx_dev->azx_tc); 1919 nsec = div_u64(nsec, 3); /* can be optimized */ 1920 nsec = azx_adjust_codec_delay(substream, nsec); 1921 1922 *ts = ns_to_timespec(nsec); 1923 1924 return 0; 1925 } 1926 1927 static struct snd_pcm_hardware azx_pcm_hw = { 1928 .info = (SNDRV_PCM_INFO_MMAP | 1929 SNDRV_PCM_INFO_INTERLEAVED | 1930 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1931 SNDRV_PCM_INFO_MMAP_VALID | 1932 /* No full-resume yet implemented */ 1933 /* SNDRV_PCM_INFO_RESUME |*/ 1934 SNDRV_PCM_INFO_PAUSE | 1935 SNDRV_PCM_INFO_SYNC_START | 1936 SNDRV_PCM_INFO_HAS_WALL_CLOCK | 1937 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), 1938 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1939 .rates = SNDRV_PCM_RATE_48000, 1940 .rate_min = 48000, 1941 .rate_max = 48000, 1942 .channels_min = 2, 1943 .channels_max = 2, 1944 .buffer_bytes_max = AZX_MAX_BUF_SIZE, 1945 .period_bytes_min = 128, 1946 .period_bytes_max = AZX_MAX_BUF_SIZE / 2, 1947 .periods_min = 2, 1948 .periods_max = AZX_MAX_FRAG, 1949 .fifo_size = 0, 1950 }; 1951 1952 static int azx_pcm_open(struct snd_pcm_substream *substream) 1953 { 1954 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1955 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 1956 struct azx *chip = apcm->chip; 1957 struct azx_dev *azx_dev; 1958 struct snd_pcm_runtime *runtime = substream->runtime; 1959 unsigned long flags; 1960 int err; 1961 int buff_step; 1962 1963 mutex_lock(&chip->open_mutex); 1964 azx_dev = azx_assign_device(chip, substream); 1965 if (azx_dev == NULL) { 1966 mutex_unlock(&chip->open_mutex); 1967 return -EBUSY; 1968 } 1969 runtime->hw = azx_pcm_hw; 1970 runtime->hw.channels_min = hinfo->channels_min; 1971 runtime->hw.channels_max = hinfo->channels_max; 1972 runtime->hw.formats = hinfo->formats; 1973 runtime->hw.rates = hinfo->rates; 1974 snd_pcm_limit_hw_rates(runtime); 1975 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); 1976 1977 /* avoid wrap-around with wall-clock */ 1978 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME, 1979 20, 1980 178000000); 1981 1982 if (chip->align_buffer_size) 1983 /* constrain buffer sizes to be multiple of 128 1984 bytes. This is more efficient in terms of memory 1985 access but isn't required by the HDA spec and 1986 prevents users from specifying exact period/buffer 1987 sizes. For example for 44.1kHz, a period size set 1988 to 20ms will be rounded to 19.59ms. */ 1989 buff_step = 128; 1990 else 1991 /* Don't enforce steps on buffer sizes, still need to 1992 be multiple of 4 bytes (HDA spec). Tested on Intel 1993 HDA controllers, may not work on all devices where 1994 option needs to be disabled */ 1995 buff_step = 4; 1996 1997 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 1998 buff_step); 1999 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 2000 buff_step); 2001 snd_hda_power_up_d3wait(apcm->codec); 2002 err = hinfo->ops.open(hinfo, apcm->codec, substream); 2003 if (err < 0) { 2004 azx_release_device(azx_dev); 2005 snd_hda_power_down(apcm->codec); 2006 mutex_unlock(&chip->open_mutex); 2007 return err; 2008 } 2009 snd_pcm_limit_hw_rates(runtime); 2010 /* sanity check */ 2011 if (snd_BUG_ON(!runtime->hw.channels_min) || 2012 snd_BUG_ON(!runtime->hw.channels_max) || 2013 snd_BUG_ON(!runtime->hw.formats) || 2014 snd_BUG_ON(!runtime->hw.rates)) { 2015 azx_release_device(azx_dev); 2016 hinfo->ops.close(hinfo, apcm->codec, substream); 2017 snd_hda_power_down(apcm->codec); 2018 mutex_unlock(&chip->open_mutex); 2019 return -EINVAL; 2020 } 2021 2022 /* disable WALLCLOCK timestamps for capture streams 2023 until we figure out how to handle digital inputs */ 2024 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 2025 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; 2026 2027 spin_lock_irqsave(&chip->reg_lock, flags); 2028 azx_dev->substream = substream; 2029 azx_dev->running = 0; 2030 spin_unlock_irqrestore(&chip->reg_lock, flags); 2031 2032 runtime->private_data = azx_dev; 2033 snd_pcm_set_sync(substream); 2034 mutex_unlock(&chip->open_mutex); 2035 return 0; 2036 } 2037 2038 static int azx_pcm_close(struct snd_pcm_substream *substream) 2039 { 2040 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2041 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 2042 struct azx *chip = apcm->chip; 2043 struct azx_dev *azx_dev = get_azx_dev(substream); 2044 unsigned long flags; 2045 2046 mutex_lock(&chip->open_mutex); 2047 spin_lock_irqsave(&chip->reg_lock, flags); 2048 azx_dev->substream = NULL; 2049 azx_dev->running = 0; 2050 spin_unlock_irqrestore(&chip->reg_lock, flags); 2051 azx_release_device(azx_dev); 2052 hinfo->ops.close(hinfo, apcm->codec, substream); 2053 snd_hda_power_down(apcm->codec); 2054 mutex_unlock(&chip->open_mutex); 2055 return 0; 2056 } 2057 2058 static int azx_pcm_hw_params(struct snd_pcm_substream *substream, 2059 struct snd_pcm_hw_params *hw_params) 2060 { 2061 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2062 struct azx *chip = apcm->chip; 2063 struct azx_dev *azx_dev = get_azx_dev(substream); 2064 int ret; 2065 2066 dsp_lock(azx_dev); 2067 if (dsp_is_locked(azx_dev)) { 2068 ret = -EBUSY; 2069 goto unlock; 2070 } 2071 2072 mark_runtime_wc(chip, azx_dev, substream, false); 2073 azx_dev->bufsize = 0; 2074 azx_dev->period_bytes = 0; 2075 azx_dev->format_val = 0; 2076 ret = snd_pcm_lib_malloc_pages(substream, 2077 params_buffer_bytes(hw_params)); 2078 if (ret < 0) 2079 goto unlock; 2080 mark_runtime_wc(chip, azx_dev, substream, true); 2081 unlock: 2082 dsp_unlock(azx_dev); 2083 return ret; 2084 } 2085 2086 static int azx_pcm_hw_free(struct snd_pcm_substream *substream) 2087 { 2088 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2089 struct azx_dev *azx_dev = get_azx_dev(substream); 2090 struct azx *chip = apcm->chip; 2091 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 2092 2093 /* reset BDL address */ 2094 dsp_lock(azx_dev); 2095 if (!dsp_is_locked(azx_dev)) { 2096 azx_sd_writel(azx_dev, SD_BDLPL, 0); 2097 azx_sd_writel(azx_dev, SD_BDLPU, 0); 2098 azx_sd_writel(azx_dev, SD_CTL, 0); 2099 azx_dev->bufsize = 0; 2100 azx_dev->period_bytes = 0; 2101 azx_dev->format_val = 0; 2102 } 2103 2104 snd_hda_codec_cleanup(apcm->codec, hinfo, substream); 2105 2106 mark_runtime_wc(chip, azx_dev, substream, false); 2107 azx_dev->prepared = 0; 2108 dsp_unlock(azx_dev); 2109 return snd_pcm_lib_free_pages(substream); 2110 } 2111 2112 static int azx_pcm_prepare(struct snd_pcm_substream *substream) 2113 { 2114 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2115 struct azx *chip = apcm->chip; 2116 struct azx_dev *azx_dev = get_azx_dev(substream); 2117 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 2118 struct snd_pcm_runtime *runtime = substream->runtime; 2119 unsigned int bufsize, period_bytes, format_val, stream_tag; 2120 int err; 2121 struct hda_spdif_out *spdif = 2122 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid); 2123 unsigned short ctls = spdif ? spdif->ctls : 0; 2124 2125 dsp_lock(azx_dev); 2126 if (dsp_is_locked(azx_dev)) { 2127 err = -EBUSY; 2128 goto unlock; 2129 } 2130 2131 azx_stream_reset(chip, azx_dev); 2132 format_val = snd_hda_calc_stream_format(runtime->rate, 2133 runtime->channels, 2134 runtime->format, 2135 hinfo->maxbps, 2136 ctls); 2137 if (!format_val) { 2138 snd_printk(KERN_ERR SFX 2139 "%s: invalid format_val, rate=%d, ch=%d, format=%d\n", 2140 pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format); 2141 err = -EINVAL; 2142 goto unlock; 2143 } 2144 2145 bufsize = snd_pcm_lib_buffer_bytes(substream); 2146 period_bytes = snd_pcm_lib_period_bytes(substream); 2147 2148 snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n", 2149 pci_name(chip->pci), bufsize, format_val); 2150 2151 if (bufsize != azx_dev->bufsize || 2152 period_bytes != azx_dev->period_bytes || 2153 format_val != azx_dev->format_val || 2154 runtime->no_period_wakeup != azx_dev->no_period_wakeup) { 2155 azx_dev->bufsize = bufsize; 2156 azx_dev->period_bytes = period_bytes; 2157 azx_dev->format_val = format_val; 2158 azx_dev->no_period_wakeup = runtime->no_period_wakeup; 2159 err = azx_setup_periods(chip, substream, azx_dev); 2160 if (err < 0) 2161 goto unlock; 2162 } 2163 2164 /* wallclk has 24Mhz clock source */ 2165 azx_dev->period_wallclk = (((runtime->period_size * 24000) / 2166 runtime->rate) * 1000); 2167 azx_setup_controller(chip, azx_dev); 2168 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 2169 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1; 2170 else 2171 azx_dev->fifo_size = 0; 2172 2173 stream_tag = azx_dev->stream_tag; 2174 /* CA-IBG chips need the playback stream starting from 1 */ 2175 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) && 2176 stream_tag > chip->capture_streams) 2177 stream_tag -= chip->capture_streams; 2178 err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag, 2179 azx_dev->format_val, substream); 2180 2181 unlock: 2182 if (!err) 2183 azx_dev->prepared = 1; 2184 dsp_unlock(azx_dev); 2185 return err; 2186 } 2187 2188 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 2189 { 2190 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2191 struct azx *chip = apcm->chip; 2192 struct azx_dev *azx_dev; 2193 struct snd_pcm_substream *s; 2194 int rstart = 0, start, nsync = 0, sbits = 0; 2195 int nwait, timeout; 2196 2197 azx_dev = get_azx_dev(substream); 2198 trace_azx_pcm_trigger(chip, azx_dev, cmd); 2199 2200 if (dsp_is_locked(azx_dev) || !azx_dev->prepared) 2201 return -EPIPE; 2202 2203 switch (cmd) { 2204 case SNDRV_PCM_TRIGGER_START: 2205 rstart = 1; 2206 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 2207 case SNDRV_PCM_TRIGGER_RESUME: 2208 start = 1; 2209 break; 2210 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 2211 case SNDRV_PCM_TRIGGER_SUSPEND: 2212 case SNDRV_PCM_TRIGGER_STOP: 2213 start = 0; 2214 break; 2215 default: 2216 return -EINVAL; 2217 } 2218 2219 snd_pcm_group_for_each_entry(s, substream) { 2220 if (s->pcm->card != substream->pcm->card) 2221 continue; 2222 azx_dev = get_azx_dev(s); 2223 sbits |= 1 << azx_dev->index; 2224 nsync++; 2225 snd_pcm_trigger_done(s, substream); 2226 } 2227 2228 spin_lock(&chip->reg_lock); 2229 2230 /* first, set SYNC bits of corresponding streams */ 2231 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC) 2232 azx_writel(chip, OLD_SSYNC, 2233 azx_readl(chip, OLD_SSYNC) | sbits); 2234 else 2235 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits); 2236 2237 snd_pcm_group_for_each_entry(s, substream) { 2238 if (s->pcm->card != substream->pcm->card) 2239 continue; 2240 azx_dev = get_azx_dev(s); 2241 if (start) { 2242 azx_dev->start_wallclk = azx_readl(chip, WALLCLK); 2243 if (!rstart) 2244 azx_dev->start_wallclk -= 2245 azx_dev->period_wallclk; 2246 azx_stream_start(chip, azx_dev); 2247 } else { 2248 azx_stream_stop(chip, azx_dev); 2249 } 2250 azx_dev->running = start; 2251 } 2252 spin_unlock(&chip->reg_lock); 2253 if (start) { 2254 /* wait until all FIFOs get ready */ 2255 for (timeout = 5000; timeout; timeout--) { 2256 nwait = 0; 2257 snd_pcm_group_for_each_entry(s, substream) { 2258 if (s->pcm->card != substream->pcm->card) 2259 continue; 2260 azx_dev = get_azx_dev(s); 2261 if (!(azx_sd_readb(azx_dev, SD_STS) & 2262 SD_STS_FIFO_READY)) 2263 nwait++; 2264 } 2265 if (!nwait) 2266 break; 2267 cpu_relax(); 2268 } 2269 } else { 2270 /* wait until all RUN bits are cleared */ 2271 for (timeout = 5000; timeout; timeout--) { 2272 nwait = 0; 2273 snd_pcm_group_for_each_entry(s, substream) { 2274 if (s->pcm->card != substream->pcm->card) 2275 continue; 2276 azx_dev = get_azx_dev(s); 2277 if (azx_sd_readb(azx_dev, SD_CTL) & 2278 SD_CTL_DMA_START) 2279 nwait++; 2280 } 2281 if (!nwait) 2282 break; 2283 cpu_relax(); 2284 } 2285 } 2286 spin_lock(&chip->reg_lock); 2287 /* reset SYNC bits */ 2288 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC) 2289 azx_writel(chip, OLD_SSYNC, 2290 azx_readl(chip, OLD_SSYNC) & ~sbits); 2291 else 2292 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits); 2293 if (start) { 2294 azx_timecounter_init(substream, 0, 0); 2295 if (nsync > 1) { 2296 cycle_t cycle_last; 2297 2298 /* same start cycle for master and group */ 2299 azx_dev = get_azx_dev(substream); 2300 cycle_last = azx_dev->azx_tc.cycle_last; 2301 2302 snd_pcm_group_for_each_entry(s, substream) { 2303 if (s->pcm->card != substream->pcm->card) 2304 continue; 2305 azx_timecounter_init(s, 1, cycle_last); 2306 } 2307 } 2308 } 2309 spin_unlock(&chip->reg_lock); 2310 return 0; 2311 } 2312 2313 /* get the current DMA position with correction on VIA chips */ 2314 static unsigned int azx_via_get_position(struct azx *chip, 2315 struct azx_dev *azx_dev) 2316 { 2317 unsigned int link_pos, mini_pos, bound_pos; 2318 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 2319 unsigned int fifo_size; 2320 2321 link_pos = azx_sd_readl(azx_dev, SD_LPIB); 2322 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 2323 /* Playback, no problem using link position */ 2324 return link_pos; 2325 } 2326 2327 /* Capture */ 2328 /* For new chipset, 2329 * use mod to get the DMA position just like old chipset 2330 */ 2331 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf); 2332 mod_dma_pos %= azx_dev->period_bytes; 2333 2334 /* azx_dev->fifo_size can't get FIFO size of in stream. 2335 * Get from base address + offset. 2336 */ 2337 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET); 2338 2339 if (azx_dev->insufficient) { 2340 /* Link position never gather than FIFO size */ 2341 if (link_pos <= fifo_size) 2342 return 0; 2343 2344 azx_dev->insufficient = 0; 2345 } 2346 2347 if (link_pos <= fifo_size) 2348 mini_pos = azx_dev->bufsize + link_pos - fifo_size; 2349 else 2350 mini_pos = link_pos - fifo_size; 2351 2352 /* Find nearest previous boudary */ 2353 mod_mini_pos = mini_pos % azx_dev->period_bytes; 2354 mod_link_pos = link_pos % azx_dev->period_bytes; 2355 if (mod_link_pos >= fifo_size) 2356 bound_pos = link_pos - mod_link_pos; 2357 else if (mod_dma_pos >= mod_mini_pos) 2358 bound_pos = mini_pos - mod_mini_pos; 2359 else { 2360 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes; 2361 if (bound_pos >= azx_dev->bufsize) 2362 bound_pos = 0; 2363 } 2364 2365 /* Calculate real DMA position we want */ 2366 return bound_pos + mod_dma_pos; 2367 } 2368 2369 static unsigned int azx_get_position(struct azx *chip, 2370 struct azx_dev *azx_dev, 2371 bool with_check) 2372 { 2373 struct snd_pcm_substream *substream = azx_dev->substream; 2374 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2375 unsigned int pos; 2376 int stream = substream->stream; 2377 struct hda_pcm_stream *hinfo = apcm->hinfo[stream]; 2378 int delay = 0; 2379 2380 switch (chip->position_fix[stream]) { 2381 case POS_FIX_LPIB: 2382 /* read LPIB */ 2383 pos = azx_sd_readl(azx_dev, SD_LPIB); 2384 break; 2385 case POS_FIX_VIACOMBO: 2386 pos = azx_via_get_position(chip, azx_dev); 2387 break; 2388 default: 2389 /* use the position buffer */ 2390 pos = le32_to_cpu(*azx_dev->posbuf); 2391 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) { 2392 if (!pos || pos == (u32)-1) { 2393 printk(KERN_WARNING 2394 "hda-intel: Invalid position buffer, " 2395 "using LPIB read method instead.\n"); 2396 chip->position_fix[stream] = POS_FIX_LPIB; 2397 pos = azx_sd_readl(azx_dev, SD_LPIB); 2398 } else 2399 chip->position_fix[stream] = POS_FIX_POSBUF; 2400 } 2401 break; 2402 } 2403 2404 if (pos >= azx_dev->bufsize) 2405 pos = 0; 2406 2407 /* calculate runtime delay from LPIB */ 2408 if (substream->runtime && 2409 chip->position_fix[stream] == POS_FIX_POSBUF && 2410 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 2411 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB); 2412 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 2413 delay = pos - lpib_pos; 2414 else 2415 delay = lpib_pos - pos; 2416 if (delay < 0) 2417 delay += azx_dev->bufsize; 2418 if (delay >= azx_dev->period_bytes) { 2419 snd_printk(KERN_WARNING SFX 2420 "%s: Unstable LPIB (%d >= %d); " 2421 "disabling LPIB delay counting\n", 2422 pci_name(chip->pci), delay, azx_dev->period_bytes); 2423 delay = 0; 2424 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 2425 } 2426 delay = bytes_to_frames(substream->runtime, delay); 2427 } 2428 2429 if (substream->runtime) { 2430 if (hinfo->ops.get_delay) 2431 delay += hinfo->ops.get_delay(hinfo, apcm->codec, 2432 substream); 2433 substream->runtime->delay = delay; 2434 } 2435 2436 trace_azx_get_position(chip, azx_dev, pos, delay); 2437 return pos; 2438 } 2439 2440 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) 2441 { 2442 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2443 struct azx *chip = apcm->chip; 2444 struct azx_dev *azx_dev = get_azx_dev(substream); 2445 return bytes_to_frames(substream->runtime, 2446 azx_get_position(chip, azx_dev, false)); 2447 } 2448 2449 /* 2450 * Check whether the current DMA position is acceptable for updating 2451 * periods. Returns non-zero if it's OK. 2452 * 2453 * Many HD-audio controllers appear pretty inaccurate about 2454 * the update-IRQ timing. The IRQ is issued before actually the 2455 * data is processed. So, we need to process it afterwords in a 2456 * workqueue. 2457 */ 2458 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 2459 { 2460 u32 wallclk; 2461 unsigned int pos; 2462 2463 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk; 2464 if (wallclk < (azx_dev->period_wallclk * 2) / 3) 2465 return -1; /* bogus (too early) interrupt */ 2466 2467 pos = azx_get_position(chip, azx_dev, true); 2468 2469 if (WARN_ONCE(!azx_dev->period_bytes, 2470 "hda-intel: zero azx_dev->period_bytes")) 2471 return -1; /* this shouldn't happen! */ 2472 if (wallclk < (azx_dev->period_wallclk * 5) / 4 && 2473 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2) 2474 /* NG - it's below the first next period boundary */ 2475 return bdl_pos_adj[chip->dev_index] ? 0 : -1; 2476 azx_dev->start_wallclk += wallclk; 2477 return 1; /* OK, it's fine */ 2478 } 2479 2480 /* 2481 * The work for pending PCM period updates. 2482 */ 2483 static void azx_irq_pending_work(struct work_struct *work) 2484 { 2485 struct azx *chip = container_of(work, struct azx, irq_pending_work); 2486 int i, pending, ok; 2487 2488 if (!chip->irq_pending_warned) { 2489 printk(KERN_WARNING 2490 "hda-intel: IRQ timing workaround is activated " 2491 "for card #%d. Suggest a bigger bdl_pos_adj.\n", 2492 chip->card->number); 2493 chip->irq_pending_warned = 1; 2494 } 2495 2496 for (;;) { 2497 pending = 0; 2498 spin_lock_irq(&chip->reg_lock); 2499 for (i = 0; i < chip->num_streams; i++) { 2500 struct azx_dev *azx_dev = &chip->azx_dev[i]; 2501 if (!azx_dev->irq_pending || 2502 !azx_dev->substream || 2503 !azx_dev->running) 2504 continue; 2505 ok = azx_position_ok(chip, azx_dev); 2506 if (ok > 0) { 2507 azx_dev->irq_pending = 0; 2508 spin_unlock(&chip->reg_lock); 2509 snd_pcm_period_elapsed(azx_dev->substream); 2510 spin_lock(&chip->reg_lock); 2511 } else if (ok < 0) { 2512 pending = 0; /* too early */ 2513 } else 2514 pending++; 2515 } 2516 spin_unlock_irq(&chip->reg_lock); 2517 if (!pending) 2518 return; 2519 msleep(1); 2520 } 2521 } 2522 2523 /* clear irq_pending flags and assure no on-going workq */ 2524 static void azx_clear_irq_pending(struct azx *chip) 2525 { 2526 int i; 2527 2528 spin_lock_irq(&chip->reg_lock); 2529 for (i = 0; i < chip->num_streams; i++) 2530 chip->azx_dev[i].irq_pending = 0; 2531 spin_unlock_irq(&chip->reg_lock); 2532 } 2533 2534 #ifdef CONFIG_X86 2535 static int azx_pcm_mmap(struct snd_pcm_substream *substream, 2536 struct vm_area_struct *area) 2537 { 2538 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2539 struct azx *chip = apcm->chip; 2540 if (!azx_snoop(chip)) 2541 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); 2542 return snd_pcm_lib_default_mmap(substream, area); 2543 } 2544 #else 2545 #define azx_pcm_mmap NULL 2546 #endif 2547 2548 static struct snd_pcm_ops azx_pcm_ops = { 2549 .open = azx_pcm_open, 2550 .close = azx_pcm_close, 2551 .ioctl = snd_pcm_lib_ioctl, 2552 .hw_params = azx_pcm_hw_params, 2553 .hw_free = azx_pcm_hw_free, 2554 .prepare = azx_pcm_prepare, 2555 .trigger = azx_pcm_trigger, 2556 .pointer = azx_pcm_pointer, 2557 .wall_clock = azx_get_wallclock_tstamp, 2558 .mmap = azx_pcm_mmap, 2559 .page = snd_pcm_sgbuf_ops_page, 2560 }; 2561 2562 static void azx_pcm_free(struct snd_pcm *pcm) 2563 { 2564 struct azx_pcm *apcm = pcm->private_data; 2565 if (apcm) { 2566 list_del(&apcm->list); 2567 kfree(apcm); 2568 } 2569 } 2570 2571 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024) 2572 2573 static int 2574 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, 2575 struct hda_pcm *cpcm) 2576 { 2577 struct azx *chip = bus->private_data; 2578 struct snd_pcm *pcm; 2579 struct azx_pcm *apcm; 2580 int pcm_dev = cpcm->device; 2581 unsigned int size; 2582 int s, err; 2583 2584 list_for_each_entry(apcm, &chip->pcm_list, list) { 2585 if (apcm->pcm->device == pcm_dev) { 2586 snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n", 2587 pci_name(chip->pci), pcm_dev); 2588 return -EBUSY; 2589 } 2590 } 2591 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, 2592 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams, 2593 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams, 2594 &pcm); 2595 if (err < 0) 2596 return err; 2597 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name)); 2598 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL); 2599 if (apcm == NULL) 2600 return -ENOMEM; 2601 apcm->chip = chip; 2602 apcm->pcm = pcm; 2603 apcm->codec = codec; 2604 pcm->private_data = apcm; 2605 pcm->private_free = azx_pcm_free; 2606 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM) 2607 pcm->dev_class = SNDRV_PCM_CLASS_MODEM; 2608 list_add_tail(&apcm->list, &chip->pcm_list); 2609 cpcm->pcm = pcm; 2610 for (s = 0; s < 2; s++) { 2611 apcm->hinfo[s] = &cpcm->stream[s]; 2612 if (cpcm->stream[s].substreams) 2613 snd_pcm_set_ops(pcm, s, &azx_pcm_ops); 2614 } 2615 /* buffer pre-allocation */ 2616 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024; 2617 if (size > MAX_PREALLOC_SIZE) 2618 size = MAX_PREALLOC_SIZE; 2619 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG, 2620 snd_dma_pci_data(chip->pci), 2621 size, MAX_PREALLOC_SIZE); 2622 return 0; 2623 } 2624 2625 /* 2626 * mixer creation - all stuff is implemented in hda module 2627 */ 2628 static int azx_mixer_create(struct azx *chip) 2629 { 2630 return snd_hda_build_controls(chip->bus); 2631 } 2632 2633 2634 /* 2635 * initialize SD streams 2636 */ 2637 static int azx_init_stream(struct azx *chip) 2638 { 2639 int i; 2640 2641 /* initialize each stream (aka device) 2642 * assign the starting bdl address to each stream (device) 2643 * and initialize 2644 */ 2645 for (i = 0; i < chip->num_streams; i++) { 2646 struct azx_dev *azx_dev = &chip->azx_dev[i]; 2647 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8); 2648 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ 2649 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80); 2650 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ 2651 azx_dev->sd_int_sta_mask = 1 << i; 2652 /* stream tag: must be non-zero and unique */ 2653 azx_dev->index = i; 2654 azx_dev->stream_tag = i + 1; 2655 } 2656 2657 return 0; 2658 } 2659 2660 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 2661 { 2662 if (request_irq(chip->pci->irq, azx_interrupt, 2663 chip->msi ? 0 : IRQF_SHARED, 2664 KBUILD_MODNAME, chip)) { 2665 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, " 2666 "disabling device\n", chip->pci->irq); 2667 if (do_disconnect) 2668 snd_card_disconnect(chip->card); 2669 return -1; 2670 } 2671 chip->irq = chip->pci->irq; 2672 pci_intx(chip->pci, !chip->msi); 2673 return 0; 2674 } 2675 2676 2677 static void azx_stop_chip(struct azx *chip) 2678 { 2679 if (!chip->initialized) 2680 return; 2681 2682 /* disable interrupts */ 2683 azx_int_disable(chip); 2684 azx_int_clear(chip); 2685 2686 /* disable CORB/RIRB */ 2687 azx_free_cmd_io(chip); 2688 2689 /* disable position buffer */ 2690 azx_writel(chip, DPLBASE, 0); 2691 azx_writel(chip, DPUBASE, 0); 2692 2693 chip->initialized = 0; 2694 } 2695 2696 #ifdef CONFIG_SND_HDA_DSP_LOADER 2697 /* 2698 * DSP loading code (e.g. for CA0132) 2699 */ 2700 2701 /* use the first stream for loading DSP */ 2702 static struct azx_dev * 2703 azx_get_dsp_loader_dev(struct azx *chip) 2704 { 2705 return &chip->azx_dev[chip->playback_index_offset]; 2706 } 2707 2708 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format, 2709 unsigned int byte_size, 2710 struct snd_dma_buffer *bufp) 2711 { 2712 u32 *bdl; 2713 struct azx *chip = bus->private_data; 2714 struct azx_dev *azx_dev; 2715 int err; 2716 2717 azx_dev = azx_get_dsp_loader_dev(chip); 2718 2719 dsp_lock(azx_dev); 2720 spin_lock_irq(&chip->reg_lock); 2721 if (azx_dev->running || azx_dev->locked) { 2722 spin_unlock_irq(&chip->reg_lock); 2723 err = -EBUSY; 2724 goto unlock; 2725 } 2726 azx_dev->prepared = 0; 2727 chip->saved_azx_dev = *azx_dev; 2728 azx_dev->locked = 1; 2729 spin_unlock_irq(&chip->reg_lock); 2730 2731 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, 2732 snd_dma_pci_data(chip->pci), 2733 byte_size, bufp); 2734 if (err < 0) 2735 goto err_alloc; 2736 2737 mark_pages_wc(chip, bufp, true); 2738 azx_dev->bufsize = byte_size; 2739 azx_dev->period_bytes = byte_size; 2740 azx_dev->format_val = format; 2741 2742 azx_stream_reset(chip, azx_dev); 2743 2744 /* reset BDL address */ 2745 azx_sd_writel(azx_dev, SD_BDLPL, 0); 2746 azx_sd_writel(azx_dev, SD_BDLPU, 0); 2747 2748 azx_dev->frags = 0; 2749 bdl = (u32 *)azx_dev->bdl.area; 2750 err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0); 2751 if (err < 0) 2752 goto error; 2753 2754 azx_setup_controller(chip, azx_dev); 2755 dsp_unlock(azx_dev); 2756 return azx_dev->stream_tag; 2757 2758 error: 2759 mark_pages_wc(chip, bufp, false); 2760 snd_dma_free_pages(bufp); 2761 err_alloc: 2762 spin_lock_irq(&chip->reg_lock); 2763 if (azx_dev->opened) 2764 *azx_dev = chip->saved_azx_dev; 2765 azx_dev->locked = 0; 2766 spin_unlock_irq(&chip->reg_lock); 2767 unlock: 2768 dsp_unlock(azx_dev); 2769 return err; 2770 } 2771 2772 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start) 2773 { 2774 struct azx *chip = bus->private_data; 2775 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); 2776 2777 if (start) 2778 azx_stream_start(chip, azx_dev); 2779 else 2780 azx_stream_stop(chip, azx_dev); 2781 azx_dev->running = start; 2782 } 2783 2784 static void azx_load_dsp_cleanup(struct hda_bus *bus, 2785 struct snd_dma_buffer *dmab) 2786 { 2787 struct azx *chip = bus->private_data; 2788 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); 2789 2790 if (!dmab->area || !azx_dev->locked) 2791 return; 2792 2793 dsp_lock(azx_dev); 2794 /* reset BDL address */ 2795 azx_sd_writel(azx_dev, SD_BDLPL, 0); 2796 azx_sd_writel(azx_dev, SD_BDLPU, 0); 2797 azx_sd_writel(azx_dev, SD_CTL, 0); 2798 azx_dev->bufsize = 0; 2799 azx_dev->period_bytes = 0; 2800 azx_dev->format_val = 0; 2801 2802 mark_pages_wc(chip, dmab, false); 2803 snd_dma_free_pages(dmab); 2804 dmab->area = NULL; 2805 2806 spin_lock_irq(&chip->reg_lock); 2807 if (azx_dev->opened) 2808 *azx_dev = chip->saved_azx_dev; 2809 azx_dev->locked = 0; 2810 spin_unlock_irq(&chip->reg_lock); 2811 dsp_unlock(azx_dev); 2812 } 2813 #endif /* CONFIG_SND_HDA_DSP_LOADER */ 2814 2815 #ifdef CONFIG_PM 2816 /* power-up/down the controller */ 2817 static void azx_power_notify(struct hda_bus *bus, bool power_up) 2818 { 2819 struct azx *chip = bus->private_data; 2820 2821 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) 2822 return; 2823 2824 if (power_up) 2825 pm_runtime_get_sync(&chip->pci->dev); 2826 else 2827 pm_runtime_put_sync(&chip->pci->dev); 2828 } 2829 2830 static DEFINE_MUTEX(card_list_lock); 2831 static LIST_HEAD(card_list); 2832 2833 static void azx_add_card_list(struct azx *chip) 2834 { 2835 mutex_lock(&card_list_lock); 2836 list_add(&chip->list, &card_list); 2837 mutex_unlock(&card_list_lock); 2838 } 2839 2840 static void azx_del_card_list(struct azx *chip) 2841 { 2842 mutex_lock(&card_list_lock); 2843 list_del_init(&chip->list); 2844 mutex_unlock(&card_list_lock); 2845 } 2846 2847 /* trigger power-save check at writing parameter */ 2848 static int param_set_xint(const char *val, const struct kernel_param *kp) 2849 { 2850 struct azx *chip; 2851 struct hda_codec *c; 2852 int prev = power_save; 2853 int ret = param_set_int(val, kp); 2854 2855 if (ret || prev == power_save) 2856 return ret; 2857 2858 mutex_lock(&card_list_lock); 2859 list_for_each_entry(chip, &card_list, list) { 2860 if (!chip->bus || chip->disabled) 2861 continue; 2862 list_for_each_entry(c, &chip->bus->codec_list, list) 2863 snd_hda_power_sync(c); 2864 } 2865 mutex_unlock(&card_list_lock); 2866 return 0; 2867 } 2868 #else 2869 #define azx_add_card_list(chip) /* NOP */ 2870 #define azx_del_card_list(chip) /* NOP */ 2871 #endif /* CONFIG_PM */ 2872 2873 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO) 2874 /* 2875 * power management 2876 */ 2877 static int azx_suspend(struct device *dev) 2878 { 2879 struct pci_dev *pci = to_pci_dev(dev); 2880 struct snd_card *card = dev_get_drvdata(dev); 2881 struct azx *chip = card->private_data; 2882 struct azx_pcm *p; 2883 2884 if (chip->disabled) 2885 return 0; 2886 2887 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2888 azx_clear_irq_pending(chip); 2889 list_for_each_entry(p, &chip->pcm_list, list) 2890 snd_pcm_suspend_all(p->pcm); 2891 if (chip->initialized) 2892 snd_hda_suspend(chip->bus); 2893 azx_stop_chip(chip); 2894 if (chip->irq >= 0) { 2895 free_irq(chip->irq, chip); 2896 chip->irq = -1; 2897 } 2898 if (chip->msi) 2899 pci_disable_msi(chip->pci); 2900 pci_disable_device(pci); 2901 pci_save_state(pci); 2902 pci_set_power_state(pci, PCI_D3hot); 2903 return 0; 2904 } 2905 2906 static int azx_resume(struct device *dev) 2907 { 2908 struct pci_dev *pci = to_pci_dev(dev); 2909 struct snd_card *card = dev_get_drvdata(dev); 2910 struct azx *chip = card->private_data; 2911 2912 if (chip->disabled) 2913 return 0; 2914 2915 pci_set_power_state(pci, PCI_D0); 2916 pci_restore_state(pci); 2917 if (pci_enable_device(pci) < 0) { 2918 printk(KERN_ERR "hda-intel: pci_enable_device failed, " 2919 "disabling device\n"); 2920 snd_card_disconnect(card); 2921 return -EIO; 2922 } 2923 pci_set_master(pci); 2924 if (chip->msi) 2925 if (pci_enable_msi(pci) < 0) 2926 chip->msi = 0; 2927 if (azx_acquire_irq(chip, 1) < 0) 2928 return -EIO; 2929 azx_init_pci(chip); 2930 2931 azx_init_chip(chip, 1); 2932 2933 snd_hda_resume(chip->bus); 2934 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2935 return 0; 2936 } 2937 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */ 2938 2939 #ifdef CONFIG_PM_RUNTIME 2940 static int azx_runtime_suspend(struct device *dev) 2941 { 2942 struct snd_card *card = dev_get_drvdata(dev); 2943 struct azx *chip = card->private_data; 2944 2945 azx_stop_chip(chip); 2946 azx_clear_irq_pending(chip); 2947 return 0; 2948 } 2949 2950 static int azx_runtime_resume(struct device *dev) 2951 { 2952 struct snd_card *card = dev_get_drvdata(dev); 2953 struct azx *chip = card->private_data; 2954 2955 azx_init_pci(chip); 2956 azx_init_chip(chip, 1); 2957 return 0; 2958 } 2959 2960 static int azx_runtime_idle(struct device *dev) 2961 { 2962 struct snd_card *card = dev_get_drvdata(dev); 2963 struct azx *chip = card->private_data; 2964 2965 if (!power_save_controller || 2966 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) 2967 return -EBUSY; 2968 2969 return 0; 2970 } 2971 2972 #endif /* CONFIG_PM_RUNTIME */ 2973 2974 #ifdef CONFIG_PM 2975 static const struct dev_pm_ops azx_pm = { 2976 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 2977 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 2978 }; 2979 2980 #define AZX_PM_OPS &azx_pm 2981 #else 2982 #define AZX_PM_OPS NULL 2983 #endif /* CONFIG_PM */ 2984 2985 2986 /* 2987 * reboot notifier for hang-up problem at power-down 2988 */ 2989 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf) 2990 { 2991 struct azx *chip = container_of(nb, struct azx, reboot_notifier); 2992 snd_hda_bus_reboot_notify(chip->bus); 2993 azx_stop_chip(chip); 2994 return NOTIFY_OK; 2995 } 2996 2997 static void azx_notifier_register(struct azx *chip) 2998 { 2999 chip->reboot_notifier.notifier_call = azx_halt; 3000 register_reboot_notifier(&chip->reboot_notifier); 3001 } 3002 3003 static void azx_notifier_unregister(struct azx *chip) 3004 { 3005 if (chip->reboot_notifier.notifier_call) 3006 unregister_reboot_notifier(&chip->reboot_notifier); 3007 } 3008 3009 static int azx_first_init(struct azx *chip); 3010 static int azx_probe_continue(struct azx *chip); 3011 3012 #ifdef SUPPORT_VGA_SWITCHEROO 3013 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 3014 3015 static void azx_vs_set_state(struct pci_dev *pci, 3016 enum vga_switcheroo_state state) 3017 { 3018 struct snd_card *card = pci_get_drvdata(pci); 3019 struct azx *chip = card->private_data; 3020 bool disabled; 3021 3022 wait_for_completion(&chip->probe_wait); 3023 if (chip->init_failed) 3024 return; 3025 3026 disabled = (state == VGA_SWITCHEROO_OFF); 3027 if (chip->disabled == disabled) 3028 return; 3029 3030 if (!chip->bus) { 3031 chip->disabled = disabled; 3032 if (!disabled) { 3033 snd_printk(KERN_INFO SFX 3034 "%s: Start delayed initialization\n", 3035 pci_name(chip->pci)); 3036 if (azx_first_init(chip) < 0 || 3037 azx_probe_continue(chip) < 0) { 3038 snd_printk(KERN_ERR SFX 3039 "%s: initialization error\n", 3040 pci_name(chip->pci)); 3041 chip->init_failed = true; 3042 } 3043 } 3044 } else { 3045 snd_printk(KERN_INFO SFX 3046 "%s: %s via VGA-switcheroo\n", pci_name(chip->pci), 3047 disabled ? "Disabling" : "Enabling"); 3048 if (disabled) { 3049 azx_suspend(&pci->dev); 3050 chip->disabled = true; 3051 if (snd_hda_lock_devices(chip->bus)) 3052 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n", 3053 pci_name(chip->pci)); 3054 } else { 3055 snd_hda_unlock_devices(chip->bus); 3056 chip->disabled = false; 3057 azx_resume(&pci->dev); 3058 } 3059 } 3060 } 3061 3062 static bool azx_vs_can_switch(struct pci_dev *pci) 3063 { 3064 struct snd_card *card = pci_get_drvdata(pci); 3065 struct azx *chip = card->private_data; 3066 3067 wait_for_completion(&chip->probe_wait); 3068 if (chip->init_failed) 3069 return false; 3070 if (chip->disabled || !chip->bus) 3071 return true; 3072 if (snd_hda_lock_devices(chip->bus)) 3073 return false; 3074 snd_hda_unlock_devices(chip->bus); 3075 return true; 3076 } 3077 3078 static void init_vga_switcheroo(struct azx *chip) 3079 { 3080 struct pci_dev *p = get_bound_vga(chip->pci); 3081 if (p) { 3082 snd_printk(KERN_INFO SFX 3083 "%s: Handle VGA-switcheroo audio client\n", 3084 pci_name(chip->pci)); 3085 chip->use_vga_switcheroo = 1; 3086 pci_dev_put(p); 3087 } 3088 } 3089 3090 static const struct vga_switcheroo_client_ops azx_vs_ops = { 3091 .set_gpu_state = azx_vs_set_state, 3092 .can_switch = azx_vs_can_switch, 3093 }; 3094 3095 static int register_vga_switcheroo(struct azx *chip) 3096 { 3097 int err; 3098 3099 if (!chip->use_vga_switcheroo) 3100 return 0; 3101 /* FIXME: currently only handling DIS controller 3102 * is there any machine with two switchable HDMI audio controllers? 3103 */ 3104 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, 3105 VGA_SWITCHEROO_DIS, 3106 chip->bus != NULL); 3107 if (err < 0) 3108 return err; 3109 chip->vga_switcheroo_registered = 1; 3110 return 0; 3111 } 3112 #else 3113 #define init_vga_switcheroo(chip) /* NOP */ 3114 #define register_vga_switcheroo(chip) 0 3115 #define check_hdmi_disabled(pci) false 3116 #endif /* SUPPORT_VGA_SWITCHER */ 3117 3118 /* 3119 * destructor 3120 */ 3121 static int azx_free(struct azx *chip) 3122 { 3123 int i; 3124 3125 azx_del_card_list(chip); 3126 3127 azx_notifier_unregister(chip); 3128 3129 chip->init_failed = 1; /* to be sure */ 3130 complete_all(&chip->probe_wait); 3131 3132 if (use_vga_switcheroo(chip)) { 3133 if (chip->disabled && chip->bus) 3134 snd_hda_unlock_devices(chip->bus); 3135 if (chip->vga_switcheroo_registered) 3136 vga_switcheroo_unregister_client(chip->pci); 3137 } 3138 3139 if (chip->initialized) { 3140 azx_clear_irq_pending(chip); 3141 for (i = 0; i < chip->num_streams; i++) 3142 azx_stream_stop(chip, &chip->azx_dev[i]); 3143 azx_stop_chip(chip); 3144 } 3145 3146 if (chip->irq >= 0) 3147 free_irq(chip->irq, (void*)chip); 3148 if (chip->msi) 3149 pci_disable_msi(chip->pci); 3150 if (chip->remap_addr) 3151 iounmap(chip->remap_addr); 3152 3153 if (chip->azx_dev) { 3154 for (i = 0; i < chip->num_streams; i++) 3155 if (chip->azx_dev[i].bdl.area) { 3156 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false); 3157 snd_dma_free_pages(&chip->azx_dev[i].bdl); 3158 } 3159 } 3160 if (chip->rb.area) { 3161 mark_pages_wc(chip, &chip->rb, false); 3162 snd_dma_free_pages(&chip->rb); 3163 } 3164 if (chip->posbuf.area) { 3165 mark_pages_wc(chip, &chip->posbuf, false); 3166 snd_dma_free_pages(&chip->posbuf); 3167 } 3168 if (chip->region_requested) 3169 pci_release_regions(chip->pci); 3170 pci_disable_device(chip->pci); 3171 kfree(chip->azx_dev); 3172 #ifdef CONFIG_SND_HDA_PATCH_LOADER 3173 if (chip->fw) 3174 release_firmware(chip->fw); 3175 #endif 3176 kfree(chip); 3177 3178 return 0; 3179 } 3180 3181 static int azx_dev_free(struct snd_device *device) 3182 { 3183 return azx_free(device->device_data); 3184 } 3185 3186 #ifdef SUPPORT_VGA_SWITCHEROO 3187 /* 3188 * Check of disabled HDMI controller by vga-switcheroo 3189 */ 3190 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 3191 { 3192 struct pci_dev *p; 3193 3194 /* check only discrete GPU */ 3195 switch (pci->vendor) { 3196 case PCI_VENDOR_ID_ATI: 3197 case PCI_VENDOR_ID_AMD: 3198 case PCI_VENDOR_ID_NVIDIA: 3199 if (pci->devfn == 1) { 3200 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 3201 pci->bus->number, 0); 3202 if (p) { 3203 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA) 3204 return p; 3205 pci_dev_put(p); 3206 } 3207 } 3208 break; 3209 } 3210 return NULL; 3211 } 3212 3213 static bool check_hdmi_disabled(struct pci_dev *pci) 3214 { 3215 bool vga_inactive = false; 3216 struct pci_dev *p = get_bound_vga(pci); 3217 3218 if (p) { 3219 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 3220 vga_inactive = true; 3221 pci_dev_put(p); 3222 } 3223 return vga_inactive; 3224 } 3225 #endif /* SUPPORT_VGA_SWITCHEROO */ 3226 3227 /* 3228 * white/black-listing for position_fix 3229 */ 3230 static struct snd_pci_quirk position_fix_list[] = { 3231 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 3232 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 3233 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 3234 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 3235 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 3236 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 3237 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 3238 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 3239 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 3240 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 3241 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 3242 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 3243 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 3244 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 3245 {} 3246 }; 3247 3248 static int check_position_fix(struct azx *chip, int fix) 3249 { 3250 const struct snd_pci_quirk *q; 3251 3252 switch (fix) { 3253 case POS_FIX_AUTO: 3254 case POS_FIX_LPIB: 3255 case POS_FIX_POSBUF: 3256 case POS_FIX_VIACOMBO: 3257 case POS_FIX_COMBO: 3258 return fix; 3259 } 3260 3261 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 3262 if (q) { 3263 printk(KERN_INFO 3264 "hda_intel: position_fix set to %d " 3265 "for device %04x:%04x\n", 3266 q->value, q->subvendor, q->subdevice); 3267 return q->value; 3268 } 3269 3270 /* Check VIA/ATI HD Audio Controller exist */ 3271 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) { 3272 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci)); 3273 return POS_FIX_VIACOMBO; 3274 } 3275 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 3276 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci)); 3277 return POS_FIX_LPIB; 3278 } 3279 return POS_FIX_AUTO; 3280 } 3281 3282 /* 3283 * black-lists for probe_mask 3284 */ 3285 static struct snd_pci_quirk probe_mask_list[] = { 3286 /* Thinkpad often breaks the controller communication when accessing 3287 * to the non-working (or non-existing) modem codec slot. 3288 */ 3289 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 3290 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 3291 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 3292 /* broken BIOS */ 3293 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 3294 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 3295 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 3296 /* forced codec slots */ 3297 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 3298 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 3299 /* WinFast VP200 H (Teradici) user reported broken communication */ 3300 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 3301 {} 3302 }; 3303 3304 #define AZX_FORCE_CODEC_MASK 0x100 3305 3306 static void check_probe_mask(struct azx *chip, int dev) 3307 { 3308 const struct snd_pci_quirk *q; 3309 3310 chip->codec_probe_mask = probe_mask[dev]; 3311 if (chip->codec_probe_mask == -1) { 3312 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 3313 if (q) { 3314 printk(KERN_INFO 3315 "hda_intel: probe_mask set to 0x%x " 3316 "for device %04x:%04x\n", 3317 q->value, q->subvendor, q->subdevice); 3318 chip->codec_probe_mask = q->value; 3319 } 3320 } 3321 3322 /* check forced option */ 3323 if (chip->codec_probe_mask != -1 && 3324 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 3325 chip->codec_mask = chip->codec_probe_mask & 0xff; 3326 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n", 3327 chip->codec_mask); 3328 } 3329 } 3330 3331 /* 3332 * white/black-list for enable_msi 3333 */ 3334 static struct snd_pci_quirk msi_black_list[] = { 3335 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 3336 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 3337 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 3338 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 3339 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 3340 {} 3341 }; 3342 3343 static void check_msi(struct azx *chip) 3344 { 3345 const struct snd_pci_quirk *q; 3346 3347 if (enable_msi >= 0) { 3348 chip->msi = !!enable_msi; 3349 return; 3350 } 3351 chip->msi = 1; /* enable MSI as default */ 3352 q = snd_pci_quirk_lookup(chip->pci, msi_black_list); 3353 if (q) { 3354 printk(KERN_INFO 3355 "hda_intel: msi for device %04x:%04x set to %d\n", 3356 q->subvendor, q->subdevice, q->value); 3357 chip->msi = q->value; 3358 return; 3359 } 3360 3361 /* NVidia chipsets seem to cause troubles with MSI */ 3362 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 3363 printk(KERN_INFO "hda_intel: Disabling MSI\n"); 3364 chip->msi = 0; 3365 } 3366 } 3367 3368 /* check the snoop mode availability */ 3369 static void azx_check_snoop_available(struct azx *chip) 3370 { 3371 bool snoop = chip->snoop; 3372 3373 switch (chip->driver_type) { 3374 case AZX_DRIVER_VIA: 3375 /* force to non-snoop mode for a new VIA controller 3376 * when BIOS is set 3377 */ 3378 if (snoop) { 3379 u8 val; 3380 pci_read_config_byte(chip->pci, 0x42, &val); 3381 if (!(val & 0x80) && chip->pci->revision == 0x30) 3382 snoop = false; 3383 } 3384 break; 3385 case AZX_DRIVER_ATIHDMI_NS: 3386 /* new ATI HDMI requires non-snoop */ 3387 snoop = false; 3388 break; 3389 case AZX_DRIVER_CTHDA: 3390 snoop = false; 3391 break; 3392 } 3393 3394 if (snoop != chip->snoop) { 3395 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n", 3396 pci_name(chip->pci), snoop ? "snoop" : "non-snoop"); 3397 chip->snoop = snoop; 3398 } 3399 } 3400 3401 /* 3402 * constructor 3403 */ 3404 static int azx_create(struct snd_card *card, struct pci_dev *pci, 3405 int dev, unsigned int driver_caps, 3406 struct azx **rchip) 3407 { 3408 static struct snd_device_ops ops = { 3409 .dev_free = azx_dev_free, 3410 }; 3411 struct azx *chip; 3412 int err; 3413 3414 *rchip = NULL; 3415 3416 err = pci_enable_device(pci); 3417 if (err < 0) 3418 return err; 3419 3420 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 3421 if (!chip) { 3422 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci)); 3423 pci_disable_device(pci); 3424 return -ENOMEM; 3425 } 3426 3427 spin_lock_init(&chip->reg_lock); 3428 mutex_init(&chip->open_mutex); 3429 chip->card = card; 3430 chip->pci = pci; 3431 chip->irq = -1; 3432 chip->driver_caps = driver_caps; 3433 chip->driver_type = driver_caps & 0xff; 3434 check_msi(chip); 3435 chip->dev_index = dev; 3436 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work); 3437 INIT_LIST_HEAD(&chip->pcm_list); 3438 INIT_LIST_HEAD(&chip->list); 3439 init_vga_switcheroo(chip); 3440 init_completion(&chip->probe_wait); 3441 3442 chip->position_fix[0] = chip->position_fix[1] = 3443 check_position_fix(chip, position_fix[dev]); 3444 /* combo mode uses LPIB for playback */ 3445 if (chip->position_fix[0] == POS_FIX_COMBO) { 3446 chip->position_fix[0] = POS_FIX_LPIB; 3447 chip->position_fix[1] = POS_FIX_AUTO; 3448 } 3449 3450 check_probe_mask(chip, dev); 3451 3452 chip->single_cmd = single_cmd; 3453 chip->snoop = hda_snoop; 3454 azx_check_snoop_available(chip); 3455 3456 if (bdl_pos_adj[dev] < 0) { 3457 switch (chip->driver_type) { 3458 case AZX_DRIVER_ICH: 3459 case AZX_DRIVER_PCH: 3460 bdl_pos_adj[dev] = 1; 3461 break; 3462 default: 3463 bdl_pos_adj[dev] = 32; 3464 break; 3465 } 3466 } 3467 3468 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 3469 if (err < 0) { 3470 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n", 3471 pci_name(chip->pci)); 3472 azx_free(chip); 3473 return err; 3474 } 3475 3476 *rchip = chip; 3477 return 0; 3478 } 3479 3480 static int azx_first_init(struct azx *chip) 3481 { 3482 int dev = chip->dev_index; 3483 struct pci_dev *pci = chip->pci; 3484 struct snd_card *card = chip->card; 3485 int i, err; 3486 unsigned short gcap; 3487 3488 #if BITS_PER_LONG != 64 3489 /* Fix up base address on ULI M5461 */ 3490 if (chip->driver_type == AZX_DRIVER_ULI) { 3491 u16 tmp3; 3492 pci_read_config_word(pci, 0x40, &tmp3); 3493 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 3494 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 3495 } 3496 #endif 3497 3498 err = pci_request_regions(pci, "ICH HD audio"); 3499 if (err < 0) 3500 return err; 3501 chip->region_requested = 1; 3502 3503 chip->addr = pci_resource_start(pci, 0); 3504 chip->remap_addr = pci_ioremap_bar(pci, 0); 3505 if (chip->remap_addr == NULL) { 3506 snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci)); 3507 return -ENXIO; 3508 } 3509 3510 if (chip->msi) 3511 if (pci_enable_msi(pci) < 0) 3512 chip->msi = 0; 3513 3514 if (azx_acquire_irq(chip, 0) < 0) 3515 return -EBUSY; 3516 3517 pci_set_master(pci); 3518 synchronize_irq(chip->irq); 3519 3520 gcap = azx_readw(chip, GCAP); 3521 snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap); 3522 3523 /* disable SB600 64bit support for safety */ 3524 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 3525 struct pci_dev *p_smbus; 3526 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 3527 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 3528 NULL); 3529 if (p_smbus) { 3530 if (p_smbus->revision < 0x30) 3531 gcap &= ~ICH6_GCAP_64OK; 3532 pci_dev_put(p_smbus); 3533 } 3534 } 3535 3536 /* disable 64bit DMA address on some devices */ 3537 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 3538 snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci)); 3539 gcap &= ~ICH6_GCAP_64OK; 3540 } 3541 3542 /* disable buffer size rounding to 128-byte multiples if supported */ 3543 if (align_buffer_size >= 0) 3544 chip->align_buffer_size = !!align_buffer_size; 3545 else { 3546 if (chip->driver_caps & AZX_DCAPS_BUFSIZE) 3547 chip->align_buffer_size = 0; 3548 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE) 3549 chip->align_buffer_size = 1; 3550 else 3551 chip->align_buffer_size = 1; 3552 } 3553 3554 /* allow 64bit DMA address if supported by H/W */ 3555 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64))) 3556 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64)); 3557 else { 3558 pci_set_dma_mask(pci, DMA_BIT_MASK(32)); 3559 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32)); 3560 } 3561 3562 /* read number of streams from GCAP register instead of using 3563 * hardcoded value 3564 */ 3565 chip->capture_streams = (gcap >> 8) & 0x0f; 3566 chip->playback_streams = (gcap >> 12) & 0x0f; 3567 if (!chip->playback_streams && !chip->capture_streams) { 3568 /* gcap didn't give any info, switching to old method */ 3569 3570 switch (chip->driver_type) { 3571 case AZX_DRIVER_ULI: 3572 chip->playback_streams = ULI_NUM_PLAYBACK; 3573 chip->capture_streams = ULI_NUM_CAPTURE; 3574 break; 3575 case AZX_DRIVER_ATIHDMI: 3576 case AZX_DRIVER_ATIHDMI_NS: 3577 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 3578 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 3579 break; 3580 case AZX_DRIVER_GENERIC: 3581 default: 3582 chip->playback_streams = ICH6_NUM_PLAYBACK; 3583 chip->capture_streams = ICH6_NUM_CAPTURE; 3584 break; 3585 } 3586 } 3587 chip->capture_index_offset = 0; 3588 chip->playback_index_offset = chip->capture_streams; 3589 chip->num_streams = chip->playback_streams + chip->capture_streams; 3590 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), 3591 GFP_KERNEL); 3592 if (!chip->azx_dev) { 3593 snd_printk(KERN_ERR SFX "%s: cannot malloc azx_dev\n", pci_name(chip->pci)); 3594 return -ENOMEM; 3595 } 3596 3597 for (i = 0; i < chip->num_streams; i++) { 3598 dsp_lock_init(&chip->azx_dev[i]); 3599 /* allocate memory for the BDL for each stream */ 3600 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, 3601 snd_dma_pci_data(chip->pci), 3602 BDL_SIZE, &chip->azx_dev[i].bdl); 3603 if (err < 0) { 3604 snd_printk(KERN_ERR SFX "%s: cannot allocate BDL\n", pci_name(chip->pci)); 3605 return -ENOMEM; 3606 } 3607 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true); 3608 } 3609 /* allocate memory for the position buffer */ 3610 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, 3611 snd_dma_pci_data(chip->pci), 3612 chip->num_streams * 8, &chip->posbuf); 3613 if (err < 0) { 3614 snd_printk(KERN_ERR SFX "%s: cannot allocate posbuf\n", pci_name(chip->pci)); 3615 return -ENOMEM; 3616 } 3617 mark_pages_wc(chip, &chip->posbuf, true); 3618 /* allocate CORB/RIRB */ 3619 err = azx_alloc_cmd_io(chip); 3620 if (err < 0) 3621 return err; 3622 3623 /* initialize streams */ 3624 azx_init_stream(chip); 3625 3626 /* initialize chip */ 3627 azx_init_pci(chip); 3628 azx_init_chip(chip, (probe_only[dev] & 2) == 0); 3629 3630 /* codec detection */ 3631 if (!chip->codec_mask) { 3632 snd_printk(KERN_ERR SFX "%s: no codecs found!\n", pci_name(chip->pci)); 3633 return -ENODEV; 3634 } 3635 3636 strcpy(card->driver, "HDA-Intel"); 3637 strlcpy(card->shortname, driver_short_names[chip->driver_type], 3638 sizeof(card->shortname)); 3639 snprintf(card->longname, sizeof(card->longname), 3640 "%s at 0x%lx irq %i", 3641 card->shortname, chip->addr, chip->irq); 3642 3643 return 0; 3644 } 3645 3646 static void power_down_all_codecs(struct azx *chip) 3647 { 3648 #ifdef CONFIG_PM 3649 /* The codecs were powered up in snd_hda_codec_new(). 3650 * Now all initialization done, so turn them down if possible 3651 */ 3652 struct hda_codec *codec; 3653 list_for_each_entry(codec, &chip->bus->codec_list, list) { 3654 snd_hda_power_down(codec); 3655 } 3656 #endif 3657 } 3658 3659 #ifdef CONFIG_SND_HDA_PATCH_LOADER 3660 /* callback from request_firmware_nowait() */ 3661 static void azx_firmware_cb(const struct firmware *fw, void *context) 3662 { 3663 struct snd_card *card = context; 3664 struct azx *chip = card->private_data; 3665 struct pci_dev *pci = chip->pci; 3666 3667 if (!fw) { 3668 snd_printk(KERN_ERR SFX "%s: Cannot load firmware, aborting\n", 3669 pci_name(chip->pci)); 3670 goto error; 3671 } 3672 3673 chip->fw = fw; 3674 if (!chip->disabled) { 3675 /* continue probing */ 3676 if (azx_probe_continue(chip)) 3677 goto error; 3678 } 3679 return; /* OK */ 3680 3681 error: 3682 snd_card_free(card); 3683 pci_set_drvdata(pci, NULL); 3684 } 3685 #endif 3686 3687 static int azx_probe(struct pci_dev *pci, 3688 const struct pci_device_id *pci_id) 3689 { 3690 static int dev; 3691 struct snd_card *card; 3692 struct azx *chip; 3693 bool probe_now; 3694 int err; 3695 3696 if (dev >= SNDRV_CARDS) 3697 return -ENODEV; 3698 if (!enable[dev]) { 3699 dev++; 3700 return -ENOENT; 3701 } 3702 3703 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card); 3704 if (err < 0) { 3705 snd_printk(KERN_ERR "hda-intel: Error creating card!\n"); 3706 return err; 3707 } 3708 3709 snd_card_set_dev(card, &pci->dev); 3710 3711 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 3712 if (err < 0) 3713 goto out_free; 3714 card->private_data = chip; 3715 3716 pci_set_drvdata(pci, card); 3717 3718 err = register_vga_switcheroo(chip); 3719 if (err < 0) { 3720 snd_printk(KERN_ERR SFX 3721 "%s: Error registering VGA-switcheroo client\n", pci_name(pci)); 3722 goto out_free; 3723 } 3724 3725 if (check_hdmi_disabled(pci)) { 3726 snd_printk(KERN_INFO SFX "%s: VGA controller is disabled\n", 3727 pci_name(pci)); 3728 snd_printk(KERN_INFO SFX "%s: Delaying initialization\n", pci_name(pci)); 3729 chip->disabled = true; 3730 } 3731 3732 probe_now = !chip->disabled; 3733 if (probe_now) { 3734 err = azx_first_init(chip); 3735 if (err < 0) 3736 goto out_free; 3737 } 3738 3739 #ifdef CONFIG_SND_HDA_PATCH_LOADER 3740 if (patch[dev] && *patch[dev]) { 3741 snd_printk(KERN_ERR SFX "%s: Applying patch firmware '%s'\n", 3742 pci_name(pci), patch[dev]); 3743 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 3744 &pci->dev, GFP_KERNEL, card, 3745 azx_firmware_cb); 3746 if (err < 0) 3747 goto out_free; 3748 probe_now = false; /* continued in azx_firmware_cb() */ 3749 } 3750 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 3751 3752 if (probe_now) { 3753 err = azx_probe_continue(chip); 3754 if (err < 0) 3755 goto out_free; 3756 } 3757 3758 if (pci_dev_run_wake(pci)) 3759 pm_runtime_put_noidle(&pci->dev); 3760 3761 dev++; 3762 complete_all(&chip->probe_wait); 3763 return 0; 3764 3765 out_free: 3766 snd_card_free(card); 3767 return err; 3768 } 3769 3770 static int azx_probe_continue(struct azx *chip) 3771 { 3772 int dev = chip->dev_index; 3773 int err; 3774 3775 #ifdef CONFIG_SND_HDA_INPUT_BEEP 3776 chip->beep_mode = beep_mode[dev]; 3777 #endif 3778 3779 /* create codec instances */ 3780 err = azx_codec_create(chip, model[dev]); 3781 if (err < 0) 3782 goto out_free; 3783 #ifdef CONFIG_SND_HDA_PATCH_LOADER 3784 if (chip->fw) { 3785 err = snd_hda_load_patch(chip->bus, chip->fw->size, 3786 chip->fw->data); 3787 if (err < 0) 3788 goto out_free; 3789 #ifndef CONFIG_PM 3790 release_firmware(chip->fw); /* no longer needed */ 3791 chip->fw = NULL; 3792 #endif 3793 } 3794 #endif 3795 if ((probe_only[dev] & 1) == 0) { 3796 err = azx_codec_configure(chip); 3797 if (err < 0) 3798 goto out_free; 3799 } 3800 3801 /* create PCM streams */ 3802 err = snd_hda_build_pcms(chip->bus); 3803 if (err < 0) 3804 goto out_free; 3805 3806 /* create mixer controls */ 3807 err = azx_mixer_create(chip); 3808 if (err < 0) 3809 goto out_free; 3810 3811 err = snd_card_register(chip->card); 3812 if (err < 0) 3813 goto out_free; 3814 3815 chip->running = 1; 3816 power_down_all_codecs(chip); 3817 azx_notifier_register(chip); 3818 azx_add_card_list(chip); 3819 3820 return 0; 3821 3822 out_free: 3823 chip->init_failed = 1; 3824 return err; 3825 } 3826 3827 static void azx_remove(struct pci_dev *pci) 3828 { 3829 struct snd_card *card = pci_get_drvdata(pci); 3830 3831 if (pci_dev_run_wake(pci)) 3832 pm_runtime_get_noresume(&pci->dev); 3833 3834 if (card) 3835 snd_card_free(card); 3836 } 3837 3838 /* PCI IDs */ 3839 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = { 3840 /* CPT */ 3841 { PCI_DEVICE(0x8086, 0x1c20), 3842 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 3843 /* PBG */ 3844 { PCI_DEVICE(0x8086, 0x1d20), 3845 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 3846 /* Panther Point */ 3847 { PCI_DEVICE(0x8086, 0x1e20), 3848 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 3849 /* Lynx Point */ 3850 { PCI_DEVICE(0x8086, 0x8c20), 3851 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 3852 /* Wellsburg */ 3853 { PCI_DEVICE(0x8086, 0x8d20), 3854 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 3855 { PCI_DEVICE(0x8086, 0x8d21), 3856 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 3857 /* Lynx Point-LP */ 3858 { PCI_DEVICE(0x8086, 0x9c20), 3859 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 3860 /* Lynx Point-LP */ 3861 { PCI_DEVICE(0x8086, 0x9c21), 3862 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 3863 /* Haswell */ 3864 { PCI_DEVICE(0x8086, 0x0a0c), 3865 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH }, 3866 { PCI_DEVICE(0x8086, 0x0c0c), 3867 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH }, 3868 { PCI_DEVICE(0x8086, 0x0d0c), 3869 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH }, 3870 /* 5 Series/3400 */ 3871 { PCI_DEVICE(0x8086, 0x3b56), 3872 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 3873 /* Poulsbo */ 3874 { PCI_DEVICE(0x8086, 0x811b), 3875 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 3876 /* Oaktrail */ 3877 { PCI_DEVICE(0x8086, 0x080a), 3878 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 3879 /* BayTrail */ 3880 { PCI_DEVICE(0x8086, 0x0f04), 3881 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 3882 /* ICH */ 3883 { PCI_DEVICE(0x8086, 0x2668), 3884 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 3885 AZX_DCAPS_BUFSIZE }, /* ICH6 */ 3886 { PCI_DEVICE(0x8086, 0x27d8), 3887 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 3888 AZX_DCAPS_BUFSIZE }, /* ICH7 */ 3889 { PCI_DEVICE(0x8086, 0x269a), 3890 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 3891 AZX_DCAPS_BUFSIZE }, /* ESB2 */ 3892 { PCI_DEVICE(0x8086, 0x284b), 3893 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 3894 AZX_DCAPS_BUFSIZE }, /* ICH8 */ 3895 { PCI_DEVICE(0x8086, 0x293e), 3896 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 3897 AZX_DCAPS_BUFSIZE }, /* ICH9 */ 3898 { PCI_DEVICE(0x8086, 0x293f), 3899 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 3900 AZX_DCAPS_BUFSIZE }, /* ICH9 */ 3901 { PCI_DEVICE(0x8086, 0x3a3e), 3902 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 3903 AZX_DCAPS_BUFSIZE }, /* ICH10 */ 3904 { PCI_DEVICE(0x8086, 0x3a6e), 3905 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 3906 AZX_DCAPS_BUFSIZE }, /* ICH10 */ 3907 /* Generic Intel */ 3908 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 3909 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 3910 .class_mask = 0xffffff, 3911 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE }, 3912 /* ATI SB 450/600/700/800/900 */ 3913 { PCI_DEVICE(0x1002, 0x437b), 3914 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 3915 { PCI_DEVICE(0x1002, 0x4383), 3916 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 3917 /* AMD Hudson */ 3918 { PCI_DEVICE(0x1022, 0x780d), 3919 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 3920 /* ATI HDMI */ 3921 { PCI_DEVICE(0x1002, 0x793b), 3922 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 3923 { PCI_DEVICE(0x1002, 0x7919), 3924 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 3925 { PCI_DEVICE(0x1002, 0x960f), 3926 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 3927 { PCI_DEVICE(0x1002, 0x970f), 3928 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 3929 { PCI_DEVICE(0x1002, 0xaa00), 3930 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 3931 { PCI_DEVICE(0x1002, 0xaa08), 3932 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 3933 { PCI_DEVICE(0x1002, 0xaa10), 3934 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 3935 { PCI_DEVICE(0x1002, 0xaa18), 3936 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 3937 { PCI_DEVICE(0x1002, 0xaa20), 3938 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 3939 { PCI_DEVICE(0x1002, 0xaa28), 3940 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 3941 { PCI_DEVICE(0x1002, 0xaa30), 3942 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 3943 { PCI_DEVICE(0x1002, 0xaa38), 3944 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 3945 { PCI_DEVICE(0x1002, 0xaa40), 3946 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 3947 { PCI_DEVICE(0x1002, 0xaa48), 3948 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 3949 { PCI_DEVICE(0x1002, 0x9902), 3950 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, 3951 { PCI_DEVICE(0x1002, 0xaaa0), 3952 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, 3953 { PCI_DEVICE(0x1002, 0xaaa8), 3954 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, 3955 { PCI_DEVICE(0x1002, 0xaab0), 3956 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, 3957 /* VIA VT8251/VT8237A */ 3958 { PCI_DEVICE(0x1106, 0x3288), 3959 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA }, 3960 /* VIA GFX VT7122/VX900 */ 3961 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 3962 /* VIA GFX VT6122/VX11 */ 3963 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 3964 /* SIS966 */ 3965 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 3966 /* ULI M5461 */ 3967 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 3968 /* NVIDIA MCP */ 3969 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 3970 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 3971 .class_mask = 0xffffff, 3972 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 3973 /* Teradici */ 3974 { PCI_DEVICE(0x6549, 0x1200), 3975 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 3976 { PCI_DEVICE(0x6549, 0x2200), 3977 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 3978 /* Creative X-Fi (CA0110-IBG) */ 3979 /* CTHDA chips */ 3980 { PCI_DEVICE(0x1102, 0x0010), 3981 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 3982 { PCI_DEVICE(0x1102, 0x0012), 3983 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 3984 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE) 3985 /* the following entry conflicts with snd-ctxfi driver, 3986 * as ctxfi driver mutates from HD-audio to native mode with 3987 * a special command sequence. 3988 */ 3989 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 3990 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 3991 .class_mask = 0xffffff, 3992 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 3993 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, 3994 #else 3995 /* this entry seems still valid -- i.e. without emu20kx chip */ 3996 { PCI_DEVICE(0x1102, 0x0009), 3997 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 3998 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, 3999 #endif 4000 /* Vortex86MX */ 4001 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 4002 /* VMware HDAudio */ 4003 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 4004 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 4005 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 4006 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 4007 .class_mask = 0xffffff, 4008 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 4009 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 4010 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 4011 .class_mask = 0xffffff, 4012 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 4013 { 0, } 4014 }; 4015 MODULE_DEVICE_TABLE(pci, azx_ids); 4016 4017 /* pci_driver definition */ 4018 static struct pci_driver azx_driver = { 4019 .name = KBUILD_MODNAME, 4020 .id_table = azx_ids, 4021 .probe = azx_probe, 4022 .remove = azx_remove, 4023 .driver = { 4024 .pm = AZX_PM_OPS, 4025 }, 4026 }; 4027 4028 module_pci_driver(azx_driver); 4029