1 /* 2 * 3 * hda_intel.c - Implementation of primary alsa driver code base 4 * for Intel HD Audio. 5 * 6 * Copyright(c) 2004 Intel Corporation. All rights reserved. 7 * 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the Free 13 * Software Foundation; either version 2 of the License, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 * 21 * You should have received a copy of the GNU General Public License along with 22 * this program; if not, write to the Free Software Foundation, Inc., 59 23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 24 * 25 * CONTACTS: 26 * 27 * Matt Jared matt.jared@intel.com 28 * Andy Kopp andy.kopp@intel.com 29 * Dan Kogan dan.d.kogan@intel.com 30 * 31 * CHANGES: 32 * 33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 34 * 35 */ 36 37 #include <asm/io.h> 38 #include <linux/delay.h> 39 #include <linux/interrupt.h> 40 #include <linux/kernel.h> 41 #include <linux/module.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/moduleparam.h> 44 #include <linux/init.h> 45 #include <linux/slab.h> 46 #include <linux/pci.h> 47 #include <linux/mutex.h> 48 #include <sound/core.h> 49 #include <sound/initval.h> 50 #include "hda_codec.h" 51 52 53 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 54 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 55 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 56 static char *model[SNDRV_CARDS]; 57 static int position_fix[SNDRV_CARDS]; 58 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 59 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 60 static int single_cmd; 61 static int enable_msi; 62 63 module_param_array(index, int, NULL, 0444); 64 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 65 module_param_array(id, charp, NULL, 0444); 66 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 67 module_param_array(enable, bool, NULL, 0444); 68 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 69 module_param_array(model, charp, NULL, 0444); 70 MODULE_PARM_DESC(model, "Use the given board model."); 71 module_param_array(position_fix, int, NULL, 0444); 72 MODULE_PARM_DESC(position_fix, "Fix DMA pointer " 73 "(0 = auto, 1 = none, 2 = POSBUF)."); 74 module_param_array(bdl_pos_adj, int, NULL, 0644); 75 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 76 module_param_array(probe_mask, int, NULL, 0444); 77 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 78 module_param(single_cmd, bool, 0444); 79 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 80 "(for debugging only)."); 81 module_param(enable_msi, int, 0444); 82 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 83 84 #ifdef CONFIG_SND_HDA_POWER_SAVE 85 /* power_save option is defined in hda_codec.c */ 86 87 /* reset the HD-audio controller in power save mode. 88 * this may give more power-saving, but will take longer time to 89 * wake up. 90 */ 91 static int power_save_controller = 1; 92 module_param(power_save_controller, bool, 0644); 93 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 94 #endif 95 96 MODULE_LICENSE("GPL"); 97 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 98 "{Intel, ICH6M}," 99 "{Intel, ICH7}," 100 "{Intel, ESB2}," 101 "{Intel, ICH8}," 102 "{Intel, ICH9}," 103 "{Intel, ICH10}," 104 "{Intel, SCH}," 105 "{ATI, SB450}," 106 "{ATI, SB600}," 107 "{ATI, RS600}," 108 "{ATI, RS690}," 109 "{ATI, RS780}," 110 "{ATI, R600}," 111 "{ATI, RV630}," 112 "{ATI, RV610}," 113 "{ATI, RV670}," 114 "{ATI, RV635}," 115 "{ATI, RV620}," 116 "{ATI, RV770}," 117 "{VIA, VT8251}," 118 "{VIA, VT8237A}," 119 "{SiS, SIS966}," 120 "{ULI, M5461}}"); 121 MODULE_DESCRIPTION("Intel HDA driver"); 122 123 #define SFX "hda-intel: " 124 125 126 /* 127 * registers 128 */ 129 #define ICH6_REG_GCAP 0x00 130 #define ICH6_REG_VMIN 0x02 131 #define ICH6_REG_VMAJ 0x03 132 #define ICH6_REG_OUTPAY 0x04 133 #define ICH6_REG_INPAY 0x06 134 #define ICH6_REG_GCTL 0x08 135 #define ICH6_REG_WAKEEN 0x0c 136 #define ICH6_REG_STATESTS 0x0e 137 #define ICH6_REG_GSTS 0x10 138 #define ICH6_REG_INTCTL 0x20 139 #define ICH6_REG_INTSTS 0x24 140 #define ICH6_REG_WALCLK 0x30 141 #define ICH6_REG_SYNC 0x34 142 #define ICH6_REG_CORBLBASE 0x40 143 #define ICH6_REG_CORBUBASE 0x44 144 #define ICH6_REG_CORBWP 0x48 145 #define ICH6_REG_CORBRP 0x4A 146 #define ICH6_REG_CORBCTL 0x4c 147 #define ICH6_REG_CORBSTS 0x4d 148 #define ICH6_REG_CORBSIZE 0x4e 149 150 #define ICH6_REG_RIRBLBASE 0x50 151 #define ICH6_REG_RIRBUBASE 0x54 152 #define ICH6_REG_RIRBWP 0x58 153 #define ICH6_REG_RINTCNT 0x5a 154 #define ICH6_REG_RIRBCTL 0x5c 155 #define ICH6_REG_RIRBSTS 0x5d 156 #define ICH6_REG_RIRBSIZE 0x5e 157 158 #define ICH6_REG_IC 0x60 159 #define ICH6_REG_IR 0x64 160 #define ICH6_REG_IRS 0x68 161 #define ICH6_IRS_VALID (1<<1) 162 #define ICH6_IRS_BUSY (1<<0) 163 164 #define ICH6_REG_DPLBASE 0x70 165 #define ICH6_REG_DPUBASE 0x74 166 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */ 167 168 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ 169 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; 170 171 /* stream register offsets from stream base */ 172 #define ICH6_REG_SD_CTL 0x00 173 #define ICH6_REG_SD_STS 0x03 174 #define ICH6_REG_SD_LPIB 0x04 175 #define ICH6_REG_SD_CBL 0x08 176 #define ICH6_REG_SD_LVI 0x0c 177 #define ICH6_REG_SD_FIFOW 0x0e 178 #define ICH6_REG_SD_FIFOSIZE 0x10 179 #define ICH6_REG_SD_FORMAT 0x12 180 #define ICH6_REG_SD_BDLPL 0x18 181 #define ICH6_REG_SD_BDLPU 0x1c 182 183 /* PCI space */ 184 #define ICH6_PCIREG_TCSEL 0x44 185 186 /* 187 * other constants 188 */ 189 190 /* max number of SDs */ 191 /* ICH, ATI and VIA have 4 playback and 4 capture */ 192 #define ICH6_NUM_CAPTURE 4 193 #define ICH6_NUM_PLAYBACK 4 194 195 /* ULI has 6 playback and 5 capture */ 196 #define ULI_NUM_CAPTURE 5 197 #define ULI_NUM_PLAYBACK 6 198 199 /* ATI HDMI has 1 playback and 0 capture */ 200 #define ATIHDMI_NUM_CAPTURE 0 201 #define ATIHDMI_NUM_PLAYBACK 1 202 203 /* TERA has 4 playback and 3 capture */ 204 #define TERA_NUM_CAPTURE 3 205 #define TERA_NUM_PLAYBACK 4 206 207 /* this number is statically defined for simplicity */ 208 #define MAX_AZX_DEV 16 209 210 /* max number of fragments - we may use more if allocating more pages for BDL */ 211 #define BDL_SIZE 4096 212 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16) 213 #define AZX_MAX_FRAG 32 214 /* max buffer size - no h/w limit, you can increase as you like */ 215 #define AZX_MAX_BUF_SIZE (1024*1024*1024) 216 /* max number of PCM devics per card */ 217 #define AZX_MAX_PCMS 8 218 219 /* RIRB int mask: overrun[2], response[0] */ 220 #define RIRB_INT_RESPONSE 0x01 221 #define RIRB_INT_OVERRUN 0x04 222 #define RIRB_INT_MASK 0x05 223 224 /* STATESTS int mask: SD2,SD1,SD0 */ 225 #define AZX_MAX_CODECS 3 226 #define STATESTS_INT_MASK 0x07 227 228 /* SD_CTL bits */ 229 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ 230 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ 231 #define SD_CTL_STRIPE (3 << 16) /* stripe control */ 232 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */ 233 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */ 234 #define SD_CTL_STREAM_TAG_MASK (0xf << 20) 235 #define SD_CTL_STREAM_TAG_SHIFT 20 236 237 /* SD_CTL and SD_STS */ 238 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ 239 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ 240 #define SD_INT_COMPLETE 0x04 /* completion interrupt */ 241 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\ 242 SD_INT_COMPLETE) 243 244 /* SD_STS */ 245 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */ 246 247 /* INTCTL and INTSTS */ 248 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */ 249 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ 250 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ 251 252 /* GCTL unsolicited response enable bit */ 253 #define ICH6_GCTL_UREN (1<<8) 254 255 /* GCTL reset bit */ 256 #define ICH6_GCTL_RESET (1<<0) 257 258 /* CORB/RIRB control, read/write pointer */ 259 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */ 260 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */ 261 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */ 262 /* below are so far hardcoded - should read registers in future */ 263 #define ICH6_MAX_CORB_ENTRIES 256 264 #define ICH6_MAX_RIRB_ENTRIES 256 265 266 /* position fix mode */ 267 enum { 268 POS_FIX_AUTO, 269 POS_FIX_LPIB, 270 POS_FIX_POSBUF, 271 }; 272 273 /* Defines for ATI HD Audio support in SB450 south bridge */ 274 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 275 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 276 277 /* Defines for Nvidia HDA support */ 278 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 279 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 280 281 /* Defines for Intel SCH HDA snoop control */ 282 #define INTEL_SCH_HDA_DEVC 0x78 283 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 284 285 286 /* 287 */ 288 289 struct azx_dev { 290 struct snd_dma_buffer bdl; /* BDL buffer */ 291 u32 *posbuf; /* position buffer pointer */ 292 293 unsigned int bufsize; /* size of the play buffer in bytes */ 294 unsigned int period_bytes; /* size of the period in bytes */ 295 unsigned int frags; /* number for period in the play buffer */ 296 unsigned int fifo_size; /* FIFO size */ 297 298 void __iomem *sd_addr; /* stream descriptor pointer */ 299 300 u32 sd_int_sta_mask; /* stream int status mask */ 301 302 /* pcm support */ 303 struct snd_pcm_substream *substream; /* assigned substream, 304 * set in PCM open 305 */ 306 unsigned int format_val; /* format value to be set in the 307 * controller and the codec 308 */ 309 unsigned char stream_tag; /* assigned stream */ 310 unsigned char index; /* stream index */ 311 312 unsigned int opened :1; 313 unsigned int running :1; 314 unsigned int irq_pending :1; 315 unsigned int irq_ignore :1; 316 }; 317 318 /* CORB/RIRB */ 319 struct azx_rb { 320 u32 *buf; /* CORB/RIRB buffer 321 * Each CORB entry is 4byte, RIRB is 8byte 322 */ 323 dma_addr_t addr; /* physical address of CORB/RIRB buffer */ 324 /* for RIRB */ 325 unsigned short rp, wp; /* read/write pointers */ 326 int cmds; /* number of pending requests */ 327 u32 res; /* last read value */ 328 }; 329 330 struct azx { 331 struct snd_card *card; 332 struct pci_dev *pci; 333 int dev_index; 334 335 /* chip type specific */ 336 int driver_type; 337 int playback_streams; 338 int playback_index_offset; 339 int capture_streams; 340 int capture_index_offset; 341 int num_streams; 342 343 /* pci resources */ 344 unsigned long addr; 345 void __iomem *remap_addr; 346 int irq; 347 348 /* locks */ 349 spinlock_t reg_lock; 350 struct mutex open_mutex; 351 352 /* streams (x num_streams) */ 353 struct azx_dev *azx_dev; 354 355 /* PCM */ 356 struct snd_pcm *pcm[AZX_MAX_PCMS]; 357 358 /* HD codec */ 359 unsigned short codec_mask; 360 struct hda_bus *bus; 361 362 /* CORB/RIRB */ 363 struct azx_rb corb; 364 struct azx_rb rirb; 365 366 /* CORB/RIRB and position buffers */ 367 struct snd_dma_buffer rb; 368 struct snd_dma_buffer posbuf; 369 370 /* flags */ 371 int position_fix; 372 unsigned int running :1; 373 unsigned int initialized :1; 374 unsigned int single_cmd :1; 375 unsigned int polling_mode :1; 376 unsigned int msi :1; 377 unsigned int irq_pending_warned :1; 378 379 /* for debugging */ 380 unsigned int last_cmd; /* last issued command (to sync) */ 381 382 /* for pending irqs */ 383 struct work_struct irq_pending_work; 384 }; 385 386 /* driver types */ 387 enum { 388 AZX_DRIVER_ICH, 389 AZX_DRIVER_SCH, 390 AZX_DRIVER_ATI, 391 AZX_DRIVER_ATIHDMI, 392 AZX_DRIVER_VIA, 393 AZX_DRIVER_SIS, 394 AZX_DRIVER_ULI, 395 AZX_DRIVER_NVIDIA, 396 AZX_DRIVER_TERA, 397 }; 398 399 static char *driver_short_names[] __devinitdata = { 400 [AZX_DRIVER_ICH] = "HDA Intel", 401 [AZX_DRIVER_SCH] = "HDA Intel MID", 402 [AZX_DRIVER_ATI] = "HDA ATI SB", 403 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 404 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 405 [AZX_DRIVER_SIS] = "HDA SIS966", 406 [AZX_DRIVER_ULI] = "HDA ULI M5461", 407 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 408 [AZX_DRIVER_TERA] = "HDA Teradici", 409 }; 410 411 /* 412 * macros for easy use 413 */ 414 #define azx_writel(chip,reg,value) \ 415 writel(value, (chip)->remap_addr + ICH6_REG_##reg) 416 #define azx_readl(chip,reg) \ 417 readl((chip)->remap_addr + ICH6_REG_##reg) 418 #define azx_writew(chip,reg,value) \ 419 writew(value, (chip)->remap_addr + ICH6_REG_##reg) 420 #define azx_readw(chip,reg) \ 421 readw((chip)->remap_addr + ICH6_REG_##reg) 422 #define azx_writeb(chip,reg,value) \ 423 writeb(value, (chip)->remap_addr + ICH6_REG_##reg) 424 #define azx_readb(chip,reg) \ 425 readb((chip)->remap_addr + ICH6_REG_##reg) 426 427 #define azx_sd_writel(dev,reg,value) \ 428 writel(value, (dev)->sd_addr + ICH6_REG_##reg) 429 #define azx_sd_readl(dev,reg) \ 430 readl((dev)->sd_addr + ICH6_REG_##reg) 431 #define azx_sd_writew(dev,reg,value) \ 432 writew(value, (dev)->sd_addr + ICH6_REG_##reg) 433 #define azx_sd_readw(dev,reg) \ 434 readw((dev)->sd_addr + ICH6_REG_##reg) 435 #define azx_sd_writeb(dev,reg,value) \ 436 writeb(value, (dev)->sd_addr + ICH6_REG_##reg) 437 #define azx_sd_readb(dev,reg) \ 438 readb((dev)->sd_addr + ICH6_REG_##reg) 439 440 /* for pcm support */ 441 #define get_azx_dev(substream) (substream->runtime->private_data) 442 443 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 444 445 /* 446 * Interface for HD codec 447 */ 448 449 /* 450 * CORB / RIRB interface 451 */ 452 static int azx_alloc_cmd_io(struct azx *chip) 453 { 454 int err; 455 456 /* single page (at least 4096 bytes) must suffice for both ringbuffes */ 457 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, 458 snd_dma_pci_data(chip->pci), 459 PAGE_SIZE, &chip->rb); 460 if (err < 0) { 461 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n"); 462 return err; 463 } 464 return 0; 465 } 466 467 static void azx_init_cmd_io(struct azx *chip) 468 { 469 /* CORB set up */ 470 chip->corb.addr = chip->rb.addr; 471 chip->corb.buf = (u32 *)chip->rb.area; 472 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr); 473 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr)); 474 475 /* set the corb size to 256 entries (ULI requires explicitly) */ 476 azx_writeb(chip, CORBSIZE, 0x02); 477 /* set the corb write pointer to 0 */ 478 azx_writew(chip, CORBWP, 0); 479 /* reset the corb hw read pointer */ 480 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR); 481 /* enable corb dma */ 482 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN); 483 484 /* RIRB set up */ 485 chip->rirb.addr = chip->rb.addr + 2048; 486 chip->rirb.buf = (u32 *)(chip->rb.area + 2048); 487 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr); 488 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr)); 489 490 /* set the rirb size to 256 entries (ULI requires explicitly) */ 491 azx_writeb(chip, RIRBSIZE, 0x02); 492 /* reset the rirb hw write pointer */ 493 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR); 494 /* set N=1, get RIRB response interrupt for new entry */ 495 azx_writew(chip, RINTCNT, 1); 496 /* enable rirb dma and response irq */ 497 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN); 498 chip->rirb.rp = chip->rirb.cmds = 0; 499 } 500 501 static void azx_free_cmd_io(struct azx *chip) 502 { 503 /* disable ringbuffer DMAs */ 504 azx_writeb(chip, RIRBCTL, 0); 505 azx_writeb(chip, CORBCTL, 0); 506 } 507 508 /* send a command */ 509 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val) 510 { 511 struct azx *chip = codec->bus->private_data; 512 unsigned int wp; 513 514 /* add command to corb */ 515 wp = azx_readb(chip, CORBWP); 516 wp++; 517 wp %= ICH6_MAX_CORB_ENTRIES; 518 519 spin_lock_irq(&chip->reg_lock); 520 chip->rirb.cmds++; 521 chip->corb.buf[wp] = cpu_to_le32(val); 522 azx_writel(chip, CORBWP, wp); 523 spin_unlock_irq(&chip->reg_lock); 524 525 return 0; 526 } 527 528 #define ICH6_RIRB_EX_UNSOL_EV (1<<4) 529 530 /* retrieve RIRB entry - called from interrupt handler */ 531 static void azx_update_rirb(struct azx *chip) 532 { 533 unsigned int rp, wp; 534 u32 res, res_ex; 535 536 wp = azx_readb(chip, RIRBWP); 537 if (wp == chip->rirb.wp) 538 return; 539 chip->rirb.wp = wp; 540 541 while (chip->rirb.rp != wp) { 542 chip->rirb.rp++; 543 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES; 544 545 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */ 546 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]); 547 res = le32_to_cpu(chip->rirb.buf[rp]); 548 if (res_ex & ICH6_RIRB_EX_UNSOL_EV) 549 snd_hda_queue_unsol_event(chip->bus, res, res_ex); 550 else if (chip->rirb.cmds) { 551 chip->rirb.res = res; 552 smp_wmb(); 553 chip->rirb.cmds--; 554 } 555 } 556 } 557 558 /* receive a response */ 559 static unsigned int azx_rirb_get_response(struct hda_codec *codec) 560 { 561 struct azx *chip = codec->bus->private_data; 562 unsigned long timeout; 563 564 again: 565 timeout = jiffies + msecs_to_jiffies(1000); 566 for (;;) { 567 if (chip->polling_mode) { 568 spin_lock_irq(&chip->reg_lock); 569 azx_update_rirb(chip); 570 spin_unlock_irq(&chip->reg_lock); 571 } 572 if (!chip->rirb.cmds) { 573 smp_rmb(); 574 return chip->rirb.res; /* the last value */ 575 } 576 if (time_after(jiffies, timeout)) 577 break; 578 if (codec->bus->needs_damn_long_delay) 579 msleep(2); /* temporary workaround */ 580 else { 581 udelay(10); 582 cond_resched(); 583 } 584 } 585 586 if (chip->msi) { 587 snd_printk(KERN_WARNING "hda_intel: No response from codec, " 588 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd); 589 free_irq(chip->irq, chip); 590 chip->irq = -1; 591 pci_disable_msi(chip->pci); 592 chip->msi = 0; 593 if (azx_acquire_irq(chip, 1) < 0) 594 return -1; 595 goto again; 596 } 597 598 if (!chip->polling_mode) { 599 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, " 600 "switching to polling mode: last cmd=0x%08x\n", 601 chip->last_cmd); 602 chip->polling_mode = 1; 603 goto again; 604 } 605 606 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, " 607 "switching to single_cmd mode: last cmd=0x%08x\n", 608 chip->last_cmd); 609 chip->rirb.rp = azx_readb(chip, RIRBWP); 610 chip->rirb.cmds = 0; 611 /* switch to single_cmd mode */ 612 chip->single_cmd = 1; 613 azx_free_cmd_io(chip); 614 return -1; 615 } 616 617 /* 618 * Use the single immediate command instead of CORB/RIRB for simplicity 619 * 620 * Note: according to Intel, this is not preferred use. The command was 621 * intended for the BIOS only, and may get confused with unsolicited 622 * responses. So, we shouldn't use it for normal operation from the 623 * driver. 624 * I left the codes, however, for debugging/testing purposes. 625 */ 626 627 /* send a command */ 628 static int azx_single_send_cmd(struct hda_codec *codec, u32 val) 629 { 630 struct azx *chip = codec->bus->private_data; 631 int timeout = 50; 632 633 while (timeout--) { 634 /* check ICB busy bit */ 635 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) { 636 /* Clear IRV valid bit */ 637 azx_writew(chip, IRS, azx_readw(chip, IRS) | 638 ICH6_IRS_VALID); 639 azx_writel(chip, IC, val); 640 azx_writew(chip, IRS, azx_readw(chip, IRS) | 641 ICH6_IRS_BUSY); 642 return 0; 643 } 644 udelay(1); 645 } 646 if (printk_ratelimit()) 647 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", 648 azx_readw(chip, IRS), val); 649 return -EIO; 650 } 651 652 /* receive a response */ 653 static unsigned int azx_single_get_response(struct hda_codec *codec) 654 { 655 struct azx *chip = codec->bus->private_data; 656 int timeout = 50; 657 658 while (timeout--) { 659 /* check IRV busy bit */ 660 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) 661 return azx_readl(chip, IR); 662 udelay(1); 663 } 664 if (printk_ratelimit()) 665 snd_printd(SFX "get_response timeout: IRS=0x%x\n", 666 azx_readw(chip, IRS)); 667 return (unsigned int)-1; 668 } 669 670 /* 671 * The below are the main callbacks from hda_codec. 672 * 673 * They are just the skeleton to call sub-callbacks according to the 674 * current setting of chip->single_cmd. 675 */ 676 677 /* send a command */ 678 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, 679 int direct, unsigned int verb, 680 unsigned int para) 681 { 682 struct azx *chip = codec->bus->private_data; 683 u32 val; 684 685 val = (u32)(codec->addr & 0x0f) << 28; 686 val |= (u32)direct << 27; 687 val |= (u32)nid << 20; 688 val |= verb << 8; 689 val |= para; 690 chip->last_cmd = val; 691 692 if (chip->single_cmd) 693 return azx_single_send_cmd(codec, val); 694 else 695 return azx_corb_send_cmd(codec, val); 696 } 697 698 /* get a response */ 699 static unsigned int azx_get_response(struct hda_codec *codec) 700 { 701 struct azx *chip = codec->bus->private_data; 702 if (chip->single_cmd) 703 return azx_single_get_response(codec); 704 else 705 return azx_rirb_get_response(codec); 706 } 707 708 #ifdef CONFIG_SND_HDA_POWER_SAVE 709 static void azx_power_notify(struct hda_codec *codec); 710 #endif 711 712 /* reset codec link */ 713 static int azx_reset(struct azx *chip) 714 { 715 int count; 716 717 /* clear STATESTS */ 718 azx_writeb(chip, STATESTS, STATESTS_INT_MASK); 719 720 /* reset controller */ 721 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); 722 723 count = 50; 724 while (azx_readb(chip, GCTL) && --count) 725 msleep(1); 726 727 /* delay for >= 100us for codec PLL to settle per spec 728 * Rev 0.9 section 5.5.1 729 */ 730 msleep(1); 731 732 /* Bring controller out of reset */ 733 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET); 734 735 count = 50; 736 while (!azx_readb(chip, GCTL) && --count) 737 msleep(1); 738 739 /* Brent Chartrand said to wait >= 540us for codecs to initialize */ 740 msleep(1); 741 742 /* check to see if controller is ready */ 743 if (!azx_readb(chip, GCTL)) { 744 snd_printd("azx_reset: controller not ready!\n"); 745 return -EBUSY; 746 } 747 748 /* Accept unsolicited responses */ 749 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN); 750 751 /* detect codecs */ 752 if (!chip->codec_mask) { 753 chip->codec_mask = azx_readw(chip, STATESTS); 754 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask); 755 } 756 757 return 0; 758 } 759 760 761 /* 762 * Lowlevel interface 763 */ 764 765 /* enable interrupts */ 766 static void azx_int_enable(struct azx *chip) 767 { 768 /* enable controller CIE and GIE */ 769 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) | 770 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN); 771 } 772 773 /* disable interrupts */ 774 static void azx_int_disable(struct azx *chip) 775 { 776 int i; 777 778 /* disable interrupts in stream descriptor */ 779 for (i = 0; i < chip->num_streams; i++) { 780 struct azx_dev *azx_dev = &chip->azx_dev[i]; 781 azx_sd_writeb(azx_dev, SD_CTL, 782 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK); 783 } 784 785 /* disable SIE for all streams */ 786 azx_writeb(chip, INTCTL, 0); 787 788 /* disable controller CIE and GIE */ 789 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) & 790 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN)); 791 } 792 793 /* clear interrupts */ 794 static void azx_int_clear(struct azx *chip) 795 { 796 int i; 797 798 /* clear stream status */ 799 for (i = 0; i < chip->num_streams; i++) { 800 struct azx_dev *azx_dev = &chip->azx_dev[i]; 801 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); 802 } 803 804 /* clear STATESTS */ 805 azx_writeb(chip, STATESTS, STATESTS_INT_MASK); 806 807 /* clear rirb status */ 808 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); 809 810 /* clear int status */ 811 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM); 812 } 813 814 /* start a stream */ 815 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev) 816 { 817 /* enable SIE */ 818 azx_writeb(chip, INTCTL, 819 azx_readb(chip, INTCTL) | (1 << azx_dev->index)); 820 /* set DMA start and interrupt mask */ 821 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | 822 SD_CTL_DMA_START | SD_INT_MASK); 823 } 824 825 /* stop a stream */ 826 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev) 827 { 828 /* stop DMA */ 829 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & 830 ~(SD_CTL_DMA_START | SD_INT_MASK)); 831 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ 832 /* disable SIE */ 833 azx_writeb(chip, INTCTL, 834 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index)); 835 } 836 837 838 /* 839 * reset and start the controller registers 840 */ 841 static void azx_init_chip(struct azx *chip) 842 { 843 if (chip->initialized) 844 return; 845 846 /* reset controller */ 847 azx_reset(chip); 848 849 /* initialize interrupts */ 850 azx_int_clear(chip); 851 azx_int_enable(chip); 852 853 /* initialize the codec command I/O */ 854 if (!chip->single_cmd) 855 azx_init_cmd_io(chip); 856 857 /* program the position buffer */ 858 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr); 859 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr)); 860 861 chip->initialized = 1; 862 } 863 864 /* 865 * initialize the PCI registers 866 */ 867 /* update bits in a PCI register byte */ 868 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 869 unsigned char mask, unsigned char val) 870 { 871 unsigned char data; 872 873 pci_read_config_byte(pci, reg, &data); 874 data &= ~mask; 875 data |= (val & mask); 876 pci_write_config_byte(pci, reg, data); 877 } 878 879 static void azx_init_pci(struct azx *chip) 880 { 881 unsigned short snoop; 882 883 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 884 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 885 * Ensuring these bits are 0 clears playback static on some HD Audio 886 * codecs 887 */ 888 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0); 889 890 switch (chip->driver_type) { 891 case AZX_DRIVER_ATI: 892 /* For ATI SB450 azalia HD audio, we need to enable snoop */ 893 update_pci_byte(chip->pci, 894 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 895 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP); 896 break; 897 case AZX_DRIVER_NVIDIA: 898 /* For NVIDIA HDA, enable snoop */ 899 update_pci_byte(chip->pci, 900 NVIDIA_HDA_TRANSREG_ADDR, 901 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 902 break; 903 case AZX_DRIVER_SCH: 904 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 905 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) { 906 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \ 907 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP)); 908 pci_read_config_word(chip->pci, 909 INTEL_SCH_HDA_DEVC, &snoop); 910 snd_printdd("HDA snoop disabled, enabling ... %s\n",\ 911 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \ 912 ? "Failed" : "OK"); 913 } 914 break; 915 916 } 917 } 918 919 920 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 921 922 /* 923 * interrupt handler 924 */ 925 static irqreturn_t azx_interrupt(int irq, void *dev_id) 926 { 927 struct azx *chip = dev_id; 928 struct azx_dev *azx_dev; 929 u32 status; 930 int i; 931 932 spin_lock(&chip->reg_lock); 933 934 status = azx_readl(chip, INTSTS); 935 if (status == 0) { 936 spin_unlock(&chip->reg_lock); 937 return IRQ_NONE; 938 } 939 940 for (i = 0; i < chip->num_streams; i++) { 941 azx_dev = &chip->azx_dev[i]; 942 if (status & azx_dev->sd_int_sta_mask) { 943 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); 944 if (!azx_dev->substream || !azx_dev->running) 945 continue; 946 /* ignore the first dummy IRQ (due to pos_adj) */ 947 if (azx_dev->irq_ignore) { 948 azx_dev->irq_ignore = 0; 949 continue; 950 } 951 /* check whether this IRQ is really acceptable */ 952 if (azx_position_ok(chip, azx_dev)) { 953 azx_dev->irq_pending = 0; 954 spin_unlock(&chip->reg_lock); 955 snd_pcm_period_elapsed(azx_dev->substream); 956 spin_lock(&chip->reg_lock); 957 } else { 958 /* bogus IRQ, process it later */ 959 azx_dev->irq_pending = 1; 960 schedule_work(&chip->irq_pending_work); 961 } 962 } 963 } 964 965 /* clear rirb int */ 966 status = azx_readb(chip, RIRBSTS); 967 if (status & RIRB_INT_MASK) { 968 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE)) 969 azx_update_rirb(chip); 970 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); 971 } 972 973 #if 0 974 /* clear state status int */ 975 if (azx_readb(chip, STATESTS) & 0x04) 976 azx_writeb(chip, STATESTS, 0x04); 977 #endif 978 spin_unlock(&chip->reg_lock); 979 980 return IRQ_HANDLED; 981 } 982 983 984 /* 985 * set up a BDL entry 986 */ 987 static int setup_bdle(struct snd_pcm_substream *substream, 988 struct azx_dev *azx_dev, u32 **bdlp, 989 int ofs, int size, int with_ioc) 990 { 991 struct snd_sg_buf *sgbuf = snd_pcm_substream_sgbuf(substream); 992 u32 *bdl = *bdlp; 993 994 while (size > 0) { 995 dma_addr_t addr; 996 int chunk; 997 998 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES) 999 return -EINVAL; 1000 1001 addr = snd_pcm_sgbuf_get_addr(sgbuf, ofs); 1002 /* program the address field of the BDL entry */ 1003 bdl[0] = cpu_to_le32((u32)addr); 1004 bdl[1] = cpu_to_le32(upper_32_bits(addr)); 1005 /* program the size field of the BDL entry */ 1006 chunk = PAGE_SIZE - (ofs % PAGE_SIZE); 1007 if (size < chunk) 1008 chunk = size; 1009 bdl[2] = cpu_to_le32(chunk); 1010 /* program the IOC to enable interrupt 1011 * only when the whole fragment is processed 1012 */ 1013 size -= chunk; 1014 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01); 1015 bdl += 4; 1016 azx_dev->frags++; 1017 ofs += chunk; 1018 } 1019 *bdlp = bdl; 1020 return ofs; 1021 } 1022 1023 /* 1024 * set up BDL entries 1025 */ 1026 static int azx_setup_periods(struct azx *chip, 1027 struct snd_pcm_substream *substream, 1028 struct azx_dev *azx_dev) 1029 { 1030 u32 *bdl; 1031 int i, ofs, periods, period_bytes; 1032 int pos_adj; 1033 1034 /* reset BDL address */ 1035 azx_sd_writel(azx_dev, SD_BDLPL, 0); 1036 azx_sd_writel(azx_dev, SD_BDLPU, 0); 1037 1038 period_bytes = snd_pcm_lib_period_bytes(substream); 1039 azx_dev->period_bytes = period_bytes; 1040 periods = azx_dev->bufsize / period_bytes; 1041 1042 /* program the initial BDL entries */ 1043 bdl = (u32 *)azx_dev->bdl.area; 1044 ofs = 0; 1045 azx_dev->frags = 0; 1046 azx_dev->irq_ignore = 0; 1047 pos_adj = bdl_pos_adj[chip->dev_index]; 1048 if (pos_adj > 0) { 1049 struct snd_pcm_runtime *runtime = substream->runtime; 1050 int pos_align = pos_adj; 1051 pos_adj = (pos_adj * runtime->rate + 47999) / 48000; 1052 if (!pos_adj) 1053 pos_adj = pos_align; 1054 else 1055 pos_adj = ((pos_adj + pos_align - 1) / pos_align) * 1056 pos_align; 1057 pos_adj = frames_to_bytes(runtime, pos_adj); 1058 if (pos_adj >= period_bytes) { 1059 snd_printk(KERN_WARNING "Too big adjustment %d\n", 1060 bdl_pos_adj[chip->dev_index]); 1061 pos_adj = 0; 1062 } else { 1063 ofs = setup_bdle(substream, azx_dev, 1064 &bdl, ofs, pos_adj, 1); 1065 if (ofs < 0) 1066 goto error; 1067 azx_dev->irq_ignore = 1; 1068 } 1069 } else 1070 pos_adj = 0; 1071 for (i = 0; i < periods; i++) { 1072 if (i == periods - 1 && pos_adj) 1073 ofs = setup_bdle(substream, azx_dev, &bdl, ofs, 1074 period_bytes - pos_adj, 0); 1075 else 1076 ofs = setup_bdle(substream, azx_dev, &bdl, ofs, 1077 period_bytes, 1); 1078 if (ofs < 0) 1079 goto error; 1080 } 1081 return 0; 1082 1083 error: 1084 snd_printk(KERN_ERR "Too many BDL entries: buffer=%d, period=%d\n", 1085 azx_dev->bufsize, period_bytes); 1086 /* reset */ 1087 azx_sd_writel(azx_dev, SD_BDLPL, 0); 1088 azx_sd_writel(azx_dev, SD_BDLPU, 0); 1089 return -EINVAL; 1090 } 1091 1092 /* 1093 * set up the SD for streaming 1094 */ 1095 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev) 1096 { 1097 unsigned char val; 1098 int timeout; 1099 1100 /* make sure the run bit is zero for SD */ 1101 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & 1102 ~SD_CTL_DMA_START); 1103 /* reset stream */ 1104 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | 1105 SD_CTL_STREAM_RESET); 1106 udelay(3); 1107 timeout = 300; 1108 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && 1109 --timeout) 1110 ; 1111 val &= ~SD_CTL_STREAM_RESET; 1112 azx_sd_writeb(azx_dev, SD_CTL, val); 1113 udelay(3); 1114 1115 timeout = 300; 1116 /* waiting for hardware to report that the stream is out of reset */ 1117 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && 1118 --timeout) 1119 ; 1120 1121 /* program the stream_tag */ 1122 azx_sd_writel(azx_dev, SD_CTL, 1123 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)| 1124 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT)); 1125 1126 /* program the length of samples in cyclic buffer */ 1127 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize); 1128 1129 /* program the stream format */ 1130 /* this value needs to be the same as the one programmed */ 1131 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val); 1132 1133 /* program the stream LVI (last valid index) of the BDL */ 1134 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1); 1135 1136 /* program the BDL address */ 1137 /* lower BDL address */ 1138 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); 1139 /* upper BDL address */ 1140 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr)); 1141 1142 /* enable the position buffer */ 1143 if (chip->position_fix == POS_FIX_POSBUF || 1144 chip->position_fix == POS_FIX_AUTO) { 1145 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE)) 1146 azx_writel(chip, DPLBASE, 1147 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE); 1148 } 1149 1150 /* set the interrupt enable bits in the descriptor control register */ 1151 azx_sd_writel(azx_dev, SD_CTL, 1152 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK); 1153 1154 return 0; 1155 } 1156 1157 1158 /* 1159 * Codec initialization 1160 */ 1161 1162 static unsigned int azx_max_codecs[] __devinitdata = { 1163 [AZX_DRIVER_ICH] = 4, /* Some ICH9 boards use SD3 */ 1164 [AZX_DRIVER_SCH] = 3, 1165 [AZX_DRIVER_ATI] = 4, 1166 [AZX_DRIVER_ATIHDMI] = 4, 1167 [AZX_DRIVER_VIA] = 3, /* FIXME: correct? */ 1168 [AZX_DRIVER_SIS] = 3, /* FIXME: correct? */ 1169 [AZX_DRIVER_ULI] = 3, /* FIXME: correct? */ 1170 [AZX_DRIVER_NVIDIA] = 3, /* FIXME: correct? */ 1171 [AZX_DRIVER_TERA] = 1, 1172 }; 1173 1174 static int __devinit azx_codec_create(struct azx *chip, const char *model, 1175 unsigned int codec_probe_mask) 1176 { 1177 struct hda_bus_template bus_temp; 1178 int c, codecs, audio_codecs, err; 1179 1180 memset(&bus_temp, 0, sizeof(bus_temp)); 1181 bus_temp.private_data = chip; 1182 bus_temp.modelname = model; 1183 bus_temp.pci = chip->pci; 1184 bus_temp.ops.command = azx_send_cmd; 1185 bus_temp.ops.get_response = azx_get_response; 1186 #ifdef CONFIG_SND_HDA_POWER_SAVE 1187 bus_temp.ops.pm_notify = azx_power_notify; 1188 #endif 1189 1190 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus); 1191 if (err < 0) 1192 return err; 1193 1194 codecs = audio_codecs = 0; 1195 for (c = 0; c < AZX_MAX_CODECS; c++) { 1196 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) { 1197 struct hda_codec *codec; 1198 err = snd_hda_codec_new(chip->bus, c, &codec); 1199 if (err < 0) 1200 continue; 1201 codecs++; 1202 if (codec->afg) 1203 audio_codecs++; 1204 } 1205 } 1206 if (!audio_codecs) { 1207 /* probe additional slots if no codec is found */ 1208 for (; c < azx_max_codecs[chip->driver_type]; c++) { 1209 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) { 1210 err = snd_hda_codec_new(chip->bus, c, NULL); 1211 if (err < 0) 1212 continue; 1213 codecs++; 1214 } 1215 } 1216 } 1217 if (!codecs) { 1218 snd_printk(KERN_ERR SFX "no codecs initialized\n"); 1219 return -ENXIO; 1220 } 1221 1222 return 0; 1223 } 1224 1225 1226 /* 1227 * PCM support 1228 */ 1229 1230 /* assign a stream for the PCM */ 1231 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream) 1232 { 1233 int dev, i, nums; 1234 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1235 dev = chip->playback_index_offset; 1236 nums = chip->playback_streams; 1237 } else { 1238 dev = chip->capture_index_offset; 1239 nums = chip->capture_streams; 1240 } 1241 for (i = 0; i < nums; i++, dev++) 1242 if (!chip->azx_dev[dev].opened) { 1243 chip->azx_dev[dev].opened = 1; 1244 return &chip->azx_dev[dev]; 1245 } 1246 return NULL; 1247 } 1248 1249 /* release the assigned stream */ 1250 static inline void azx_release_device(struct azx_dev *azx_dev) 1251 { 1252 azx_dev->opened = 0; 1253 } 1254 1255 static struct snd_pcm_hardware azx_pcm_hw = { 1256 .info = (SNDRV_PCM_INFO_MMAP | 1257 SNDRV_PCM_INFO_INTERLEAVED | 1258 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1259 SNDRV_PCM_INFO_MMAP_VALID | 1260 /* No full-resume yet implemented */ 1261 /* SNDRV_PCM_INFO_RESUME |*/ 1262 SNDRV_PCM_INFO_PAUSE | 1263 SNDRV_PCM_INFO_SYNC_START), 1264 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1265 .rates = SNDRV_PCM_RATE_48000, 1266 .rate_min = 48000, 1267 .rate_max = 48000, 1268 .channels_min = 2, 1269 .channels_max = 2, 1270 .buffer_bytes_max = AZX_MAX_BUF_SIZE, 1271 .period_bytes_min = 128, 1272 .period_bytes_max = AZX_MAX_BUF_SIZE / 2, 1273 .periods_min = 2, 1274 .periods_max = AZX_MAX_FRAG, 1275 .fifo_size = 0, 1276 }; 1277 1278 struct azx_pcm { 1279 struct azx *chip; 1280 struct hda_codec *codec; 1281 struct hda_pcm_stream *hinfo[2]; 1282 }; 1283 1284 static int azx_pcm_open(struct snd_pcm_substream *substream) 1285 { 1286 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1287 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 1288 struct azx *chip = apcm->chip; 1289 struct azx_dev *azx_dev; 1290 struct snd_pcm_runtime *runtime = substream->runtime; 1291 unsigned long flags; 1292 int err; 1293 1294 mutex_lock(&chip->open_mutex); 1295 azx_dev = azx_assign_device(chip, substream->stream); 1296 if (azx_dev == NULL) { 1297 mutex_unlock(&chip->open_mutex); 1298 return -EBUSY; 1299 } 1300 runtime->hw = azx_pcm_hw; 1301 runtime->hw.channels_min = hinfo->channels_min; 1302 runtime->hw.channels_max = hinfo->channels_max; 1303 runtime->hw.formats = hinfo->formats; 1304 runtime->hw.rates = hinfo->rates; 1305 snd_pcm_limit_hw_rates(runtime); 1306 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); 1307 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 1308 128); 1309 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1310 128); 1311 snd_hda_power_up(apcm->codec); 1312 err = hinfo->ops.open(hinfo, apcm->codec, substream); 1313 if (err < 0) { 1314 azx_release_device(azx_dev); 1315 snd_hda_power_down(apcm->codec); 1316 mutex_unlock(&chip->open_mutex); 1317 return err; 1318 } 1319 spin_lock_irqsave(&chip->reg_lock, flags); 1320 azx_dev->substream = substream; 1321 azx_dev->running = 0; 1322 spin_unlock_irqrestore(&chip->reg_lock, flags); 1323 1324 runtime->private_data = azx_dev; 1325 snd_pcm_set_sync(substream); 1326 mutex_unlock(&chip->open_mutex); 1327 return 0; 1328 } 1329 1330 static int azx_pcm_close(struct snd_pcm_substream *substream) 1331 { 1332 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1333 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 1334 struct azx *chip = apcm->chip; 1335 struct azx_dev *azx_dev = get_azx_dev(substream); 1336 unsigned long flags; 1337 1338 mutex_lock(&chip->open_mutex); 1339 spin_lock_irqsave(&chip->reg_lock, flags); 1340 azx_dev->substream = NULL; 1341 azx_dev->running = 0; 1342 spin_unlock_irqrestore(&chip->reg_lock, flags); 1343 azx_release_device(azx_dev); 1344 hinfo->ops.close(hinfo, apcm->codec, substream); 1345 snd_hda_power_down(apcm->codec); 1346 mutex_unlock(&chip->open_mutex); 1347 return 0; 1348 } 1349 1350 static int azx_pcm_hw_params(struct snd_pcm_substream *substream, 1351 struct snd_pcm_hw_params *hw_params) 1352 { 1353 return snd_pcm_lib_malloc_pages(substream, 1354 params_buffer_bytes(hw_params)); 1355 } 1356 1357 static int azx_pcm_hw_free(struct snd_pcm_substream *substream) 1358 { 1359 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1360 struct azx_dev *azx_dev = get_azx_dev(substream); 1361 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 1362 1363 /* reset BDL address */ 1364 azx_sd_writel(azx_dev, SD_BDLPL, 0); 1365 azx_sd_writel(azx_dev, SD_BDLPU, 0); 1366 azx_sd_writel(azx_dev, SD_CTL, 0); 1367 1368 hinfo->ops.cleanup(hinfo, apcm->codec, substream); 1369 1370 return snd_pcm_lib_free_pages(substream); 1371 } 1372 1373 static int azx_pcm_prepare(struct snd_pcm_substream *substream) 1374 { 1375 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1376 struct azx *chip = apcm->chip; 1377 struct azx_dev *azx_dev = get_azx_dev(substream); 1378 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 1379 struct snd_pcm_runtime *runtime = substream->runtime; 1380 1381 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream); 1382 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate, 1383 runtime->channels, 1384 runtime->format, 1385 hinfo->maxbps); 1386 if (!azx_dev->format_val) { 1387 snd_printk(KERN_ERR SFX 1388 "invalid format_val, rate=%d, ch=%d, format=%d\n", 1389 runtime->rate, runtime->channels, runtime->format); 1390 return -EINVAL; 1391 } 1392 1393 snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n", 1394 azx_dev->bufsize, azx_dev->format_val); 1395 if (azx_setup_periods(chip, substream, azx_dev) < 0) 1396 return -EINVAL; 1397 azx_setup_controller(chip, azx_dev); 1398 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1399 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1; 1400 else 1401 azx_dev->fifo_size = 0; 1402 1403 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag, 1404 azx_dev->format_val, substream); 1405 } 1406 1407 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 1408 { 1409 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1410 struct azx *chip = apcm->chip; 1411 struct azx_dev *azx_dev; 1412 struct snd_pcm_substream *s; 1413 int start, nsync = 0, sbits = 0; 1414 int nwait, timeout; 1415 1416 switch (cmd) { 1417 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1418 case SNDRV_PCM_TRIGGER_RESUME: 1419 case SNDRV_PCM_TRIGGER_START: 1420 start = 1; 1421 break; 1422 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1423 case SNDRV_PCM_TRIGGER_SUSPEND: 1424 case SNDRV_PCM_TRIGGER_STOP: 1425 start = 0; 1426 break; 1427 default: 1428 return -EINVAL; 1429 } 1430 1431 snd_pcm_group_for_each_entry(s, substream) { 1432 if (s->pcm->card != substream->pcm->card) 1433 continue; 1434 azx_dev = get_azx_dev(s); 1435 sbits |= 1 << azx_dev->index; 1436 nsync++; 1437 snd_pcm_trigger_done(s, substream); 1438 } 1439 1440 spin_lock(&chip->reg_lock); 1441 if (nsync > 1) { 1442 /* first, set SYNC bits of corresponding streams */ 1443 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits); 1444 } 1445 snd_pcm_group_for_each_entry(s, substream) { 1446 if (s->pcm->card != substream->pcm->card) 1447 continue; 1448 azx_dev = get_azx_dev(s); 1449 if (start) 1450 azx_stream_start(chip, azx_dev); 1451 else 1452 azx_stream_stop(chip, azx_dev); 1453 azx_dev->running = start; 1454 } 1455 spin_unlock(&chip->reg_lock); 1456 if (start) { 1457 if (nsync == 1) 1458 return 0; 1459 /* wait until all FIFOs get ready */ 1460 for (timeout = 5000; timeout; timeout--) { 1461 nwait = 0; 1462 snd_pcm_group_for_each_entry(s, substream) { 1463 if (s->pcm->card != substream->pcm->card) 1464 continue; 1465 azx_dev = get_azx_dev(s); 1466 if (!(azx_sd_readb(azx_dev, SD_STS) & 1467 SD_STS_FIFO_READY)) 1468 nwait++; 1469 } 1470 if (!nwait) 1471 break; 1472 cpu_relax(); 1473 } 1474 } else { 1475 /* wait until all RUN bits are cleared */ 1476 for (timeout = 5000; timeout; timeout--) { 1477 nwait = 0; 1478 snd_pcm_group_for_each_entry(s, substream) { 1479 if (s->pcm->card != substream->pcm->card) 1480 continue; 1481 azx_dev = get_azx_dev(s); 1482 if (azx_sd_readb(azx_dev, SD_CTL) & 1483 SD_CTL_DMA_START) 1484 nwait++; 1485 } 1486 if (!nwait) 1487 break; 1488 cpu_relax(); 1489 } 1490 } 1491 if (nsync > 1) { 1492 spin_lock(&chip->reg_lock); 1493 /* reset SYNC bits */ 1494 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits); 1495 spin_unlock(&chip->reg_lock); 1496 } 1497 return 0; 1498 } 1499 1500 static unsigned int azx_get_position(struct azx *chip, 1501 struct azx_dev *azx_dev) 1502 { 1503 unsigned int pos; 1504 1505 if (chip->position_fix == POS_FIX_POSBUF || 1506 chip->position_fix == POS_FIX_AUTO) { 1507 /* use the position buffer */ 1508 pos = le32_to_cpu(*azx_dev->posbuf); 1509 } else { 1510 /* read LPIB */ 1511 pos = azx_sd_readl(azx_dev, SD_LPIB); 1512 } 1513 if (pos >= azx_dev->bufsize) 1514 pos = 0; 1515 return pos; 1516 } 1517 1518 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) 1519 { 1520 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1521 struct azx *chip = apcm->chip; 1522 struct azx_dev *azx_dev = get_azx_dev(substream); 1523 return bytes_to_frames(substream->runtime, 1524 azx_get_position(chip, azx_dev)); 1525 } 1526 1527 /* 1528 * Check whether the current DMA position is acceptable for updating 1529 * periods. Returns non-zero if it's OK. 1530 * 1531 * Many HD-audio controllers appear pretty inaccurate about 1532 * the update-IRQ timing. The IRQ is issued before actually the 1533 * data is processed. So, we need to process it afterwords in a 1534 * workqueue. 1535 */ 1536 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 1537 { 1538 unsigned int pos; 1539 1540 pos = azx_get_position(chip, azx_dev); 1541 if (chip->position_fix == POS_FIX_AUTO) { 1542 if (!pos) { 1543 printk(KERN_WARNING 1544 "hda-intel: Invalid position buffer, " 1545 "using LPIB read method instead.\n"); 1546 chip->position_fix = POS_FIX_LPIB; 1547 pos = azx_get_position(chip, azx_dev); 1548 } else 1549 chip->position_fix = POS_FIX_POSBUF; 1550 } 1551 1552 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2) 1553 return 0; /* NG - it's below the period boundary */ 1554 return 1; /* OK, it's fine */ 1555 } 1556 1557 /* 1558 * The work for pending PCM period updates. 1559 */ 1560 static void azx_irq_pending_work(struct work_struct *work) 1561 { 1562 struct azx *chip = container_of(work, struct azx, irq_pending_work); 1563 int i, pending; 1564 1565 if (!chip->irq_pending_warned) { 1566 printk(KERN_WARNING 1567 "hda-intel: IRQ timing workaround is activated " 1568 "for card #%d. Suggest a bigger bdl_pos_adj.\n", 1569 chip->card->number); 1570 chip->irq_pending_warned = 1; 1571 } 1572 1573 for (;;) { 1574 pending = 0; 1575 spin_lock_irq(&chip->reg_lock); 1576 for (i = 0; i < chip->num_streams; i++) { 1577 struct azx_dev *azx_dev = &chip->azx_dev[i]; 1578 if (!azx_dev->irq_pending || 1579 !azx_dev->substream || 1580 !azx_dev->running) 1581 continue; 1582 if (azx_position_ok(chip, azx_dev)) { 1583 azx_dev->irq_pending = 0; 1584 spin_unlock(&chip->reg_lock); 1585 snd_pcm_period_elapsed(azx_dev->substream); 1586 spin_lock(&chip->reg_lock); 1587 } else 1588 pending++; 1589 } 1590 spin_unlock_irq(&chip->reg_lock); 1591 if (!pending) 1592 return; 1593 cond_resched(); 1594 } 1595 } 1596 1597 /* clear irq_pending flags and assure no on-going workq */ 1598 static void azx_clear_irq_pending(struct azx *chip) 1599 { 1600 int i; 1601 1602 spin_lock_irq(&chip->reg_lock); 1603 for (i = 0; i < chip->num_streams; i++) 1604 chip->azx_dev[i].irq_pending = 0; 1605 spin_unlock_irq(&chip->reg_lock); 1606 flush_scheduled_work(); 1607 } 1608 1609 static struct snd_pcm_ops azx_pcm_ops = { 1610 .open = azx_pcm_open, 1611 .close = azx_pcm_close, 1612 .ioctl = snd_pcm_lib_ioctl, 1613 .hw_params = azx_pcm_hw_params, 1614 .hw_free = azx_pcm_hw_free, 1615 .prepare = azx_pcm_prepare, 1616 .trigger = azx_pcm_trigger, 1617 .pointer = azx_pcm_pointer, 1618 .page = snd_pcm_sgbuf_ops_page, 1619 }; 1620 1621 static void azx_pcm_free(struct snd_pcm *pcm) 1622 { 1623 kfree(pcm->private_data); 1624 } 1625 1626 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec, 1627 struct hda_pcm *cpcm) 1628 { 1629 int err; 1630 struct snd_pcm *pcm; 1631 struct azx_pcm *apcm; 1632 1633 /* if no substreams are defined for both playback and capture, 1634 * it's just a placeholder. ignore it. 1635 */ 1636 if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams) 1637 return 0; 1638 1639 snd_assert(cpcm->name, return -EINVAL); 1640 1641 err = snd_pcm_new(chip->card, cpcm->name, cpcm->device, 1642 cpcm->stream[0].substreams, 1643 cpcm->stream[1].substreams, 1644 &pcm); 1645 if (err < 0) 1646 return err; 1647 strcpy(pcm->name, cpcm->name); 1648 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL); 1649 if (apcm == NULL) 1650 return -ENOMEM; 1651 apcm->chip = chip; 1652 apcm->codec = codec; 1653 apcm->hinfo[0] = &cpcm->stream[0]; 1654 apcm->hinfo[1] = &cpcm->stream[1]; 1655 pcm->private_data = apcm; 1656 pcm->private_free = azx_pcm_free; 1657 if (cpcm->stream[0].substreams) 1658 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops); 1659 if (cpcm->stream[1].substreams) 1660 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops); 1661 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG, 1662 snd_dma_pci_data(chip->pci), 1663 1024 * 64, 1024 * 1024); 1664 chip->pcm[cpcm->device] = pcm; 1665 return 0; 1666 } 1667 1668 static int __devinit azx_pcm_create(struct azx *chip) 1669 { 1670 static const char *dev_name[HDA_PCM_NTYPES] = { 1671 "Audio", "SPDIF", "HDMI", "Modem" 1672 }; 1673 /* starting device index for each PCM type */ 1674 static int dev_idx[HDA_PCM_NTYPES] = { 1675 [HDA_PCM_TYPE_AUDIO] = 0, 1676 [HDA_PCM_TYPE_SPDIF] = 1, 1677 [HDA_PCM_TYPE_HDMI] = 3, 1678 [HDA_PCM_TYPE_MODEM] = 6 1679 }; 1680 /* normal audio device indices; not linear to keep compatibility */ 1681 static int audio_idx[4] = { 0, 2, 4, 5 }; 1682 struct hda_codec *codec; 1683 int c, err; 1684 int num_devs[HDA_PCM_NTYPES]; 1685 1686 err = snd_hda_build_pcms(chip->bus); 1687 if (err < 0) 1688 return err; 1689 1690 /* create audio PCMs */ 1691 memset(num_devs, 0, sizeof(num_devs)); 1692 list_for_each_entry(codec, &chip->bus->codec_list, list) { 1693 for (c = 0; c < codec->num_pcms; c++) { 1694 struct hda_pcm *cpcm = &codec->pcm_info[c]; 1695 int type = cpcm->pcm_type; 1696 switch (type) { 1697 case HDA_PCM_TYPE_AUDIO: 1698 if (num_devs[type] >= ARRAY_SIZE(audio_idx)) { 1699 snd_printk(KERN_WARNING 1700 "Too many audio devices\n"); 1701 continue; 1702 } 1703 cpcm->device = audio_idx[num_devs[type]]; 1704 break; 1705 case HDA_PCM_TYPE_SPDIF: 1706 case HDA_PCM_TYPE_HDMI: 1707 case HDA_PCM_TYPE_MODEM: 1708 if (num_devs[type]) { 1709 snd_printk(KERN_WARNING 1710 "%s already defined\n", 1711 dev_name[type]); 1712 continue; 1713 } 1714 cpcm->device = dev_idx[type]; 1715 break; 1716 default: 1717 snd_printk(KERN_WARNING 1718 "Invalid PCM type %d\n", type); 1719 continue; 1720 } 1721 num_devs[type]++; 1722 err = create_codec_pcm(chip, codec, cpcm); 1723 if (err < 0) 1724 return err; 1725 } 1726 } 1727 return 0; 1728 } 1729 1730 /* 1731 * mixer creation - all stuff is implemented in hda module 1732 */ 1733 static int __devinit azx_mixer_create(struct azx *chip) 1734 { 1735 return snd_hda_build_controls(chip->bus); 1736 } 1737 1738 1739 /* 1740 * initialize SD streams 1741 */ 1742 static int __devinit azx_init_stream(struct azx *chip) 1743 { 1744 int i; 1745 1746 /* initialize each stream (aka device) 1747 * assign the starting bdl address to each stream (device) 1748 * and initialize 1749 */ 1750 for (i = 0; i < chip->num_streams; i++) { 1751 struct azx_dev *azx_dev = &chip->azx_dev[i]; 1752 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8); 1753 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ 1754 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80); 1755 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ 1756 azx_dev->sd_int_sta_mask = 1 << i; 1757 /* stream tag: must be non-zero and unique */ 1758 azx_dev->index = i; 1759 azx_dev->stream_tag = i + 1; 1760 } 1761 1762 return 0; 1763 } 1764 1765 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 1766 { 1767 if (request_irq(chip->pci->irq, azx_interrupt, 1768 chip->msi ? 0 : IRQF_SHARED, 1769 "HDA Intel", chip)) { 1770 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, " 1771 "disabling device\n", chip->pci->irq); 1772 if (do_disconnect) 1773 snd_card_disconnect(chip->card); 1774 return -1; 1775 } 1776 chip->irq = chip->pci->irq; 1777 pci_intx(chip->pci, !chip->msi); 1778 return 0; 1779 } 1780 1781 1782 static void azx_stop_chip(struct azx *chip) 1783 { 1784 if (!chip->initialized) 1785 return; 1786 1787 /* disable interrupts */ 1788 azx_int_disable(chip); 1789 azx_int_clear(chip); 1790 1791 /* disable CORB/RIRB */ 1792 azx_free_cmd_io(chip); 1793 1794 /* disable position buffer */ 1795 azx_writel(chip, DPLBASE, 0); 1796 azx_writel(chip, DPUBASE, 0); 1797 1798 chip->initialized = 0; 1799 } 1800 1801 #ifdef CONFIG_SND_HDA_POWER_SAVE 1802 /* power-up/down the controller */ 1803 static void azx_power_notify(struct hda_codec *codec) 1804 { 1805 struct azx *chip = codec->bus->private_data; 1806 struct hda_codec *c; 1807 int power_on = 0; 1808 1809 list_for_each_entry(c, &codec->bus->codec_list, list) { 1810 if (c->power_on) { 1811 power_on = 1; 1812 break; 1813 } 1814 } 1815 if (power_on) 1816 azx_init_chip(chip); 1817 else if (chip->running && power_save_controller) 1818 azx_stop_chip(chip); 1819 } 1820 #endif /* CONFIG_SND_HDA_POWER_SAVE */ 1821 1822 #ifdef CONFIG_PM 1823 /* 1824 * power management 1825 */ 1826 static int azx_suspend(struct pci_dev *pci, pm_message_t state) 1827 { 1828 struct snd_card *card = pci_get_drvdata(pci); 1829 struct azx *chip = card->private_data; 1830 int i; 1831 1832 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1833 azx_clear_irq_pending(chip); 1834 for (i = 0; i < AZX_MAX_PCMS; i++) 1835 snd_pcm_suspend_all(chip->pcm[i]); 1836 if (chip->initialized) 1837 snd_hda_suspend(chip->bus, state); 1838 azx_stop_chip(chip); 1839 if (chip->irq >= 0) { 1840 free_irq(chip->irq, chip); 1841 chip->irq = -1; 1842 } 1843 if (chip->msi) 1844 pci_disable_msi(chip->pci); 1845 pci_disable_device(pci); 1846 pci_save_state(pci); 1847 pci_set_power_state(pci, pci_choose_state(pci, state)); 1848 return 0; 1849 } 1850 1851 static int azx_resume(struct pci_dev *pci) 1852 { 1853 struct snd_card *card = pci_get_drvdata(pci); 1854 struct azx *chip = card->private_data; 1855 1856 pci_set_power_state(pci, PCI_D0); 1857 pci_restore_state(pci); 1858 if (pci_enable_device(pci) < 0) { 1859 printk(KERN_ERR "hda-intel: pci_enable_device failed, " 1860 "disabling device\n"); 1861 snd_card_disconnect(card); 1862 return -EIO; 1863 } 1864 pci_set_master(pci); 1865 if (chip->msi) 1866 if (pci_enable_msi(pci) < 0) 1867 chip->msi = 0; 1868 if (azx_acquire_irq(chip, 1) < 0) 1869 return -EIO; 1870 azx_init_pci(chip); 1871 1872 if (snd_hda_codecs_inuse(chip->bus)) 1873 azx_init_chip(chip); 1874 1875 snd_hda_resume(chip->bus); 1876 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1877 return 0; 1878 } 1879 #endif /* CONFIG_PM */ 1880 1881 1882 /* 1883 * destructor 1884 */ 1885 static int azx_free(struct azx *chip) 1886 { 1887 int i; 1888 1889 if (chip->initialized) { 1890 azx_clear_irq_pending(chip); 1891 for (i = 0; i < chip->num_streams; i++) 1892 azx_stream_stop(chip, &chip->azx_dev[i]); 1893 azx_stop_chip(chip); 1894 } 1895 1896 if (chip->irq >= 0) 1897 free_irq(chip->irq, (void*)chip); 1898 if (chip->msi) 1899 pci_disable_msi(chip->pci); 1900 if (chip->remap_addr) 1901 iounmap(chip->remap_addr); 1902 1903 if (chip->azx_dev) { 1904 for (i = 0; i < chip->num_streams; i++) 1905 if (chip->azx_dev[i].bdl.area) 1906 snd_dma_free_pages(&chip->azx_dev[i].bdl); 1907 } 1908 if (chip->rb.area) 1909 snd_dma_free_pages(&chip->rb); 1910 if (chip->posbuf.area) 1911 snd_dma_free_pages(&chip->posbuf); 1912 pci_release_regions(chip->pci); 1913 pci_disable_device(chip->pci); 1914 kfree(chip->azx_dev); 1915 kfree(chip); 1916 1917 return 0; 1918 } 1919 1920 static int azx_dev_free(struct snd_device *device) 1921 { 1922 return azx_free(device->device_data); 1923 } 1924 1925 /* 1926 * white/black-listing for position_fix 1927 */ 1928 static struct snd_pci_quirk position_fix_list[] __devinitdata = { 1929 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1930 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1931 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1932 {} 1933 }; 1934 1935 static int __devinit check_position_fix(struct azx *chip, int fix) 1936 { 1937 const struct snd_pci_quirk *q; 1938 1939 if (fix == POS_FIX_AUTO) { 1940 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1941 if (q) { 1942 printk(KERN_INFO 1943 "hda_intel: position_fix set to %d " 1944 "for device %04x:%04x\n", 1945 q->value, q->subvendor, q->subdevice); 1946 return q->value; 1947 } 1948 } 1949 return fix; 1950 } 1951 1952 /* 1953 * black-lists for probe_mask 1954 */ 1955 static struct snd_pci_quirk probe_mask_list[] __devinitdata = { 1956 /* Thinkpad often breaks the controller communication when accessing 1957 * to the non-working (or non-existing) modem codec slot. 1958 */ 1959 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1960 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1961 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1962 {} 1963 }; 1964 1965 static void __devinit check_probe_mask(struct azx *chip, int dev) 1966 { 1967 const struct snd_pci_quirk *q; 1968 1969 if (probe_mask[dev] == -1) { 1970 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1971 if (q) { 1972 printk(KERN_INFO 1973 "hda_intel: probe_mask set to 0x%x " 1974 "for device %04x:%04x\n", 1975 q->value, q->subvendor, q->subdevice); 1976 probe_mask[dev] = q->value; 1977 } 1978 } 1979 } 1980 1981 1982 /* 1983 * constructor 1984 */ 1985 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci, 1986 int dev, int driver_type, 1987 struct azx **rchip) 1988 { 1989 struct azx *chip; 1990 int i, err; 1991 unsigned short gcap; 1992 static struct snd_device_ops ops = { 1993 .dev_free = azx_dev_free, 1994 }; 1995 1996 *rchip = NULL; 1997 1998 err = pci_enable_device(pci); 1999 if (err < 0) 2000 return err; 2001 2002 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 2003 if (!chip) { 2004 snd_printk(KERN_ERR SFX "cannot allocate chip\n"); 2005 pci_disable_device(pci); 2006 return -ENOMEM; 2007 } 2008 2009 spin_lock_init(&chip->reg_lock); 2010 mutex_init(&chip->open_mutex); 2011 chip->card = card; 2012 chip->pci = pci; 2013 chip->irq = -1; 2014 chip->driver_type = driver_type; 2015 chip->msi = enable_msi; 2016 chip->dev_index = dev; 2017 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work); 2018 2019 chip->position_fix = check_position_fix(chip, position_fix[dev]); 2020 check_probe_mask(chip, dev); 2021 2022 chip->single_cmd = single_cmd; 2023 2024 if (bdl_pos_adj[dev] < 0) { 2025 switch (chip->driver_type) { 2026 case AZX_DRIVER_ICH: 2027 bdl_pos_adj[dev] = 1; 2028 break; 2029 default: 2030 bdl_pos_adj[dev] = 32; 2031 break; 2032 } 2033 } 2034 2035 #if BITS_PER_LONG != 64 2036 /* Fix up base address on ULI M5461 */ 2037 if (chip->driver_type == AZX_DRIVER_ULI) { 2038 u16 tmp3; 2039 pci_read_config_word(pci, 0x40, &tmp3); 2040 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 2041 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 2042 } 2043 #endif 2044 2045 err = pci_request_regions(pci, "ICH HD audio"); 2046 if (err < 0) { 2047 kfree(chip); 2048 pci_disable_device(pci); 2049 return err; 2050 } 2051 2052 chip->addr = pci_resource_start(pci, 0); 2053 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0)); 2054 if (chip->remap_addr == NULL) { 2055 snd_printk(KERN_ERR SFX "ioremap error\n"); 2056 err = -ENXIO; 2057 goto errout; 2058 } 2059 2060 if (chip->msi) 2061 if (pci_enable_msi(pci) < 0) 2062 chip->msi = 0; 2063 2064 if (azx_acquire_irq(chip, 0) < 0) { 2065 err = -EBUSY; 2066 goto errout; 2067 } 2068 2069 pci_set_master(pci); 2070 synchronize_irq(chip->irq); 2071 2072 gcap = azx_readw(chip, GCAP); 2073 snd_printdd("chipset global capabilities = 0x%x\n", gcap); 2074 2075 /* allow 64bit DMA address if supported by H/W */ 2076 if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK)) 2077 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK); 2078 2079 /* read number of streams from GCAP register instead of using 2080 * hardcoded value 2081 */ 2082 chip->capture_streams = (gcap >> 8) & 0x0f; 2083 chip->playback_streams = (gcap >> 12) & 0x0f; 2084 if (!chip->playback_streams && !chip->capture_streams) { 2085 /* gcap didn't give any info, switching to old method */ 2086 2087 switch (chip->driver_type) { 2088 case AZX_DRIVER_ULI: 2089 chip->playback_streams = ULI_NUM_PLAYBACK; 2090 chip->capture_streams = ULI_NUM_CAPTURE; 2091 break; 2092 case AZX_DRIVER_ATIHDMI: 2093 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 2094 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 2095 break; 2096 default: 2097 chip->playback_streams = ICH6_NUM_PLAYBACK; 2098 chip->capture_streams = ICH6_NUM_CAPTURE; 2099 break; 2100 } 2101 } 2102 chip->capture_index_offset = 0; 2103 chip->playback_index_offset = chip->capture_streams; 2104 chip->num_streams = chip->playback_streams + chip->capture_streams; 2105 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), 2106 GFP_KERNEL); 2107 if (!chip->azx_dev) { 2108 snd_printk(KERN_ERR "cannot malloc azx_dev\n"); 2109 goto errout; 2110 } 2111 2112 for (i = 0; i < chip->num_streams; i++) { 2113 /* allocate memory for the BDL for each stream */ 2114 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, 2115 snd_dma_pci_data(chip->pci), 2116 BDL_SIZE, &chip->azx_dev[i].bdl); 2117 if (err < 0) { 2118 snd_printk(KERN_ERR SFX "cannot allocate BDL\n"); 2119 goto errout; 2120 } 2121 } 2122 /* allocate memory for the position buffer */ 2123 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, 2124 snd_dma_pci_data(chip->pci), 2125 chip->num_streams * 8, &chip->posbuf); 2126 if (err < 0) { 2127 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n"); 2128 goto errout; 2129 } 2130 /* allocate CORB/RIRB */ 2131 if (!chip->single_cmd) { 2132 err = azx_alloc_cmd_io(chip); 2133 if (err < 0) 2134 goto errout; 2135 } 2136 2137 /* initialize streams */ 2138 azx_init_stream(chip); 2139 2140 /* initialize chip */ 2141 azx_init_pci(chip); 2142 azx_init_chip(chip); 2143 2144 /* codec detection */ 2145 if (!chip->codec_mask) { 2146 snd_printk(KERN_ERR SFX "no codecs found!\n"); 2147 err = -ENODEV; 2148 goto errout; 2149 } 2150 2151 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 2152 if (err <0) { 2153 snd_printk(KERN_ERR SFX "Error creating device [card]!\n"); 2154 goto errout; 2155 } 2156 2157 strcpy(card->driver, "HDA-Intel"); 2158 strcpy(card->shortname, driver_short_names[chip->driver_type]); 2159 sprintf(card->longname, "%s at 0x%lx irq %i", 2160 card->shortname, chip->addr, chip->irq); 2161 2162 *rchip = chip; 2163 return 0; 2164 2165 errout: 2166 azx_free(chip); 2167 return err; 2168 } 2169 2170 static void power_down_all_codecs(struct azx *chip) 2171 { 2172 #ifdef CONFIG_SND_HDA_POWER_SAVE 2173 /* The codecs were powered up in snd_hda_codec_new(). 2174 * Now all initialization done, so turn them down if possible 2175 */ 2176 struct hda_codec *codec; 2177 list_for_each_entry(codec, &chip->bus->codec_list, list) { 2178 snd_hda_power_down(codec); 2179 } 2180 #endif 2181 } 2182 2183 static int __devinit azx_probe(struct pci_dev *pci, 2184 const struct pci_device_id *pci_id) 2185 { 2186 static int dev; 2187 struct snd_card *card; 2188 struct azx *chip; 2189 int err; 2190 2191 if (dev >= SNDRV_CARDS) 2192 return -ENODEV; 2193 if (!enable[dev]) { 2194 dev++; 2195 return -ENOENT; 2196 } 2197 2198 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); 2199 if (!card) { 2200 snd_printk(KERN_ERR SFX "Error creating card!\n"); 2201 return -ENOMEM; 2202 } 2203 2204 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2205 if (err < 0) { 2206 snd_card_free(card); 2207 return err; 2208 } 2209 card->private_data = chip; 2210 2211 /* create codec instances */ 2212 err = azx_codec_create(chip, model[dev], probe_mask[dev]); 2213 if (err < 0) { 2214 snd_card_free(card); 2215 return err; 2216 } 2217 2218 /* create PCM streams */ 2219 err = azx_pcm_create(chip); 2220 if (err < 0) { 2221 snd_card_free(card); 2222 return err; 2223 } 2224 2225 /* create mixer controls */ 2226 err = azx_mixer_create(chip); 2227 if (err < 0) { 2228 snd_card_free(card); 2229 return err; 2230 } 2231 2232 snd_card_set_dev(card, &pci->dev); 2233 2234 err = snd_card_register(card); 2235 if (err < 0) { 2236 snd_card_free(card); 2237 return err; 2238 } 2239 2240 pci_set_drvdata(pci, card); 2241 chip->running = 1; 2242 power_down_all_codecs(chip); 2243 2244 dev++; 2245 return err; 2246 } 2247 2248 static void __devexit azx_remove(struct pci_dev *pci) 2249 { 2250 snd_card_free(pci_get_drvdata(pci)); 2251 pci_set_drvdata(pci, NULL); 2252 } 2253 2254 /* PCI IDs */ 2255 static struct pci_device_id azx_ids[] = { 2256 /* ICH 6..10 */ 2257 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH }, 2258 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH }, 2259 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH }, 2260 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH }, 2261 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH }, 2262 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH }, 2263 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH }, 2264 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH }, 2265 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH }, 2266 /* SCH */ 2267 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH }, 2268 /* ATI SB 450/600 */ 2269 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI }, 2270 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI }, 2271 /* ATI HDMI */ 2272 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI }, 2273 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI }, 2274 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI }, 2275 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI }, 2276 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI }, 2277 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI }, 2278 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI }, 2279 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI }, 2280 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI }, 2281 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI }, 2282 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI }, 2283 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI }, 2284 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI }, 2285 /* VIA VT8251/VT8237A */ 2286 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2287 /* SIS966 */ 2288 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2289 /* ULI M5461 */ 2290 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2291 /* NVIDIA MCP */ 2292 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA }, 2293 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA }, 2294 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA }, 2295 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA }, 2296 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA }, 2297 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA }, 2298 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA }, 2299 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA }, 2300 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA }, 2301 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA }, 2302 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA }, 2303 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA }, 2304 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA }, 2305 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA }, 2306 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA }, 2307 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA }, 2308 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA }, 2309 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA }, 2310 { PCI_DEVICE(0x10de, 0x0bd4), .driver_data = AZX_DRIVER_NVIDIA }, 2311 { PCI_DEVICE(0x10de, 0x0bd5), .driver_data = AZX_DRIVER_NVIDIA }, 2312 { PCI_DEVICE(0x10de, 0x0bd6), .driver_data = AZX_DRIVER_NVIDIA }, 2313 { PCI_DEVICE(0x10de, 0x0bd7), .driver_data = AZX_DRIVER_NVIDIA }, 2314 /* Teradici */ 2315 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA }, 2316 { 0, } 2317 }; 2318 MODULE_DEVICE_TABLE(pci, azx_ids); 2319 2320 /* pci_driver definition */ 2321 static struct pci_driver driver = { 2322 .name = "HDA Intel", 2323 .id_table = azx_ids, 2324 .probe = azx_probe, 2325 .remove = __devexit_p(azx_remove), 2326 #ifdef CONFIG_PM 2327 .suspend = azx_suspend, 2328 .resume = azx_resume, 2329 #endif 2330 }; 2331 2332 static int __init alsa_card_azx_init(void) 2333 { 2334 return pci_register_driver(&driver); 2335 } 2336 2337 static void __exit alsa_card_azx_exit(void) 2338 { 2339 pci_unregister_driver(&driver); 2340 } 2341 2342 module_init(alsa_card_azx_init) 2343 module_exit(alsa_card_azx_exit) 2344