1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * hda_intel.c - Implementation of primary alsa driver code base 5 * for Intel HD Audio. 6 * 7 * Copyright(c) 2004 Intel Corporation. All rights reserved. 8 * 9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 10 * PeiSen Hou <pshou@realtek.com.tw> 11 * 12 * CONTACTS: 13 * 14 * Matt Jared matt.jared@intel.com 15 * Andy Kopp andy.kopp@intel.com 16 * Dan Kogan dan.d.kogan@intel.com 17 * 18 * CHANGES: 19 * 20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/moduleparam.h> 29 #include <linux/init.h> 30 #include <linux/slab.h> 31 #include <linux/pci.h> 32 #include <linux/mutex.h> 33 #include <linux/io.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/clocksource.h> 36 #include <linux/time.h> 37 #include <linux/completion.h> 38 39 #ifdef CONFIG_X86 40 /* for snoop control */ 41 #include <asm/pgtable.h> 42 #include <asm/set_memory.h> 43 #include <asm/cpufeature.h> 44 #endif 45 #include <sound/core.h> 46 #include <sound/initval.h> 47 #include <sound/hdaudio.h> 48 #include <sound/hda_i915.h> 49 #include <linux/vgaarb.h> 50 #include <linux/vga_switcheroo.h> 51 #include <linux/firmware.h> 52 #include <sound/hda_codec.h> 53 #include "hda_controller.h" 54 #include "hda_intel.h" 55 56 #define CREATE_TRACE_POINTS 57 #include "hda_intel_trace.h" 58 59 /* position fix mode */ 60 enum { 61 POS_FIX_AUTO, 62 POS_FIX_LPIB, 63 POS_FIX_POSBUF, 64 POS_FIX_VIACOMBO, 65 POS_FIX_COMBO, 66 POS_FIX_SKL, 67 }; 68 69 /* Defines for ATI HD Audio support in SB450 south bridge */ 70 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 71 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 72 73 /* Defines for Nvidia HDA support */ 74 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 75 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 76 #define NVIDIA_HDA_ISTRM_COH 0x4d 77 #define NVIDIA_HDA_OSTRM_COH 0x4c 78 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 79 80 /* Defines for Intel SCH HDA snoop control */ 81 #define INTEL_HDA_CGCTL 0x48 82 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) 83 #define INTEL_SCH_HDA_DEVC 0x78 84 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 85 86 /* Define IN stream 0 FIFO size offset in VIA controller */ 87 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 88 /* Define VIA HD Audio Device ID*/ 89 #define VIA_HDAC_DEVICE_ID 0x3288 90 91 /* max number of SDs */ 92 /* ICH, ATI and VIA have 4 playback and 4 capture */ 93 #define ICH6_NUM_CAPTURE 4 94 #define ICH6_NUM_PLAYBACK 4 95 96 /* ULI has 6 playback and 5 capture */ 97 #define ULI_NUM_CAPTURE 5 98 #define ULI_NUM_PLAYBACK 6 99 100 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 101 #define ATIHDMI_NUM_CAPTURE 0 102 #define ATIHDMI_NUM_PLAYBACK 8 103 104 /* TERA has 4 playback and 3 capture */ 105 #define TERA_NUM_CAPTURE 3 106 #define TERA_NUM_PLAYBACK 4 107 108 109 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 110 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 111 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 112 static char *model[SNDRV_CARDS]; 113 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 114 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 115 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 116 static int probe_only[SNDRV_CARDS]; 117 static int jackpoll_ms[SNDRV_CARDS]; 118 static int single_cmd = -1; 119 static int enable_msi = -1; 120 #ifdef CONFIG_SND_HDA_PATCH_LOADER 121 static char *patch[SNDRV_CARDS]; 122 #endif 123 #ifdef CONFIG_SND_HDA_INPUT_BEEP 124 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 125 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 126 #endif 127 128 module_param_array(index, int, NULL, 0444); 129 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 130 module_param_array(id, charp, NULL, 0444); 131 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 132 module_param_array(enable, bool, NULL, 0444); 133 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 134 module_param_array(model, charp, NULL, 0444); 135 MODULE_PARM_DESC(model, "Use the given board model."); 136 module_param_array(position_fix, int, NULL, 0444); 137 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 138 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+)."); 139 module_param_array(bdl_pos_adj, int, NULL, 0644); 140 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 141 module_param_array(probe_mask, int, NULL, 0444); 142 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 143 module_param_array(probe_only, int, NULL, 0444); 144 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 145 module_param_array(jackpoll_ms, int, NULL, 0444); 146 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 147 module_param(single_cmd, bint, 0444); 148 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 149 "(for debugging only)."); 150 module_param(enable_msi, bint, 0444); 151 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 152 #ifdef CONFIG_SND_HDA_PATCH_LOADER 153 module_param_array(patch, charp, NULL, 0444); 154 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 155 #endif 156 #ifdef CONFIG_SND_HDA_INPUT_BEEP 157 module_param_array(beep_mode, bool, NULL, 0444); 158 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 159 "(0=off, 1=on) (default=1)."); 160 #endif 161 162 #ifdef CONFIG_PM 163 static int param_set_xint(const char *val, const struct kernel_param *kp); 164 static const struct kernel_param_ops param_ops_xint = { 165 .set = param_set_xint, 166 .get = param_get_int, 167 }; 168 #define param_check_xint param_check_int 169 170 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 171 module_param(power_save, xint, 0644); 172 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 173 "(in second, 0 = disable)."); 174 175 static bool pm_blacklist = true; 176 module_param(pm_blacklist, bool, 0644); 177 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist"); 178 179 /* reset the HD-audio controller in power save mode. 180 * this may give more power-saving, but will take longer time to 181 * wake up. 182 */ 183 static bool power_save_controller = 1; 184 module_param(power_save_controller, bool, 0644); 185 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 186 #else 187 #define power_save 0 188 #endif /* CONFIG_PM */ 189 190 static int align_buffer_size = -1; 191 module_param(align_buffer_size, bint, 0644); 192 MODULE_PARM_DESC(align_buffer_size, 193 "Force buffer and period sizes to be multiple of 128 bytes."); 194 195 #ifdef CONFIG_X86 196 static int hda_snoop = -1; 197 module_param_named(snoop, hda_snoop, bint, 0444); 198 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 199 #else 200 #define hda_snoop true 201 #endif 202 203 204 MODULE_LICENSE("GPL"); 205 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 206 "{Intel, ICH6M}," 207 "{Intel, ICH7}," 208 "{Intel, ESB2}," 209 "{Intel, ICH8}," 210 "{Intel, ICH9}," 211 "{Intel, ICH10}," 212 "{Intel, PCH}," 213 "{Intel, CPT}," 214 "{Intel, PPT}," 215 "{Intel, LPT}," 216 "{Intel, LPT_LP}," 217 "{Intel, WPT_LP}," 218 "{Intel, SPT}," 219 "{Intel, SPT_LP}," 220 "{Intel, HPT}," 221 "{Intel, PBG}," 222 "{Intel, SCH}," 223 "{ATI, SB450}," 224 "{ATI, SB600}," 225 "{ATI, RS600}," 226 "{ATI, RS690}," 227 "{ATI, RS780}," 228 "{ATI, R600}," 229 "{ATI, RV630}," 230 "{ATI, RV610}," 231 "{ATI, RV670}," 232 "{ATI, RV635}," 233 "{ATI, RV620}," 234 "{ATI, RV770}," 235 "{VIA, VT8251}," 236 "{VIA, VT8237A}," 237 "{SiS, SIS966}," 238 "{ULI, M5461}}"); 239 MODULE_DESCRIPTION("Intel HDA driver"); 240 241 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 242 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 243 #define SUPPORT_VGA_SWITCHEROO 244 #endif 245 #endif 246 247 248 /* 249 */ 250 251 /* driver types */ 252 enum { 253 AZX_DRIVER_ICH, 254 AZX_DRIVER_PCH, 255 AZX_DRIVER_SCH, 256 AZX_DRIVER_SKL, 257 AZX_DRIVER_HDMI, 258 AZX_DRIVER_ATI, 259 AZX_DRIVER_ATIHDMI, 260 AZX_DRIVER_ATIHDMI_NS, 261 AZX_DRIVER_VIA, 262 AZX_DRIVER_SIS, 263 AZX_DRIVER_ULI, 264 AZX_DRIVER_NVIDIA, 265 AZX_DRIVER_TERA, 266 AZX_DRIVER_CTX, 267 AZX_DRIVER_CTHDA, 268 AZX_DRIVER_CMEDIA, 269 AZX_DRIVER_GENERIC, 270 AZX_NUM_DRIVERS, /* keep this as last entry */ 271 }; 272 273 #define azx_get_snoop_type(chip) \ 274 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 275 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 276 277 /* quirks for old Intel chipsets */ 278 #define AZX_DCAPS_INTEL_ICH \ 279 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 280 281 /* quirks for Intel PCH */ 282 #define AZX_DCAPS_INTEL_PCH_BASE \ 283 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 284 AZX_DCAPS_SNOOP_TYPE(SCH)) 285 286 /* PCH up to IVB; no runtime PM; bind with i915 gfx */ 287 #define AZX_DCAPS_INTEL_PCH_NOPM \ 288 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 289 290 /* PCH for HSW/BDW; with runtime PM */ 291 /* no i915 binding for this as HSW/BDW has another controller for HDMI */ 292 #define AZX_DCAPS_INTEL_PCH \ 293 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) 294 295 /* HSW HDMI */ 296 #define AZX_DCAPS_INTEL_HASWELL \ 297 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 298 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 299 AZX_DCAPS_SNOOP_TYPE(SCH)) 300 301 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 302 #define AZX_DCAPS_INTEL_BROADWELL \ 303 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 304 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 305 AZX_DCAPS_SNOOP_TYPE(SCH)) 306 307 #define AZX_DCAPS_INTEL_BAYTRAIL \ 308 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 309 310 #define AZX_DCAPS_INTEL_BRASWELL \ 311 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 312 AZX_DCAPS_I915_COMPONENT) 313 314 #define AZX_DCAPS_INTEL_SKYLAKE \ 315 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 316 AZX_DCAPS_SYNC_WRITE |\ 317 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT) 318 319 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE 320 321 /* quirks for ATI SB / AMD Hudson */ 322 #define AZX_DCAPS_PRESET_ATI_SB \ 323 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\ 324 AZX_DCAPS_SNOOP_TYPE(ATI)) 325 326 /* quirks for ATI/AMD HDMI */ 327 #define AZX_DCAPS_PRESET_ATI_HDMI \ 328 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\ 329 AZX_DCAPS_NO_MSI64) 330 331 /* quirks for ATI HDMI with snoop off */ 332 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 333 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 334 335 /* quirks for Nvidia */ 336 #define AZX_DCAPS_PRESET_NVIDIA \ 337 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 338 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 339 340 #define AZX_DCAPS_PRESET_CTHDA \ 341 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 342 AZX_DCAPS_NO_64BIT |\ 343 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 344 345 /* 346 * vga_switcheroo support 347 */ 348 #ifdef SUPPORT_VGA_SWITCHEROO 349 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 350 #define needs_eld_notify_link(chip) ((chip)->need_eld_notify_link) 351 #else 352 #define use_vga_switcheroo(chip) 0 353 #define needs_eld_notify_link(chip) false 354 #endif 355 356 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \ 357 ((pci)->device == 0x0c0c) || \ 358 ((pci)->device == 0x0d0c) || \ 359 ((pci)->device == 0x160c)) 360 361 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98) 362 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348) 363 #define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8) 364 365 static char *driver_short_names[] = { 366 [AZX_DRIVER_ICH] = "HDA Intel", 367 [AZX_DRIVER_PCH] = "HDA Intel PCH", 368 [AZX_DRIVER_SCH] = "HDA Intel MID", 369 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */ 370 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 371 [AZX_DRIVER_ATI] = "HDA ATI SB", 372 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 373 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 374 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 375 [AZX_DRIVER_SIS] = "HDA SIS966", 376 [AZX_DRIVER_ULI] = "HDA ULI M5461", 377 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 378 [AZX_DRIVER_TERA] = "HDA Teradici", 379 [AZX_DRIVER_CTX] = "HDA Creative", 380 [AZX_DRIVER_CTHDA] = "HDA Creative", 381 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 382 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 383 }; 384 385 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 386 static void set_default_power_save(struct azx *chip); 387 388 /* 389 * initialize the PCI registers 390 */ 391 /* update bits in a PCI register byte */ 392 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 393 unsigned char mask, unsigned char val) 394 { 395 unsigned char data; 396 397 pci_read_config_byte(pci, reg, &data); 398 data &= ~mask; 399 data |= (val & mask); 400 pci_write_config_byte(pci, reg, data); 401 } 402 403 static void azx_init_pci(struct azx *chip) 404 { 405 int snoop_type = azx_get_snoop_type(chip); 406 407 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 408 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 409 * Ensuring these bits are 0 clears playback static on some HD Audio 410 * codecs. 411 * The PCI register TCSEL is defined in the Intel manuals. 412 */ 413 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 414 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 415 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 416 } 417 418 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 419 * we need to enable snoop. 420 */ 421 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 422 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 423 azx_snoop(chip)); 424 update_pci_byte(chip->pci, 425 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 426 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 427 } 428 429 /* For NVIDIA HDA, enable snoop */ 430 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 431 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 432 azx_snoop(chip)); 433 update_pci_byte(chip->pci, 434 NVIDIA_HDA_TRANSREG_ADDR, 435 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 436 update_pci_byte(chip->pci, 437 NVIDIA_HDA_ISTRM_COH, 438 0x01, NVIDIA_HDA_ENABLE_COHBIT); 439 update_pci_byte(chip->pci, 440 NVIDIA_HDA_OSTRM_COH, 441 0x01, NVIDIA_HDA_ENABLE_COHBIT); 442 } 443 444 /* Enable SCH/PCH snoop if needed */ 445 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 446 unsigned short snoop; 447 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 448 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 449 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 450 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 451 if (!azx_snoop(chip)) 452 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 453 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 454 pci_read_config_word(chip->pci, 455 INTEL_SCH_HDA_DEVC, &snoop); 456 } 457 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 458 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 459 "Disabled" : "Enabled"); 460 } 461 } 462 463 /* 464 * In BXT-P A0, HD-Audio DMA requests is later than expected, 465 * and makes an audio stream sensitive to system latencies when 466 * 24/32 bits are playing. 467 * Adjusting threshold of DMA fifo to force the DMA request 468 * sooner to improve latency tolerance at the expense of power. 469 */ 470 static void bxt_reduce_dma_latency(struct azx *chip) 471 { 472 u32 val; 473 474 val = azx_readl(chip, VS_EM4L); 475 val &= (0x3 << 20); 476 azx_writel(chip, VS_EM4L, val); 477 } 478 479 /* 480 * ML_LCAP bits: 481 * bit 0: 6 MHz Supported 482 * bit 1: 12 MHz Supported 483 * bit 2: 24 MHz Supported 484 * bit 3: 48 MHz Supported 485 * bit 4: 96 MHz Supported 486 * bit 5: 192 MHz Supported 487 */ 488 static int intel_get_lctl_scf(struct azx *chip) 489 { 490 struct hdac_bus *bus = azx_bus(chip); 491 static int preferred_bits[] = { 2, 3, 1, 4, 5 }; 492 u32 val, t; 493 int i; 494 495 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); 496 497 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) { 498 t = preferred_bits[i]; 499 if (val & (1 << t)) 500 return t; 501 } 502 503 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz"); 504 return 0; 505 } 506 507 static int intel_ml_lctl_set_power(struct azx *chip, int state) 508 { 509 struct hdac_bus *bus = azx_bus(chip); 510 u32 val; 511 int timeout; 512 513 /* 514 * the codecs are sharing the first link setting by default 515 * If other links are enabled for stream, they need similar fix 516 */ 517 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 518 val &= ~AZX_MLCTL_SPA; 519 val |= state << AZX_MLCTL_SPA_SHIFT; 520 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 521 /* wait for CPA */ 522 timeout = 50; 523 while (timeout) { 524 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) & 525 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT)) 526 return 0; 527 timeout--; 528 udelay(10); 529 } 530 531 return -1; 532 } 533 534 static void intel_init_lctl(struct azx *chip) 535 { 536 struct hdac_bus *bus = azx_bus(chip); 537 u32 val; 538 int ret; 539 540 /* 0. check lctl register value is correct or not */ 541 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 542 /* if SCF is already set, let's use it */ 543 if ((val & ML_LCTL_SCF_MASK) != 0) 544 return; 545 546 /* 547 * Before operating on SPA, CPA must match SPA. 548 * Any deviation may result in undefined behavior. 549 */ 550 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) != 551 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT)) 552 return; 553 554 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */ 555 ret = intel_ml_lctl_set_power(chip, 0); 556 udelay(100); 557 if (ret) 558 goto set_spa; 559 560 /* 2. update SCF to select a properly audio clock*/ 561 val &= ~ML_LCTL_SCF_MASK; 562 val |= intel_get_lctl_scf(chip); 563 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 564 565 set_spa: 566 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */ 567 intel_ml_lctl_set_power(chip, 1); 568 udelay(100); 569 } 570 571 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 572 { 573 struct hdac_bus *bus = azx_bus(chip); 574 struct pci_dev *pci = chip->pci; 575 u32 val; 576 577 snd_hdac_set_codec_wakeup(bus, true); 578 if (chip->driver_type == AZX_DRIVER_SKL) { 579 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 580 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; 581 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 582 } 583 azx_init_chip(chip, full_reset); 584 if (chip->driver_type == AZX_DRIVER_SKL) { 585 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 586 val = val | INTEL_HDA_CGCTL_MISCBDCGE; 587 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 588 } 589 590 snd_hdac_set_codec_wakeup(bus, false); 591 592 /* reduce dma latency to avoid noise */ 593 if (IS_BXT(pci)) 594 bxt_reduce_dma_latency(chip); 595 596 if (bus->mlcap != NULL) 597 intel_init_lctl(chip); 598 } 599 600 /* calculate runtime delay from LPIB */ 601 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 602 unsigned int pos) 603 { 604 struct snd_pcm_substream *substream = azx_dev->core.substream; 605 int stream = substream->stream; 606 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 607 int delay; 608 609 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 610 delay = pos - lpib_pos; 611 else 612 delay = lpib_pos - pos; 613 if (delay < 0) { 614 if (delay >= azx_dev->core.delay_negative_threshold) 615 delay = 0; 616 else 617 delay += azx_dev->core.bufsize; 618 } 619 620 if (delay >= azx_dev->core.period_bytes) { 621 dev_info(chip->card->dev, 622 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 623 delay, azx_dev->core.period_bytes); 624 delay = 0; 625 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 626 chip->get_delay[stream] = NULL; 627 } 628 629 return bytes_to_frames(substream->runtime, delay); 630 } 631 632 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 633 634 /* called from IRQ */ 635 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 636 { 637 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 638 int ok; 639 640 ok = azx_position_ok(chip, azx_dev); 641 if (ok == 1) { 642 azx_dev->irq_pending = 0; 643 return ok; 644 } else if (ok == 0) { 645 /* bogus IRQ, process it later */ 646 azx_dev->irq_pending = 1; 647 schedule_work(&hda->irq_pending_work); 648 } 649 return 0; 650 } 651 652 #define display_power(chip, enable) \ 653 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable) 654 655 /* 656 * Check whether the current DMA position is acceptable for updating 657 * periods. Returns non-zero if it's OK. 658 * 659 * Many HD-audio controllers appear pretty inaccurate about 660 * the update-IRQ timing. The IRQ is issued before actually the 661 * data is processed. So, we need to process it afterwords in a 662 * workqueue. 663 */ 664 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 665 { 666 struct snd_pcm_substream *substream = azx_dev->core.substream; 667 int stream = substream->stream; 668 u32 wallclk; 669 unsigned int pos; 670 671 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 672 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 673 return -1; /* bogus (too early) interrupt */ 674 675 if (chip->get_position[stream]) 676 pos = chip->get_position[stream](chip, azx_dev); 677 else { /* use the position buffer as default */ 678 pos = azx_get_pos_posbuf(chip, azx_dev); 679 if (!pos || pos == (u32)-1) { 680 dev_info(chip->card->dev, 681 "Invalid position buffer, using LPIB read method instead.\n"); 682 chip->get_position[stream] = azx_get_pos_lpib; 683 if (chip->get_position[0] == azx_get_pos_lpib && 684 chip->get_position[1] == azx_get_pos_lpib) 685 azx_bus(chip)->use_posbuf = false; 686 pos = azx_get_pos_lpib(chip, azx_dev); 687 chip->get_delay[stream] = NULL; 688 } else { 689 chip->get_position[stream] = azx_get_pos_posbuf; 690 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 691 chip->get_delay[stream] = azx_get_delay_from_lpib; 692 } 693 } 694 695 if (pos >= azx_dev->core.bufsize) 696 pos = 0; 697 698 if (WARN_ONCE(!azx_dev->core.period_bytes, 699 "hda-intel: zero azx_dev->period_bytes")) 700 return -1; /* this shouldn't happen! */ 701 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 702 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 703 /* NG - it's below the first next period boundary */ 704 return chip->bdl_pos_adj ? 0 : -1; 705 azx_dev->core.start_wallclk += wallclk; 706 return 1; /* OK, it's fine */ 707 } 708 709 /* 710 * The work for pending PCM period updates. 711 */ 712 static void azx_irq_pending_work(struct work_struct *work) 713 { 714 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 715 struct azx *chip = &hda->chip; 716 struct hdac_bus *bus = azx_bus(chip); 717 struct hdac_stream *s; 718 int pending, ok; 719 720 if (!hda->irq_pending_warned) { 721 dev_info(chip->card->dev, 722 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 723 chip->card->number); 724 hda->irq_pending_warned = 1; 725 } 726 727 for (;;) { 728 pending = 0; 729 spin_lock_irq(&bus->reg_lock); 730 list_for_each_entry(s, &bus->stream_list, list) { 731 struct azx_dev *azx_dev = stream_to_azx_dev(s); 732 if (!azx_dev->irq_pending || 733 !s->substream || 734 !s->running) 735 continue; 736 ok = azx_position_ok(chip, azx_dev); 737 if (ok > 0) { 738 azx_dev->irq_pending = 0; 739 spin_unlock(&bus->reg_lock); 740 snd_pcm_period_elapsed(s->substream); 741 spin_lock(&bus->reg_lock); 742 } else if (ok < 0) { 743 pending = 0; /* too early */ 744 } else 745 pending++; 746 } 747 spin_unlock_irq(&bus->reg_lock); 748 if (!pending) 749 return; 750 msleep(1); 751 } 752 } 753 754 /* clear irq_pending flags and assure no on-going workq */ 755 static void azx_clear_irq_pending(struct azx *chip) 756 { 757 struct hdac_bus *bus = azx_bus(chip); 758 struct hdac_stream *s; 759 760 spin_lock_irq(&bus->reg_lock); 761 list_for_each_entry(s, &bus->stream_list, list) { 762 struct azx_dev *azx_dev = stream_to_azx_dev(s); 763 azx_dev->irq_pending = 0; 764 } 765 spin_unlock_irq(&bus->reg_lock); 766 } 767 768 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 769 { 770 struct hdac_bus *bus = azx_bus(chip); 771 772 if (request_irq(chip->pci->irq, azx_interrupt, 773 chip->msi ? 0 : IRQF_SHARED, 774 chip->card->irq_descr, chip)) { 775 dev_err(chip->card->dev, 776 "unable to grab IRQ %d, disabling device\n", 777 chip->pci->irq); 778 if (do_disconnect) 779 snd_card_disconnect(chip->card); 780 return -1; 781 } 782 bus->irq = chip->pci->irq; 783 pci_intx(chip->pci, !chip->msi); 784 return 0; 785 } 786 787 /* get the current DMA position with correction on VIA chips */ 788 static unsigned int azx_via_get_position(struct azx *chip, 789 struct azx_dev *azx_dev) 790 { 791 unsigned int link_pos, mini_pos, bound_pos; 792 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 793 unsigned int fifo_size; 794 795 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 796 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 797 /* Playback, no problem using link position */ 798 return link_pos; 799 } 800 801 /* Capture */ 802 /* For new chipset, 803 * use mod to get the DMA position just like old chipset 804 */ 805 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 806 mod_dma_pos %= azx_dev->core.period_bytes; 807 808 /* azx_dev->fifo_size can't get FIFO size of in stream. 809 * Get from base address + offset. 810 */ 811 fifo_size = readw(azx_bus(chip)->remap_addr + 812 VIA_IN_STREAM0_FIFO_SIZE_OFFSET); 813 814 if (azx_dev->insufficient) { 815 /* Link position never gather than FIFO size */ 816 if (link_pos <= fifo_size) 817 return 0; 818 819 azx_dev->insufficient = 0; 820 } 821 822 if (link_pos <= fifo_size) 823 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 824 else 825 mini_pos = link_pos - fifo_size; 826 827 /* Find nearest previous boudary */ 828 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 829 mod_link_pos = link_pos % azx_dev->core.period_bytes; 830 if (mod_link_pos >= fifo_size) 831 bound_pos = link_pos - mod_link_pos; 832 else if (mod_dma_pos >= mod_mini_pos) 833 bound_pos = mini_pos - mod_mini_pos; 834 else { 835 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 836 if (bound_pos >= azx_dev->core.bufsize) 837 bound_pos = 0; 838 } 839 840 /* Calculate real DMA position we want */ 841 return bound_pos + mod_dma_pos; 842 } 843 844 static unsigned int azx_skl_get_dpib_pos(struct azx *chip, 845 struct azx_dev *azx_dev) 846 { 847 return _snd_hdac_chip_readl(azx_bus(chip), 848 AZX_REG_VS_SDXDPIB_XBASE + 849 (AZX_REG_VS_SDXDPIB_XINTERVAL * 850 azx_dev->core.index)); 851 } 852 853 /* get the current DMA position with correction on SKL+ chips */ 854 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev) 855 { 856 /* DPIB register gives a more accurate position for playback */ 857 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 858 return azx_skl_get_dpib_pos(chip, azx_dev); 859 860 /* For capture, we need to read posbuf, but it requires a delay 861 * for the possible boundary overlap; the read of DPIB fetches the 862 * actual posbuf 863 */ 864 udelay(20); 865 azx_skl_get_dpib_pos(chip, azx_dev); 866 return azx_get_pos_posbuf(chip, azx_dev); 867 } 868 869 #ifdef CONFIG_PM 870 static DEFINE_MUTEX(card_list_lock); 871 static LIST_HEAD(card_list); 872 873 static void azx_add_card_list(struct azx *chip) 874 { 875 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 876 mutex_lock(&card_list_lock); 877 list_add(&hda->list, &card_list); 878 mutex_unlock(&card_list_lock); 879 } 880 881 static void azx_del_card_list(struct azx *chip) 882 { 883 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 884 mutex_lock(&card_list_lock); 885 list_del_init(&hda->list); 886 mutex_unlock(&card_list_lock); 887 } 888 889 /* trigger power-save check at writing parameter */ 890 static int param_set_xint(const char *val, const struct kernel_param *kp) 891 { 892 struct hda_intel *hda; 893 struct azx *chip; 894 int prev = power_save; 895 int ret = param_set_int(val, kp); 896 897 if (ret || prev == power_save) 898 return ret; 899 900 mutex_lock(&card_list_lock); 901 list_for_each_entry(hda, &card_list, list) { 902 chip = &hda->chip; 903 if (!hda->probe_continued || chip->disabled) 904 continue; 905 snd_hda_set_power_save(&chip->bus, power_save * 1000); 906 } 907 mutex_unlock(&card_list_lock); 908 return 0; 909 } 910 911 /* 912 * power management 913 */ 914 static bool azx_is_pm_ready(struct snd_card *card) 915 { 916 struct azx *chip; 917 struct hda_intel *hda; 918 919 if (!card) 920 return false; 921 chip = card->private_data; 922 hda = container_of(chip, struct hda_intel, chip); 923 if (chip->disabled || hda->init_failed || !chip->running) 924 return false; 925 return true; 926 } 927 928 static void __azx_runtime_suspend(struct azx *chip) 929 { 930 azx_stop_chip(chip); 931 azx_enter_link_reset(chip); 932 azx_clear_irq_pending(chip); 933 display_power(chip, false); 934 } 935 936 static void __azx_runtime_resume(struct azx *chip, bool from_rt) 937 { 938 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 939 struct hdac_bus *bus = azx_bus(chip); 940 struct hda_codec *codec; 941 int status; 942 943 display_power(chip, true); 944 if (hda->need_i915_power) 945 snd_hdac_i915_set_bclk(bus); 946 947 /* Read STATESTS before controller reset */ 948 status = azx_readw(chip, STATESTS); 949 950 azx_init_pci(chip); 951 hda_intel_init_chip(chip, true); 952 953 if (status && from_rt) { 954 list_for_each_codec(codec, &chip->bus) 955 if (status & (1 << codec->addr)) 956 schedule_delayed_work(&codec->jackpoll_work, 957 codec->jackpoll_interval); 958 } 959 960 /* power down again for link-controlled chips */ 961 if (!hda->need_i915_power) 962 display_power(chip, false); 963 } 964 965 #ifdef CONFIG_PM_SLEEP 966 static int azx_suspend(struct device *dev) 967 { 968 struct snd_card *card = dev_get_drvdata(dev); 969 struct azx *chip; 970 struct hdac_bus *bus; 971 972 if (!azx_is_pm_ready(card)) 973 return 0; 974 975 chip = card->private_data; 976 bus = azx_bus(chip); 977 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 978 __azx_runtime_suspend(chip); 979 if (bus->irq >= 0) { 980 free_irq(bus->irq, chip); 981 bus->irq = -1; 982 } 983 984 if (chip->msi) 985 pci_disable_msi(chip->pci); 986 987 trace_azx_suspend(chip); 988 return 0; 989 } 990 991 static int azx_resume(struct device *dev) 992 { 993 struct snd_card *card = dev_get_drvdata(dev); 994 struct azx *chip; 995 996 if (!azx_is_pm_ready(card)) 997 return 0; 998 999 chip = card->private_data; 1000 if (chip->msi) 1001 if (pci_enable_msi(chip->pci) < 0) 1002 chip->msi = 0; 1003 if (azx_acquire_irq(chip, 1) < 0) 1004 return -EIO; 1005 __azx_runtime_resume(chip, false); 1006 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1007 1008 trace_azx_resume(chip); 1009 return 0; 1010 } 1011 1012 /* put codec down to D3 at hibernation for Intel SKL+; 1013 * otherwise BIOS may still access the codec and screw up the driver 1014 */ 1015 static int azx_freeze_noirq(struct device *dev) 1016 { 1017 struct snd_card *card = dev_get_drvdata(dev); 1018 struct azx *chip = card->private_data; 1019 struct pci_dev *pci = to_pci_dev(dev); 1020 1021 if (chip->driver_type == AZX_DRIVER_SKL) 1022 pci_set_power_state(pci, PCI_D3hot); 1023 1024 return 0; 1025 } 1026 1027 static int azx_thaw_noirq(struct device *dev) 1028 { 1029 struct snd_card *card = dev_get_drvdata(dev); 1030 struct azx *chip = card->private_data; 1031 struct pci_dev *pci = to_pci_dev(dev); 1032 1033 if (chip->driver_type == AZX_DRIVER_SKL) 1034 pci_set_power_state(pci, PCI_D0); 1035 1036 return 0; 1037 } 1038 #endif /* CONFIG_PM_SLEEP */ 1039 1040 static int azx_runtime_suspend(struct device *dev) 1041 { 1042 struct snd_card *card = dev_get_drvdata(dev); 1043 struct azx *chip; 1044 1045 if (!azx_is_pm_ready(card)) 1046 return 0; 1047 chip = card->private_data; 1048 if (!azx_has_pm_runtime(chip)) 1049 return 0; 1050 1051 /* enable controller wake up event */ 1052 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 1053 STATESTS_INT_MASK); 1054 1055 __azx_runtime_suspend(chip); 1056 trace_azx_runtime_suspend(chip); 1057 return 0; 1058 } 1059 1060 static int azx_runtime_resume(struct device *dev) 1061 { 1062 struct snd_card *card = dev_get_drvdata(dev); 1063 struct azx *chip; 1064 1065 if (!azx_is_pm_ready(card)) 1066 return 0; 1067 chip = card->private_data; 1068 if (!azx_has_pm_runtime(chip)) 1069 return 0; 1070 __azx_runtime_resume(chip, true); 1071 1072 /* disable controller Wake Up event*/ 1073 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 1074 ~STATESTS_INT_MASK); 1075 1076 trace_azx_runtime_resume(chip); 1077 return 0; 1078 } 1079 1080 static int azx_runtime_idle(struct device *dev) 1081 { 1082 struct snd_card *card = dev_get_drvdata(dev); 1083 struct azx *chip; 1084 struct hda_intel *hda; 1085 1086 if (!card) 1087 return 0; 1088 1089 chip = card->private_data; 1090 hda = container_of(chip, struct hda_intel, chip); 1091 if (chip->disabled || hda->init_failed) 1092 return 0; 1093 1094 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1095 azx_bus(chip)->codec_powered || !chip->running) 1096 return -EBUSY; 1097 1098 /* ELD notification gets broken when HD-audio bus is off */ 1099 if (needs_eld_notify_link(hda)) 1100 return -EBUSY; 1101 1102 return 0; 1103 } 1104 1105 static const struct dev_pm_ops azx_pm = { 1106 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1107 #ifdef CONFIG_PM_SLEEP 1108 .freeze_noirq = azx_freeze_noirq, 1109 .thaw_noirq = azx_thaw_noirq, 1110 #endif 1111 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1112 }; 1113 1114 #define AZX_PM_OPS &azx_pm 1115 #else 1116 #define azx_add_card_list(chip) /* NOP */ 1117 #define azx_del_card_list(chip) /* NOP */ 1118 #define AZX_PM_OPS NULL 1119 #endif /* CONFIG_PM */ 1120 1121 1122 static int azx_probe_continue(struct azx *chip); 1123 1124 #ifdef SUPPORT_VGA_SWITCHEROO 1125 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1126 1127 static void azx_vs_set_state(struct pci_dev *pci, 1128 enum vga_switcheroo_state state) 1129 { 1130 struct snd_card *card = pci_get_drvdata(pci); 1131 struct azx *chip = card->private_data; 1132 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1133 struct hda_codec *codec; 1134 bool disabled; 1135 1136 wait_for_completion(&hda->probe_wait); 1137 if (hda->init_failed) 1138 return; 1139 1140 disabled = (state == VGA_SWITCHEROO_OFF); 1141 if (chip->disabled == disabled) 1142 return; 1143 1144 if (!hda->probe_continued) { 1145 chip->disabled = disabled; 1146 if (!disabled) { 1147 dev_info(chip->card->dev, 1148 "Start delayed initialization\n"); 1149 if (azx_probe_continue(chip) < 0) { 1150 dev_err(chip->card->dev, "initialization error\n"); 1151 hda->init_failed = true; 1152 } 1153 } 1154 } else { 1155 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1156 disabled ? "Disabling" : "Enabling"); 1157 if (disabled) { 1158 list_for_each_codec(codec, &chip->bus) { 1159 pm_runtime_suspend(hda_codec_dev(codec)); 1160 pm_runtime_disable(hda_codec_dev(codec)); 1161 } 1162 pm_runtime_suspend(card->dev); 1163 pm_runtime_disable(card->dev); 1164 /* when we get suspended by vga_switcheroo we end up in D3cold, 1165 * however we have no ACPI handle, so pci/acpi can't put us there, 1166 * put ourselves there */ 1167 pci->current_state = PCI_D3cold; 1168 chip->disabled = true; 1169 if (snd_hda_lock_devices(&chip->bus)) 1170 dev_warn(chip->card->dev, 1171 "Cannot lock devices!\n"); 1172 } else { 1173 snd_hda_unlock_devices(&chip->bus); 1174 chip->disabled = false; 1175 pm_runtime_enable(card->dev); 1176 list_for_each_codec(codec, &chip->bus) { 1177 pm_runtime_enable(hda_codec_dev(codec)); 1178 pm_runtime_resume(hda_codec_dev(codec)); 1179 } 1180 } 1181 } 1182 } 1183 1184 static bool azx_vs_can_switch(struct pci_dev *pci) 1185 { 1186 struct snd_card *card = pci_get_drvdata(pci); 1187 struct azx *chip = card->private_data; 1188 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1189 1190 wait_for_completion(&hda->probe_wait); 1191 if (hda->init_failed) 1192 return false; 1193 if (chip->disabled || !hda->probe_continued) 1194 return true; 1195 if (snd_hda_lock_devices(&chip->bus)) 1196 return false; 1197 snd_hda_unlock_devices(&chip->bus); 1198 return true; 1199 } 1200 1201 /* 1202 * The discrete GPU cannot power down unless the HDA controller runtime 1203 * suspends, so activate runtime PM on codecs even if power_save == 0. 1204 */ 1205 static void setup_vga_switcheroo_runtime_pm(struct azx *chip) 1206 { 1207 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1208 struct hda_codec *codec; 1209 1210 if (hda->use_vga_switcheroo && !hda->need_eld_notify_link) { 1211 list_for_each_codec(codec, &chip->bus) 1212 codec->auto_runtime_pm = 1; 1213 /* reset the power save setup */ 1214 if (chip->running) 1215 set_default_power_save(chip); 1216 } 1217 } 1218 1219 static void azx_vs_gpu_bound(struct pci_dev *pci, 1220 enum vga_switcheroo_client_id client_id) 1221 { 1222 struct snd_card *card = pci_get_drvdata(pci); 1223 struct azx *chip = card->private_data; 1224 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1225 1226 if (client_id == VGA_SWITCHEROO_DIS) 1227 hda->need_eld_notify_link = 0; 1228 setup_vga_switcheroo_runtime_pm(chip); 1229 } 1230 1231 static void init_vga_switcheroo(struct azx *chip) 1232 { 1233 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1234 struct pci_dev *p = get_bound_vga(chip->pci); 1235 if (p) { 1236 dev_info(chip->card->dev, 1237 "Handle vga_switcheroo audio client\n"); 1238 hda->use_vga_switcheroo = 1; 1239 hda->need_eld_notify_link = 1; /* cleared in gpu_bound op */ 1240 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; 1241 pci_dev_put(p); 1242 } 1243 } 1244 1245 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1246 .set_gpu_state = azx_vs_set_state, 1247 .can_switch = azx_vs_can_switch, 1248 .gpu_bound = azx_vs_gpu_bound, 1249 }; 1250 1251 static int register_vga_switcheroo(struct azx *chip) 1252 { 1253 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1254 struct pci_dev *p; 1255 int err; 1256 1257 if (!hda->use_vga_switcheroo) 1258 return 0; 1259 1260 p = get_bound_vga(chip->pci); 1261 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p); 1262 pci_dev_put(p); 1263 1264 if (err < 0) 1265 return err; 1266 hda->vga_switcheroo_registered = 1; 1267 1268 return 0; 1269 } 1270 #else 1271 #define init_vga_switcheroo(chip) /* NOP */ 1272 #define register_vga_switcheroo(chip) 0 1273 #define check_hdmi_disabled(pci) false 1274 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */ 1275 #endif /* SUPPORT_VGA_SWITCHER */ 1276 1277 /* 1278 * destructor 1279 */ 1280 static int azx_free(struct azx *chip) 1281 { 1282 struct pci_dev *pci = chip->pci; 1283 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1284 struct hdac_bus *bus = azx_bus(chip); 1285 1286 if (azx_has_pm_runtime(chip) && chip->running) 1287 pm_runtime_get_noresume(&pci->dev); 1288 chip->running = 0; 1289 1290 azx_del_card_list(chip); 1291 1292 hda->init_failed = 1; /* to be sure */ 1293 complete_all(&hda->probe_wait); 1294 1295 if (use_vga_switcheroo(hda)) { 1296 if (chip->disabled && hda->probe_continued) 1297 snd_hda_unlock_devices(&chip->bus); 1298 if (hda->vga_switcheroo_registered) 1299 vga_switcheroo_unregister_client(chip->pci); 1300 } 1301 1302 if (bus->chip_init) { 1303 azx_clear_irq_pending(chip); 1304 azx_stop_all_streams(chip); 1305 azx_stop_chip(chip); 1306 } 1307 1308 if (bus->irq >= 0) 1309 free_irq(bus->irq, (void*)chip); 1310 if (chip->msi) 1311 pci_disable_msi(chip->pci); 1312 iounmap(bus->remap_addr); 1313 1314 azx_free_stream_pages(chip); 1315 azx_free_streams(chip); 1316 snd_hdac_bus_exit(bus); 1317 1318 if (chip->region_requested) 1319 pci_release_regions(chip->pci); 1320 1321 pci_disable_device(chip->pci); 1322 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1323 release_firmware(chip->fw); 1324 #endif 1325 display_power(chip, false); 1326 1327 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) 1328 snd_hdac_i915_exit(bus); 1329 kfree(hda); 1330 1331 return 0; 1332 } 1333 1334 static int azx_dev_disconnect(struct snd_device *device) 1335 { 1336 struct azx *chip = device->device_data; 1337 1338 chip->bus.shutdown = 1; 1339 return 0; 1340 } 1341 1342 static int azx_dev_free(struct snd_device *device) 1343 { 1344 return azx_free(device->device_data); 1345 } 1346 1347 #ifdef SUPPORT_VGA_SWITCHEROO 1348 /* 1349 * Check of disabled HDMI controller by vga_switcheroo 1350 */ 1351 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1352 { 1353 struct pci_dev *p; 1354 1355 /* check only discrete GPU */ 1356 switch (pci->vendor) { 1357 case PCI_VENDOR_ID_ATI: 1358 case PCI_VENDOR_ID_AMD: 1359 case PCI_VENDOR_ID_NVIDIA: 1360 if (pci->devfn == 1) { 1361 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1362 pci->bus->number, 0); 1363 if (p) { 1364 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) 1365 return p; 1366 pci_dev_put(p); 1367 } 1368 } 1369 break; 1370 } 1371 return NULL; 1372 } 1373 1374 static bool check_hdmi_disabled(struct pci_dev *pci) 1375 { 1376 bool vga_inactive = false; 1377 struct pci_dev *p = get_bound_vga(pci); 1378 1379 if (p) { 1380 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1381 vga_inactive = true; 1382 pci_dev_put(p); 1383 } 1384 return vga_inactive; 1385 } 1386 #endif /* SUPPORT_VGA_SWITCHEROO */ 1387 1388 /* 1389 * white/black-listing for position_fix 1390 */ 1391 static struct snd_pci_quirk position_fix_list[] = { 1392 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1393 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1394 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1395 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1396 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1397 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1398 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1399 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1400 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1401 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1402 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1403 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1404 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1405 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1406 {} 1407 }; 1408 1409 static int check_position_fix(struct azx *chip, int fix) 1410 { 1411 const struct snd_pci_quirk *q; 1412 1413 switch (fix) { 1414 case POS_FIX_AUTO: 1415 case POS_FIX_LPIB: 1416 case POS_FIX_POSBUF: 1417 case POS_FIX_VIACOMBO: 1418 case POS_FIX_COMBO: 1419 case POS_FIX_SKL: 1420 return fix; 1421 } 1422 1423 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1424 if (q) { 1425 dev_info(chip->card->dev, 1426 "position_fix set to %d for device %04x:%04x\n", 1427 q->value, q->subvendor, q->subdevice); 1428 return q->value; 1429 } 1430 1431 /* Check VIA/ATI HD Audio Controller exist */ 1432 if (chip->driver_type == AZX_DRIVER_VIA) { 1433 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1434 return POS_FIX_VIACOMBO; 1435 } 1436 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1437 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1438 return POS_FIX_LPIB; 1439 } 1440 if (chip->driver_type == AZX_DRIVER_SKL) { 1441 dev_dbg(chip->card->dev, "Using SKL position fix\n"); 1442 return POS_FIX_SKL; 1443 } 1444 return POS_FIX_AUTO; 1445 } 1446 1447 static void assign_position_fix(struct azx *chip, int fix) 1448 { 1449 static azx_get_pos_callback_t callbacks[] = { 1450 [POS_FIX_AUTO] = NULL, 1451 [POS_FIX_LPIB] = azx_get_pos_lpib, 1452 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1453 [POS_FIX_VIACOMBO] = azx_via_get_position, 1454 [POS_FIX_COMBO] = azx_get_pos_lpib, 1455 [POS_FIX_SKL] = azx_get_pos_skl, 1456 }; 1457 1458 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1459 1460 /* combo mode uses LPIB only for playback */ 1461 if (fix == POS_FIX_COMBO) 1462 chip->get_position[1] = NULL; 1463 1464 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) && 1465 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1466 chip->get_delay[0] = chip->get_delay[1] = 1467 azx_get_delay_from_lpib; 1468 } 1469 1470 } 1471 1472 /* 1473 * black-lists for probe_mask 1474 */ 1475 static struct snd_pci_quirk probe_mask_list[] = { 1476 /* Thinkpad often breaks the controller communication when accessing 1477 * to the non-working (or non-existing) modem codec slot. 1478 */ 1479 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1480 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1481 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1482 /* broken BIOS */ 1483 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1484 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1485 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1486 /* forced codec slots */ 1487 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1488 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1489 /* WinFast VP200 H (Teradici) user reported broken communication */ 1490 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1491 {} 1492 }; 1493 1494 #define AZX_FORCE_CODEC_MASK 0x100 1495 1496 static void check_probe_mask(struct azx *chip, int dev) 1497 { 1498 const struct snd_pci_quirk *q; 1499 1500 chip->codec_probe_mask = probe_mask[dev]; 1501 if (chip->codec_probe_mask == -1) { 1502 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1503 if (q) { 1504 dev_info(chip->card->dev, 1505 "probe_mask set to 0x%x for device %04x:%04x\n", 1506 q->value, q->subvendor, q->subdevice); 1507 chip->codec_probe_mask = q->value; 1508 } 1509 } 1510 1511 /* check forced option */ 1512 if (chip->codec_probe_mask != -1 && 1513 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1514 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1515 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1516 (int)azx_bus(chip)->codec_mask); 1517 } 1518 } 1519 1520 /* 1521 * white/black-list for enable_msi 1522 */ 1523 static struct snd_pci_quirk msi_black_list[] = { 1524 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1525 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1526 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1527 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1528 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1529 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1530 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1531 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1532 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1533 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1534 {} 1535 }; 1536 1537 static void check_msi(struct azx *chip) 1538 { 1539 const struct snd_pci_quirk *q; 1540 1541 if (enable_msi >= 0) { 1542 chip->msi = !!enable_msi; 1543 return; 1544 } 1545 chip->msi = 1; /* enable MSI as default */ 1546 q = snd_pci_quirk_lookup(chip->pci, msi_black_list); 1547 if (q) { 1548 dev_info(chip->card->dev, 1549 "msi for device %04x:%04x set to %d\n", 1550 q->subvendor, q->subdevice, q->value); 1551 chip->msi = q->value; 1552 return; 1553 } 1554 1555 /* NVidia chipsets seem to cause troubles with MSI */ 1556 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1557 dev_info(chip->card->dev, "Disabling MSI\n"); 1558 chip->msi = 0; 1559 } 1560 } 1561 1562 /* check the snoop mode availability */ 1563 static void azx_check_snoop_available(struct azx *chip) 1564 { 1565 int snoop = hda_snoop; 1566 1567 if (snoop >= 0) { 1568 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1569 snoop ? "snoop" : "non-snoop"); 1570 chip->snoop = snoop; 1571 chip->uc_buffer = !snoop; 1572 return; 1573 } 1574 1575 snoop = true; 1576 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1577 chip->driver_type == AZX_DRIVER_VIA) { 1578 /* force to non-snoop mode for a new VIA controller 1579 * when BIOS is set 1580 */ 1581 u8 val; 1582 pci_read_config_byte(chip->pci, 0x42, &val); 1583 if (!(val & 0x80) && (chip->pci->revision == 0x30 || 1584 chip->pci->revision == 0x20)) 1585 snoop = false; 1586 } 1587 1588 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1589 snoop = false; 1590 1591 chip->snoop = snoop; 1592 if (!snoop) { 1593 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1594 /* C-Media requires non-cached pages only for CORB/RIRB */ 1595 if (chip->driver_type != AZX_DRIVER_CMEDIA) 1596 chip->uc_buffer = true; 1597 } 1598 } 1599 1600 static void azx_probe_work(struct work_struct *work) 1601 { 1602 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work); 1603 azx_probe_continue(&hda->chip); 1604 } 1605 1606 static int default_bdl_pos_adj(struct azx *chip) 1607 { 1608 /* some exceptions: Atoms seem problematic with value 1 */ 1609 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { 1610 switch (chip->pci->device) { 1611 case 0x0f04: /* Baytrail */ 1612 case 0x2284: /* Braswell */ 1613 return 32; 1614 } 1615 } 1616 1617 switch (chip->driver_type) { 1618 case AZX_DRIVER_ICH: 1619 case AZX_DRIVER_PCH: 1620 return 1; 1621 default: 1622 return 32; 1623 } 1624 } 1625 1626 /* 1627 * constructor 1628 */ 1629 static const struct hdac_io_ops pci_hda_io_ops; 1630 static const struct hda_controller_ops pci_hda_ops; 1631 1632 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1633 int dev, unsigned int driver_caps, 1634 struct azx **rchip) 1635 { 1636 static struct snd_device_ops ops = { 1637 .dev_disconnect = azx_dev_disconnect, 1638 .dev_free = azx_dev_free, 1639 }; 1640 struct hda_intel *hda; 1641 struct azx *chip; 1642 int err; 1643 1644 *rchip = NULL; 1645 1646 err = pci_enable_device(pci); 1647 if (err < 0) 1648 return err; 1649 1650 hda = kzalloc(sizeof(*hda), GFP_KERNEL); 1651 if (!hda) { 1652 pci_disable_device(pci); 1653 return -ENOMEM; 1654 } 1655 1656 chip = &hda->chip; 1657 mutex_init(&chip->open_mutex); 1658 chip->card = card; 1659 chip->pci = pci; 1660 chip->ops = &pci_hda_ops; 1661 chip->driver_caps = driver_caps; 1662 chip->driver_type = driver_caps & 0xff; 1663 check_msi(chip); 1664 chip->dev_index = dev; 1665 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000) 1666 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]); 1667 INIT_LIST_HEAD(&chip->pcm_list); 1668 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1669 INIT_LIST_HEAD(&hda->list); 1670 init_vga_switcheroo(chip); 1671 init_completion(&hda->probe_wait); 1672 1673 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1674 1675 check_probe_mask(chip, dev); 1676 1677 if (single_cmd < 0) /* allow fallback to single_cmd at errors */ 1678 chip->fallback_to_single_cmd = 1; 1679 else /* explicitly set to single_cmd or not */ 1680 chip->single_cmd = single_cmd; 1681 1682 azx_check_snoop_available(chip); 1683 1684 if (bdl_pos_adj[dev] < 0) 1685 chip->bdl_pos_adj = default_bdl_pos_adj(chip); 1686 else 1687 chip->bdl_pos_adj = bdl_pos_adj[dev]; 1688 1689 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops); 1690 if (err < 0) { 1691 kfree(hda); 1692 pci_disable_device(pci); 1693 return err; 1694 } 1695 1696 /* Workaround for a communication error on CFL (bko#199007) and CNL */ 1697 if (IS_CFL(pci) || IS_CNL(pci)) 1698 azx_bus(chip)->polling_mode = 1; 1699 1700 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 1701 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); 1702 chip->bus.needs_damn_long_delay = 1; 1703 } 1704 1705 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1706 if (err < 0) { 1707 dev_err(card->dev, "Error creating device [card]!\n"); 1708 azx_free(chip); 1709 return err; 1710 } 1711 1712 /* continue probing in work context as may trigger request module */ 1713 INIT_WORK(&hda->probe_work, azx_probe_work); 1714 1715 *rchip = chip; 1716 1717 return 0; 1718 } 1719 1720 static int azx_first_init(struct azx *chip) 1721 { 1722 int dev = chip->dev_index; 1723 struct pci_dev *pci = chip->pci; 1724 struct snd_card *card = chip->card; 1725 struct hdac_bus *bus = azx_bus(chip); 1726 int err; 1727 unsigned short gcap; 1728 unsigned int dma_bits = 64; 1729 1730 #if BITS_PER_LONG != 64 1731 /* Fix up base address on ULI M5461 */ 1732 if (chip->driver_type == AZX_DRIVER_ULI) { 1733 u16 tmp3; 1734 pci_read_config_word(pci, 0x40, &tmp3); 1735 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1736 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1737 } 1738 #endif 1739 1740 err = pci_request_regions(pci, "ICH HD audio"); 1741 if (err < 0) 1742 return err; 1743 chip->region_requested = 1; 1744 1745 bus->addr = pci_resource_start(pci, 0); 1746 bus->remap_addr = pci_ioremap_bar(pci, 0); 1747 if (bus->remap_addr == NULL) { 1748 dev_err(card->dev, "ioremap error\n"); 1749 return -ENXIO; 1750 } 1751 1752 if (chip->driver_type == AZX_DRIVER_SKL) 1753 snd_hdac_bus_parse_capabilities(bus); 1754 1755 /* 1756 * Some Intel CPUs has always running timer (ART) feature and 1757 * controller may have Global time sync reporting capability, so 1758 * check both of these before declaring synchronized time reporting 1759 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 1760 */ 1761 chip->gts_present = false; 1762 1763 #ifdef CONFIG_X86 1764 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART)) 1765 chip->gts_present = true; 1766 #endif 1767 1768 if (chip->msi) { 1769 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1770 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1771 pci->no_64bit_msi = true; 1772 } 1773 if (pci_enable_msi(pci) < 0) 1774 chip->msi = 0; 1775 } 1776 1777 pci_set_master(pci); 1778 synchronize_irq(bus->irq); 1779 1780 gcap = azx_readw(chip, GCAP); 1781 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1782 1783 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1784 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1785 dma_bits = 40; 1786 1787 /* disable SB600 64bit support for safety */ 1788 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1789 struct pci_dev *p_smbus; 1790 dma_bits = 40; 1791 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1792 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1793 NULL); 1794 if (p_smbus) { 1795 if (p_smbus->revision < 0x30) 1796 gcap &= ~AZX_GCAP_64OK; 1797 pci_dev_put(p_smbus); 1798 } 1799 } 1800 1801 /* NVidia hardware normally only supports up to 40 bits of DMA */ 1802 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) 1803 dma_bits = 40; 1804 1805 /* disable 64bit DMA address on some devices */ 1806 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1807 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1808 gcap &= ~AZX_GCAP_64OK; 1809 } 1810 1811 /* disable buffer size rounding to 128-byte multiples if supported */ 1812 if (align_buffer_size >= 0) 1813 chip->align_buffer_size = !!align_buffer_size; 1814 else { 1815 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1816 chip->align_buffer_size = 0; 1817 else 1818 chip->align_buffer_size = 1; 1819 } 1820 1821 /* allow 64bit DMA address if supported by H/W */ 1822 if (!(gcap & AZX_GCAP_64OK)) 1823 dma_bits = 32; 1824 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) { 1825 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits)); 1826 } else { 1827 dma_set_mask(&pci->dev, DMA_BIT_MASK(32)); 1828 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32)); 1829 } 1830 1831 /* read number of streams from GCAP register instead of using 1832 * hardcoded value 1833 */ 1834 chip->capture_streams = (gcap >> 8) & 0x0f; 1835 chip->playback_streams = (gcap >> 12) & 0x0f; 1836 if (!chip->playback_streams && !chip->capture_streams) { 1837 /* gcap didn't give any info, switching to old method */ 1838 1839 switch (chip->driver_type) { 1840 case AZX_DRIVER_ULI: 1841 chip->playback_streams = ULI_NUM_PLAYBACK; 1842 chip->capture_streams = ULI_NUM_CAPTURE; 1843 break; 1844 case AZX_DRIVER_ATIHDMI: 1845 case AZX_DRIVER_ATIHDMI_NS: 1846 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1847 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1848 break; 1849 case AZX_DRIVER_GENERIC: 1850 default: 1851 chip->playback_streams = ICH6_NUM_PLAYBACK; 1852 chip->capture_streams = ICH6_NUM_CAPTURE; 1853 break; 1854 } 1855 } 1856 chip->capture_index_offset = 0; 1857 chip->playback_index_offset = chip->capture_streams; 1858 chip->num_streams = chip->playback_streams + chip->capture_streams; 1859 1860 /* sanity check for the SDxCTL.STRM field overflow */ 1861 if (chip->num_streams > 15 && 1862 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) { 1863 dev_warn(chip->card->dev, "number of I/O streams is %d, " 1864 "forcing separate stream tags", chip->num_streams); 1865 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG; 1866 } 1867 1868 /* initialize streams */ 1869 err = azx_init_streams(chip); 1870 if (err < 0) 1871 return err; 1872 1873 err = azx_alloc_stream_pages(chip); 1874 if (err < 0) 1875 return err; 1876 1877 /* initialize chip */ 1878 azx_init_pci(chip); 1879 1880 snd_hdac_i915_set_bclk(bus); 1881 1882 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 1883 1884 /* codec detection */ 1885 if (!azx_bus(chip)->codec_mask) { 1886 dev_err(card->dev, "no codecs found!\n"); 1887 return -ENODEV; 1888 } 1889 1890 if (azx_acquire_irq(chip, 0) < 0) 1891 return -EBUSY; 1892 1893 strcpy(card->driver, "HDA-Intel"); 1894 strlcpy(card->shortname, driver_short_names[chip->driver_type], 1895 sizeof(card->shortname)); 1896 snprintf(card->longname, sizeof(card->longname), 1897 "%s at 0x%lx irq %i", 1898 card->shortname, bus->addr, bus->irq); 1899 1900 return 0; 1901 } 1902 1903 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1904 /* callback from request_firmware_nowait() */ 1905 static void azx_firmware_cb(const struct firmware *fw, void *context) 1906 { 1907 struct snd_card *card = context; 1908 struct azx *chip = card->private_data; 1909 struct pci_dev *pci = chip->pci; 1910 1911 if (!fw) { 1912 dev_err(card->dev, "Cannot load firmware, aborting\n"); 1913 goto error; 1914 } 1915 1916 chip->fw = fw; 1917 if (!chip->disabled) { 1918 /* continue probing */ 1919 if (azx_probe_continue(chip)) 1920 goto error; 1921 } 1922 return; /* OK */ 1923 1924 error: 1925 snd_card_free(card); 1926 pci_set_drvdata(pci, NULL); 1927 } 1928 #endif 1929 1930 /* 1931 * HDA controller ops. 1932 */ 1933 1934 /* PCI register access. */ 1935 static void pci_azx_writel(u32 value, u32 __iomem *addr) 1936 { 1937 writel(value, addr); 1938 } 1939 1940 static u32 pci_azx_readl(u32 __iomem *addr) 1941 { 1942 return readl(addr); 1943 } 1944 1945 static void pci_azx_writew(u16 value, u16 __iomem *addr) 1946 { 1947 writew(value, addr); 1948 } 1949 1950 static u16 pci_azx_readw(u16 __iomem *addr) 1951 { 1952 return readw(addr); 1953 } 1954 1955 static void pci_azx_writeb(u8 value, u8 __iomem *addr) 1956 { 1957 writeb(value, addr); 1958 } 1959 1960 static u8 pci_azx_readb(u8 __iomem *addr) 1961 { 1962 return readb(addr); 1963 } 1964 1965 static int disable_msi_reset_irq(struct azx *chip) 1966 { 1967 struct hdac_bus *bus = azx_bus(chip); 1968 int err; 1969 1970 free_irq(bus->irq, chip); 1971 bus->irq = -1; 1972 pci_disable_msi(chip->pci); 1973 chip->msi = 0; 1974 err = azx_acquire_irq(chip, 1); 1975 if (err < 0) 1976 return err; 1977 1978 return 0; 1979 } 1980 1981 /* DMA page allocation helpers. */ 1982 static int dma_alloc_pages(struct hdac_bus *bus, 1983 int type, 1984 size_t size, 1985 struct snd_dma_buffer *buf) 1986 { 1987 struct azx *chip = bus_to_azx(bus); 1988 1989 if (!azx_snoop(chip) && type == SNDRV_DMA_TYPE_DEV) 1990 type = SNDRV_DMA_TYPE_DEV_UC; 1991 return snd_dma_alloc_pages(type, bus->dev, size, buf); 1992 } 1993 1994 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf) 1995 { 1996 snd_dma_free_pages(buf); 1997 } 1998 1999 static void pcm_mmap_prepare(struct snd_pcm_substream *substream, 2000 struct vm_area_struct *area) 2001 { 2002 #ifdef CONFIG_X86 2003 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2004 struct azx *chip = apcm->chip; 2005 if (chip->uc_buffer) 2006 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); 2007 #endif 2008 } 2009 2010 static const struct hdac_io_ops pci_hda_io_ops = { 2011 .reg_writel = pci_azx_writel, 2012 .reg_readl = pci_azx_readl, 2013 .reg_writew = pci_azx_writew, 2014 .reg_readw = pci_azx_readw, 2015 .reg_writeb = pci_azx_writeb, 2016 .reg_readb = pci_azx_readb, 2017 .dma_alloc_pages = dma_alloc_pages, 2018 .dma_free_pages = dma_free_pages, 2019 }; 2020 2021 static const struct hda_controller_ops pci_hda_ops = { 2022 .disable_msi_reset_irq = disable_msi_reset_irq, 2023 .pcm_mmap_prepare = pcm_mmap_prepare, 2024 .position_check = azx_position_check, 2025 }; 2026 2027 static int azx_probe(struct pci_dev *pci, 2028 const struct pci_device_id *pci_id) 2029 { 2030 static int dev; 2031 struct snd_card *card; 2032 struct hda_intel *hda; 2033 struct azx *chip; 2034 bool schedule_probe; 2035 int err; 2036 2037 if (dev >= SNDRV_CARDS) 2038 return -ENODEV; 2039 if (!enable[dev]) { 2040 dev++; 2041 return -ENOENT; 2042 } 2043 2044 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2045 0, &card); 2046 if (err < 0) { 2047 dev_err(&pci->dev, "Error creating card!\n"); 2048 return err; 2049 } 2050 2051 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2052 if (err < 0) 2053 goto out_free; 2054 card->private_data = chip; 2055 hda = container_of(chip, struct hda_intel, chip); 2056 2057 pci_set_drvdata(pci, card); 2058 2059 err = register_vga_switcheroo(chip); 2060 if (err < 0) { 2061 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 2062 goto out_free; 2063 } 2064 2065 if (check_hdmi_disabled(pci)) { 2066 dev_info(card->dev, "VGA controller is disabled\n"); 2067 dev_info(card->dev, "Delaying initialization\n"); 2068 chip->disabled = true; 2069 } 2070 2071 schedule_probe = !chip->disabled; 2072 2073 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2074 if (patch[dev] && *patch[dev]) { 2075 dev_info(card->dev, "Applying patch firmware '%s'\n", 2076 patch[dev]); 2077 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 2078 &pci->dev, GFP_KERNEL, card, 2079 azx_firmware_cb); 2080 if (err < 0) 2081 goto out_free; 2082 schedule_probe = false; /* continued in azx_firmware_cb() */ 2083 } 2084 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 2085 2086 #ifndef CONFIG_SND_HDA_I915 2087 if (CONTROLLER_IN_GPU(pci)) 2088 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); 2089 #endif 2090 2091 if (schedule_probe) 2092 schedule_work(&hda->probe_work); 2093 2094 dev++; 2095 if (chip->disabled) 2096 complete_all(&hda->probe_wait); 2097 return 0; 2098 2099 out_free: 2100 snd_card_free(card); 2101 return err; 2102 } 2103 2104 #ifdef CONFIG_PM 2105 /* On some boards setting power_save to a non 0 value leads to clicking / 2106 * popping sounds when ever we enter/leave powersaving mode. Ideally we would 2107 * figure out how to avoid these sounds, but that is not always feasible. 2108 * So we keep a list of devices where we disable powersaving as its known 2109 * to causes problems on these devices. 2110 */ 2111 static struct snd_pci_quirk power_save_blacklist[] = { 2112 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2113 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0), 2114 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2115 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0), 2116 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2117 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0), 2118 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2119 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0), 2120 /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */ 2121 SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0), 2122 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2123 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0), 2124 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2125 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ 2126 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0), 2127 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2128 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0), 2129 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */ 2130 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0), 2131 /* https://bugs.launchpad.net/bugs/1821663 */ 2132 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0), 2133 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */ 2134 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), 2135 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ 2136 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), 2137 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ 2138 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), 2139 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ 2140 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0), 2141 /* https://bugs.launchpad.net/bugs/1821663 */ 2142 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0), 2143 {} 2144 }; 2145 #endif /* CONFIG_PM */ 2146 2147 static void set_default_power_save(struct azx *chip) 2148 { 2149 int val = power_save; 2150 2151 #ifdef CONFIG_PM 2152 if (pm_blacklist) { 2153 const struct snd_pci_quirk *q; 2154 2155 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist); 2156 if (q && val) { 2157 dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n", 2158 q->subvendor, q->subdevice); 2159 val = 0; 2160 } 2161 } 2162 #endif /* CONFIG_PM */ 2163 snd_hda_set_power_save(&chip->bus, val * 1000); 2164 } 2165 2166 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 2167 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 2168 [AZX_DRIVER_NVIDIA] = 8, 2169 [AZX_DRIVER_TERA] = 1, 2170 }; 2171 2172 static int azx_probe_continue(struct azx *chip) 2173 { 2174 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2175 struct hdac_bus *bus = azx_bus(chip); 2176 struct pci_dev *pci = chip->pci; 2177 int dev = chip->dev_index; 2178 int err; 2179 2180 to_hda_bus(bus)->bus_probing = 1; 2181 hda->probe_continued = 1; 2182 2183 /* bind with i915 if needed */ 2184 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) { 2185 err = snd_hdac_i915_init(bus); 2186 if (err < 0) { 2187 /* if the controller is bound only with HDMI/DP 2188 * (for HSW and BDW), we need to abort the probe; 2189 * for other chips, still continue probing as other 2190 * codecs can be on the same link. 2191 */ 2192 if (CONTROLLER_IN_GPU(pci)) { 2193 dev_err(chip->card->dev, 2194 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); 2195 goto out_free; 2196 } else { 2197 /* don't bother any longer */ 2198 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT; 2199 } 2200 } 2201 2202 /* HSW/BDW controllers need this power */ 2203 if (CONTROLLER_IN_GPU(pci)) 2204 hda->need_i915_power = 1; 2205 } 2206 2207 /* Request display power well for the HDA controller or codec. For 2208 * Haswell/Broadwell, both the display HDA controller and codec need 2209 * this power. For other platforms, like Baytrail/Braswell, only the 2210 * display codec needs the power and it can be released after probe. 2211 */ 2212 display_power(chip, true); 2213 2214 err = azx_first_init(chip); 2215 if (err < 0) 2216 goto out_free; 2217 2218 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2219 chip->beep_mode = beep_mode[dev]; 2220 #endif 2221 2222 /* create codec instances */ 2223 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2224 if (err < 0) 2225 goto out_free; 2226 2227 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2228 if (chip->fw) { 2229 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2230 chip->fw->data); 2231 if (err < 0) 2232 goto out_free; 2233 #ifndef CONFIG_PM 2234 release_firmware(chip->fw); /* no longer needed */ 2235 chip->fw = NULL; 2236 #endif 2237 } 2238 #endif 2239 if ((probe_only[dev] & 1) == 0) { 2240 err = azx_codec_configure(chip); 2241 if (err < 0) 2242 goto out_free; 2243 } 2244 2245 err = snd_card_register(chip->card); 2246 if (err < 0) 2247 goto out_free; 2248 2249 setup_vga_switcheroo_runtime_pm(chip); 2250 2251 chip->running = 1; 2252 azx_add_card_list(chip); 2253 2254 set_default_power_save(chip); 2255 2256 if (azx_has_pm_runtime(chip)) 2257 pm_runtime_put_autosuspend(&pci->dev); 2258 2259 out_free: 2260 if (err < 0 || !hda->need_i915_power) 2261 display_power(chip, false); 2262 if (err < 0) 2263 hda->init_failed = 1; 2264 complete_all(&hda->probe_wait); 2265 to_hda_bus(bus)->bus_probing = 0; 2266 return err; 2267 } 2268 2269 static void azx_remove(struct pci_dev *pci) 2270 { 2271 struct snd_card *card = pci_get_drvdata(pci); 2272 struct azx *chip; 2273 struct hda_intel *hda; 2274 2275 if (card) { 2276 /* cancel the pending probing work */ 2277 chip = card->private_data; 2278 hda = container_of(chip, struct hda_intel, chip); 2279 /* FIXME: below is an ugly workaround. 2280 * Both device_release_driver() and driver_probe_device() 2281 * take *both* the device's and its parent's lock before 2282 * calling the remove() and probe() callbacks. The codec 2283 * probe takes the locks of both the codec itself and its 2284 * parent, i.e. the PCI controller dev. Meanwhile, when 2285 * the PCI controller is unbound, it takes its lock, too 2286 * ==> ouch, a deadlock! 2287 * As a workaround, we unlock temporarily here the controller 2288 * device during cancel_work_sync() call. 2289 */ 2290 device_unlock(&pci->dev); 2291 cancel_work_sync(&hda->probe_work); 2292 device_lock(&pci->dev); 2293 2294 snd_card_free(card); 2295 } 2296 } 2297 2298 static void azx_shutdown(struct pci_dev *pci) 2299 { 2300 struct snd_card *card = pci_get_drvdata(pci); 2301 struct azx *chip; 2302 2303 if (!card) 2304 return; 2305 chip = card->private_data; 2306 if (chip && chip->running) 2307 azx_stop_chip(chip); 2308 } 2309 2310 /* PCI IDs */ 2311 static const struct pci_device_id azx_ids[] = { 2312 /* CPT */ 2313 { PCI_DEVICE(0x8086, 0x1c20), 2314 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2315 /* PBG */ 2316 { PCI_DEVICE(0x8086, 0x1d20), 2317 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2318 /* Panther Point */ 2319 { PCI_DEVICE(0x8086, 0x1e20), 2320 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2321 /* Lynx Point */ 2322 { PCI_DEVICE(0x8086, 0x8c20), 2323 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2324 /* 9 Series */ 2325 { PCI_DEVICE(0x8086, 0x8ca0), 2326 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2327 /* Wellsburg */ 2328 { PCI_DEVICE(0x8086, 0x8d20), 2329 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2330 { PCI_DEVICE(0x8086, 0x8d21), 2331 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2332 /* Lewisburg */ 2333 { PCI_DEVICE(0x8086, 0xa1f0), 2334 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2335 { PCI_DEVICE(0x8086, 0xa270), 2336 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2337 /* Lynx Point-LP */ 2338 { PCI_DEVICE(0x8086, 0x9c20), 2339 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2340 /* Lynx Point-LP */ 2341 { PCI_DEVICE(0x8086, 0x9c21), 2342 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2343 /* Wildcat Point-LP */ 2344 { PCI_DEVICE(0x8086, 0x9ca0), 2345 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2346 /* Sunrise Point */ 2347 { PCI_DEVICE(0x8086, 0xa170), 2348 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2349 /* Sunrise Point-LP */ 2350 { PCI_DEVICE(0x8086, 0x9d70), 2351 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2352 /* Kabylake */ 2353 { PCI_DEVICE(0x8086, 0xa171), 2354 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2355 /* Kabylake-LP */ 2356 { PCI_DEVICE(0x8086, 0x9d71), 2357 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2358 /* Kabylake-H */ 2359 { PCI_DEVICE(0x8086, 0xa2f0), 2360 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2361 /* Coffelake */ 2362 { PCI_DEVICE(0x8086, 0xa348), 2363 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2364 /* Cannonlake */ 2365 { PCI_DEVICE(0x8086, 0x9dc8), 2366 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2367 /* CometLake-LP */ 2368 { PCI_DEVICE(0x8086, 0x02C8), 2369 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2370 /* CometLake-H */ 2371 { PCI_DEVICE(0x8086, 0x06C8), 2372 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2373 /* Icelake */ 2374 { PCI_DEVICE(0x8086, 0x34c8), 2375 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2376 /* Elkhart Lake */ 2377 { PCI_DEVICE(0x8086, 0x4b55), 2378 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2379 /* Broxton-P(Apollolake) */ 2380 { PCI_DEVICE(0x8086, 0x5a98), 2381 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2382 /* Broxton-T */ 2383 { PCI_DEVICE(0x8086, 0x1a98), 2384 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2385 /* Gemini-Lake */ 2386 { PCI_DEVICE(0x8086, 0x3198), 2387 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2388 /* Haswell */ 2389 { PCI_DEVICE(0x8086, 0x0a0c), 2390 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2391 { PCI_DEVICE(0x8086, 0x0c0c), 2392 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2393 { PCI_DEVICE(0x8086, 0x0d0c), 2394 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2395 /* Broadwell */ 2396 { PCI_DEVICE(0x8086, 0x160c), 2397 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 2398 /* 5 Series/3400 */ 2399 { PCI_DEVICE(0x8086, 0x3b56), 2400 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2401 /* Poulsbo */ 2402 { PCI_DEVICE(0x8086, 0x811b), 2403 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2404 /* Oaktrail */ 2405 { PCI_DEVICE(0x8086, 0x080a), 2406 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2407 /* BayTrail */ 2408 { PCI_DEVICE(0x8086, 0x0f04), 2409 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL }, 2410 /* Braswell */ 2411 { PCI_DEVICE(0x8086, 0x2284), 2412 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL }, 2413 /* ICH6 */ 2414 { PCI_DEVICE(0x8086, 0x2668), 2415 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2416 /* ICH7 */ 2417 { PCI_DEVICE(0x8086, 0x27d8), 2418 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2419 /* ESB2 */ 2420 { PCI_DEVICE(0x8086, 0x269a), 2421 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2422 /* ICH8 */ 2423 { PCI_DEVICE(0x8086, 0x284b), 2424 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2425 /* ICH9 */ 2426 { PCI_DEVICE(0x8086, 0x293e), 2427 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2428 /* ICH9 */ 2429 { PCI_DEVICE(0x8086, 0x293f), 2430 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2431 /* ICH10 */ 2432 { PCI_DEVICE(0x8086, 0x3a3e), 2433 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2434 /* ICH10 */ 2435 { PCI_DEVICE(0x8086, 0x3a6e), 2436 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2437 /* Generic Intel */ 2438 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2439 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2440 .class_mask = 0xffffff, 2441 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2442 /* ATI SB 450/600/700/800/900 */ 2443 { PCI_DEVICE(0x1002, 0x437b), 2444 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2445 { PCI_DEVICE(0x1002, 0x4383), 2446 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2447 /* AMD Hudson */ 2448 { PCI_DEVICE(0x1022, 0x780d), 2449 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2450 /* AMD Stoney */ 2451 { PCI_DEVICE(0x1022, 0x157a), 2452 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | 2453 AZX_DCAPS_PM_RUNTIME }, 2454 /* AMD Raven */ 2455 { PCI_DEVICE(0x1022, 0x15e3), 2456 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | 2457 AZX_DCAPS_PM_RUNTIME }, 2458 /* ATI HDMI */ 2459 { PCI_DEVICE(0x1002, 0x0002), 2460 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2461 { PCI_DEVICE(0x1002, 0x1308), 2462 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2463 { PCI_DEVICE(0x1002, 0x157a), 2464 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2465 { PCI_DEVICE(0x1002, 0x15b3), 2466 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2467 { PCI_DEVICE(0x1002, 0x793b), 2468 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2469 { PCI_DEVICE(0x1002, 0x7919), 2470 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2471 { PCI_DEVICE(0x1002, 0x960f), 2472 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2473 { PCI_DEVICE(0x1002, 0x970f), 2474 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2475 { PCI_DEVICE(0x1002, 0x9840), 2476 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2477 { PCI_DEVICE(0x1002, 0xaa00), 2478 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2479 { PCI_DEVICE(0x1002, 0xaa08), 2480 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2481 { PCI_DEVICE(0x1002, 0xaa10), 2482 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2483 { PCI_DEVICE(0x1002, 0xaa18), 2484 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2485 { PCI_DEVICE(0x1002, 0xaa20), 2486 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2487 { PCI_DEVICE(0x1002, 0xaa28), 2488 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2489 { PCI_DEVICE(0x1002, 0xaa30), 2490 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2491 { PCI_DEVICE(0x1002, 0xaa38), 2492 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2493 { PCI_DEVICE(0x1002, 0xaa40), 2494 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2495 { PCI_DEVICE(0x1002, 0xaa48), 2496 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2497 { PCI_DEVICE(0x1002, 0xaa50), 2498 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2499 { PCI_DEVICE(0x1002, 0xaa58), 2500 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2501 { PCI_DEVICE(0x1002, 0xaa60), 2502 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2503 { PCI_DEVICE(0x1002, 0xaa68), 2504 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2505 { PCI_DEVICE(0x1002, 0xaa80), 2506 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2507 { PCI_DEVICE(0x1002, 0xaa88), 2508 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2509 { PCI_DEVICE(0x1002, 0xaa90), 2510 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2511 { PCI_DEVICE(0x1002, 0xaa98), 2512 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2513 { PCI_DEVICE(0x1002, 0x9902), 2514 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2515 { PCI_DEVICE(0x1002, 0xaaa0), 2516 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2517 { PCI_DEVICE(0x1002, 0xaaa8), 2518 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2519 { PCI_DEVICE(0x1002, 0xaab0), 2520 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2521 { PCI_DEVICE(0x1002, 0xaac0), 2522 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2523 { PCI_DEVICE(0x1002, 0xaac8), 2524 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2525 { PCI_DEVICE(0x1002, 0xaad8), 2526 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2527 { PCI_DEVICE(0x1002, 0xaae8), 2528 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2529 { PCI_DEVICE(0x1002, 0xaae0), 2530 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2531 { PCI_DEVICE(0x1002, 0xaaf0), 2532 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2533 /* VIA VT8251/VT8237A */ 2534 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2535 /* VIA GFX VT7122/VX900 */ 2536 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2537 /* VIA GFX VT6122/VX11 */ 2538 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2539 /* SIS966 */ 2540 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2541 /* ULI M5461 */ 2542 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2543 /* NVIDIA MCP */ 2544 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2545 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2546 .class_mask = 0xffffff, 2547 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2548 /* Teradici */ 2549 { PCI_DEVICE(0x6549, 0x1200), 2550 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2551 { PCI_DEVICE(0x6549, 0x2200), 2552 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2553 /* Creative X-Fi (CA0110-IBG) */ 2554 /* CTHDA chips */ 2555 { PCI_DEVICE(0x1102, 0x0010), 2556 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2557 { PCI_DEVICE(0x1102, 0x0012), 2558 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2559 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2560 /* the following entry conflicts with snd-ctxfi driver, 2561 * as ctxfi driver mutates from HD-audio to native mode with 2562 * a special command sequence. 2563 */ 2564 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2565 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2566 .class_mask = 0xffffff, 2567 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2568 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2569 #else 2570 /* this entry seems still valid -- i.e. without emu20kx chip */ 2571 { PCI_DEVICE(0x1102, 0x0009), 2572 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2573 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2574 #endif 2575 /* CM8888 */ 2576 { PCI_DEVICE(0x13f6, 0x5011), 2577 .driver_data = AZX_DRIVER_CMEDIA | 2578 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2579 /* Vortex86MX */ 2580 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2581 /* VMware HDAudio */ 2582 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2583 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2584 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2585 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2586 .class_mask = 0xffffff, 2587 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2588 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2589 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2590 .class_mask = 0xffffff, 2591 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2592 { 0, } 2593 }; 2594 MODULE_DEVICE_TABLE(pci, azx_ids); 2595 2596 /* pci_driver definition */ 2597 static struct pci_driver azx_driver = { 2598 .name = KBUILD_MODNAME, 2599 .id_table = azx_ids, 2600 .probe = azx_probe, 2601 .remove = azx_remove, 2602 .shutdown = azx_shutdown, 2603 .driver = { 2604 .pm = AZX_PM_OPS, 2605 }, 2606 }; 2607 2608 module_pci_driver(azx_driver); 2609