1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * hda_intel.c - Implementation of primary alsa driver code base 5 * for Intel HD Audio. 6 * 7 * Copyright(c) 2004 Intel Corporation. All rights reserved. 8 * 9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 10 * PeiSen Hou <pshou@realtek.com.tw> 11 * 12 * CONTACTS: 13 * 14 * Matt Jared matt.jared@intel.com 15 * Andy Kopp andy.kopp@intel.com 16 * Dan Kogan dan.d.kogan@intel.com 17 * 18 * CHANGES: 19 * 20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/moduleparam.h> 29 #include <linux/init.h> 30 #include <linux/slab.h> 31 #include <linux/pci.h> 32 #include <linux/mutex.h> 33 #include <linux/io.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/clocksource.h> 36 #include <linux/time.h> 37 #include <linux/completion.h> 38 #include <linux/acpi.h> 39 #include <linux/pgtable.h> 40 41 #ifdef CONFIG_X86 42 /* for snoop control */ 43 #include <asm/set_memory.h> 44 #include <asm/cpufeature.h> 45 #endif 46 #include <sound/core.h> 47 #include <sound/initval.h> 48 #include <sound/hdaudio.h> 49 #include <sound/hda_i915.h> 50 #include <sound/intel-dsp-config.h> 51 #include <linux/vgaarb.h> 52 #include <linux/vga_switcheroo.h> 53 #include <linux/firmware.h> 54 #include <sound/hda_codec.h> 55 #include "hda_controller.h" 56 #include "hda_intel.h" 57 58 #define CREATE_TRACE_POINTS 59 #include "hda_intel_trace.h" 60 61 /* position fix mode */ 62 enum { 63 POS_FIX_AUTO, 64 POS_FIX_LPIB, 65 POS_FIX_POSBUF, 66 POS_FIX_VIACOMBO, 67 POS_FIX_COMBO, 68 POS_FIX_SKL, 69 POS_FIX_FIFO, 70 }; 71 72 /* Defines for ATI HD Audio support in SB450 south bridge */ 73 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 74 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 75 76 /* Defines for Nvidia HDA support */ 77 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 78 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 79 #define NVIDIA_HDA_ISTRM_COH 0x4d 80 #define NVIDIA_HDA_OSTRM_COH 0x4c 81 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 82 83 /* Defines for Intel SCH HDA snoop control */ 84 #define INTEL_HDA_CGCTL 0x48 85 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) 86 #define INTEL_SCH_HDA_DEVC 0x78 87 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 88 89 /* Define VIA HD Audio Device ID*/ 90 #define VIA_HDAC_DEVICE_ID 0x3288 91 92 /* max number of SDs */ 93 /* ICH, ATI and VIA have 4 playback and 4 capture */ 94 #define ICH6_NUM_CAPTURE 4 95 #define ICH6_NUM_PLAYBACK 4 96 97 /* ULI has 6 playback and 5 capture */ 98 #define ULI_NUM_CAPTURE 5 99 #define ULI_NUM_PLAYBACK 6 100 101 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 102 #define ATIHDMI_NUM_CAPTURE 0 103 #define ATIHDMI_NUM_PLAYBACK 8 104 105 /* TERA has 4 playback and 3 capture */ 106 #define TERA_NUM_CAPTURE 3 107 #define TERA_NUM_PLAYBACK 4 108 109 110 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 111 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 112 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 113 static char *model[SNDRV_CARDS]; 114 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 115 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 116 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 117 static int probe_only[SNDRV_CARDS]; 118 static int jackpoll_ms[SNDRV_CARDS]; 119 static int single_cmd = -1; 120 static int enable_msi = -1; 121 #ifdef CONFIG_SND_HDA_PATCH_LOADER 122 static char *patch[SNDRV_CARDS]; 123 #endif 124 #ifdef CONFIG_SND_HDA_INPUT_BEEP 125 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 126 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 127 #endif 128 static bool dmic_detect = 1; 129 130 module_param_array(index, int, NULL, 0444); 131 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 132 module_param_array(id, charp, NULL, 0444); 133 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 134 module_param_array(enable, bool, NULL, 0444); 135 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 136 module_param_array(model, charp, NULL, 0444); 137 MODULE_PARM_DESC(model, "Use the given board model."); 138 module_param_array(position_fix, int, NULL, 0444); 139 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 140 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO)."); 141 module_param_array(bdl_pos_adj, int, NULL, 0644); 142 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 143 module_param_array(probe_mask, int, NULL, 0444); 144 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 145 module_param_array(probe_only, int, NULL, 0444); 146 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 147 module_param_array(jackpoll_ms, int, NULL, 0444); 148 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 149 module_param(single_cmd, bint, 0444); 150 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 151 "(for debugging only)."); 152 module_param(enable_msi, bint, 0444); 153 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 154 #ifdef CONFIG_SND_HDA_PATCH_LOADER 155 module_param_array(patch, charp, NULL, 0444); 156 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 157 #endif 158 #ifdef CONFIG_SND_HDA_INPUT_BEEP 159 module_param_array(beep_mode, bool, NULL, 0444); 160 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 161 "(0=off, 1=on) (default=1)."); 162 #endif 163 module_param(dmic_detect, bool, 0444); 164 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) " 165 "(0=off, 1=on) (default=1); " 166 "deprecated, use snd-intel-dspcfg.dsp_driver option instead"); 167 168 #ifdef CONFIG_PM 169 static int param_set_xint(const char *val, const struct kernel_param *kp); 170 static const struct kernel_param_ops param_ops_xint = { 171 .set = param_set_xint, 172 .get = param_get_int, 173 }; 174 #define param_check_xint param_check_int 175 176 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 177 module_param(power_save, xint, 0644); 178 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 179 "(in second, 0 = disable)."); 180 181 static bool pm_blacklist = true; 182 module_param(pm_blacklist, bool, 0644); 183 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist"); 184 185 /* reset the HD-audio controller in power save mode. 186 * this may give more power-saving, but will take longer time to 187 * wake up. 188 */ 189 static bool power_save_controller = 1; 190 module_param(power_save_controller, bool, 0644); 191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 192 #else 193 #define power_save 0 194 #endif /* CONFIG_PM */ 195 196 static int align_buffer_size = -1; 197 module_param(align_buffer_size, bint, 0644); 198 MODULE_PARM_DESC(align_buffer_size, 199 "Force buffer and period sizes to be multiple of 128 bytes."); 200 201 #ifdef CONFIG_X86 202 static int hda_snoop = -1; 203 module_param_named(snoop, hda_snoop, bint, 0444); 204 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 205 #else 206 #define hda_snoop true 207 #endif 208 209 210 MODULE_LICENSE("GPL"); 211 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 212 "{Intel, ICH6M}," 213 "{Intel, ICH7}," 214 "{Intel, ESB2}," 215 "{Intel, ICH8}," 216 "{Intel, ICH9}," 217 "{Intel, ICH10}," 218 "{Intel, PCH}," 219 "{Intel, CPT}," 220 "{Intel, PPT}," 221 "{Intel, LPT}," 222 "{Intel, LPT_LP}," 223 "{Intel, WPT_LP}," 224 "{Intel, SPT}," 225 "{Intel, SPT_LP}," 226 "{Intel, HPT}," 227 "{Intel, PBG}," 228 "{Intel, SCH}," 229 "{ATI, SB450}," 230 "{ATI, SB600}," 231 "{ATI, RS600}," 232 "{ATI, RS690}," 233 "{ATI, RS780}," 234 "{ATI, R600}," 235 "{ATI, RV630}," 236 "{ATI, RV610}," 237 "{ATI, RV670}," 238 "{ATI, RV635}," 239 "{ATI, RV620}," 240 "{ATI, RV770}," 241 "{VIA, VT8251}," 242 "{VIA, VT8237A}," 243 "{SiS, SIS966}," 244 "{ULI, M5461}}"); 245 MODULE_DESCRIPTION("Intel HDA driver"); 246 247 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 248 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 249 #define SUPPORT_VGA_SWITCHEROO 250 #endif 251 #endif 252 253 254 /* 255 */ 256 257 /* driver types */ 258 enum { 259 AZX_DRIVER_ICH, 260 AZX_DRIVER_PCH, 261 AZX_DRIVER_SCH, 262 AZX_DRIVER_SKL, 263 AZX_DRIVER_HDMI, 264 AZX_DRIVER_ATI, 265 AZX_DRIVER_ATIHDMI, 266 AZX_DRIVER_ATIHDMI_NS, 267 AZX_DRIVER_VIA, 268 AZX_DRIVER_SIS, 269 AZX_DRIVER_ULI, 270 AZX_DRIVER_NVIDIA, 271 AZX_DRIVER_TERA, 272 AZX_DRIVER_CTX, 273 AZX_DRIVER_CTHDA, 274 AZX_DRIVER_CMEDIA, 275 AZX_DRIVER_ZHAOXIN, 276 AZX_DRIVER_GENERIC, 277 AZX_NUM_DRIVERS, /* keep this as last entry */ 278 }; 279 280 #define azx_get_snoop_type(chip) \ 281 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 282 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 283 284 /* quirks for old Intel chipsets */ 285 #define AZX_DCAPS_INTEL_ICH \ 286 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 287 288 /* quirks for Intel PCH */ 289 #define AZX_DCAPS_INTEL_PCH_BASE \ 290 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 291 AZX_DCAPS_SNOOP_TYPE(SCH)) 292 293 /* PCH up to IVB; no runtime PM; bind with i915 gfx */ 294 #define AZX_DCAPS_INTEL_PCH_NOPM \ 295 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 296 297 /* PCH for HSW/BDW; with runtime PM */ 298 /* no i915 binding for this as HSW/BDW has another controller for HDMI */ 299 #define AZX_DCAPS_INTEL_PCH \ 300 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) 301 302 /* HSW HDMI */ 303 #define AZX_DCAPS_INTEL_HASWELL \ 304 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 305 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 306 AZX_DCAPS_SNOOP_TYPE(SCH)) 307 308 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 309 #define AZX_DCAPS_INTEL_BROADWELL \ 310 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 311 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 312 AZX_DCAPS_SNOOP_TYPE(SCH)) 313 314 #define AZX_DCAPS_INTEL_BAYTRAIL \ 315 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 316 317 #define AZX_DCAPS_INTEL_BRASWELL \ 318 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 319 AZX_DCAPS_I915_COMPONENT) 320 321 #define AZX_DCAPS_INTEL_SKYLAKE \ 322 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 323 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT) 324 325 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE 326 327 /* quirks for ATI SB / AMD Hudson */ 328 #define AZX_DCAPS_PRESET_ATI_SB \ 329 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\ 330 AZX_DCAPS_SNOOP_TYPE(ATI)) 331 332 /* quirks for ATI/AMD HDMI */ 333 #define AZX_DCAPS_PRESET_ATI_HDMI \ 334 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\ 335 AZX_DCAPS_NO_MSI64) 336 337 /* quirks for ATI HDMI with snoop off */ 338 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 339 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 340 341 /* quirks for AMD SB */ 342 #define AZX_DCAPS_PRESET_AMD_SB \ 343 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\ 344 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME) 345 346 /* quirks for Nvidia */ 347 #define AZX_DCAPS_PRESET_NVIDIA \ 348 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 349 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 350 351 #define AZX_DCAPS_PRESET_CTHDA \ 352 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 353 AZX_DCAPS_NO_64BIT |\ 354 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 355 356 /* 357 * vga_switcheroo support 358 */ 359 #ifdef SUPPORT_VGA_SWITCHEROO 360 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 361 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power) 362 #else 363 #define use_vga_switcheroo(chip) 0 364 #define needs_eld_notify_link(chip) false 365 #endif 366 367 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \ 368 ((pci)->device == 0x0c0c) || \ 369 ((pci)->device == 0x0d0c) || \ 370 ((pci)->device == 0x160c) || \ 371 ((pci)->device == 0x490d)) 372 373 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98) 374 375 static const char * const driver_short_names[] = { 376 [AZX_DRIVER_ICH] = "HDA Intel", 377 [AZX_DRIVER_PCH] = "HDA Intel PCH", 378 [AZX_DRIVER_SCH] = "HDA Intel MID", 379 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */ 380 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 381 [AZX_DRIVER_ATI] = "HDA ATI SB", 382 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 383 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 384 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 385 [AZX_DRIVER_SIS] = "HDA SIS966", 386 [AZX_DRIVER_ULI] = "HDA ULI M5461", 387 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 388 [AZX_DRIVER_TERA] = "HDA Teradici", 389 [AZX_DRIVER_CTX] = "HDA Creative", 390 [AZX_DRIVER_CTHDA] = "HDA Creative", 391 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 392 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin", 393 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 394 }; 395 396 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 397 static void set_default_power_save(struct azx *chip); 398 399 /* 400 * initialize the PCI registers 401 */ 402 /* update bits in a PCI register byte */ 403 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 404 unsigned char mask, unsigned char val) 405 { 406 unsigned char data; 407 408 pci_read_config_byte(pci, reg, &data); 409 data &= ~mask; 410 data |= (val & mask); 411 pci_write_config_byte(pci, reg, data); 412 } 413 414 static void azx_init_pci(struct azx *chip) 415 { 416 int snoop_type = azx_get_snoop_type(chip); 417 418 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 419 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 420 * Ensuring these bits are 0 clears playback static on some HD Audio 421 * codecs. 422 * The PCI register TCSEL is defined in the Intel manuals. 423 */ 424 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 425 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 426 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 427 } 428 429 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 430 * we need to enable snoop. 431 */ 432 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 433 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 434 azx_snoop(chip)); 435 update_pci_byte(chip->pci, 436 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 437 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 438 } 439 440 /* For NVIDIA HDA, enable snoop */ 441 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 442 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 443 azx_snoop(chip)); 444 update_pci_byte(chip->pci, 445 NVIDIA_HDA_TRANSREG_ADDR, 446 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 447 update_pci_byte(chip->pci, 448 NVIDIA_HDA_ISTRM_COH, 449 0x01, NVIDIA_HDA_ENABLE_COHBIT); 450 update_pci_byte(chip->pci, 451 NVIDIA_HDA_OSTRM_COH, 452 0x01, NVIDIA_HDA_ENABLE_COHBIT); 453 } 454 455 /* Enable SCH/PCH snoop if needed */ 456 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 457 unsigned short snoop; 458 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 459 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 460 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 461 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 462 if (!azx_snoop(chip)) 463 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 464 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 465 pci_read_config_word(chip->pci, 466 INTEL_SCH_HDA_DEVC, &snoop); 467 } 468 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 469 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 470 "Disabled" : "Enabled"); 471 } 472 } 473 474 /* 475 * In BXT-P A0, HD-Audio DMA requests is later than expected, 476 * and makes an audio stream sensitive to system latencies when 477 * 24/32 bits are playing. 478 * Adjusting threshold of DMA fifo to force the DMA request 479 * sooner to improve latency tolerance at the expense of power. 480 */ 481 static void bxt_reduce_dma_latency(struct azx *chip) 482 { 483 u32 val; 484 485 val = azx_readl(chip, VS_EM4L); 486 val &= (0x3 << 20); 487 azx_writel(chip, VS_EM4L, val); 488 } 489 490 /* 491 * ML_LCAP bits: 492 * bit 0: 6 MHz Supported 493 * bit 1: 12 MHz Supported 494 * bit 2: 24 MHz Supported 495 * bit 3: 48 MHz Supported 496 * bit 4: 96 MHz Supported 497 * bit 5: 192 MHz Supported 498 */ 499 static int intel_get_lctl_scf(struct azx *chip) 500 { 501 struct hdac_bus *bus = azx_bus(chip); 502 static const int preferred_bits[] = { 2, 3, 1, 4, 5 }; 503 u32 val, t; 504 int i; 505 506 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); 507 508 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) { 509 t = preferred_bits[i]; 510 if (val & (1 << t)) 511 return t; 512 } 513 514 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz"); 515 return 0; 516 } 517 518 static int intel_ml_lctl_set_power(struct azx *chip, int state) 519 { 520 struct hdac_bus *bus = azx_bus(chip); 521 u32 val; 522 int timeout; 523 524 /* 525 * the codecs are sharing the first link setting by default 526 * If other links are enabled for stream, they need similar fix 527 */ 528 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 529 val &= ~AZX_MLCTL_SPA; 530 val |= state << AZX_MLCTL_SPA_SHIFT; 531 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 532 /* wait for CPA */ 533 timeout = 50; 534 while (timeout) { 535 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) & 536 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT)) 537 return 0; 538 timeout--; 539 udelay(10); 540 } 541 542 return -1; 543 } 544 545 static void intel_init_lctl(struct azx *chip) 546 { 547 struct hdac_bus *bus = azx_bus(chip); 548 u32 val; 549 int ret; 550 551 /* 0. check lctl register value is correct or not */ 552 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 553 /* if SCF is already set, let's use it */ 554 if ((val & ML_LCTL_SCF_MASK) != 0) 555 return; 556 557 /* 558 * Before operating on SPA, CPA must match SPA. 559 * Any deviation may result in undefined behavior. 560 */ 561 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) != 562 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT)) 563 return; 564 565 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */ 566 ret = intel_ml_lctl_set_power(chip, 0); 567 udelay(100); 568 if (ret) 569 goto set_spa; 570 571 /* 2. update SCF to select a properly audio clock*/ 572 val &= ~ML_LCTL_SCF_MASK; 573 val |= intel_get_lctl_scf(chip); 574 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 575 576 set_spa: 577 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */ 578 intel_ml_lctl_set_power(chip, 1); 579 udelay(100); 580 } 581 582 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 583 { 584 struct hdac_bus *bus = azx_bus(chip); 585 struct pci_dev *pci = chip->pci; 586 u32 val; 587 588 snd_hdac_set_codec_wakeup(bus, true); 589 if (chip->driver_type == AZX_DRIVER_SKL) { 590 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 591 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; 592 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 593 } 594 azx_init_chip(chip, full_reset); 595 if (chip->driver_type == AZX_DRIVER_SKL) { 596 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 597 val = val | INTEL_HDA_CGCTL_MISCBDCGE; 598 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 599 } 600 601 snd_hdac_set_codec_wakeup(bus, false); 602 603 /* reduce dma latency to avoid noise */ 604 if (IS_BXT(pci)) 605 bxt_reduce_dma_latency(chip); 606 607 if (bus->mlcap != NULL) 608 intel_init_lctl(chip); 609 } 610 611 /* calculate runtime delay from LPIB */ 612 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 613 unsigned int pos) 614 { 615 struct snd_pcm_substream *substream = azx_dev->core.substream; 616 int stream = substream->stream; 617 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 618 int delay; 619 620 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 621 delay = pos - lpib_pos; 622 else 623 delay = lpib_pos - pos; 624 if (delay < 0) { 625 if (delay >= azx_dev->core.delay_negative_threshold) 626 delay = 0; 627 else 628 delay += azx_dev->core.bufsize; 629 } 630 631 if (delay >= azx_dev->core.period_bytes) { 632 dev_info(chip->card->dev, 633 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 634 delay, azx_dev->core.period_bytes); 635 delay = 0; 636 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 637 chip->get_delay[stream] = NULL; 638 } 639 640 return bytes_to_frames(substream->runtime, delay); 641 } 642 643 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 644 645 /* called from IRQ */ 646 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 647 { 648 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 649 int ok; 650 651 ok = azx_position_ok(chip, azx_dev); 652 if (ok == 1) { 653 azx_dev->irq_pending = 0; 654 return ok; 655 } else if (ok == 0) { 656 /* bogus IRQ, process it later */ 657 azx_dev->irq_pending = 1; 658 schedule_work(&hda->irq_pending_work); 659 } 660 return 0; 661 } 662 663 #define display_power(chip, enable) \ 664 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable) 665 666 /* 667 * Check whether the current DMA position is acceptable for updating 668 * periods. Returns non-zero if it's OK. 669 * 670 * Many HD-audio controllers appear pretty inaccurate about 671 * the update-IRQ timing. The IRQ is issued before actually the 672 * data is processed. So, we need to process it afterwords in a 673 * workqueue. 674 */ 675 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 676 { 677 struct snd_pcm_substream *substream = azx_dev->core.substream; 678 int stream = substream->stream; 679 u32 wallclk; 680 unsigned int pos; 681 682 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 683 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 684 return -1; /* bogus (too early) interrupt */ 685 686 if (chip->get_position[stream]) 687 pos = chip->get_position[stream](chip, azx_dev); 688 else { /* use the position buffer as default */ 689 pos = azx_get_pos_posbuf(chip, azx_dev); 690 if (!pos || pos == (u32)-1) { 691 dev_info(chip->card->dev, 692 "Invalid position buffer, using LPIB read method instead.\n"); 693 chip->get_position[stream] = azx_get_pos_lpib; 694 if (chip->get_position[0] == azx_get_pos_lpib && 695 chip->get_position[1] == azx_get_pos_lpib) 696 azx_bus(chip)->use_posbuf = false; 697 pos = azx_get_pos_lpib(chip, azx_dev); 698 chip->get_delay[stream] = NULL; 699 } else { 700 chip->get_position[stream] = azx_get_pos_posbuf; 701 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 702 chip->get_delay[stream] = azx_get_delay_from_lpib; 703 } 704 } 705 706 if (pos >= azx_dev->core.bufsize) 707 pos = 0; 708 709 if (WARN_ONCE(!azx_dev->core.period_bytes, 710 "hda-intel: zero azx_dev->period_bytes")) 711 return -1; /* this shouldn't happen! */ 712 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 713 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 714 /* NG - it's below the first next period boundary */ 715 return chip->bdl_pos_adj ? 0 : -1; 716 azx_dev->core.start_wallclk += wallclk; 717 return 1; /* OK, it's fine */ 718 } 719 720 /* 721 * The work for pending PCM period updates. 722 */ 723 static void azx_irq_pending_work(struct work_struct *work) 724 { 725 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 726 struct azx *chip = &hda->chip; 727 struct hdac_bus *bus = azx_bus(chip); 728 struct hdac_stream *s; 729 int pending, ok; 730 731 if (!hda->irq_pending_warned) { 732 dev_info(chip->card->dev, 733 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 734 chip->card->number); 735 hda->irq_pending_warned = 1; 736 } 737 738 for (;;) { 739 pending = 0; 740 spin_lock_irq(&bus->reg_lock); 741 list_for_each_entry(s, &bus->stream_list, list) { 742 struct azx_dev *azx_dev = stream_to_azx_dev(s); 743 if (!azx_dev->irq_pending || 744 !s->substream || 745 !s->running) 746 continue; 747 ok = azx_position_ok(chip, azx_dev); 748 if (ok > 0) { 749 azx_dev->irq_pending = 0; 750 spin_unlock(&bus->reg_lock); 751 snd_pcm_period_elapsed(s->substream); 752 spin_lock(&bus->reg_lock); 753 } else if (ok < 0) { 754 pending = 0; /* too early */ 755 } else 756 pending++; 757 } 758 spin_unlock_irq(&bus->reg_lock); 759 if (!pending) 760 return; 761 msleep(1); 762 } 763 } 764 765 /* clear irq_pending flags and assure no on-going workq */ 766 static void azx_clear_irq_pending(struct azx *chip) 767 { 768 struct hdac_bus *bus = azx_bus(chip); 769 struct hdac_stream *s; 770 771 spin_lock_irq(&bus->reg_lock); 772 list_for_each_entry(s, &bus->stream_list, list) { 773 struct azx_dev *azx_dev = stream_to_azx_dev(s); 774 azx_dev->irq_pending = 0; 775 } 776 spin_unlock_irq(&bus->reg_lock); 777 } 778 779 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 780 { 781 struct hdac_bus *bus = azx_bus(chip); 782 783 if (request_irq(chip->pci->irq, azx_interrupt, 784 chip->msi ? 0 : IRQF_SHARED, 785 chip->card->irq_descr, chip)) { 786 dev_err(chip->card->dev, 787 "unable to grab IRQ %d, disabling device\n", 788 chip->pci->irq); 789 if (do_disconnect) 790 snd_card_disconnect(chip->card); 791 return -1; 792 } 793 bus->irq = chip->pci->irq; 794 chip->card->sync_irq = bus->irq; 795 pci_intx(chip->pci, !chip->msi); 796 return 0; 797 } 798 799 /* get the current DMA position with correction on VIA chips */ 800 static unsigned int azx_via_get_position(struct azx *chip, 801 struct azx_dev *azx_dev) 802 { 803 unsigned int link_pos, mini_pos, bound_pos; 804 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 805 unsigned int fifo_size; 806 807 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 808 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 809 /* Playback, no problem using link position */ 810 return link_pos; 811 } 812 813 /* Capture */ 814 /* For new chipset, 815 * use mod to get the DMA position just like old chipset 816 */ 817 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 818 mod_dma_pos %= azx_dev->core.period_bytes; 819 820 fifo_size = azx_stream(azx_dev)->fifo_size - 1; 821 822 if (azx_dev->insufficient) { 823 /* Link position never gather than FIFO size */ 824 if (link_pos <= fifo_size) 825 return 0; 826 827 azx_dev->insufficient = 0; 828 } 829 830 if (link_pos <= fifo_size) 831 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 832 else 833 mini_pos = link_pos - fifo_size; 834 835 /* Find nearest previous boudary */ 836 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 837 mod_link_pos = link_pos % azx_dev->core.period_bytes; 838 if (mod_link_pos >= fifo_size) 839 bound_pos = link_pos - mod_link_pos; 840 else if (mod_dma_pos >= mod_mini_pos) 841 bound_pos = mini_pos - mod_mini_pos; 842 else { 843 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 844 if (bound_pos >= azx_dev->core.bufsize) 845 bound_pos = 0; 846 } 847 848 /* Calculate real DMA position we want */ 849 return bound_pos + mod_dma_pos; 850 } 851 852 #define AMD_FIFO_SIZE 32 853 854 /* get the current DMA position with FIFO size correction */ 855 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev) 856 { 857 struct snd_pcm_substream *substream = azx_dev->core.substream; 858 struct snd_pcm_runtime *runtime = substream->runtime; 859 unsigned int pos, delay; 860 861 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 862 if (!runtime) 863 return pos; 864 865 runtime->delay = AMD_FIFO_SIZE; 866 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE); 867 if (azx_dev->insufficient) { 868 if (pos < delay) { 869 delay = pos; 870 runtime->delay = bytes_to_frames(runtime, pos); 871 } else { 872 azx_dev->insufficient = 0; 873 } 874 } 875 876 /* correct the DMA position for capture stream */ 877 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 878 if (pos < delay) 879 pos += azx_dev->core.bufsize; 880 pos -= delay; 881 } 882 883 return pos; 884 } 885 886 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev, 887 unsigned int pos) 888 { 889 struct snd_pcm_substream *substream = azx_dev->core.substream; 890 891 /* just read back the calculated value in the above */ 892 return substream->runtime->delay; 893 } 894 895 static unsigned int azx_skl_get_dpib_pos(struct azx *chip, 896 struct azx_dev *azx_dev) 897 { 898 return _snd_hdac_chip_readl(azx_bus(chip), 899 AZX_REG_VS_SDXDPIB_XBASE + 900 (AZX_REG_VS_SDXDPIB_XINTERVAL * 901 azx_dev->core.index)); 902 } 903 904 /* get the current DMA position with correction on SKL+ chips */ 905 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev) 906 { 907 /* DPIB register gives a more accurate position for playback */ 908 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 909 return azx_skl_get_dpib_pos(chip, azx_dev); 910 911 /* For capture, we need to read posbuf, but it requires a delay 912 * for the possible boundary overlap; the read of DPIB fetches the 913 * actual posbuf 914 */ 915 udelay(20); 916 azx_skl_get_dpib_pos(chip, azx_dev); 917 return azx_get_pos_posbuf(chip, azx_dev); 918 } 919 920 #ifdef CONFIG_PM 921 static DEFINE_MUTEX(card_list_lock); 922 static LIST_HEAD(card_list); 923 924 static void azx_add_card_list(struct azx *chip) 925 { 926 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 927 mutex_lock(&card_list_lock); 928 list_add(&hda->list, &card_list); 929 mutex_unlock(&card_list_lock); 930 } 931 932 static void azx_del_card_list(struct azx *chip) 933 { 934 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 935 mutex_lock(&card_list_lock); 936 list_del_init(&hda->list); 937 mutex_unlock(&card_list_lock); 938 } 939 940 /* trigger power-save check at writing parameter */ 941 static int param_set_xint(const char *val, const struct kernel_param *kp) 942 { 943 struct hda_intel *hda; 944 struct azx *chip; 945 int prev = power_save; 946 int ret = param_set_int(val, kp); 947 948 if (ret || prev == power_save) 949 return ret; 950 951 mutex_lock(&card_list_lock); 952 list_for_each_entry(hda, &card_list, list) { 953 chip = &hda->chip; 954 if (!hda->probe_continued || chip->disabled) 955 continue; 956 snd_hda_set_power_save(&chip->bus, power_save * 1000); 957 } 958 mutex_unlock(&card_list_lock); 959 return 0; 960 } 961 962 /* 963 * power management 964 */ 965 static bool azx_is_pm_ready(struct snd_card *card) 966 { 967 struct azx *chip; 968 struct hda_intel *hda; 969 970 if (!card) 971 return false; 972 chip = card->private_data; 973 hda = container_of(chip, struct hda_intel, chip); 974 if (chip->disabled || hda->init_failed || !chip->running) 975 return false; 976 return true; 977 } 978 979 static void __azx_runtime_suspend(struct azx *chip) 980 { 981 azx_stop_chip(chip); 982 azx_enter_link_reset(chip); 983 azx_clear_irq_pending(chip); 984 display_power(chip, false); 985 } 986 987 static void __azx_runtime_resume(struct azx *chip) 988 { 989 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 990 struct hdac_bus *bus = azx_bus(chip); 991 struct hda_codec *codec; 992 int status; 993 994 display_power(chip, true); 995 if (hda->need_i915_power) 996 snd_hdac_i915_set_bclk(bus); 997 998 /* Read STATESTS before controller reset */ 999 status = azx_readw(chip, STATESTS); 1000 1001 azx_init_pci(chip); 1002 hda_intel_init_chip(chip, true); 1003 1004 /* Avoid codec resume if runtime resume is for system suspend */ 1005 if (!chip->pm_prepared) { 1006 list_for_each_codec(codec, &chip->bus) { 1007 if (codec->relaxed_resume) 1008 continue; 1009 1010 if (codec->forced_resume || (status & (1 << codec->addr))) 1011 pm_request_resume(hda_codec_dev(codec)); 1012 } 1013 } 1014 1015 /* power down again for link-controlled chips */ 1016 if (!hda->need_i915_power) 1017 display_power(chip, false); 1018 } 1019 1020 #ifdef CONFIG_PM_SLEEP 1021 static int azx_prepare(struct device *dev) 1022 { 1023 struct snd_card *card = dev_get_drvdata(dev); 1024 struct azx *chip; 1025 1026 chip = card->private_data; 1027 chip->pm_prepared = 1; 1028 1029 flush_work(&azx_bus(chip)->unsol_work); 1030 1031 /* HDA controller always requires different WAKEEN for runtime suspend 1032 * and system suspend, so don't use direct-complete here. 1033 */ 1034 return 0; 1035 } 1036 1037 static void azx_complete(struct device *dev) 1038 { 1039 struct snd_card *card = dev_get_drvdata(dev); 1040 struct azx *chip; 1041 1042 chip = card->private_data; 1043 chip->pm_prepared = 0; 1044 } 1045 1046 static int azx_suspend(struct device *dev) 1047 { 1048 struct snd_card *card = dev_get_drvdata(dev); 1049 struct azx *chip; 1050 struct hdac_bus *bus; 1051 1052 if (!azx_is_pm_ready(card)) 1053 return 0; 1054 1055 chip = card->private_data; 1056 bus = azx_bus(chip); 1057 __azx_runtime_suspend(chip); 1058 if (bus->irq >= 0) { 1059 free_irq(bus->irq, chip); 1060 bus->irq = -1; 1061 chip->card->sync_irq = -1; 1062 } 1063 1064 if (chip->msi) 1065 pci_disable_msi(chip->pci); 1066 1067 trace_azx_suspend(chip); 1068 return 0; 1069 } 1070 1071 static int azx_resume(struct device *dev) 1072 { 1073 struct snd_card *card = dev_get_drvdata(dev); 1074 struct azx *chip; 1075 1076 if (!azx_is_pm_ready(card)) 1077 return 0; 1078 1079 chip = card->private_data; 1080 if (chip->msi) 1081 if (pci_enable_msi(chip->pci) < 0) 1082 chip->msi = 0; 1083 if (azx_acquire_irq(chip, 1) < 0) 1084 return -EIO; 1085 1086 __azx_runtime_resume(chip); 1087 1088 trace_azx_resume(chip); 1089 return 0; 1090 } 1091 1092 /* put codec down to D3 at hibernation for Intel SKL+; 1093 * otherwise BIOS may still access the codec and screw up the driver 1094 */ 1095 static int azx_freeze_noirq(struct device *dev) 1096 { 1097 struct snd_card *card = dev_get_drvdata(dev); 1098 struct azx *chip = card->private_data; 1099 struct pci_dev *pci = to_pci_dev(dev); 1100 1101 if (!azx_is_pm_ready(card)) 1102 return 0; 1103 if (chip->driver_type == AZX_DRIVER_SKL) 1104 pci_set_power_state(pci, PCI_D3hot); 1105 1106 return 0; 1107 } 1108 1109 static int azx_thaw_noirq(struct device *dev) 1110 { 1111 struct snd_card *card = dev_get_drvdata(dev); 1112 struct azx *chip = card->private_data; 1113 struct pci_dev *pci = to_pci_dev(dev); 1114 1115 if (!azx_is_pm_ready(card)) 1116 return 0; 1117 if (chip->driver_type == AZX_DRIVER_SKL) 1118 pci_set_power_state(pci, PCI_D0); 1119 1120 return 0; 1121 } 1122 #endif /* CONFIG_PM_SLEEP */ 1123 1124 static int azx_runtime_suspend(struct device *dev) 1125 { 1126 struct snd_card *card = dev_get_drvdata(dev); 1127 struct azx *chip; 1128 1129 if (!azx_is_pm_ready(card)) 1130 return 0; 1131 chip = card->private_data; 1132 1133 /* enable controller wake up event */ 1134 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK); 1135 1136 __azx_runtime_suspend(chip); 1137 trace_azx_runtime_suspend(chip); 1138 return 0; 1139 } 1140 1141 static int azx_runtime_resume(struct device *dev) 1142 { 1143 struct snd_card *card = dev_get_drvdata(dev); 1144 struct azx *chip; 1145 1146 if (!azx_is_pm_ready(card)) 1147 return 0; 1148 chip = card->private_data; 1149 __azx_runtime_resume(chip); 1150 1151 /* disable controller Wake Up event*/ 1152 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK); 1153 1154 trace_azx_runtime_resume(chip); 1155 return 0; 1156 } 1157 1158 static int azx_runtime_idle(struct device *dev) 1159 { 1160 struct snd_card *card = dev_get_drvdata(dev); 1161 struct azx *chip; 1162 struct hda_intel *hda; 1163 1164 if (!card) 1165 return 0; 1166 1167 chip = card->private_data; 1168 hda = container_of(chip, struct hda_intel, chip); 1169 if (chip->disabled || hda->init_failed) 1170 return 0; 1171 1172 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1173 azx_bus(chip)->codec_powered || !chip->running) 1174 return -EBUSY; 1175 1176 /* ELD notification gets broken when HD-audio bus is off */ 1177 if (needs_eld_notify_link(chip)) 1178 return -EBUSY; 1179 1180 return 0; 1181 } 1182 1183 static const struct dev_pm_ops azx_pm = { 1184 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1185 #ifdef CONFIG_PM_SLEEP 1186 .prepare = azx_prepare, 1187 .complete = azx_complete, 1188 .freeze_noirq = azx_freeze_noirq, 1189 .thaw_noirq = azx_thaw_noirq, 1190 #endif 1191 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1192 }; 1193 1194 #define AZX_PM_OPS &azx_pm 1195 #else 1196 #define azx_add_card_list(chip) /* NOP */ 1197 #define azx_del_card_list(chip) /* NOP */ 1198 #define AZX_PM_OPS NULL 1199 #endif /* CONFIG_PM */ 1200 1201 1202 static int azx_probe_continue(struct azx *chip); 1203 1204 #ifdef SUPPORT_VGA_SWITCHEROO 1205 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1206 1207 static void azx_vs_set_state(struct pci_dev *pci, 1208 enum vga_switcheroo_state state) 1209 { 1210 struct snd_card *card = pci_get_drvdata(pci); 1211 struct azx *chip = card->private_data; 1212 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1213 struct hda_codec *codec; 1214 bool disabled; 1215 1216 wait_for_completion(&hda->probe_wait); 1217 if (hda->init_failed) 1218 return; 1219 1220 disabled = (state == VGA_SWITCHEROO_OFF); 1221 if (chip->disabled == disabled) 1222 return; 1223 1224 if (!hda->probe_continued) { 1225 chip->disabled = disabled; 1226 if (!disabled) { 1227 dev_info(chip->card->dev, 1228 "Start delayed initialization\n"); 1229 if (azx_probe_continue(chip) < 0) 1230 dev_err(chip->card->dev, "initialization error\n"); 1231 } 1232 } else { 1233 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1234 disabled ? "Disabling" : "Enabling"); 1235 if (disabled) { 1236 list_for_each_codec(codec, &chip->bus) { 1237 pm_runtime_suspend(hda_codec_dev(codec)); 1238 pm_runtime_disable(hda_codec_dev(codec)); 1239 } 1240 pm_runtime_suspend(card->dev); 1241 pm_runtime_disable(card->dev); 1242 /* when we get suspended by vga_switcheroo we end up in D3cold, 1243 * however we have no ACPI handle, so pci/acpi can't put us there, 1244 * put ourselves there */ 1245 pci->current_state = PCI_D3cold; 1246 chip->disabled = true; 1247 if (snd_hda_lock_devices(&chip->bus)) 1248 dev_warn(chip->card->dev, 1249 "Cannot lock devices!\n"); 1250 } else { 1251 snd_hda_unlock_devices(&chip->bus); 1252 chip->disabled = false; 1253 pm_runtime_enable(card->dev); 1254 list_for_each_codec(codec, &chip->bus) { 1255 pm_runtime_enable(hda_codec_dev(codec)); 1256 pm_runtime_resume(hda_codec_dev(codec)); 1257 } 1258 } 1259 } 1260 } 1261 1262 static bool azx_vs_can_switch(struct pci_dev *pci) 1263 { 1264 struct snd_card *card = pci_get_drvdata(pci); 1265 struct azx *chip = card->private_data; 1266 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1267 1268 wait_for_completion(&hda->probe_wait); 1269 if (hda->init_failed) 1270 return false; 1271 if (chip->disabled || !hda->probe_continued) 1272 return true; 1273 if (snd_hda_lock_devices(&chip->bus)) 1274 return false; 1275 snd_hda_unlock_devices(&chip->bus); 1276 return true; 1277 } 1278 1279 /* 1280 * The discrete GPU cannot power down unless the HDA controller runtime 1281 * suspends, so activate runtime PM on codecs even if power_save == 0. 1282 */ 1283 static void setup_vga_switcheroo_runtime_pm(struct azx *chip) 1284 { 1285 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1286 struct hda_codec *codec; 1287 1288 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) { 1289 list_for_each_codec(codec, &chip->bus) 1290 codec->auto_runtime_pm = 1; 1291 /* reset the power save setup */ 1292 if (chip->running) 1293 set_default_power_save(chip); 1294 } 1295 } 1296 1297 static void azx_vs_gpu_bound(struct pci_dev *pci, 1298 enum vga_switcheroo_client_id client_id) 1299 { 1300 struct snd_card *card = pci_get_drvdata(pci); 1301 struct azx *chip = card->private_data; 1302 1303 if (client_id == VGA_SWITCHEROO_DIS) 1304 chip->bus.keep_power = 0; 1305 setup_vga_switcheroo_runtime_pm(chip); 1306 } 1307 1308 static void init_vga_switcheroo(struct azx *chip) 1309 { 1310 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1311 struct pci_dev *p = get_bound_vga(chip->pci); 1312 struct pci_dev *parent; 1313 if (p) { 1314 dev_info(chip->card->dev, 1315 "Handle vga_switcheroo audio client\n"); 1316 hda->use_vga_switcheroo = 1; 1317 1318 /* cleared in either gpu_bound op or codec probe, or when its 1319 * upstream port has _PR3 (i.e. dGPU). 1320 */ 1321 parent = pci_upstream_bridge(p); 1322 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1; 1323 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; 1324 pci_dev_put(p); 1325 } 1326 } 1327 1328 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1329 .set_gpu_state = azx_vs_set_state, 1330 .can_switch = azx_vs_can_switch, 1331 .gpu_bound = azx_vs_gpu_bound, 1332 }; 1333 1334 static int register_vga_switcheroo(struct azx *chip) 1335 { 1336 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1337 struct pci_dev *p; 1338 int err; 1339 1340 if (!hda->use_vga_switcheroo) 1341 return 0; 1342 1343 p = get_bound_vga(chip->pci); 1344 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p); 1345 pci_dev_put(p); 1346 1347 if (err < 0) 1348 return err; 1349 hda->vga_switcheroo_registered = 1; 1350 1351 return 0; 1352 } 1353 #else 1354 #define init_vga_switcheroo(chip) /* NOP */ 1355 #define register_vga_switcheroo(chip) 0 1356 #define check_hdmi_disabled(pci) false 1357 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */ 1358 #endif /* SUPPORT_VGA_SWITCHER */ 1359 1360 /* 1361 * destructor 1362 */ 1363 static void azx_free(struct azx *chip) 1364 { 1365 struct pci_dev *pci = chip->pci; 1366 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1367 struct hdac_bus *bus = azx_bus(chip); 1368 1369 if (hda->freed) 1370 return; 1371 1372 if (azx_has_pm_runtime(chip) && chip->running) 1373 pm_runtime_get_noresume(&pci->dev); 1374 chip->running = 0; 1375 1376 azx_del_card_list(chip); 1377 1378 hda->init_failed = 1; /* to be sure */ 1379 complete_all(&hda->probe_wait); 1380 1381 if (use_vga_switcheroo(hda)) { 1382 if (chip->disabled && hda->probe_continued) 1383 snd_hda_unlock_devices(&chip->bus); 1384 if (hda->vga_switcheroo_registered) 1385 vga_switcheroo_unregister_client(chip->pci); 1386 } 1387 1388 if (bus->chip_init) { 1389 azx_clear_irq_pending(chip); 1390 azx_stop_all_streams(chip); 1391 azx_stop_chip(chip); 1392 } 1393 1394 if (bus->irq >= 0) 1395 free_irq(bus->irq, (void*)chip); 1396 if (chip->msi) 1397 pci_disable_msi(chip->pci); 1398 iounmap(bus->remap_addr); 1399 1400 azx_free_stream_pages(chip); 1401 azx_free_streams(chip); 1402 snd_hdac_bus_exit(bus); 1403 1404 if (chip->region_requested) 1405 pci_release_regions(chip->pci); 1406 1407 pci_disable_device(chip->pci); 1408 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1409 release_firmware(chip->fw); 1410 #endif 1411 display_power(chip, false); 1412 1413 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) 1414 snd_hdac_i915_exit(bus); 1415 1416 hda->freed = 1; 1417 } 1418 1419 static int azx_dev_disconnect(struct snd_device *device) 1420 { 1421 struct azx *chip = device->device_data; 1422 struct hdac_bus *bus = azx_bus(chip); 1423 1424 chip->bus.shutdown = 1; 1425 cancel_work_sync(&bus->unsol_work); 1426 1427 return 0; 1428 } 1429 1430 static int azx_dev_free(struct snd_device *device) 1431 { 1432 azx_free(device->device_data); 1433 return 0; 1434 } 1435 1436 #ifdef SUPPORT_VGA_SWITCHEROO 1437 #ifdef CONFIG_ACPI 1438 /* ATPX is in the integrated GPU's namespace */ 1439 static bool atpx_present(void) 1440 { 1441 struct pci_dev *pdev = NULL; 1442 acpi_handle dhandle, atpx_handle; 1443 acpi_status status; 1444 1445 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 1446 dhandle = ACPI_HANDLE(&pdev->dev); 1447 if (dhandle) { 1448 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1449 if (ACPI_SUCCESS(status)) { 1450 pci_dev_put(pdev); 1451 return true; 1452 } 1453 } 1454 } 1455 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 1456 dhandle = ACPI_HANDLE(&pdev->dev); 1457 if (dhandle) { 1458 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1459 if (ACPI_SUCCESS(status)) { 1460 pci_dev_put(pdev); 1461 return true; 1462 } 1463 } 1464 } 1465 return false; 1466 } 1467 #else 1468 static bool atpx_present(void) 1469 { 1470 return false; 1471 } 1472 #endif 1473 1474 /* 1475 * Check of disabled HDMI controller by vga_switcheroo 1476 */ 1477 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1478 { 1479 struct pci_dev *p; 1480 1481 /* check only discrete GPU */ 1482 switch (pci->vendor) { 1483 case PCI_VENDOR_ID_ATI: 1484 case PCI_VENDOR_ID_AMD: 1485 if (pci->devfn == 1) { 1486 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1487 pci->bus->number, 0); 1488 if (p) { 1489 /* ATPX is in the integrated GPU's ACPI namespace 1490 * rather than the dGPU's namespace. However, 1491 * the dGPU is the one who is involved in 1492 * vgaswitcheroo. 1493 */ 1494 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) && 1495 atpx_present()) 1496 return p; 1497 pci_dev_put(p); 1498 } 1499 } 1500 break; 1501 case PCI_VENDOR_ID_NVIDIA: 1502 if (pci->devfn == 1) { 1503 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1504 pci->bus->number, 0); 1505 if (p) { 1506 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) 1507 return p; 1508 pci_dev_put(p); 1509 } 1510 } 1511 break; 1512 } 1513 return NULL; 1514 } 1515 1516 static bool check_hdmi_disabled(struct pci_dev *pci) 1517 { 1518 bool vga_inactive = false; 1519 struct pci_dev *p = get_bound_vga(pci); 1520 1521 if (p) { 1522 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1523 vga_inactive = true; 1524 pci_dev_put(p); 1525 } 1526 return vga_inactive; 1527 } 1528 #endif /* SUPPORT_VGA_SWITCHEROO */ 1529 1530 /* 1531 * allow/deny-listing for position_fix 1532 */ 1533 static const struct snd_pci_quirk position_fix_list[] = { 1534 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1535 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1536 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1537 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1538 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1539 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1540 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1541 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1542 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1543 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1544 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1545 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1546 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1547 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1548 {} 1549 }; 1550 1551 static int check_position_fix(struct azx *chip, int fix) 1552 { 1553 const struct snd_pci_quirk *q; 1554 1555 switch (fix) { 1556 case POS_FIX_AUTO: 1557 case POS_FIX_LPIB: 1558 case POS_FIX_POSBUF: 1559 case POS_FIX_VIACOMBO: 1560 case POS_FIX_COMBO: 1561 case POS_FIX_SKL: 1562 case POS_FIX_FIFO: 1563 return fix; 1564 } 1565 1566 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1567 if (q) { 1568 dev_info(chip->card->dev, 1569 "position_fix set to %d for device %04x:%04x\n", 1570 q->value, q->subvendor, q->subdevice); 1571 return q->value; 1572 } 1573 1574 /* Check VIA/ATI HD Audio Controller exist */ 1575 if (chip->driver_type == AZX_DRIVER_VIA) { 1576 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1577 return POS_FIX_VIACOMBO; 1578 } 1579 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) { 1580 dev_dbg(chip->card->dev, "Using FIFO position fix\n"); 1581 return POS_FIX_FIFO; 1582 } 1583 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1584 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1585 return POS_FIX_LPIB; 1586 } 1587 if (chip->driver_type == AZX_DRIVER_SKL) { 1588 dev_dbg(chip->card->dev, "Using SKL position fix\n"); 1589 return POS_FIX_SKL; 1590 } 1591 return POS_FIX_AUTO; 1592 } 1593 1594 static void assign_position_fix(struct azx *chip, int fix) 1595 { 1596 static const azx_get_pos_callback_t callbacks[] = { 1597 [POS_FIX_AUTO] = NULL, 1598 [POS_FIX_LPIB] = azx_get_pos_lpib, 1599 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1600 [POS_FIX_VIACOMBO] = azx_via_get_position, 1601 [POS_FIX_COMBO] = azx_get_pos_lpib, 1602 [POS_FIX_SKL] = azx_get_pos_skl, 1603 [POS_FIX_FIFO] = azx_get_pos_fifo, 1604 }; 1605 1606 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1607 1608 /* combo mode uses LPIB only for playback */ 1609 if (fix == POS_FIX_COMBO) 1610 chip->get_position[1] = NULL; 1611 1612 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) && 1613 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1614 chip->get_delay[0] = chip->get_delay[1] = 1615 azx_get_delay_from_lpib; 1616 } 1617 1618 if (fix == POS_FIX_FIFO) 1619 chip->get_delay[0] = chip->get_delay[1] = 1620 azx_get_delay_from_fifo; 1621 } 1622 1623 /* 1624 * deny-lists for probe_mask 1625 */ 1626 static const struct snd_pci_quirk probe_mask_list[] = { 1627 /* Thinkpad often breaks the controller communication when accessing 1628 * to the non-working (or non-existing) modem codec slot. 1629 */ 1630 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1631 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1632 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1633 /* broken BIOS */ 1634 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1635 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1636 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1637 /* forced codec slots */ 1638 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1639 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1640 /* WinFast VP200 H (Teradici) user reported broken communication */ 1641 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1642 {} 1643 }; 1644 1645 #define AZX_FORCE_CODEC_MASK 0x100 1646 1647 static void check_probe_mask(struct azx *chip, int dev) 1648 { 1649 const struct snd_pci_quirk *q; 1650 1651 chip->codec_probe_mask = probe_mask[dev]; 1652 if (chip->codec_probe_mask == -1) { 1653 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1654 if (q) { 1655 dev_info(chip->card->dev, 1656 "probe_mask set to 0x%x for device %04x:%04x\n", 1657 q->value, q->subvendor, q->subdevice); 1658 chip->codec_probe_mask = q->value; 1659 } 1660 } 1661 1662 /* check forced option */ 1663 if (chip->codec_probe_mask != -1 && 1664 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1665 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1666 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1667 (int)azx_bus(chip)->codec_mask); 1668 } 1669 } 1670 1671 /* 1672 * allow/deny-list for enable_msi 1673 */ 1674 static const struct snd_pci_quirk msi_deny_list[] = { 1675 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1676 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1677 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1678 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1679 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1680 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1681 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1682 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1683 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1684 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1685 {} 1686 }; 1687 1688 static void check_msi(struct azx *chip) 1689 { 1690 const struct snd_pci_quirk *q; 1691 1692 if (enable_msi >= 0) { 1693 chip->msi = !!enable_msi; 1694 return; 1695 } 1696 chip->msi = 1; /* enable MSI as default */ 1697 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list); 1698 if (q) { 1699 dev_info(chip->card->dev, 1700 "msi for device %04x:%04x set to %d\n", 1701 q->subvendor, q->subdevice, q->value); 1702 chip->msi = q->value; 1703 return; 1704 } 1705 1706 /* NVidia chipsets seem to cause troubles with MSI */ 1707 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1708 dev_info(chip->card->dev, "Disabling MSI\n"); 1709 chip->msi = 0; 1710 } 1711 } 1712 1713 /* check the snoop mode availability */ 1714 static void azx_check_snoop_available(struct azx *chip) 1715 { 1716 int snoop = hda_snoop; 1717 1718 if (snoop >= 0) { 1719 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1720 snoop ? "snoop" : "non-snoop"); 1721 chip->snoop = snoop; 1722 chip->uc_buffer = !snoop; 1723 return; 1724 } 1725 1726 snoop = true; 1727 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1728 chip->driver_type == AZX_DRIVER_VIA) { 1729 /* force to non-snoop mode for a new VIA controller 1730 * when BIOS is set 1731 */ 1732 u8 val; 1733 pci_read_config_byte(chip->pci, 0x42, &val); 1734 if (!(val & 0x80) && (chip->pci->revision == 0x30 || 1735 chip->pci->revision == 0x20)) 1736 snoop = false; 1737 } 1738 1739 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1740 snoop = false; 1741 1742 chip->snoop = snoop; 1743 if (!snoop) { 1744 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1745 /* C-Media requires non-cached pages only for CORB/RIRB */ 1746 if (chip->driver_type != AZX_DRIVER_CMEDIA) 1747 chip->uc_buffer = true; 1748 } 1749 } 1750 1751 static void azx_probe_work(struct work_struct *work) 1752 { 1753 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work); 1754 azx_probe_continue(&hda->chip); 1755 } 1756 1757 static int default_bdl_pos_adj(struct azx *chip) 1758 { 1759 /* some exceptions: Atoms seem problematic with value 1 */ 1760 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { 1761 switch (chip->pci->device) { 1762 case 0x0f04: /* Baytrail */ 1763 case 0x2284: /* Braswell */ 1764 return 32; 1765 } 1766 } 1767 1768 switch (chip->driver_type) { 1769 case AZX_DRIVER_ICH: 1770 case AZX_DRIVER_PCH: 1771 return 1; 1772 default: 1773 return 32; 1774 } 1775 } 1776 1777 /* 1778 * constructor 1779 */ 1780 static const struct hda_controller_ops pci_hda_ops; 1781 1782 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1783 int dev, unsigned int driver_caps, 1784 struct azx **rchip) 1785 { 1786 static const struct snd_device_ops ops = { 1787 .dev_disconnect = azx_dev_disconnect, 1788 .dev_free = azx_dev_free, 1789 }; 1790 struct hda_intel *hda; 1791 struct azx *chip; 1792 int err; 1793 1794 *rchip = NULL; 1795 1796 err = pci_enable_device(pci); 1797 if (err < 0) 1798 return err; 1799 1800 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL); 1801 if (!hda) { 1802 pci_disable_device(pci); 1803 return -ENOMEM; 1804 } 1805 1806 chip = &hda->chip; 1807 mutex_init(&chip->open_mutex); 1808 chip->card = card; 1809 chip->pci = pci; 1810 chip->ops = &pci_hda_ops; 1811 chip->driver_caps = driver_caps; 1812 chip->driver_type = driver_caps & 0xff; 1813 check_msi(chip); 1814 chip->dev_index = dev; 1815 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000) 1816 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]); 1817 INIT_LIST_HEAD(&chip->pcm_list); 1818 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1819 INIT_LIST_HEAD(&hda->list); 1820 init_vga_switcheroo(chip); 1821 init_completion(&hda->probe_wait); 1822 1823 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1824 1825 check_probe_mask(chip, dev); 1826 1827 if (single_cmd < 0) /* allow fallback to single_cmd at errors */ 1828 chip->fallback_to_single_cmd = 1; 1829 else /* explicitly set to single_cmd or not */ 1830 chip->single_cmd = single_cmd; 1831 1832 azx_check_snoop_available(chip); 1833 1834 if (bdl_pos_adj[dev] < 0) 1835 chip->bdl_pos_adj = default_bdl_pos_adj(chip); 1836 else 1837 chip->bdl_pos_adj = bdl_pos_adj[dev]; 1838 1839 err = azx_bus_init(chip, model[dev]); 1840 if (err < 0) { 1841 pci_disable_device(pci); 1842 return err; 1843 } 1844 1845 /* use the non-cached pages in non-snoop mode */ 1846 if (!azx_snoop(chip)) 1847 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC; 1848 1849 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 1850 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); 1851 chip->bus.core.needs_damn_long_delay = 1; 1852 } 1853 1854 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1855 if (err < 0) { 1856 dev_err(card->dev, "Error creating device [card]!\n"); 1857 azx_free(chip); 1858 return err; 1859 } 1860 1861 /* continue probing in work context as may trigger request module */ 1862 INIT_WORK(&hda->probe_work, azx_probe_work); 1863 1864 *rchip = chip; 1865 1866 return 0; 1867 } 1868 1869 static int azx_first_init(struct azx *chip) 1870 { 1871 int dev = chip->dev_index; 1872 struct pci_dev *pci = chip->pci; 1873 struct snd_card *card = chip->card; 1874 struct hdac_bus *bus = azx_bus(chip); 1875 int err; 1876 unsigned short gcap; 1877 unsigned int dma_bits = 64; 1878 1879 #if BITS_PER_LONG != 64 1880 /* Fix up base address on ULI M5461 */ 1881 if (chip->driver_type == AZX_DRIVER_ULI) { 1882 u16 tmp3; 1883 pci_read_config_word(pci, 0x40, &tmp3); 1884 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1885 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1886 } 1887 #endif 1888 1889 err = pci_request_regions(pci, "ICH HD audio"); 1890 if (err < 0) 1891 return err; 1892 chip->region_requested = 1; 1893 1894 bus->addr = pci_resource_start(pci, 0); 1895 bus->remap_addr = pci_ioremap_bar(pci, 0); 1896 if (bus->remap_addr == NULL) { 1897 dev_err(card->dev, "ioremap error\n"); 1898 return -ENXIO; 1899 } 1900 1901 if (chip->driver_type == AZX_DRIVER_SKL) 1902 snd_hdac_bus_parse_capabilities(bus); 1903 1904 /* 1905 * Some Intel CPUs has always running timer (ART) feature and 1906 * controller may have Global time sync reporting capability, so 1907 * check both of these before declaring synchronized time reporting 1908 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 1909 */ 1910 chip->gts_present = false; 1911 1912 #ifdef CONFIG_X86 1913 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART)) 1914 chip->gts_present = true; 1915 #endif 1916 1917 if (chip->msi) { 1918 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1919 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1920 pci->no_64bit_msi = true; 1921 } 1922 if (pci_enable_msi(pci) < 0) 1923 chip->msi = 0; 1924 } 1925 1926 pci_set_master(pci); 1927 1928 gcap = azx_readw(chip, GCAP); 1929 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1930 1931 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1932 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1933 dma_bits = 40; 1934 1935 /* disable SB600 64bit support for safety */ 1936 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1937 struct pci_dev *p_smbus; 1938 dma_bits = 40; 1939 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1940 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1941 NULL); 1942 if (p_smbus) { 1943 if (p_smbus->revision < 0x30) 1944 gcap &= ~AZX_GCAP_64OK; 1945 pci_dev_put(p_smbus); 1946 } 1947 } 1948 1949 /* NVidia hardware normally only supports up to 40 bits of DMA */ 1950 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) 1951 dma_bits = 40; 1952 1953 /* disable 64bit DMA address on some devices */ 1954 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1955 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1956 gcap &= ~AZX_GCAP_64OK; 1957 } 1958 1959 /* disable buffer size rounding to 128-byte multiples if supported */ 1960 if (align_buffer_size >= 0) 1961 chip->align_buffer_size = !!align_buffer_size; 1962 else { 1963 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1964 chip->align_buffer_size = 0; 1965 else 1966 chip->align_buffer_size = 1; 1967 } 1968 1969 /* allow 64bit DMA address if supported by H/W */ 1970 if (!(gcap & AZX_GCAP_64OK)) 1971 dma_bits = 32; 1972 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits))) 1973 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); 1974 1975 /* read number of streams from GCAP register instead of using 1976 * hardcoded value 1977 */ 1978 chip->capture_streams = (gcap >> 8) & 0x0f; 1979 chip->playback_streams = (gcap >> 12) & 0x0f; 1980 if (!chip->playback_streams && !chip->capture_streams) { 1981 /* gcap didn't give any info, switching to old method */ 1982 1983 switch (chip->driver_type) { 1984 case AZX_DRIVER_ULI: 1985 chip->playback_streams = ULI_NUM_PLAYBACK; 1986 chip->capture_streams = ULI_NUM_CAPTURE; 1987 break; 1988 case AZX_DRIVER_ATIHDMI: 1989 case AZX_DRIVER_ATIHDMI_NS: 1990 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1991 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1992 break; 1993 case AZX_DRIVER_GENERIC: 1994 default: 1995 chip->playback_streams = ICH6_NUM_PLAYBACK; 1996 chip->capture_streams = ICH6_NUM_CAPTURE; 1997 break; 1998 } 1999 } 2000 chip->capture_index_offset = 0; 2001 chip->playback_index_offset = chip->capture_streams; 2002 chip->num_streams = chip->playback_streams + chip->capture_streams; 2003 2004 /* sanity check for the SDxCTL.STRM field overflow */ 2005 if (chip->num_streams > 15 && 2006 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) { 2007 dev_warn(chip->card->dev, "number of I/O streams is %d, " 2008 "forcing separate stream tags", chip->num_streams); 2009 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG; 2010 } 2011 2012 /* initialize streams */ 2013 err = azx_init_streams(chip); 2014 if (err < 0) 2015 return err; 2016 2017 err = azx_alloc_stream_pages(chip); 2018 if (err < 0) 2019 return err; 2020 2021 /* initialize chip */ 2022 azx_init_pci(chip); 2023 2024 snd_hdac_i915_set_bclk(bus); 2025 2026 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 2027 2028 /* codec detection */ 2029 if (!azx_bus(chip)->codec_mask) { 2030 dev_err(card->dev, "no codecs found!\n"); 2031 /* keep running the rest for the runtime PM */ 2032 } 2033 2034 if (azx_acquire_irq(chip, 0) < 0) 2035 return -EBUSY; 2036 2037 strcpy(card->driver, "HDA-Intel"); 2038 strscpy(card->shortname, driver_short_names[chip->driver_type], 2039 sizeof(card->shortname)); 2040 snprintf(card->longname, sizeof(card->longname), 2041 "%s at 0x%lx irq %i", 2042 card->shortname, bus->addr, bus->irq); 2043 2044 return 0; 2045 } 2046 2047 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2048 /* callback from request_firmware_nowait() */ 2049 static void azx_firmware_cb(const struct firmware *fw, void *context) 2050 { 2051 struct snd_card *card = context; 2052 struct azx *chip = card->private_data; 2053 2054 if (fw) 2055 chip->fw = fw; 2056 else 2057 dev_err(card->dev, "Cannot load firmware, continue without patching\n"); 2058 if (!chip->disabled) { 2059 /* continue probing */ 2060 azx_probe_continue(chip); 2061 } 2062 } 2063 #endif 2064 2065 static int disable_msi_reset_irq(struct azx *chip) 2066 { 2067 struct hdac_bus *bus = azx_bus(chip); 2068 int err; 2069 2070 free_irq(bus->irq, chip); 2071 bus->irq = -1; 2072 chip->card->sync_irq = -1; 2073 pci_disable_msi(chip->pci); 2074 chip->msi = 0; 2075 err = azx_acquire_irq(chip, 1); 2076 if (err < 0) 2077 return err; 2078 2079 return 0; 2080 } 2081 2082 static void pcm_mmap_prepare(struct snd_pcm_substream *substream, 2083 struct vm_area_struct *area) 2084 { 2085 #ifdef CONFIG_X86 2086 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2087 struct azx *chip = apcm->chip; 2088 if (chip->uc_buffer) 2089 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); 2090 #endif 2091 } 2092 2093 /* Denylist for skipping the whole probe: 2094 * some HD-audio PCI entries are exposed without any codecs, and such devices 2095 * should be ignored from the beginning. 2096 */ 2097 static const struct pci_device_id driver_denylist[] = { 2098 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */ 2099 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */ 2100 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */ 2101 {} 2102 }; 2103 2104 static const struct hda_controller_ops pci_hda_ops = { 2105 .disable_msi_reset_irq = disable_msi_reset_irq, 2106 .pcm_mmap_prepare = pcm_mmap_prepare, 2107 .position_check = azx_position_check, 2108 }; 2109 2110 static int azx_probe(struct pci_dev *pci, 2111 const struct pci_device_id *pci_id) 2112 { 2113 static int dev; 2114 struct snd_card *card; 2115 struct hda_intel *hda; 2116 struct azx *chip; 2117 bool schedule_probe; 2118 int err; 2119 2120 if (pci_match_id(driver_denylist, pci)) { 2121 dev_info(&pci->dev, "Skipping the device on the denylist\n"); 2122 return -ENODEV; 2123 } 2124 2125 if (dev >= SNDRV_CARDS) 2126 return -ENODEV; 2127 if (!enable[dev]) { 2128 dev++; 2129 return -ENOENT; 2130 } 2131 2132 /* 2133 * stop probe if another Intel's DSP driver should be activated 2134 */ 2135 if (dmic_detect) { 2136 err = snd_intel_dsp_driver_probe(pci); 2137 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) { 2138 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n"); 2139 return -ENODEV; 2140 } 2141 } else { 2142 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n"); 2143 } 2144 2145 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2146 0, &card); 2147 if (err < 0) { 2148 dev_err(&pci->dev, "Error creating card!\n"); 2149 return err; 2150 } 2151 2152 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2153 if (err < 0) 2154 goto out_free; 2155 card->private_data = chip; 2156 hda = container_of(chip, struct hda_intel, chip); 2157 2158 pci_set_drvdata(pci, card); 2159 2160 err = register_vga_switcheroo(chip); 2161 if (err < 0) { 2162 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 2163 goto out_free; 2164 } 2165 2166 if (check_hdmi_disabled(pci)) { 2167 dev_info(card->dev, "VGA controller is disabled\n"); 2168 dev_info(card->dev, "Delaying initialization\n"); 2169 chip->disabled = true; 2170 } 2171 2172 schedule_probe = !chip->disabled; 2173 2174 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2175 if (patch[dev] && *patch[dev]) { 2176 dev_info(card->dev, "Applying patch firmware '%s'\n", 2177 patch[dev]); 2178 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 2179 &pci->dev, GFP_KERNEL, card, 2180 azx_firmware_cb); 2181 if (err < 0) 2182 goto out_free; 2183 schedule_probe = false; /* continued in azx_firmware_cb() */ 2184 } 2185 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 2186 2187 #ifndef CONFIG_SND_HDA_I915 2188 if (CONTROLLER_IN_GPU(pci)) 2189 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); 2190 #endif 2191 2192 if (schedule_probe) 2193 schedule_work(&hda->probe_work); 2194 2195 dev++; 2196 if (chip->disabled) 2197 complete_all(&hda->probe_wait); 2198 return 0; 2199 2200 out_free: 2201 snd_card_free(card); 2202 return err; 2203 } 2204 2205 #ifdef CONFIG_PM 2206 /* On some boards setting power_save to a non 0 value leads to clicking / 2207 * popping sounds when ever we enter/leave powersaving mode. Ideally we would 2208 * figure out how to avoid these sounds, but that is not always feasible. 2209 * So we keep a list of devices where we disable powersaving as its known 2210 * to causes problems on these devices. 2211 */ 2212 static const struct snd_pci_quirk power_save_denylist[] = { 2213 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2214 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0), 2215 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2216 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0), 2217 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2218 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0), 2219 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2220 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0), 2221 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2222 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0), 2223 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2224 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ 2225 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0), 2226 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2227 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0), 2228 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */ 2229 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0), 2230 /* https://bugs.launchpad.net/bugs/1821663 */ 2231 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0), 2232 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */ 2233 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), 2234 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ 2235 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), 2236 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ 2237 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), 2238 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ 2239 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0), 2240 /* https://bugs.launchpad.net/bugs/1821663 */ 2241 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0), 2242 {} 2243 }; 2244 #endif /* CONFIG_PM */ 2245 2246 static void set_default_power_save(struct azx *chip) 2247 { 2248 int val = power_save; 2249 2250 #ifdef CONFIG_PM 2251 if (pm_blacklist) { 2252 const struct snd_pci_quirk *q; 2253 2254 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist); 2255 if (q && val) { 2256 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n", 2257 q->subvendor, q->subdevice); 2258 val = 0; 2259 } 2260 } 2261 #endif /* CONFIG_PM */ 2262 snd_hda_set_power_save(&chip->bus, val * 1000); 2263 } 2264 2265 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 2266 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 2267 [AZX_DRIVER_NVIDIA] = 8, 2268 [AZX_DRIVER_TERA] = 1, 2269 }; 2270 2271 static int azx_probe_continue(struct azx *chip) 2272 { 2273 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2274 struct hdac_bus *bus = azx_bus(chip); 2275 struct pci_dev *pci = chip->pci; 2276 int dev = chip->dev_index; 2277 int err; 2278 2279 to_hda_bus(bus)->bus_probing = 1; 2280 hda->probe_continued = 1; 2281 2282 /* bind with i915 if needed */ 2283 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) { 2284 err = snd_hdac_i915_init(bus); 2285 if (err < 0) { 2286 /* if the controller is bound only with HDMI/DP 2287 * (for HSW and BDW), we need to abort the probe; 2288 * for other chips, still continue probing as other 2289 * codecs can be on the same link. 2290 */ 2291 if (CONTROLLER_IN_GPU(pci)) { 2292 dev_err(chip->card->dev, 2293 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); 2294 goto out_free; 2295 } else { 2296 /* don't bother any longer */ 2297 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT; 2298 } 2299 } 2300 2301 /* HSW/BDW controllers need this power */ 2302 if (CONTROLLER_IN_GPU(pci)) 2303 hda->need_i915_power = true; 2304 } 2305 2306 /* Request display power well for the HDA controller or codec. For 2307 * Haswell/Broadwell, both the display HDA controller and codec need 2308 * this power. For other platforms, like Baytrail/Braswell, only the 2309 * display codec needs the power and it can be released after probe. 2310 */ 2311 display_power(chip, true); 2312 2313 err = azx_first_init(chip); 2314 if (err < 0) 2315 goto out_free; 2316 2317 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2318 chip->beep_mode = beep_mode[dev]; 2319 #endif 2320 2321 /* create codec instances */ 2322 if (bus->codec_mask) { 2323 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2324 if (err < 0) 2325 goto out_free; 2326 } 2327 2328 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2329 if (chip->fw) { 2330 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2331 chip->fw->data); 2332 if (err < 0) 2333 goto out_free; 2334 #ifndef CONFIG_PM 2335 release_firmware(chip->fw); /* no longer needed */ 2336 chip->fw = NULL; 2337 #endif 2338 } 2339 #endif 2340 if (bus->codec_mask && !(probe_only[dev] & 1)) { 2341 err = azx_codec_configure(chip); 2342 if (err < 0) 2343 goto out_free; 2344 } 2345 2346 err = snd_card_register(chip->card); 2347 if (err < 0) 2348 goto out_free; 2349 2350 setup_vga_switcheroo_runtime_pm(chip); 2351 2352 chip->running = 1; 2353 azx_add_card_list(chip); 2354 2355 set_default_power_save(chip); 2356 2357 if (azx_has_pm_runtime(chip)) { 2358 pm_runtime_use_autosuspend(&pci->dev); 2359 pm_runtime_allow(&pci->dev); 2360 pm_runtime_put_autosuspend(&pci->dev); 2361 } 2362 2363 out_free: 2364 if (err < 0) { 2365 azx_free(chip); 2366 return err; 2367 } 2368 2369 if (!hda->need_i915_power) 2370 display_power(chip, false); 2371 complete_all(&hda->probe_wait); 2372 to_hda_bus(bus)->bus_probing = 0; 2373 return 0; 2374 } 2375 2376 static void azx_remove(struct pci_dev *pci) 2377 { 2378 struct snd_card *card = pci_get_drvdata(pci); 2379 struct azx *chip; 2380 struct hda_intel *hda; 2381 2382 if (card) { 2383 /* cancel the pending probing work */ 2384 chip = card->private_data; 2385 hda = container_of(chip, struct hda_intel, chip); 2386 /* FIXME: below is an ugly workaround. 2387 * Both device_release_driver() and driver_probe_device() 2388 * take *both* the device's and its parent's lock before 2389 * calling the remove() and probe() callbacks. The codec 2390 * probe takes the locks of both the codec itself and its 2391 * parent, i.e. the PCI controller dev. Meanwhile, when 2392 * the PCI controller is unbound, it takes its lock, too 2393 * ==> ouch, a deadlock! 2394 * As a workaround, we unlock temporarily here the controller 2395 * device during cancel_work_sync() call. 2396 */ 2397 device_unlock(&pci->dev); 2398 cancel_work_sync(&hda->probe_work); 2399 device_lock(&pci->dev); 2400 2401 snd_card_free(card); 2402 } 2403 } 2404 2405 static void azx_shutdown(struct pci_dev *pci) 2406 { 2407 struct snd_card *card = pci_get_drvdata(pci); 2408 struct azx *chip; 2409 2410 if (!card) 2411 return; 2412 chip = card->private_data; 2413 if (chip && chip->running) 2414 azx_stop_chip(chip); 2415 } 2416 2417 /* PCI IDs */ 2418 static const struct pci_device_id azx_ids[] = { 2419 /* CPT */ 2420 { PCI_DEVICE(0x8086, 0x1c20), 2421 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2422 /* PBG */ 2423 { PCI_DEVICE(0x8086, 0x1d20), 2424 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2425 /* Panther Point */ 2426 { PCI_DEVICE(0x8086, 0x1e20), 2427 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2428 /* Lynx Point */ 2429 { PCI_DEVICE(0x8086, 0x8c20), 2430 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2431 /* 9 Series */ 2432 { PCI_DEVICE(0x8086, 0x8ca0), 2433 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2434 /* Wellsburg */ 2435 { PCI_DEVICE(0x8086, 0x8d20), 2436 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2437 { PCI_DEVICE(0x8086, 0x8d21), 2438 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2439 /* Lewisburg */ 2440 { PCI_DEVICE(0x8086, 0xa1f0), 2441 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2442 { PCI_DEVICE(0x8086, 0xa270), 2443 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2444 /* Lynx Point-LP */ 2445 { PCI_DEVICE(0x8086, 0x9c20), 2446 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2447 /* Lynx Point-LP */ 2448 { PCI_DEVICE(0x8086, 0x9c21), 2449 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2450 /* Wildcat Point-LP */ 2451 { PCI_DEVICE(0x8086, 0x9ca0), 2452 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2453 /* Sunrise Point */ 2454 { PCI_DEVICE(0x8086, 0xa170), 2455 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2456 /* Sunrise Point-LP */ 2457 { PCI_DEVICE(0x8086, 0x9d70), 2458 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2459 /* Kabylake */ 2460 { PCI_DEVICE(0x8086, 0xa171), 2461 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2462 /* Kabylake-LP */ 2463 { PCI_DEVICE(0x8086, 0x9d71), 2464 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2465 /* Kabylake-H */ 2466 { PCI_DEVICE(0x8086, 0xa2f0), 2467 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2468 /* Coffelake */ 2469 { PCI_DEVICE(0x8086, 0xa348), 2470 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2471 /* Cannonlake */ 2472 { PCI_DEVICE(0x8086, 0x9dc8), 2473 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2474 /* CometLake-LP */ 2475 { PCI_DEVICE(0x8086, 0x02C8), 2476 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2477 /* CometLake-H */ 2478 { PCI_DEVICE(0x8086, 0x06C8), 2479 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2480 { PCI_DEVICE(0x8086, 0xf1c8), 2481 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2482 /* CometLake-S */ 2483 { PCI_DEVICE(0x8086, 0xa3f0), 2484 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2485 /* CometLake-R */ 2486 { PCI_DEVICE(0x8086, 0xf0c8), 2487 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2488 /* Icelake */ 2489 { PCI_DEVICE(0x8086, 0x34c8), 2490 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2491 /* Icelake-H */ 2492 { PCI_DEVICE(0x8086, 0x3dc8), 2493 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2494 /* Jasperlake */ 2495 { PCI_DEVICE(0x8086, 0x38c8), 2496 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2497 { PCI_DEVICE(0x8086, 0x4dc8), 2498 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2499 /* Tigerlake */ 2500 { PCI_DEVICE(0x8086, 0xa0c8), 2501 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2502 /* Tigerlake-H */ 2503 { PCI_DEVICE(0x8086, 0x43c8), 2504 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2505 /* DG1 */ 2506 { PCI_DEVICE(0x8086, 0x490d), 2507 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2508 /* Alderlake-S */ 2509 { PCI_DEVICE(0x8086, 0x7ad0), 2510 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2511 /* Alderlake-P */ 2512 { PCI_DEVICE(0x8086, 0x51c8), 2513 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2514 /* Elkhart Lake */ 2515 { PCI_DEVICE(0x8086, 0x4b55), 2516 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2517 { PCI_DEVICE(0x8086, 0x4b58), 2518 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2519 /* Broxton-P(Apollolake) */ 2520 { PCI_DEVICE(0x8086, 0x5a98), 2521 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2522 /* Broxton-T */ 2523 { PCI_DEVICE(0x8086, 0x1a98), 2524 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2525 /* Gemini-Lake */ 2526 { PCI_DEVICE(0x8086, 0x3198), 2527 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2528 /* Haswell */ 2529 { PCI_DEVICE(0x8086, 0x0a0c), 2530 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2531 { PCI_DEVICE(0x8086, 0x0c0c), 2532 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2533 { PCI_DEVICE(0x8086, 0x0d0c), 2534 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2535 /* Broadwell */ 2536 { PCI_DEVICE(0x8086, 0x160c), 2537 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 2538 /* 5 Series/3400 */ 2539 { PCI_DEVICE(0x8086, 0x3b56), 2540 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2541 /* Poulsbo */ 2542 { PCI_DEVICE(0x8086, 0x811b), 2543 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2544 /* Oaktrail */ 2545 { PCI_DEVICE(0x8086, 0x080a), 2546 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2547 /* BayTrail */ 2548 { PCI_DEVICE(0x8086, 0x0f04), 2549 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL }, 2550 /* Braswell */ 2551 { PCI_DEVICE(0x8086, 0x2284), 2552 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL }, 2553 /* ICH6 */ 2554 { PCI_DEVICE(0x8086, 0x2668), 2555 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2556 /* ICH7 */ 2557 { PCI_DEVICE(0x8086, 0x27d8), 2558 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2559 /* ESB2 */ 2560 { PCI_DEVICE(0x8086, 0x269a), 2561 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2562 /* ICH8 */ 2563 { PCI_DEVICE(0x8086, 0x284b), 2564 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2565 /* ICH9 */ 2566 { PCI_DEVICE(0x8086, 0x293e), 2567 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2568 /* ICH9 */ 2569 { PCI_DEVICE(0x8086, 0x293f), 2570 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2571 /* ICH10 */ 2572 { PCI_DEVICE(0x8086, 0x3a3e), 2573 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2574 /* ICH10 */ 2575 { PCI_DEVICE(0x8086, 0x3a6e), 2576 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2577 /* Generic Intel */ 2578 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2579 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2580 .class_mask = 0xffffff, 2581 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2582 /* ATI SB 450/600/700/800/900 */ 2583 { PCI_DEVICE(0x1002, 0x437b), 2584 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2585 { PCI_DEVICE(0x1002, 0x4383), 2586 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2587 /* AMD Hudson */ 2588 { PCI_DEVICE(0x1022, 0x780d), 2589 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2590 /* AMD, X370 & co */ 2591 { PCI_DEVICE(0x1022, 0x1457), 2592 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2593 /* AMD, X570 & co */ 2594 { PCI_DEVICE(0x1022, 0x1487), 2595 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2596 /* AMD Stoney */ 2597 { PCI_DEVICE(0x1022, 0x157a), 2598 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | 2599 AZX_DCAPS_PM_RUNTIME }, 2600 /* AMD Raven */ 2601 { PCI_DEVICE(0x1022, 0x15e3), 2602 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2603 /* ATI HDMI */ 2604 { PCI_DEVICE(0x1002, 0x0002), 2605 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2606 AZX_DCAPS_PM_RUNTIME }, 2607 { PCI_DEVICE(0x1002, 0x1308), 2608 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2609 { PCI_DEVICE(0x1002, 0x157a), 2610 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2611 { PCI_DEVICE(0x1002, 0x15b3), 2612 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2613 { PCI_DEVICE(0x1002, 0x793b), 2614 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2615 { PCI_DEVICE(0x1002, 0x7919), 2616 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2617 { PCI_DEVICE(0x1002, 0x960f), 2618 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2619 { PCI_DEVICE(0x1002, 0x970f), 2620 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2621 { PCI_DEVICE(0x1002, 0x9840), 2622 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2623 { PCI_DEVICE(0x1002, 0xaa00), 2624 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2625 { PCI_DEVICE(0x1002, 0xaa08), 2626 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2627 { PCI_DEVICE(0x1002, 0xaa10), 2628 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2629 { PCI_DEVICE(0x1002, 0xaa18), 2630 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2631 { PCI_DEVICE(0x1002, 0xaa20), 2632 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2633 { PCI_DEVICE(0x1002, 0xaa28), 2634 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2635 { PCI_DEVICE(0x1002, 0xaa30), 2636 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2637 { PCI_DEVICE(0x1002, 0xaa38), 2638 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2639 { PCI_DEVICE(0x1002, 0xaa40), 2640 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2641 { PCI_DEVICE(0x1002, 0xaa48), 2642 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2643 { PCI_DEVICE(0x1002, 0xaa50), 2644 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2645 { PCI_DEVICE(0x1002, 0xaa58), 2646 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2647 { PCI_DEVICE(0x1002, 0xaa60), 2648 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2649 { PCI_DEVICE(0x1002, 0xaa68), 2650 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2651 { PCI_DEVICE(0x1002, 0xaa80), 2652 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2653 { PCI_DEVICE(0x1002, 0xaa88), 2654 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2655 { PCI_DEVICE(0x1002, 0xaa90), 2656 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2657 { PCI_DEVICE(0x1002, 0xaa98), 2658 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2659 { PCI_DEVICE(0x1002, 0x9902), 2660 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2661 { PCI_DEVICE(0x1002, 0xaaa0), 2662 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2663 { PCI_DEVICE(0x1002, 0xaaa8), 2664 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2665 { PCI_DEVICE(0x1002, 0xaab0), 2666 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2667 { PCI_DEVICE(0x1002, 0xaac0), 2668 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2669 AZX_DCAPS_PM_RUNTIME }, 2670 { PCI_DEVICE(0x1002, 0xaac8), 2671 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2672 AZX_DCAPS_PM_RUNTIME }, 2673 { PCI_DEVICE(0x1002, 0xaad8), 2674 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2675 AZX_DCAPS_PM_RUNTIME }, 2676 { PCI_DEVICE(0x1002, 0xaae0), 2677 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2678 AZX_DCAPS_PM_RUNTIME }, 2679 { PCI_DEVICE(0x1002, 0xaae8), 2680 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2681 AZX_DCAPS_PM_RUNTIME }, 2682 { PCI_DEVICE(0x1002, 0xaaf0), 2683 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2684 AZX_DCAPS_PM_RUNTIME }, 2685 { PCI_DEVICE(0x1002, 0xaaf8), 2686 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2687 AZX_DCAPS_PM_RUNTIME }, 2688 { PCI_DEVICE(0x1002, 0xab00), 2689 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2690 AZX_DCAPS_PM_RUNTIME }, 2691 { PCI_DEVICE(0x1002, 0xab08), 2692 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2693 AZX_DCAPS_PM_RUNTIME }, 2694 { PCI_DEVICE(0x1002, 0xab10), 2695 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2696 AZX_DCAPS_PM_RUNTIME }, 2697 { PCI_DEVICE(0x1002, 0xab18), 2698 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2699 AZX_DCAPS_PM_RUNTIME }, 2700 { PCI_DEVICE(0x1002, 0xab20), 2701 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2702 AZX_DCAPS_PM_RUNTIME }, 2703 { PCI_DEVICE(0x1002, 0xab28), 2704 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2705 AZX_DCAPS_PM_RUNTIME }, 2706 { PCI_DEVICE(0x1002, 0xab38), 2707 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2708 AZX_DCAPS_PM_RUNTIME }, 2709 /* VIA VT8251/VT8237A */ 2710 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2711 /* VIA GFX VT7122/VX900 */ 2712 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2713 /* VIA GFX VT6122/VX11 */ 2714 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2715 /* SIS966 */ 2716 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2717 /* ULI M5461 */ 2718 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2719 /* NVIDIA MCP */ 2720 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2721 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2722 .class_mask = 0xffffff, 2723 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2724 /* Teradici */ 2725 { PCI_DEVICE(0x6549, 0x1200), 2726 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2727 { PCI_DEVICE(0x6549, 0x2200), 2728 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2729 /* Creative X-Fi (CA0110-IBG) */ 2730 /* CTHDA chips */ 2731 { PCI_DEVICE(0x1102, 0x0010), 2732 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2733 { PCI_DEVICE(0x1102, 0x0012), 2734 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2735 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2736 /* the following entry conflicts with snd-ctxfi driver, 2737 * as ctxfi driver mutates from HD-audio to native mode with 2738 * a special command sequence. 2739 */ 2740 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2741 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2742 .class_mask = 0xffffff, 2743 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2744 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2745 #else 2746 /* this entry seems still valid -- i.e. without emu20kx chip */ 2747 { PCI_DEVICE(0x1102, 0x0009), 2748 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2749 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2750 #endif 2751 /* CM8888 */ 2752 { PCI_DEVICE(0x13f6, 0x5011), 2753 .driver_data = AZX_DRIVER_CMEDIA | 2754 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2755 /* Vortex86MX */ 2756 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2757 /* VMware HDAudio */ 2758 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2759 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2760 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2761 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2762 .class_mask = 0xffffff, 2763 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2764 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2765 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2766 .class_mask = 0xffffff, 2767 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2768 /* Zhaoxin */ 2769 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN }, 2770 { 0, } 2771 }; 2772 MODULE_DEVICE_TABLE(pci, azx_ids); 2773 2774 /* pci_driver definition */ 2775 static struct pci_driver azx_driver = { 2776 .name = KBUILD_MODNAME, 2777 .id_table = azx_ids, 2778 .probe = azx_probe, 2779 .remove = azx_remove, 2780 .shutdown = azx_shutdown, 2781 .driver = { 2782 .pm = AZX_PM_OPS, 2783 }, 2784 }; 2785 2786 module_pci_driver(azx_driver); 2787