1 /* 2 * 3 * hda_intel.c - Implementation of primary alsa driver code base 4 * for Intel HD Audio. 5 * 6 * Copyright(c) 2004 Intel Corporation. All rights reserved. 7 * 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the Free 13 * Software Foundation; either version 2 of the License, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 * 21 * You should have received a copy of the GNU General Public License along with 22 * this program; if not, write to the Free Software Foundation, Inc., 59 23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 24 * 25 * CONTACTS: 26 * 27 * Matt Jared matt.jared@intel.com 28 * Andy Kopp andy.kopp@intel.com 29 * Dan Kogan dan.d.kogan@intel.com 30 * 31 * CHANGES: 32 * 33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 34 * 35 */ 36 37 #include <linux/delay.h> 38 #include <linux/interrupt.h> 39 #include <linux/kernel.h> 40 #include <linux/module.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/moduleparam.h> 43 #include <linux/init.h> 44 #include <linux/slab.h> 45 #include <linux/pci.h> 46 #include <linux/mutex.h> 47 #include <linux/io.h> 48 #include <linux/pm_runtime.h> 49 #include <linux/clocksource.h> 50 #include <linux/time.h> 51 #include <linux/completion.h> 52 53 #ifdef CONFIG_X86 54 /* for snoop control */ 55 #include <asm/pgtable.h> 56 #include <asm/cacheflush.h> 57 #endif 58 #include <sound/core.h> 59 #include <sound/initval.h> 60 #include <sound/hdaudio.h> 61 #include <sound/hda_i915.h> 62 #include <linux/vgaarb.h> 63 #include <linux/vga_switcheroo.h> 64 #include <linux/firmware.h> 65 #include "hda_codec.h" 66 #include "hda_controller.h" 67 #include "hda_intel.h" 68 69 #define CREATE_TRACE_POINTS 70 #include "hda_intel_trace.h" 71 72 /* position fix mode */ 73 enum { 74 POS_FIX_AUTO, 75 POS_FIX_LPIB, 76 POS_FIX_POSBUF, 77 POS_FIX_VIACOMBO, 78 POS_FIX_COMBO, 79 }; 80 81 /* Defines for ATI HD Audio support in SB450 south bridge */ 82 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 83 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 84 85 /* Defines for Nvidia HDA support */ 86 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 87 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 88 #define NVIDIA_HDA_ISTRM_COH 0x4d 89 #define NVIDIA_HDA_OSTRM_COH 0x4c 90 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 91 92 /* Defines for Intel SCH HDA snoop control */ 93 #define INTEL_HDA_CGCTL 0x48 94 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) 95 #define INTEL_SCH_HDA_DEVC 0x78 96 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 97 98 /* Define IN stream 0 FIFO size offset in VIA controller */ 99 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 100 /* Define VIA HD Audio Device ID*/ 101 #define VIA_HDAC_DEVICE_ID 0x3288 102 103 /* max number of SDs */ 104 /* ICH, ATI and VIA have 4 playback and 4 capture */ 105 #define ICH6_NUM_CAPTURE 4 106 #define ICH6_NUM_PLAYBACK 4 107 108 /* ULI has 6 playback and 5 capture */ 109 #define ULI_NUM_CAPTURE 5 110 #define ULI_NUM_PLAYBACK 6 111 112 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 113 #define ATIHDMI_NUM_CAPTURE 0 114 #define ATIHDMI_NUM_PLAYBACK 8 115 116 /* TERA has 4 playback and 3 capture */ 117 #define TERA_NUM_CAPTURE 3 118 #define TERA_NUM_PLAYBACK 4 119 120 121 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 122 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 123 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 124 static char *model[SNDRV_CARDS]; 125 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 126 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 127 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 128 static int probe_only[SNDRV_CARDS]; 129 static int jackpoll_ms[SNDRV_CARDS]; 130 static bool single_cmd; 131 static int enable_msi = -1; 132 #ifdef CONFIG_SND_HDA_PATCH_LOADER 133 static char *patch[SNDRV_CARDS]; 134 #endif 135 #ifdef CONFIG_SND_HDA_INPUT_BEEP 136 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 137 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 138 #endif 139 140 module_param_array(index, int, NULL, 0444); 141 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 142 module_param_array(id, charp, NULL, 0444); 143 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 144 module_param_array(enable, bool, NULL, 0444); 145 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 146 module_param_array(model, charp, NULL, 0444); 147 MODULE_PARM_DESC(model, "Use the given board model."); 148 module_param_array(position_fix, int, NULL, 0444); 149 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 150 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO)."); 151 module_param_array(bdl_pos_adj, int, NULL, 0644); 152 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 153 module_param_array(probe_mask, int, NULL, 0444); 154 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 155 module_param_array(probe_only, int, NULL, 0444); 156 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 157 module_param_array(jackpoll_ms, int, NULL, 0444); 158 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 159 module_param(single_cmd, bool, 0444); 160 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 161 "(for debugging only)."); 162 module_param(enable_msi, bint, 0444); 163 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 164 #ifdef CONFIG_SND_HDA_PATCH_LOADER 165 module_param_array(patch, charp, NULL, 0444); 166 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 167 #endif 168 #ifdef CONFIG_SND_HDA_INPUT_BEEP 169 module_param_array(beep_mode, bool, NULL, 0444); 170 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 171 "(0=off, 1=on) (default=1)."); 172 #endif 173 174 #ifdef CONFIG_PM 175 static int param_set_xint(const char *val, const struct kernel_param *kp); 176 static const struct kernel_param_ops param_ops_xint = { 177 .set = param_set_xint, 178 .get = param_get_int, 179 }; 180 #define param_check_xint param_check_int 181 182 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 183 module_param(power_save, xint, 0644); 184 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 185 "(in second, 0 = disable)."); 186 187 /* reset the HD-audio controller in power save mode. 188 * this may give more power-saving, but will take longer time to 189 * wake up. 190 */ 191 static bool power_save_controller = 1; 192 module_param(power_save_controller, bool, 0644); 193 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 194 #else 195 #define power_save 0 196 #endif /* CONFIG_PM */ 197 198 static int align_buffer_size = -1; 199 module_param(align_buffer_size, bint, 0644); 200 MODULE_PARM_DESC(align_buffer_size, 201 "Force buffer and period sizes to be multiple of 128 bytes."); 202 203 #ifdef CONFIG_X86 204 static int hda_snoop = -1; 205 module_param_named(snoop, hda_snoop, bint, 0444); 206 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 207 #else 208 #define hda_snoop true 209 #endif 210 211 212 MODULE_LICENSE("GPL"); 213 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 214 "{Intel, ICH6M}," 215 "{Intel, ICH7}," 216 "{Intel, ESB2}," 217 "{Intel, ICH8}," 218 "{Intel, ICH9}," 219 "{Intel, ICH10}," 220 "{Intel, PCH}," 221 "{Intel, CPT}," 222 "{Intel, PPT}," 223 "{Intel, LPT}," 224 "{Intel, LPT_LP}," 225 "{Intel, WPT_LP}," 226 "{Intel, SPT}," 227 "{Intel, SPT_LP}," 228 "{Intel, HPT}," 229 "{Intel, PBG}," 230 "{Intel, SCH}," 231 "{ATI, SB450}," 232 "{ATI, SB600}," 233 "{ATI, RS600}," 234 "{ATI, RS690}," 235 "{ATI, RS780}," 236 "{ATI, R600}," 237 "{ATI, RV630}," 238 "{ATI, RV610}," 239 "{ATI, RV670}," 240 "{ATI, RV635}," 241 "{ATI, RV620}," 242 "{ATI, RV770}," 243 "{VIA, VT8251}," 244 "{VIA, VT8237A}," 245 "{SiS, SIS966}," 246 "{ULI, M5461}}"); 247 MODULE_DESCRIPTION("Intel HDA driver"); 248 249 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 250 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 251 #define SUPPORT_VGA_SWITCHEROO 252 #endif 253 #endif 254 255 256 /* 257 */ 258 259 /* driver types */ 260 enum { 261 AZX_DRIVER_ICH, 262 AZX_DRIVER_PCH, 263 AZX_DRIVER_SCH, 264 AZX_DRIVER_HDMI, 265 AZX_DRIVER_ATI, 266 AZX_DRIVER_ATIHDMI, 267 AZX_DRIVER_ATIHDMI_NS, 268 AZX_DRIVER_VIA, 269 AZX_DRIVER_SIS, 270 AZX_DRIVER_ULI, 271 AZX_DRIVER_NVIDIA, 272 AZX_DRIVER_TERA, 273 AZX_DRIVER_CTX, 274 AZX_DRIVER_CTHDA, 275 AZX_DRIVER_CMEDIA, 276 AZX_DRIVER_GENERIC, 277 AZX_NUM_DRIVERS, /* keep this as last entry */ 278 }; 279 280 #define azx_get_snoop_type(chip) \ 281 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 282 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 283 284 /* quirks for old Intel chipsets */ 285 #define AZX_DCAPS_INTEL_ICH \ 286 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 287 288 /* quirks for Intel PCH */ 289 #define AZX_DCAPS_INTEL_PCH_BASE \ 290 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 291 AZX_DCAPS_SNOOP_TYPE(SCH)) 292 293 /* PCH up to IVB; no runtime PM */ 294 #define AZX_DCAPS_INTEL_PCH_NOPM \ 295 (AZX_DCAPS_INTEL_PCH_BASE) 296 297 /* PCH for HSW/BDW; with runtime PM */ 298 #define AZX_DCAPS_INTEL_PCH \ 299 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) 300 301 /* HSW HDMI */ 302 #define AZX_DCAPS_INTEL_HASWELL \ 303 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 304 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\ 305 AZX_DCAPS_SNOOP_TYPE(SCH)) 306 307 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 308 #define AZX_DCAPS_INTEL_BROADWELL \ 309 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 310 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\ 311 AZX_DCAPS_SNOOP_TYPE(SCH)) 312 313 #define AZX_DCAPS_INTEL_BAYTRAIL \ 314 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL) 315 316 #define AZX_DCAPS_INTEL_BRASWELL \ 317 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL) 318 319 #define AZX_DCAPS_INTEL_SKYLAKE \ 320 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\ 321 AZX_DCAPS_I915_POWERWELL) 322 323 #define AZX_DCAPS_INTEL_BROXTON \ 324 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\ 325 AZX_DCAPS_I915_POWERWELL) 326 327 /* quirks for ATI SB / AMD Hudson */ 328 #define AZX_DCAPS_PRESET_ATI_SB \ 329 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\ 330 AZX_DCAPS_SNOOP_TYPE(ATI)) 331 332 /* quirks for ATI/AMD HDMI */ 333 #define AZX_DCAPS_PRESET_ATI_HDMI \ 334 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\ 335 AZX_DCAPS_NO_MSI64) 336 337 /* quirks for ATI HDMI with snoop off */ 338 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 339 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 340 341 /* quirks for Nvidia */ 342 #define AZX_DCAPS_PRESET_NVIDIA \ 343 (AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \ 344 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 345 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 346 347 #define AZX_DCAPS_PRESET_CTHDA \ 348 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 349 AZX_DCAPS_NO_64BIT |\ 350 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 351 352 /* 353 * vga_switcheroo support 354 */ 355 #ifdef SUPPORT_VGA_SWITCHEROO 356 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 357 #else 358 #define use_vga_switcheroo(chip) 0 359 #endif 360 361 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \ 362 ((pci)->device == 0x0c0c) || \ 363 ((pci)->device == 0x0d0c) || \ 364 ((pci)->device == 0x160c)) 365 366 #define IS_BROXTON(pci) ((pci)->device == 0x5a98) 367 368 static char *driver_short_names[] = { 369 [AZX_DRIVER_ICH] = "HDA Intel", 370 [AZX_DRIVER_PCH] = "HDA Intel PCH", 371 [AZX_DRIVER_SCH] = "HDA Intel MID", 372 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 373 [AZX_DRIVER_ATI] = "HDA ATI SB", 374 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 375 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 376 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 377 [AZX_DRIVER_SIS] = "HDA SIS966", 378 [AZX_DRIVER_ULI] = "HDA ULI M5461", 379 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 380 [AZX_DRIVER_TERA] = "HDA Teradici", 381 [AZX_DRIVER_CTX] = "HDA Creative", 382 [AZX_DRIVER_CTHDA] = "HDA Creative", 383 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 384 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 385 }; 386 387 #ifdef CONFIG_X86 388 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on) 389 { 390 int pages; 391 392 if (azx_snoop(chip)) 393 return; 394 if (!dmab || !dmab->area || !dmab->bytes) 395 return; 396 397 #ifdef CONFIG_SND_DMA_SGBUF 398 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) { 399 struct snd_sg_buf *sgbuf = dmab->private_data; 400 if (chip->driver_type == AZX_DRIVER_CMEDIA) 401 return; /* deal with only CORB/RIRB buffers */ 402 if (on) 403 set_pages_array_wc(sgbuf->page_table, sgbuf->pages); 404 else 405 set_pages_array_wb(sgbuf->page_table, sgbuf->pages); 406 return; 407 } 408 #endif 409 410 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT; 411 if (on) 412 set_memory_wc((unsigned long)dmab->area, pages); 413 else 414 set_memory_wb((unsigned long)dmab->area, pages); 415 } 416 417 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 418 bool on) 419 { 420 __mark_pages_wc(chip, buf, on); 421 } 422 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 423 struct snd_pcm_substream *substream, bool on) 424 { 425 if (azx_dev->wc_marked != on) { 426 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on); 427 azx_dev->wc_marked = on; 428 } 429 } 430 #else 431 /* NOP for other archs */ 432 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 433 bool on) 434 { 435 } 436 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 437 struct snd_pcm_substream *substream, bool on) 438 { 439 } 440 #endif 441 442 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 443 444 /* 445 * initialize the PCI registers 446 */ 447 /* update bits in a PCI register byte */ 448 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 449 unsigned char mask, unsigned char val) 450 { 451 unsigned char data; 452 453 pci_read_config_byte(pci, reg, &data); 454 data &= ~mask; 455 data |= (val & mask); 456 pci_write_config_byte(pci, reg, data); 457 } 458 459 static void azx_init_pci(struct azx *chip) 460 { 461 int snoop_type = azx_get_snoop_type(chip); 462 463 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 464 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 465 * Ensuring these bits are 0 clears playback static on some HD Audio 466 * codecs. 467 * The PCI register TCSEL is defined in the Intel manuals. 468 */ 469 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 470 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 471 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 472 } 473 474 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 475 * we need to enable snoop. 476 */ 477 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 478 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 479 azx_snoop(chip)); 480 update_pci_byte(chip->pci, 481 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 482 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 483 } 484 485 /* For NVIDIA HDA, enable snoop */ 486 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 487 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 488 azx_snoop(chip)); 489 update_pci_byte(chip->pci, 490 NVIDIA_HDA_TRANSREG_ADDR, 491 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 492 update_pci_byte(chip->pci, 493 NVIDIA_HDA_ISTRM_COH, 494 0x01, NVIDIA_HDA_ENABLE_COHBIT); 495 update_pci_byte(chip->pci, 496 NVIDIA_HDA_OSTRM_COH, 497 0x01, NVIDIA_HDA_ENABLE_COHBIT); 498 } 499 500 /* Enable SCH/PCH snoop if needed */ 501 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 502 unsigned short snoop; 503 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 504 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 505 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 506 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 507 if (!azx_snoop(chip)) 508 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 509 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 510 pci_read_config_word(chip->pci, 511 INTEL_SCH_HDA_DEVC, &snoop); 512 } 513 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 514 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 515 "Disabled" : "Enabled"); 516 } 517 } 518 519 /* 520 * In BXT-P A0, HD-Audio DMA requests is later than expected, 521 * and makes an audio stream sensitive to system latencies when 522 * 24/32 bits are playing. 523 * Adjusting threshold of DMA fifo to force the DMA request 524 * sooner to improve latency tolerance at the expense of power. 525 */ 526 static void bxt_reduce_dma_latency(struct azx *chip) 527 { 528 u32 val; 529 530 val = azx_readl(chip, SKL_EM4L); 531 val &= (0x3 << 20); 532 azx_writel(chip, SKL_EM4L, val); 533 } 534 535 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 536 { 537 struct hdac_bus *bus = azx_bus(chip); 538 struct pci_dev *pci = chip->pci; 539 u32 val; 540 541 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 542 snd_hdac_set_codec_wakeup(bus, true); 543 if (IS_BROXTON(pci)) { 544 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 545 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; 546 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 547 } 548 azx_init_chip(chip, full_reset); 549 if (IS_BROXTON(pci)) { 550 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 551 val = val | INTEL_HDA_CGCTL_MISCBDCGE; 552 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 553 } 554 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 555 snd_hdac_set_codec_wakeup(bus, false); 556 557 /* reduce dma latency to avoid noise */ 558 if (IS_BROXTON(pci)) 559 bxt_reduce_dma_latency(chip); 560 } 561 562 /* calculate runtime delay from LPIB */ 563 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 564 unsigned int pos) 565 { 566 struct snd_pcm_substream *substream = azx_dev->core.substream; 567 int stream = substream->stream; 568 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 569 int delay; 570 571 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 572 delay = pos - lpib_pos; 573 else 574 delay = lpib_pos - pos; 575 if (delay < 0) { 576 if (delay >= azx_dev->core.delay_negative_threshold) 577 delay = 0; 578 else 579 delay += azx_dev->core.bufsize; 580 } 581 582 if (delay >= azx_dev->core.period_bytes) { 583 dev_info(chip->card->dev, 584 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 585 delay, azx_dev->core.period_bytes); 586 delay = 0; 587 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 588 chip->get_delay[stream] = NULL; 589 } 590 591 return bytes_to_frames(substream->runtime, delay); 592 } 593 594 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 595 596 /* called from IRQ */ 597 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 598 { 599 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 600 int ok; 601 602 ok = azx_position_ok(chip, azx_dev); 603 if (ok == 1) { 604 azx_dev->irq_pending = 0; 605 return ok; 606 } else if (ok == 0) { 607 /* bogus IRQ, process it later */ 608 azx_dev->irq_pending = 1; 609 schedule_work(&hda->irq_pending_work); 610 } 611 return 0; 612 } 613 614 /* Enable/disable i915 display power for the link */ 615 static int azx_intel_link_power(struct azx *chip, bool enable) 616 { 617 struct hdac_bus *bus = azx_bus(chip); 618 619 return snd_hdac_display_power(bus, enable); 620 } 621 622 /* 623 * Check whether the current DMA position is acceptable for updating 624 * periods. Returns non-zero if it's OK. 625 * 626 * Many HD-audio controllers appear pretty inaccurate about 627 * the update-IRQ timing. The IRQ is issued before actually the 628 * data is processed. So, we need to process it afterwords in a 629 * workqueue. 630 */ 631 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 632 { 633 struct snd_pcm_substream *substream = azx_dev->core.substream; 634 int stream = substream->stream; 635 u32 wallclk; 636 unsigned int pos; 637 638 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 639 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 640 return -1; /* bogus (too early) interrupt */ 641 642 if (chip->get_position[stream]) 643 pos = chip->get_position[stream](chip, azx_dev); 644 else { /* use the position buffer as default */ 645 pos = azx_get_pos_posbuf(chip, azx_dev); 646 if (!pos || pos == (u32)-1) { 647 dev_info(chip->card->dev, 648 "Invalid position buffer, using LPIB read method instead.\n"); 649 chip->get_position[stream] = azx_get_pos_lpib; 650 if (chip->get_position[0] == azx_get_pos_lpib && 651 chip->get_position[1] == azx_get_pos_lpib) 652 azx_bus(chip)->use_posbuf = false; 653 pos = azx_get_pos_lpib(chip, azx_dev); 654 chip->get_delay[stream] = NULL; 655 } else { 656 chip->get_position[stream] = azx_get_pos_posbuf; 657 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 658 chip->get_delay[stream] = azx_get_delay_from_lpib; 659 } 660 } 661 662 if (pos >= azx_dev->core.bufsize) 663 pos = 0; 664 665 if (WARN_ONCE(!azx_dev->core.period_bytes, 666 "hda-intel: zero azx_dev->period_bytes")) 667 return -1; /* this shouldn't happen! */ 668 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 669 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 670 /* NG - it's below the first next period boundary */ 671 return chip->bdl_pos_adj ? 0 : -1; 672 azx_dev->core.start_wallclk += wallclk; 673 return 1; /* OK, it's fine */ 674 } 675 676 /* 677 * The work for pending PCM period updates. 678 */ 679 static void azx_irq_pending_work(struct work_struct *work) 680 { 681 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 682 struct azx *chip = &hda->chip; 683 struct hdac_bus *bus = azx_bus(chip); 684 struct hdac_stream *s; 685 int pending, ok; 686 687 if (!hda->irq_pending_warned) { 688 dev_info(chip->card->dev, 689 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 690 chip->card->number); 691 hda->irq_pending_warned = 1; 692 } 693 694 for (;;) { 695 pending = 0; 696 spin_lock_irq(&bus->reg_lock); 697 list_for_each_entry(s, &bus->stream_list, list) { 698 struct azx_dev *azx_dev = stream_to_azx_dev(s); 699 if (!azx_dev->irq_pending || 700 !s->substream || 701 !s->running) 702 continue; 703 ok = azx_position_ok(chip, azx_dev); 704 if (ok > 0) { 705 azx_dev->irq_pending = 0; 706 spin_unlock(&bus->reg_lock); 707 snd_pcm_period_elapsed(s->substream); 708 spin_lock(&bus->reg_lock); 709 } else if (ok < 0) { 710 pending = 0; /* too early */ 711 } else 712 pending++; 713 } 714 spin_unlock_irq(&bus->reg_lock); 715 if (!pending) 716 return; 717 msleep(1); 718 } 719 } 720 721 /* clear irq_pending flags and assure no on-going workq */ 722 static void azx_clear_irq_pending(struct azx *chip) 723 { 724 struct hdac_bus *bus = azx_bus(chip); 725 struct hdac_stream *s; 726 727 spin_lock_irq(&bus->reg_lock); 728 list_for_each_entry(s, &bus->stream_list, list) { 729 struct azx_dev *azx_dev = stream_to_azx_dev(s); 730 azx_dev->irq_pending = 0; 731 } 732 spin_unlock_irq(&bus->reg_lock); 733 } 734 735 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 736 { 737 struct hdac_bus *bus = azx_bus(chip); 738 739 if (request_irq(chip->pci->irq, azx_interrupt, 740 chip->msi ? 0 : IRQF_SHARED, 741 chip->card->irq_descr, chip)) { 742 dev_err(chip->card->dev, 743 "unable to grab IRQ %d, disabling device\n", 744 chip->pci->irq); 745 if (do_disconnect) 746 snd_card_disconnect(chip->card); 747 return -1; 748 } 749 bus->irq = chip->pci->irq; 750 pci_intx(chip->pci, !chip->msi); 751 return 0; 752 } 753 754 /* get the current DMA position with correction on VIA chips */ 755 static unsigned int azx_via_get_position(struct azx *chip, 756 struct azx_dev *azx_dev) 757 { 758 unsigned int link_pos, mini_pos, bound_pos; 759 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 760 unsigned int fifo_size; 761 762 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 763 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 764 /* Playback, no problem using link position */ 765 return link_pos; 766 } 767 768 /* Capture */ 769 /* For new chipset, 770 * use mod to get the DMA position just like old chipset 771 */ 772 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 773 mod_dma_pos %= azx_dev->core.period_bytes; 774 775 /* azx_dev->fifo_size can't get FIFO size of in stream. 776 * Get from base address + offset. 777 */ 778 fifo_size = readw(azx_bus(chip)->remap_addr + 779 VIA_IN_STREAM0_FIFO_SIZE_OFFSET); 780 781 if (azx_dev->insufficient) { 782 /* Link position never gather than FIFO size */ 783 if (link_pos <= fifo_size) 784 return 0; 785 786 azx_dev->insufficient = 0; 787 } 788 789 if (link_pos <= fifo_size) 790 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 791 else 792 mini_pos = link_pos - fifo_size; 793 794 /* Find nearest previous boudary */ 795 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 796 mod_link_pos = link_pos % azx_dev->core.period_bytes; 797 if (mod_link_pos >= fifo_size) 798 bound_pos = link_pos - mod_link_pos; 799 else if (mod_dma_pos >= mod_mini_pos) 800 bound_pos = mini_pos - mod_mini_pos; 801 else { 802 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 803 if (bound_pos >= azx_dev->core.bufsize) 804 bound_pos = 0; 805 } 806 807 /* Calculate real DMA position we want */ 808 return bound_pos + mod_dma_pos; 809 } 810 811 #ifdef CONFIG_PM 812 static DEFINE_MUTEX(card_list_lock); 813 static LIST_HEAD(card_list); 814 815 static void azx_add_card_list(struct azx *chip) 816 { 817 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 818 mutex_lock(&card_list_lock); 819 list_add(&hda->list, &card_list); 820 mutex_unlock(&card_list_lock); 821 } 822 823 static void azx_del_card_list(struct azx *chip) 824 { 825 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 826 mutex_lock(&card_list_lock); 827 list_del_init(&hda->list); 828 mutex_unlock(&card_list_lock); 829 } 830 831 /* trigger power-save check at writing parameter */ 832 static int param_set_xint(const char *val, const struct kernel_param *kp) 833 { 834 struct hda_intel *hda; 835 struct azx *chip; 836 int prev = power_save; 837 int ret = param_set_int(val, kp); 838 839 if (ret || prev == power_save) 840 return ret; 841 842 mutex_lock(&card_list_lock); 843 list_for_each_entry(hda, &card_list, list) { 844 chip = &hda->chip; 845 if (!hda->probe_continued || chip->disabled) 846 continue; 847 snd_hda_set_power_save(&chip->bus, power_save * 1000); 848 } 849 mutex_unlock(&card_list_lock); 850 return 0; 851 } 852 #else 853 #define azx_add_card_list(chip) /* NOP */ 854 #define azx_del_card_list(chip) /* NOP */ 855 #endif /* CONFIG_PM */ 856 857 /* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK 858 * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value) 859 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK: 860 * BCLK = CDCLK * M / N 861 * The values will be lost when the display power well is disabled and need to 862 * be restored to avoid abnormal playback speed. 863 */ 864 static void haswell_set_bclk(struct hda_intel *hda) 865 { 866 struct azx *chip = &hda->chip; 867 int cdclk_freq; 868 unsigned int bclk_m, bclk_n; 869 870 if (!hda->need_i915_power) 871 return; 872 873 cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip)); 874 switch (cdclk_freq) { 875 case 337500: 876 bclk_m = 16; 877 bclk_n = 225; 878 break; 879 880 case 450000: 881 default: /* default CDCLK 450MHz */ 882 bclk_m = 4; 883 bclk_n = 75; 884 break; 885 886 case 540000: 887 bclk_m = 4; 888 bclk_n = 90; 889 break; 890 891 case 675000: 892 bclk_m = 8; 893 bclk_n = 225; 894 break; 895 } 896 897 azx_writew(chip, HSW_EM4, bclk_m); 898 azx_writew(chip, HSW_EM5, bclk_n); 899 } 900 901 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO) 902 /* 903 * power management 904 */ 905 static int azx_suspend(struct device *dev) 906 { 907 struct snd_card *card = dev_get_drvdata(dev); 908 struct azx *chip; 909 struct hda_intel *hda; 910 struct hdac_bus *bus; 911 912 if (!card) 913 return 0; 914 915 chip = card->private_data; 916 hda = container_of(chip, struct hda_intel, chip); 917 if (chip->disabled || hda->init_failed || !chip->running) 918 return 0; 919 920 bus = azx_bus(chip); 921 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 922 azx_clear_irq_pending(chip); 923 azx_stop_chip(chip); 924 azx_enter_link_reset(chip); 925 if (bus->irq >= 0) { 926 free_irq(bus->irq, chip); 927 bus->irq = -1; 928 } 929 930 if (chip->msi) 931 pci_disable_msi(chip->pci); 932 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL 933 && hda->need_i915_power) 934 snd_hdac_display_power(bus, false); 935 936 trace_azx_suspend(chip); 937 return 0; 938 } 939 940 static int azx_resume(struct device *dev) 941 { 942 struct pci_dev *pci = to_pci_dev(dev); 943 struct snd_card *card = dev_get_drvdata(dev); 944 struct azx *chip; 945 struct hda_intel *hda; 946 947 if (!card) 948 return 0; 949 950 chip = card->private_data; 951 hda = container_of(chip, struct hda_intel, chip); 952 if (chip->disabled || hda->init_failed || !chip->running) 953 return 0; 954 955 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL 956 && hda->need_i915_power) { 957 snd_hdac_display_power(azx_bus(chip), true); 958 haswell_set_bclk(hda); 959 } 960 if (chip->msi) 961 if (pci_enable_msi(pci) < 0) 962 chip->msi = 0; 963 if (azx_acquire_irq(chip, 1) < 0) 964 return -EIO; 965 azx_init_pci(chip); 966 967 hda_intel_init_chip(chip, true); 968 969 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 970 971 trace_azx_resume(chip); 972 return 0; 973 } 974 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */ 975 976 #ifdef CONFIG_PM_SLEEP 977 /* put codec down to D3 at hibernation for Intel SKL+; 978 * otherwise BIOS may still access the codec and screw up the driver 979 */ 980 #define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170) 981 #define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70) 982 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98) 983 #define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci)) 984 985 static int azx_freeze_noirq(struct device *dev) 986 { 987 struct pci_dev *pci = to_pci_dev(dev); 988 989 if (IS_SKL_PLUS(pci)) 990 pci_set_power_state(pci, PCI_D3hot); 991 992 return 0; 993 } 994 995 static int azx_thaw_noirq(struct device *dev) 996 { 997 struct pci_dev *pci = to_pci_dev(dev); 998 999 if (IS_SKL_PLUS(pci)) 1000 pci_set_power_state(pci, PCI_D0); 1001 1002 return 0; 1003 } 1004 #endif /* CONFIG_PM_SLEEP */ 1005 1006 #ifdef CONFIG_PM 1007 static int azx_runtime_suspend(struct device *dev) 1008 { 1009 struct snd_card *card = dev_get_drvdata(dev); 1010 struct azx *chip; 1011 struct hda_intel *hda; 1012 1013 if (!card) 1014 return 0; 1015 1016 chip = card->private_data; 1017 hda = container_of(chip, struct hda_intel, chip); 1018 if (chip->disabled || hda->init_failed) 1019 return 0; 1020 1021 if (!azx_has_pm_runtime(chip)) 1022 return 0; 1023 1024 /* enable controller wake up event */ 1025 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 1026 STATESTS_INT_MASK); 1027 1028 azx_stop_chip(chip); 1029 azx_enter_link_reset(chip); 1030 azx_clear_irq_pending(chip); 1031 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL 1032 && hda->need_i915_power) 1033 snd_hdac_display_power(azx_bus(chip), false); 1034 1035 trace_azx_runtime_suspend(chip); 1036 return 0; 1037 } 1038 1039 static int azx_runtime_resume(struct device *dev) 1040 { 1041 struct snd_card *card = dev_get_drvdata(dev); 1042 struct azx *chip; 1043 struct hda_intel *hda; 1044 struct hdac_bus *bus; 1045 struct hda_codec *codec; 1046 int status; 1047 1048 if (!card) 1049 return 0; 1050 1051 chip = card->private_data; 1052 hda = container_of(chip, struct hda_intel, chip); 1053 if (chip->disabled || hda->init_failed) 1054 return 0; 1055 1056 if (!azx_has_pm_runtime(chip)) 1057 return 0; 1058 1059 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1060 bus = azx_bus(chip); 1061 if (hda->need_i915_power) { 1062 snd_hdac_display_power(bus, true); 1063 haswell_set_bclk(hda); 1064 } else { 1065 /* toggle codec wakeup bit for STATESTS read */ 1066 snd_hdac_set_codec_wakeup(bus, true); 1067 snd_hdac_set_codec_wakeup(bus, false); 1068 } 1069 } 1070 1071 /* Read STATESTS before controller reset */ 1072 status = azx_readw(chip, STATESTS); 1073 1074 azx_init_pci(chip); 1075 hda_intel_init_chip(chip, true); 1076 1077 if (status) { 1078 list_for_each_codec(codec, &chip->bus) 1079 if (status & (1 << codec->addr)) 1080 schedule_delayed_work(&codec->jackpoll_work, 1081 codec->jackpoll_interval); 1082 } 1083 1084 /* disable controller Wake Up event*/ 1085 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 1086 ~STATESTS_INT_MASK); 1087 1088 trace_azx_runtime_resume(chip); 1089 return 0; 1090 } 1091 1092 static int azx_runtime_idle(struct device *dev) 1093 { 1094 struct snd_card *card = dev_get_drvdata(dev); 1095 struct azx *chip; 1096 struct hda_intel *hda; 1097 1098 if (!card) 1099 return 0; 1100 1101 chip = card->private_data; 1102 hda = container_of(chip, struct hda_intel, chip); 1103 if (chip->disabled || hda->init_failed) 1104 return 0; 1105 1106 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1107 azx_bus(chip)->codec_powered || !chip->running) 1108 return -EBUSY; 1109 1110 return 0; 1111 } 1112 1113 static const struct dev_pm_ops azx_pm = { 1114 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1115 #ifdef CONFIG_PM_SLEEP 1116 .freeze_noirq = azx_freeze_noirq, 1117 .thaw_noirq = azx_thaw_noirq, 1118 #endif 1119 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1120 }; 1121 1122 #define AZX_PM_OPS &azx_pm 1123 #else 1124 #define AZX_PM_OPS NULL 1125 #endif /* CONFIG_PM */ 1126 1127 1128 static int azx_probe_continue(struct azx *chip); 1129 1130 #ifdef SUPPORT_VGA_SWITCHEROO 1131 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1132 1133 static void azx_vs_set_state(struct pci_dev *pci, 1134 enum vga_switcheroo_state state) 1135 { 1136 struct snd_card *card = pci_get_drvdata(pci); 1137 struct azx *chip = card->private_data; 1138 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1139 bool disabled; 1140 1141 wait_for_completion(&hda->probe_wait); 1142 if (hda->init_failed) 1143 return; 1144 1145 disabled = (state == VGA_SWITCHEROO_OFF); 1146 if (chip->disabled == disabled) 1147 return; 1148 1149 if (!hda->probe_continued) { 1150 chip->disabled = disabled; 1151 if (!disabled) { 1152 dev_info(chip->card->dev, 1153 "Start delayed initialization\n"); 1154 if (azx_probe_continue(chip) < 0) { 1155 dev_err(chip->card->dev, "initialization error\n"); 1156 hda->init_failed = true; 1157 } 1158 } 1159 } else { 1160 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1161 disabled ? "Disabling" : "Enabling"); 1162 if (disabled) { 1163 pm_runtime_put_sync_suspend(card->dev); 1164 azx_suspend(card->dev); 1165 /* when we get suspended by vga_switcheroo we end up in D3cold, 1166 * however we have no ACPI handle, so pci/acpi can't put us there, 1167 * put ourselves there */ 1168 pci->current_state = PCI_D3cold; 1169 chip->disabled = true; 1170 if (snd_hda_lock_devices(&chip->bus)) 1171 dev_warn(chip->card->dev, 1172 "Cannot lock devices!\n"); 1173 } else { 1174 snd_hda_unlock_devices(&chip->bus); 1175 pm_runtime_get_noresume(card->dev); 1176 chip->disabled = false; 1177 azx_resume(card->dev); 1178 } 1179 } 1180 } 1181 1182 static bool azx_vs_can_switch(struct pci_dev *pci) 1183 { 1184 struct snd_card *card = pci_get_drvdata(pci); 1185 struct azx *chip = card->private_data; 1186 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1187 1188 wait_for_completion(&hda->probe_wait); 1189 if (hda->init_failed) 1190 return false; 1191 if (chip->disabled || !hda->probe_continued) 1192 return true; 1193 if (snd_hda_lock_devices(&chip->bus)) 1194 return false; 1195 snd_hda_unlock_devices(&chip->bus); 1196 return true; 1197 } 1198 1199 static void init_vga_switcheroo(struct azx *chip) 1200 { 1201 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1202 struct pci_dev *p = get_bound_vga(chip->pci); 1203 if (p) { 1204 dev_info(chip->card->dev, 1205 "Handle vga_switcheroo audio client\n"); 1206 hda->use_vga_switcheroo = 1; 1207 pci_dev_put(p); 1208 } 1209 } 1210 1211 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1212 .set_gpu_state = azx_vs_set_state, 1213 .can_switch = azx_vs_can_switch, 1214 }; 1215 1216 static int register_vga_switcheroo(struct azx *chip) 1217 { 1218 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1219 int err; 1220 1221 if (!hda->use_vga_switcheroo) 1222 return 0; 1223 /* FIXME: currently only handling DIS controller 1224 * is there any machine with two switchable HDMI audio controllers? 1225 */ 1226 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, 1227 VGA_SWITCHEROO_DIS); 1228 if (err < 0) 1229 return err; 1230 hda->vga_switcheroo_registered = 1; 1231 1232 /* register as an optimus hdmi audio power domain */ 1233 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev, 1234 &hda->hdmi_pm_domain); 1235 return 0; 1236 } 1237 #else 1238 #define init_vga_switcheroo(chip) /* NOP */ 1239 #define register_vga_switcheroo(chip) 0 1240 #define check_hdmi_disabled(pci) false 1241 #endif /* SUPPORT_VGA_SWITCHER */ 1242 1243 /* 1244 * destructor 1245 */ 1246 static int azx_free(struct azx *chip) 1247 { 1248 struct pci_dev *pci = chip->pci; 1249 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1250 struct hdac_bus *bus = azx_bus(chip); 1251 1252 if (azx_has_pm_runtime(chip) && chip->running) 1253 pm_runtime_get_noresume(&pci->dev); 1254 1255 azx_del_card_list(chip); 1256 1257 hda->init_failed = 1; /* to be sure */ 1258 complete_all(&hda->probe_wait); 1259 1260 if (use_vga_switcheroo(hda)) { 1261 if (chip->disabled && hda->probe_continued) 1262 snd_hda_unlock_devices(&chip->bus); 1263 if (hda->vga_switcheroo_registered) 1264 vga_switcheroo_unregister_client(chip->pci); 1265 } 1266 1267 if (bus->chip_init) { 1268 azx_clear_irq_pending(chip); 1269 azx_stop_all_streams(chip); 1270 azx_stop_chip(chip); 1271 } 1272 1273 if (bus->irq >= 0) 1274 free_irq(bus->irq, (void*)chip); 1275 if (chip->msi) 1276 pci_disable_msi(chip->pci); 1277 iounmap(bus->remap_addr); 1278 1279 azx_free_stream_pages(chip); 1280 azx_free_streams(chip); 1281 snd_hdac_bus_exit(bus); 1282 1283 if (chip->region_requested) 1284 pci_release_regions(chip->pci); 1285 1286 pci_disable_device(chip->pci); 1287 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1288 release_firmware(chip->fw); 1289 #endif 1290 1291 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1292 if (hda->need_i915_power) 1293 snd_hdac_display_power(bus, false); 1294 snd_hdac_i915_exit(bus); 1295 } 1296 kfree(hda); 1297 1298 return 0; 1299 } 1300 1301 static int azx_dev_disconnect(struct snd_device *device) 1302 { 1303 struct azx *chip = device->device_data; 1304 1305 chip->bus.shutdown = 1; 1306 return 0; 1307 } 1308 1309 static int azx_dev_free(struct snd_device *device) 1310 { 1311 return azx_free(device->device_data); 1312 } 1313 1314 #ifdef SUPPORT_VGA_SWITCHEROO 1315 /* 1316 * Check of disabled HDMI controller by vga_switcheroo 1317 */ 1318 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1319 { 1320 struct pci_dev *p; 1321 1322 /* check only discrete GPU */ 1323 switch (pci->vendor) { 1324 case PCI_VENDOR_ID_ATI: 1325 case PCI_VENDOR_ID_AMD: 1326 case PCI_VENDOR_ID_NVIDIA: 1327 if (pci->devfn == 1) { 1328 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1329 pci->bus->number, 0); 1330 if (p) { 1331 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA) 1332 return p; 1333 pci_dev_put(p); 1334 } 1335 } 1336 break; 1337 } 1338 return NULL; 1339 } 1340 1341 static bool check_hdmi_disabled(struct pci_dev *pci) 1342 { 1343 bool vga_inactive = false; 1344 struct pci_dev *p = get_bound_vga(pci); 1345 1346 if (p) { 1347 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1348 vga_inactive = true; 1349 pci_dev_put(p); 1350 } 1351 return vga_inactive; 1352 } 1353 #endif /* SUPPORT_VGA_SWITCHEROO */ 1354 1355 /* 1356 * white/black-listing for position_fix 1357 */ 1358 static struct snd_pci_quirk position_fix_list[] = { 1359 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1360 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1361 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1362 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1363 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1364 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1365 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1366 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1367 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1368 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1369 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1370 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1371 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1372 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1373 {} 1374 }; 1375 1376 static int check_position_fix(struct azx *chip, int fix) 1377 { 1378 const struct snd_pci_quirk *q; 1379 1380 switch (fix) { 1381 case POS_FIX_AUTO: 1382 case POS_FIX_LPIB: 1383 case POS_FIX_POSBUF: 1384 case POS_FIX_VIACOMBO: 1385 case POS_FIX_COMBO: 1386 return fix; 1387 } 1388 1389 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1390 if (q) { 1391 dev_info(chip->card->dev, 1392 "position_fix set to %d for device %04x:%04x\n", 1393 q->value, q->subvendor, q->subdevice); 1394 return q->value; 1395 } 1396 1397 /* Check VIA/ATI HD Audio Controller exist */ 1398 if (chip->driver_type == AZX_DRIVER_VIA) { 1399 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1400 return POS_FIX_VIACOMBO; 1401 } 1402 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1403 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1404 return POS_FIX_LPIB; 1405 } 1406 return POS_FIX_AUTO; 1407 } 1408 1409 static void assign_position_fix(struct azx *chip, int fix) 1410 { 1411 static azx_get_pos_callback_t callbacks[] = { 1412 [POS_FIX_AUTO] = NULL, 1413 [POS_FIX_LPIB] = azx_get_pos_lpib, 1414 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1415 [POS_FIX_VIACOMBO] = azx_via_get_position, 1416 [POS_FIX_COMBO] = azx_get_pos_lpib, 1417 }; 1418 1419 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1420 1421 /* combo mode uses LPIB only for playback */ 1422 if (fix == POS_FIX_COMBO) 1423 chip->get_position[1] = NULL; 1424 1425 if (fix == POS_FIX_POSBUF && 1426 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1427 chip->get_delay[0] = chip->get_delay[1] = 1428 azx_get_delay_from_lpib; 1429 } 1430 1431 } 1432 1433 /* 1434 * black-lists for probe_mask 1435 */ 1436 static struct snd_pci_quirk probe_mask_list[] = { 1437 /* Thinkpad often breaks the controller communication when accessing 1438 * to the non-working (or non-existing) modem codec slot. 1439 */ 1440 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1441 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1442 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1443 /* broken BIOS */ 1444 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1445 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1446 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1447 /* forced codec slots */ 1448 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1449 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1450 /* WinFast VP200 H (Teradici) user reported broken communication */ 1451 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1452 {} 1453 }; 1454 1455 #define AZX_FORCE_CODEC_MASK 0x100 1456 1457 static void check_probe_mask(struct azx *chip, int dev) 1458 { 1459 const struct snd_pci_quirk *q; 1460 1461 chip->codec_probe_mask = probe_mask[dev]; 1462 if (chip->codec_probe_mask == -1) { 1463 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1464 if (q) { 1465 dev_info(chip->card->dev, 1466 "probe_mask set to 0x%x for device %04x:%04x\n", 1467 q->value, q->subvendor, q->subdevice); 1468 chip->codec_probe_mask = q->value; 1469 } 1470 } 1471 1472 /* check forced option */ 1473 if (chip->codec_probe_mask != -1 && 1474 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1475 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1476 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1477 (int)azx_bus(chip)->codec_mask); 1478 } 1479 } 1480 1481 /* 1482 * white/black-list for enable_msi 1483 */ 1484 static struct snd_pci_quirk msi_black_list[] = { 1485 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1486 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1487 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1488 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1489 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1490 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1491 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1492 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1493 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1494 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1495 {} 1496 }; 1497 1498 static void check_msi(struct azx *chip) 1499 { 1500 const struct snd_pci_quirk *q; 1501 1502 if (enable_msi >= 0) { 1503 chip->msi = !!enable_msi; 1504 return; 1505 } 1506 chip->msi = 1; /* enable MSI as default */ 1507 q = snd_pci_quirk_lookup(chip->pci, msi_black_list); 1508 if (q) { 1509 dev_info(chip->card->dev, 1510 "msi for device %04x:%04x set to %d\n", 1511 q->subvendor, q->subdevice, q->value); 1512 chip->msi = q->value; 1513 return; 1514 } 1515 1516 /* NVidia chipsets seem to cause troubles with MSI */ 1517 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1518 dev_info(chip->card->dev, "Disabling MSI\n"); 1519 chip->msi = 0; 1520 } 1521 } 1522 1523 /* check the snoop mode availability */ 1524 static void azx_check_snoop_available(struct azx *chip) 1525 { 1526 int snoop = hda_snoop; 1527 1528 if (snoop >= 0) { 1529 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1530 snoop ? "snoop" : "non-snoop"); 1531 chip->snoop = snoop; 1532 return; 1533 } 1534 1535 snoop = true; 1536 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1537 chip->driver_type == AZX_DRIVER_VIA) { 1538 /* force to non-snoop mode for a new VIA controller 1539 * when BIOS is set 1540 */ 1541 u8 val; 1542 pci_read_config_byte(chip->pci, 0x42, &val); 1543 if (!(val & 0x80) && chip->pci->revision == 0x30) 1544 snoop = false; 1545 } 1546 1547 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1548 snoop = false; 1549 1550 chip->snoop = snoop; 1551 if (!snoop) 1552 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1553 } 1554 1555 static void azx_probe_work(struct work_struct *work) 1556 { 1557 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work); 1558 azx_probe_continue(&hda->chip); 1559 } 1560 1561 static int default_bdl_pos_adj(struct azx *chip) 1562 { 1563 /* some exceptions: Atoms seem problematic with value 1 */ 1564 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { 1565 switch (chip->pci->device) { 1566 case 0x0f04: /* Baytrail */ 1567 case 0x2284: /* Braswell */ 1568 return 32; 1569 } 1570 } 1571 1572 switch (chip->driver_type) { 1573 case AZX_DRIVER_ICH: 1574 case AZX_DRIVER_PCH: 1575 return 1; 1576 default: 1577 return 32; 1578 } 1579 } 1580 1581 /* 1582 * constructor 1583 */ 1584 static const struct hdac_io_ops pci_hda_io_ops; 1585 static const struct hda_controller_ops pci_hda_ops; 1586 1587 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1588 int dev, unsigned int driver_caps, 1589 struct azx **rchip) 1590 { 1591 static struct snd_device_ops ops = { 1592 .dev_disconnect = azx_dev_disconnect, 1593 .dev_free = azx_dev_free, 1594 }; 1595 struct hda_intel *hda; 1596 struct azx *chip; 1597 int err; 1598 1599 *rchip = NULL; 1600 1601 err = pci_enable_device(pci); 1602 if (err < 0) 1603 return err; 1604 1605 hda = kzalloc(sizeof(*hda), GFP_KERNEL); 1606 if (!hda) { 1607 pci_disable_device(pci); 1608 return -ENOMEM; 1609 } 1610 1611 chip = &hda->chip; 1612 mutex_init(&chip->open_mutex); 1613 chip->card = card; 1614 chip->pci = pci; 1615 chip->ops = &pci_hda_ops; 1616 chip->driver_caps = driver_caps; 1617 chip->driver_type = driver_caps & 0xff; 1618 check_msi(chip); 1619 chip->dev_index = dev; 1620 chip->jackpoll_ms = jackpoll_ms; 1621 INIT_LIST_HEAD(&chip->pcm_list); 1622 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1623 INIT_LIST_HEAD(&hda->list); 1624 init_vga_switcheroo(chip); 1625 init_completion(&hda->probe_wait); 1626 1627 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1628 1629 check_probe_mask(chip, dev); 1630 1631 chip->single_cmd = single_cmd; 1632 azx_check_snoop_available(chip); 1633 1634 if (bdl_pos_adj[dev] < 0) 1635 chip->bdl_pos_adj = default_bdl_pos_adj(chip); 1636 else 1637 chip->bdl_pos_adj = bdl_pos_adj[dev]; 1638 1639 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops); 1640 if (err < 0) { 1641 kfree(hda); 1642 pci_disable_device(pci); 1643 return err; 1644 } 1645 1646 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 1647 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); 1648 chip->bus.needs_damn_long_delay = 1; 1649 } 1650 1651 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1652 if (err < 0) { 1653 dev_err(card->dev, "Error creating device [card]!\n"); 1654 azx_free(chip); 1655 return err; 1656 } 1657 1658 /* continue probing in work context as may trigger request module */ 1659 INIT_WORK(&hda->probe_work, azx_probe_work); 1660 1661 *rchip = chip; 1662 1663 return 0; 1664 } 1665 1666 static int azx_first_init(struct azx *chip) 1667 { 1668 int dev = chip->dev_index; 1669 struct pci_dev *pci = chip->pci; 1670 struct snd_card *card = chip->card; 1671 struct hdac_bus *bus = azx_bus(chip); 1672 int err; 1673 unsigned short gcap; 1674 unsigned int dma_bits = 64; 1675 1676 #if BITS_PER_LONG != 64 1677 /* Fix up base address on ULI M5461 */ 1678 if (chip->driver_type == AZX_DRIVER_ULI) { 1679 u16 tmp3; 1680 pci_read_config_word(pci, 0x40, &tmp3); 1681 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1682 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1683 } 1684 #endif 1685 1686 err = pci_request_regions(pci, "ICH HD audio"); 1687 if (err < 0) 1688 return err; 1689 chip->region_requested = 1; 1690 1691 bus->addr = pci_resource_start(pci, 0); 1692 bus->remap_addr = pci_ioremap_bar(pci, 0); 1693 if (bus->remap_addr == NULL) { 1694 dev_err(card->dev, "ioremap error\n"); 1695 return -ENXIO; 1696 } 1697 1698 if (chip->msi) { 1699 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1700 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1701 pci->no_64bit_msi = true; 1702 } 1703 if (pci_enable_msi(pci) < 0) 1704 chip->msi = 0; 1705 } 1706 1707 if (azx_acquire_irq(chip, 0) < 0) 1708 return -EBUSY; 1709 1710 pci_set_master(pci); 1711 synchronize_irq(bus->irq); 1712 1713 gcap = azx_readw(chip, GCAP); 1714 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1715 1716 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1717 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1718 dma_bits = 40; 1719 1720 /* disable SB600 64bit support for safety */ 1721 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1722 struct pci_dev *p_smbus; 1723 dma_bits = 40; 1724 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1725 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1726 NULL); 1727 if (p_smbus) { 1728 if (p_smbus->revision < 0x30) 1729 gcap &= ~AZX_GCAP_64OK; 1730 pci_dev_put(p_smbus); 1731 } 1732 } 1733 1734 /* disable 64bit DMA address on some devices */ 1735 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1736 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1737 gcap &= ~AZX_GCAP_64OK; 1738 } 1739 1740 /* disable buffer size rounding to 128-byte multiples if supported */ 1741 if (align_buffer_size >= 0) 1742 chip->align_buffer_size = !!align_buffer_size; 1743 else { 1744 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1745 chip->align_buffer_size = 0; 1746 else 1747 chip->align_buffer_size = 1; 1748 } 1749 1750 /* allow 64bit DMA address if supported by H/W */ 1751 if (!(gcap & AZX_GCAP_64OK)) 1752 dma_bits = 32; 1753 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) { 1754 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits)); 1755 } else { 1756 dma_set_mask(&pci->dev, DMA_BIT_MASK(32)); 1757 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32)); 1758 } 1759 1760 /* read number of streams from GCAP register instead of using 1761 * hardcoded value 1762 */ 1763 chip->capture_streams = (gcap >> 8) & 0x0f; 1764 chip->playback_streams = (gcap >> 12) & 0x0f; 1765 if (!chip->playback_streams && !chip->capture_streams) { 1766 /* gcap didn't give any info, switching to old method */ 1767 1768 switch (chip->driver_type) { 1769 case AZX_DRIVER_ULI: 1770 chip->playback_streams = ULI_NUM_PLAYBACK; 1771 chip->capture_streams = ULI_NUM_CAPTURE; 1772 break; 1773 case AZX_DRIVER_ATIHDMI: 1774 case AZX_DRIVER_ATIHDMI_NS: 1775 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1776 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1777 break; 1778 case AZX_DRIVER_GENERIC: 1779 default: 1780 chip->playback_streams = ICH6_NUM_PLAYBACK; 1781 chip->capture_streams = ICH6_NUM_CAPTURE; 1782 break; 1783 } 1784 } 1785 chip->capture_index_offset = 0; 1786 chip->playback_index_offset = chip->capture_streams; 1787 chip->num_streams = chip->playback_streams + chip->capture_streams; 1788 1789 /* initialize streams */ 1790 err = azx_init_streams(chip); 1791 if (err < 0) 1792 return err; 1793 1794 err = azx_alloc_stream_pages(chip); 1795 if (err < 0) 1796 return err; 1797 1798 /* initialize chip */ 1799 azx_init_pci(chip); 1800 1801 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1802 struct hda_intel *hda; 1803 1804 hda = container_of(chip, struct hda_intel, chip); 1805 haswell_set_bclk(hda); 1806 } 1807 1808 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 1809 1810 /* codec detection */ 1811 if (!azx_bus(chip)->codec_mask) { 1812 dev_err(card->dev, "no codecs found!\n"); 1813 return -ENODEV; 1814 } 1815 1816 strcpy(card->driver, "HDA-Intel"); 1817 strlcpy(card->shortname, driver_short_names[chip->driver_type], 1818 sizeof(card->shortname)); 1819 snprintf(card->longname, sizeof(card->longname), 1820 "%s at 0x%lx irq %i", 1821 card->shortname, bus->addr, bus->irq); 1822 1823 return 0; 1824 } 1825 1826 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1827 /* callback from request_firmware_nowait() */ 1828 static void azx_firmware_cb(const struct firmware *fw, void *context) 1829 { 1830 struct snd_card *card = context; 1831 struct azx *chip = card->private_data; 1832 struct pci_dev *pci = chip->pci; 1833 1834 if (!fw) { 1835 dev_err(card->dev, "Cannot load firmware, aborting\n"); 1836 goto error; 1837 } 1838 1839 chip->fw = fw; 1840 if (!chip->disabled) { 1841 /* continue probing */ 1842 if (azx_probe_continue(chip)) 1843 goto error; 1844 } 1845 return; /* OK */ 1846 1847 error: 1848 snd_card_free(card); 1849 pci_set_drvdata(pci, NULL); 1850 } 1851 #endif 1852 1853 /* 1854 * HDA controller ops. 1855 */ 1856 1857 /* PCI register access. */ 1858 static void pci_azx_writel(u32 value, u32 __iomem *addr) 1859 { 1860 writel(value, addr); 1861 } 1862 1863 static u32 pci_azx_readl(u32 __iomem *addr) 1864 { 1865 return readl(addr); 1866 } 1867 1868 static void pci_azx_writew(u16 value, u16 __iomem *addr) 1869 { 1870 writew(value, addr); 1871 } 1872 1873 static u16 pci_azx_readw(u16 __iomem *addr) 1874 { 1875 return readw(addr); 1876 } 1877 1878 static void pci_azx_writeb(u8 value, u8 __iomem *addr) 1879 { 1880 writeb(value, addr); 1881 } 1882 1883 static u8 pci_azx_readb(u8 __iomem *addr) 1884 { 1885 return readb(addr); 1886 } 1887 1888 static int disable_msi_reset_irq(struct azx *chip) 1889 { 1890 struct hdac_bus *bus = azx_bus(chip); 1891 int err; 1892 1893 free_irq(bus->irq, chip); 1894 bus->irq = -1; 1895 pci_disable_msi(chip->pci); 1896 chip->msi = 0; 1897 err = azx_acquire_irq(chip, 1); 1898 if (err < 0) 1899 return err; 1900 1901 return 0; 1902 } 1903 1904 /* DMA page allocation helpers. */ 1905 static int dma_alloc_pages(struct hdac_bus *bus, 1906 int type, 1907 size_t size, 1908 struct snd_dma_buffer *buf) 1909 { 1910 struct azx *chip = bus_to_azx(bus); 1911 int err; 1912 1913 err = snd_dma_alloc_pages(type, 1914 bus->dev, 1915 size, buf); 1916 if (err < 0) 1917 return err; 1918 mark_pages_wc(chip, buf, true); 1919 return 0; 1920 } 1921 1922 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf) 1923 { 1924 struct azx *chip = bus_to_azx(bus); 1925 1926 mark_pages_wc(chip, buf, false); 1927 snd_dma_free_pages(buf); 1928 } 1929 1930 static int substream_alloc_pages(struct azx *chip, 1931 struct snd_pcm_substream *substream, 1932 size_t size) 1933 { 1934 struct azx_dev *azx_dev = get_azx_dev(substream); 1935 int ret; 1936 1937 mark_runtime_wc(chip, azx_dev, substream, false); 1938 ret = snd_pcm_lib_malloc_pages(substream, size); 1939 if (ret < 0) 1940 return ret; 1941 mark_runtime_wc(chip, azx_dev, substream, true); 1942 return 0; 1943 } 1944 1945 static int substream_free_pages(struct azx *chip, 1946 struct snd_pcm_substream *substream) 1947 { 1948 struct azx_dev *azx_dev = get_azx_dev(substream); 1949 mark_runtime_wc(chip, azx_dev, substream, false); 1950 return snd_pcm_lib_free_pages(substream); 1951 } 1952 1953 static void pcm_mmap_prepare(struct snd_pcm_substream *substream, 1954 struct vm_area_struct *area) 1955 { 1956 #ifdef CONFIG_X86 1957 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1958 struct azx *chip = apcm->chip; 1959 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA) 1960 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); 1961 #endif 1962 } 1963 1964 static const struct hdac_io_ops pci_hda_io_ops = { 1965 .reg_writel = pci_azx_writel, 1966 .reg_readl = pci_azx_readl, 1967 .reg_writew = pci_azx_writew, 1968 .reg_readw = pci_azx_readw, 1969 .reg_writeb = pci_azx_writeb, 1970 .reg_readb = pci_azx_readb, 1971 .dma_alloc_pages = dma_alloc_pages, 1972 .dma_free_pages = dma_free_pages, 1973 }; 1974 1975 static const struct hda_controller_ops pci_hda_ops = { 1976 .disable_msi_reset_irq = disable_msi_reset_irq, 1977 .substream_alloc_pages = substream_alloc_pages, 1978 .substream_free_pages = substream_free_pages, 1979 .pcm_mmap_prepare = pcm_mmap_prepare, 1980 .position_check = azx_position_check, 1981 .link_power = azx_intel_link_power, 1982 }; 1983 1984 static int azx_probe(struct pci_dev *pci, 1985 const struct pci_device_id *pci_id) 1986 { 1987 static int dev; 1988 struct snd_card *card; 1989 struct hda_intel *hda; 1990 struct azx *chip; 1991 bool schedule_probe; 1992 int err; 1993 1994 if (dev >= SNDRV_CARDS) 1995 return -ENODEV; 1996 if (!enable[dev]) { 1997 dev++; 1998 return -ENOENT; 1999 } 2000 2001 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2002 0, &card); 2003 if (err < 0) { 2004 dev_err(&pci->dev, "Error creating card!\n"); 2005 return err; 2006 } 2007 2008 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2009 if (err < 0) 2010 goto out_free; 2011 card->private_data = chip; 2012 hda = container_of(chip, struct hda_intel, chip); 2013 2014 pci_set_drvdata(pci, card); 2015 2016 err = register_vga_switcheroo(chip); 2017 if (err < 0) { 2018 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 2019 goto out_free; 2020 } 2021 2022 if (check_hdmi_disabled(pci)) { 2023 dev_info(card->dev, "VGA controller is disabled\n"); 2024 dev_info(card->dev, "Delaying initialization\n"); 2025 chip->disabled = true; 2026 } 2027 2028 schedule_probe = !chip->disabled; 2029 2030 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2031 if (patch[dev] && *patch[dev]) { 2032 dev_info(card->dev, "Applying patch firmware '%s'\n", 2033 patch[dev]); 2034 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 2035 &pci->dev, GFP_KERNEL, card, 2036 azx_firmware_cb); 2037 if (err < 0) 2038 goto out_free; 2039 schedule_probe = false; /* continued in azx_firmware_cb() */ 2040 } 2041 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 2042 2043 #ifndef CONFIG_SND_HDA_I915 2044 if (CONTROLLER_IN_GPU(pci)) 2045 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); 2046 #endif 2047 2048 if (schedule_probe) 2049 schedule_work(&hda->probe_work); 2050 2051 dev++; 2052 if (chip->disabled) 2053 complete_all(&hda->probe_wait); 2054 return 0; 2055 2056 out_free: 2057 snd_card_free(card); 2058 return err; 2059 } 2060 2061 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 2062 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 2063 [AZX_DRIVER_NVIDIA] = 8, 2064 [AZX_DRIVER_TERA] = 1, 2065 }; 2066 2067 static int azx_probe_continue(struct azx *chip) 2068 { 2069 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2070 struct hdac_bus *bus = azx_bus(chip); 2071 struct pci_dev *pci = chip->pci; 2072 int dev = chip->dev_index; 2073 int err; 2074 2075 hda->probe_continued = 1; 2076 2077 /* Request display power well for the HDA controller or codec. For 2078 * Haswell/Broadwell, both the display HDA controller and codec need 2079 * this power. For other platforms, like Baytrail/Braswell, only the 2080 * display codec needs the power and it can be released after probe. 2081 */ 2082 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 2083 /* HSW/BDW controllers need this power */ 2084 if (CONTROLLER_IN_GPU(pci)) 2085 hda->need_i915_power = 1; 2086 2087 err = snd_hdac_i915_init(bus); 2088 if (err < 0) { 2089 /* if the controller is bound only with HDMI/DP 2090 * (for HSW and BDW), we need to abort the probe; 2091 * for other chips, still continue probing as other 2092 * codecs can be on the same link. 2093 */ 2094 if (CONTROLLER_IN_GPU(pci)) { 2095 dev_err(chip->card->dev, 2096 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); 2097 goto out_free; 2098 } else 2099 goto skip_i915; 2100 } 2101 2102 err = snd_hdac_display_power(bus, true); 2103 if (err < 0) { 2104 dev_err(chip->card->dev, 2105 "Cannot turn on display power on i915\n"); 2106 goto i915_power_fail; 2107 } 2108 } 2109 2110 skip_i915: 2111 err = azx_first_init(chip); 2112 if (err < 0) 2113 goto out_free; 2114 2115 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2116 chip->beep_mode = beep_mode[dev]; 2117 #endif 2118 2119 /* create codec instances */ 2120 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2121 if (err < 0) 2122 goto out_free; 2123 2124 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2125 if (chip->fw) { 2126 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2127 chip->fw->data); 2128 if (err < 0) 2129 goto out_free; 2130 #ifndef CONFIG_PM 2131 release_firmware(chip->fw); /* no longer needed */ 2132 chip->fw = NULL; 2133 #endif 2134 } 2135 #endif 2136 if ((probe_only[dev] & 1) == 0) { 2137 err = azx_codec_configure(chip); 2138 if (err < 0) 2139 goto out_free; 2140 } 2141 2142 err = snd_card_register(chip->card); 2143 if (err < 0) 2144 goto out_free; 2145 2146 chip->running = 1; 2147 azx_add_card_list(chip); 2148 snd_hda_set_power_save(&chip->bus, power_save * 1000); 2149 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo) 2150 pm_runtime_put_noidle(&pci->dev); 2151 2152 out_free: 2153 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL 2154 && !hda->need_i915_power) 2155 snd_hdac_display_power(bus, false); 2156 2157 i915_power_fail: 2158 if (err < 0) 2159 hda->init_failed = 1; 2160 complete_all(&hda->probe_wait); 2161 return err; 2162 } 2163 2164 static void azx_remove(struct pci_dev *pci) 2165 { 2166 struct snd_card *card = pci_get_drvdata(pci); 2167 struct azx *chip; 2168 struct hda_intel *hda; 2169 2170 if (card) { 2171 /* flush the pending probing work */ 2172 chip = card->private_data; 2173 hda = container_of(chip, struct hda_intel, chip); 2174 flush_work(&hda->probe_work); 2175 2176 snd_card_free(card); 2177 } 2178 } 2179 2180 static void azx_shutdown(struct pci_dev *pci) 2181 { 2182 struct snd_card *card = pci_get_drvdata(pci); 2183 struct azx *chip; 2184 2185 if (!card) 2186 return; 2187 chip = card->private_data; 2188 if (chip && chip->running) 2189 azx_stop_chip(chip); 2190 } 2191 2192 /* PCI IDs */ 2193 static const struct pci_device_id azx_ids[] = { 2194 /* CPT */ 2195 { PCI_DEVICE(0x8086, 0x1c20), 2196 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2197 /* PBG */ 2198 { PCI_DEVICE(0x8086, 0x1d20), 2199 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2200 /* Panther Point */ 2201 { PCI_DEVICE(0x8086, 0x1e20), 2202 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2203 /* Lynx Point */ 2204 { PCI_DEVICE(0x8086, 0x8c20), 2205 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2206 /* 9 Series */ 2207 { PCI_DEVICE(0x8086, 0x8ca0), 2208 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2209 /* Wellsburg */ 2210 { PCI_DEVICE(0x8086, 0x8d20), 2211 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2212 { PCI_DEVICE(0x8086, 0x8d21), 2213 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2214 /* Lewisburg */ 2215 { PCI_DEVICE(0x8086, 0xa1f0), 2216 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2217 { PCI_DEVICE(0x8086, 0xa270), 2218 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2219 /* Lynx Point-LP */ 2220 { PCI_DEVICE(0x8086, 0x9c20), 2221 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2222 /* Lynx Point-LP */ 2223 { PCI_DEVICE(0x8086, 0x9c21), 2224 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2225 /* Wildcat Point-LP */ 2226 { PCI_DEVICE(0x8086, 0x9ca0), 2227 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2228 /* Sunrise Point */ 2229 { PCI_DEVICE(0x8086, 0xa170), 2230 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2231 /* Sunrise Point-LP */ 2232 { PCI_DEVICE(0x8086, 0x9d70), 2233 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2234 /* Broxton-P(Apollolake) */ 2235 { PCI_DEVICE(0x8086, 0x5a98), 2236 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON }, 2237 /* Haswell */ 2238 { PCI_DEVICE(0x8086, 0x0a0c), 2239 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2240 { PCI_DEVICE(0x8086, 0x0c0c), 2241 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2242 { PCI_DEVICE(0x8086, 0x0d0c), 2243 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2244 /* Broadwell */ 2245 { PCI_DEVICE(0x8086, 0x160c), 2246 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 2247 /* 5 Series/3400 */ 2248 { PCI_DEVICE(0x8086, 0x3b56), 2249 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2250 /* Poulsbo */ 2251 { PCI_DEVICE(0x8086, 0x811b), 2252 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2253 /* Oaktrail */ 2254 { PCI_DEVICE(0x8086, 0x080a), 2255 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2256 /* BayTrail */ 2257 { PCI_DEVICE(0x8086, 0x0f04), 2258 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL }, 2259 /* Braswell */ 2260 { PCI_DEVICE(0x8086, 0x2284), 2261 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL }, 2262 /* ICH6 */ 2263 { PCI_DEVICE(0x8086, 0x2668), 2264 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2265 /* ICH7 */ 2266 { PCI_DEVICE(0x8086, 0x27d8), 2267 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2268 /* ESB2 */ 2269 { PCI_DEVICE(0x8086, 0x269a), 2270 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2271 /* ICH8 */ 2272 { PCI_DEVICE(0x8086, 0x284b), 2273 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2274 /* ICH9 */ 2275 { PCI_DEVICE(0x8086, 0x293e), 2276 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2277 /* ICH9 */ 2278 { PCI_DEVICE(0x8086, 0x293f), 2279 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2280 /* ICH10 */ 2281 { PCI_DEVICE(0x8086, 0x3a3e), 2282 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2283 /* ICH10 */ 2284 { PCI_DEVICE(0x8086, 0x3a6e), 2285 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2286 /* Generic Intel */ 2287 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2288 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2289 .class_mask = 0xffffff, 2290 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2291 /* ATI SB 450/600/700/800/900 */ 2292 { PCI_DEVICE(0x1002, 0x437b), 2293 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2294 { PCI_DEVICE(0x1002, 0x4383), 2295 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2296 /* AMD Hudson */ 2297 { PCI_DEVICE(0x1022, 0x780d), 2298 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2299 /* ATI HDMI */ 2300 { PCI_DEVICE(0x1002, 0x1308), 2301 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2302 { PCI_DEVICE(0x1002, 0x157a), 2303 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2304 { PCI_DEVICE(0x1002, 0x793b), 2305 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2306 { PCI_DEVICE(0x1002, 0x7919), 2307 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2308 { PCI_DEVICE(0x1002, 0x960f), 2309 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2310 { PCI_DEVICE(0x1002, 0x970f), 2311 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2312 { PCI_DEVICE(0x1002, 0x9840), 2313 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2314 { PCI_DEVICE(0x1002, 0xaa00), 2315 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2316 { PCI_DEVICE(0x1002, 0xaa08), 2317 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2318 { PCI_DEVICE(0x1002, 0xaa10), 2319 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2320 { PCI_DEVICE(0x1002, 0xaa18), 2321 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2322 { PCI_DEVICE(0x1002, 0xaa20), 2323 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2324 { PCI_DEVICE(0x1002, 0xaa28), 2325 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2326 { PCI_DEVICE(0x1002, 0xaa30), 2327 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2328 { PCI_DEVICE(0x1002, 0xaa38), 2329 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2330 { PCI_DEVICE(0x1002, 0xaa40), 2331 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2332 { PCI_DEVICE(0x1002, 0xaa48), 2333 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2334 { PCI_DEVICE(0x1002, 0xaa50), 2335 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2336 { PCI_DEVICE(0x1002, 0xaa58), 2337 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2338 { PCI_DEVICE(0x1002, 0xaa60), 2339 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2340 { PCI_DEVICE(0x1002, 0xaa68), 2341 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2342 { PCI_DEVICE(0x1002, 0xaa80), 2343 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2344 { PCI_DEVICE(0x1002, 0xaa88), 2345 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2346 { PCI_DEVICE(0x1002, 0xaa90), 2347 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2348 { PCI_DEVICE(0x1002, 0xaa98), 2349 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2350 { PCI_DEVICE(0x1002, 0x9902), 2351 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2352 { PCI_DEVICE(0x1002, 0xaaa0), 2353 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2354 { PCI_DEVICE(0x1002, 0xaaa8), 2355 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2356 { PCI_DEVICE(0x1002, 0xaab0), 2357 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2358 { PCI_DEVICE(0x1002, 0xaac0), 2359 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2360 { PCI_DEVICE(0x1002, 0xaac8), 2361 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2362 { PCI_DEVICE(0x1002, 0xaad8), 2363 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2364 { PCI_DEVICE(0x1002, 0xaae8), 2365 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2366 /* VIA VT8251/VT8237A */ 2367 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2368 /* VIA GFX VT7122/VX900 */ 2369 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2370 /* VIA GFX VT6122/VX11 */ 2371 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2372 /* SIS966 */ 2373 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2374 /* ULI M5461 */ 2375 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2376 /* NVIDIA MCP */ 2377 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2378 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2379 .class_mask = 0xffffff, 2380 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2381 /* Teradici */ 2382 { PCI_DEVICE(0x6549, 0x1200), 2383 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2384 { PCI_DEVICE(0x6549, 0x2200), 2385 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2386 /* Creative X-Fi (CA0110-IBG) */ 2387 /* CTHDA chips */ 2388 { PCI_DEVICE(0x1102, 0x0010), 2389 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2390 { PCI_DEVICE(0x1102, 0x0012), 2391 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2392 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2393 /* the following entry conflicts with snd-ctxfi driver, 2394 * as ctxfi driver mutates from HD-audio to native mode with 2395 * a special command sequence. 2396 */ 2397 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2398 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2399 .class_mask = 0xffffff, 2400 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2401 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2402 #else 2403 /* this entry seems still valid -- i.e. without emu20kx chip */ 2404 { PCI_DEVICE(0x1102, 0x0009), 2405 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2406 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2407 #endif 2408 /* CM8888 */ 2409 { PCI_DEVICE(0x13f6, 0x5011), 2410 .driver_data = AZX_DRIVER_CMEDIA | 2411 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2412 /* Vortex86MX */ 2413 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2414 /* VMware HDAudio */ 2415 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2416 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2417 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2418 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2419 .class_mask = 0xffffff, 2420 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2421 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2422 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2423 .class_mask = 0xffffff, 2424 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2425 { 0, } 2426 }; 2427 MODULE_DEVICE_TABLE(pci, azx_ids); 2428 2429 /* pci_driver definition */ 2430 static struct pci_driver azx_driver = { 2431 .name = KBUILD_MODNAME, 2432 .id_table = azx_ids, 2433 .probe = azx_probe, 2434 .remove = azx_remove, 2435 .shutdown = azx_shutdown, 2436 .driver = { 2437 .pm = AZX_PM_OPS, 2438 }, 2439 }; 2440 2441 module_pci_driver(azx_driver); 2442