1 /* 2 * 3 * hda_intel.c - Implementation of primary alsa driver code base 4 * for Intel HD Audio. 5 * 6 * Copyright(c) 2004 Intel Corporation. All rights reserved. 7 * 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the Free 13 * Software Foundation; either version 2 of the License, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 * 21 * You should have received a copy of the GNU General Public License along with 22 * this program; if not, write to the Free Software Foundation, Inc., 59 23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 24 * 25 * CONTACTS: 26 * 27 * Matt Jared matt.jared@intel.com 28 * Andy Kopp andy.kopp@intel.com 29 * Dan Kogan dan.d.kogan@intel.com 30 * 31 * CHANGES: 32 * 33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 34 * 35 */ 36 37 #include <asm/io.h> 38 #include <linux/delay.h> 39 #include <linux/interrupt.h> 40 #include <linux/kernel.h> 41 #include <linux/module.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/moduleparam.h> 44 #include <linux/init.h> 45 #include <linux/slab.h> 46 #include <linux/pci.h> 47 #include <linux/mutex.h> 48 #include <linux/reboot.h> 49 #include <sound/core.h> 50 #include <sound/initval.h> 51 #include "hda_codec.h" 52 53 54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 57 static char *model[SNDRV_CARDS]; 58 static int position_fix[SNDRV_CARDS]; 59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 61 static int probe_only[SNDRV_CARDS]; 62 static int single_cmd; 63 static int enable_msi = -1; 64 #ifdef CONFIG_SND_HDA_PATCH_LOADER 65 static char *patch[SNDRV_CARDS]; 66 #endif 67 #ifdef CONFIG_SND_HDA_INPUT_BEEP 68 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 69 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 70 #endif 71 72 module_param_array(index, int, NULL, 0444); 73 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 74 module_param_array(id, charp, NULL, 0444); 75 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 76 module_param_array(enable, bool, NULL, 0444); 77 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 78 module_param_array(model, charp, NULL, 0444); 79 MODULE_PARM_DESC(model, "Use the given board model."); 80 module_param_array(position_fix, int, NULL, 0444); 81 MODULE_PARM_DESC(position_fix, "Fix DMA pointer " 82 "(0 = auto, 1 = none, 2 = POSBUF)."); 83 module_param_array(bdl_pos_adj, int, NULL, 0644); 84 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 85 module_param_array(probe_mask, int, NULL, 0444); 86 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 87 module_param_array(probe_only, bool, NULL, 0444); 88 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 89 module_param(single_cmd, bool, 0444); 90 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 91 "(for debugging only)."); 92 module_param(enable_msi, int, 0444); 93 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 94 #ifdef CONFIG_SND_HDA_PATCH_LOADER 95 module_param_array(patch, charp, NULL, 0444); 96 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 97 #endif 98 #ifdef CONFIG_SND_HDA_INPUT_BEEP 99 module_param_array(beep_mode, int, NULL, 0444); 100 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 101 "(0=off, 1=on, 2=mute switch on/off) (default=1)."); 102 #endif 103 104 #ifdef CONFIG_SND_HDA_POWER_SAVE 105 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 106 module_param(power_save, int, 0644); 107 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 108 "(in second, 0 = disable)."); 109 110 /* reset the HD-audio controller in power save mode. 111 * this may give more power-saving, but will take longer time to 112 * wake up. 113 */ 114 static int power_save_controller = 1; 115 module_param(power_save_controller, bool, 0644); 116 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 117 #endif 118 119 MODULE_LICENSE("GPL"); 120 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 121 "{Intel, ICH6M}," 122 "{Intel, ICH7}," 123 "{Intel, ESB2}," 124 "{Intel, ICH8}," 125 "{Intel, ICH9}," 126 "{Intel, ICH10}," 127 "{Intel, PCH}," 128 "{Intel, SCH}," 129 "{ATI, SB450}," 130 "{ATI, SB600}," 131 "{ATI, RS600}," 132 "{ATI, RS690}," 133 "{ATI, RS780}," 134 "{ATI, R600}," 135 "{ATI, RV630}," 136 "{ATI, RV610}," 137 "{ATI, RV670}," 138 "{ATI, RV635}," 139 "{ATI, RV620}," 140 "{ATI, RV770}," 141 "{VIA, VT8251}," 142 "{VIA, VT8237A}," 143 "{SiS, SIS966}," 144 "{ULI, M5461}}"); 145 MODULE_DESCRIPTION("Intel HDA driver"); 146 147 #ifdef CONFIG_SND_VERBOSE_PRINTK 148 #define SFX /* nop */ 149 #else 150 #define SFX "hda-intel: " 151 #endif 152 153 /* 154 * registers 155 */ 156 #define ICH6_REG_GCAP 0x00 157 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */ 158 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */ 159 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */ 160 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */ 161 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */ 162 #define ICH6_REG_VMIN 0x02 163 #define ICH6_REG_VMAJ 0x03 164 #define ICH6_REG_OUTPAY 0x04 165 #define ICH6_REG_INPAY 0x06 166 #define ICH6_REG_GCTL 0x08 167 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */ 168 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */ 169 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */ 170 #define ICH6_REG_WAKEEN 0x0c 171 #define ICH6_REG_STATESTS 0x0e 172 #define ICH6_REG_GSTS 0x10 173 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */ 174 #define ICH6_REG_INTCTL 0x20 175 #define ICH6_REG_INTSTS 0x24 176 #define ICH6_REG_WALCLK 0x30 177 #define ICH6_REG_SYNC 0x34 178 #define ICH6_REG_CORBLBASE 0x40 179 #define ICH6_REG_CORBUBASE 0x44 180 #define ICH6_REG_CORBWP 0x48 181 #define ICH6_REG_CORBRP 0x4a 182 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */ 183 #define ICH6_REG_CORBCTL 0x4c 184 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */ 185 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */ 186 #define ICH6_REG_CORBSTS 0x4d 187 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */ 188 #define ICH6_REG_CORBSIZE 0x4e 189 190 #define ICH6_REG_RIRBLBASE 0x50 191 #define ICH6_REG_RIRBUBASE 0x54 192 #define ICH6_REG_RIRBWP 0x58 193 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */ 194 #define ICH6_REG_RINTCNT 0x5a 195 #define ICH6_REG_RIRBCTL 0x5c 196 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */ 197 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */ 198 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */ 199 #define ICH6_REG_RIRBSTS 0x5d 200 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */ 201 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */ 202 #define ICH6_REG_RIRBSIZE 0x5e 203 204 #define ICH6_REG_IC 0x60 205 #define ICH6_REG_IR 0x64 206 #define ICH6_REG_IRS 0x68 207 #define ICH6_IRS_VALID (1<<1) 208 #define ICH6_IRS_BUSY (1<<0) 209 210 #define ICH6_REG_DPLBASE 0x70 211 #define ICH6_REG_DPUBASE 0x74 212 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */ 213 214 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ 215 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; 216 217 /* stream register offsets from stream base */ 218 #define ICH6_REG_SD_CTL 0x00 219 #define ICH6_REG_SD_STS 0x03 220 #define ICH6_REG_SD_LPIB 0x04 221 #define ICH6_REG_SD_CBL 0x08 222 #define ICH6_REG_SD_LVI 0x0c 223 #define ICH6_REG_SD_FIFOW 0x0e 224 #define ICH6_REG_SD_FIFOSIZE 0x10 225 #define ICH6_REG_SD_FORMAT 0x12 226 #define ICH6_REG_SD_BDLPL 0x18 227 #define ICH6_REG_SD_BDLPU 0x1c 228 229 /* PCI space */ 230 #define ICH6_PCIREG_TCSEL 0x44 231 232 /* 233 * other constants 234 */ 235 236 /* max number of SDs */ 237 /* ICH, ATI and VIA have 4 playback and 4 capture */ 238 #define ICH6_NUM_CAPTURE 4 239 #define ICH6_NUM_PLAYBACK 4 240 241 /* ULI has 6 playback and 5 capture */ 242 #define ULI_NUM_CAPTURE 5 243 #define ULI_NUM_PLAYBACK 6 244 245 /* ATI HDMI has 1 playback and 0 capture */ 246 #define ATIHDMI_NUM_CAPTURE 0 247 #define ATIHDMI_NUM_PLAYBACK 1 248 249 /* TERA has 4 playback and 3 capture */ 250 #define TERA_NUM_CAPTURE 3 251 #define TERA_NUM_PLAYBACK 4 252 253 /* this number is statically defined for simplicity */ 254 #define MAX_AZX_DEV 16 255 256 /* max number of fragments - we may use more if allocating more pages for BDL */ 257 #define BDL_SIZE 4096 258 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16) 259 #define AZX_MAX_FRAG 32 260 /* max buffer size - no h/w limit, you can increase as you like */ 261 #define AZX_MAX_BUF_SIZE (1024*1024*1024) 262 /* max number of PCM devics per card */ 263 #define AZX_MAX_PCMS 8 264 265 /* RIRB int mask: overrun[2], response[0] */ 266 #define RIRB_INT_RESPONSE 0x01 267 #define RIRB_INT_OVERRUN 0x04 268 #define RIRB_INT_MASK 0x05 269 270 /* STATESTS int mask: S3,SD2,SD1,SD0 */ 271 #define AZX_MAX_CODECS 4 272 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1) 273 274 /* SD_CTL bits */ 275 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ 276 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ 277 #define SD_CTL_STRIPE (3 << 16) /* stripe control */ 278 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */ 279 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */ 280 #define SD_CTL_STREAM_TAG_MASK (0xf << 20) 281 #define SD_CTL_STREAM_TAG_SHIFT 20 282 283 /* SD_CTL and SD_STS */ 284 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ 285 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ 286 #define SD_INT_COMPLETE 0x04 /* completion interrupt */ 287 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\ 288 SD_INT_COMPLETE) 289 290 /* SD_STS */ 291 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */ 292 293 /* INTCTL and INTSTS */ 294 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */ 295 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ 296 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ 297 298 /* below are so far hardcoded - should read registers in future */ 299 #define ICH6_MAX_CORB_ENTRIES 256 300 #define ICH6_MAX_RIRB_ENTRIES 256 301 302 /* position fix mode */ 303 enum { 304 POS_FIX_AUTO, 305 POS_FIX_LPIB, 306 POS_FIX_POSBUF, 307 }; 308 309 /* Defines for ATI HD Audio support in SB450 south bridge */ 310 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 311 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 312 313 /* Defines for Nvidia HDA support */ 314 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 315 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 316 #define NVIDIA_HDA_ISTRM_COH 0x4d 317 #define NVIDIA_HDA_OSTRM_COH 0x4c 318 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 319 320 /* Defines for Intel SCH HDA snoop control */ 321 #define INTEL_SCH_HDA_DEVC 0x78 322 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 323 324 /* Define IN stream 0 FIFO size offset in VIA controller */ 325 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 326 /* Define VIA HD Audio Device ID*/ 327 #define VIA_HDAC_DEVICE_ID 0x3288 328 329 /* HD Audio class code */ 330 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403 331 332 /* 333 */ 334 335 struct azx_dev { 336 struct snd_dma_buffer bdl; /* BDL buffer */ 337 u32 *posbuf; /* position buffer pointer */ 338 339 unsigned int bufsize; /* size of the play buffer in bytes */ 340 unsigned int period_bytes; /* size of the period in bytes */ 341 unsigned int frags; /* number for period in the play buffer */ 342 unsigned int fifo_size; /* FIFO size */ 343 unsigned long start_jiffies; /* start + minimum jiffies */ 344 unsigned long min_jiffies; /* minimum jiffies before position is valid */ 345 346 void __iomem *sd_addr; /* stream descriptor pointer */ 347 348 u32 sd_int_sta_mask; /* stream int status mask */ 349 350 /* pcm support */ 351 struct snd_pcm_substream *substream; /* assigned substream, 352 * set in PCM open 353 */ 354 unsigned int format_val; /* format value to be set in the 355 * controller and the codec 356 */ 357 unsigned char stream_tag; /* assigned stream */ 358 unsigned char index; /* stream index */ 359 int device; /* last device number assigned to */ 360 361 unsigned int opened :1; 362 unsigned int running :1; 363 unsigned int irq_pending :1; 364 unsigned int start_flag: 1; /* stream full start flag */ 365 /* 366 * For VIA: 367 * A flag to ensure DMA position is 0 368 * when link position is not greater than FIFO size 369 */ 370 unsigned int insufficient :1; 371 }; 372 373 /* CORB/RIRB */ 374 struct azx_rb { 375 u32 *buf; /* CORB/RIRB buffer 376 * Each CORB entry is 4byte, RIRB is 8byte 377 */ 378 dma_addr_t addr; /* physical address of CORB/RIRB buffer */ 379 /* for RIRB */ 380 unsigned short rp, wp; /* read/write pointers */ 381 int cmds[AZX_MAX_CODECS]; /* number of pending requests */ 382 u32 res[AZX_MAX_CODECS]; /* last read value */ 383 }; 384 385 struct azx { 386 struct snd_card *card; 387 struct pci_dev *pci; 388 int dev_index; 389 390 /* chip type specific */ 391 int driver_type; 392 int playback_streams; 393 int playback_index_offset; 394 int capture_streams; 395 int capture_index_offset; 396 int num_streams; 397 398 /* pci resources */ 399 unsigned long addr; 400 void __iomem *remap_addr; 401 int irq; 402 403 /* locks */ 404 spinlock_t reg_lock; 405 struct mutex open_mutex; 406 407 /* streams (x num_streams) */ 408 struct azx_dev *azx_dev; 409 410 /* PCM */ 411 struct snd_pcm *pcm[AZX_MAX_PCMS]; 412 413 /* HD codec */ 414 unsigned short codec_mask; 415 int codec_probe_mask; /* copied from probe_mask option */ 416 struct hda_bus *bus; 417 unsigned int beep_mode; 418 419 /* CORB/RIRB */ 420 struct azx_rb corb; 421 struct azx_rb rirb; 422 423 /* CORB/RIRB and position buffers */ 424 struct snd_dma_buffer rb; 425 struct snd_dma_buffer posbuf; 426 427 /* flags */ 428 int position_fix; 429 unsigned int running :1; 430 unsigned int initialized :1; 431 unsigned int single_cmd :1; 432 unsigned int polling_mode :1; 433 unsigned int msi :1; 434 unsigned int irq_pending_warned :1; 435 unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */ 436 unsigned int probing :1; /* codec probing phase */ 437 438 /* for debugging */ 439 unsigned int last_cmd[AZX_MAX_CODECS]; 440 441 /* for pending irqs */ 442 struct work_struct irq_pending_work; 443 444 /* reboot notifier (for mysterious hangup problem at power-down) */ 445 struct notifier_block reboot_notifier; 446 }; 447 448 /* driver types */ 449 enum { 450 AZX_DRIVER_ICH, 451 AZX_DRIVER_SCH, 452 AZX_DRIVER_ATI, 453 AZX_DRIVER_ATIHDMI, 454 AZX_DRIVER_VIA, 455 AZX_DRIVER_SIS, 456 AZX_DRIVER_ULI, 457 AZX_DRIVER_NVIDIA, 458 AZX_DRIVER_TERA, 459 AZX_DRIVER_GENERIC, 460 AZX_NUM_DRIVERS, /* keep this as last entry */ 461 }; 462 463 static char *driver_short_names[] __devinitdata = { 464 [AZX_DRIVER_ICH] = "HDA Intel", 465 [AZX_DRIVER_SCH] = "HDA Intel MID", 466 [AZX_DRIVER_ATI] = "HDA ATI SB", 467 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 468 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 469 [AZX_DRIVER_SIS] = "HDA SIS966", 470 [AZX_DRIVER_ULI] = "HDA ULI M5461", 471 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 472 [AZX_DRIVER_TERA] = "HDA Teradici", 473 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 474 }; 475 476 /* 477 * macros for easy use 478 */ 479 #define azx_writel(chip,reg,value) \ 480 writel(value, (chip)->remap_addr + ICH6_REG_##reg) 481 #define azx_readl(chip,reg) \ 482 readl((chip)->remap_addr + ICH6_REG_##reg) 483 #define azx_writew(chip,reg,value) \ 484 writew(value, (chip)->remap_addr + ICH6_REG_##reg) 485 #define azx_readw(chip,reg) \ 486 readw((chip)->remap_addr + ICH6_REG_##reg) 487 #define azx_writeb(chip,reg,value) \ 488 writeb(value, (chip)->remap_addr + ICH6_REG_##reg) 489 #define azx_readb(chip,reg) \ 490 readb((chip)->remap_addr + ICH6_REG_##reg) 491 492 #define azx_sd_writel(dev,reg,value) \ 493 writel(value, (dev)->sd_addr + ICH6_REG_##reg) 494 #define azx_sd_readl(dev,reg) \ 495 readl((dev)->sd_addr + ICH6_REG_##reg) 496 #define azx_sd_writew(dev,reg,value) \ 497 writew(value, (dev)->sd_addr + ICH6_REG_##reg) 498 #define azx_sd_readw(dev,reg) \ 499 readw((dev)->sd_addr + ICH6_REG_##reg) 500 #define azx_sd_writeb(dev,reg,value) \ 501 writeb(value, (dev)->sd_addr + ICH6_REG_##reg) 502 #define azx_sd_readb(dev,reg) \ 503 readb((dev)->sd_addr + ICH6_REG_##reg) 504 505 /* for pcm support */ 506 #define get_azx_dev(substream) (substream->runtime->private_data) 507 508 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 509 510 /* 511 * Interface for HD codec 512 */ 513 514 /* 515 * CORB / RIRB interface 516 */ 517 static int azx_alloc_cmd_io(struct azx *chip) 518 { 519 int err; 520 521 /* single page (at least 4096 bytes) must suffice for both ringbuffes */ 522 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, 523 snd_dma_pci_data(chip->pci), 524 PAGE_SIZE, &chip->rb); 525 if (err < 0) { 526 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n"); 527 return err; 528 } 529 return 0; 530 } 531 532 static void azx_init_cmd_io(struct azx *chip) 533 { 534 spin_lock_irq(&chip->reg_lock); 535 /* CORB set up */ 536 chip->corb.addr = chip->rb.addr; 537 chip->corb.buf = (u32 *)chip->rb.area; 538 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr); 539 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr)); 540 541 /* set the corb size to 256 entries (ULI requires explicitly) */ 542 azx_writeb(chip, CORBSIZE, 0x02); 543 /* set the corb write pointer to 0 */ 544 azx_writew(chip, CORBWP, 0); 545 /* reset the corb hw read pointer */ 546 azx_writew(chip, CORBRP, ICH6_CORBRP_RST); 547 /* enable corb dma */ 548 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN); 549 550 /* RIRB set up */ 551 chip->rirb.addr = chip->rb.addr + 2048; 552 chip->rirb.buf = (u32 *)(chip->rb.area + 2048); 553 chip->rirb.wp = chip->rirb.rp = 0; 554 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds)); 555 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr); 556 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr)); 557 558 /* set the rirb size to 256 entries (ULI requires explicitly) */ 559 azx_writeb(chip, RIRBSIZE, 0x02); 560 /* reset the rirb hw write pointer */ 561 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST); 562 /* set N=1, get RIRB response interrupt for new entry */ 563 azx_writew(chip, RINTCNT, 1); 564 /* enable rirb dma and response irq */ 565 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN); 566 spin_unlock_irq(&chip->reg_lock); 567 } 568 569 static void azx_free_cmd_io(struct azx *chip) 570 { 571 spin_lock_irq(&chip->reg_lock); 572 /* disable ringbuffer DMAs */ 573 azx_writeb(chip, RIRBCTL, 0); 574 azx_writeb(chip, CORBCTL, 0); 575 spin_unlock_irq(&chip->reg_lock); 576 } 577 578 static unsigned int azx_command_addr(u32 cmd) 579 { 580 unsigned int addr = cmd >> 28; 581 582 if (addr >= AZX_MAX_CODECS) { 583 snd_BUG(); 584 addr = 0; 585 } 586 587 return addr; 588 } 589 590 static unsigned int azx_response_addr(u32 res) 591 { 592 unsigned int addr = res & 0xf; 593 594 if (addr >= AZX_MAX_CODECS) { 595 snd_BUG(); 596 addr = 0; 597 } 598 599 return addr; 600 } 601 602 /* send a command */ 603 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val) 604 { 605 struct azx *chip = bus->private_data; 606 unsigned int addr = azx_command_addr(val); 607 unsigned int wp; 608 609 spin_lock_irq(&chip->reg_lock); 610 611 /* add command to corb */ 612 wp = azx_readb(chip, CORBWP); 613 wp++; 614 wp %= ICH6_MAX_CORB_ENTRIES; 615 616 chip->rirb.cmds[addr]++; 617 chip->corb.buf[wp] = cpu_to_le32(val); 618 azx_writel(chip, CORBWP, wp); 619 620 spin_unlock_irq(&chip->reg_lock); 621 622 return 0; 623 } 624 625 #define ICH6_RIRB_EX_UNSOL_EV (1<<4) 626 627 /* retrieve RIRB entry - called from interrupt handler */ 628 static void azx_update_rirb(struct azx *chip) 629 { 630 unsigned int rp, wp; 631 unsigned int addr; 632 u32 res, res_ex; 633 634 wp = azx_readb(chip, RIRBWP); 635 if (wp == chip->rirb.wp) 636 return; 637 chip->rirb.wp = wp; 638 639 while (chip->rirb.rp != wp) { 640 chip->rirb.rp++; 641 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES; 642 643 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */ 644 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]); 645 res = le32_to_cpu(chip->rirb.buf[rp]); 646 addr = azx_response_addr(res_ex); 647 if (res_ex & ICH6_RIRB_EX_UNSOL_EV) 648 snd_hda_queue_unsol_event(chip->bus, res, res_ex); 649 else if (chip->rirb.cmds[addr]) { 650 chip->rirb.res[addr] = res; 651 smp_wmb(); 652 chip->rirb.cmds[addr]--; 653 } else 654 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, " 655 "last cmd=%#08x\n", 656 res, res_ex, 657 chip->last_cmd[addr]); 658 } 659 } 660 661 /* receive a response */ 662 static unsigned int azx_rirb_get_response(struct hda_bus *bus, 663 unsigned int addr) 664 { 665 struct azx *chip = bus->private_data; 666 unsigned long timeout; 667 668 again: 669 timeout = jiffies + msecs_to_jiffies(1000); 670 for (;;) { 671 if (chip->polling_mode) { 672 spin_lock_irq(&chip->reg_lock); 673 azx_update_rirb(chip); 674 spin_unlock_irq(&chip->reg_lock); 675 } 676 if (!chip->rirb.cmds[addr]) { 677 smp_rmb(); 678 bus->rirb_error = 0; 679 return chip->rirb.res[addr]; /* the last value */ 680 } 681 if (time_after(jiffies, timeout)) 682 break; 683 if (bus->needs_damn_long_delay) 684 msleep(2); /* temporary workaround */ 685 else { 686 udelay(10); 687 cond_resched(); 688 } 689 } 690 691 if (!chip->polling_mode) { 692 snd_printk(KERN_WARNING SFX "azx_get_response timeout, " 693 "switching to polling mode: last cmd=0x%08x\n", 694 chip->last_cmd[addr]); 695 chip->polling_mode = 1; 696 goto again; 697 } 698 699 if (chip->msi) { 700 snd_printk(KERN_WARNING SFX "No response from codec, " 701 "disabling MSI: last cmd=0x%08x\n", 702 chip->last_cmd[addr]); 703 free_irq(chip->irq, chip); 704 chip->irq = -1; 705 pci_disable_msi(chip->pci); 706 chip->msi = 0; 707 if (azx_acquire_irq(chip, 1) < 0) { 708 bus->rirb_error = 1; 709 return -1; 710 } 711 goto again; 712 } 713 714 if (chip->probing) { 715 /* If this critical timeout happens during the codec probing 716 * phase, this is likely an access to a non-existing codec 717 * slot. Better to return an error and reset the system. 718 */ 719 return -1; 720 } 721 722 /* a fatal communication error; need either to reset or to fallback 723 * to the single_cmd mode 724 */ 725 bus->rirb_error = 1; 726 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) { 727 bus->response_reset = 1; 728 return -1; /* give a chance to retry */ 729 } 730 731 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, " 732 "switching to single_cmd mode: last cmd=0x%08x\n", 733 chip->last_cmd[addr]); 734 chip->single_cmd = 1; 735 bus->response_reset = 0; 736 /* release CORB/RIRB */ 737 azx_free_cmd_io(chip); 738 /* disable unsolicited responses */ 739 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL); 740 return -1; 741 } 742 743 /* 744 * Use the single immediate command instead of CORB/RIRB for simplicity 745 * 746 * Note: according to Intel, this is not preferred use. The command was 747 * intended for the BIOS only, and may get confused with unsolicited 748 * responses. So, we shouldn't use it for normal operation from the 749 * driver. 750 * I left the codes, however, for debugging/testing purposes. 751 */ 752 753 /* receive a response */ 754 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr) 755 { 756 int timeout = 50; 757 758 while (timeout--) { 759 /* check IRV busy bit */ 760 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) { 761 /* reuse rirb.res as the response return value */ 762 chip->rirb.res[addr] = azx_readl(chip, IR); 763 return 0; 764 } 765 udelay(1); 766 } 767 if (printk_ratelimit()) 768 snd_printd(SFX "get_response timeout: IRS=0x%x\n", 769 azx_readw(chip, IRS)); 770 chip->rirb.res[addr] = -1; 771 return -EIO; 772 } 773 774 /* send a command */ 775 static int azx_single_send_cmd(struct hda_bus *bus, u32 val) 776 { 777 struct azx *chip = bus->private_data; 778 unsigned int addr = azx_command_addr(val); 779 int timeout = 50; 780 781 bus->rirb_error = 0; 782 while (timeout--) { 783 /* check ICB busy bit */ 784 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) { 785 /* Clear IRV valid bit */ 786 azx_writew(chip, IRS, azx_readw(chip, IRS) | 787 ICH6_IRS_VALID); 788 azx_writel(chip, IC, val); 789 azx_writew(chip, IRS, azx_readw(chip, IRS) | 790 ICH6_IRS_BUSY); 791 return azx_single_wait_for_response(chip, addr); 792 } 793 udelay(1); 794 } 795 if (printk_ratelimit()) 796 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", 797 azx_readw(chip, IRS), val); 798 return -EIO; 799 } 800 801 /* receive a response */ 802 static unsigned int azx_single_get_response(struct hda_bus *bus, 803 unsigned int addr) 804 { 805 struct azx *chip = bus->private_data; 806 return chip->rirb.res[addr]; 807 } 808 809 /* 810 * The below are the main callbacks from hda_codec. 811 * 812 * They are just the skeleton to call sub-callbacks according to the 813 * current setting of chip->single_cmd. 814 */ 815 816 /* send a command */ 817 static int azx_send_cmd(struct hda_bus *bus, unsigned int val) 818 { 819 struct azx *chip = bus->private_data; 820 821 chip->last_cmd[azx_command_addr(val)] = val; 822 if (chip->single_cmd) 823 return azx_single_send_cmd(bus, val); 824 else 825 return azx_corb_send_cmd(bus, val); 826 } 827 828 /* get a response */ 829 static unsigned int azx_get_response(struct hda_bus *bus, 830 unsigned int addr) 831 { 832 struct azx *chip = bus->private_data; 833 if (chip->single_cmd) 834 return azx_single_get_response(bus, addr); 835 else 836 return azx_rirb_get_response(bus, addr); 837 } 838 839 #ifdef CONFIG_SND_HDA_POWER_SAVE 840 static void azx_power_notify(struct hda_bus *bus); 841 #endif 842 843 /* reset codec link */ 844 static int azx_reset(struct azx *chip) 845 { 846 int count; 847 848 /* clear STATESTS */ 849 azx_writeb(chip, STATESTS, STATESTS_INT_MASK); 850 851 /* reset controller */ 852 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); 853 854 count = 50; 855 while (azx_readb(chip, GCTL) && --count) 856 msleep(1); 857 858 /* delay for >= 100us for codec PLL to settle per spec 859 * Rev 0.9 section 5.5.1 860 */ 861 msleep(1); 862 863 /* Bring controller out of reset */ 864 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET); 865 866 count = 50; 867 while (!azx_readb(chip, GCTL) && --count) 868 msleep(1); 869 870 /* Brent Chartrand said to wait >= 540us for codecs to initialize */ 871 msleep(1); 872 873 /* check to see if controller is ready */ 874 if (!azx_readb(chip, GCTL)) { 875 snd_printd(SFX "azx_reset: controller not ready!\n"); 876 return -EBUSY; 877 } 878 879 /* Accept unsolicited responses */ 880 if (!chip->single_cmd) 881 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | 882 ICH6_GCTL_UNSOL); 883 884 /* detect codecs */ 885 if (!chip->codec_mask) { 886 chip->codec_mask = azx_readw(chip, STATESTS); 887 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask); 888 } 889 890 return 0; 891 } 892 893 894 /* 895 * Lowlevel interface 896 */ 897 898 /* enable interrupts */ 899 static void azx_int_enable(struct azx *chip) 900 { 901 /* enable controller CIE and GIE */ 902 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) | 903 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN); 904 } 905 906 /* disable interrupts */ 907 static void azx_int_disable(struct azx *chip) 908 { 909 int i; 910 911 /* disable interrupts in stream descriptor */ 912 for (i = 0; i < chip->num_streams; i++) { 913 struct azx_dev *azx_dev = &chip->azx_dev[i]; 914 azx_sd_writeb(azx_dev, SD_CTL, 915 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK); 916 } 917 918 /* disable SIE for all streams */ 919 azx_writeb(chip, INTCTL, 0); 920 921 /* disable controller CIE and GIE */ 922 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) & 923 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN)); 924 } 925 926 /* clear interrupts */ 927 static void azx_int_clear(struct azx *chip) 928 { 929 int i; 930 931 /* clear stream status */ 932 for (i = 0; i < chip->num_streams; i++) { 933 struct azx_dev *azx_dev = &chip->azx_dev[i]; 934 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); 935 } 936 937 /* clear STATESTS */ 938 azx_writeb(chip, STATESTS, STATESTS_INT_MASK); 939 940 /* clear rirb status */ 941 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); 942 943 /* clear int status */ 944 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM); 945 } 946 947 /* start a stream */ 948 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev) 949 { 950 /* 951 * Before stream start, initialize parameter 952 */ 953 azx_dev->insufficient = 1; 954 955 /* enable SIE */ 956 azx_writeb(chip, INTCTL, 957 azx_readb(chip, INTCTL) | (1 << azx_dev->index)); 958 /* set DMA start and interrupt mask */ 959 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | 960 SD_CTL_DMA_START | SD_INT_MASK); 961 } 962 963 /* stop DMA */ 964 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev) 965 { 966 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & 967 ~(SD_CTL_DMA_START | SD_INT_MASK)); 968 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ 969 } 970 971 /* stop a stream */ 972 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev) 973 { 974 azx_stream_clear(chip, azx_dev); 975 /* disable SIE */ 976 azx_writeb(chip, INTCTL, 977 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index)); 978 } 979 980 981 /* 982 * reset and start the controller registers 983 */ 984 static void azx_init_chip(struct azx *chip) 985 { 986 if (chip->initialized) 987 return; 988 989 /* reset controller */ 990 azx_reset(chip); 991 992 /* initialize interrupts */ 993 azx_int_clear(chip); 994 azx_int_enable(chip); 995 996 /* initialize the codec command I/O */ 997 if (!chip->single_cmd) 998 azx_init_cmd_io(chip); 999 1000 /* program the position buffer */ 1001 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr); 1002 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr)); 1003 1004 chip->initialized = 1; 1005 } 1006 1007 /* 1008 * initialize the PCI registers 1009 */ 1010 /* update bits in a PCI register byte */ 1011 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 1012 unsigned char mask, unsigned char val) 1013 { 1014 unsigned char data; 1015 1016 pci_read_config_byte(pci, reg, &data); 1017 data &= ~mask; 1018 data |= (val & mask); 1019 pci_write_config_byte(pci, reg, data); 1020 } 1021 1022 static void azx_init_pci(struct azx *chip) 1023 { 1024 unsigned short snoop; 1025 1026 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 1027 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 1028 * Ensuring these bits are 0 clears playback static on some HD Audio 1029 * codecs 1030 */ 1031 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0); 1032 1033 switch (chip->driver_type) { 1034 case AZX_DRIVER_ATI: 1035 /* For ATI SB450 azalia HD audio, we need to enable snoop */ 1036 update_pci_byte(chip->pci, 1037 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 1038 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP); 1039 break; 1040 case AZX_DRIVER_NVIDIA: 1041 /* For NVIDIA HDA, enable snoop */ 1042 update_pci_byte(chip->pci, 1043 NVIDIA_HDA_TRANSREG_ADDR, 1044 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 1045 update_pci_byte(chip->pci, 1046 NVIDIA_HDA_ISTRM_COH, 1047 0x01, NVIDIA_HDA_ENABLE_COHBIT); 1048 update_pci_byte(chip->pci, 1049 NVIDIA_HDA_OSTRM_COH, 1050 0x01, NVIDIA_HDA_ENABLE_COHBIT); 1051 break; 1052 case AZX_DRIVER_SCH: 1053 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 1054 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) { 1055 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, 1056 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP)); 1057 pci_read_config_word(chip->pci, 1058 INTEL_SCH_HDA_DEVC, &snoop); 1059 snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n", 1060 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) 1061 ? "Failed" : "OK"); 1062 } 1063 break; 1064 1065 } 1066 } 1067 1068 1069 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 1070 1071 /* 1072 * interrupt handler 1073 */ 1074 static irqreturn_t azx_interrupt(int irq, void *dev_id) 1075 { 1076 struct azx *chip = dev_id; 1077 struct azx_dev *azx_dev; 1078 u32 status; 1079 int i, ok; 1080 1081 spin_lock(&chip->reg_lock); 1082 1083 status = azx_readl(chip, INTSTS); 1084 if (status == 0) { 1085 spin_unlock(&chip->reg_lock); 1086 return IRQ_NONE; 1087 } 1088 1089 for (i = 0; i < chip->num_streams; i++) { 1090 azx_dev = &chip->azx_dev[i]; 1091 if (status & azx_dev->sd_int_sta_mask) { 1092 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); 1093 if (!azx_dev->substream || !azx_dev->running) 1094 continue; 1095 /* check whether this IRQ is really acceptable */ 1096 ok = azx_position_ok(chip, azx_dev); 1097 if (ok == 1) { 1098 azx_dev->irq_pending = 0; 1099 spin_unlock(&chip->reg_lock); 1100 snd_pcm_period_elapsed(azx_dev->substream); 1101 spin_lock(&chip->reg_lock); 1102 } else if (ok == 0 && chip->bus && chip->bus->workq) { 1103 /* bogus IRQ, process it later */ 1104 azx_dev->irq_pending = 1; 1105 queue_work(chip->bus->workq, 1106 &chip->irq_pending_work); 1107 } 1108 } 1109 } 1110 1111 /* clear rirb int */ 1112 status = azx_readb(chip, RIRBSTS); 1113 if (status & RIRB_INT_MASK) { 1114 if (status & RIRB_INT_RESPONSE) 1115 azx_update_rirb(chip); 1116 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); 1117 } 1118 1119 #if 0 1120 /* clear state status int */ 1121 if (azx_readb(chip, STATESTS) & 0x04) 1122 azx_writeb(chip, STATESTS, 0x04); 1123 #endif 1124 spin_unlock(&chip->reg_lock); 1125 1126 return IRQ_HANDLED; 1127 } 1128 1129 1130 /* 1131 * set up a BDL entry 1132 */ 1133 static int setup_bdle(struct snd_pcm_substream *substream, 1134 struct azx_dev *azx_dev, u32 **bdlp, 1135 int ofs, int size, int with_ioc) 1136 { 1137 u32 *bdl = *bdlp; 1138 1139 while (size > 0) { 1140 dma_addr_t addr; 1141 int chunk; 1142 1143 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES) 1144 return -EINVAL; 1145 1146 addr = snd_pcm_sgbuf_get_addr(substream, ofs); 1147 /* program the address field of the BDL entry */ 1148 bdl[0] = cpu_to_le32((u32)addr); 1149 bdl[1] = cpu_to_le32(upper_32_bits(addr)); 1150 /* program the size field of the BDL entry */ 1151 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size); 1152 bdl[2] = cpu_to_le32(chunk); 1153 /* program the IOC to enable interrupt 1154 * only when the whole fragment is processed 1155 */ 1156 size -= chunk; 1157 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01); 1158 bdl += 4; 1159 azx_dev->frags++; 1160 ofs += chunk; 1161 } 1162 *bdlp = bdl; 1163 return ofs; 1164 } 1165 1166 /* 1167 * set up BDL entries 1168 */ 1169 static int azx_setup_periods(struct azx *chip, 1170 struct snd_pcm_substream *substream, 1171 struct azx_dev *azx_dev) 1172 { 1173 u32 *bdl; 1174 int i, ofs, periods, period_bytes; 1175 int pos_adj; 1176 1177 /* reset BDL address */ 1178 azx_sd_writel(azx_dev, SD_BDLPL, 0); 1179 azx_sd_writel(azx_dev, SD_BDLPU, 0); 1180 1181 period_bytes = azx_dev->period_bytes; 1182 periods = azx_dev->bufsize / period_bytes; 1183 1184 /* program the initial BDL entries */ 1185 bdl = (u32 *)azx_dev->bdl.area; 1186 ofs = 0; 1187 azx_dev->frags = 0; 1188 pos_adj = bdl_pos_adj[chip->dev_index]; 1189 if (pos_adj > 0) { 1190 struct snd_pcm_runtime *runtime = substream->runtime; 1191 int pos_align = pos_adj; 1192 pos_adj = (pos_adj * runtime->rate + 47999) / 48000; 1193 if (!pos_adj) 1194 pos_adj = pos_align; 1195 else 1196 pos_adj = ((pos_adj + pos_align - 1) / pos_align) * 1197 pos_align; 1198 pos_adj = frames_to_bytes(runtime, pos_adj); 1199 if (pos_adj >= period_bytes) { 1200 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n", 1201 bdl_pos_adj[chip->dev_index]); 1202 pos_adj = 0; 1203 } else { 1204 ofs = setup_bdle(substream, azx_dev, 1205 &bdl, ofs, pos_adj, 1); 1206 if (ofs < 0) 1207 goto error; 1208 } 1209 } else 1210 pos_adj = 0; 1211 for (i = 0; i < periods; i++) { 1212 if (i == periods - 1 && pos_adj) 1213 ofs = setup_bdle(substream, azx_dev, &bdl, ofs, 1214 period_bytes - pos_adj, 0); 1215 else 1216 ofs = setup_bdle(substream, azx_dev, &bdl, ofs, 1217 period_bytes, 1); 1218 if (ofs < 0) 1219 goto error; 1220 } 1221 return 0; 1222 1223 error: 1224 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n", 1225 azx_dev->bufsize, period_bytes); 1226 return -EINVAL; 1227 } 1228 1229 /* reset stream */ 1230 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev) 1231 { 1232 unsigned char val; 1233 int timeout; 1234 1235 azx_stream_clear(chip, azx_dev); 1236 1237 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | 1238 SD_CTL_STREAM_RESET); 1239 udelay(3); 1240 timeout = 300; 1241 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && 1242 --timeout) 1243 ; 1244 val &= ~SD_CTL_STREAM_RESET; 1245 azx_sd_writeb(azx_dev, SD_CTL, val); 1246 udelay(3); 1247 1248 timeout = 300; 1249 /* waiting for hardware to report that the stream is out of reset */ 1250 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && 1251 --timeout) 1252 ; 1253 1254 /* reset first position - may not be synced with hw at this time */ 1255 *azx_dev->posbuf = 0; 1256 } 1257 1258 /* 1259 * set up the SD for streaming 1260 */ 1261 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev) 1262 { 1263 /* make sure the run bit is zero for SD */ 1264 azx_stream_clear(chip, azx_dev); 1265 /* program the stream_tag */ 1266 azx_sd_writel(azx_dev, SD_CTL, 1267 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)| 1268 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT)); 1269 1270 /* program the length of samples in cyclic buffer */ 1271 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize); 1272 1273 /* program the stream format */ 1274 /* this value needs to be the same as the one programmed */ 1275 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val); 1276 1277 /* program the stream LVI (last valid index) of the BDL */ 1278 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1); 1279 1280 /* program the BDL address */ 1281 /* lower BDL address */ 1282 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); 1283 /* upper BDL address */ 1284 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr)); 1285 1286 /* enable the position buffer */ 1287 if (chip->position_fix == POS_FIX_POSBUF || 1288 chip->position_fix == POS_FIX_AUTO || 1289 chip->via_dmapos_patch) { 1290 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE)) 1291 azx_writel(chip, DPLBASE, 1292 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE); 1293 } 1294 1295 /* set the interrupt enable bits in the descriptor control register */ 1296 azx_sd_writel(azx_dev, SD_CTL, 1297 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK); 1298 1299 return 0; 1300 } 1301 1302 /* 1303 * Probe the given codec address 1304 */ 1305 static int probe_codec(struct azx *chip, int addr) 1306 { 1307 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | 1308 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; 1309 unsigned int res; 1310 1311 mutex_lock(&chip->bus->cmd_mutex); 1312 chip->probing = 1; 1313 azx_send_cmd(chip->bus, cmd); 1314 res = azx_get_response(chip->bus, addr); 1315 chip->probing = 0; 1316 mutex_unlock(&chip->bus->cmd_mutex); 1317 if (res == -1) 1318 return -EIO; 1319 snd_printdd(SFX "codec #%d probed OK\n", addr); 1320 return 0; 1321 } 1322 1323 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, 1324 struct hda_pcm *cpcm); 1325 static void azx_stop_chip(struct azx *chip); 1326 1327 static void azx_bus_reset(struct hda_bus *bus) 1328 { 1329 struct azx *chip = bus->private_data; 1330 1331 bus->in_reset = 1; 1332 azx_stop_chip(chip); 1333 azx_init_chip(chip); 1334 #ifdef CONFIG_PM 1335 if (chip->initialized) { 1336 int i; 1337 1338 for (i = 0; i < AZX_MAX_PCMS; i++) 1339 snd_pcm_suspend_all(chip->pcm[i]); 1340 snd_hda_suspend(chip->bus); 1341 snd_hda_resume(chip->bus); 1342 } 1343 #endif 1344 bus->in_reset = 0; 1345 } 1346 1347 /* 1348 * Codec initialization 1349 */ 1350 1351 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 1352 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = { 1353 [AZX_DRIVER_TERA] = 1, 1354 }; 1355 1356 static int __devinit azx_codec_create(struct azx *chip, const char *model) 1357 { 1358 struct hda_bus_template bus_temp; 1359 int c, codecs, err; 1360 int max_slots; 1361 1362 memset(&bus_temp, 0, sizeof(bus_temp)); 1363 bus_temp.private_data = chip; 1364 bus_temp.modelname = model; 1365 bus_temp.pci = chip->pci; 1366 bus_temp.ops.command = azx_send_cmd; 1367 bus_temp.ops.get_response = azx_get_response; 1368 bus_temp.ops.attach_pcm = azx_attach_pcm_stream; 1369 bus_temp.ops.bus_reset = azx_bus_reset; 1370 #ifdef CONFIG_SND_HDA_POWER_SAVE 1371 bus_temp.power_save = &power_save; 1372 bus_temp.ops.pm_notify = azx_power_notify; 1373 #endif 1374 1375 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus); 1376 if (err < 0) 1377 return err; 1378 1379 if (chip->driver_type == AZX_DRIVER_NVIDIA) 1380 chip->bus->needs_damn_long_delay = 1; 1381 1382 codecs = 0; 1383 max_slots = azx_max_codecs[chip->driver_type]; 1384 if (!max_slots) 1385 max_slots = AZX_MAX_CODECS; 1386 1387 /* First try to probe all given codec slots */ 1388 for (c = 0; c < max_slots; c++) { 1389 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { 1390 if (probe_codec(chip, c) < 0) { 1391 /* Some BIOSen give you wrong codec addresses 1392 * that don't exist 1393 */ 1394 snd_printk(KERN_WARNING SFX 1395 "Codec #%d probe error; " 1396 "disabling it...\n", c); 1397 chip->codec_mask &= ~(1 << c); 1398 /* More badly, accessing to a non-existing 1399 * codec often screws up the controller chip, 1400 * and distrubs the further communications. 1401 * Thus if an error occurs during probing, 1402 * better to reset the controller chip to 1403 * get back to the sanity state. 1404 */ 1405 azx_stop_chip(chip); 1406 azx_init_chip(chip); 1407 } 1408 } 1409 } 1410 1411 /* Then create codec instances */ 1412 for (c = 0; c < max_slots; c++) { 1413 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { 1414 struct hda_codec *codec; 1415 err = snd_hda_codec_new(chip->bus, c, &codec); 1416 if (err < 0) 1417 continue; 1418 codec->beep_mode = chip->beep_mode; 1419 codecs++; 1420 } 1421 } 1422 if (!codecs) { 1423 snd_printk(KERN_ERR SFX "no codecs initialized\n"); 1424 return -ENXIO; 1425 } 1426 return 0; 1427 } 1428 1429 /* configure each codec instance */ 1430 static int __devinit azx_codec_configure(struct azx *chip) 1431 { 1432 struct hda_codec *codec; 1433 list_for_each_entry(codec, &chip->bus->codec_list, list) { 1434 snd_hda_codec_configure(codec); 1435 } 1436 return 0; 1437 } 1438 1439 1440 /* 1441 * PCM support 1442 */ 1443 1444 /* assign a stream for the PCM */ 1445 static inline struct azx_dev * 1446 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream) 1447 { 1448 int dev, i, nums; 1449 struct azx_dev *res = NULL; 1450 1451 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1452 dev = chip->playback_index_offset; 1453 nums = chip->playback_streams; 1454 } else { 1455 dev = chip->capture_index_offset; 1456 nums = chip->capture_streams; 1457 } 1458 for (i = 0; i < nums; i++, dev++) 1459 if (!chip->azx_dev[dev].opened) { 1460 res = &chip->azx_dev[dev]; 1461 if (res->device == substream->pcm->device) 1462 break; 1463 } 1464 if (res) { 1465 res->opened = 1; 1466 res->device = substream->pcm->device; 1467 } 1468 return res; 1469 } 1470 1471 /* release the assigned stream */ 1472 static inline void azx_release_device(struct azx_dev *azx_dev) 1473 { 1474 azx_dev->opened = 0; 1475 } 1476 1477 static struct snd_pcm_hardware azx_pcm_hw = { 1478 .info = (SNDRV_PCM_INFO_MMAP | 1479 SNDRV_PCM_INFO_INTERLEAVED | 1480 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1481 SNDRV_PCM_INFO_MMAP_VALID | 1482 /* No full-resume yet implemented */ 1483 /* SNDRV_PCM_INFO_RESUME |*/ 1484 SNDRV_PCM_INFO_PAUSE | 1485 SNDRV_PCM_INFO_SYNC_START), 1486 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1487 .rates = SNDRV_PCM_RATE_48000, 1488 .rate_min = 48000, 1489 .rate_max = 48000, 1490 .channels_min = 2, 1491 .channels_max = 2, 1492 .buffer_bytes_max = AZX_MAX_BUF_SIZE, 1493 .period_bytes_min = 128, 1494 .period_bytes_max = AZX_MAX_BUF_SIZE / 2, 1495 .periods_min = 2, 1496 .periods_max = AZX_MAX_FRAG, 1497 .fifo_size = 0, 1498 }; 1499 1500 struct azx_pcm { 1501 struct azx *chip; 1502 struct hda_codec *codec; 1503 struct hda_pcm_stream *hinfo[2]; 1504 }; 1505 1506 static int azx_pcm_open(struct snd_pcm_substream *substream) 1507 { 1508 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1509 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 1510 struct azx *chip = apcm->chip; 1511 struct azx_dev *azx_dev; 1512 struct snd_pcm_runtime *runtime = substream->runtime; 1513 unsigned long flags; 1514 int err; 1515 1516 mutex_lock(&chip->open_mutex); 1517 azx_dev = azx_assign_device(chip, substream); 1518 if (azx_dev == NULL) { 1519 mutex_unlock(&chip->open_mutex); 1520 return -EBUSY; 1521 } 1522 runtime->hw = azx_pcm_hw; 1523 runtime->hw.channels_min = hinfo->channels_min; 1524 runtime->hw.channels_max = hinfo->channels_max; 1525 runtime->hw.formats = hinfo->formats; 1526 runtime->hw.rates = hinfo->rates; 1527 snd_pcm_limit_hw_rates(runtime); 1528 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); 1529 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 1530 128); 1531 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1532 128); 1533 snd_hda_power_up(apcm->codec); 1534 err = hinfo->ops.open(hinfo, apcm->codec, substream); 1535 if (err < 0) { 1536 azx_release_device(azx_dev); 1537 snd_hda_power_down(apcm->codec); 1538 mutex_unlock(&chip->open_mutex); 1539 return err; 1540 } 1541 snd_pcm_limit_hw_rates(runtime); 1542 /* sanity check */ 1543 if (snd_BUG_ON(!runtime->hw.channels_min) || 1544 snd_BUG_ON(!runtime->hw.channels_max) || 1545 snd_BUG_ON(!runtime->hw.formats) || 1546 snd_BUG_ON(!runtime->hw.rates)) { 1547 azx_release_device(azx_dev); 1548 hinfo->ops.close(hinfo, apcm->codec, substream); 1549 snd_hda_power_down(apcm->codec); 1550 mutex_unlock(&chip->open_mutex); 1551 return -EINVAL; 1552 } 1553 spin_lock_irqsave(&chip->reg_lock, flags); 1554 azx_dev->substream = substream; 1555 azx_dev->running = 0; 1556 spin_unlock_irqrestore(&chip->reg_lock, flags); 1557 1558 runtime->private_data = azx_dev; 1559 snd_pcm_set_sync(substream); 1560 mutex_unlock(&chip->open_mutex); 1561 return 0; 1562 } 1563 1564 static int azx_pcm_close(struct snd_pcm_substream *substream) 1565 { 1566 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1567 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 1568 struct azx *chip = apcm->chip; 1569 struct azx_dev *azx_dev = get_azx_dev(substream); 1570 unsigned long flags; 1571 1572 mutex_lock(&chip->open_mutex); 1573 spin_lock_irqsave(&chip->reg_lock, flags); 1574 azx_dev->substream = NULL; 1575 azx_dev->running = 0; 1576 spin_unlock_irqrestore(&chip->reg_lock, flags); 1577 azx_release_device(azx_dev); 1578 hinfo->ops.close(hinfo, apcm->codec, substream); 1579 snd_hda_power_down(apcm->codec); 1580 mutex_unlock(&chip->open_mutex); 1581 return 0; 1582 } 1583 1584 static int azx_pcm_hw_params(struct snd_pcm_substream *substream, 1585 struct snd_pcm_hw_params *hw_params) 1586 { 1587 struct azx_dev *azx_dev = get_azx_dev(substream); 1588 1589 azx_dev->bufsize = 0; 1590 azx_dev->period_bytes = 0; 1591 azx_dev->format_val = 0; 1592 return snd_pcm_lib_malloc_pages(substream, 1593 params_buffer_bytes(hw_params)); 1594 } 1595 1596 static int azx_pcm_hw_free(struct snd_pcm_substream *substream) 1597 { 1598 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1599 struct azx_dev *azx_dev = get_azx_dev(substream); 1600 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 1601 1602 /* reset BDL address */ 1603 azx_sd_writel(azx_dev, SD_BDLPL, 0); 1604 azx_sd_writel(azx_dev, SD_BDLPU, 0); 1605 azx_sd_writel(azx_dev, SD_CTL, 0); 1606 azx_dev->bufsize = 0; 1607 azx_dev->period_bytes = 0; 1608 azx_dev->format_val = 0; 1609 1610 hinfo->ops.cleanup(hinfo, apcm->codec, substream); 1611 1612 return snd_pcm_lib_free_pages(substream); 1613 } 1614 1615 static int azx_pcm_prepare(struct snd_pcm_substream *substream) 1616 { 1617 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1618 struct azx *chip = apcm->chip; 1619 struct azx_dev *azx_dev = get_azx_dev(substream); 1620 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 1621 struct snd_pcm_runtime *runtime = substream->runtime; 1622 unsigned int bufsize, period_bytes, format_val; 1623 int err; 1624 1625 azx_stream_reset(chip, azx_dev); 1626 format_val = snd_hda_calc_stream_format(runtime->rate, 1627 runtime->channels, 1628 runtime->format, 1629 hinfo->maxbps); 1630 if (!format_val) { 1631 snd_printk(KERN_ERR SFX 1632 "invalid format_val, rate=%d, ch=%d, format=%d\n", 1633 runtime->rate, runtime->channels, runtime->format); 1634 return -EINVAL; 1635 } 1636 1637 bufsize = snd_pcm_lib_buffer_bytes(substream); 1638 period_bytes = snd_pcm_lib_period_bytes(substream); 1639 1640 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n", 1641 bufsize, format_val); 1642 1643 if (bufsize != azx_dev->bufsize || 1644 period_bytes != azx_dev->period_bytes || 1645 format_val != azx_dev->format_val) { 1646 azx_dev->bufsize = bufsize; 1647 azx_dev->period_bytes = period_bytes; 1648 azx_dev->format_val = format_val; 1649 err = azx_setup_periods(chip, substream, azx_dev); 1650 if (err < 0) 1651 return err; 1652 } 1653 1654 azx_dev->min_jiffies = (runtime->period_size * HZ) / 1655 (runtime->rate * 2); 1656 azx_setup_controller(chip, azx_dev); 1657 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1658 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1; 1659 else 1660 azx_dev->fifo_size = 0; 1661 1662 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag, 1663 azx_dev->format_val, substream); 1664 } 1665 1666 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 1667 { 1668 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1669 struct azx *chip = apcm->chip; 1670 struct azx_dev *azx_dev; 1671 struct snd_pcm_substream *s; 1672 int rstart = 0, start, nsync = 0, sbits = 0; 1673 int nwait, timeout; 1674 1675 switch (cmd) { 1676 case SNDRV_PCM_TRIGGER_START: 1677 rstart = 1; 1678 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1679 case SNDRV_PCM_TRIGGER_RESUME: 1680 start = 1; 1681 break; 1682 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1683 case SNDRV_PCM_TRIGGER_SUSPEND: 1684 case SNDRV_PCM_TRIGGER_STOP: 1685 start = 0; 1686 break; 1687 default: 1688 return -EINVAL; 1689 } 1690 1691 snd_pcm_group_for_each_entry(s, substream) { 1692 if (s->pcm->card != substream->pcm->card) 1693 continue; 1694 azx_dev = get_azx_dev(s); 1695 sbits |= 1 << azx_dev->index; 1696 nsync++; 1697 snd_pcm_trigger_done(s, substream); 1698 } 1699 1700 spin_lock(&chip->reg_lock); 1701 if (nsync > 1) { 1702 /* first, set SYNC bits of corresponding streams */ 1703 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits); 1704 } 1705 snd_pcm_group_for_each_entry(s, substream) { 1706 if (s->pcm->card != substream->pcm->card) 1707 continue; 1708 azx_dev = get_azx_dev(s); 1709 if (rstart) { 1710 azx_dev->start_flag = 1; 1711 azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies; 1712 } 1713 if (start) 1714 azx_stream_start(chip, azx_dev); 1715 else 1716 azx_stream_stop(chip, azx_dev); 1717 azx_dev->running = start; 1718 } 1719 spin_unlock(&chip->reg_lock); 1720 if (start) { 1721 if (nsync == 1) 1722 return 0; 1723 /* wait until all FIFOs get ready */ 1724 for (timeout = 5000; timeout; timeout--) { 1725 nwait = 0; 1726 snd_pcm_group_for_each_entry(s, substream) { 1727 if (s->pcm->card != substream->pcm->card) 1728 continue; 1729 azx_dev = get_azx_dev(s); 1730 if (!(azx_sd_readb(azx_dev, SD_STS) & 1731 SD_STS_FIFO_READY)) 1732 nwait++; 1733 } 1734 if (!nwait) 1735 break; 1736 cpu_relax(); 1737 } 1738 } else { 1739 /* wait until all RUN bits are cleared */ 1740 for (timeout = 5000; timeout; timeout--) { 1741 nwait = 0; 1742 snd_pcm_group_for_each_entry(s, substream) { 1743 if (s->pcm->card != substream->pcm->card) 1744 continue; 1745 azx_dev = get_azx_dev(s); 1746 if (azx_sd_readb(azx_dev, SD_CTL) & 1747 SD_CTL_DMA_START) 1748 nwait++; 1749 } 1750 if (!nwait) 1751 break; 1752 cpu_relax(); 1753 } 1754 } 1755 if (nsync > 1) { 1756 spin_lock(&chip->reg_lock); 1757 /* reset SYNC bits */ 1758 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits); 1759 spin_unlock(&chip->reg_lock); 1760 } 1761 return 0; 1762 } 1763 1764 /* get the current DMA position with correction on VIA chips */ 1765 static unsigned int azx_via_get_position(struct azx *chip, 1766 struct azx_dev *azx_dev) 1767 { 1768 unsigned int link_pos, mini_pos, bound_pos; 1769 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 1770 unsigned int fifo_size; 1771 1772 link_pos = azx_sd_readl(azx_dev, SD_LPIB); 1773 if (azx_dev->index >= 4) { 1774 /* Playback, no problem using link position */ 1775 return link_pos; 1776 } 1777 1778 /* Capture */ 1779 /* For new chipset, 1780 * use mod to get the DMA position just like old chipset 1781 */ 1782 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf); 1783 mod_dma_pos %= azx_dev->period_bytes; 1784 1785 /* azx_dev->fifo_size can't get FIFO size of in stream. 1786 * Get from base address + offset. 1787 */ 1788 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET); 1789 1790 if (azx_dev->insufficient) { 1791 /* Link position never gather than FIFO size */ 1792 if (link_pos <= fifo_size) 1793 return 0; 1794 1795 azx_dev->insufficient = 0; 1796 } 1797 1798 if (link_pos <= fifo_size) 1799 mini_pos = azx_dev->bufsize + link_pos - fifo_size; 1800 else 1801 mini_pos = link_pos - fifo_size; 1802 1803 /* Find nearest previous boudary */ 1804 mod_mini_pos = mini_pos % azx_dev->period_bytes; 1805 mod_link_pos = link_pos % azx_dev->period_bytes; 1806 if (mod_link_pos >= fifo_size) 1807 bound_pos = link_pos - mod_link_pos; 1808 else if (mod_dma_pos >= mod_mini_pos) 1809 bound_pos = mini_pos - mod_mini_pos; 1810 else { 1811 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes; 1812 if (bound_pos >= azx_dev->bufsize) 1813 bound_pos = 0; 1814 } 1815 1816 /* Calculate real DMA position we want */ 1817 return bound_pos + mod_dma_pos; 1818 } 1819 1820 static unsigned int azx_get_position(struct azx *chip, 1821 struct azx_dev *azx_dev) 1822 { 1823 unsigned int pos; 1824 1825 if (chip->via_dmapos_patch) 1826 pos = azx_via_get_position(chip, azx_dev); 1827 else if (chip->position_fix == POS_FIX_POSBUF || 1828 chip->position_fix == POS_FIX_AUTO) { 1829 /* use the position buffer */ 1830 pos = le32_to_cpu(*azx_dev->posbuf); 1831 } else { 1832 /* read LPIB */ 1833 pos = azx_sd_readl(azx_dev, SD_LPIB); 1834 } 1835 if (pos >= azx_dev->bufsize) 1836 pos = 0; 1837 return pos; 1838 } 1839 1840 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) 1841 { 1842 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1843 struct azx *chip = apcm->chip; 1844 struct azx_dev *azx_dev = get_azx_dev(substream); 1845 return bytes_to_frames(substream->runtime, 1846 azx_get_position(chip, azx_dev)); 1847 } 1848 1849 /* 1850 * Check whether the current DMA position is acceptable for updating 1851 * periods. Returns non-zero if it's OK. 1852 * 1853 * Many HD-audio controllers appear pretty inaccurate about 1854 * the update-IRQ timing. The IRQ is issued before actually the 1855 * data is processed. So, we need to process it afterwords in a 1856 * workqueue. 1857 */ 1858 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 1859 { 1860 unsigned int pos; 1861 1862 if (azx_dev->start_flag && 1863 time_before_eq(jiffies, azx_dev->start_jiffies)) 1864 return -1; /* bogus (too early) interrupt */ 1865 azx_dev->start_flag = 0; 1866 1867 pos = azx_get_position(chip, azx_dev); 1868 if (chip->position_fix == POS_FIX_AUTO) { 1869 if (!pos) { 1870 printk(KERN_WARNING 1871 "hda-intel: Invalid position buffer, " 1872 "using LPIB read method instead.\n"); 1873 chip->position_fix = POS_FIX_LPIB; 1874 pos = azx_get_position(chip, azx_dev); 1875 } else 1876 chip->position_fix = POS_FIX_POSBUF; 1877 } 1878 1879 if (!bdl_pos_adj[chip->dev_index]) 1880 return 1; /* no delayed ack */ 1881 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2) 1882 return 0; /* NG - it's below the period boundary */ 1883 return 1; /* OK, it's fine */ 1884 } 1885 1886 /* 1887 * The work for pending PCM period updates. 1888 */ 1889 static void azx_irq_pending_work(struct work_struct *work) 1890 { 1891 struct azx *chip = container_of(work, struct azx, irq_pending_work); 1892 int i, pending; 1893 1894 if (!chip->irq_pending_warned) { 1895 printk(KERN_WARNING 1896 "hda-intel: IRQ timing workaround is activated " 1897 "for card #%d. Suggest a bigger bdl_pos_adj.\n", 1898 chip->card->number); 1899 chip->irq_pending_warned = 1; 1900 } 1901 1902 for (;;) { 1903 pending = 0; 1904 spin_lock_irq(&chip->reg_lock); 1905 for (i = 0; i < chip->num_streams; i++) { 1906 struct azx_dev *azx_dev = &chip->azx_dev[i]; 1907 if (!azx_dev->irq_pending || 1908 !azx_dev->substream || 1909 !azx_dev->running) 1910 continue; 1911 if (azx_position_ok(chip, azx_dev)) { 1912 azx_dev->irq_pending = 0; 1913 spin_unlock(&chip->reg_lock); 1914 snd_pcm_period_elapsed(azx_dev->substream); 1915 spin_lock(&chip->reg_lock); 1916 } else 1917 pending++; 1918 } 1919 spin_unlock_irq(&chip->reg_lock); 1920 if (!pending) 1921 return; 1922 cond_resched(); 1923 } 1924 } 1925 1926 /* clear irq_pending flags and assure no on-going workq */ 1927 static void azx_clear_irq_pending(struct azx *chip) 1928 { 1929 int i; 1930 1931 spin_lock_irq(&chip->reg_lock); 1932 for (i = 0; i < chip->num_streams; i++) 1933 chip->azx_dev[i].irq_pending = 0; 1934 spin_unlock_irq(&chip->reg_lock); 1935 } 1936 1937 static struct snd_pcm_ops azx_pcm_ops = { 1938 .open = azx_pcm_open, 1939 .close = azx_pcm_close, 1940 .ioctl = snd_pcm_lib_ioctl, 1941 .hw_params = azx_pcm_hw_params, 1942 .hw_free = azx_pcm_hw_free, 1943 .prepare = azx_pcm_prepare, 1944 .trigger = azx_pcm_trigger, 1945 .pointer = azx_pcm_pointer, 1946 .page = snd_pcm_sgbuf_ops_page, 1947 }; 1948 1949 static void azx_pcm_free(struct snd_pcm *pcm) 1950 { 1951 struct azx_pcm *apcm = pcm->private_data; 1952 if (apcm) { 1953 apcm->chip->pcm[pcm->device] = NULL; 1954 kfree(apcm); 1955 } 1956 } 1957 1958 static int 1959 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, 1960 struct hda_pcm *cpcm) 1961 { 1962 struct azx *chip = bus->private_data; 1963 struct snd_pcm *pcm; 1964 struct azx_pcm *apcm; 1965 int pcm_dev = cpcm->device; 1966 int s, err; 1967 1968 if (pcm_dev >= AZX_MAX_PCMS) { 1969 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n", 1970 pcm_dev); 1971 return -EINVAL; 1972 } 1973 if (chip->pcm[pcm_dev]) { 1974 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev); 1975 return -EBUSY; 1976 } 1977 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, 1978 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams, 1979 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams, 1980 &pcm); 1981 if (err < 0) 1982 return err; 1983 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name)); 1984 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL); 1985 if (apcm == NULL) 1986 return -ENOMEM; 1987 apcm->chip = chip; 1988 apcm->codec = codec; 1989 pcm->private_data = apcm; 1990 pcm->private_free = azx_pcm_free; 1991 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM) 1992 pcm->dev_class = SNDRV_PCM_CLASS_MODEM; 1993 chip->pcm[pcm_dev] = pcm; 1994 cpcm->pcm = pcm; 1995 for (s = 0; s < 2; s++) { 1996 apcm->hinfo[s] = &cpcm->stream[s]; 1997 if (cpcm->stream[s].substreams) 1998 snd_pcm_set_ops(pcm, s, &azx_pcm_ops); 1999 } 2000 /* buffer pre-allocation */ 2001 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG, 2002 snd_dma_pci_data(chip->pci), 2003 1024 * 64, 32 * 1024 * 1024); 2004 return 0; 2005 } 2006 2007 /* 2008 * mixer creation - all stuff is implemented in hda module 2009 */ 2010 static int __devinit azx_mixer_create(struct azx *chip) 2011 { 2012 return snd_hda_build_controls(chip->bus); 2013 } 2014 2015 2016 /* 2017 * initialize SD streams 2018 */ 2019 static int __devinit azx_init_stream(struct azx *chip) 2020 { 2021 int i; 2022 2023 /* initialize each stream (aka device) 2024 * assign the starting bdl address to each stream (device) 2025 * and initialize 2026 */ 2027 for (i = 0; i < chip->num_streams; i++) { 2028 struct azx_dev *azx_dev = &chip->azx_dev[i]; 2029 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8); 2030 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ 2031 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80); 2032 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ 2033 azx_dev->sd_int_sta_mask = 1 << i; 2034 /* stream tag: must be non-zero and unique */ 2035 azx_dev->index = i; 2036 azx_dev->stream_tag = i + 1; 2037 } 2038 2039 return 0; 2040 } 2041 2042 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 2043 { 2044 if (request_irq(chip->pci->irq, azx_interrupt, 2045 chip->msi ? 0 : IRQF_SHARED, 2046 "HDA Intel", chip)) { 2047 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, " 2048 "disabling device\n", chip->pci->irq); 2049 if (do_disconnect) 2050 snd_card_disconnect(chip->card); 2051 return -1; 2052 } 2053 chip->irq = chip->pci->irq; 2054 pci_intx(chip->pci, !chip->msi); 2055 return 0; 2056 } 2057 2058 2059 static void azx_stop_chip(struct azx *chip) 2060 { 2061 if (!chip->initialized) 2062 return; 2063 2064 /* disable interrupts */ 2065 azx_int_disable(chip); 2066 azx_int_clear(chip); 2067 2068 /* disable CORB/RIRB */ 2069 azx_free_cmd_io(chip); 2070 2071 /* disable position buffer */ 2072 azx_writel(chip, DPLBASE, 0); 2073 azx_writel(chip, DPUBASE, 0); 2074 2075 chip->initialized = 0; 2076 } 2077 2078 #ifdef CONFIG_SND_HDA_POWER_SAVE 2079 /* power-up/down the controller */ 2080 static void azx_power_notify(struct hda_bus *bus) 2081 { 2082 struct azx *chip = bus->private_data; 2083 struct hda_codec *c; 2084 int power_on = 0; 2085 2086 list_for_each_entry(c, &bus->codec_list, list) { 2087 if (c->power_on) { 2088 power_on = 1; 2089 break; 2090 } 2091 } 2092 if (power_on) 2093 azx_init_chip(chip); 2094 else if (chip->running && power_save_controller && 2095 !bus->power_keep_link_on) 2096 azx_stop_chip(chip); 2097 } 2098 #endif /* CONFIG_SND_HDA_POWER_SAVE */ 2099 2100 #ifdef CONFIG_PM 2101 /* 2102 * power management 2103 */ 2104 2105 static int snd_hda_codecs_inuse(struct hda_bus *bus) 2106 { 2107 struct hda_codec *codec; 2108 2109 list_for_each_entry(codec, &bus->codec_list, list) { 2110 if (snd_hda_codec_needs_resume(codec)) 2111 return 1; 2112 } 2113 return 0; 2114 } 2115 2116 static int azx_suspend(struct pci_dev *pci, pm_message_t state) 2117 { 2118 struct snd_card *card = pci_get_drvdata(pci); 2119 struct azx *chip = card->private_data; 2120 int i; 2121 2122 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2123 azx_clear_irq_pending(chip); 2124 for (i = 0; i < AZX_MAX_PCMS; i++) 2125 snd_pcm_suspend_all(chip->pcm[i]); 2126 if (chip->initialized) 2127 snd_hda_suspend(chip->bus); 2128 azx_stop_chip(chip); 2129 if (chip->irq >= 0) { 2130 free_irq(chip->irq, chip); 2131 chip->irq = -1; 2132 } 2133 if (chip->msi) 2134 pci_disable_msi(chip->pci); 2135 pci_disable_device(pci); 2136 pci_save_state(pci); 2137 pci_set_power_state(pci, pci_choose_state(pci, state)); 2138 return 0; 2139 } 2140 2141 static int azx_resume(struct pci_dev *pci) 2142 { 2143 struct snd_card *card = pci_get_drvdata(pci); 2144 struct azx *chip = card->private_data; 2145 2146 pci_set_power_state(pci, PCI_D0); 2147 pci_restore_state(pci); 2148 if (pci_enable_device(pci) < 0) { 2149 printk(KERN_ERR "hda-intel: pci_enable_device failed, " 2150 "disabling device\n"); 2151 snd_card_disconnect(card); 2152 return -EIO; 2153 } 2154 pci_set_master(pci); 2155 if (chip->msi) 2156 if (pci_enable_msi(pci) < 0) 2157 chip->msi = 0; 2158 if (azx_acquire_irq(chip, 1) < 0) 2159 return -EIO; 2160 azx_init_pci(chip); 2161 2162 if (snd_hda_codecs_inuse(chip->bus)) 2163 azx_init_chip(chip); 2164 2165 snd_hda_resume(chip->bus); 2166 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2167 return 0; 2168 } 2169 #endif /* CONFIG_PM */ 2170 2171 2172 /* 2173 * reboot notifier for hang-up problem at power-down 2174 */ 2175 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf) 2176 { 2177 struct azx *chip = container_of(nb, struct azx, reboot_notifier); 2178 snd_hda_bus_reboot_notify(chip->bus); 2179 azx_stop_chip(chip); 2180 return NOTIFY_OK; 2181 } 2182 2183 static void azx_notifier_register(struct azx *chip) 2184 { 2185 chip->reboot_notifier.notifier_call = azx_halt; 2186 register_reboot_notifier(&chip->reboot_notifier); 2187 } 2188 2189 static void azx_notifier_unregister(struct azx *chip) 2190 { 2191 if (chip->reboot_notifier.notifier_call) 2192 unregister_reboot_notifier(&chip->reboot_notifier); 2193 } 2194 2195 /* 2196 * destructor 2197 */ 2198 static int azx_free(struct azx *chip) 2199 { 2200 int i; 2201 2202 azx_notifier_unregister(chip); 2203 2204 if (chip->initialized) { 2205 azx_clear_irq_pending(chip); 2206 for (i = 0; i < chip->num_streams; i++) 2207 azx_stream_stop(chip, &chip->azx_dev[i]); 2208 azx_stop_chip(chip); 2209 } 2210 2211 if (chip->irq >= 0) 2212 free_irq(chip->irq, (void*)chip); 2213 if (chip->msi) 2214 pci_disable_msi(chip->pci); 2215 if (chip->remap_addr) 2216 iounmap(chip->remap_addr); 2217 2218 if (chip->azx_dev) { 2219 for (i = 0; i < chip->num_streams; i++) 2220 if (chip->azx_dev[i].bdl.area) 2221 snd_dma_free_pages(&chip->azx_dev[i].bdl); 2222 } 2223 if (chip->rb.area) 2224 snd_dma_free_pages(&chip->rb); 2225 if (chip->posbuf.area) 2226 snd_dma_free_pages(&chip->posbuf); 2227 pci_release_regions(chip->pci); 2228 pci_disable_device(chip->pci); 2229 kfree(chip->azx_dev); 2230 kfree(chip); 2231 2232 return 0; 2233 } 2234 2235 static int azx_dev_free(struct snd_device *device) 2236 { 2237 return azx_free(device->device_data); 2238 } 2239 2240 /* 2241 * white/black-listing for position_fix 2242 */ 2243 static struct snd_pci_quirk position_fix_list[] __devinitdata = { 2244 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 2245 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 2246 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 2247 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 2248 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 2249 {} 2250 }; 2251 2252 static int __devinit check_position_fix(struct azx *chip, int fix) 2253 { 2254 const struct snd_pci_quirk *q; 2255 2256 switch (fix) { 2257 case POS_FIX_LPIB: 2258 case POS_FIX_POSBUF: 2259 return fix; 2260 } 2261 2262 /* Check VIA/ATI HD Audio Controller exist */ 2263 switch (chip->driver_type) { 2264 case AZX_DRIVER_VIA: 2265 case AZX_DRIVER_ATI: 2266 chip->via_dmapos_patch = 1; 2267 /* Use link position directly, avoid any transfer problem. */ 2268 return POS_FIX_LPIB; 2269 } 2270 chip->via_dmapos_patch = 0; 2271 2272 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 2273 if (q) { 2274 printk(KERN_INFO 2275 "hda_intel: position_fix set to %d " 2276 "for device %04x:%04x\n", 2277 q->value, q->subvendor, q->subdevice); 2278 return q->value; 2279 } 2280 return POS_FIX_AUTO; 2281 } 2282 2283 /* 2284 * black-lists for probe_mask 2285 */ 2286 static struct snd_pci_quirk probe_mask_list[] __devinitdata = { 2287 /* Thinkpad often breaks the controller communication when accessing 2288 * to the non-working (or non-existing) modem codec slot. 2289 */ 2290 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 2291 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 2292 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 2293 /* broken BIOS */ 2294 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 2295 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 2296 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 2297 /* forced codec slots */ 2298 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 2299 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 2300 {} 2301 }; 2302 2303 #define AZX_FORCE_CODEC_MASK 0x100 2304 2305 static void __devinit check_probe_mask(struct azx *chip, int dev) 2306 { 2307 const struct snd_pci_quirk *q; 2308 2309 chip->codec_probe_mask = probe_mask[dev]; 2310 if (chip->codec_probe_mask == -1) { 2311 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 2312 if (q) { 2313 printk(KERN_INFO 2314 "hda_intel: probe_mask set to 0x%x " 2315 "for device %04x:%04x\n", 2316 q->value, q->subvendor, q->subdevice); 2317 chip->codec_probe_mask = q->value; 2318 } 2319 } 2320 2321 /* check forced option */ 2322 if (chip->codec_probe_mask != -1 && 2323 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 2324 chip->codec_mask = chip->codec_probe_mask & 0xff; 2325 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n", 2326 chip->codec_mask); 2327 } 2328 } 2329 2330 /* 2331 * white/black-list for enable_msi 2332 */ 2333 static struct snd_pci_quirk msi_black_list[] __devinitdata = { 2334 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 2335 {} 2336 }; 2337 2338 static void __devinit check_msi(struct azx *chip) 2339 { 2340 const struct snd_pci_quirk *q; 2341 2342 if (enable_msi >= 0) { 2343 chip->msi = !!enable_msi; 2344 return; 2345 } 2346 chip->msi = 1; /* enable MSI as default */ 2347 q = snd_pci_quirk_lookup(chip->pci, msi_black_list); 2348 if (q) { 2349 printk(KERN_INFO 2350 "hda_intel: msi for device %04x:%04x set to %d\n", 2351 q->subvendor, q->subdevice, q->value); 2352 chip->msi = q->value; 2353 } 2354 } 2355 2356 2357 /* 2358 * constructor 2359 */ 2360 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci, 2361 int dev, int driver_type, 2362 struct azx **rchip) 2363 { 2364 struct azx *chip; 2365 int i, err; 2366 unsigned short gcap; 2367 static struct snd_device_ops ops = { 2368 .dev_free = azx_dev_free, 2369 }; 2370 2371 *rchip = NULL; 2372 2373 err = pci_enable_device(pci); 2374 if (err < 0) 2375 return err; 2376 2377 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 2378 if (!chip) { 2379 snd_printk(KERN_ERR SFX "cannot allocate chip\n"); 2380 pci_disable_device(pci); 2381 return -ENOMEM; 2382 } 2383 2384 spin_lock_init(&chip->reg_lock); 2385 mutex_init(&chip->open_mutex); 2386 chip->card = card; 2387 chip->pci = pci; 2388 chip->irq = -1; 2389 chip->driver_type = driver_type; 2390 check_msi(chip); 2391 chip->dev_index = dev; 2392 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work); 2393 2394 chip->position_fix = check_position_fix(chip, position_fix[dev]); 2395 check_probe_mask(chip, dev); 2396 2397 chip->single_cmd = single_cmd; 2398 2399 if (bdl_pos_adj[dev] < 0) { 2400 switch (chip->driver_type) { 2401 case AZX_DRIVER_ICH: 2402 bdl_pos_adj[dev] = 1; 2403 break; 2404 default: 2405 bdl_pos_adj[dev] = 32; 2406 break; 2407 } 2408 } 2409 2410 #if BITS_PER_LONG != 64 2411 /* Fix up base address on ULI M5461 */ 2412 if (chip->driver_type == AZX_DRIVER_ULI) { 2413 u16 tmp3; 2414 pci_read_config_word(pci, 0x40, &tmp3); 2415 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 2416 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 2417 } 2418 #endif 2419 2420 err = pci_request_regions(pci, "ICH HD audio"); 2421 if (err < 0) { 2422 kfree(chip); 2423 pci_disable_device(pci); 2424 return err; 2425 } 2426 2427 chip->addr = pci_resource_start(pci, 0); 2428 chip->remap_addr = pci_ioremap_bar(pci, 0); 2429 if (chip->remap_addr == NULL) { 2430 snd_printk(KERN_ERR SFX "ioremap error\n"); 2431 err = -ENXIO; 2432 goto errout; 2433 } 2434 2435 if (chip->msi) 2436 if (pci_enable_msi(pci) < 0) 2437 chip->msi = 0; 2438 2439 if (azx_acquire_irq(chip, 0) < 0) { 2440 err = -EBUSY; 2441 goto errout; 2442 } 2443 2444 pci_set_master(pci); 2445 synchronize_irq(chip->irq); 2446 2447 gcap = azx_readw(chip, GCAP); 2448 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap); 2449 2450 /* disable SB600 64bit support for safety */ 2451 if ((chip->driver_type == AZX_DRIVER_ATI) || 2452 (chip->driver_type == AZX_DRIVER_ATIHDMI)) { 2453 struct pci_dev *p_smbus; 2454 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 2455 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 2456 NULL); 2457 if (p_smbus) { 2458 if (p_smbus->revision < 0x30) 2459 gcap &= ~ICH6_GCAP_64OK; 2460 pci_dev_put(p_smbus); 2461 } 2462 } 2463 2464 /* disable 64bit DMA address for Teradici */ 2465 /* it does not work with device 6549:1200 subsys e4a2:040b */ 2466 if (chip->driver_type == AZX_DRIVER_TERA) 2467 gcap &= ~ICH6_GCAP_64OK; 2468 2469 /* allow 64bit DMA address if supported by H/W */ 2470 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64))) 2471 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64)); 2472 else { 2473 pci_set_dma_mask(pci, DMA_BIT_MASK(32)); 2474 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32)); 2475 } 2476 2477 /* read number of streams from GCAP register instead of using 2478 * hardcoded value 2479 */ 2480 chip->capture_streams = (gcap >> 8) & 0x0f; 2481 chip->playback_streams = (gcap >> 12) & 0x0f; 2482 if (!chip->playback_streams && !chip->capture_streams) { 2483 /* gcap didn't give any info, switching to old method */ 2484 2485 switch (chip->driver_type) { 2486 case AZX_DRIVER_ULI: 2487 chip->playback_streams = ULI_NUM_PLAYBACK; 2488 chip->capture_streams = ULI_NUM_CAPTURE; 2489 break; 2490 case AZX_DRIVER_ATIHDMI: 2491 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 2492 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 2493 break; 2494 case AZX_DRIVER_GENERIC: 2495 default: 2496 chip->playback_streams = ICH6_NUM_PLAYBACK; 2497 chip->capture_streams = ICH6_NUM_CAPTURE; 2498 break; 2499 } 2500 } 2501 chip->capture_index_offset = 0; 2502 chip->playback_index_offset = chip->capture_streams; 2503 chip->num_streams = chip->playback_streams + chip->capture_streams; 2504 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), 2505 GFP_KERNEL); 2506 if (!chip->azx_dev) { 2507 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n"); 2508 goto errout; 2509 } 2510 2511 for (i = 0; i < chip->num_streams; i++) { 2512 /* allocate memory for the BDL for each stream */ 2513 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, 2514 snd_dma_pci_data(chip->pci), 2515 BDL_SIZE, &chip->azx_dev[i].bdl); 2516 if (err < 0) { 2517 snd_printk(KERN_ERR SFX "cannot allocate BDL\n"); 2518 goto errout; 2519 } 2520 } 2521 /* allocate memory for the position buffer */ 2522 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, 2523 snd_dma_pci_data(chip->pci), 2524 chip->num_streams * 8, &chip->posbuf); 2525 if (err < 0) { 2526 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n"); 2527 goto errout; 2528 } 2529 /* allocate CORB/RIRB */ 2530 err = azx_alloc_cmd_io(chip); 2531 if (err < 0) 2532 goto errout; 2533 2534 /* initialize streams */ 2535 azx_init_stream(chip); 2536 2537 /* initialize chip */ 2538 azx_init_pci(chip); 2539 azx_init_chip(chip); 2540 2541 /* codec detection */ 2542 if (!chip->codec_mask) { 2543 snd_printk(KERN_ERR SFX "no codecs found!\n"); 2544 err = -ENODEV; 2545 goto errout; 2546 } 2547 2548 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 2549 if (err <0) { 2550 snd_printk(KERN_ERR SFX "Error creating device [card]!\n"); 2551 goto errout; 2552 } 2553 2554 strcpy(card->driver, "HDA-Intel"); 2555 strlcpy(card->shortname, driver_short_names[chip->driver_type], 2556 sizeof(card->shortname)); 2557 snprintf(card->longname, sizeof(card->longname), 2558 "%s at 0x%lx irq %i", 2559 card->shortname, chip->addr, chip->irq); 2560 2561 *rchip = chip; 2562 return 0; 2563 2564 errout: 2565 azx_free(chip); 2566 return err; 2567 } 2568 2569 static void power_down_all_codecs(struct azx *chip) 2570 { 2571 #ifdef CONFIG_SND_HDA_POWER_SAVE 2572 /* The codecs were powered up in snd_hda_codec_new(). 2573 * Now all initialization done, so turn them down if possible 2574 */ 2575 struct hda_codec *codec; 2576 list_for_each_entry(codec, &chip->bus->codec_list, list) { 2577 snd_hda_power_down(codec); 2578 } 2579 #endif 2580 } 2581 2582 static int __devinit azx_probe(struct pci_dev *pci, 2583 const struct pci_device_id *pci_id) 2584 { 2585 static int dev; 2586 struct snd_card *card; 2587 struct azx *chip; 2588 int err; 2589 2590 if (dev >= SNDRV_CARDS) 2591 return -ENODEV; 2592 if (!enable[dev]) { 2593 dev++; 2594 return -ENOENT; 2595 } 2596 2597 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card); 2598 if (err < 0) { 2599 snd_printk(KERN_ERR SFX "Error creating card!\n"); 2600 return err; 2601 } 2602 2603 /* set this here since it's referred in snd_hda_load_patch() */ 2604 snd_card_set_dev(card, &pci->dev); 2605 2606 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2607 if (err < 0) 2608 goto out_free; 2609 card->private_data = chip; 2610 2611 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2612 chip->beep_mode = beep_mode[dev]; 2613 #endif 2614 2615 /* create codec instances */ 2616 err = azx_codec_create(chip, model[dev]); 2617 if (err < 0) 2618 goto out_free; 2619 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2620 if (patch[dev]) { 2621 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n", 2622 patch[dev]); 2623 err = snd_hda_load_patch(chip->bus, patch[dev]); 2624 if (err < 0) 2625 goto out_free; 2626 } 2627 #endif 2628 if (!probe_only[dev]) { 2629 err = azx_codec_configure(chip); 2630 if (err < 0) 2631 goto out_free; 2632 } 2633 2634 /* create PCM streams */ 2635 err = snd_hda_build_pcms(chip->bus); 2636 if (err < 0) 2637 goto out_free; 2638 2639 /* create mixer controls */ 2640 err = azx_mixer_create(chip); 2641 if (err < 0) 2642 goto out_free; 2643 2644 err = snd_card_register(card); 2645 if (err < 0) 2646 goto out_free; 2647 2648 pci_set_drvdata(pci, card); 2649 chip->running = 1; 2650 power_down_all_codecs(chip); 2651 azx_notifier_register(chip); 2652 2653 dev++; 2654 return err; 2655 out_free: 2656 snd_card_free(card); 2657 return err; 2658 } 2659 2660 static void __devexit azx_remove(struct pci_dev *pci) 2661 { 2662 snd_card_free(pci_get_drvdata(pci)); 2663 pci_set_drvdata(pci, NULL); 2664 } 2665 2666 /* PCI IDs */ 2667 static struct pci_device_id azx_ids[] = { 2668 /* ICH 6..10 */ 2669 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH }, 2670 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH }, 2671 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH }, 2672 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH }, 2673 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH }, 2674 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH }, 2675 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH }, 2676 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH }, 2677 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH }, 2678 /* PCH */ 2679 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH }, 2680 /* SCH */ 2681 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH }, 2682 /* ATI SB 450/600 */ 2683 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI }, 2684 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI }, 2685 /* ATI HDMI */ 2686 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI }, 2687 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI }, 2688 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI }, 2689 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI }, 2690 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI }, 2691 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI }, 2692 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI }, 2693 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI }, 2694 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI }, 2695 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI }, 2696 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI }, 2697 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI }, 2698 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI }, 2699 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI }, 2700 /* VIA VT8251/VT8237A */ 2701 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2702 /* SIS966 */ 2703 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2704 /* ULI M5461 */ 2705 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2706 /* NVIDIA MCP */ 2707 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA }, 2708 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA }, 2709 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA }, 2710 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA }, 2711 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA }, 2712 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA }, 2713 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA }, 2714 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA }, 2715 { PCI_DEVICE(0x10de, 0x0590), .driver_data = AZX_DRIVER_NVIDIA }, 2716 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA }, 2717 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA }, 2718 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA }, 2719 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA }, 2720 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA }, 2721 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA }, 2722 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA }, 2723 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA }, 2724 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA }, 2725 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA }, 2726 { PCI_DEVICE(0x10de, 0x0be2), .driver_data = AZX_DRIVER_NVIDIA }, 2727 { PCI_DEVICE(0x10de, 0x0be3), .driver_data = AZX_DRIVER_NVIDIA }, 2728 { PCI_DEVICE(0x10de, 0x0be4), .driver_data = AZX_DRIVER_NVIDIA }, 2729 { PCI_DEVICE(0x10de, 0x0d94), .driver_data = AZX_DRIVER_NVIDIA }, 2730 { PCI_DEVICE(0x10de, 0x0d95), .driver_data = AZX_DRIVER_NVIDIA }, 2731 { PCI_DEVICE(0x10de, 0x0d96), .driver_data = AZX_DRIVER_NVIDIA }, 2732 { PCI_DEVICE(0x10de, 0x0d97), .driver_data = AZX_DRIVER_NVIDIA }, 2733 /* Teradici */ 2734 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA }, 2735 /* Creative X-Fi (CA0110-IBG) */ 2736 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE) 2737 /* the following entry conflicts with snd-ctxfi driver, 2738 * as ctxfi driver mutates from HD-audio to native mode with 2739 * a special command sequence. 2740 */ 2741 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2742 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2743 .class_mask = 0xffffff, 2744 .driver_data = AZX_DRIVER_GENERIC }, 2745 #else 2746 /* this entry seems still valid -- i.e. without emu20kx chip */ 2747 { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC }, 2748 #endif 2749 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2750 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2751 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2752 .class_mask = 0xffffff, 2753 .driver_data = AZX_DRIVER_GENERIC }, 2754 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2755 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2756 .class_mask = 0xffffff, 2757 .driver_data = AZX_DRIVER_GENERIC }, 2758 { 0, } 2759 }; 2760 MODULE_DEVICE_TABLE(pci, azx_ids); 2761 2762 /* pci_driver definition */ 2763 static struct pci_driver driver = { 2764 .name = "HDA Intel", 2765 .id_table = azx_ids, 2766 .probe = azx_probe, 2767 .remove = __devexit_p(azx_remove), 2768 #ifdef CONFIG_PM 2769 .suspend = azx_suspend, 2770 .resume = azx_resume, 2771 #endif 2772 }; 2773 2774 static int __init alsa_card_azx_init(void) 2775 { 2776 return pci_register_driver(&driver); 2777 } 2778 2779 static void __exit alsa_card_azx_exit(void) 2780 { 2781 pci_unregister_driver(&driver); 2782 } 2783 2784 module_init(alsa_card_azx_init) 2785 module_exit(alsa_card_azx_exit) 2786