1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * hda_intel.c - Implementation of primary alsa driver code base 5 * for Intel HD Audio. 6 * 7 * Copyright(c) 2004 Intel Corporation. All rights reserved. 8 * 9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 10 * PeiSen Hou <pshou@realtek.com.tw> 11 * 12 * CONTACTS: 13 * 14 * Matt Jared matt.jared@intel.com 15 * Andy Kopp andy.kopp@intel.com 16 * Dan Kogan dan.d.kogan@intel.com 17 * 18 * CHANGES: 19 * 20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/moduleparam.h> 29 #include <linux/init.h> 30 #include <linux/slab.h> 31 #include <linux/pci.h> 32 #include <linux/mutex.h> 33 #include <linux/io.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/clocksource.h> 36 #include <linux/time.h> 37 #include <linux/completion.h> 38 #include <linux/acpi.h> 39 #include <linux/pgtable.h> 40 41 #ifdef CONFIG_X86 42 /* for snoop control */ 43 #include <asm/set_memory.h> 44 #include <asm/cpufeature.h> 45 #endif 46 #include <sound/core.h> 47 #include <sound/initval.h> 48 #include <sound/hdaudio.h> 49 #include <sound/hda_i915.h> 50 #include <sound/intel-dsp-config.h> 51 #include <linux/vgaarb.h> 52 #include <linux/vga_switcheroo.h> 53 #include <linux/apple-gmux.h> 54 #include <linux/firmware.h> 55 #include <sound/hda_codec.h> 56 #include "hda_controller.h" 57 #include "hda_intel.h" 58 59 #define CREATE_TRACE_POINTS 60 #include "hda_intel_trace.h" 61 62 /* position fix mode */ 63 enum { 64 POS_FIX_AUTO, 65 POS_FIX_LPIB, 66 POS_FIX_POSBUF, 67 POS_FIX_VIACOMBO, 68 POS_FIX_COMBO, 69 POS_FIX_SKL, 70 POS_FIX_FIFO, 71 }; 72 73 /* Defines for ATI HD Audio support in SB450 south bridge */ 74 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 75 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 76 77 /* Defines for Nvidia HDA support */ 78 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 79 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 80 #define NVIDIA_HDA_ISTRM_COH 0x4d 81 #define NVIDIA_HDA_OSTRM_COH 0x4c 82 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 83 84 /* Defines for Intel SCH HDA snoop control */ 85 #define INTEL_HDA_CGCTL 0x48 86 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) 87 #define INTEL_SCH_HDA_DEVC 0x78 88 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 89 90 /* max number of SDs */ 91 /* ICH, ATI and VIA have 4 playback and 4 capture */ 92 #define ICH6_NUM_CAPTURE 4 93 #define ICH6_NUM_PLAYBACK 4 94 95 /* ULI has 6 playback and 5 capture */ 96 #define ULI_NUM_CAPTURE 5 97 #define ULI_NUM_PLAYBACK 6 98 99 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 100 #define ATIHDMI_NUM_CAPTURE 0 101 #define ATIHDMI_NUM_PLAYBACK 8 102 103 104 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 105 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 106 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 107 static char *model[SNDRV_CARDS]; 108 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 109 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 110 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 111 static int probe_only[SNDRV_CARDS]; 112 static int jackpoll_ms[SNDRV_CARDS]; 113 static int single_cmd = -1; 114 static int enable_msi = -1; 115 #ifdef CONFIG_SND_HDA_PATCH_LOADER 116 static char *patch[SNDRV_CARDS]; 117 #endif 118 #ifdef CONFIG_SND_HDA_INPUT_BEEP 119 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 120 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 121 #endif 122 static bool dmic_detect = 1; 123 static bool ctl_dev_id = IS_ENABLED(CONFIG_SND_HDA_CTL_DEV_ID) ? 1 : 0; 124 125 module_param_array(index, int, NULL, 0444); 126 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 127 module_param_array(id, charp, NULL, 0444); 128 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 129 module_param_array(enable, bool, NULL, 0444); 130 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 131 module_param_array(model, charp, NULL, 0444); 132 MODULE_PARM_DESC(model, "Use the given board model."); 133 module_param_array(position_fix, int, NULL, 0444); 134 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 135 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO)."); 136 module_param_array(bdl_pos_adj, int, NULL, 0644); 137 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 138 module_param_array(probe_mask, int, NULL, 0444); 139 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 140 module_param_array(probe_only, int, NULL, 0444); 141 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 142 module_param_array(jackpoll_ms, int, NULL, 0444); 143 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 144 module_param(single_cmd, bint, 0444); 145 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 146 "(for debugging only)."); 147 module_param(enable_msi, bint, 0444); 148 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 149 #ifdef CONFIG_SND_HDA_PATCH_LOADER 150 module_param_array(patch, charp, NULL, 0444); 151 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 152 #endif 153 #ifdef CONFIG_SND_HDA_INPUT_BEEP 154 module_param_array(beep_mode, bool, NULL, 0444); 155 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 156 "(0=off, 1=on) (default=1)."); 157 #endif 158 module_param(dmic_detect, bool, 0444); 159 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) " 160 "(0=off, 1=on) (default=1); " 161 "deprecated, use snd-intel-dspcfg.dsp_driver option instead"); 162 module_param(ctl_dev_id, bool, 0444); 163 MODULE_PARM_DESC(ctl_dev_id, "Use control device identifier (based on codec address)."); 164 165 #ifdef CONFIG_PM 166 static int param_set_xint(const char *val, const struct kernel_param *kp); 167 static const struct kernel_param_ops param_ops_xint = { 168 .set = param_set_xint, 169 .get = param_get_int, 170 }; 171 #define param_check_xint param_check_int 172 173 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 174 module_param(power_save, xint, 0644); 175 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 176 "(in second, 0 = disable)."); 177 178 static bool pm_blacklist = true; 179 module_param(pm_blacklist, bool, 0644); 180 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist"); 181 182 /* reset the HD-audio controller in power save mode. 183 * this may give more power-saving, but will take longer time to 184 * wake up. 185 */ 186 static bool power_save_controller = 1; 187 module_param(power_save_controller, bool, 0644); 188 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 189 #else 190 #define power_save 0 191 #endif /* CONFIG_PM */ 192 193 static int align_buffer_size = -1; 194 module_param(align_buffer_size, bint, 0644); 195 MODULE_PARM_DESC(align_buffer_size, 196 "Force buffer and period sizes to be multiple of 128 bytes."); 197 198 #ifdef CONFIG_X86 199 static int hda_snoop = -1; 200 module_param_named(snoop, hda_snoop, bint, 0444); 201 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 202 #else 203 #define hda_snoop true 204 #endif 205 206 207 MODULE_LICENSE("GPL"); 208 MODULE_DESCRIPTION("Intel HDA driver"); 209 210 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 211 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 212 #define SUPPORT_VGA_SWITCHEROO 213 #endif 214 #endif 215 216 217 /* 218 */ 219 220 /* driver types */ 221 enum { 222 AZX_DRIVER_ICH, 223 AZX_DRIVER_PCH, 224 AZX_DRIVER_SCH, 225 AZX_DRIVER_SKL, 226 AZX_DRIVER_HDMI, 227 AZX_DRIVER_ATI, 228 AZX_DRIVER_ATIHDMI, 229 AZX_DRIVER_ATIHDMI_NS, 230 AZX_DRIVER_VIA, 231 AZX_DRIVER_SIS, 232 AZX_DRIVER_ULI, 233 AZX_DRIVER_NVIDIA, 234 AZX_DRIVER_TERA, 235 AZX_DRIVER_CTX, 236 AZX_DRIVER_CTHDA, 237 AZX_DRIVER_CMEDIA, 238 AZX_DRIVER_ZHAOXIN, 239 AZX_DRIVER_GENERIC, 240 AZX_NUM_DRIVERS, /* keep this as last entry */ 241 }; 242 243 #define azx_get_snoop_type(chip) \ 244 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 245 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 246 247 /* quirks for old Intel chipsets */ 248 #define AZX_DCAPS_INTEL_ICH \ 249 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 250 251 /* quirks for Intel PCH */ 252 #define AZX_DCAPS_INTEL_PCH_BASE \ 253 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 254 AZX_DCAPS_SNOOP_TYPE(SCH)) 255 256 /* PCH up to IVB; no runtime PM; bind with i915 gfx */ 257 #define AZX_DCAPS_INTEL_PCH_NOPM \ 258 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 259 260 /* PCH for HSW/BDW; with runtime PM */ 261 /* no i915 binding for this as HSW/BDW has another controller for HDMI */ 262 #define AZX_DCAPS_INTEL_PCH \ 263 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) 264 265 /* HSW HDMI */ 266 #define AZX_DCAPS_INTEL_HASWELL \ 267 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 268 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 269 AZX_DCAPS_SNOOP_TYPE(SCH)) 270 271 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 272 #define AZX_DCAPS_INTEL_BROADWELL \ 273 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 274 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 275 AZX_DCAPS_SNOOP_TYPE(SCH)) 276 277 #define AZX_DCAPS_INTEL_BAYTRAIL \ 278 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 279 280 #define AZX_DCAPS_INTEL_BRASWELL \ 281 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 282 AZX_DCAPS_I915_COMPONENT) 283 284 #define AZX_DCAPS_INTEL_SKYLAKE \ 285 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 286 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT) 287 288 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE 289 290 /* quirks for ATI SB / AMD Hudson */ 291 #define AZX_DCAPS_PRESET_ATI_SB \ 292 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\ 293 AZX_DCAPS_SNOOP_TYPE(ATI)) 294 295 /* quirks for ATI/AMD HDMI */ 296 #define AZX_DCAPS_PRESET_ATI_HDMI \ 297 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\ 298 AZX_DCAPS_NO_MSI64) 299 300 /* quirks for ATI HDMI with snoop off */ 301 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 302 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 303 304 /* quirks for AMD SB */ 305 #define AZX_DCAPS_PRESET_AMD_SB \ 306 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\ 307 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\ 308 AZX_DCAPS_RETRY_PROBE) 309 310 /* quirks for Nvidia */ 311 #define AZX_DCAPS_PRESET_NVIDIA \ 312 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 313 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 314 315 #define AZX_DCAPS_PRESET_CTHDA \ 316 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 317 AZX_DCAPS_NO_64BIT |\ 318 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 319 320 /* 321 * vga_switcheroo support 322 */ 323 #ifdef SUPPORT_VGA_SWITCHEROO 324 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 325 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power) 326 #else 327 #define use_vga_switcheroo(chip) 0 328 #define needs_eld_notify_link(chip) false 329 #endif 330 331 #define CONTROLLER_IN_GPU(pci) (((pci)->vendor == 0x8086) && \ 332 (((pci)->device == 0x0a0c) || \ 333 ((pci)->device == 0x0c0c) || \ 334 ((pci)->device == 0x0d0c) || \ 335 ((pci)->device == 0x160c) || \ 336 ((pci)->device == 0x490d) || \ 337 ((pci)->device == 0x4f90) || \ 338 ((pci)->device == 0x4f91) || \ 339 ((pci)->device == 0x4f92))) 340 341 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98) 342 343 static const char * const driver_short_names[] = { 344 [AZX_DRIVER_ICH] = "HDA Intel", 345 [AZX_DRIVER_PCH] = "HDA Intel PCH", 346 [AZX_DRIVER_SCH] = "HDA Intel MID", 347 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */ 348 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 349 [AZX_DRIVER_ATI] = "HDA ATI SB", 350 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 351 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 352 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 353 [AZX_DRIVER_SIS] = "HDA SIS966", 354 [AZX_DRIVER_ULI] = "HDA ULI M5461", 355 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 356 [AZX_DRIVER_TERA] = "HDA Teradici", 357 [AZX_DRIVER_CTX] = "HDA Creative", 358 [AZX_DRIVER_CTHDA] = "HDA Creative", 359 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 360 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin", 361 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 362 }; 363 364 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 365 static void set_default_power_save(struct azx *chip); 366 367 /* 368 * initialize the PCI registers 369 */ 370 /* update bits in a PCI register byte */ 371 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 372 unsigned char mask, unsigned char val) 373 { 374 unsigned char data; 375 376 pci_read_config_byte(pci, reg, &data); 377 data &= ~mask; 378 data |= (val & mask); 379 pci_write_config_byte(pci, reg, data); 380 } 381 382 static void azx_init_pci(struct azx *chip) 383 { 384 int snoop_type = azx_get_snoop_type(chip); 385 386 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 387 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 388 * Ensuring these bits are 0 clears playback static on some HD Audio 389 * codecs. 390 * The PCI register TCSEL is defined in the Intel manuals. 391 */ 392 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 393 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 394 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 395 } 396 397 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 398 * we need to enable snoop. 399 */ 400 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 401 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 402 azx_snoop(chip)); 403 update_pci_byte(chip->pci, 404 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 405 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 406 } 407 408 /* For NVIDIA HDA, enable snoop */ 409 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 410 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 411 azx_snoop(chip)); 412 update_pci_byte(chip->pci, 413 NVIDIA_HDA_TRANSREG_ADDR, 414 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 415 update_pci_byte(chip->pci, 416 NVIDIA_HDA_ISTRM_COH, 417 0x01, NVIDIA_HDA_ENABLE_COHBIT); 418 update_pci_byte(chip->pci, 419 NVIDIA_HDA_OSTRM_COH, 420 0x01, NVIDIA_HDA_ENABLE_COHBIT); 421 } 422 423 /* Enable SCH/PCH snoop if needed */ 424 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 425 unsigned short snoop; 426 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 427 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 428 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 429 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 430 if (!azx_snoop(chip)) 431 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 432 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 433 pci_read_config_word(chip->pci, 434 INTEL_SCH_HDA_DEVC, &snoop); 435 } 436 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 437 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 438 "Disabled" : "Enabled"); 439 } 440 } 441 442 /* 443 * In BXT-P A0, HD-Audio DMA requests is later than expected, 444 * and makes an audio stream sensitive to system latencies when 445 * 24/32 bits are playing. 446 * Adjusting threshold of DMA fifo to force the DMA request 447 * sooner to improve latency tolerance at the expense of power. 448 */ 449 static void bxt_reduce_dma_latency(struct azx *chip) 450 { 451 u32 val; 452 453 val = azx_readl(chip, VS_EM4L); 454 val &= (0x3 << 20); 455 azx_writel(chip, VS_EM4L, val); 456 } 457 458 /* 459 * ML_LCAP bits: 460 * bit 0: 6 MHz Supported 461 * bit 1: 12 MHz Supported 462 * bit 2: 24 MHz Supported 463 * bit 3: 48 MHz Supported 464 * bit 4: 96 MHz Supported 465 * bit 5: 192 MHz Supported 466 */ 467 static int intel_get_lctl_scf(struct azx *chip) 468 { 469 struct hdac_bus *bus = azx_bus(chip); 470 static const int preferred_bits[] = { 2, 3, 1, 4, 5 }; 471 u32 val, t; 472 int i; 473 474 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); 475 476 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) { 477 t = preferred_bits[i]; 478 if (val & (1 << t)) 479 return t; 480 } 481 482 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz"); 483 return 0; 484 } 485 486 static int intel_ml_lctl_set_power(struct azx *chip, int state) 487 { 488 struct hdac_bus *bus = azx_bus(chip); 489 u32 val; 490 int timeout; 491 492 /* 493 * Changes to LCTL.SCF are only needed for the first multi-link dealing 494 * with external codecs 495 */ 496 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 497 val &= ~AZX_ML_LCTL_SPA; 498 val |= state << AZX_ML_LCTL_SPA_SHIFT; 499 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 500 /* wait for CPA */ 501 timeout = 50; 502 while (timeout) { 503 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) & 504 AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT)) 505 return 0; 506 timeout--; 507 udelay(10); 508 } 509 510 return -1; 511 } 512 513 static void intel_init_lctl(struct azx *chip) 514 { 515 struct hdac_bus *bus = azx_bus(chip); 516 u32 val; 517 int ret; 518 519 /* 0. check lctl register value is correct or not */ 520 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 521 /* only perform additional configurations if the SCF is initially based on 6MHz */ 522 if ((val & AZX_ML_LCTL_SCF) != 0) 523 return; 524 525 /* 526 * Before operating on SPA, CPA must match SPA. 527 * Any deviation may result in undefined behavior. 528 */ 529 if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) != 530 ((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT)) 531 return; 532 533 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */ 534 ret = intel_ml_lctl_set_power(chip, 0); 535 udelay(100); 536 if (ret) 537 goto set_spa; 538 539 /* 2. update SCF to select an audio clock different from 6MHz */ 540 val &= ~AZX_ML_LCTL_SCF; 541 val |= intel_get_lctl_scf(chip); 542 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 543 544 set_spa: 545 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */ 546 intel_ml_lctl_set_power(chip, 1); 547 udelay(100); 548 } 549 550 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 551 { 552 struct hdac_bus *bus = azx_bus(chip); 553 struct pci_dev *pci = chip->pci; 554 u32 val; 555 556 snd_hdac_set_codec_wakeup(bus, true); 557 if (chip->driver_type == AZX_DRIVER_SKL) { 558 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 559 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; 560 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 561 } 562 azx_init_chip(chip, full_reset); 563 if (chip->driver_type == AZX_DRIVER_SKL) { 564 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 565 val = val | INTEL_HDA_CGCTL_MISCBDCGE; 566 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 567 } 568 569 snd_hdac_set_codec_wakeup(bus, false); 570 571 /* reduce dma latency to avoid noise */ 572 if (IS_BXT(pci)) 573 bxt_reduce_dma_latency(chip); 574 575 if (bus->mlcap != NULL) 576 intel_init_lctl(chip); 577 } 578 579 /* calculate runtime delay from LPIB */ 580 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 581 unsigned int pos) 582 { 583 struct snd_pcm_substream *substream = azx_dev->core.substream; 584 int stream = substream->stream; 585 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 586 int delay; 587 588 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 589 delay = pos - lpib_pos; 590 else 591 delay = lpib_pos - pos; 592 if (delay < 0) { 593 if (delay >= azx_dev->core.delay_negative_threshold) 594 delay = 0; 595 else 596 delay += azx_dev->core.bufsize; 597 } 598 599 if (delay >= azx_dev->core.period_bytes) { 600 dev_info(chip->card->dev, 601 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 602 delay, azx_dev->core.period_bytes); 603 delay = 0; 604 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 605 chip->get_delay[stream] = NULL; 606 } 607 608 return bytes_to_frames(substream->runtime, delay); 609 } 610 611 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 612 613 /* called from IRQ */ 614 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 615 { 616 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 617 int ok; 618 619 ok = azx_position_ok(chip, azx_dev); 620 if (ok == 1) { 621 azx_dev->irq_pending = 0; 622 return ok; 623 } else if (ok == 0) { 624 /* bogus IRQ, process it later */ 625 azx_dev->irq_pending = 1; 626 schedule_work(&hda->irq_pending_work); 627 } 628 return 0; 629 } 630 631 #define display_power(chip, enable) \ 632 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable) 633 634 /* 635 * Check whether the current DMA position is acceptable for updating 636 * periods. Returns non-zero if it's OK. 637 * 638 * Many HD-audio controllers appear pretty inaccurate about 639 * the update-IRQ timing. The IRQ is issued before actually the 640 * data is processed. So, we need to process it afterwords in a 641 * workqueue. 642 * 643 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update 644 */ 645 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 646 { 647 struct snd_pcm_substream *substream = azx_dev->core.substream; 648 struct snd_pcm_runtime *runtime = substream->runtime; 649 int stream = substream->stream; 650 u32 wallclk; 651 unsigned int pos; 652 snd_pcm_uframes_t hwptr, target; 653 654 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 655 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 656 return -1; /* bogus (too early) interrupt */ 657 658 if (chip->get_position[stream]) 659 pos = chip->get_position[stream](chip, azx_dev); 660 else { /* use the position buffer as default */ 661 pos = azx_get_pos_posbuf(chip, azx_dev); 662 if (!pos || pos == (u32)-1) { 663 dev_info(chip->card->dev, 664 "Invalid position buffer, using LPIB read method instead.\n"); 665 chip->get_position[stream] = azx_get_pos_lpib; 666 if (chip->get_position[0] == azx_get_pos_lpib && 667 chip->get_position[1] == azx_get_pos_lpib) 668 azx_bus(chip)->use_posbuf = false; 669 pos = azx_get_pos_lpib(chip, azx_dev); 670 chip->get_delay[stream] = NULL; 671 } else { 672 chip->get_position[stream] = azx_get_pos_posbuf; 673 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 674 chip->get_delay[stream] = azx_get_delay_from_lpib; 675 } 676 } 677 678 if (pos >= azx_dev->core.bufsize) 679 pos = 0; 680 681 if (WARN_ONCE(!azx_dev->core.period_bytes, 682 "hda-intel: zero azx_dev->period_bytes")) 683 return -1; /* this shouldn't happen! */ 684 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 685 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 686 /* NG - it's below the first next period boundary */ 687 return chip->bdl_pos_adj ? 0 : -1; 688 azx_dev->core.start_wallclk += wallclk; 689 690 if (azx_dev->core.no_period_wakeup) 691 return 1; /* OK, no need to check period boundary */ 692 693 if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt) 694 return 1; /* OK, already in hwptr updating process */ 695 696 /* check whether the period gets really elapsed */ 697 pos = bytes_to_frames(runtime, pos); 698 hwptr = runtime->hw_ptr_base + pos; 699 if (hwptr < runtime->status->hw_ptr) 700 hwptr += runtime->buffer_size; 701 target = runtime->hw_ptr_interrupt + runtime->period_size; 702 if (hwptr < target) { 703 /* too early wakeup, process it later */ 704 return chip->bdl_pos_adj ? 0 : -1; 705 } 706 707 return 1; /* OK, it's fine */ 708 } 709 710 /* 711 * The work for pending PCM period updates. 712 */ 713 static void azx_irq_pending_work(struct work_struct *work) 714 { 715 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 716 struct azx *chip = &hda->chip; 717 struct hdac_bus *bus = azx_bus(chip); 718 struct hdac_stream *s; 719 int pending, ok; 720 721 if (!hda->irq_pending_warned) { 722 dev_info(chip->card->dev, 723 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 724 chip->card->number); 725 hda->irq_pending_warned = 1; 726 } 727 728 for (;;) { 729 pending = 0; 730 spin_lock_irq(&bus->reg_lock); 731 list_for_each_entry(s, &bus->stream_list, list) { 732 struct azx_dev *azx_dev = stream_to_azx_dev(s); 733 if (!azx_dev->irq_pending || 734 !s->substream || 735 !s->running) 736 continue; 737 ok = azx_position_ok(chip, azx_dev); 738 if (ok > 0) { 739 azx_dev->irq_pending = 0; 740 spin_unlock(&bus->reg_lock); 741 snd_pcm_period_elapsed(s->substream); 742 spin_lock(&bus->reg_lock); 743 } else if (ok < 0) { 744 pending = 0; /* too early */ 745 } else 746 pending++; 747 } 748 spin_unlock_irq(&bus->reg_lock); 749 if (!pending) 750 return; 751 msleep(1); 752 } 753 } 754 755 /* clear irq_pending flags and assure no on-going workq */ 756 static void azx_clear_irq_pending(struct azx *chip) 757 { 758 struct hdac_bus *bus = azx_bus(chip); 759 struct hdac_stream *s; 760 761 spin_lock_irq(&bus->reg_lock); 762 list_for_each_entry(s, &bus->stream_list, list) { 763 struct azx_dev *azx_dev = stream_to_azx_dev(s); 764 azx_dev->irq_pending = 0; 765 } 766 spin_unlock_irq(&bus->reg_lock); 767 } 768 769 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 770 { 771 struct hdac_bus *bus = azx_bus(chip); 772 773 if (request_irq(chip->pci->irq, azx_interrupt, 774 chip->msi ? 0 : IRQF_SHARED, 775 chip->card->irq_descr, chip)) { 776 dev_err(chip->card->dev, 777 "unable to grab IRQ %d, disabling device\n", 778 chip->pci->irq); 779 if (do_disconnect) 780 snd_card_disconnect(chip->card); 781 return -1; 782 } 783 bus->irq = chip->pci->irq; 784 chip->card->sync_irq = bus->irq; 785 pci_intx(chip->pci, !chip->msi); 786 return 0; 787 } 788 789 /* get the current DMA position with correction on VIA chips */ 790 static unsigned int azx_via_get_position(struct azx *chip, 791 struct azx_dev *azx_dev) 792 { 793 unsigned int link_pos, mini_pos, bound_pos; 794 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 795 unsigned int fifo_size; 796 797 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 798 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 799 /* Playback, no problem using link position */ 800 return link_pos; 801 } 802 803 /* Capture */ 804 /* For new chipset, 805 * use mod to get the DMA position just like old chipset 806 */ 807 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 808 mod_dma_pos %= azx_dev->core.period_bytes; 809 810 fifo_size = azx_stream(azx_dev)->fifo_size - 1; 811 812 if (azx_dev->insufficient) { 813 /* Link position never gather than FIFO size */ 814 if (link_pos <= fifo_size) 815 return 0; 816 817 azx_dev->insufficient = 0; 818 } 819 820 if (link_pos <= fifo_size) 821 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 822 else 823 mini_pos = link_pos - fifo_size; 824 825 /* Find nearest previous boudary */ 826 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 827 mod_link_pos = link_pos % azx_dev->core.period_bytes; 828 if (mod_link_pos >= fifo_size) 829 bound_pos = link_pos - mod_link_pos; 830 else if (mod_dma_pos >= mod_mini_pos) 831 bound_pos = mini_pos - mod_mini_pos; 832 else { 833 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 834 if (bound_pos >= azx_dev->core.bufsize) 835 bound_pos = 0; 836 } 837 838 /* Calculate real DMA position we want */ 839 return bound_pos + mod_dma_pos; 840 } 841 842 #define AMD_FIFO_SIZE 32 843 844 /* get the current DMA position with FIFO size correction */ 845 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev) 846 { 847 struct snd_pcm_substream *substream = azx_dev->core.substream; 848 struct snd_pcm_runtime *runtime = substream->runtime; 849 unsigned int pos, delay; 850 851 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 852 if (!runtime) 853 return pos; 854 855 runtime->delay = AMD_FIFO_SIZE; 856 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE); 857 if (azx_dev->insufficient) { 858 if (pos < delay) { 859 delay = pos; 860 runtime->delay = bytes_to_frames(runtime, pos); 861 } else { 862 azx_dev->insufficient = 0; 863 } 864 } 865 866 /* correct the DMA position for capture stream */ 867 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 868 if (pos < delay) 869 pos += azx_dev->core.bufsize; 870 pos -= delay; 871 } 872 873 return pos; 874 } 875 876 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev, 877 unsigned int pos) 878 { 879 struct snd_pcm_substream *substream = azx_dev->core.substream; 880 881 /* just read back the calculated value in the above */ 882 return substream->runtime->delay; 883 } 884 885 static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset) 886 { 887 azx_stop_chip(chip); 888 if (!skip_link_reset) 889 azx_enter_link_reset(chip); 890 azx_clear_irq_pending(chip); 891 display_power(chip, false); 892 } 893 894 #ifdef CONFIG_PM 895 static DEFINE_MUTEX(card_list_lock); 896 static LIST_HEAD(card_list); 897 898 static void azx_shutdown_chip(struct azx *chip) 899 { 900 __azx_shutdown_chip(chip, false); 901 } 902 903 static void azx_add_card_list(struct azx *chip) 904 { 905 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 906 mutex_lock(&card_list_lock); 907 list_add(&hda->list, &card_list); 908 mutex_unlock(&card_list_lock); 909 } 910 911 static void azx_del_card_list(struct azx *chip) 912 { 913 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 914 mutex_lock(&card_list_lock); 915 list_del_init(&hda->list); 916 mutex_unlock(&card_list_lock); 917 } 918 919 /* trigger power-save check at writing parameter */ 920 static int param_set_xint(const char *val, const struct kernel_param *kp) 921 { 922 struct hda_intel *hda; 923 struct azx *chip; 924 int prev = power_save; 925 int ret = param_set_int(val, kp); 926 927 if (ret || prev == power_save) 928 return ret; 929 930 mutex_lock(&card_list_lock); 931 list_for_each_entry(hda, &card_list, list) { 932 chip = &hda->chip; 933 if (!hda->probe_continued || chip->disabled) 934 continue; 935 snd_hda_set_power_save(&chip->bus, power_save * 1000); 936 } 937 mutex_unlock(&card_list_lock); 938 return 0; 939 } 940 941 /* 942 * power management 943 */ 944 static bool azx_is_pm_ready(struct snd_card *card) 945 { 946 struct azx *chip; 947 struct hda_intel *hda; 948 949 if (!card) 950 return false; 951 chip = card->private_data; 952 hda = container_of(chip, struct hda_intel, chip); 953 if (chip->disabled || hda->init_failed || !chip->running) 954 return false; 955 return true; 956 } 957 958 static void __azx_runtime_resume(struct azx *chip) 959 { 960 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 961 struct hdac_bus *bus = azx_bus(chip); 962 struct hda_codec *codec; 963 int status; 964 965 display_power(chip, true); 966 if (hda->need_i915_power) 967 snd_hdac_i915_set_bclk(bus); 968 969 /* Read STATESTS before controller reset */ 970 status = azx_readw(chip, STATESTS); 971 972 azx_init_pci(chip); 973 hda_intel_init_chip(chip, true); 974 975 /* Avoid codec resume if runtime resume is for system suspend */ 976 if (!chip->pm_prepared) { 977 list_for_each_codec(codec, &chip->bus) { 978 if (codec->relaxed_resume) 979 continue; 980 981 if (codec->forced_resume || (status & (1 << codec->addr))) 982 pm_request_resume(hda_codec_dev(codec)); 983 } 984 } 985 986 /* power down again for link-controlled chips */ 987 if (!hda->need_i915_power) 988 display_power(chip, false); 989 } 990 991 #ifdef CONFIG_PM_SLEEP 992 static int azx_prepare(struct device *dev) 993 { 994 struct snd_card *card = dev_get_drvdata(dev); 995 struct azx *chip; 996 997 if (!azx_is_pm_ready(card)) 998 return 0; 999 1000 chip = card->private_data; 1001 chip->pm_prepared = 1; 1002 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1003 1004 flush_work(&azx_bus(chip)->unsol_work); 1005 1006 /* HDA controller always requires different WAKEEN for runtime suspend 1007 * and system suspend, so don't use direct-complete here. 1008 */ 1009 return 0; 1010 } 1011 1012 static void azx_complete(struct device *dev) 1013 { 1014 struct snd_card *card = dev_get_drvdata(dev); 1015 struct azx *chip; 1016 1017 if (!azx_is_pm_ready(card)) 1018 return; 1019 1020 chip = card->private_data; 1021 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1022 chip->pm_prepared = 0; 1023 } 1024 1025 static int azx_suspend(struct device *dev) 1026 { 1027 struct snd_card *card = dev_get_drvdata(dev); 1028 struct azx *chip; 1029 struct hdac_bus *bus; 1030 1031 if (!azx_is_pm_ready(card)) 1032 return 0; 1033 1034 chip = card->private_data; 1035 bus = azx_bus(chip); 1036 azx_shutdown_chip(chip); 1037 if (bus->irq >= 0) { 1038 free_irq(bus->irq, chip); 1039 bus->irq = -1; 1040 chip->card->sync_irq = -1; 1041 } 1042 1043 if (chip->msi) 1044 pci_disable_msi(chip->pci); 1045 1046 trace_azx_suspend(chip); 1047 return 0; 1048 } 1049 1050 static int azx_resume(struct device *dev) 1051 { 1052 struct snd_card *card = dev_get_drvdata(dev); 1053 struct azx *chip; 1054 1055 if (!azx_is_pm_ready(card)) 1056 return 0; 1057 1058 chip = card->private_data; 1059 if (chip->msi) 1060 if (pci_enable_msi(chip->pci) < 0) 1061 chip->msi = 0; 1062 if (azx_acquire_irq(chip, 1) < 0) 1063 return -EIO; 1064 1065 __azx_runtime_resume(chip); 1066 1067 trace_azx_resume(chip); 1068 return 0; 1069 } 1070 1071 /* put codec down to D3 at hibernation for Intel SKL+; 1072 * otherwise BIOS may still access the codec and screw up the driver 1073 */ 1074 static int azx_freeze_noirq(struct device *dev) 1075 { 1076 struct snd_card *card = dev_get_drvdata(dev); 1077 struct azx *chip = card->private_data; 1078 struct pci_dev *pci = to_pci_dev(dev); 1079 1080 if (!azx_is_pm_ready(card)) 1081 return 0; 1082 if (chip->driver_type == AZX_DRIVER_SKL) 1083 pci_set_power_state(pci, PCI_D3hot); 1084 1085 return 0; 1086 } 1087 1088 static int azx_thaw_noirq(struct device *dev) 1089 { 1090 struct snd_card *card = dev_get_drvdata(dev); 1091 struct azx *chip = card->private_data; 1092 struct pci_dev *pci = to_pci_dev(dev); 1093 1094 if (!azx_is_pm_ready(card)) 1095 return 0; 1096 if (chip->driver_type == AZX_DRIVER_SKL) 1097 pci_set_power_state(pci, PCI_D0); 1098 1099 return 0; 1100 } 1101 #endif /* CONFIG_PM_SLEEP */ 1102 1103 static int azx_runtime_suspend(struct device *dev) 1104 { 1105 struct snd_card *card = dev_get_drvdata(dev); 1106 struct azx *chip; 1107 1108 if (!azx_is_pm_ready(card)) 1109 return 0; 1110 chip = card->private_data; 1111 1112 /* enable controller wake up event */ 1113 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK); 1114 1115 azx_shutdown_chip(chip); 1116 trace_azx_runtime_suspend(chip); 1117 return 0; 1118 } 1119 1120 static int azx_runtime_resume(struct device *dev) 1121 { 1122 struct snd_card *card = dev_get_drvdata(dev); 1123 struct azx *chip; 1124 1125 if (!azx_is_pm_ready(card)) 1126 return 0; 1127 chip = card->private_data; 1128 __azx_runtime_resume(chip); 1129 1130 /* disable controller Wake Up event*/ 1131 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK); 1132 1133 trace_azx_runtime_resume(chip); 1134 return 0; 1135 } 1136 1137 static int azx_runtime_idle(struct device *dev) 1138 { 1139 struct snd_card *card = dev_get_drvdata(dev); 1140 struct azx *chip; 1141 struct hda_intel *hda; 1142 1143 if (!card) 1144 return 0; 1145 1146 chip = card->private_data; 1147 hda = container_of(chip, struct hda_intel, chip); 1148 if (chip->disabled || hda->init_failed) 1149 return 0; 1150 1151 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1152 azx_bus(chip)->codec_powered || !chip->running) 1153 return -EBUSY; 1154 1155 /* ELD notification gets broken when HD-audio bus is off */ 1156 if (needs_eld_notify_link(chip)) 1157 return -EBUSY; 1158 1159 return 0; 1160 } 1161 1162 static const struct dev_pm_ops azx_pm = { 1163 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1164 #ifdef CONFIG_PM_SLEEP 1165 .prepare = azx_prepare, 1166 .complete = azx_complete, 1167 .freeze_noirq = azx_freeze_noirq, 1168 .thaw_noirq = azx_thaw_noirq, 1169 #endif 1170 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1171 }; 1172 1173 #define AZX_PM_OPS &azx_pm 1174 #else 1175 #define azx_add_card_list(chip) /* NOP */ 1176 #define azx_del_card_list(chip) /* NOP */ 1177 #define AZX_PM_OPS NULL 1178 #endif /* CONFIG_PM */ 1179 1180 1181 static int azx_probe_continue(struct azx *chip); 1182 1183 #ifdef SUPPORT_VGA_SWITCHEROO 1184 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1185 1186 static void azx_vs_set_state(struct pci_dev *pci, 1187 enum vga_switcheroo_state state) 1188 { 1189 struct snd_card *card = pci_get_drvdata(pci); 1190 struct azx *chip = card->private_data; 1191 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1192 struct hda_codec *codec; 1193 bool disabled; 1194 1195 wait_for_completion(&hda->probe_wait); 1196 if (hda->init_failed) 1197 return; 1198 1199 disabled = (state == VGA_SWITCHEROO_OFF); 1200 if (chip->disabled == disabled) 1201 return; 1202 1203 if (!hda->probe_continued) { 1204 chip->disabled = disabled; 1205 if (!disabled) { 1206 dev_info(chip->card->dev, 1207 "Start delayed initialization\n"); 1208 if (azx_probe_continue(chip) < 0) 1209 dev_err(chip->card->dev, "initialization error\n"); 1210 } 1211 } else { 1212 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1213 disabled ? "Disabling" : "Enabling"); 1214 if (disabled) { 1215 list_for_each_codec(codec, &chip->bus) { 1216 pm_runtime_suspend(hda_codec_dev(codec)); 1217 pm_runtime_disable(hda_codec_dev(codec)); 1218 } 1219 pm_runtime_suspend(card->dev); 1220 pm_runtime_disable(card->dev); 1221 /* when we get suspended by vga_switcheroo we end up in D3cold, 1222 * however we have no ACPI handle, so pci/acpi can't put us there, 1223 * put ourselves there */ 1224 pci->current_state = PCI_D3cold; 1225 chip->disabled = true; 1226 if (snd_hda_lock_devices(&chip->bus)) 1227 dev_warn(chip->card->dev, 1228 "Cannot lock devices!\n"); 1229 } else { 1230 snd_hda_unlock_devices(&chip->bus); 1231 chip->disabled = false; 1232 pm_runtime_enable(card->dev); 1233 list_for_each_codec(codec, &chip->bus) { 1234 pm_runtime_enable(hda_codec_dev(codec)); 1235 pm_runtime_resume(hda_codec_dev(codec)); 1236 } 1237 } 1238 } 1239 } 1240 1241 static bool azx_vs_can_switch(struct pci_dev *pci) 1242 { 1243 struct snd_card *card = pci_get_drvdata(pci); 1244 struct azx *chip = card->private_data; 1245 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1246 1247 wait_for_completion(&hda->probe_wait); 1248 if (hda->init_failed) 1249 return false; 1250 if (chip->disabled || !hda->probe_continued) 1251 return true; 1252 if (snd_hda_lock_devices(&chip->bus)) 1253 return false; 1254 snd_hda_unlock_devices(&chip->bus); 1255 return true; 1256 } 1257 1258 /* 1259 * The discrete GPU cannot power down unless the HDA controller runtime 1260 * suspends, so activate runtime PM on codecs even if power_save == 0. 1261 */ 1262 static void setup_vga_switcheroo_runtime_pm(struct azx *chip) 1263 { 1264 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1265 struct hda_codec *codec; 1266 1267 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) { 1268 list_for_each_codec(codec, &chip->bus) 1269 codec->auto_runtime_pm = 1; 1270 /* reset the power save setup */ 1271 if (chip->running) 1272 set_default_power_save(chip); 1273 } 1274 } 1275 1276 static void azx_vs_gpu_bound(struct pci_dev *pci, 1277 enum vga_switcheroo_client_id client_id) 1278 { 1279 struct snd_card *card = pci_get_drvdata(pci); 1280 struct azx *chip = card->private_data; 1281 1282 if (client_id == VGA_SWITCHEROO_DIS) 1283 chip->bus.keep_power = 0; 1284 setup_vga_switcheroo_runtime_pm(chip); 1285 } 1286 1287 static void init_vga_switcheroo(struct azx *chip) 1288 { 1289 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1290 struct pci_dev *p = get_bound_vga(chip->pci); 1291 struct pci_dev *parent; 1292 if (p) { 1293 dev_info(chip->card->dev, 1294 "Handle vga_switcheroo audio client\n"); 1295 hda->use_vga_switcheroo = 1; 1296 1297 /* cleared in either gpu_bound op or codec probe, or when its 1298 * upstream port has _PR3 (i.e. dGPU). 1299 */ 1300 parent = pci_upstream_bridge(p); 1301 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1; 1302 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; 1303 pci_dev_put(p); 1304 } 1305 } 1306 1307 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1308 .set_gpu_state = azx_vs_set_state, 1309 .can_switch = azx_vs_can_switch, 1310 .gpu_bound = azx_vs_gpu_bound, 1311 }; 1312 1313 static int register_vga_switcheroo(struct azx *chip) 1314 { 1315 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1316 struct pci_dev *p; 1317 int err; 1318 1319 if (!hda->use_vga_switcheroo) 1320 return 0; 1321 1322 p = get_bound_vga(chip->pci); 1323 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p); 1324 pci_dev_put(p); 1325 1326 if (err < 0) 1327 return err; 1328 hda->vga_switcheroo_registered = 1; 1329 1330 return 0; 1331 } 1332 #else 1333 #define init_vga_switcheroo(chip) /* NOP */ 1334 #define register_vga_switcheroo(chip) 0 1335 #define check_hdmi_disabled(pci) false 1336 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */ 1337 #endif /* SUPPORT_VGA_SWITCHER */ 1338 1339 /* 1340 * destructor 1341 */ 1342 static void azx_free(struct azx *chip) 1343 { 1344 struct pci_dev *pci = chip->pci; 1345 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1346 struct hdac_bus *bus = azx_bus(chip); 1347 1348 if (hda->freed) 1349 return; 1350 1351 if (azx_has_pm_runtime(chip) && chip->running) { 1352 pm_runtime_get_noresume(&pci->dev); 1353 pm_runtime_forbid(&pci->dev); 1354 pm_runtime_dont_use_autosuspend(&pci->dev); 1355 } 1356 1357 chip->running = 0; 1358 1359 azx_del_card_list(chip); 1360 1361 hda->init_failed = 1; /* to be sure */ 1362 complete_all(&hda->probe_wait); 1363 1364 if (use_vga_switcheroo(hda)) { 1365 if (chip->disabled && hda->probe_continued) 1366 snd_hda_unlock_devices(&chip->bus); 1367 if (hda->vga_switcheroo_registered) 1368 vga_switcheroo_unregister_client(chip->pci); 1369 } 1370 1371 if (bus->chip_init) { 1372 azx_clear_irq_pending(chip); 1373 azx_stop_all_streams(chip); 1374 azx_stop_chip(chip); 1375 } 1376 1377 if (bus->irq >= 0) 1378 free_irq(bus->irq, (void*)chip); 1379 1380 azx_free_stream_pages(chip); 1381 azx_free_streams(chip); 1382 snd_hdac_bus_exit(bus); 1383 1384 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1385 release_firmware(chip->fw); 1386 #endif 1387 display_power(chip, false); 1388 1389 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) 1390 snd_hdac_i915_exit(bus); 1391 1392 hda->freed = 1; 1393 } 1394 1395 static int azx_dev_disconnect(struct snd_device *device) 1396 { 1397 struct azx *chip = device->device_data; 1398 struct hdac_bus *bus = azx_bus(chip); 1399 1400 chip->bus.shutdown = 1; 1401 cancel_work_sync(&bus->unsol_work); 1402 1403 return 0; 1404 } 1405 1406 static int azx_dev_free(struct snd_device *device) 1407 { 1408 azx_free(device->device_data); 1409 return 0; 1410 } 1411 1412 #ifdef SUPPORT_VGA_SWITCHEROO 1413 #ifdef CONFIG_ACPI 1414 /* ATPX is in the integrated GPU's namespace */ 1415 static bool atpx_present(void) 1416 { 1417 struct pci_dev *pdev = NULL; 1418 acpi_handle dhandle, atpx_handle; 1419 acpi_status status; 1420 1421 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 1422 dhandle = ACPI_HANDLE(&pdev->dev); 1423 if (dhandle) { 1424 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1425 if (ACPI_SUCCESS(status)) { 1426 pci_dev_put(pdev); 1427 return true; 1428 } 1429 } 1430 } 1431 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 1432 dhandle = ACPI_HANDLE(&pdev->dev); 1433 if (dhandle) { 1434 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1435 if (ACPI_SUCCESS(status)) { 1436 pci_dev_put(pdev); 1437 return true; 1438 } 1439 } 1440 } 1441 return false; 1442 } 1443 #else 1444 static bool atpx_present(void) 1445 { 1446 return false; 1447 } 1448 #endif 1449 1450 /* 1451 * Check of disabled HDMI controller by vga_switcheroo 1452 */ 1453 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1454 { 1455 struct pci_dev *p; 1456 1457 /* check only discrete GPU */ 1458 switch (pci->vendor) { 1459 case PCI_VENDOR_ID_ATI: 1460 case PCI_VENDOR_ID_AMD: 1461 if (pci->devfn == 1) { 1462 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1463 pci->bus->number, 0); 1464 if (p) { 1465 /* ATPX is in the integrated GPU's ACPI namespace 1466 * rather than the dGPU's namespace. However, 1467 * the dGPU is the one who is involved in 1468 * vgaswitcheroo. 1469 */ 1470 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) && 1471 (atpx_present() || apple_gmux_detect(NULL, NULL))) 1472 return p; 1473 pci_dev_put(p); 1474 } 1475 } 1476 break; 1477 case PCI_VENDOR_ID_NVIDIA: 1478 if (pci->devfn == 1) { 1479 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1480 pci->bus->number, 0); 1481 if (p) { 1482 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) 1483 return p; 1484 pci_dev_put(p); 1485 } 1486 } 1487 break; 1488 } 1489 return NULL; 1490 } 1491 1492 static bool check_hdmi_disabled(struct pci_dev *pci) 1493 { 1494 bool vga_inactive = false; 1495 struct pci_dev *p = get_bound_vga(pci); 1496 1497 if (p) { 1498 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1499 vga_inactive = true; 1500 pci_dev_put(p); 1501 } 1502 return vga_inactive; 1503 } 1504 #endif /* SUPPORT_VGA_SWITCHEROO */ 1505 1506 /* 1507 * allow/deny-listing for position_fix 1508 */ 1509 static const struct snd_pci_quirk position_fix_list[] = { 1510 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1511 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1512 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1513 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1514 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1515 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1516 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1517 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1518 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1519 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1520 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1521 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1522 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1523 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1524 {} 1525 }; 1526 1527 static int check_position_fix(struct azx *chip, int fix) 1528 { 1529 const struct snd_pci_quirk *q; 1530 1531 switch (fix) { 1532 case POS_FIX_AUTO: 1533 case POS_FIX_LPIB: 1534 case POS_FIX_POSBUF: 1535 case POS_FIX_VIACOMBO: 1536 case POS_FIX_COMBO: 1537 case POS_FIX_SKL: 1538 case POS_FIX_FIFO: 1539 return fix; 1540 } 1541 1542 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1543 if (q) { 1544 dev_info(chip->card->dev, 1545 "position_fix set to %d for device %04x:%04x\n", 1546 q->value, q->subvendor, q->subdevice); 1547 return q->value; 1548 } 1549 1550 /* Check VIA/ATI HD Audio Controller exist */ 1551 if (chip->driver_type == AZX_DRIVER_VIA) { 1552 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1553 return POS_FIX_VIACOMBO; 1554 } 1555 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) { 1556 dev_dbg(chip->card->dev, "Using FIFO position fix\n"); 1557 return POS_FIX_FIFO; 1558 } 1559 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1560 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1561 return POS_FIX_LPIB; 1562 } 1563 if (chip->driver_type == AZX_DRIVER_SKL) { 1564 dev_dbg(chip->card->dev, "Using SKL position fix\n"); 1565 return POS_FIX_SKL; 1566 } 1567 return POS_FIX_AUTO; 1568 } 1569 1570 static void assign_position_fix(struct azx *chip, int fix) 1571 { 1572 static const azx_get_pos_callback_t callbacks[] = { 1573 [POS_FIX_AUTO] = NULL, 1574 [POS_FIX_LPIB] = azx_get_pos_lpib, 1575 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1576 [POS_FIX_VIACOMBO] = azx_via_get_position, 1577 [POS_FIX_COMBO] = azx_get_pos_lpib, 1578 [POS_FIX_SKL] = azx_get_pos_posbuf, 1579 [POS_FIX_FIFO] = azx_get_pos_fifo, 1580 }; 1581 1582 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1583 1584 /* combo mode uses LPIB only for playback */ 1585 if (fix == POS_FIX_COMBO) 1586 chip->get_position[1] = NULL; 1587 1588 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) && 1589 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1590 chip->get_delay[0] = chip->get_delay[1] = 1591 azx_get_delay_from_lpib; 1592 } 1593 1594 if (fix == POS_FIX_FIFO) 1595 chip->get_delay[0] = chip->get_delay[1] = 1596 azx_get_delay_from_fifo; 1597 } 1598 1599 /* 1600 * deny-lists for probe_mask 1601 */ 1602 static const struct snd_pci_quirk probe_mask_list[] = { 1603 /* Thinkpad often breaks the controller communication when accessing 1604 * to the non-working (or non-existing) modem codec slot. 1605 */ 1606 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1607 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1608 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1609 /* broken BIOS */ 1610 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1611 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1612 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1613 /* forced codec slots */ 1614 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1615 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1616 SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105), 1617 /* WinFast VP200 H (Teradici) user reported broken communication */ 1618 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1619 {} 1620 }; 1621 1622 #define AZX_FORCE_CODEC_MASK 0x100 1623 1624 static void check_probe_mask(struct azx *chip, int dev) 1625 { 1626 const struct snd_pci_quirk *q; 1627 1628 chip->codec_probe_mask = probe_mask[dev]; 1629 if (chip->codec_probe_mask == -1) { 1630 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1631 if (q) { 1632 dev_info(chip->card->dev, 1633 "probe_mask set to 0x%x for device %04x:%04x\n", 1634 q->value, q->subvendor, q->subdevice); 1635 chip->codec_probe_mask = q->value; 1636 } 1637 } 1638 1639 /* check forced option */ 1640 if (chip->codec_probe_mask != -1 && 1641 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1642 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1643 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1644 (int)azx_bus(chip)->codec_mask); 1645 } 1646 } 1647 1648 /* 1649 * allow/deny-list for enable_msi 1650 */ 1651 static const struct snd_pci_quirk msi_deny_list[] = { 1652 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1653 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1654 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1655 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1656 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1657 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1658 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1659 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1660 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1661 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1662 {} 1663 }; 1664 1665 static void check_msi(struct azx *chip) 1666 { 1667 const struct snd_pci_quirk *q; 1668 1669 if (enable_msi >= 0) { 1670 chip->msi = !!enable_msi; 1671 return; 1672 } 1673 chip->msi = 1; /* enable MSI as default */ 1674 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list); 1675 if (q) { 1676 dev_info(chip->card->dev, 1677 "msi for device %04x:%04x set to %d\n", 1678 q->subvendor, q->subdevice, q->value); 1679 chip->msi = q->value; 1680 return; 1681 } 1682 1683 /* NVidia chipsets seem to cause troubles with MSI */ 1684 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1685 dev_info(chip->card->dev, "Disabling MSI\n"); 1686 chip->msi = 0; 1687 } 1688 } 1689 1690 /* check the snoop mode availability */ 1691 static void azx_check_snoop_available(struct azx *chip) 1692 { 1693 int snoop = hda_snoop; 1694 1695 if (snoop >= 0) { 1696 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1697 snoop ? "snoop" : "non-snoop"); 1698 chip->snoop = snoop; 1699 chip->uc_buffer = !snoop; 1700 return; 1701 } 1702 1703 snoop = true; 1704 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1705 chip->driver_type == AZX_DRIVER_VIA) { 1706 /* force to non-snoop mode for a new VIA controller 1707 * when BIOS is set 1708 */ 1709 u8 val; 1710 pci_read_config_byte(chip->pci, 0x42, &val); 1711 if (!(val & 0x80) && (chip->pci->revision == 0x30 || 1712 chip->pci->revision == 0x20)) 1713 snoop = false; 1714 } 1715 1716 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1717 snoop = false; 1718 1719 chip->snoop = snoop; 1720 if (!snoop) { 1721 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1722 /* C-Media requires non-cached pages only for CORB/RIRB */ 1723 if (chip->driver_type != AZX_DRIVER_CMEDIA) 1724 chip->uc_buffer = true; 1725 } 1726 } 1727 1728 static void azx_probe_work(struct work_struct *work) 1729 { 1730 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work); 1731 azx_probe_continue(&hda->chip); 1732 } 1733 1734 static int default_bdl_pos_adj(struct azx *chip) 1735 { 1736 /* some exceptions: Atoms seem problematic with value 1 */ 1737 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { 1738 switch (chip->pci->device) { 1739 case 0x0f04: /* Baytrail */ 1740 case 0x2284: /* Braswell */ 1741 return 32; 1742 } 1743 } 1744 1745 switch (chip->driver_type) { 1746 case AZX_DRIVER_ICH: 1747 case AZX_DRIVER_PCH: 1748 return 1; 1749 default: 1750 return 32; 1751 } 1752 } 1753 1754 /* 1755 * constructor 1756 */ 1757 static const struct hda_controller_ops pci_hda_ops; 1758 1759 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1760 int dev, unsigned int driver_caps, 1761 struct azx **rchip) 1762 { 1763 static const struct snd_device_ops ops = { 1764 .dev_disconnect = azx_dev_disconnect, 1765 .dev_free = azx_dev_free, 1766 }; 1767 struct hda_intel *hda; 1768 struct azx *chip; 1769 int err; 1770 1771 *rchip = NULL; 1772 1773 err = pcim_enable_device(pci); 1774 if (err < 0) 1775 return err; 1776 1777 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL); 1778 if (!hda) 1779 return -ENOMEM; 1780 1781 chip = &hda->chip; 1782 mutex_init(&chip->open_mutex); 1783 chip->card = card; 1784 chip->pci = pci; 1785 chip->ops = &pci_hda_ops; 1786 chip->driver_caps = driver_caps; 1787 chip->driver_type = driver_caps & 0xff; 1788 check_msi(chip); 1789 chip->dev_index = dev; 1790 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000) 1791 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]); 1792 INIT_LIST_HEAD(&chip->pcm_list); 1793 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1794 INIT_LIST_HEAD(&hda->list); 1795 init_vga_switcheroo(chip); 1796 init_completion(&hda->probe_wait); 1797 1798 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1799 1800 if (single_cmd < 0) /* allow fallback to single_cmd at errors */ 1801 chip->fallback_to_single_cmd = 1; 1802 else /* explicitly set to single_cmd or not */ 1803 chip->single_cmd = single_cmd; 1804 1805 azx_check_snoop_available(chip); 1806 1807 if (bdl_pos_adj[dev] < 0) 1808 chip->bdl_pos_adj = default_bdl_pos_adj(chip); 1809 else 1810 chip->bdl_pos_adj = bdl_pos_adj[dev]; 1811 1812 err = azx_bus_init(chip, model[dev]); 1813 if (err < 0) 1814 return err; 1815 1816 /* use the non-cached pages in non-snoop mode */ 1817 if (!azx_snoop(chip)) 1818 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC_SG; 1819 1820 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 1821 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); 1822 chip->bus.core.needs_damn_long_delay = 1; 1823 } 1824 1825 check_probe_mask(chip, dev); 1826 1827 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1828 if (err < 0) { 1829 dev_err(card->dev, "Error creating device [card]!\n"); 1830 azx_free(chip); 1831 return err; 1832 } 1833 1834 /* continue probing in work context as may trigger request module */ 1835 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work); 1836 1837 *rchip = chip; 1838 1839 return 0; 1840 } 1841 1842 static int azx_first_init(struct azx *chip) 1843 { 1844 int dev = chip->dev_index; 1845 struct pci_dev *pci = chip->pci; 1846 struct snd_card *card = chip->card; 1847 struct hdac_bus *bus = azx_bus(chip); 1848 int err; 1849 unsigned short gcap; 1850 unsigned int dma_bits = 64; 1851 1852 #if BITS_PER_LONG != 64 1853 /* Fix up base address on ULI M5461 */ 1854 if (chip->driver_type == AZX_DRIVER_ULI) { 1855 u16 tmp3; 1856 pci_read_config_word(pci, 0x40, &tmp3); 1857 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1858 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1859 } 1860 #endif 1861 1862 err = pcim_iomap_regions(pci, 1 << 0, "ICH HD audio"); 1863 if (err < 0) 1864 return err; 1865 1866 bus->addr = pci_resource_start(pci, 0); 1867 bus->remap_addr = pcim_iomap_table(pci)[0]; 1868 1869 if (chip->driver_type == AZX_DRIVER_SKL) 1870 snd_hdac_bus_parse_capabilities(bus); 1871 1872 /* 1873 * Some Intel CPUs has always running timer (ART) feature and 1874 * controller may have Global time sync reporting capability, so 1875 * check both of these before declaring synchronized time reporting 1876 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 1877 */ 1878 chip->gts_present = false; 1879 1880 #ifdef CONFIG_X86 1881 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART)) 1882 chip->gts_present = true; 1883 #endif 1884 1885 if (chip->msi) { 1886 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1887 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1888 pci->no_64bit_msi = true; 1889 } 1890 if (pci_enable_msi(pci) < 0) 1891 chip->msi = 0; 1892 } 1893 1894 pci_set_master(pci); 1895 1896 gcap = azx_readw(chip, GCAP); 1897 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1898 1899 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1900 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1901 dma_bits = 40; 1902 1903 /* disable SB600 64bit support for safety */ 1904 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1905 struct pci_dev *p_smbus; 1906 dma_bits = 40; 1907 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1908 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1909 NULL); 1910 if (p_smbus) { 1911 if (p_smbus->revision < 0x30) 1912 gcap &= ~AZX_GCAP_64OK; 1913 pci_dev_put(p_smbus); 1914 } 1915 } 1916 1917 /* NVidia hardware normally only supports up to 40 bits of DMA */ 1918 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) 1919 dma_bits = 40; 1920 1921 /* disable 64bit DMA address on some devices */ 1922 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1923 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1924 gcap &= ~AZX_GCAP_64OK; 1925 } 1926 1927 /* disable buffer size rounding to 128-byte multiples if supported */ 1928 if (align_buffer_size >= 0) 1929 chip->align_buffer_size = !!align_buffer_size; 1930 else { 1931 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1932 chip->align_buffer_size = 0; 1933 else 1934 chip->align_buffer_size = 1; 1935 } 1936 1937 /* allow 64bit DMA address if supported by H/W */ 1938 if (!(gcap & AZX_GCAP_64OK)) 1939 dma_bits = 32; 1940 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits))) 1941 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); 1942 dma_set_max_seg_size(&pci->dev, UINT_MAX); 1943 1944 /* read number of streams from GCAP register instead of using 1945 * hardcoded value 1946 */ 1947 chip->capture_streams = (gcap >> 8) & 0x0f; 1948 chip->playback_streams = (gcap >> 12) & 0x0f; 1949 if (!chip->playback_streams && !chip->capture_streams) { 1950 /* gcap didn't give any info, switching to old method */ 1951 1952 switch (chip->driver_type) { 1953 case AZX_DRIVER_ULI: 1954 chip->playback_streams = ULI_NUM_PLAYBACK; 1955 chip->capture_streams = ULI_NUM_CAPTURE; 1956 break; 1957 case AZX_DRIVER_ATIHDMI: 1958 case AZX_DRIVER_ATIHDMI_NS: 1959 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1960 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1961 break; 1962 case AZX_DRIVER_GENERIC: 1963 default: 1964 chip->playback_streams = ICH6_NUM_PLAYBACK; 1965 chip->capture_streams = ICH6_NUM_CAPTURE; 1966 break; 1967 } 1968 } 1969 chip->capture_index_offset = 0; 1970 chip->playback_index_offset = chip->capture_streams; 1971 chip->num_streams = chip->playback_streams + chip->capture_streams; 1972 1973 /* sanity check for the SDxCTL.STRM field overflow */ 1974 if (chip->num_streams > 15 && 1975 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) { 1976 dev_warn(chip->card->dev, "number of I/O streams is %d, " 1977 "forcing separate stream tags", chip->num_streams); 1978 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG; 1979 } 1980 1981 /* initialize streams */ 1982 err = azx_init_streams(chip); 1983 if (err < 0) 1984 return err; 1985 1986 err = azx_alloc_stream_pages(chip); 1987 if (err < 0) 1988 return err; 1989 1990 /* initialize chip */ 1991 azx_init_pci(chip); 1992 1993 snd_hdac_i915_set_bclk(bus); 1994 1995 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 1996 1997 /* codec detection */ 1998 if (!azx_bus(chip)->codec_mask) { 1999 dev_err(card->dev, "no codecs found!\n"); 2000 /* keep running the rest for the runtime PM */ 2001 } 2002 2003 if (azx_acquire_irq(chip, 0) < 0) 2004 return -EBUSY; 2005 2006 strcpy(card->driver, "HDA-Intel"); 2007 strscpy(card->shortname, driver_short_names[chip->driver_type], 2008 sizeof(card->shortname)); 2009 snprintf(card->longname, sizeof(card->longname), 2010 "%s at 0x%lx irq %i", 2011 card->shortname, bus->addr, bus->irq); 2012 2013 return 0; 2014 } 2015 2016 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2017 /* callback from request_firmware_nowait() */ 2018 static void azx_firmware_cb(const struct firmware *fw, void *context) 2019 { 2020 struct snd_card *card = context; 2021 struct azx *chip = card->private_data; 2022 2023 if (fw) 2024 chip->fw = fw; 2025 else 2026 dev_err(card->dev, "Cannot load firmware, continue without patching\n"); 2027 if (!chip->disabled) { 2028 /* continue probing */ 2029 azx_probe_continue(chip); 2030 } 2031 } 2032 #endif 2033 2034 static int disable_msi_reset_irq(struct azx *chip) 2035 { 2036 struct hdac_bus *bus = azx_bus(chip); 2037 int err; 2038 2039 free_irq(bus->irq, chip); 2040 bus->irq = -1; 2041 chip->card->sync_irq = -1; 2042 pci_disable_msi(chip->pci); 2043 chip->msi = 0; 2044 err = azx_acquire_irq(chip, 1); 2045 if (err < 0) 2046 return err; 2047 2048 return 0; 2049 } 2050 2051 /* Denylist for skipping the whole probe: 2052 * some HD-audio PCI entries are exposed without any codecs, and such devices 2053 * should be ignored from the beginning. 2054 */ 2055 static const struct pci_device_id driver_denylist[] = { 2056 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */ 2057 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */ 2058 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */ 2059 {} 2060 }; 2061 2062 static const struct hda_controller_ops pci_hda_ops = { 2063 .disable_msi_reset_irq = disable_msi_reset_irq, 2064 .position_check = azx_position_check, 2065 }; 2066 2067 static DECLARE_BITMAP(probed_devs, SNDRV_CARDS); 2068 2069 static int azx_probe(struct pci_dev *pci, 2070 const struct pci_device_id *pci_id) 2071 { 2072 struct snd_card *card; 2073 struct hda_intel *hda; 2074 struct azx *chip; 2075 bool schedule_probe; 2076 int dev; 2077 int err; 2078 2079 if (pci_match_id(driver_denylist, pci)) { 2080 dev_info(&pci->dev, "Skipping the device on the denylist\n"); 2081 return -ENODEV; 2082 } 2083 2084 dev = find_first_zero_bit(probed_devs, SNDRV_CARDS); 2085 if (dev >= SNDRV_CARDS) 2086 return -ENODEV; 2087 if (!enable[dev]) { 2088 set_bit(dev, probed_devs); 2089 return -ENOENT; 2090 } 2091 2092 /* 2093 * stop probe if another Intel's DSP driver should be activated 2094 */ 2095 if (dmic_detect) { 2096 err = snd_intel_dsp_driver_probe(pci); 2097 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) { 2098 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n"); 2099 return -ENODEV; 2100 } 2101 } else { 2102 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n"); 2103 } 2104 2105 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2106 0, &card); 2107 if (err < 0) { 2108 dev_err(&pci->dev, "Error creating card!\n"); 2109 return err; 2110 } 2111 2112 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2113 if (err < 0) 2114 goto out_free; 2115 card->private_data = chip; 2116 hda = container_of(chip, struct hda_intel, chip); 2117 2118 pci_set_drvdata(pci, card); 2119 2120 err = register_vga_switcheroo(chip); 2121 if (err < 0) { 2122 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 2123 goto out_free; 2124 } 2125 2126 if (check_hdmi_disabled(pci)) { 2127 dev_info(card->dev, "VGA controller is disabled\n"); 2128 dev_info(card->dev, "Delaying initialization\n"); 2129 chip->disabled = true; 2130 } 2131 2132 schedule_probe = !chip->disabled; 2133 2134 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2135 if (patch[dev] && *patch[dev]) { 2136 dev_info(card->dev, "Applying patch firmware '%s'\n", 2137 patch[dev]); 2138 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 2139 &pci->dev, GFP_KERNEL, card, 2140 azx_firmware_cb); 2141 if (err < 0) 2142 goto out_free; 2143 schedule_probe = false; /* continued in azx_firmware_cb() */ 2144 } 2145 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 2146 2147 #ifndef CONFIG_SND_HDA_I915 2148 if (CONTROLLER_IN_GPU(pci)) 2149 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); 2150 #endif 2151 2152 if (schedule_probe) 2153 schedule_delayed_work(&hda->probe_work, 0); 2154 2155 set_bit(dev, probed_devs); 2156 if (chip->disabled) 2157 complete_all(&hda->probe_wait); 2158 return 0; 2159 2160 out_free: 2161 snd_card_free(card); 2162 return err; 2163 } 2164 2165 #ifdef CONFIG_PM 2166 /* On some boards setting power_save to a non 0 value leads to clicking / 2167 * popping sounds when ever we enter/leave powersaving mode. Ideally we would 2168 * figure out how to avoid these sounds, but that is not always feasible. 2169 * So we keep a list of devices where we disable powersaving as its known 2170 * to causes problems on these devices. 2171 */ 2172 static const struct snd_pci_quirk power_save_denylist[] = { 2173 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2174 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0), 2175 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2176 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0), 2177 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2178 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0), 2179 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2180 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0), 2181 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2182 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0), 2183 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2184 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ 2185 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0), 2186 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2187 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0), 2188 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */ 2189 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0), 2190 /* https://bugs.launchpad.net/bugs/1821663 */ 2191 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0), 2192 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */ 2193 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), 2194 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ 2195 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), 2196 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ 2197 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), 2198 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ 2199 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0), 2200 /* https://bugs.launchpad.net/bugs/1821663 */ 2201 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0), 2202 {} 2203 }; 2204 #endif /* CONFIG_PM */ 2205 2206 static void set_default_power_save(struct azx *chip) 2207 { 2208 int val = power_save; 2209 2210 #ifdef CONFIG_PM 2211 if (pm_blacklist) { 2212 const struct snd_pci_quirk *q; 2213 2214 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist); 2215 if (q && val) { 2216 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n", 2217 q->subvendor, q->subdevice); 2218 val = 0; 2219 } 2220 } 2221 #endif /* CONFIG_PM */ 2222 snd_hda_set_power_save(&chip->bus, val * 1000); 2223 } 2224 2225 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 2226 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 2227 [AZX_DRIVER_NVIDIA] = 8, 2228 [AZX_DRIVER_TERA] = 1, 2229 }; 2230 2231 static int azx_probe_continue(struct azx *chip) 2232 { 2233 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2234 struct hdac_bus *bus = azx_bus(chip); 2235 struct pci_dev *pci = chip->pci; 2236 int dev = chip->dev_index; 2237 int err; 2238 2239 if (chip->disabled || hda->init_failed) 2240 return -EIO; 2241 if (hda->probe_retry) 2242 goto probe_retry; 2243 2244 to_hda_bus(bus)->bus_probing = 1; 2245 hda->probe_continued = 1; 2246 2247 /* bind with i915 if needed */ 2248 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) { 2249 err = snd_hdac_i915_init(bus); 2250 if (err < 0) { 2251 /* if the controller is bound only with HDMI/DP 2252 * (for HSW and BDW), we need to abort the probe; 2253 * for other chips, still continue probing as other 2254 * codecs can be on the same link. 2255 */ 2256 if (CONTROLLER_IN_GPU(pci)) { 2257 dev_err(chip->card->dev, 2258 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); 2259 goto out_free; 2260 } else { 2261 /* don't bother any longer */ 2262 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT; 2263 } 2264 } 2265 2266 /* HSW/BDW controllers need this power */ 2267 if (CONTROLLER_IN_GPU(pci)) 2268 hda->need_i915_power = true; 2269 } 2270 2271 /* Request display power well for the HDA controller or codec. For 2272 * Haswell/Broadwell, both the display HDA controller and codec need 2273 * this power. For other platforms, like Baytrail/Braswell, only the 2274 * display codec needs the power and it can be released after probe. 2275 */ 2276 display_power(chip, true); 2277 2278 err = azx_first_init(chip); 2279 if (err < 0) 2280 goto out_free; 2281 2282 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2283 chip->beep_mode = beep_mode[dev]; 2284 #endif 2285 2286 chip->ctl_dev_id = ctl_dev_id; 2287 2288 /* create codec instances */ 2289 if (bus->codec_mask) { 2290 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2291 if (err < 0) 2292 goto out_free; 2293 } 2294 2295 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2296 if (chip->fw) { 2297 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2298 chip->fw->data); 2299 if (err < 0) 2300 goto out_free; 2301 #ifndef CONFIG_PM 2302 release_firmware(chip->fw); /* no longer needed */ 2303 chip->fw = NULL; 2304 #endif 2305 } 2306 #endif 2307 2308 probe_retry: 2309 if (bus->codec_mask && !(probe_only[dev] & 1)) { 2310 err = azx_codec_configure(chip); 2311 if (err) { 2312 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) && 2313 ++hda->probe_retry < 60) { 2314 schedule_delayed_work(&hda->probe_work, 2315 msecs_to_jiffies(1000)); 2316 return 0; /* keep things up */ 2317 } 2318 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n"); 2319 goto out_free; 2320 } 2321 } 2322 2323 err = snd_card_register(chip->card); 2324 if (err < 0) 2325 goto out_free; 2326 2327 setup_vga_switcheroo_runtime_pm(chip); 2328 2329 chip->running = 1; 2330 azx_add_card_list(chip); 2331 2332 set_default_power_save(chip); 2333 2334 if (azx_has_pm_runtime(chip)) { 2335 pm_runtime_use_autosuspend(&pci->dev); 2336 pm_runtime_allow(&pci->dev); 2337 pm_runtime_put_autosuspend(&pci->dev); 2338 } 2339 2340 out_free: 2341 if (err < 0) { 2342 pci_set_drvdata(pci, NULL); 2343 snd_card_free(chip->card); 2344 return err; 2345 } 2346 2347 if (!hda->need_i915_power) 2348 display_power(chip, false); 2349 complete_all(&hda->probe_wait); 2350 to_hda_bus(bus)->bus_probing = 0; 2351 hda->probe_retry = 0; 2352 return 0; 2353 } 2354 2355 static void azx_remove(struct pci_dev *pci) 2356 { 2357 struct snd_card *card = pci_get_drvdata(pci); 2358 struct azx *chip; 2359 struct hda_intel *hda; 2360 2361 if (card) { 2362 /* cancel the pending probing work */ 2363 chip = card->private_data; 2364 hda = container_of(chip, struct hda_intel, chip); 2365 /* FIXME: below is an ugly workaround. 2366 * Both device_release_driver() and driver_probe_device() 2367 * take *both* the device's and its parent's lock before 2368 * calling the remove() and probe() callbacks. The codec 2369 * probe takes the locks of both the codec itself and its 2370 * parent, i.e. the PCI controller dev. Meanwhile, when 2371 * the PCI controller is unbound, it takes its lock, too 2372 * ==> ouch, a deadlock! 2373 * As a workaround, we unlock temporarily here the controller 2374 * device during cancel_work_sync() call. 2375 */ 2376 device_unlock(&pci->dev); 2377 cancel_delayed_work_sync(&hda->probe_work); 2378 device_lock(&pci->dev); 2379 2380 clear_bit(chip->dev_index, probed_devs); 2381 pci_set_drvdata(pci, NULL); 2382 snd_card_free(card); 2383 } 2384 } 2385 2386 static void azx_shutdown(struct pci_dev *pci) 2387 { 2388 struct snd_card *card = pci_get_drvdata(pci); 2389 struct azx *chip; 2390 2391 if (!card) 2392 return; 2393 chip = card->private_data; 2394 if (chip && chip->running) 2395 __azx_shutdown_chip(chip, true); 2396 } 2397 2398 /* PCI IDs */ 2399 static const struct pci_device_id azx_ids[] = { 2400 /* CPT */ 2401 { PCI_DEVICE(0x8086, 0x1c20), 2402 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2403 /* PBG */ 2404 { PCI_DEVICE(0x8086, 0x1d20), 2405 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2406 /* Panther Point */ 2407 { PCI_DEVICE(0x8086, 0x1e20), 2408 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2409 /* Lynx Point */ 2410 { PCI_DEVICE(0x8086, 0x8c20), 2411 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2412 /* 9 Series */ 2413 { PCI_DEVICE(0x8086, 0x8ca0), 2414 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2415 /* Wellsburg */ 2416 { PCI_DEVICE(0x8086, 0x8d20), 2417 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2418 { PCI_DEVICE(0x8086, 0x8d21), 2419 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2420 /* Lewisburg */ 2421 { PCI_DEVICE(0x8086, 0xa1f0), 2422 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2423 { PCI_DEVICE(0x8086, 0xa270), 2424 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2425 /* Lynx Point-LP */ 2426 { PCI_DEVICE(0x8086, 0x9c20), 2427 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2428 /* Lynx Point-LP */ 2429 { PCI_DEVICE(0x8086, 0x9c21), 2430 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2431 /* Wildcat Point-LP */ 2432 { PCI_DEVICE(0x8086, 0x9ca0), 2433 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2434 /* Sunrise Point */ 2435 { PCI_DEVICE(0x8086, 0xa170), 2436 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2437 /* Sunrise Point-LP */ 2438 { PCI_DEVICE(0x8086, 0x9d70), 2439 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2440 /* Kabylake */ 2441 { PCI_DEVICE(0x8086, 0xa171), 2442 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2443 /* Kabylake-LP */ 2444 { PCI_DEVICE(0x8086, 0x9d71), 2445 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2446 /* Kabylake-H */ 2447 { PCI_DEVICE(0x8086, 0xa2f0), 2448 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2449 /* Coffelake */ 2450 { PCI_DEVICE(0x8086, 0xa348), 2451 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2452 /* Cannonlake */ 2453 { PCI_DEVICE(0x8086, 0x9dc8), 2454 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2455 /* CometLake-LP */ 2456 { PCI_DEVICE(0x8086, 0x02C8), 2457 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2458 /* CometLake-H */ 2459 { PCI_DEVICE(0x8086, 0x06C8), 2460 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2461 { PCI_DEVICE(0x8086, 0xf1c8), 2462 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2463 /* CometLake-S */ 2464 { PCI_DEVICE(0x8086, 0xa3f0), 2465 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2466 /* CometLake-R */ 2467 { PCI_DEVICE(0x8086, 0xf0c8), 2468 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2469 /* Icelake */ 2470 { PCI_DEVICE(0x8086, 0x34c8), 2471 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2472 /* Icelake-H */ 2473 { PCI_DEVICE(0x8086, 0x3dc8), 2474 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2475 /* Jasperlake */ 2476 { PCI_DEVICE(0x8086, 0x38c8), 2477 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2478 { PCI_DEVICE(0x8086, 0x4dc8), 2479 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2480 /* Tigerlake */ 2481 { PCI_DEVICE(0x8086, 0xa0c8), 2482 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2483 /* Tigerlake-H */ 2484 { PCI_DEVICE(0x8086, 0x43c8), 2485 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2486 /* DG1 */ 2487 { PCI_DEVICE(0x8086, 0x490d), 2488 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2489 /* DG2 */ 2490 { PCI_DEVICE(0x8086, 0x4f90), 2491 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2492 { PCI_DEVICE(0x8086, 0x4f91), 2493 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2494 { PCI_DEVICE(0x8086, 0x4f92), 2495 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2496 /* Alderlake-S */ 2497 { PCI_DEVICE(0x8086, 0x7ad0), 2498 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2499 /* Alderlake-P */ 2500 { PCI_DEVICE(0x8086, 0x51c8), 2501 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2502 { PCI_DEVICE(0x8086, 0x51c9), 2503 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2504 { PCI_DEVICE(0x8086, 0x51cd), 2505 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2506 /* Alderlake-M */ 2507 { PCI_DEVICE(0x8086, 0x51cc), 2508 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2509 /* Alderlake-N */ 2510 { PCI_DEVICE(0x8086, 0x54c8), 2511 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2512 /* Elkhart Lake */ 2513 { PCI_DEVICE(0x8086, 0x4b55), 2514 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2515 { PCI_DEVICE(0x8086, 0x4b58), 2516 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2517 /* Raptor Lake */ 2518 { PCI_DEVICE(0x8086, 0x7a50), 2519 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2520 { PCI_DEVICE(0x8086, 0x51ca), 2521 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2522 { PCI_DEVICE(0x8086, 0x51cb), 2523 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2524 { PCI_DEVICE(0x8086, 0x51ce), 2525 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2526 { PCI_DEVICE(0x8086, 0x51cf), 2527 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2528 /* Meteorlake-P */ 2529 { PCI_DEVICE(0x8086, 0x7e28), 2530 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2531 /* Broxton-P(Apollolake) */ 2532 { PCI_DEVICE(0x8086, 0x5a98), 2533 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2534 /* Broxton-T */ 2535 { PCI_DEVICE(0x8086, 0x1a98), 2536 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2537 /* Gemini-Lake */ 2538 { PCI_DEVICE(0x8086, 0x3198), 2539 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2540 /* Haswell */ 2541 { PCI_DEVICE(0x8086, 0x0a0c), 2542 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2543 { PCI_DEVICE(0x8086, 0x0c0c), 2544 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2545 { PCI_DEVICE(0x8086, 0x0d0c), 2546 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2547 /* Broadwell */ 2548 { PCI_DEVICE(0x8086, 0x160c), 2549 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 2550 /* 5 Series/3400 */ 2551 { PCI_DEVICE(0x8086, 0x3b56), 2552 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2553 { PCI_DEVICE(0x8086, 0x3b57), 2554 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2555 /* Poulsbo */ 2556 { PCI_DEVICE(0x8086, 0x811b), 2557 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE | 2558 AZX_DCAPS_POSFIX_LPIB }, 2559 /* Oaktrail */ 2560 { PCI_DEVICE(0x8086, 0x080a), 2561 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2562 /* BayTrail */ 2563 { PCI_DEVICE(0x8086, 0x0f04), 2564 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL }, 2565 /* Braswell */ 2566 { PCI_DEVICE(0x8086, 0x2284), 2567 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL }, 2568 /* ICH6 */ 2569 { PCI_DEVICE(0x8086, 0x2668), 2570 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2571 /* ICH7 */ 2572 { PCI_DEVICE(0x8086, 0x27d8), 2573 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2574 /* ESB2 */ 2575 { PCI_DEVICE(0x8086, 0x269a), 2576 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2577 /* ICH8 */ 2578 { PCI_DEVICE(0x8086, 0x284b), 2579 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2580 /* ICH9 */ 2581 { PCI_DEVICE(0x8086, 0x293e), 2582 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2583 /* ICH9 */ 2584 { PCI_DEVICE(0x8086, 0x293f), 2585 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2586 /* ICH10 */ 2587 { PCI_DEVICE(0x8086, 0x3a3e), 2588 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2589 /* ICH10 */ 2590 { PCI_DEVICE(0x8086, 0x3a6e), 2591 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2592 /* Generic Intel */ 2593 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2594 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2595 .class_mask = 0xffffff, 2596 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2597 /* ATI SB 450/600/700/800/900 */ 2598 { PCI_DEVICE(0x1002, 0x437b), 2599 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2600 { PCI_DEVICE(0x1002, 0x4383), 2601 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2602 /* AMD Hudson */ 2603 { PCI_DEVICE(0x1022, 0x780d), 2604 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2605 /* AMD, X370 & co */ 2606 { PCI_DEVICE(0x1022, 0x1457), 2607 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2608 /* AMD, X570 & co */ 2609 { PCI_DEVICE(0x1022, 0x1487), 2610 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2611 /* AMD Stoney */ 2612 { PCI_DEVICE(0x1022, 0x157a), 2613 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | 2614 AZX_DCAPS_PM_RUNTIME }, 2615 /* AMD Raven */ 2616 { PCI_DEVICE(0x1022, 0x15e3), 2617 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2618 /* ATI HDMI */ 2619 { PCI_DEVICE(0x1002, 0x0002), 2620 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2621 AZX_DCAPS_PM_RUNTIME }, 2622 { PCI_DEVICE(0x1002, 0x1308), 2623 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2624 { PCI_DEVICE(0x1002, 0x157a), 2625 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2626 { PCI_DEVICE(0x1002, 0x15b3), 2627 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2628 { PCI_DEVICE(0x1002, 0x793b), 2629 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2630 { PCI_DEVICE(0x1002, 0x7919), 2631 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2632 { PCI_DEVICE(0x1002, 0x960f), 2633 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2634 { PCI_DEVICE(0x1002, 0x970f), 2635 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2636 { PCI_DEVICE(0x1002, 0x9840), 2637 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2638 { PCI_DEVICE(0x1002, 0xaa00), 2639 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2640 { PCI_DEVICE(0x1002, 0xaa08), 2641 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2642 { PCI_DEVICE(0x1002, 0xaa10), 2643 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2644 { PCI_DEVICE(0x1002, 0xaa18), 2645 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2646 { PCI_DEVICE(0x1002, 0xaa20), 2647 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2648 { PCI_DEVICE(0x1002, 0xaa28), 2649 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2650 { PCI_DEVICE(0x1002, 0xaa30), 2651 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2652 { PCI_DEVICE(0x1002, 0xaa38), 2653 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2654 { PCI_DEVICE(0x1002, 0xaa40), 2655 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2656 { PCI_DEVICE(0x1002, 0xaa48), 2657 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2658 { PCI_DEVICE(0x1002, 0xaa50), 2659 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2660 { PCI_DEVICE(0x1002, 0xaa58), 2661 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2662 { PCI_DEVICE(0x1002, 0xaa60), 2663 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2664 { PCI_DEVICE(0x1002, 0xaa68), 2665 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2666 { PCI_DEVICE(0x1002, 0xaa80), 2667 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2668 { PCI_DEVICE(0x1002, 0xaa88), 2669 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2670 { PCI_DEVICE(0x1002, 0xaa90), 2671 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2672 { PCI_DEVICE(0x1002, 0xaa98), 2673 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2674 { PCI_DEVICE(0x1002, 0x9902), 2675 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2676 { PCI_DEVICE(0x1002, 0xaaa0), 2677 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2678 { PCI_DEVICE(0x1002, 0xaaa8), 2679 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2680 { PCI_DEVICE(0x1002, 0xaab0), 2681 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2682 { PCI_DEVICE(0x1002, 0xaac0), 2683 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2684 AZX_DCAPS_PM_RUNTIME }, 2685 { PCI_DEVICE(0x1002, 0xaac8), 2686 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2687 AZX_DCAPS_PM_RUNTIME }, 2688 { PCI_DEVICE(0x1002, 0xaad8), 2689 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2690 AZX_DCAPS_PM_RUNTIME }, 2691 { PCI_DEVICE(0x1002, 0xaae0), 2692 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2693 AZX_DCAPS_PM_RUNTIME }, 2694 { PCI_DEVICE(0x1002, 0xaae8), 2695 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2696 AZX_DCAPS_PM_RUNTIME }, 2697 { PCI_DEVICE(0x1002, 0xaaf0), 2698 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2699 AZX_DCAPS_PM_RUNTIME }, 2700 { PCI_DEVICE(0x1002, 0xaaf8), 2701 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2702 AZX_DCAPS_PM_RUNTIME }, 2703 { PCI_DEVICE(0x1002, 0xab00), 2704 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2705 AZX_DCAPS_PM_RUNTIME }, 2706 { PCI_DEVICE(0x1002, 0xab08), 2707 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2708 AZX_DCAPS_PM_RUNTIME }, 2709 { PCI_DEVICE(0x1002, 0xab10), 2710 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2711 AZX_DCAPS_PM_RUNTIME }, 2712 { PCI_DEVICE(0x1002, 0xab18), 2713 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2714 AZX_DCAPS_PM_RUNTIME }, 2715 { PCI_DEVICE(0x1002, 0xab20), 2716 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2717 AZX_DCAPS_PM_RUNTIME }, 2718 { PCI_DEVICE(0x1002, 0xab28), 2719 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2720 AZX_DCAPS_PM_RUNTIME }, 2721 { PCI_DEVICE(0x1002, 0xab30), 2722 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2723 AZX_DCAPS_PM_RUNTIME }, 2724 { PCI_DEVICE(0x1002, 0xab38), 2725 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2726 AZX_DCAPS_PM_RUNTIME }, 2727 /* VIA VT8251/VT8237A */ 2728 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2729 /* VIA GFX VT7122/VX900 */ 2730 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2731 /* VIA GFX VT6122/VX11 */ 2732 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2733 /* SIS966 */ 2734 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2735 /* ULI M5461 */ 2736 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2737 /* NVIDIA MCP */ 2738 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2739 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2740 .class_mask = 0xffffff, 2741 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2742 /* Teradici */ 2743 { PCI_DEVICE(0x6549, 0x1200), 2744 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2745 { PCI_DEVICE(0x6549, 0x2200), 2746 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2747 /* Creative X-Fi (CA0110-IBG) */ 2748 /* CTHDA chips */ 2749 { PCI_DEVICE(0x1102, 0x0010), 2750 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2751 { PCI_DEVICE(0x1102, 0x0012), 2752 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2753 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2754 /* the following entry conflicts with snd-ctxfi driver, 2755 * as ctxfi driver mutates from HD-audio to native mode with 2756 * a special command sequence. 2757 */ 2758 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2759 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2760 .class_mask = 0xffffff, 2761 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2762 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2763 #else 2764 /* this entry seems still valid -- i.e. without emu20kx chip */ 2765 { PCI_DEVICE(0x1102, 0x0009), 2766 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2767 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2768 #endif 2769 /* CM8888 */ 2770 { PCI_DEVICE(0x13f6, 0x5011), 2771 .driver_data = AZX_DRIVER_CMEDIA | 2772 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2773 /* Vortex86MX */ 2774 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2775 /* VMware HDAudio */ 2776 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2777 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2778 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2779 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2780 .class_mask = 0xffffff, 2781 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2782 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2783 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2784 .class_mask = 0xffffff, 2785 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2786 /* Zhaoxin */ 2787 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN }, 2788 { 0, } 2789 }; 2790 MODULE_DEVICE_TABLE(pci, azx_ids); 2791 2792 /* pci_driver definition */ 2793 static struct pci_driver azx_driver = { 2794 .name = KBUILD_MODNAME, 2795 .id_table = azx_ids, 2796 .probe = azx_probe, 2797 .remove = azx_remove, 2798 .shutdown = azx_shutdown, 2799 .driver = { 2800 .pm = AZX_PM_OPS, 2801 }, 2802 }; 2803 2804 module_pci_driver(azx_driver); 2805