1 /* 2 * 3 * hda_intel.c - Implementation of primary alsa driver code base 4 * for Intel HD Audio. 5 * 6 * Copyright(c) 2004 Intel Corporation. All rights reserved. 7 * 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the Free 13 * Software Foundation; either version 2 of the License, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 * 21 * You should have received a copy of the GNU General Public License along with 22 * this program; if not, write to the Free Software Foundation, Inc., 59 23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 24 * 25 * CONTACTS: 26 * 27 * Matt Jared matt.jared@intel.com 28 * Andy Kopp andy.kopp@intel.com 29 * Dan Kogan dan.d.kogan@intel.com 30 * 31 * CHANGES: 32 * 33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 34 * 35 */ 36 37 #include <linux/delay.h> 38 #include <linux/interrupt.h> 39 #include <linux/kernel.h> 40 #include <linux/module.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/moduleparam.h> 43 #include <linux/init.h> 44 #include <linux/slab.h> 45 #include <linux/pci.h> 46 #include <linux/mutex.h> 47 #include <linux/io.h> 48 #include <linux/pm_runtime.h> 49 #include <linux/clocksource.h> 50 #include <linux/time.h> 51 #include <linux/completion.h> 52 53 #ifdef CONFIG_X86 54 /* for snoop control */ 55 #include <asm/pgtable.h> 56 #include <asm/cacheflush.h> 57 #endif 58 #include <sound/core.h> 59 #include <sound/initval.h> 60 #include <sound/hdaudio.h> 61 #include <sound/hda_i915.h> 62 #include <linux/vgaarb.h> 63 #include <linux/vga_switcheroo.h> 64 #include <linux/firmware.h> 65 #include "hda_codec.h" 66 #include "hda_controller.h" 67 #include "hda_intel.h" 68 69 #define CREATE_TRACE_POINTS 70 #include "hda_intel_trace.h" 71 72 /* position fix mode */ 73 enum { 74 POS_FIX_AUTO, 75 POS_FIX_LPIB, 76 POS_FIX_POSBUF, 77 POS_FIX_VIACOMBO, 78 POS_FIX_COMBO, 79 }; 80 81 /* Defines for ATI HD Audio support in SB450 south bridge */ 82 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 83 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 84 85 /* Defines for Nvidia HDA support */ 86 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 87 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 88 #define NVIDIA_HDA_ISTRM_COH 0x4d 89 #define NVIDIA_HDA_OSTRM_COH 0x4c 90 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 91 92 /* Defines for Intel SCH HDA snoop control */ 93 #define INTEL_SCH_HDA_DEVC 0x78 94 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 95 96 /* Define IN stream 0 FIFO size offset in VIA controller */ 97 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 98 /* Define VIA HD Audio Device ID*/ 99 #define VIA_HDAC_DEVICE_ID 0x3288 100 101 /* max number of SDs */ 102 /* ICH, ATI and VIA have 4 playback and 4 capture */ 103 #define ICH6_NUM_CAPTURE 4 104 #define ICH6_NUM_PLAYBACK 4 105 106 /* ULI has 6 playback and 5 capture */ 107 #define ULI_NUM_CAPTURE 5 108 #define ULI_NUM_PLAYBACK 6 109 110 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 111 #define ATIHDMI_NUM_CAPTURE 0 112 #define ATIHDMI_NUM_PLAYBACK 8 113 114 /* TERA has 4 playback and 3 capture */ 115 #define TERA_NUM_CAPTURE 3 116 #define TERA_NUM_PLAYBACK 4 117 118 119 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 120 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 121 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 122 static char *model[SNDRV_CARDS]; 123 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 124 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 125 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 126 static int probe_only[SNDRV_CARDS]; 127 static int jackpoll_ms[SNDRV_CARDS]; 128 static bool single_cmd; 129 static int enable_msi = -1; 130 #ifdef CONFIG_SND_HDA_PATCH_LOADER 131 static char *patch[SNDRV_CARDS]; 132 #endif 133 #ifdef CONFIG_SND_HDA_INPUT_BEEP 134 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 135 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 136 #endif 137 138 module_param_array(index, int, NULL, 0444); 139 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 140 module_param_array(id, charp, NULL, 0444); 141 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 142 module_param_array(enable, bool, NULL, 0444); 143 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 144 module_param_array(model, charp, NULL, 0444); 145 MODULE_PARM_DESC(model, "Use the given board model."); 146 module_param_array(position_fix, int, NULL, 0444); 147 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 148 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO)."); 149 module_param_array(bdl_pos_adj, int, NULL, 0644); 150 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 151 module_param_array(probe_mask, int, NULL, 0444); 152 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 153 module_param_array(probe_only, int, NULL, 0444); 154 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 155 module_param_array(jackpoll_ms, int, NULL, 0444); 156 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 157 module_param(single_cmd, bool, 0444); 158 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 159 "(for debugging only)."); 160 module_param(enable_msi, bint, 0444); 161 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 162 #ifdef CONFIG_SND_HDA_PATCH_LOADER 163 module_param_array(patch, charp, NULL, 0444); 164 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 165 #endif 166 #ifdef CONFIG_SND_HDA_INPUT_BEEP 167 module_param_array(beep_mode, bool, NULL, 0444); 168 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 169 "(0=off, 1=on) (default=1)."); 170 #endif 171 172 #ifdef CONFIG_PM 173 static int param_set_xint(const char *val, const struct kernel_param *kp); 174 static const struct kernel_param_ops param_ops_xint = { 175 .set = param_set_xint, 176 .get = param_get_int, 177 }; 178 #define param_check_xint param_check_int 179 180 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 181 module_param(power_save, xint, 0644); 182 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 183 "(in second, 0 = disable)."); 184 185 /* reset the HD-audio controller in power save mode. 186 * this may give more power-saving, but will take longer time to 187 * wake up. 188 */ 189 static bool power_save_controller = 1; 190 module_param(power_save_controller, bool, 0644); 191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 192 #else 193 #define power_save 0 194 #endif /* CONFIG_PM */ 195 196 static int align_buffer_size = -1; 197 module_param(align_buffer_size, bint, 0644); 198 MODULE_PARM_DESC(align_buffer_size, 199 "Force buffer and period sizes to be multiple of 128 bytes."); 200 201 #ifdef CONFIG_X86 202 static int hda_snoop = -1; 203 module_param_named(snoop, hda_snoop, bint, 0444); 204 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 205 #else 206 #define hda_snoop true 207 #endif 208 209 210 MODULE_LICENSE("GPL"); 211 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 212 "{Intel, ICH6M}," 213 "{Intel, ICH7}," 214 "{Intel, ESB2}," 215 "{Intel, ICH8}," 216 "{Intel, ICH9}," 217 "{Intel, ICH10}," 218 "{Intel, PCH}," 219 "{Intel, CPT}," 220 "{Intel, PPT}," 221 "{Intel, LPT}," 222 "{Intel, LPT_LP}," 223 "{Intel, WPT_LP}," 224 "{Intel, SPT}," 225 "{Intel, SPT_LP}," 226 "{Intel, HPT}," 227 "{Intel, PBG}," 228 "{Intel, SCH}," 229 "{ATI, SB450}," 230 "{ATI, SB600}," 231 "{ATI, RS600}," 232 "{ATI, RS690}," 233 "{ATI, RS780}," 234 "{ATI, R600}," 235 "{ATI, RV630}," 236 "{ATI, RV610}," 237 "{ATI, RV670}," 238 "{ATI, RV635}," 239 "{ATI, RV620}," 240 "{ATI, RV770}," 241 "{VIA, VT8251}," 242 "{VIA, VT8237A}," 243 "{SiS, SIS966}," 244 "{ULI, M5461}}"); 245 MODULE_DESCRIPTION("Intel HDA driver"); 246 247 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 248 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 249 #define SUPPORT_VGA_SWITCHEROO 250 #endif 251 #endif 252 253 254 /* 255 */ 256 257 /* driver types */ 258 enum { 259 AZX_DRIVER_ICH, 260 AZX_DRIVER_PCH, 261 AZX_DRIVER_SCH, 262 AZX_DRIVER_HDMI, 263 AZX_DRIVER_ATI, 264 AZX_DRIVER_ATIHDMI, 265 AZX_DRIVER_ATIHDMI_NS, 266 AZX_DRIVER_VIA, 267 AZX_DRIVER_SIS, 268 AZX_DRIVER_ULI, 269 AZX_DRIVER_NVIDIA, 270 AZX_DRIVER_TERA, 271 AZX_DRIVER_CTX, 272 AZX_DRIVER_CTHDA, 273 AZX_DRIVER_CMEDIA, 274 AZX_DRIVER_GENERIC, 275 AZX_NUM_DRIVERS, /* keep this as last entry */ 276 }; 277 278 #define azx_get_snoop_type(chip) \ 279 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 280 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 281 282 /* quirks for old Intel chipsets */ 283 #define AZX_DCAPS_INTEL_ICH \ 284 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 285 286 /* quirks for Intel PCH */ 287 #define AZX_DCAPS_INTEL_PCH_NOPM \ 288 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 289 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH)) 290 291 #define AZX_DCAPS_INTEL_PCH \ 292 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME) 293 294 #define AZX_DCAPS_INTEL_HASWELL \ 295 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 296 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\ 297 AZX_DCAPS_SNOOP_TYPE(SCH)) 298 299 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 300 #define AZX_DCAPS_INTEL_BROADWELL \ 301 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 302 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\ 303 AZX_DCAPS_SNOOP_TYPE(SCH)) 304 305 #define AZX_DCAPS_INTEL_BAYTRAIL \ 306 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL) 307 308 #define AZX_DCAPS_INTEL_BRASWELL \ 309 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL) 310 311 #define AZX_DCAPS_INTEL_SKYLAKE \ 312 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\ 313 AZX_DCAPS_I915_POWERWELL) 314 315 /* quirks for ATI SB / AMD Hudson */ 316 #define AZX_DCAPS_PRESET_ATI_SB \ 317 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\ 318 AZX_DCAPS_SNOOP_TYPE(ATI)) 319 320 /* quirks for ATI/AMD HDMI */ 321 #define AZX_DCAPS_PRESET_ATI_HDMI \ 322 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\ 323 AZX_DCAPS_NO_MSI64) 324 325 /* quirks for ATI HDMI with snoop off */ 326 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 327 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 328 329 /* quirks for Nvidia */ 330 #define AZX_DCAPS_PRESET_NVIDIA \ 331 (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \ 332 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 333 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 334 335 #define AZX_DCAPS_PRESET_CTHDA \ 336 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 337 AZX_DCAPS_NO_64BIT |\ 338 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 339 340 /* 341 * vga_switcheroo support 342 */ 343 #ifdef SUPPORT_VGA_SWITCHEROO 344 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 345 #else 346 #define use_vga_switcheroo(chip) 0 347 #endif 348 349 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \ 350 ((pci)->device == 0x0c0c) || \ 351 ((pci)->device == 0x0d0c) || \ 352 ((pci)->device == 0x160c)) 353 354 static char *driver_short_names[] = { 355 [AZX_DRIVER_ICH] = "HDA Intel", 356 [AZX_DRIVER_PCH] = "HDA Intel PCH", 357 [AZX_DRIVER_SCH] = "HDA Intel MID", 358 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 359 [AZX_DRIVER_ATI] = "HDA ATI SB", 360 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 361 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 362 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 363 [AZX_DRIVER_SIS] = "HDA SIS966", 364 [AZX_DRIVER_ULI] = "HDA ULI M5461", 365 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 366 [AZX_DRIVER_TERA] = "HDA Teradici", 367 [AZX_DRIVER_CTX] = "HDA Creative", 368 [AZX_DRIVER_CTHDA] = "HDA Creative", 369 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 370 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 371 }; 372 373 #ifdef CONFIG_X86 374 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on) 375 { 376 int pages; 377 378 if (azx_snoop(chip)) 379 return; 380 if (!dmab || !dmab->area || !dmab->bytes) 381 return; 382 383 #ifdef CONFIG_SND_DMA_SGBUF 384 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) { 385 struct snd_sg_buf *sgbuf = dmab->private_data; 386 if (chip->driver_type == AZX_DRIVER_CMEDIA) 387 return; /* deal with only CORB/RIRB buffers */ 388 if (on) 389 set_pages_array_wc(sgbuf->page_table, sgbuf->pages); 390 else 391 set_pages_array_wb(sgbuf->page_table, sgbuf->pages); 392 return; 393 } 394 #endif 395 396 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT; 397 if (on) 398 set_memory_wc((unsigned long)dmab->area, pages); 399 else 400 set_memory_wb((unsigned long)dmab->area, pages); 401 } 402 403 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 404 bool on) 405 { 406 __mark_pages_wc(chip, buf, on); 407 } 408 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 409 struct snd_pcm_substream *substream, bool on) 410 { 411 if (azx_dev->wc_marked != on) { 412 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on); 413 azx_dev->wc_marked = on; 414 } 415 } 416 #else 417 /* NOP for other archs */ 418 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 419 bool on) 420 { 421 } 422 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 423 struct snd_pcm_substream *substream, bool on) 424 { 425 } 426 #endif 427 428 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 429 430 /* 431 * initialize the PCI registers 432 */ 433 /* update bits in a PCI register byte */ 434 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 435 unsigned char mask, unsigned char val) 436 { 437 unsigned char data; 438 439 pci_read_config_byte(pci, reg, &data); 440 data &= ~mask; 441 data |= (val & mask); 442 pci_write_config_byte(pci, reg, data); 443 } 444 445 static void azx_init_pci(struct azx *chip) 446 { 447 int snoop_type = azx_get_snoop_type(chip); 448 449 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 450 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 451 * Ensuring these bits are 0 clears playback static on some HD Audio 452 * codecs. 453 * The PCI register TCSEL is defined in the Intel manuals. 454 */ 455 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 456 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 457 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 458 } 459 460 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 461 * we need to enable snoop. 462 */ 463 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 464 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 465 azx_snoop(chip)); 466 update_pci_byte(chip->pci, 467 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 468 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 469 } 470 471 /* For NVIDIA HDA, enable snoop */ 472 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 473 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 474 azx_snoop(chip)); 475 update_pci_byte(chip->pci, 476 NVIDIA_HDA_TRANSREG_ADDR, 477 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 478 update_pci_byte(chip->pci, 479 NVIDIA_HDA_ISTRM_COH, 480 0x01, NVIDIA_HDA_ENABLE_COHBIT); 481 update_pci_byte(chip->pci, 482 NVIDIA_HDA_OSTRM_COH, 483 0x01, NVIDIA_HDA_ENABLE_COHBIT); 484 } 485 486 /* Enable SCH/PCH snoop if needed */ 487 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 488 unsigned short snoop; 489 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 490 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 491 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 492 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 493 if (!azx_snoop(chip)) 494 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 495 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 496 pci_read_config_word(chip->pci, 497 INTEL_SCH_HDA_DEVC, &snoop); 498 } 499 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 500 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 501 "Disabled" : "Enabled"); 502 } 503 } 504 505 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 506 { 507 struct hdac_bus *bus = azx_bus(chip); 508 509 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 510 snd_hdac_set_codec_wakeup(bus, true); 511 azx_init_chip(chip, full_reset); 512 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 513 snd_hdac_set_codec_wakeup(bus, false); 514 } 515 516 /* calculate runtime delay from LPIB */ 517 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 518 unsigned int pos) 519 { 520 struct snd_pcm_substream *substream = azx_dev->core.substream; 521 int stream = substream->stream; 522 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 523 int delay; 524 525 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 526 delay = pos - lpib_pos; 527 else 528 delay = lpib_pos - pos; 529 if (delay < 0) { 530 if (delay >= azx_dev->core.delay_negative_threshold) 531 delay = 0; 532 else 533 delay += azx_dev->core.bufsize; 534 } 535 536 if (delay >= azx_dev->core.period_bytes) { 537 dev_info(chip->card->dev, 538 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 539 delay, azx_dev->core.period_bytes); 540 delay = 0; 541 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 542 chip->get_delay[stream] = NULL; 543 } 544 545 return bytes_to_frames(substream->runtime, delay); 546 } 547 548 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 549 550 /* called from IRQ */ 551 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 552 { 553 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 554 int ok; 555 556 ok = azx_position_ok(chip, azx_dev); 557 if (ok == 1) { 558 azx_dev->irq_pending = 0; 559 return ok; 560 } else if (ok == 0) { 561 /* bogus IRQ, process it later */ 562 azx_dev->irq_pending = 1; 563 schedule_work(&hda->irq_pending_work); 564 } 565 return 0; 566 } 567 568 /* Enable/disable i915 display power for the link */ 569 static int azx_intel_link_power(struct azx *chip, bool enable) 570 { 571 struct hdac_bus *bus = azx_bus(chip); 572 573 return snd_hdac_display_power(bus, enable); 574 } 575 576 /* 577 * Check whether the current DMA position is acceptable for updating 578 * periods. Returns non-zero if it's OK. 579 * 580 * Many HD-audio controllers appear pretty inaccurate about 581 * the update-IRQ timing. The IRQ is issued before actually the 582 * data is processed. So, we need to process it afterwords in a 583 * workqueue. 584 */ 585 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 586 { 587 struct snd_pcm_substream *substream = azx_dev->core.substream; 588 int stream = substream->stream; 589 u32 wallclk; 590 unsigned int pos; 591 592 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 593 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 594 return -1; /* bogus (too early) interrupt */ 595 596 if (chip->get_position[stream]) 597 pos = chip->get_position[stream](chip, azx_dev); 598 else { /* use the position buffer as default */ 599 pos = azx_get_pos_posbuf(chip, azx_dev); 600 if (!pos || pos == (u32)-1) { 601 dev_info(chip->card->dev, 602 "Invalid position buffer, using LPIB read method instead.\n"); 603 chip->get_position[stream] = azx_get_pos_lpib; 604 if (chip->get_position[0] == azx_get_pos_lpib && 605 chip->get_position[1] == azx_get_pos_lpib) 606 azx_bus(chip)->use_posbuf = false; 607 pos = azx_get_pos_lpib(chip, azx_dev); 608 chip->get_delay[stream] = NULL; 609 } else { 610 chip->get_position[stream] = azx_get_pos_posbuf; 611 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 612 chip->get_delay[stream] = azx_get_delay_from_lpib; 613 } 614 } 615 616 if (pos >= azx_dev->core.bufsize) 617 pos = 0; 618 619 if (WARN_ONCE(!azx_dev->core.period_bytes, 620 "hda-intel: zero azx_dev->period_bytes")) 621 return -1; /* this shouldn't happen! */ 622 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 623 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 624 /* NG - it's below the first next period boundary */ 625 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1; 626 azx_dev->core.start_wallclk += wallclk; 627 return 1; /* OK, it's fine */ 628 } 629 630 /* 631 * The work for pending PCM period updates. 632 */ 633 static void azx_irq_pending_work(struct work_struct *work) 634 { 635 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 636 struct azx *chip = &hda->chip; 637 struct hdac_bus *bus = azx_bus(chip); 638 struct hdac_stream *s; 639 int pending, ok; 640 641 if (!hda->irq_pending_warned) { 642 dev_info(chip->card->dev, 643 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 644 chip->card->number); 645 hda->irq_pending_warned = 1; 646 } 647 648 for (;;) { 649 pending = 0; 650 spin_lock_irq(&bus->reg_lock); 651 list_for_each_entry(s, &bus->stream_list, list) { 652 struct azx_dev *azx_dev = stream_to_azx_dev(s); 653 if (!azx_dev->irq_pending || 654 !s->substream || 655 !s->running) 656 continue; 657 ok = azx_position_ok(chip, azx_dev); 658 if (ok > 0) { 659 azx_dev->irq_pending = 0; 660 spin_unlock(&bus->reg_lock); 661 snd_pcm_period_elapsed(s->substream); 662 spin_lock(&bus->reg_lock); 663 } else if (ok < 0) { 664 pending = 0; /* too early */ 665 } else 666 pending++; 667 } 668 spin_unlock_irq(&bus->reg_lock); 669 if (!pending) 670 return; 671 msleep(1); 672 } 673 } 674 675 /* clear irq_pending flags and assure no on-going workq */ 676 static void azx_clear_irq_pending(struct azx *chip) 677 { 678 struct hdac_bus *bus = azx_bus(chip); 679 struct hdac_stream *s; 680 681 spin_lock_irq(&bus->reg_lock); 682 list_for_each_entry(s, &bus->stream_list, list) { 683 struct azx_dev *azx_dev = stream_to_azx_dev(s); 684 azx_dev->irq_pending = 0; 685 } 686 spin_unlock_irq(&bus->reg_lock); 687 } 688 689 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 690 { 691 struct hdac_bus *bus = azx_bus(chip); 692 693 if (request_irq(chip->pci->irq, azx_interrupt, 694 chip->msi ? 0 : IRQF_SHARED, 695 KBUILD_MODNAME, chip)) { 696 dev_err(chip->card->dev, 697 "unable to grab IRQ %d, disabling device\n", 698 chip->pci->irq); 699 if (do_disconnect) 700 snd_card_disconnect(chip->card); 701 return -1; 702 } 703 bus->irq = chip->pci->irq; 704 pci_intx(chip->pci, !chip->msi); 705 return 0; 706 } 707 708 /* get the current DMA position with correction on VIA chips */ 709 static unsigned int azx_via_get_position(struct azx *chip, 710 struct azx_dev *azx_dev) 711 { 712 unsigned int link_pos, mini_pos, bound_pos; 713 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 714 unsigned int fifo_size; 715 716 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 717 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 718 /* Playback, no problem using link position */ 719 return link_pos; 720 } 721 722 /* Capture */ 723 /* For new chipset, 724 * use mod to get the DMA position just like old chipset 725 */ 726 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 727 mod_dma_pos %= azx_dev->core.period_bytes; 728 729 /* azx_dev->fifo_size can't get FIFO size of in stream. 730 * Get from base address + offset. 731 */ 732 fifo_size = readw(azx_bus(chip)->remap_addr + 733 VIA_IN_STREAM0_FIFO_SIZE_OFFSET); 734 735 if (azx_dev->insufficient) { 736 /* Link position never gather than FIFO size */ 737 if (link_pos <= fifo_size) 738 return 0; 739 740 azx_dev->insufficient = 0; 741 } 742 743 if (link_pos <= fifo_size) 744 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 745 else 746 mini_pos = link_pos - fifo_size; 747 748 /* Find nearest previous boudary */ 749 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 750 mod_link_pos = link_pos % azx_dev->core.period_bytes; 751 if (mod_link_pos >= fifo_size) 752 bound_pos = link_pos - mod_link_pos; 753 else if (mod_dma_pos >= mod_mini_pos) 754 bound_pos = mini_pos - mod_mini_pos; 755 else { 756 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 757 if (bound_pos >= azx_dev->core.bufsize) 758 bound_pos = 0; 759 } 760 761 /* Calculate real DMA position we want */ 762 return bound_pos + mod_dma_pos; 763 } 764 765 #ifdef CONFIG_PM 766 static DEFINE_MUTEX(card_list_lock); 767 static LIST_HEAD(card_list); 768 769 static void azx_add_card_list(struct azx *chip) 770 { 771 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 772 mutex_lock(&card_list_lock); 773 list_add(&hda->list, &card_list); 774 mutex_unlock(&card_list_lock); 775 } 776 777 static void azx_del_card_list(struct azx *chip) 778 { 779 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 780 mutex_lock(&card_list_lock); 781 list_del_init(&hda->list); 782 mutex_unlock(&card_list_lock); 783 } 784 785 /* trigger power-save check at writing parameter */ 786 static int param_set_xint(const char *val, const struct kernel_param *kp) 787 { 788 struct hda_intel *hda; 789 struct azx *chip; 790 int prev = power_save; 791 int ret = param_set_int(val, kp); 792 793 if (ret || prev == power_save) 794 return ret; 795 796 mutex_lock(&card_list_lock); 797 list_for_each_entry(hda, &card_list, list) { 798 chip = &hda->chip; 799 if (!hda->probe_continued || chip->disabled) 800 continue; 801 snd_hda_set_power_save(&chip->bus, power_save * 1000); 802 } 803 mutex_unlock(&card_list_lock); 804 return 0; 805 } 806 #else 807 #define azx_add_card_list(chip) /* NOP */ 808 #define azx_del_card_list(chip) /* NOP */ 809 #endif /* CONFIG_PM */ 810 811 /* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK 812 * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value) 813 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK: 814 * BCLK = CDCLK * M / N 815 * The values will be lost when the display power well is disabled and need to 816 * be restored to avoid abnormal playback speed. 817 */ 818 static void haswell_set_bclk(struct hda_intel *hda) 819 { 820 struct azx *chip = &hda->chip; 821 int cdclk_freq; 822 unsigned int bclk_m, bclk_n; 823 824 if (!hda->need_i915_power) 825 return; 826 827 cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip)); 828 switch (cdclk_freq) { 829 case 337500: 830 bclk_m = 16; 831 bclk_n = 225; 832 break; 833 834 case 450000: 835 default: /* default CDCLK 450MHz */ 836 bclk_m = 4; 837 bclk_n = 75; 838 break; 839 840 case 540000: 841 bclk_m = 4; 842 bclk_n = 90; 843 break; 844 845 case 675000: 846 bclk_m = 8; 847 bclk_n = 225; 848 break; 849 } 850 851 azx_writew(chip, HSW_EM4, bclk_m); 852 azx_writew(chip, HSW_EM5, bclk_n); 853 } 854 855 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO) 856 /* 857 * power management 858 */ 859 static int azx_suspend(struct device *dev) 860 { 861 struct snd_card *card = dev_get_drvdata(dev); 862 struct azx *chip; 863 struct hda_intel *hda; 864 struct hdac_bus *bus; 865 866 if (!card) 867 return 0; 868 869 chip = card->private_data; 870 hda = container_of(chip, struct hda_intel, chip); 871 if (chip->disabled || hda->init_failed || !chip->running) 872 return 0; 873 874 bus = azx_bus(chip); 875 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 876 azx_clear_irq_pending(chip); 877 azx_stop_chip(chip); 878 azx_enter_link_reset(chip); 879 if (bus->irq >= 0) { 880 free_irq(bus->irq, chip); 881 bus->irq = -1; 882 } 883 884 if (chip->msi) 885 pci_disable_msi(chip->pci); 886 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL 887 && hda->need_i915_power) 888 snd_hdac_display_power(bus, false); 889 890 trace_azx_suspend(chip); 891 return 0; 892 } 893 894 static int azx_resume(struct device *dev) 895 { 896 struct pci_dev *pci = to_pci_dev(dev); 897 struct snd_card *card = dev_get_drvdata(dev); 898 struct azx *chip; 899 struct hda_intel *hda; 900 901 if (!card) 902 return 0; 903 904 chip = card->private_data; 905 hda = container_of(chip, struct hda_intel, chip); 906 if (chip->disabled || hda->init_failed || !chip->running) 907 return 0; 908 909 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL 910 && hda->need_i915_power) { 911 snd_hdac_display_power(azx_bus(chip), true); 912 haswell_set_bclk(hda); 913 } 914 if (chip->msi) 915 if (pci_enable_msi(pci) < 0) 916 chip->msi = 0; 917 if (azx_acquire_irq(chip, 1) < 0) 918 return -EIO; 919 azx_init_pci(chip); 920 921 hda_intel_init_chip(chip, true); 922 923 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 924 925 trace_azx_resume(chip); 926 return 0; 927 } 928 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */ 929 930 #ifdef CONFIG_PM 931 static int azx_runtime_suspend(struct device *dev) 932 { 933 struct snd_card *card = dev_get_drvdata(dev); 934 struct azx *chip; 935 struct hda_intel *hda; 936 937 if (!card) 938 return 0; 939 940 chip = card->private_data; 941 hda = container_of(chip, struct hda_intel, chip); 942 if (chip->disabled || hda->init_failed) 943 return 0; 944 945 if (!azx_has_pm_runtime(chip)) 946 return 0; 947 948 /* enable controller wake up event */ 949 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 950 STATESTS_INT_MASK); 951 952 azx_stop_chip(chip); 953 azx_enter_link_reset(chip); 954 azx_clear_irq_pending(chip); 955 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL 956 && hda->need_i915_power) 957 snd_hdac_display_power(azx_bus(chip), false); 958 959 trace_azx_runtime_suspend(chip); 960 return 0; 961 } 962 963 static int azx_runtime_resume(struct device *dev) 964 { 965 struct snd_card *card = dev_get_drvdata(dev); 966 struct azx *chip; 967 struct hda_intel *hda; 968 struct hdac_bus *bus; 969 struct hda_codec *codec; 970 int status; 971 972 if (!card) 973 return 0; 974 975 chip = card->private_data; 976 hda = container_of(chip, struct hda_intel, chip); 977 if (chip->disabled || hda->init_failed) 978 return 0; 979 980 if (!azx_has_pm_runtime(chip)) 981 return 0; 982 983 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 984 bus = azx_bus(chip); 985 if (hda->need_i915_power) { 986 snd_hdac_display_power(bus, true); 987 haswell_set_bclk(hda); 988 } else { 989 /* toggle codec wakeup bit for STATESTS read */ 990 snd_hdac_set_codec_wakeup(bus, true); 991 snd_hdac_set_codec_wakeup(bus, false); 992 } 993 } 994 995 /* Read STATESTS before controller reset */ 996 status = azx_readw(chip, STATESTS); 997 998 azx_init_pci(chip); 999 hda_intel_init_chip(chip, true); 1000 1001 if (status) { 1002 list_for_each_codec(codec, &chip->bus) 1003 if (status & (1 << codec->addr)) 1004 schedule_delayed_work(&codec->jackpoll_work, 1005 codec->jackpoll_interval); 1006 } 1007 1008 /* disable controller Wake Up event*/ 1009 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 1010 ~STATESTS_INT_MASK); 1011 1012 trace_azx_runtime_resume(chip); 1013 return 0; 1014 } 1015 1016 static int azx_runtime_idle(struct device *dev) 1017 { 1018 struct snd_card *card = dev_get_drvdata(dev); 1019 struct azx *chip; 1020 struct hda_intel *hda; 1021 1022 if (!card) 1023 return 0; 1024 1025 chip = card->private_data; 1026 hda = container_of(chip, struct hda_intel, chip); 1027 if (chip->disabled || hda->init_failed) 1028 return 0; 1029 1030 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1031 azx_bus(chip)->codec_powered || !chip->running) 1032 return -EBUSY; 1033 1034 return 0; 1035 } 1036 1037 static const struct dev_pm_ops azx_pm = { 1038 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1039 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1040 }; 1041 1042 #define AZX_PM_OPS &azx_pm 1043 #else 1044 #define AZX_PM_OPS NULL 1045 #endif /* CONFIG_PM */ 1046 1047 1048 static int azx_probe_continue(struct azx *chip); 1049 1050 #ifdef SUPPORT_VGA_SWITCHEROO 1051 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1052 1053 static void azx_vs_set_state(struct pci_dev *pci, 1054 enum vga_switcheroo_state state) 1055 { 1056 struct snd_card *card = pci_get_drvdata(pci); 1057 struct azx *chip = card->private_data; 1058 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1059 bool disabled; 1060 1061 wait_for_completion(&hda->probe_wait); 1062 if (hda->init_failed) 1063 return; 1064 1065 disabled = (state == VGA_SWITCHEROO_OFF); 1066 if (chip->disabled == disabled) 1067 return; 1068 1069 if (!hda->probe_continued) { 1070 chip->disabled = disabled; 1071 if (!disabled) { 1072 dev_info(chip->card->dev, 1073 "Start delayed initialization\n"); 1074 if (azx_probe_continue(chip) < 0) { 1075 dev_err(chip->card->dev, "initialization error\n"); 1076 hda->init_failed = true; 1077 } 1078 } 1079 } else { 1080 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1081 disabled ? "Disabling" : "Enabling"); 1082 if (disabled) { 1083 pm_runtime_put_sync_suspend(card->dev); 1084 azx_suspend(card->dev); 1085 /* when we get suspended by vga_switcheroo we end up in D3cold, 1086 * however we have no ACPI handle, so pci/acpi can't put us there, 1087 * put ourselves there */ 1088 pci->current_state = PCI_D3cold; 1089 chip->disabled = true; 1090 if (snd_hda_lock_devices(&chip->bus)) 1091 dev_warn(chip->card->dev, 1092 "Cannot lock devices!\n"); 1093 } else { 1094 snd_hda_unlock_devices(&chip->bus); 1095 pm_runtime_get_noresume(card->dev); 1096 chip->disabled = false; 1097 azx_resume(card->dev); 1098 } 1099 } 1100 } 1101 1102 static bool azx_vs_can_switch(struct pci_dev *pci) 1103 { 1104 struct snd_card *card = pci_get_drvdata(pci); 1105 struct azx *chip = card->private_data; 1106 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1107 1108 wait_for_completion(&hda->probe_wait); 1109 if (hda->init_failed) 1110 return false; 1111 if (chip->disabled || !hda->probe_continued) 1112 return true; 1113 if (snd_hda_lock_devices(&chip->bus)) 1114 return false; 1115 snd_hda_unlock_devices(&chip->bus); 1116 return true; 1117 } 1118 1119 static void init_vga_switcheroo(struct azx *chip) 1120 { 1121 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1122 struct pci_dev *p = get_bound_vga(chip->pci); 1123 if (p) { 1124 dev_info(chip->card->dev, 1125 "Handle vga_switcheroo audio client\n"); 1126 hda->use_vga_switcheroo = 1; 1127 pci_dev_put(p); 1128 } 1129 } 1130 1131 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1132 .set_gpu_state = azx_vs_set_state, 1133 .can_switch = azx_vs_can_switch, 1134 }; 1135 1136 static int register_vga_switcheroo(struct azx *chip) 1137 { 1138 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1139 int err; 1140 1141 if (!hda->use_vga_switcheroo) 1142 return 0; 1143 /* FIXME: currently only handling DIS controller 1144 * is there any machine with two switchable HDMI audio controllers? 1145 */ 1146 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, 1147 VGA_SWITCHEROO_DIS); 1148 if (err < 0) 1149 return err; 1150 hda->vga_switcheroo_registered = 1; 1151 1152 /* register as an optimus hdmi audio power domain */ 1153 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev, 1154 &hda->hdmi_pm_domain); 1155 return 0; 1156 } 1157 #else 1158 #define init_vga_switcheroo(chip) /* NOP */ 1159 #define register_vga_switcheroo(chip) 0 1160 #define check_hdmi_disabled(pci) false 1161 #endif /* SUPPORT_VGA_SWITCHER */ 1162 1163 /* 1164 * destructor 1165 */ 1166 static int azx_free(struct azx *chip) 1167 { 1168 struct pci_dev *pci = chip->pci; 1169 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1170 struct hdac_bus *bus = azx_bus(chip); 1171 1172 if (azx_has_pm_runtime(chip) && chip->running) 1173 pm_runtime_get_noresume(&pci->dev); 1174 1175 azx_del_card_list(chip); 1176 1177 hda->init_failed = 1; /* to be sure */ 1178 complete_all(&hda->probe_wait); 1179 1180 if (use_vga_switcheroo(hda)) { 1181 if (chip->disabled && hda->probe_continued) 1182 snd_hda_unlock_devices(&chip->bus); 1183 if (hda->vga_switcheroo_registered) 1184 vga_switcheroo_unregister_client(chip->pci); 1185 } 1186 1187 if (bus->chip_init) { 1188 azx_clear_irq_pending(chip); 1189 azx_stop_all_streams(chip); 1190 azx_stop_chip(chip); 1191 } 1192 1193 if (bus->irq >= 0) 1194 free_irq(bus->irq, (void*)chip); 1195 if (chip->msi) 1196 pci_disable_msi(chip->pci); 1197 iounmap(bus->remap_addr); 1198 1199 azx_free_stream_pages(chip); 1200 azx_free_streams(chip); 1201 snd_hdac_bus_exit(bus); 1202 1203 if (chip->region_requested) 1204 pci_release_regions(chip->pci); 1205 1206 pci_disable_device(chip->pci); 1207 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1208 release_firmware(chip->fw); 1209 #endif 1210 1211 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1212 if (hda->need_i915_power) 1213 snd_hdac_display_power(bus, false); 1214 snd_hdac_i915_exit(bus); 1215 } 1216 kfree(hda); 1217 1218 return 0; 1219 } 1220 1221 static int azx_dev_disconnect(struct snd_device *device) 1222 { 1223 struct azx *chip = device->device_data; 1224 1225 chip->bus.shutdown = 1; 1226 return 0; 1227 } 1228 1229 static int azx_dev_free(struct snd_device *device) 1230 { 1231 return azx_free(device->device_data); 1232 } 1233 1234 #ifdef SUPPORT_VGA_SWITCHEROO 1235 /* 1236 * Check of disabled HDMI controller by vga_switcheroo 1237 */ 1238 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1239 { 1240 struct pci_dev *p; 1241 1242 /* check only discrete GPU */ 1243 switch (pci->vendor) { 1244 case PCI_VENDOR_ID_ATI: 1245 case PCI_VENDOR_ID_AMD: 1246 case PCI_VENDOR_ID_NVIDIA: 1247 if (pci->devfn == 1) { 1248 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1249 pci->bus->number, 0); 1250 if (p) { 1251 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA) 1252 return p; 1253 pci_dev_put(p); 1254 } 1255 } 1256 break; 1257 } 1258 return NULL; 1259 } 1260 1261 static bool check_hdmi_disabled(struct pci_dev *pci) 1262 { 1263 bool vga_inactive = false; 1264 struct pci_dev *p = get_bound_vga(pci); 1265 1266 if (p) { 1267 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1268 vga_inactive = true; 1269 pci_dev_put(p); 1270 } 1271 return vga_inactive; 1272 } 1273 #endif /* SUPPORT_VGA_SWITCHEROO */ 1274 1275 /* 1276 * white/black-listing for position_fix 1277 */ 1278 static struct snd_pci_quirk position_fix_list[] = { 1279 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1280 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1281 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1282 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1283 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1284 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1285 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1286 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1287 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1288 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1289 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1290 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1291 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1292 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1293 {} 1294 }; 1295 1296 static int check_position_fix(struct azx *chip, int fix) 1297 { 1298 const struct snd_pci_quirk *q; 1299 1300 switch (fix) { 1301 case POS_FIX_AUTO: 1302 case POS_FIX_LPIB: 1303 case POS_FIX_POSBUF: 1304 case POS_FIX_VIACOMBO: 1305 case POS_FIX_COMBO: 1306 return fix; 1307 } 1308 1309 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1310 if (q) { 1311 dev_info(chip->card->dev, 1312 "position_fix set to %d for device %04x:%04x\n", 1313 q->value, q->subvendor, q->subdevice); 1314 return q->value; 1315 } 1316 1317 /* Check VIA/ATI HD Audio Controller exist */ 1318 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) { 1319 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1320 return POS_FIX_VIACOMBO; 1321 } 1322 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1323 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1324 return POS_FIX_LPIB; 1325 } 1326 return POS_FIX_AUTO; 1327 } 1328 1329 static void assign_position_fix(struct azx *chip, int fix) 1330 { 1331 static azx_get_pos_callback_t callbacks[] = { 1332 [POS_FIX_AUTO] = NULL, 1333 [POS_FIX_LPIB] = azx_get_pos_lpib, 1334 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1335 [POS_FIX_VIACOMBO] = azx_via_get_position, 1336 [POS_FIX_COMBO] = azx_get_pos_lpib, 1337 }; 1338 1339 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1340 1341 /* combo mode uses LPIB only for playback */ 1342 if (fix == POS_FIX_COMBO) 1343 chip->get_position[1] = NULL; 1344 1345 if (fix == POS_FIX_POSBUF && 1346 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1347 chip->get_delay[0] = chip->get_delay[1] = 1348 azx_get_delay_from_lpib; 1349 } 1350 1351 } 1352 1353 /* 1354 * black-lists for probe_mask 1355 */ 1356 static struct snd_pci_quirk probe_mask_list[] = { 1357 /* Thinkpad often breaks the controller communication when accessing 1358 * to the non-working (or non-existing) modem codec slot. 1359 */ 1360 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1361 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1362 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1363 /* broken BIOS */ 1364 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1365 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1366 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1367 /* forced codec slots */ 1368 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1369 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1370 /* WinFast VP200 H (Teradici) user reported broken communication */ 1371 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1372 {} 1373 }; 1374 1375 #define AZX_FORCE_CODEC_MASK 0x100 1376 1377 static void check_probe_mask(struct azx *chip, int dev) 1378 { 1379 const struct snd_pci_quirk *q; 1380 1381 chip->codec_probe_mask = probe_mask[dev]; 1382 if (chip->codec_probe_mask == -1) { 1383 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1384 if (q) { 1385 dev_info(chip->card->dev, 1386 "probe_mask set to 0x%x for device %04x:%04x\n", 1387 q->value, q->subvendor, q->subdevice); 1388 chip->codec_probe_mask = q->value; 1389 } 1390 } 1391 1392 /* check forced option */ 1393 if (chip->codec_probe_mask != -1 && 1394 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1395 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1396 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1397 (int)azx_bus(chip)->codec_mask); 1398 } 1399 } 1400 1401 /* 1402 * white/black-list for enable_msi 1403 */ 1404 static struct snd_pci_quirk msi_black_list[] = { 1405 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1406 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1407 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1408 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1409 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1410 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1411 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1412 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1413 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1414 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1415 {} 1416 }; 1417 1418 static void check_msi(struct azx *chip) 1419 { 1420 const struct snd_pci_quirk *q; 1421 1422 if (enable_msi >= 0) { 1423 chip->msi = !!enable_msi; 1424 return; 1425 } 1426 chip->msi = 1; /* enable MSI as default */ 1427 q = snd_pci_quirk_lookup(chip->pci, msi_black_list); 1428 if (q) { 1429 dev_info(chip->card->dev, 1430 "msi for device %04x:%04x set to %d\n", 1431 q->subvendor, q->subdevice, q->value); 1432 chip->msi = q->value; 1433 return; 1434 } 1435 1436 /* NVidia chipsets seem to cause troubles with MSI */ 1437 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1438 dev_info(chip->card->dev, "Disabling MSI\n"); 1439 chip->msi = 0; 1440 } 1441 } 1442 1443 /* check the snoop mode availability */ 1444 static void azx_check_snoop_available(struct azx *chip) 1445 { 1446 int snoop = hda_snoop; 1447 1448 if (snoop >= 0) { 1449 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1450 snoop ? "snoop" : "non-snoop"); 1451 chip->snoop = snoop; 1452 return; 1453 } 1454 1455 snoop = true; 1456 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1457 chip->driver_type == AZX_DRIVER_VIA) { 1458 /* force to non-snoop mode for a new VIA controller 1459 * when BIOS is set 1460 */ 1461 u8 val; 1462 pci_read_config_byte(chip->pci, 0x42, &val); 1463 if (!(val & 0x80) && chip->pci->revision == 0x30) 1464 snoop = false; 1465 } 1466 1467 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1468 snoop = false; 1469 1470 chip->snoop = snoop; 1471 if (!snoop) 1472 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1473 } 1474 1475 static void azx_probe_work(struct work_struct *work) 1476 { 1477 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work); 1478 azx_probe_continue(&hda->chip); 1479 } 1480 1481 /* 1482 * constructor 1483 */ 1484 static const struct hdac_io_ops pci_hda_io_ops; 1485 static const struct hda_controller_ops pci_hda_ops; 1486 1487 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1488 int dev, unsigned int driver_caps, 1489 struct azx **rchip) 1490 { 1491 static struct snd_device_ops ops = { 1492 .dev_disconnect = azx_dev_disconnect, 1493 .dev_free = azx_dev_free, 1494 }; 1495 struct hda_intel *hda; 1496 struct azx *chip; 1497 int err; 1498 1499 *rchip = NULL; 1500 1501 err = pci_enable_device(pci); 1502 if (err < 0) 1503 return err; 1504 1505 hda = kzalloc(sizeof(*hda), GFP_KERNEL); 1506 if (!hda) { 1507 pci_disable_device(pci); 1508 return -ENOMEM; 1509 } 1510 1511 chip = &hda->chip; 1512 mutex_init(&chip->open_mutex); 1513 chip->card = card; 1514 chip->pci = pci; 1515 chip->ops = &pci_hda_ops; 1516 chip->driver_caps = driver_caps; 1517 chip->driver_type = driver_caps & 0xff; 1518 check_msi(chip); 1519 chip->dev_index = dev; 1520 chip->jackpoll_ms = jackpoll_ms; 1521 INIT_LIST_HEAD(&chip->pcm_list); 1522 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1523 INIT_LIST_HEAD(&hda->list); 1524 init_vga_switcheroo(chip); 1525 init_completion(&hda->probe_wait); 1526 1527 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1528 1529 check_probe_mask(chip, dev); 1530 1531 chip->single_cmd = single_cmd; 1532 azx_check_snoop_available(chip); 1533 1534 if (bdl_pos_adj[dev] < 0) { 1535 switch (chip->driver_type) { 1536 case AZX_DRIVER_ICH: 1537 case AZX_DRIVER_PCH: 1538 bdl_pos_adj[dev] = 1; 1539 break; 1540 default: 1541 bdl_pos_adj[dev] = 32; 1542 break; 1543 } 1544 } 1545 chip->bdl_pos_adj = bdl_pos_adj; 1546 1547 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops); 1548 if (err < 0) { 1549 kfree(hda); 1550 pci_disable_device(pci); 1551 return err; 1552 } 1553 1554 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1555 if (err < 0) { 1556 dev_err(card->dev, "Error creating device [card]!\n"); 1557 azx_free(chip); 1558 return err; 1559 } 1560 1561 /* continue probing in work context as may trigger request module */ 1562 INIT_WORK(&hda->probe_work, azx_probe_work); 1563 1564 *rchip = chip; 1565 1566 return 0; 1567 } 1568 1569 static int azx_first_init(struct azx *chip) 1570 { 1571 int dev = chip->dev_index; 1572 struct pci_dev *pci = chip->pci; 1573 struct snd_card *card = chip->card; 1574 struct hdac_bus *bus = azx_bus(chip); 1575 int err; 1576 unsigned short gcap; 1577 unsigned int dma_bits = 64; 1578 1579 #if BITS_PER_LONG != 64 1580 /* Fix up base address on ULI M5461 */ 1581 if (chip->driver_type == AZX_DRIVER_ULI) { 1582 u16 tmp3; 1583 pci_read_config_word(pci, 0x40, &tmp3); 1584 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1585 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1586 } 1587 #endif 1588 1589 err = pci_request_regions(pci, "ICH HD audio"); 1590 if (err < 0) 1591 return err; 1592 chip->region_requested = 1; 1593 1594 bus->addr = pci_resource_start(pci, 0); 1595 bus->remap_addr = pci_ioremap_bar(pci, 0); 1596 if (bus->remap_addr == NULL) { 1597 dev_err(card->dev, "ioremap error\n"); 1598 return -ENXIO; 1599 } 1600 1601 if (chip->msi) { 1602 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1603 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1604 pci->no_64bit_msi = true; 1605 } 1606 if (pci_enable_msi(pci) < 0) 1607 chip->msi = 0; 1608 } 1609 1610 if (azx_acquire_irq(chip, 0) < 0) 1611 return -EBUSY; 1612 1613 pci_set_master(pci); 1614 synchronize_irq(bus->irq); 1615 1616 gcap = azx_readw(chip, GCAP); 1617 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1618 1619 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1620 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1621 dma_bits = 40; 1622 1623 /* disable SB600 64bit support for safety */ 1624 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1625 struct pci_dev *p_smbus; 1626 dma_bits = 40; 1627 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1628 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1629 NULL); 1630 if (p_smbus) { 1631 if (p_smbus->revision < 0x30) 1632 gcap &= ~AZX_GCAP_64OK; 1633 pci_dev_put(p_smbus); 1634 } 1635 } 1636 1637 /* disable 64bit DMA address on some devices */ 1638 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1639 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1640 gcap &= ~AZX_GCAP_64OK; 1641 } 1642 1643 /* disable buffer size rounding to 128-byte multiples if supported */ 1644 if (align_buffer_size >= 0) 1645 chip->align_buffer_size = !!align_buffer_size; 1646 else { 1647 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1648 chip->align_buffer_size = 0; 1649 else 1650 chip->align_buffer_size = 1; 1651 } 1652 1653 /* allow 64bit DMA address if supported by H/W */ 1654 if (!(gcap & AZX_GCAP_64OK)) 1655 dma_bits = 32; 1656 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) { 1657 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits)); 1658 } else { 1659 dma_set_mask(&pci->dev, DMA_BIT_MASK(32)); 1660 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32)); 1661 } 1662 1663 /* read number of streams from GCAP register instead of using 1664 * hardcoded value 1665 */ 1666 chip->capture_streams = (gcap >> 8) & 0x0f; 1667 chip->playback_streams = (gcap >> 12) & 0x0f; 1668 if (!chip->playback_streams && !chip->capture_streams) { 1669 /* gcap didn't give any info, switching to old method */ 1670 1671 switch (chip->driver_type) { 1672 case AZX_DRIVER_ULI: 1673 chip->playback_streams = ULI_NUM_PLAYBACK; 1674 chip->capture_streams = ULI_NUM_CAPTURE; 1675 break; 1676 case AZX_DRIVER_ATIHDMI: 1677 case AZX_DRIVER_ATIHDMI_NS: 1678 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1679 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1680 break; 1681 case AZX_DRIVER_GENERIC: 1682 default: 1683 chip->playback_streams = ICH6_NUM_PLAYBACK; 1684 chip->capture_streams = ICH6_NUM_CAPTURE; 1685 break; 1686 } 1687 } 1688 chip->capture_index_offset = 0; 1689 chip->playback_index_offset = chip->capture_streams; 1690 chip->num_streams = chip->playback_streams + chip->capture_streams; 1691 1692 /* initialize streams */ 1693 err = azx_init_streams(chip); 1694 if (err < 0) 1695 return err; 1696 1697 err = azx_alloc_stream_pages(chip); 1698 if (err < 0) 1699 return err; 1700 1701 /* initialize chip */ 1702 azx_init_pci(chip); 1703 1704 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1705 struct hda_intel *hda; 1706 1707 hda = container_of(chip, struct hda_intel, chip); 1708 haswell_set_bclk(hda); 1709 } 1710 1711 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 1712 1713 /* codec detection */ 1714 if (!azx_bus(chip)->codec_mask) { 1715 dev_err(card->dev, "no codecs found!\n"); 1716 return -ENODEV; 1717 } 1718 1719 strcpy(card->driver, "HDA-Intel"); 1720 strlcpy(card->shortname, driver_short_names[chip->driver_type], 1721 sizeof(card->shortname)); 1722 snprintf(card->longname, sizeof(card->longname), 1723 "%s at 0x%lx irq %i", 1724 card->shortname, bus->addr, bus->irq); 1725 1726 return 0; 1727 } 1728 1729 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1730 /* callback from request_firmware_nowait() */ 1731 static void azx_firmware_cb(const struct firmware *fw, void *context) 1732 { 1733 struct snd_card *card = context; 1734 struct azx *chip = card->private_data; 1735 struct pci_dev *pci = chip->pci; 1736 1737 if (!fw) { 1738 dev_err(card->dev, "Cannot load firmware, aborting\n"); 1739 goto error; 1740 } 1741 1742 chip->fw = fw; 1743 if (!chip->disabled) { 1744 /* continue probing */ 1745 if (azx_probe_continue(chip)) 1746 goto error; 1747 } 1748 return; /* OK */ 1749 1750 error: 1751 snd_card_free(card); 1752 pci_set_drvdata(pci, NULL); 1753 } 1754 #endif 1755 1756 /* 1757 * HDA controller ops. 1758 */ 1759 1760 /* PCI register access. */ 1761 static void pci_azx_writel(u32 value, u32 __iomem *addr) 1762 { 1763 writel(value, addr); 1764 } 1765 1766 static u32 pci_azx_readl(u32 __iomem *addr) 1767 { 1768 return readl(addr); 1769 } 1770 1771 static void pci_azx_writew(u16 value, u16 __iomem *addr) 1772 { 1773 writew(value, addr); 1774 } 1775 1776 static u16 pci_azx_readw(u16 __iomem *addr) 1777 { 1778 return readw(addr); 1779 } 1780 1781 static void pci_azx_writeb(u8 value, u8 __iomem *addr) 1782 { 1783 writeb(value, addr); 1784 } 1785 1786 static u8 pci_azx_readb(u8 __iomem *addr) 1787 { 1788 return readb(addr); 1789 } 1790 1791 static int disable_msi_reset_irq(struct azx *chip) 1792 { 1793 struct hdac_bus *bus = azx_bus(chip); 1794 int err; 1795 1796 free_irq(bus->irq, chip); 1797 bus->irq = -1; 1798 pci_disable_msi(chip->pci); 1799 chip->msi = 0; 1800 err = azx_acquire_irq(chip, 1); 1801 if (err < 0) 1802 return err; 1803 1804 return 0; 1805 } 1806 1807 /* DMA page allocation helpers. */ 1808 static int dma_alloc_pages(struct hdac_bus *bus, 1809 int type, 1810 size_t size, 1811 struct snd_dma_buffer *buf) 1812 { 1813 struct azx *chip = bus_to_azx(bus); 1814 int err; 1815 1816 err = snd_dma_alloc_pages(type, 1817 bus->dev, 1818 size, buf); 1819 if (err < 0) 1820 return err; 1821 mark_pages_wc(chip, buf, true); 1822 return 0; 1823 } 1824 1825 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf) 1826 { 1827 struct azx *chip = bus_to_azx(bus); 1828 1829 mark_pages_wc(chip, buf, false); 1830 snd_dma_free_pages(buf); 1831 } 1832 1833 static int substream_alloc_pages(struct azx *chip, 1834 struct snd_pcm_substream *substream, 1835 size_t size) 1836 { 1837 struct azx_dev *azx_dev = get_azx_dev(substream); 1838 int ret; 1839 1840 mark_runtime_wc(chip, azx_dev, substream, false); 1841 ret = snd_pcm_lib_malloc_pages(substream, size); 1842 if (ret < 0) 1843 return ret; 1844 mark_runtime_wc(chip, azx_dev, substream, true); 1845 return 0; 1846 } 1847 1848 static int substream_free_pages(struct azx *chip, 1849 struct snd_pcm_substream *substream) 1850 { 1851 struct azx_dev *azx_dev = get_azx_dev(substream); 1852 mark_runtime_wc(chip, azx_dev, substream, false); 1853 return snd_pcm_lib_free_pages(substream); 1854 } 1855 1856 static void pcm_mmap_prepare(struct snd_pcm_substream *substream, 1857 struct vm_area_struct *area) 1858 { 1859 #ifdef CONFIG_X86 1860 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1861 struct azx *chip = apcm->chip; 1862 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA) 1863 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); 1864 #endif 1865 } 1866 1867 static const struct hdac_io_ops pci_hda_io_ops = { 1868 .reg_writel = pci_azx_writel, 1869 .reg_readl = pci_azx_readl, 1870 .reg_writew = pci_azx_writew, 1871 .reg_readw = pci_azx_readw, 1872 .reg_writeb = pci_azx_writeb, 1873 .reg_readb = pci_azx_readb, 1874 .dma_alloc_pages = dma_alloc_pages, 1875 .dma_free_pages = dma_free_pages, 1876 }; 1877 1878 static const struct hda_controller_ops pci_hda_ops = { 1879 .disable_msi_reset_irq = disable_msi_reset_irq, 1880 .substream_alloc_pages = substream_alloc_pages, 1881 .substream_free_pages = substream_free_pages, 1882 .pcm_mmap_prepare = pcm_mmap_prepare, 1883 .position_check = azx_position_check, 1884 .link_power = azx_intel_link_power, 1885 }; 1886 1887 static int azx_probe(struct pci_dev *pci, 1888 const struct pci_device_id *pci_id) 1889 { 1890 static int dev; 1891 struct snd_card *card; 1892 struct hda_intel *hda; 1893 struct azx *chip; 1894 bool schedule_probe; 1895 int err; 1896 1897 if (dev >= SNDRV_CARDS) 1898 return -ENODEV; 1899 if (!enable[dev]) { 1900 dev++; 1901 return -ENOENT; 1902 } 1903 1904 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 1905 0, &card); 1906 if (err < 0) { 1907 dev_err(&pci->dev, "Error creating card!\n"); 1908 return err; 1909 } 1910 1911 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 1912 if (err < 0) 1913 goto out_free; 1914 card->private_data = chip; 1915 hda = container_of(chip, struct hda_intel, chip); 1916 1917 pci_set_drvdata(pci, card); 1918 1919 err = register_vga_switcheroo(chip); 1920 if (err < 0) { 1921 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 1922 goto out_free; 1923 } 1924 1925 if (check_hdmi_disabled(pci)) { 1926 dev_info(card->dev, "VGA controller is disabled\n"); 1927 dev_info(card->dev, "Delaying initialization\n"); 1928 chip->disabled = true; 1929 } 1930 1931 schedule_probe = !chip->disabled; 1932 1933 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1934 if (patch[dev] && *patch[dev]) { 1935 dev_info(card->dev, "Applying patch firmware '%s'\n", 1936 patch[dev]); 1937 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 1938 &pci->dev, GFP_KERNEL, card, 1939 azx_firmware_cb); 1940 if (err < 0) 1941 goto out_free; 1942 schedule_probe = false; /* continued in azx_firmware_cb() */ 1943 } 1944 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 1945 1946 #ifndef CONFIG_SND_HDA_I915 1947 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 1948 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n"); 1949 #endif 1950 1951 if (schedule_probe) 1952 schedule_work(&hda->probe_work); 1953 1954 dev++; 1955 if (chip->disabled) 1956 complete_all(&hda->probe_wait); 1957 return 0; 1958 1959 out_free: 1960 snd_card_free(card); 1961 return err; 1962 } 1963 1964 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 1965 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 1966 [AZX_DRIVER_NVIDIA] = 8, 1967 [AZX_DRIVER_TERA] = 1, 1968 }; 1969 1970 static int azx_probe_continue(struct azx *chip) 1971 { 1972 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1973 struct hdac_bus *bus = azx_bus(chip); 1974 struct pci_dev *pci = chip->pci; 1975 int dev = chip->dev_index; 1976 int err; 1977 1978 hda->probe_continued = 1; 1979 1980 /* Request display power well for the HDA controller or codec. For 1981 * Haswell/Broadwell, both the display HDA controller and codec need 1982 * this power. For other platforms, like Baytrail/Braswell, only the 1983 * display codec needs the power and it can be released after probe. 1984 */ 1985 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1986 /* HSW/BDW controllers need this power */ 1987 if (CONTROLLER_IN_GPU(pci)) 1988 hda->need_i915_power = 1; 1989 1990 err = snd_hdac_i915_init(bus); 1991 if (err < 0) { 1992 /* if the controller is bound only with HDMI/DP 1993 * (for HSW and BDW), we need to abort the probe; 1994 * for other chips, still continue probing as other 1995 * codecs can be on the same link. 1996 */ 1997 if (CONTROLLER_IN_GPU(pci)) 1998 goto out_free; 1999 else 2000 goto skip_i915; 2001 } 2002 2003 err = snd_hdac_display_power(bus, true); 2004 if (err < 0) { 2005 dev_err(chip->card->dev, 2006 "Cannot turn on display power on i915\n"); 2007 goto i915_power_fail; 2008 } 2009 } 2010 2011 skip_i915: 2012 err = azx_first_init(chip); 2013 if (err < 0) 2014 goto out_free; 2015 2016 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2017 chip->beep_mode = beep_mode[dev]; 2018 #endif 2019 2020 /* create codec instances */ 2021 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2022 if (err < 0) 2023 goto out_free; 2024 2025 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2026 if (chip->fw) { 2027 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2028 chip->fw->data); 2029 if (err < 0) 2030 goto out_free; 2031 #ifndef CONFIG_PM 2032 release_firmware(chip->fw); /* no longer needed */ 2033 chip->fw = NULL; 2034 #endif 2035 } 2036 #endif 2037 if ((probe_only[dev] & 1) == 0) { 2038 err = azx_codec_configure(chip); 2039 if (err < 0) 2040 goto out_free; 2041 } 2042 2043 err = snd_card_register(chip->card); 2044 if (err < 0) 2045 goto out_free; 2046 2047 chip->running = 1; 2048 azx_add_card_list(chip); 2049 snd_hda_set_power_save(&chip->bus, power_save * 1000); 2050 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo) 2051 pm_runtime_put_noidle(&pci->dev); 2052 2053 out_free: 2054 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL 2055 && !hda->need_i915_power) 2056 snd_hdac_display_power(bus, false); 2057 2058 i915_power_fail: 2059 if (err < 0) 2060 hda->init_failed = 1; 2061 complete_all(&hda->probe_wait); 2062 return err; 2063 } 2064 2065 static void azx_remove(struct pci_dev *pci) 2066 { 2067 struct snd_card *card = pci_get_drvdata(pci); 2068 2069 if (card) 2070 snd_card_free(card); 2071 } 2072 2073 static void azx_shutdown(struct pci_dev *pci) 2074 { 2075 struct snd_card *card = pci_get_drvdata(pci); 2076 struct azx *chip; 2077 2078 if (!card) 2079 return; 2080 chip = card->private_data; 2081 if (chip && chip->running) 2082 azx_stop_chip(chip); 2083 } 2084 2085 /* PCI IDs */ 2086 static const struct pci_device_id azx_ids[] = { 2087 /* CPT */ 2088 { PCI_DEVICE(0x8086, 0x1c20), 2089 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2090 /* PBG */ 2091 { PCI_DEVICE(0x8086, 0x1d20), 2092 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2093 /* Panther Point */ 2094 { PCI_DEVICE(0x8086, 0x1e20), 2095 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2096 /* Lynx Point */ 2097 { PCI_DEVICE(0x8086, 0x8c20), 2098 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2099 /* 9 Series */ 2100 { PCI_DEVICE(0x8086, 0x8ca0), 2101 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2102 /* Wellsburg */ 2103 { PCI_DEVICE(0x8086, 0x8d20), 2104 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2105 { PCI_DEVICE(0x8086, 0x8d21), 2106 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2107 /* Lewisburg */ 2108 { PCI_DEVICE(0x8086, 0xa1f0), 2109 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2110 { PCI_DEVICE(0x8086, 0xa270), 2111 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2112 /* Lynx Point-LP */ 2113 { PCI_DEVICE(0x8086, 0x9c20), 2114 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2115 /* Lynx Point-LP */ 2116 { PCI_DEVICE(0x8086, 0x9c21), 2117 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2118 /* Wildcat Point-LP */ 2119 { PCI_DEVICE(0x8086, 0x9ca0), 2120 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2121 /* Sunrise Point */ 2122 { PCI_DEVICE(0x8086, 0xa170), 2123 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2124 /* Sunrise Point-LP */ 2125 { PCI_DEVICE(0x8086, 0x9d70), 2126 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2127 /* Haswell */ 2128 { PCI_DEVICE(0x8086, 0x0a0c), 2129 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2130 { PCI_DEVICE(0x8086, 0x0c0c), 2131 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2132 { PCI_DEVICE(0x8086, 0x0d0c), 2133 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2134 /* Broadwell */ 2135 { PCI_DEVICE(0x8086, 0x160c), 2136 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 2137 /* 5 Series/3400 */ 2138 { PCI_DEVICE(0x8086, 0x3b56), 2139 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2140 /* Poulsbo */ 2141 { PCI_DEVICE(0x8086, 0x811b), 2142 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2143 /* Oaktrail */ 2144 { PCI_DEVICE(0x8086, 0x080a), 2145 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2146 /* BayTrail */ 2147 { PCI_DEVICE(0x8086, 0x0f04), 2148 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL }, 2149 /* Braswell */ 2150 { PCI_DEVICE(0x8086, 0x2284), 2151 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL }, 2152 /* ICH6 */ 2153 { PCI_DEVICE(0x8086, 0x2668), 2154 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2155 /* ICH7 */ 2156 { PCI_DEVICE(0x8086, 0x27d8), 2157 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2158 /* ESB2 */ 2159 { PCI_DEVICE(0x8086, 0x269a), 2160 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2161 /* ICH8 */ 2162 { PCI_DEVICE(0x8086, 0x284b), 2163 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2164 /* ICH9 */ 2165 { PCI_DEVICE(0x8086, 0x293e), 2166 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2167 /* ICH9 */ 2168 { PCI_DEVICE(0x8086, 0x293f), 2169 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2170 /* ICH10 */ 2171 { PCI_DEVICE(0x8086, 0x3a3e), 2172 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2173 /* ICH10 */ 2174 { PCI_DEVICE(0x8086, 0x3a6e), 2175 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2176 /* Generic Intel */ 2177 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2178 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2179 .class_mask = 0xffffff, 2180 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2181 /* ATI SB 450/600/700/800/900 */ 2182 { PCI_DEVICE(0x1002, 0x437b), 2183 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2184 { PCI_DEVICE(0x1002, 0x4383), 2185 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2186 /* AMD Hudson */ 2187 { PCI_DEVICE(0x1022, 0x780d), 2188 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2189 /* ATI HDMI */ 2190 { PCI_DEVICE(0x1002, 0x1308), 2191 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2192 { PCI_DEVICE(0x1002, 0x157a), 2193 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2194 { PCI_DEVICE(0x1002, 0x793b), 2195 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2196 { PCI_DEVICE(0x1002, 0x7919), 2197 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2198 { PCI_DEVICE(0x1002, 0x960f), 2199 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2200 { PCI_DEVICE(0x1002, 0x970f), 2201 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2202 { PCI_DEVICE(0x1002, 0x9840), 2203 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2204 { PCI_DEVICE(0x1002, 0xaa00), 2205 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2206 { PCI_DEVICE(0x1002, 0xaa08), 2207 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2208 { PCI_DEVICE(0x1002, 0xaa10), 2209 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2210 { PCI_DEVICE(0x1002, 0xaa18), 2211 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2212 { PCI_DEVICE(0x1002, 0xaa20), 2213 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2214 { PCI_DEVICE(0x1002, 0xaa28), 2215 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2216 { PCI_DEVICE(0x1002, 0xaa30), 2217 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2218 { PCI_DEVICE(0x1002, 0xaa38), 2219 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2220 { PCI_DEVICE(0x1002, 0xaa40), 2221 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2222 { PCI_DEVICE(0x1002, 0xaa48), 2223 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2224 { PCI_DEVICE(0x1002, 0xaa50), 2225 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2226 { PCI_DEVICE(0x1002, 0xaa58), 2227 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2228 { PCI_DEVICE(0x1002, 0xaa60), 2229 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2230 { PCI_DEVICE(0x1002, 0xaa68), 2231 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2232 { PCI_DEVICE(0x1002, 0xaa80), 2233 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2234 { PCI_DEVICE(0x1002, 0xaa88), 2235 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2236 { PCI_DEVICE(0x1002, 0xaa90), 2237 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2238 { PCI_DEVICE(0x1002, 0xaa98), 2239 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2240 { PCI_DEVICE(0x1002, 0x9902), 2241 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2242 { PCI_DEVICE(0x1002, 0xaaa0), 2243 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2244 { PCI_DEVICE(0x1002, 0xaaa8), 2245 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2246 { PCI_DEVICE(0x1002, 0xaab0), 2247 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2248 { PCI_DEVICE(0x1002, 0xaac0), 2249 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2250 { PCI_DEVICE(0x1002, 0xaac8), 2251 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2252 { PCI_DEVICE(0x1002, 0xaad8), 2253 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2254 { PCI_DEVICE(0x1002, 0xaae8), 2255 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2256 /* VIA VT8251/VT8237A */ 2257 { PCI_DEVICE(0x1106, 0x3288), 2258 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA }, 2259 /* VIA GFX VT7122/VX900 */ 2260 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2261 /* VIA GFX VT6122/VX11 */ 2262 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2263 /* SIS966 */ 2264 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2265 /* ULI M5461 */ 2266 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2267 /* NVIDIA MCP */ 2268 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2269 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2270 .class_mask = 0xffffff, 2271 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2272 /* Teradici */ 2273 { PCI_DEVICE(0x6549, 0x1200), 2274 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2275 { PCI_DEVICE(0x6549, 0x2200), 2276 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2277 /* Creative X-Fi (CA0110-IBG) */ 2278 /* CTHDA chips */ 2279 { PCI_DEVICE(0x1102, 0x0010), 2280 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2281 { PCI_DEVICE(0x1102, 0x0012), 2282 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2283 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2284 /* the following entry conflicts with snd-ctxfi driver, 2285 * as ctxfi driver mutates from HD-audio to native mode with 2286 * a special command sequence. 2287 */ 2288 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2289 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2290 .class_mask = 0xffffff, 2291 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2292 AZX_DCAPS_NO_64BIT | 2293 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, 2294 #else 2295 /* this entry seems still valid -- i.e. without emu20kx chip */ 2296 { PCI_DEVICE(0x1102, 0x0009), 2297 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2298 AZX_DCAPS_NO_64BIT | 2299 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, 2300 #endif 2301 /* CM8888 */ 2302 { PCI_DEVICE(0x13f6, 0x5011), 2303 .driver_data = AZX_DRIVER_CMEDIA | 2304 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2305 /* Vortex86MX */ 2306 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2307 /* VMware HDAudio */ 2308 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2309 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2310 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2311 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2312 .class_mask = 0xffffff, 2313 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2314 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2315 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2316 .class_mask = 0xffffff, 2317 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2318 { 0, } 2319 }; 2320 MODULE_DEVICE_TABLE(pci, azx_ids); 2321 2322 /* pci_driver definition */ 2323 static struct pci_driver azx_driver = { 2324 .name = KBUILD_MODNAME, 2325 .id_table = azx_ids, 2326 .probe = azx_probe, 2327 .remove = azx_remove, 2328 .shutdown = azx_shutdown, 2329 .driver = { 2330 .pm = AZX_PM_OPS, 2331 }, 2332 }; 2333 2334 module_pci_driver(azx_driver); 2335